2 * This file implements the IR transformation from firm into
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
26 #include "../benode_t.h"
27 #include "../besched.h"
29 #include "bearch_ia32_t.h"
31 #include "ia32_nodes_attr.h"
32 #include "../arch/archop.h" /* we need this for Min and Max nodes */
33 #include "ia32_transform.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
37 #include "gen_ia32_regalloc_if.h"
40 #define SET_IA32_ORIG_NODE(n, o)
42 #define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
46 #define SFP_SIGN "0x80000000"
47 #define DFP_SIGN "0x8000000000000000"
48 #define SFP_ABS "0x7FFFFFFF"
49 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
51 #define TP_SFP_SIGN "ia32_sfp_sign"
52 #define TP_DFP_SIGN "ia32_dfp_sign"
53 #define TP_SFP_ABS "ia32_sfp_abs"
54 #define TP_DFP_ABS "ia32_dfp_abs"
56 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
57 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
58 #define ENT_SFP_ABS "IA32_SFP_ABS"
59 #define ENT_DFP_ABS "IA32_DFP_ABS"
61 extern ir_op *get_op_Mulh(void);
63 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
64 ir_node *op1, ir_node *op2, ir_node *mem, ir_mode *mode);
66 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
67 ir_node *op, ir_node *mem, ir_mode *mode);
70 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
73 /****************************************************************************************************
75 * | | | | / _| | | (_)
76 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
77 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
78 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
79 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
81 ****************************************************************************************************/
84 * Gets the Proj with number pn from irn.
86 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
87 const ir_edge_t *edge;
89 assert(get_irn_mode(irn) == mode_T && "need mode_T");
91 foreach_out_edge(irn, edge) {
92 proj = get_edge_src_irn(edge);
94 if (get_Proj_proj(proj) == pn)
101 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
102 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
103 static const struct {
105 const char *ent_name;
106 const char *cnst_str;
107 } names [ia32_known_const_max] = {
108 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
109 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
110 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
111 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
113 static struct entity *ent_cache[ia32_known_const_max];
115 const char *tp_name, *ent_name, *cnst_str;
122 ent_name = names[kct].ent_name;
123 if (! ent_cache[kct]) {
124 tp_name = names[kct].tp_name;
125 cnst_str = names[kct].cnst_str;
127 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
128 tp = new_type_primitive(new_id_from_str(tp_name), mode);
129 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
131 set_entity_ld_ident(ent, get_entity_ident(ent));
132 set_entity_visibility(ent, visibility_local);
133 set_entity_variability(ent, variability_constant);
134 set_entity_allocation(ent, allocation_static);
136 /* we create a new entity here: It's initialization must resist on the
138 rem = current_ir_graph;
139 current_ir_graph = get_const_code_irg();
140 cnst = new_Const(mode, tv);
141 current_ir_graph = rem;
143 set_atomic_ent_value(ent, cnst);
145 /* cache the entry */
146 ent_cache[kct] = ent;
149 return get_entity_ident(ent_cache[kct]);
154 * Prints the old node name on cg obst and returns a pointer to it.
156 const char *get_old_node_name(ia32_transform_env_t *env) {
157 ia32_isa_t *isa = (ia32_isa_t *)env->cg->arch_env->isa;
159 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", env->irn);
160 obstack_1grow(isa->name_obst, 0);
161 isa->name_obst_size += obstack_object_size(isa->name_obst);
162 return obstack_finish(isa->name_obst);
166 /* determine if one operator is an Imm */
167 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
169 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
170 else return is_ia32_Cnst(op2) ? op2 : NULL;
173 /* determine if one operator is not an Imm */
174 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
175 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
180 * Construct a standard binary operation, set AM and immediate if required.
182 * @param env The transformation environment
183 * @param op1 The first operand
184 * @param op2 The second operand
185 * @param func The node constructor function
186 * @return The constructed ia32 node.
188 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
189 ir_node *new_op = NULL;
190 ir_mode *mode = env->mode;
191 dbg_info *dbg = env->dbg;
192 ir_graph *irg = env->irg;
193 ir_node *block = env->block;
194 firm_dbg_module_t *mod = env->mod;
195 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
196 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
197 ir_node *nomem = new_NoMem();
198 ir_node *expr_op, *imm_op;
200 /* Check if immediate optimization is on and */
201 /* if it's an operation with immediate. */
202 if (! env->cg->opt.immops) {
206 else if (is_op_commutative(get_irn_op(env->irn))) {
207 imm_op = get_immediate_op(op1, op2);
208 expr_op = get_expr_op(op1, op2);
211 imm_op = get_immediate_op(NULL, op2);
212 expr_op = get_expr_op(op1, op2);
215 assert((expr_op || imm_op) && "invalid operands");
218 /* We have two consts here: not yet supported */
222 if (mode_is_float(mode)) {
223 /* floating point operations */
225 DB((mod, LEVEL_1, "FP with immediate ..."));
226 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem, mode_T);
227 set_ia32_Immop_attr(new_op, imm_op);
228 set_ia32_am_support(new_op, ia32_am_None);
231 DB((mod, LEVEL_1, "FP binop ..."));
232 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
233 set_ia32_am_support(new_op, ia32_am_Source);
237 /* integer operations */
239 /* This is expr + const */
240 DB((mod, LEVEL_1, "INT with immediate ..."));
241 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem, mode_T);
242 set_ia32_Immop_attr(new_op, imm_op);
245 set_ia32_am_support(new_op, ia32_am_Dest);
248 DB((mod, LEVEL_1, "INT binop ..."));
249 /* This is a normal operation */
250 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
253 set_ia32_am_support(new_op, ia32_am_Full);
257 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
259 set_ia32_res_mode(new_op, mode);
261 if (is_op_commutative(get_irn_op(env->irn))) {
262 set_ia32_commutative(new_op);
265 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
271 * Construct a shift/rotate binary operation, sets AM and immediate if required.
273 * @param env The transformation environment
274 * @param op1 The first operand
275 * @param op2 The second operand
276 * @param func The node constructor function
277 * @return The constructed ia32 node.
279 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
280 ir_node *new_op = NULL;
281 ir_mode *mode = env->mode;
282 dbg_info *dbg = env->dbg;
283 ir_graph *irg = env->irg;
284 ir_node *block = env->block;
285 firm_dbg_module_t *mod = env->mod;
286 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
287 ir_node *nomem = new_NoMem();
288 ir_node *expr_op, *imm_op;
291 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
293 /* Check if immediate optimization is on and */
294 /* if it's an operation with immediate. */
295 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
296 expr_op = get_expr_op(op1, op2);
298 assert((expr_op || imm_op) && "invalid operands");
301 /* We have two consts here: not yet supported */
305 /* Limit imm_op within range imm8 */
307 tv = get_ia32_Immop_tarval(imm_op);
310 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
317 /* integer operations */
319 /* This is shift/rot with const */
320 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
322 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
323 set_ia32_Immop_attr(new_op, imm_op);
326 /* This is a normal shift/rot */
327 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
328 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
332 set_ia32_am_support(new_op, ia32_am_Dest);
334 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
336 set_ia32_res_mode(new_op, mode);
338 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
343 * Construct a standard unary operation, set AM and immediate if required.
345 * @param env The transformation environment
346 * @param op The operand
347 * @param func The node constructor function
348 * @return The constructed ia32 node.
350 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
351 ir_node *new_op = NULL;
352 ir_mode *mode = env->mode;
353 dbg_info *dbg = env->dbg;
354 firm_dbg_module_t *mod = env->mod;
355 ir_graph *irg = env->irg;
356 ir_node *block = env->block;
357 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
358 ir_node *nomem = new_NoMem();
360 new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
362 if (mode_is_float(mode)) {
363 DB((mod, LEVEL_1, "FP unop ..."));
364 /* floating point operations don't support implicit store */
365 set_ia32_am_support(new_op, ia32_am_None);
368 DB((mod, LEVEL_1, "INT unop ..."));
369 set_ia32_am_support(new_op, ia32_am_Dest);
372 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
374 set_ia32_res_mode(new_op, mode);
376 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
382 * Creates an ia32 Add with immediate.
384 * @param env The transformation environment
385 * @param expr_op The expression operator
386 * @param const_op The constant
387 * @return the created ia32 Add node
389 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
390 ir_node *new_op = NULL;
391 tarval *tv = get_ia32_Immop_tarval(const_op);
392 firm_dbg_module_t *mod = env->mod;
393 dbg_info *dbg = env->dbg;
394 ir_graph *irg = env->irg;
395 ir_node *block = env->block;
396 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
397 ir_node *nomem = new_NoMem();
399 tarval_classification_t class_tv, class_negtv;
401 /* try to optimize to inc/dec */
402 if (env->cg->opt.incdec && tv) {
403 /* optimize tarvals */
404 class_tv = classify_tarval(tv);
405 class_negtv = classify_tarval(tarval_neg(tv));
407 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
408 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
409 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
412 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
413 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
414 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
420 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
421 set_ia32_Immop_attr(new_op, const_op);
428 * Creates an ia32 Add.
430 * @param dbg firm node dbg
431 * @param block the block the new node should belong to
432 * @param op1 first operator
433 * @param op2 second operator
434 * @param mode node mode
435 * @return the created ia32 Add node
437 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
438 ir_node *new_op = NULL;
439 dbg_info *dbg = env->dbg;
440 ir_mode *mode = env->mode;
441 ir_graph *irg = env->irg;
442 ir_node *block = env->block;
443 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
444 ir_node *nomem = new_NoMem();
445 ir_node *expr_op, *imm_op;
447 /* Check if immediate optimization is on and */
448 /* if it's an operation with immediate. */
449 imm_op = env->cg->opt.immops ? get_immediate_op(op1, op2) : NULL;
450 expr_op = get_expr_op(op1, op2);
452 assert((expr_op || imm_op) && "invalid operands");
454 if (mode_is_float(mode)) {
455 if (USE_SSE2(env->cg))
456 return gen_binop(env, op1, op2, new_rd_ia32_fAdd);
458 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
464 /* No expr_op means, that we have two const - one symconst and */
465 /* one tarval or another symconst - because this case is not */
466 /* covered by constant folding */
468 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
469 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
470 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
473 set_ia32_am_support(new_op, ia32_am_Source);
474 set_ia32_op_type(new_op, ia32_AddrModeS);
475 set_ia32_am_flavour(new_op, ia32_am_O);
477 /* Lea doesn't need a Proj */
481 /* This is expr + const */
482 new_op = gen_imm_Add(env, expr_op, imm_op);
485 set_ia32_am_support(new_op, ia32_am_Dest);
488 /* This is a normal add */
489 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
492 set_ia32_am_support(new_op, ia32_am_Full);
496 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
498 set_ia32_res_mode(new_op, mode);
500 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
506 * Creates an ia32 Mul.
508 * @param dbg firm node dbg
509 * @param block the block the new node should belong to
510 * @param op1 first operator
511 * @param op2 second operator
512 * @param mode node mode
513 * @return the created ia32 Mul node
515 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
518 if (mode_is_float(env->mode)) {
519 if (USE_SSE2(env->cg))
520 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul);
522 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
525 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
534 * Creates an ia32 Mulh.
535 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
536 * this result while Mul returns the lower 32 bit.
538 * @param env The transformation environment
539 * @param op1 The first operator
540 * @param op2 The second operator
541 * @return the created ia32 Mulh node
543 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
544 ir_node *proj_EAX, *proj_EDX, *mulh;
547 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
548 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
549 mulh = get_Proj_pred(proj_EAX);
550 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
552 /* to be on the save side */
553 set_Proj_proj(proj_EAX, pn_EAX);
555 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
556 /* Mulh with const cannot have AM */
557 set_ia32_am_support(mulh, ia32_am_None);
560 /* Mulh cannot have AM for destination */
561 set_ia32_am_support(mulh, ia32_am_Source);
567 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
575 * Creates an ia32 And.
577 * @param env The transformation environment
578 * @param op1 The first operator
579 * @param op2 The second operator
580 * @return The created ia32 And node
582 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
583 assert (! mode_is_float(env->mode));
584 return gen_binop(env, op1, op2, new_rd_ia32_And);
590 * Creates an ia32 Or.
592 * @param env The transformation environment
593 * @param op1 The first operator
594 * @param op2 The second operator
595 * @return The created ia32 Or node
597 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
598 assert (! mode_is_float(env->mode));
599 return gen_binop(env, op1, op2, new_rd_ia32_Or);
605 * Creates an ia32 Eor.
607 * @param env The transformation environment
608 * @param op1 The first operator
609 * @param op2 The second operator
610 * @return The created ia32 Eor node
612 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
613 assert(! mode_is_float(env->mode));
614 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
620 * Creates an ia32 Max.
622 * @param env The transformation environment
623 * @param op1 The first operator
624 * @param op2 The second operator
625 * @return the created ia32 Max node
627 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
630 if (mode_is_float(env->mode)) {
631 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
634 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
635 set_ia32_am_support(new_op, ia32_am_None);
636 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
645 * Creates an ia32 Min.
647 * @param env The transformation environment
648 * @param op1 The first operator
649 * @param op2 The second operator
650 * @return the created ia32 Min node
652 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
655 if (mode_is_float(env->mode)) {
656 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
659 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
660 set_ia32_am_support(new_op, ia32_am_None);
661 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
670 * Creates an ia32 Sub with immediate.
672 * @param env The transformation environment
673 * @param op1 The first operator
674 * @param op2 The second operator
675 * @return The created ia32 Sub node
677 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
678 ir_node *new_op = NULL;
679 tarval *tv = get_ia32_Immop_tarval(const_op);
680 firm_dbg_module_t *mod = env->mod;
681 dbg_info *dbg = env->dbg;
682 ir_graph *irg = env->irg;
683 ir_node *block = env->block;
684 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
685 ir_node *nomem = new_NoMem();
687 tarval_classification_t class_tv, class_negtv;
689 /* try to optimize to inc/dec */
690 if (env->cg->opt.incdec && tv) {
691 /* optimize tarvals */
692 class_tv = classify_tarval(tv);
693 class_negtv = classify_tarval(tarval_neg(tv));
695 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
696 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
697 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
700 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
701 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
702 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
708 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
709 set_ia32_Immop_attr(new_op, const_op);
716 * Creates an ia32 Sub.
718 * @param env The transformation environment
719 * @param op1 The first operator
720 * @param op2 The second operator
721 * @return The created ia32 Sub node
723 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
724 ir_node *new_op = NULL;
725 dbg_info *dbg = env->dbg;
726 ir_mode *mode = env->mode;
727 ir_graph *irg = env->irg;
728 ir_node *block = env->block;
729 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
730 ir_node *nomem = new_NoMem();
731 ir_node *expr_op, *imm_op;
733 /* Check if immediate optimization is on and */
734 /* if it's an operation with immediate. */
735 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
736 expr_op = get_expr_op(op1, op2);
738 assert((expr_op || imm_op) && "invalid operands");
740 if (mode_is_float(mode)) {
741 if (USE_SSE2(env->cg))
742 return gen_binop(env, op1, op2, new_rd_ia32_fSub);
744 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
749 /* No expr_op means, that we have two const - one symconst and */
750 /* one tarval or another symconst - because this case is not */
751 /* covered by constant folding */
753 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
754 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
755 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
758 set_ia32_am_support(new_op, ia32_am_Source);
759 set_ia32_op_type(new_op, ia32_AddrModeS);
760 set_ia32_am_flavour(new_op, ia32_am_O);
762 /* Lea doesn't need a Proj */
766 /* This is expr - const */
767 new_op = gen_imm_Sub(env, expr_op, imm_op);
770 set_ia32_am_support(new_op, ia32_am_Dest);
773 /* This is a normal sub */
774 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
777 set_ia32_am_support(new_op, ia32_am_Full);
781 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
783 set_ia32_res_mode(new_op, mode);
785 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
791 * Generates an ia32 DivMod with additional infrastructure for the
792 * register allocator if needed.
794 * @param env The transformation environment
795 * @param dividend -no comment- :)
796 * @param divisor -no comment- :)
797 * @param dm_flav flavour_Div/Mod/DivMod
798 * @return The created ia32 DivMod node
800 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
802 ir_node *edx_node, *cltd;
804 dbg_info *dbg = env->dbg;
805 ir_graph *irg = env->irg;
806 ir_node *block = env->block;
807 ir_mode *mode = env->mode;
808 ir_node *irn = env->irn;
813 mem = get_Div_mem(irn);
814 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
817 mem = get_Mod_mem(irn);
818 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
821 mem = get_DivMod_mem(irn);
822 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
828 if (mode_is_signed(mode)) {
829 /* in signed mode, we need to sign extend the dividend */
830 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend, mode_T);
831 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EAX);
832 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EDX);
835 edx_node = new_rd_ia32_Const(dbg, irg, block, mode_Iu);
836 set_ia32_Const_type(edx_node, ia32_Const);
837 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
840 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode_T);
842 set_ia32_flavour(res, dm_flav);
843 set_ia32_n_res(res, 2);
845 /* Only one proj is used -> We must add a second proj and */
846 /* connect this one to a Keep node to eat up the second */
847 /* destroyed register. */
848 if (get_irn_n_edges(irn) == 1) {
849 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
850 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
852 if (get_Proj_proj(proj) == pn_DivMod_res_div) {
853 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
856 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
859 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
862 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
864 set_ia32_res_mode(res, mode_Is);
871 * Wrapper for generate_DivMod. Sets flavour_Mod.
873 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
874 return generate_DivMod(env, op1, op2, flavour_Mod);
880 * Wrapper for generate_DivMod. Sets flavour_Div.
882 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
883 return generate_DivMod(env, op1, op2, flavour_Div);
889 * Wrapper for generate_DivMod. Sets flavour_DivMod.
891 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
892 return generate_DivMod(env, op1, op2, flavour_DivMod);
898 * Creates an ia32 floating Div.
900 * @param env The transformation environment
901 * @param op1 The first operator
902 * @param op2 The second operator
903 * @return The created ia32 fDiv node
905 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
906 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
908 ir_node *nomem = new_rd_NoMem(env->irg);
910 if (USE_SSE2(env->cg)) {
912 if (is_ia32_fConst(op2)) {
913 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem, mode_T);
914 set_ia32_am_support(new_op, ia32_am_None);
915 set_ia32_Immop_attr(new_op, op2);
918 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T);
919 set_ia32_am_support(new_op, ia32_am_Source);
923 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T);
924 set_ia32_am_support(new_op, ia32_am_Source);
926 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
927 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
935 * Creates an ia32 Shl.
937 * @param env The transformation environment
938 * @param op1 The first operator
939 * @param op2 The second operator
940 * @return The created ia32 Shl node
942 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
943 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shl);
949 * Creates an ia32 Shr.
951 * @param env The transformation environment
952 * @param op1 The first operator
953 * @param op2 The second operator
954 * @return The created ia32 Shr node
956 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
957 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shr);
963 * Creates an ia32 Shrs.
965 * @param env The transformation environment
966 * @param op1 The first operator
967 * @param op2 The second operator
968 * @return The created ia32 Shrs node
970 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
971 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shrs);
977 * Creates an ia32 RotL.
979 * @param env The transformation environment
980 * @param op1 The first operator
981 * @param op2 The second operator
982 * @return The created ia32 RotL node
984 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
985 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
991 * Creates an ia32 RotR.
992 * NOTE: There is no RotR with immediate because this would always be a RotL
993 * "imm-mode_size_bits" which can be pre-calculated.
995 * @param env The transformation environment
996 * @param op1 The first operator
997 * @param op2 The second operator
998 * @return The created ia32 RotR node
1000 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1001 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1007 * Creates an ia32 RotR or RotL (depending on the found pattern).
1009 * @param env The transformation environment
1010 * @param op1 The first operator
1011 * @param op2 The second operator
1012 * @return The created ia32 RotL or RotR node
1014 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1015 ir_node *rotate = NULL;
1017 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1018 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1019 that means we can create a RotR instead of an Add and a RotL */
1022 ir_node *pred = get_Proj_pred(op2);
1024 if (is_ia32_Add(pred)) {
1025 ir_node *pred_pred = get_irn_n(pred, 2);
1026 tarval *tv = get_ia32_Immop_tarval(pred);
1027 long bits = get_mode_size_bits(env->mode);
1029 if (is_Proj(pred_pred)) {
1030 pred_pred = get_Proj_pred(pred_pred);
1033 if (is_ia32_Minus(pred_pred) &&
1034 tarval_is_long(tv) &&
1035 get_tarval_long(tv) == bits)
1037 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1038 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1045 rotate = gen_RotL(env, op1, op2);
1054 * Transforms a Minus node.
1056 * @param env The transformation environment
1057 * @param op The operator
1058 * @return The created ia32 Minus node
1060 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
1063 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1064 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1065 ir_node *nomem = new_rd_NoMem(env->irg);
1068 if (mode_is_float(env->mode)) {
1069 if (USE_SSE2(env->cg)) {
1070 new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1072 size = get_mode_size_bits(env->mode);
1073 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1075 set_ia32_sc(new_op, name);
1077 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1079 set_ia32_res_mode(new_op, env->mode);
1080 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1082 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1085 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1086 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1090 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1099 * Transforms a Not node.
1101 * @param env The transformation environment
1102 * @param op The operator
1103 * @return The created ia32 Not node
1105 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) {
1106 assert (! mode_is_float(env->mode));
1107 return gen_unop(env, op, new_rd_ia32_Not);
1113 * Transforms an Abs node.
1115 * @param env The transformation environment
1116 * @param op The operator
1117 * @return The created ia32 Abs node
1119 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
1120 ir_node *res, *p_eax, *p_edx;
1121 dbg_info *dbg = env->dbg;
1122 ir_mode *mode = env->mode;
1123 ir_graph *irg = env->irg;
1124 ir_node *block = env->block;
1125 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1126 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1127 ir_node *nomem = new_NoMem();
1131 if (mode_is_float(mode)) {
1132 if (USE_SSE2(env->cg)) {
1133 res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1135 size = get_mode_size_bits(mode);
1136 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1138 set_ia32_sc(res, name);
1140 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1142 set_ia32_res_mode(res, mode);
1143 set_ia32_immop_type(res, ia32_ImmSymConst);
1145 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1148 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1149 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1153 res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T);
1154 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1155 set_ia32_res_mode(res, mode);
1157 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
1158 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
1160 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T);
1161 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1162 set_ia32_res_mode(res, mode);
1164 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1166 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T);
1167 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1168 set_ia32_res_mode(res, mode);
1170 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1179 * Transforms a Load.
1181 * @param mod the debug module
1182 * @param block the block the new node should belong to
1183 * @param node the ir Load node
1184 * @param mode node mode
1185 * @return the created ia32 Load node
1187 static ir_node *gen_Load(ia32_transform_env_t *env) {
1188 ir_node *node = env->irn;
1189 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1190 ir_node *ptr = get_Load_ptr(node);
1191 ir_mode *mode = get_Load_mode(node);
1192 const char *offs = NULL;
1194 ia32_am_flavour_t am_flav = ia32_B;
1196 /* address might be a constant (symconst or absolute address) */
1197 if (is_ia32_Const(ptr)) {
1198 offs = get_ia32_cnst(ptr);
1202 if (mode_is_float(mode)) {
1203 if (USE_SSE2(env->cg))
1204 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, get_Load_mem(node), env->mode);
1206 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, get_Load_mem(node), env->mode);
1209 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, get_Load_mem(node), env->mode);
1212 /* base is an constant address */
1214 add_ia32_am_offs(new_op, offs);
1218 set_ia32_am_support(new_op, ia32_am_Source);
1219 set_ia32_op_type(new_op, ia32_AddrModeS);
1220 set_ia32_am_flavour(new_op, am_flav);
1221 set_ia32_ls_mode(new_op, mode);
1223 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1231 * Transforms a Store.
1233 * @param mod the debug module
1234 * @param block the block the new node should belong to
1235 * @param node the ir Store node
1236 * @param mode node mode
1237 * @return the created ia32 Store node
1239 static ir_node *gen_Store(ia32_transform_env_t *env) {
1240 ir_node *node = env->irn;
1241 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1242 ir_node *val = get_Store_value(node);
1243 ir_node *ptr = get_Store_ptr(node);
1244 ir_node *mem = get_Store_mem(node);
1245 ir_mode *mode = get_irn_mode(val);
1246 ir_node *sval = val;
1247 const char *offs = NULL;
1249 ia32_am_flavour_t am_flav = ia32_B;
1250 ia32_immop_type_t immop = ia32_ImmNone;
1252 /* in case of storing a const (but not a symconst) -> make it an attribute */
1253 if (is_ia32_Cnst(val)) {
1254 switch (get_ia32_op_type(val)) {
1256 immop = ia32_ImmConst;
1259 immop = ia32_ImmSymConst;
1262 assert(0 && "unsupported Const type");
1267 /* address might be a constant (symconst or absolute address) */
1268 if (is_ia32_Const(ptr)) {
1269 offs = get_ia32_cnst(ptr);
1273 if (mode_is_float(mode)) {
1274 if (USE_SSE2(env->cg))
1275 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1277 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1279 else if (get_mode_size_bits(mode) == 8) {
1280 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1283 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1286 /* stored const is an attribute (saves a register) */
1287 if (is_ia32_Cnst(val)) {
1288 set_ia32_Immop_attr(new_op, val);
1291 /* base is an constant address */
1293 add_ia32_am_offs(new_op, offs);
1297 set_ia32_am_support(new_op, ia32_am_Dest);
1298 set_ia32_op_type(new_op, ia32_AddrModeD);
1299 set_ia32_am_flavour(new_op, am_flav);
1300 set_ia32_ls_mode(new_op, get_irn_mode(val));
1301 set_ia32_immop_type(new_op, immop);
1303 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1311 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1313 * @param env The transformation environment
1314 * @return The transformed node.
1316 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1317 dbg_info *dbg = env->dbg;
1318 ir_graph *irg = env->irg;
1319 ir_node *block = env->block;
1320 ir_node *node = env->irn;
1321 ir_node *sel = get_Cond_selector(node);
1322 ir_mode *sel_mode = get_irn_mode(sel);
1323 ir_node *res = NULL;
1324 ir_node *pred = NULL;
1325 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1326 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1328 if (is_Proj(sel) && sel_mode == mode_b) {
1329 ir_node *nomem = new_NoMem();
1331 pred = get_Proj_pred(sel);
1333 /* get both compare operators */
1334 cmp_a = get_Cmp_left(pred);
1335 cmp_b = get_Cmp_right(pred);
1337 /* check if we can use a CondJmp with immediate */
1338 cnst = env->cg->opt.immops ? get_immediate_op(cmp_a, cmp_b) : NULL;
1339 expr = get_expr_op(cmp_a, cmp_b);
1342 pn_Cmp pnc = get_Proj_proj(sel);
1344 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1345 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1346 /* a Cmp A =/!= 0 */
1347 ir_node *op1 = expr;
1348 ir_node *op2 = expr;
1349 ir_node *and = skip_Proj(expr);
1350 const char *cnst = NULL;
1352 /* check, if expr is an only once used And operation */
1353 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1354 op1 = get_irn_n(and, 2);
1355 op2 = get_irn_n(and, 3);
1357 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1359 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2, mode_T);
1360 set_ia32_pncode(res, get_Proj_proj(sel));
1363 copy_ia32_Immop_attr(res, and);
1366 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1371 if (mode_is_float(get_irn_mode(expr))) {
1372 res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1375 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1377 set_ia32_Immop_attr(res, cnst);
1380 if (mode_is_float(get_irn_mode(cmp_a))) {
1381 res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1384 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1388 set_ia32_pncode(res, get_Proj_proj(sel));
1389 set_ia32_am_support(res, ia32_am_Source);
1392 res = new_rd_ia32_SwitchJmp(dbg, irg, block, sel, mode_T);
1393 set_ia32_pncode(res, get_Cond_defaultProj(node));
1396 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1403 * Transforms a CopyB node.
1405 * @param env The transformation environment
1406 * @return The transformed node.
1408 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1409 ir_node *res = NULL;
1410 dbg_info *dbg = env->dbg;
1411 ir_graph *irg = env->irg;
1412 ir_mode *mode = env->mode;
1413 ir_node *block = env->block;
1414 ir_node *node = env->irn;
1415 ir_node *src = get_CopyB_src(node);
1416 ir_node *dst = get_CopyB_dst(node);
1417 ir_node *mem = get_CopyB_mem(node);
1418 int size = get_type_size_bytes(get_CopyB_type(node));
1421 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1422 /* then we need the size explicitly in ECX. */
1423 if (size >= 16 * 4) {
1424 rem = size & 0x3; /* size % 4 */
1427 res = new_rd_ia32_Const(dbg, irg, block, mode_Is);
1428 set_ia32_op_type(res, ia32_Const);
1429 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1431 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1432 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1435 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1436 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1437 set_ia32_immop_type(res, ia32_ImmConst);
1440 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1448 * Transforms a Mux node into CMov.
1450 * @param env The transformation environment
1451 * @return The transformed node.
1453 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1454 ir_node *node = env->irn;
1455 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1456 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1458 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1465 * Following conversion rules apply:
1469 * 1) n bit -> m bit n > m (downscale)
1470 * a) target is signed: movsx
1471 * b) target is unsigned: and with lower bits sets
1472 * 2) n bit -> m bit n == m (sign change)
1474 * 3) n bit -> m bit n < m (upscale)
1475 * a) source is signed: movsx
1476 * b) source is unsigned: and with lower bits sets
1480 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1484 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1485 * if target mode < 32bit: additional INT -> INT conversion (see above)
1489 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1492 //static ir_node *gen_int_downscale_conv(ia32_transform_env_t *env, ir_node *op,
1493 // ir_mode *src_mode, ir_mode *tgt_mode)
1495 // int n = get_mode_size_bits(src_mode);
1496 // int m = get_mode_size_bits(tgt_mode);
1497 // dbg_info *dbg = env->dbg;
1498 // ir_graph *irg = env->irg;
1499 // ir_node *block = env->block;
1500 // ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1501 // ir_node *nomem = new_rd_NoMem(irg);
1502 // ir_node *new_op, *proj;
1503 // assert(n > m && "downscale expected");
1504 // if (mode_is_signed(src_mode) && mode_is_signed(tgt_mode)) {
1505 // /* ASHL Sn, n - m */
1506 // new_op = new_rd_ia32_Shl(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
1507 // proj = new_rd_Proj(dbg, irg, block, new_op, src_mode, 0);
1508 // set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
1509 // set_ia32_am_support(new_op, ia32_am_Source);
1510 // SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1511 // /* ASHR Sn, n - m */
1512 // new_op = new_rd_ia32_Shrs(dbg, irg, block, noreg, noreg, proj, noreg, nomem, mode_T);
1513 // set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
1516 // new_op = new_rd_ia32_And(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
1517 // set_ia32_Immop_tarval(new_op, new_tarval_from_long((1 << m) - 1, mode_Is));
1523 * Transforms a Conv node.
1525 * @param env The transformation environment
1526 * @param op The operator
1527 * @return The created ia32 Conv node
1529 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
1530 dbg_info *dbg = env->dbg;
1531 ir_graph *irg = env->irg;
1532 ir_mode *src_mode = get_irn_mode(op);
1533 ir_mode *tgt_mode = env->mode;
1534 int src_bits = get_mode_size_bits(src_mode);
1535 int tgt_bits = get_mode_size_bits(tgt_mode);
1536 ir_node *block = env->block;
1537 ir_node *new_op = NULL;
1538 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1539 ir_node *nomem = new_rd_NoMem(irg);
1540 firm_dbg_module_t *mod = env->mod;
1543 if (src_mode == tgt_mode) {
1544 /* this can happen when changing mode_P to mode_Is */
1545 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1546 edges_reroute(env->irn, op, irg);
1548 else if (mode_is_float(src_mode)) {
1549 /* we convert from float ... */
1550 if (mode_is_float(tgt_mode)) {
1552 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1553 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1557 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1558 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1559 /* if target mode is not int: add an additional downscale convert */
1560 if (tgt_bits < 32) {
1561 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1562 set_ia32_res_mode(new_op, tgt_mode);
1563 set_ia32_am_support(new_op, ia32_am_Source);
1565 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
1567 if (tgt_bits == 8 || src_bits == 8) {
1568 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem, mode_T);
1571 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem, mode_T);
1577 /* we convert from int ... */
1578 if (mode_is_float(tgt_mode)) {
1580 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1581 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1585 if (get_mode_size_bits(src_mode) == tgt_bits) {
1586 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
1587 edges_reroute(env->irn, op, irg);
1590 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
1591 if (tgt_bits == 8 || src_bits == 8) {
1592 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1595 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1602 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1603 set_ia32_res_mode(new_op, tgt_mode);
1605 set_ia32_am_support(new_op, ia32_am_Source);
1607 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
1615 /********************************************
1618 * | |__ ___ _ __ ___ __| | ___ ___
1619 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1620 * | |_) | __/ | | | (_) | (_| | __/\__ \
1621 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1623 ********************************************/
1625 static ir_node *gen_StackParam(ia32_transform_env_t *env) {
1626 ir_node *new_op = NULL;
1627 ir_node *node = env->irn;
1628 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1629 ir_node *mem = new_rd_NoMem(env->irg);
1630 ir_node *ptr = get_irn_n(node, 0);
1631 entity *ent = be_get_frame_entity(node);
1632 ir_mode *mode = env->mode;
1634 // /* If the StackParam has only one user -> */
1635 // /* put it in the Block where the user resides */
1636 // if (get_irn_n_edges(node) == 1) {
1637 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
1640 if (mode_is_float(mode)) {
1641 if (USE_SSE2(env->cg))
1642 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1644 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1647 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1650 set_ia32_frame_ent(new_op, ent);
1651 set_ia32_use_frame(new_op);
1653 set_ia32_am_support(new_op, ia32_am_Source);
1654 set_ia32_op_type(new_op, ia32_AddrModeS);
1655 set_ia32_am_flavour(new_op, ia32_B);
1656 set_ia32_ls_mode(new_op, mode);
1658 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1660 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
1664 * Transforms a FrameAddr into an ia32 Add.
1666 static ir_node *gen_FrameAddr(ia32_transform_env_t *env) {
1667 ir_node *new_op = NULL;
1668 ir_node *node = env->irn;
1669 ir_node *op = get_irn_n(node, 0);
1670 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1671 ir_node *nomem = new_rd_NoMem(env->irg);
1673 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem, mode_T);
1674 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1675 set_ia32_am_support(new_op, ia32_am_Full);
1676 set_ia32_use_frame(new_op);
1677 set_ia32_immop_type(new_op, ia32_ImmConst);
1679 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1681 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1685 * Transforms a FrameLoad into an ia32 Load.
1687 static ir_node *gen_FrameLoad(ia32_transform_env_t *env) {
1688 ir_node *new_op = NULL;
1689 ir_node *node = env->irn;
1690 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1691 ir_node *mem = get_irn_n(node, 0);
1692 ir_node *ptr = get_irn_n(node, 1);
1693 entity *ent = be_get_frame_entity(node);
1694 ir_mode *mode = get_type_mode(get_entity_type(ent));
1696 if (mode_is_float(mode)) {
1697 if (USE_SSE2(env->cg))
1698 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1700 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1703 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1706 set_ia32_frame_ent(new_op, ent);
1707 set_ia32_use_frame(new_op);
1709 set_ia32_am_support(new_op, ia32_am_Source);
1710 set_ia32_op_type(new_op, ia32_AddrModeS);
1711 set_ia32_am_flavour(new_op, ia32_B);
1712 set_ia32_ls_mode(new_op, mode);
1714 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1721 * Transforms a FrameStore into an ia32 Store.
1723 static ir_node *gen_FrameStore(ia32_transform_env_t *env) {
1724 ir_node *new_op = NULL;
1725 ir_node *node = env->irn;
1726 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1727 ir_node *mem = get_irn_n(node, 0);
1728 ir_node *ptr = get_irn_n(node, 1);
1729 ir_node *val = get_irn_n(node, 2);
1730 entity *ent = be_get_frame_entity(node);
1731 ir_mode *mode = get_irn_mode(val);
1733 if (mode_is_float(mode)) {
1734 if (USE_SSE2(env->cg))
1735 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1737 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1739 else if (get_mode_size_bits(mode) == 8) {
1740 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1743 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1746 set_ia32_frame_ent(new_op, ent);
1747 set_ia32_use_frame(new_op);
1749 set_ia32_am_support(new_op, ia32_am_Dest);
1750 set_ia32_op_type(new_op, ia32_AddrModeD);
1751 set_ia32_am_flavour(new_op, ia32_B);
1752 set_ia32_ls_mode(new_op, mode);
1754 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1761 /*********************************************************
1764 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1765 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1766 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1767 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1769 *********************************************************/
1772 * Transforms a Sub or fSub into Neg--Add iff OUT_REG == SRC2_REG.
1773 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
1775 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
1776 ia32_transform_env_t tenv;
1777 ir_node *in1, *in2, *noreg, *nomem, *res;
1778 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
1780 /* Return if AM node or not a Sub or fSub */
1781 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_fSub(irn)))
1784 noreg = ia32_new_NoReg_gp(cg);
1785 nomem = new_rd_NoMem(cg->irg);
1786 in1 = get_irn_n(irn, 2);
1787 in2 = get_irn_n(irn, 3);
1788 in1_reg = arch_get_irn_register(cg->arch_env, in1);
1789 in2_reg = arch_get_irn_register(cg->arch_env, in2);
1790 out_reg = get_ia32_out_reg(irn, 0);
1792 tenv.block = get_nodes_block(irn);
1793 tenv.dbg = get_irn_dbg_info(irn);
1797 tenv.mode = get_ia32_res_mode(irn);
1800 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
1801 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
1802 /* generate the neg src2 */
1803 res = gen_Minus(&tenv, in2);
1804 arch_set_irn_register(cg->arch_env, res, in2_reg);
1806 /* add to schedule */
1807 sched_add_before(irn, res);
1809 /* generate the add */
1810 if (mode_is_float(tenv.mode)) {
1811 res = new_rd_ia32_fAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
1812 set_ia32_am_support(res, ia32_am_Source);
1815 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
1816 set_ia32_am_support(res, ia32_am_Full);
1819 SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv));
1821 slots = get_ia32_slots(res);
1824 /* add to schedule */
1825 sched_add_before(irn, res);
1827 /* remove the old sub */
1830 /* exchange the add and the sub */
1836 * Transforms a LEA into an Add if possible
1837 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
1839 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
1840 ia32_am_flavour_t am_flav;
1842 ir_node *res = NULL;
1843 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
1845 ia32_transform_env_t tenv;
1846 const arch_register_t *out_reg, *base_reg, *index_reg;
1849 if (! is_ia32_Lea(irn))
1852 am_flav = get_ia32_am_flavour(irn);
1854 /* only some LEAs can be transformed to an Add */
1855 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
1858 noreg = ia32_new_NoReg_gp(cg);
1859 nomem = new_rd_NoMem(cg->irg);
1862 base = get_irn_n(irn, 0);
1863 index = get_irn_n(irn,1);
1865 offs = get_ia32_am_offs(irn);
1867 /* offset has a explicit sign -> we need to skip + */
1868 if (offs && offs[0] == '+')
1871 out_reg = arch_get_irn_register(cg->arch_env, irn);
1872 base_reg = arch_get_irn_register(cg->arch_env, base);
1873 index_reg = arch_get_irn_register(cg->arch_env, index);
1875 tenv.block = get_nodes_block(irn);
1876 tenv.dbg = get_irn_dbg_info(irn);
1880 tenv.mode = get_irn_mode(irn);
1883 switch(get_ia32_am_flavour(irn)) {
1885 /* out register must be same as base register */
1886 if (! REGS_ARE_EQUAL(out_reg, base_reg))
1892 /* out register must be same as base register */
1893 if (! REGS_ARE_EQUAL(out_reg, base_reg))
1900 /* out register must be same as index register */
1901 if (! REGS_ARE_EQUAL(out_reg, index_reg))
1908 /* out register must be same as one in register */
1909 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
1913 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
1918 /* in registers a different from out -> no Add possible */
1925 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem, mode_T);
1926 arch_set_irn_register(cg->arch_env, res, out_reg);
1927 set_ia32_op_type(res, ia32_Normal);
1930 set_ia32_cnst(res, offs);
1931 set_ia32_immop_type(res, ia32_ImmConst);
1934 SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv));
1936 /* add Add to schedule */
1937 sched_add_before(irn, res);
1939 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, 0);
1941 /* add result Proj to schedule */
1942 sched_add_before(irn, res);
1944 /* remove the old LEA */
1947 /* exchange the Add and the LEA */
1952 * Transforms the given firm node (and maybe some other related nodes)
1953 * into one or more assembler nodes.
1955 * @param node the firm node
1956 * @param env the debug module
1958 void ia32_transform_node(ir_node *node, void *env) {
1959 ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env;
1961 ir_node *asm_node = NULL;
1962 ia32_transform_env_t tenv;
1967 tenv.block = get_nodes_block(node);
1968 tenv.dbg = get_irn_dbg_info(node);
1969 tenv.irg = current_ir_graph;
1971 tenv.mod = cgenv->mod;
1972 tenv.mode = get_irn_mode(node);
1975 #define UNOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_op(node)); break
1976 #define BINOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_left(node), get_##a##_right(node)); break
1977 #define GEN(a) case iro_##a: asm_node = gen_##a(&tenv); break
1978 #define IGN(a) case iro_##a: break
1979 #define BAD(a) case iro_##a: goto bad
1980 #define OTHER_BIN(a) \
1981 if (get_irn_op(node) == get_op_##a()) { \
1982 asm_node = gen_##a(&tenv, get_irn_n(node, 0), get_irn_n(node, 1)); \
1986 if (be_is_##a(node)) { \
1987 asm_node = gen_##a(&tenv); \
1991 DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
1993 code = get_irn_opcode(node);
2039 /* constant transformation happens earlier */
2069 fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
2073 /* exchange nodes if a new one was generated */
2075 exchange(node, asm_node);
2076 DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2079 DB((tenv.mod, LEVEL_1, "ignored\n"));