2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
15 #include "irgraph_t.h"
20 #include "iredges_t.h"
30 #include "archop.h" /* we need this for Min and Max nodes */
32 #include "../benode_t.h"
33 #include "../besched.h"
36 #include "bearch_ia32_t.h"
37 #include "ia32_nodes_attr.h"
38 #include "ia32_transform.h"
39 #include "ia32_new_nodes.h"
40 #include "ia32_map_regs.h"
41 #include "ia32_dbg_stat.h"
42 #include "ia32_optimize.h"
43 #include "ia32_util.h"
45 #include "gen_ia32_regalloc_if.h"
47 #define SFP_SIGN "0x80000000"
48 #define DFP_SIGN "0x8000000000000000"
49 #define SFP_ABS "0x7FFFFFFF"
50 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
52 #define TP_SFP_SIGN "ia32_sfp_sign"
53 #define TP_DFP_SIGN "ia32_dfp_sign"
54 #define TP_SFP_ABS "ia32_sfp_abs"
55 #define TP_DFP_ABS "ia32_dfp_abs"
57 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
58 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
59 #define ENT_SFP_ABS "IA32_SFP_ABS"
60 #define ENT_DFP_ABS "IA32_DFP_ABS"
62 extern ir_op *get_op_Mulh(void);
64 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
65 ir_node *op1, ir_node *op2, ir_node *mem);
67 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
68 ir_node *op, ir_node *mem);
71 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
74 /****************************************************************************************************
76 * | | | | / _| | | (_)
77 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
78 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
79 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
80 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
82 ****************************************************************************************************/
85 * Returns 1 if irn is a Const representing 0, 0 otherwise
87 static INLINE int is_ia32_Const_0(ir_node *irn) {
88 return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
89 classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
93 * Returns 1 if irn is a Const representing 1, 0 otherwise
95 static INLINE int is_ia32_Const_1(ir_node *irn) {
96 return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
97 classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
101 * Returns the Proj representing the UNKNOWN register for given mode.
103 static ir_node *be_get_unknown_for_mode(ia32_code_gen_t *cg, ir_mode *mode) {
104 be_abi_irg_t *babi = cg->birg->abi;
105 const arch_register_t *unknwn_reg = NULL;
107 if (mode_is_float(mode)) {
108 unknwn_reg = USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_UKNWN] : &ia32_vfp_regs[REG_VFP_UKNWN];
111 unknwn_reg = &ia32_gp_regs[REG_GP_UKNWN];
114 return be_abi_get_callee_save_irn(babi, unknwn_reg);
118 * Gets the Proj with number pn from irn.
120 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
121 const ir_edge_t *edge;
123 assert(get_irn_mode(irn) == mode_T && "need mode_T");
125 foreach_out_edge(irn, edge) {
126 proj = get_edge_src_irn(edge);
128 if (get_Proj_proj(proj) == pn)
136 * SSE convert of an integer node into a floating point node.
138 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block,
139 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
141 ir_node *noreg = ia32_new_NoReg_gp(cg);
142 ir_node *nomem = new_rd_NoMem(irg);
144 ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
145 set_ia32_src_mode(conv, get_irn_mode(in));
146 set_ia32_tgt_mode(conv, tgt_mode);
147 set_ia32_am_support(conv, ia32_am_Source);
148 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
150 return new_rd_Proj(dbg, irg, block, conv, tgt_mode, pn_ia32_Conv_I2FP_res);
153 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
154 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
155 static const struct {
157 const char *ent_name;
158 const char *cnst_str;
159 } names [ia32_known_const_max] = {
160 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
161 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
162 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
163 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
165 static struct entity *ent_cache[ia32_known_const_max];
167 const char *tp_name, *ent_name, *cnst_str;
174 ent_name = names[kct].ent_name;
175 if (! ent_cache[kct]) {
176 tp_name = names[kct].tp_name;
177 cnst_str = names[kct].cnst_str;
179 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
180 tp = new_type_primitive(new_id_from_str(tp_name), mode);
181 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
183 set_entity_ld_ident(ent, get_entity_ident(ent));
184 set_entity_visibility(ent, visibility_local);
185 set_entity_variability(ent, variability_constant);
186 set_entity_allocation(ent, allocation_static);
188 /* we create a new entity here: It's initialization must resist on the
190 rem = current_ir_graph;
191 current_ir_graph = get_const_code_irg();
192 cnst = new_Const(mode, tv);
193 current_ir_graph = rem;
195 set_atomic_ent_value(ent, cnst);
197 /* cache the entry */
198 ent_cache[kct] = ent;
201 return get_entity_ident(ent_cache[kct]);
206 * Prints the old node name on cg obst and returns a pointer to it.
208 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
209 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
211 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
212 obstack_1grow(isa->name_obst, 0);
213 isa->name_obst_size += obstack_object_size(isa->name_obst);
214 return obstack_finish(isa->name_obst);
218 /* determine if one operator is an Imm */
219 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
221 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
222 else return is_ia32_Cnst(op2) ? op2 : NULL;
225 /* determine if one operator is not an Imm */
226 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
227 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
232 * Construct a standard binary operation, set AM and immediate if required.
234 * @param env The transformation environment
235 * @param op1 The first operand
236 * @param op2 The second operand
237 * @param func The node constructor function
238 * @return The constructed ia32 node.
240 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
241 ir_node *new_op = NULL;
242 ir_mode *mode = env->mode;
243 dbg_info *dbg = env->dbg;
244 ir_graph *irg = env->irg;
245 ir_node *block = env->block;
246 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
247 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
248 ir_node *nomem = new_NoMem();
250 ir_node *expr_op, *imm_op;
251 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
253 /* Check if immediate optimization is on and */
254 /* if it's an operation with immediate. */
255 /* Mul/MulS/Mulh don't support immediates */
256 if (! (env->cg->opt & IA32_OPT_IMMOPS) ||
257 func == new_rd_ia32_Mul ||
258 func == new_rd_ia32_Mulh ||
259 func == new_rd_ia32_MulS)
263 /* immediate operations are requested, but we are here: it a mul */
264 if (env->cg->opt & IA32_OPT_IMMOPS)
267 else if (is_op_commutative(get_irn_op(env->irn))) {
268 imm_op = get_immediate_op(op1, op2);
269 expr_op = get_expr_op(op1, op2);
272 imm_op = get_immediate_op(NULL, op2);
273 expr_op = get_expr_op(op1, op2);
276 assert((expr_op || imm_op) && "invalid operands");
279 /* We have two consts here: not yet supported */
283 if (mode_is_float(mode)) {
284 /* floating point operations */
286 DB((mod, LEVEL_1, "FP with immediate ..."));
287 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
288 set_ia32_Immop_attr(new_op, imm_op);
289 set_ia32_am_support(new_op, ia32_am_None);
292 DB((mod, LEVEL_1, "FP binop ..."));
293 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
294 set_ia32_am_support(new_op, ia32_am_Source);
296 set_ia32_ls_mode(new_op, mode);
299 /* integer operations */
301 /* This is expr + const */
302 DB((mod, LEVEL_1, "INT with immediate ..."));
303 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
304 set_ia32_Immop_attr(new_op, imm_op);
307 set_ia32_am_support(new_op, ia32_am_Dest);
310 DB((mod, LEVEL_1, "INT binop ..."));
311 /* This is a normal operation */
312 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
315 set_ia32_am_support(new_op, ia32_am_Full);
318 /* Muls can only have AM source */
320 set_ia32_am_support(new_op, ia32_am_Source);
323 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
325 set_ia32_res_mode(new_op, mode);
327 if (is_op_commutative(get_irn_op(env->irn))) {
328 set_ia32_commutative(new_op);
331 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
337 * Construct a shift/rotate binary operation, sets AM and immediate if required.
339 * @param env The transformation environment
340 * @param op1 The first operand
341 * @param op2 The second operand
342 * @param func The node constructor function
343 * @return The constructed ia32 node.
345 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
346 ir_node *new_op = NULL;
347 ir_mode *mode = env->mode;
348 dbg_info *dbg = env->dbg;
349 ir_graph *irg = env->irg;
350 ir_node *block = env->block;
351 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
352 ir_node *nomem = new_NoMem();
353 ir_node *expr_op, *imm_op;
355 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
357 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
359 /* Check if immediate optimization is on and */
360 /* if it's an operation with immediate. */
361 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
362 expr_op = get_expr_op(op1, op2);
364 assert((expr_op || imm_op) && "invalid operands");
367 /* We have two consts here: not yet supported */
371 /* Limit imm_op within range imm8 */
373 tv = get_ia32_Immop_tarval(imm_op);
376 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
377 set_ia32_Immop_tarval(imm_op, tv);
384 /* integer operations */
386 /* This is shift/rot with const */
387 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
389 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
390 set_ia32_Immop_attr(new_op, imm_op);
393 /* This is a normal shift/rot */
394 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
395 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
399 set_ia32_am_support(new_op, ia32_am_Dest);
401 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
403 set_ia32_res_mode(new_op, mode);
404 set_ia32_emit_cl(new_op);
406 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
411 * Construct a standard unary operation, set AM and immediate if required.
413 * @param env The transformation environment
414 * @param op The operand
415 * @param func The node constructor function
416 * @return The constructed ia32 node.
418 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
419 ir_node *new_op = NULL;
420 ir_mode *mode = env->mode;
421 dbg_info *dbg = env->dbg;
422 ir_graph *irg = env->irg;
423 ir_node *block = env->block;
424 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
425 ir_node *nomem = new_NoMem();
426 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
428 new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
430 if (mode_is_float(mode)) {
431 DB((mod, LEVEL_1, "FP unop ..."));
432 /* floating point operations don't support implicit store */
433 set_ia32_am_support(new_op, ia32_am_None);
436 DB((mod, LEVEL_1, "INT unop ..."));
437 set_ia32_am_support(new_op, ia32_am_Dest);
440 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
442 set_ia32_res_mode(new_op, mode);
444 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
450 * Creates an ia32 Add with immediate.
452 * @param env The transformation environment
453 * @param expr_op The expression operator
454 * @param const_op The constant
455 * @return the created ia32 Add node
457 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
458 ir_node *new_op = NULL;
459 tarval *tv = get_ia32_Immop_tarval(const_op);
460 dbg_info *dbg = env->dbg;
461 ir_graph *irg = env->irg;
462 ir_node *block = env->block;
463 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
464 ir_node *nomem = new_NoMem();
466 tarval_classification_t class_tv, class_negtv;
467 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
469 /* try to optimize to inc/dec */
470 if ((env->cg->opt & IA32_OPT_INCDEC) && (get_ia32_op_type(const_op) == ia32_Const)) {
471 /* optimize tarvals */
472 class_tv = classify_tarval(tv);
473 class_negtv = classify_tarval(tarval_neg(tv));
475 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
476 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
477 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
480 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
481 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
482 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
488 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
489 set_ia32_Immop_attr(new_op, const_op);
490 set_ia32_commutative(new_op);
497 * Creates an ia32 Add.
499 * @param env The transformation environment
500 * @return the created ia32 Add node
502 static ir_node *gen_Add(ia32_transform_env_t *env) {
503 ir_node *new_op = NULL;
504 dbg_info *dbg = env->dbg;
505 ir_mode *mode = env->mode;
506 ir_graph *irg = env->irg;
507 ir_node *block = env->block;
508 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
509 ir_node *nomem = new_NoMem();
510 ir_node *expr_op, *imm_op;
511 ir_node *op1 = get_Add_left(env->irn);
512 ir_node *op2 = get_Add_right(env->irn);
514 /* Check if immediate optimization is on and */
515 /* if it's an operation with immediate. */
516 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
517 expr_op = get_expr_op(op1, op2);
519 assert((expr_op || imm_op) && "invalid operands");
521 if (mode_is_float(mode)) {
523 if (USE_SSE2(env->cg))
524 return gen_binop(env, op1, op2, new_rd_ia32_xAdd);
526 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
531 /* No expr_op means, that we have two const - one symconst and */
532 /* one tarval or another symconst - because this case is not */
533 /* covered by constant folding */
534 /* We need to check for: */
535 /* 1) symconst + const -> becomes a LEA */
536 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
537 /* linker doesn't support two symconsts */
539 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
540 /* this is the 2nd case */
541 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
542 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
543 set_ia32_am_flavour(new_op, ia32_am_OB);
545 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
548 /* this is the 1st case */
549 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
551 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
553 if (get_ia32_op_type(op1) == ia32_SymConst) {
554 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
555 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
558 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
559 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
561 set_ia32_am_flavour(new_op, ia32_am_O);
565 set_ia32_am_support(new_op, ia32_am_Source);
566 set_ia32_op_type(new_op, ia32_AddrModeS);
568 /* Lea doesn't need a Proj */
572 /* This is expr + const */
573 new_op = gen_imm_Add(env, expr_op, imm_op);
576 set_ia32_am_support(new_op, ia32_am_Dest);
579 /* This is a normal add */
580 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
583 set_ia32_am_support(new_op, ia32_am_Full);
584 set_ia32_commutative(new_op);
588 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
590 set_ia32_res_mode(new_op, mode);
592 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Add_res);
598 * Creates an ia32 Mul.
600 * @param env The transformation environment
601 * @return the created ia32 Mul node
603 static ir_node *gen_Mul(ia32_transform_env_t *env) {
604 ir_node *op1 = get_Mul_left(env->irn);
605 ir_node *op2 = get_Mul_right(env->irn);
608 if (mode_is_float(env->mode)) {
610 if (USE_SSE2(env->cg))
611 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMul);
613 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
616 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
625 * Creates an ia32 Mulh.
626 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
627 * this result while Mul returns the lower 32 bit.
629 * @param env The transformation environment
630 * @return the created ia32 Mulh node
632 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
633 ir_node *op1 = get_irn_n(env->irn, 0);
634 ir_node *op2 = get_irn_n(env->irn, 1);
635 ir_node *proj_EAX, *proj_EDX, *mulh;
638 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
639 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
640 mulh = get_Proj_pred(proj_EAX);
641 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
643 /* to be on the save side */
644 set_Proj_proj(proj_EAX, pn_EAX);
646 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
647 /* Mulh with const cannot have AM */
648 set_ia32_am_support(mulh, ia32_am_None);
651 /* Mulh cannot have AM for destination */
652 set_ia32_am_support(mulh, ia32_am_Source);
658 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
666 * Creates an ia32 And.
668 * @param env The transformation environment
669 * @return The created ia32 And node
671 static ir_node *gen_And(ia32_transform_env_t *env) {
672 ir_node *op1 = get_And_left(env->irn);
673 ir_node *op2 = get_And_right(env->irn);
675 assert (! mode_is_float(env->mode));
676 return gen_binop(env, op1, op2, new_rd_ia32_And);
682 * Creates an ia32 Or.
684 * @param env The transformation environment
685 * @return The created ia32 Or node
687 static ir_node *gen_Or(ia32_transform_env_t *env) {
688 ir_node *op1 = get_Or_left(env->irn);
689 ir_node *op2 = get_Or_right(env->irn);
691 assert (! mode_is_float(env->mode));
692 return gen_binop(env, op1, op2, new_rd_ia32_Or);
698 * Creates an ia32 Eor.
700 * @param env The transformation environment
701 * @return The created ia32 Eor node
703 static ir_node *gen_Eor(ia32_transform_env_t *env) {
704 ir_node *op1 = get_Eor_left(env->irn);
705 ir_node *op2 = get_Eor_right(env->irn);
707 assert(! mode_is_float(env->mode));
708 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
714 * Creates an ia32 Max.
716 * @param env The transformation environment
717 * @return the created ia32 Max node
719 static ir_node *gen_Max(ia32_transform_env_t *env) {
720 ir_node *op1 = get_irn_n(env->irn, 0);
721 ir_node *op2 = get_irn_n(env->irn, 1);
724 if (mode_is_float(env->mode)) {
726 if (USE_SSE2(env->cg))
727 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMax);
733 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
734 set_ia32_am_support(new_op, ia32_am_None);
735 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
744 * Creates an ia32 Min.
746 * @param env The transformation environment
747 * @return the created ia32 Min node
749 static ir_node *gen_Min(ia32_transform_env_t *env) {
750 ir_node *op1 = get_irn_n(env->irn, 0);
751 ir_node *op2 = get_irn_n(env->irn, 1);
754 if (mode_is_float(env->mode)) {
756 if (USE_SSE2(env->cg))
757 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMin);
763 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
764 set_ia32_am_support(new_op, ia32_am_None);
765 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
774 * Creates an ia32 Sub with immediate.
776 * @param env The transformation environment
777 * @param expr_op The first operator
778 * @param const_op The constant operator
779 * @return The created ia32 Sub node
781 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
782 ir_node *new_op = NULL;
783 tarval *tv = get_ia32_Immop_tarval(const_op);
784 dbg_info *dbg = env->dbg;
785 ir_graph *irg = env->irg;
786 ir_node *block = env->block;
787 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
788 ir_node *nomem = new_NoMem();
790 tarval_classification_t class_tv, class_negtv;
791 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
793 /* try to optimize to inc/dec */
794 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
795 /* optimize tarvals */
796 class_tv = classify_tarval(tv);
797 class_negtv = classify_tarval(tarval_neg(tv));
799 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
800 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
801 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
804 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
805 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
806 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
812 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
813 set_ia32_Immop_attr(new_op, const_op);
820 * Creates an ia32 Sub.
822 * @param env The transformation environment
823 * @return The created ia32 Sub node
825 static ir_node *gen_Sub(ia32_transform_env_t *env) {
826 ir_node *new_op = NULL;
827 dbg_info *dbg = env->dbg;
828 ir_mode *mode = env->mode;
829 ir_graph *irg = env->irg;
830 ir_node *block = env->block;
831 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
832 ir_node *nomem = new_NoMem();
833 ir_node *op1 = get_Sub_left(env->irn);
834 ir_node *op2 = get_Sub_right(env->irn);
835 ir_node *expr_op, *imm_op;
837 /* Check if immediate optimization is on and */
838 /* if it's an operation with immediate. */
839 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
840 expr_op = get_expr_op(op1, op2);
842 assert((expr_op || imm_op) && "invalid operands");
844 if (mode_is_float(mode)) {
846 if (USE_SSE2(env->cg))
847 return gen_binop(env, op1, op2, new_rd_ia32_xSub);
849 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
854 /* No expr_op means, that we have two const - one symconst and */
855 /* one tarval or another symconst - because this case is not */
856 /* covered by constant folding */
857 /* We need to check for: */
858 /* 1) symconst - const -> becomes a LEA */
859 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
860 /* linker doesn't support two symconsts */
862 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
863 /* this is the 2nd case */
864 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
865 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
866 set_ia32_am_sc_sign(new_op);
867 set_ia32_am_flavour(new_op, ia32_am_OB);
869 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
872 /* this is the 1st case */
873 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
875 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
877 if (get_ia32_op_type(op1) == ia32_SymConst) {
878 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
879 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
882 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
883 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
884 set_ia32_am_sc_sign(new_op);
886 set_ia32_am_flavour(new_op, ia32_am_O);
890 set_ia32_am_support(new_op, ia32_am_Source);
891 set_ia32_op_type(new_op, ia32_AddrModeS);
893 /* Lea doesn't need a Proj */
897 /* This is expr - const */
898 new_op = gen_imm_Sub(env, expr_op, imm_op);
901 set_ia32_am_support(new_op, ia32_am_Dest);
904 /* This is a normal sub */
905 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
908 set_ia32_am_support(new_op, ia32_am_Full);
912 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
914 set_ia32_res_mode(new_op, mode);
916 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Sub_res);
922 * Generates an ia32 DivMod with additional infrastructure for the
923 * register allocator if needed.
925 * @param env The transformation environment
926 * @param dividend -no comment- :)
927 * @param divisor -no comment- :)
928 * @param dm_flav flavour_Div/Mod/DivMod
929 * @return The created ia32 DivMod node
931 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
933 ir_node *edx_node, *cltd;
935 dbg_info *dbg = env->dbg;
936 ir_graph *irg = env->irg;
937 ir_node *block = env->block;
938 ir_mode *mode = env->mode;
939 ir_node *irn = env->irn;
945 mem = get_Div_mem(irn);
946 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
949 mem = get_Mod_mem(irn);
950 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
953 mem = get_DivMod_mem(irn);
954 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
960 if (mode_is_signed(mode)) {
961 /* in signed mode, we need to sign extend the dividend */
962 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
963 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
964 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
967 edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
968 set_ia32_Const_type(edx_node, ia32_Const);
969 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
972 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
974 set_ia32_n_res(res, 2);
976 /* Only one proj is used -> We must add a second proj and */
977 /* connect this one to a Keep node to eat up the second */
978 /* destroyed register. */
979 n = get_irn_n_edges(irn);
982 proj = ia32_get_proj_for_mode(irn, mode_M);
984 /* in case of two projs, one must be the memory proj */
985 if (n == 1 || (n == 2 && proj)) {
986 proj = ia32_get_res_proj(irn);
987 assert(proj && "Result proj expected");
989 if (get_irn_op(irn) == op_Div) {
990 set_Proj_proj(proj, pn_DivMod_res_div);
991 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_mod);
994 set_Proj_proj(proj, pn_DivMod_res_mod);
995 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_div);
998 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1001 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1003 set_ia32_res_mode(res, mode);
1010 * Wrapper for generate_DivMod. Sets flavour_Mod.
1012 * @param env The transformation environment
1014 static ir_node *gen_Mod(ia32_transform_env_t *env) {
1015 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
1019 * Wrapper for generate_DivMod. Sets flavour_Div.
1021 * @param env The transformation environment
1023 static ir_node *gen_Div(ia32_transform_env_t *env) {
1024 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
1028 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1030 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
1031 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
1037 * Creates an ia32 floating Div.
1039 * @param env The transformation environment
1040 * @return The created ia32 xDiv node
1042 static ir_node *gen_Quot(ia32_transform_env_t *env) {
1043 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1045 ir_node *nomem = new_rd_NoMem(env->irg);
1046 ir_node *op1 = get_Quot_left(env->irn);
1047 ir_node *op2 = get_Quot_right(env->irn);
1050 if (USE_SSE2(env->cg)) {
1051 if (is_ia32_xConst(op2)) {
1052 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
1053 set_ia32_am_support(new_op, ia32_am_None);
1054 set_ia32_Immop_attr(new_op, op2);
1057 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1058 set_ia32_am_support(new_op, ia32_am_Source);
1062 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1063 set_ia32_am_support(new_op, ia32_am_Source);
1065 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
1066 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1074 * Creates an ia32 Shl.
1076 * @param env The transformation environment
1077 * @return The created ia32 Shl node
1079 static ir_node *gen_Shl(ia32_transform_env_t *env) {
1080 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
1086 * Creates an ia32 Shr.
1088 * @param env The transformation environment
1089 * @return The created ia32 Shr node
1091 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1092 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1098 * Creates an ia32 Shrs.
1100 * @param env The transformation environment
1101 * @return The created ia32 Shrs node
1103 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1104 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1110 * Creates an ia32 RotL.
1112 * @param env The transformation environment
1113 * @param op1 The first operator
1114 * @param op2 The second operator
1115 * @return The created ia32 RotL node
1117 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1118 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1124 * Creates an ia32 RotR.
1125 * NOTE: There is no RotR with immediate because this would always be a RotL
1126 * "imm-mode_size_bits" which can be pre-calculated.
1128 * @param env The transformation environment
1129 * @param op1 The first operator
1130 * @param op2 The second operator
1131 * @return The created ia32 RotR node
1133 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1134 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1140 * Creates an ia32 RotR or RotL (depending on the found pattern).
1142 * @param env The transformation environment
1143 * @return The created ia32 RotL or RotR node
1145 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1146 ir_node *rotate = NULL;
1147 ir_node *op1 = get_Rot_left(env->irn);
1148 ir_node *op2 = get_Rot_right(env->irn);
1150 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1151 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1152 that means we can create a RotR instead of an Add and a RotL */
1155 ir_node *pred = get_Proj_pred(op2);
1157 if (is_ia32_Add(pred)) {
1158 ir_node *pred_pred = get_irn_n(pred, 2);
1159 tarval *tv = get_ia32_Immop_tarval(pred);
1160 long bits = get_mode_size_bits(env->mode);
1162 if (is_Proj(pred_pred)) {
1163 pred_pred = get_Proj_pred(pred_pred);
1166 if (is_ia32_Minus(pred_pred) &&
1167 tarval_is_long(tv) &&
1168 get_tarval_long(tv) == bits)
1170 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1171 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1178 rotate = gen_RotL(env, op1, op2);
1187 * Transforms a Minus node.
1189 * @param env The transformation environment
1190 * @param op The Minus operand
1191 * @return The created ia32 Minus node
1193 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1198 if (mode_is_float(env->mode)) {
1200 if (USE_SSE2(env->cg)) {
1201 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1202 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1203 ir_node *nomem = new_rd_NoMem(env->irg);
1205 new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1207 size = get_mode_size_bits(env->mode);
1208 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1210 set_ia32_am_sc(new_op, name);
1212 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1214 set_ia32_res_mode(new_op, env->mode);
1215 set_ia32_op_type(new_op, ia32_AddrModeS);
1216 set_ia32_ls_mode(new_op, env->mode);
1218 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
1221 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1222 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1226 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1233 * Transforms a Minus node.
1235 * @param env The transformation environment
1236 * @return The created ia32 Minus node
1238 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1239 return gen_Minus_ex(env, get_Minus_op(env->irn));
1244 * Transforms a Not node.
1246 * @param env The transformation environment
1247 * @return The created ia32 Not node
1249 static ir_node *gen_Not(ia32_transform_env_t *env) {
1250 assert (! mode_is_float(env->mode));
1251 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1257 * Transforms an Abs node.
1259 * @param env The transformation environment
1260 * @return The created ia32 Abs node
1262 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1263 ir_node *res, *p_eax, *p_edx;
1264 dbg_info *dbg = env->dbg;
1265 ir_mode *mode = env->mode;
1266 ir_graph *irg = env->irg;
1267 ir_node *block = env->block;
1268 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1269 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1270 ir_node *nomem = new_NoMem();
1271 ir_node *op = get_Abs_op(env->irn);
1275 if (mode_is_float(mode)) {
1277 if (USE_SSE2(env->cg)) {
1278 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1280 size = get_mode_size_bits(mode);
1281 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1283 set_ia32_am_sc(res, name);
1285 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1287 set_ia32_res_mode(res, mode);
1288 set_ia32_op_type(res, ia32_AddrModeS);
1289 set_ia32_ls_mode(res, env->mode);
1291 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
1294 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1295 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1299 res = new_rd_ia32_Cdq(dbg, irg, block, op);
1300 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1301 set_ia32_res_mode(res, mode);
1303 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
1304 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
1306 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1307 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1308 set_ia32_res_mode(res, mode);
1310 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
1312 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1313 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1314 set_ia32_res_mode(res, mode);
1316 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
1325 * Transforms a Load.
1327 * @param env The transformation environment
1328 * @return the created ia32 Load node
1330 static ir_node *gen_Load(ia32_transform_env_t *env) {
1331 ir_node *node = env->irn;
1332 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1333 ir_node *ptr = get_Load_ptr(node);
1334 ir_node *lptr = ptr;
1335 ir_mode *mode = get_Load_mode(node);
1338 ia32_am_flavour_t am_flav = ia32_am_B;
1340 /* address might be a constant (symconst or absolute address) */
1341 if (is_ia32_Const(ptr)) {
1346 if (mode_is_float(mode)) {
1348 if (USE_SSE2(env->cg))
1349 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1351 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1354 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1357 /* base is an constant address */
1359 if (get_ia32_op_type(ptr) == ia32_SymConst) {
1360 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1361 am_flav = ia32_am_N;
1364 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1365 am_flav = ia32_am_O;
1369 set_ia32_am_support(new_op, ia32_am_Source);
1370 set_ia32_op_type(new_op, ia32_AddrModeS);
1371 set_ia32_am_flavour(new_op, am_flav);
1372 set_ia32_ls_mode(new_op, mode);
1375 check for special case: the loaded value might not be used (optimized, volatile, ...)
1376 we add a Proj + Keep for volatile loads and ignore all other cases
1378 if (! get_proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1379 /* add a result proj and a Keep to produce a pseudo use */
1380 ir_node *proj = new_r_Proj(env->irg, env->block, new_op, mode, pn_ia32_Load_res);
1381 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), env->irg, env->block, 1, &proj);
1384 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1392 * Transforms a Store.
1394 * @param env The transformation environment
1395 * @return the created ia32 Store node
1397 static ir_node *gen_Store(ia32_transform_env_t *env) {
1398 ir_node *node = env->irn;
1399 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1400 ir_node *val = get_Store_value(node);
1401 ir_node *ptr = get_Store_ptr(node);
1402 ir_node *sptr = ptr;
1403 ir_node *mem = get_Store_mem(node);
1404 ir_mode *mode = get_irn_mode(val);
1405 ir_node *sval = val;
1408 ia32_am_flavour_t am_flav = ia32_am_B;
1409 ia32_immop_type_t immop = ia32_ImmNone;
1411 if (! mode_is_float(mode)) {
1412 /* in case of storing a const (but not a symconst) -> make it an attribute */
1413 if (is_ia32_Cnst(val)) {
1414 switch (get_ia32_op_type(val)) {
1416 immop = ia32_ImmConst;
1419 immop = ia32_ImmSymConst;
1422 assert(0 && "unsupported Const type");
1428 /* address might be a constant (symconst or absolute address) */
1429 if (is_ia32_Const(ptr)) {
1434 if (mode_is_float(mode)) {
1436 if (USE_SSE2(env->cg))
1437 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1439 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1441 else if (get_mode_size_bits(mode) == 8) {
1442 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1445 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1448 /* stored const is an attribute (saves a register) */
1449 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1450 set_ia32_Immop_attr(new_op, val);
1453 /* base is an constant address */
1455 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1456 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1457 am_flav = ia32_am_N;
1460 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1461 am_flav = ia32_am_O;
1465 set_ia32_am_support(new_op, ia32_am_Dest);
1466 set_ia32_op_type(new_op, ia32_AddrModeD);
1467 set_ia32_am_flavour(new_op, am_flav);
1468 set_ia32_ls_mode(new_op, mode);
1469 set_ia32_immop_type(new_op, immop);
1471 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1479 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1481 * @param env The transformation environment
1482 * @return The transformed node.
1484 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1485 dbg_info *dbg = env->dbg;
1486 ir_graph *irg = env->irg;
1487 ir_node *block = env->block;
1488 ir_node *node = env->irn;
1489 ir_node *sel = get_Cond_selector(node);
1490 ir_mode *sel_mode = get_irn_mode(sel);
1491 ir_node *res = NULL;
1492 ir_node *pred = NULL;
1493 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1494 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1496 if (is_Proj(sel) && sel_mode == mode_b) {
1497 ir_node *nomem = new_NoMem();
1499 pred = get_Proj_pred(sel);
1501 /* get both compare operators */
1502 cmp_a = get_Cmp_left(pred);
1503 cmp_b = get_Cmp_right(pred);
1505 /* check if we can use a CondJmp with immediate */
1506 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1507 expr = get_expr_op(cmp_a, cmp_b);
1510 pn_Cmp pnc = get_Proj_proj(sel);
1512 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1513 if (get_ia32_op_type(cnst) == ia32_Const &&
1514 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1516 /* a Cmp A =/!= 0 */
1517 ir_node *op1 = expr;
1518 ir_node *op2 = expr;
1519 ir_node *and = skip_Proj(expr);
1520 const char *cnst = NULL;
1522 /* check, if expr is an only once used And operation */
1523 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1524 op1 = get_irn_n(and, 2);
1525 op2 = get_irn_n(and, 3);
1527 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1529 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1530 set_ia32_pncode(res, get_Proj_proj(sel));
1531 set_ia32_res_mode(res, get_irn_mode(op1));
1534 copy_ia32_Immop_attr(res, and);
1537 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1542 if (mode_is_float(get_irn_mode(expr))) {
1544 if (USE_SSE2(env->cg))
1545 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1551 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1553 set_ia32_Immop_attr(res, cnst);
1554 set_ia32_res_mode(res, get_irn_mode(expr));
1557 if (mode_is_float(get_irn_mode(cmp_a))) {
1559 if (USE_SSE2(env->cg))
1560 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1563 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1564 proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
1565 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1569 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1570 set_ia32_commutative(res);
1572 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1575 set_ia32_pncode(res, get_Proj_proj(sel));
1576 //set_ia32_am_support(res, ia32_am_Source);
1579 /* determine the smallest switch case value */
1580 int switch_min = INT_MAX;
1581 const ir_edge_t *edge;
1584 foreach_out_edge(node, edge) {
1585 int pn = get_Proj_proj(get_edge_src_irn(edge));
1586 switch_min = pn < switch_min ? pn : switch_min;
1590 /* if smallest switch case is not 0 we need an additional sub */
1591 snprintf(buf, sizeof(buf), "%d", switch_min);
1592 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1593 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1594 sub_ia32_am_offs(res, buf);
1595 set_ia32_am_flavour(res, ia32_am_OB);
1596 set_ia32_am_support(res, ia32_am_Source);
1597 set_ia32_op_type(res, ia32_AddrModeS);
1600 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1601 set_ia32_pncode(res, get_Cond_defaultProj(node));
1602 set_ia32_res_mode(res, get_irn_mode(sel));
1605 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1612 * Transforms a CopyB node.
1614 * @param env The transformation environment
1615 * @return The transformed node.
1617 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1618 ir_node *res = NULL;
1619 dbg_info *dbg = env->dbg;
1620 ir_graph *irg = env->irg;
1621 ir_node *block = env->block;
1622 ir_node *node = env->irn;
1623 ir_node *src = get_CopyB_src(node);
1624 ir_node *dst = get_CopyB_dst(node);
1625 ir_node *mem = get_CopyB_mem(node);
1626 int size = get_type_size_bytes(get_CopyB_type(node));
1627 ir_mode *dst_mode = get_irn_mode(dst);
1628 ir_mode *src_mode = get_irn_mode(src);
1630 ir_node *in[3], *tmp;
1632 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1633 /* then we need the size explicitly in ECX. */
1634 if (size >= 16 * 4) {
1635 rem = size & 0x3; /* size % 4 */
1638 res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
1639 set_ia32_op_type(res, ia32_Const);
1640 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1642 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem);
1643 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1645 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1646 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1647 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1648 in[2] = new_r_Proj(irg, block, res, mode_Is, pn_ia32_CopyB_CNT);
1649 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1651 tmp = ia32_get_proj_for_mode(node, mode_M);
1652 set_Proj_proj(tmp, pn_ia32_CopyB_M);
1655 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem);
1656 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1657 set_ia32_immop_type(res, ia32_ImmConst);
1659 /* ok: now attach Proj's because movsd will destroy esi and edi */
1660 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1661 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1662 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1664 tmp = ia32_get_proj_for_mode(node, mode_M);
1665 set_Proj_proj(tmp, pn_ia32_CopyB_i_M);
1668 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1676 * Transforms a Mux node into CMov.
1678 * @param env The transformation environment
1679 * @return The transformed node.
1681 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1683 ir_node *node = env->irn;
1684 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1685 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1687 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1694 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *cmp_a, ir_node *cmp_b, \
1695 ir_node *psi_true, ir_node *psi_default, ir_mode *mode);
1698 * Transforms a Psi node into CMov.
1700 * @param env The transformation environment
1701 * @return The transformed node.
1703 static ir_node *gen_Psi(ia32_transform_env_t *env) {
1704 ia32_code_gen_t *cg = env->cg;
1705 dbg_info *dbg = env->dbg;
1706 ir_graph *irg = env->irg;
1707 ir_mode *mode = env->mode;
1708 ir_node *block = env->block;
1709 ir_node *node = env->irn;
1710 ir_node *cmp_proj = get_Mux_sel(node);
1711 ir_node *psi_true = get_Psi_val(node, 0);
1712 ir_node *psi_default = get_Psi_default(node);
1713 ir_node *noreg = ia32_new_NoReg_gp(cg);
1714 ir_node *nomem = new_rd_NoMem(irg);
1715 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
1718 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
1720 cmp = get_Proj_pred(cmp_proj);
1721 cmp_a = get_Cmp_left(cmp);
1722 cmp_b = get_Cmp_right(cmp);
1723 pnc = get_Proj_proj(cmp_proj);
1725 if (mode_is_float(mode)) {
1726 /* floating point psi */
1729 /* 1st case: compare operands are float too */
1731 /* psi(cmp(a, b), t, f) can be done as: */
1732 /* tmp = cmp a, b */
1733 /* tmp2 = t and tmp */
1734 /* tmp3 = f and not tmp */
1735 /* res = tmp2 or tmp3 */
1737 /* in case the compare operands are int, we move them into xmm register */
1738 if (! mode_is_float(get_irn_mode(cmp_a))) {
1739 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, node, mode_D);
1740 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, node, mode_D);
1742 pnc |= 8; /* transform integer compare to fp compare */
1745 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1746 set_ia32_pncode(new_op, pnc);
1747 set_ia32_am_support(new_op, ia32_am_Source);
1748 set_ia32_res_mode(new_op, mode);
1749 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1750 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xCmp_res);
1752 and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, psi_true, new_op, nomem);
1753 set_ia32_am_support(and1, ia32_am_None);
1754 set_ia32_res_mode(and1, mode);
1755 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
1756 and1 = new_rd_Proj(dbg, irg, block, and1, mode, pn_ia32_xAnd_res);
1758 and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, psi_default, nomem);
1759 set_ia32_am_support(and2, ia32_am_None);
1760 set_ia32_res_mode(and2, mode);
1761 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
1762 and2 = new_rd_Proj(dbg, irg, block, and2, mode, pn_ia32_xAndNot_res);
1764 new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
1765 set_ia32_am_support(new_op, ia32_am_None);
1766 set_ia32_res_mode(new_op, mode);
1767 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1768 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xOr_res);
1772 new_op = new_rd_ia32_vfCMov(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1773 set_ia32_pncode(new_op, pnc);
1774 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1779 construct_binop_func *set_func = NULL;
1780 cmov_func_t *cmov_func = NULL;
1782 if (mode_is_float(get_irn_mode(cmp_a))) {
1783 /* 1st case: compare operands are floats */
1788 set_func = new_rd_ia32_xCmpSet;
1789 cmov_func = new_rd_ia32_xCmpCMov;
1793 set_func = new_rd_ia32_vfCmpSet;
1794 cmov_func = new_rd_ia32_vfCmpCMov;
1797 pnc &= 7; /* fp compare -> int compare */
1800 /* 2nd case: compare operand are integer too */
1801 set_func = new_rd_ia32_CmpSet;
1802 cmov_func = new_rd_ia32_CmpCMov;
1805 /* create the nodes */
1807 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
1808 if (is_ia32_Const_0(cmp_b) && is_Proj(cmp_a) && (is_ia32_And(get_Proj_pred(cmp_a)) || is_ia32_Or(get_Proj_pred(cmp_a)))) {
1809 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1810 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1811 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1812 set_ia32_pncode(new_op, pnc);
1814 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1815 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1816 /* we invert condition and set default to 0 */
1817 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1818 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
1821 /* otherwise: use CMOVcc */
1822 new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, cmp_a, psi_true, psi_default, mode);
1823 set_ia32_pncode(new_op, pnc);
1826 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1830 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1831 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1832 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1833 set_ia32_pncode(get_Proj_pred(new_op), pnc);
1834 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1836 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1837 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1838 /* we invert condition and set default to 0 */
1839 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1840 set_ia32_pncode(get_Proj_pred(new_op), get_inversed_pnc(pnc));
1841 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1844 /* otherwise: use CMOVcc */
1845 new_op = cmov_func(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1846 set_ia32_pncode(new_op, pnc);
1847 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1857 * Following conversion rules apply:
1861 * 1) n bit -> m bit n > m (downscale)
1862 * a) target is signed: movsx
1863 * b) target is unsigned: and with lower bits sets
1864 * 2) n bit -> m bit n == m (sign change)
1866 * 3) n bit -> m bit n < m (upscale)
1867 * a) source is signed: movsx
1868 * b) source is unsigned: and with lower bits sets
1872 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1876 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1877 * if target mode < 32bit: additional INT -> INT conversion (see above)
1881 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1882 * x87 is mode_E internally, conversions happen only at load and store
1883 * in non-strict semantic
1887 * Create a conversion from x87 state register to general purpose.
1889 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1890 ia32_code_gen_t *cg = env->cg;
1891 entity *ent = cg->fp_to_gp;
1892 ir_graph *irg = env->irg;
1893 ir_node *block = env->block;
1894 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1895 ir_node *op = get_Conv_op(env->irn);
1896 ir_node *fist, *mem, *load;
1899 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1900 ent = cg->fp_to_gp =
1901 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1905 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
1907 set_ia32_frame_ent(fist, ent);
1908 set_ia32_use_frame(fist);
1909 set_ia32_am_support(fist, ia32_am_Dest);
1910 set_ia32_op_type(fist, ia32_AddrModeD);
1911 set_ia32_am_flavour(fist, ia32_B);
1912 set_ia32_ls_mode(fist, mode_F);
1914 mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
1917 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1919 set_ia32_frame_ent(load, ent);
1920 set_ia32_use_frame(load);
1921 set_ia32_am_support(load, ia32_am_Source);
1922 set_ia32_op_type(load, ia32_AddrModeS);
1923 set_ia32_am_flavour(load, ia32_B);
1924 set_ia32_ls_mode(load, tgt_mode);
1926 return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
1930 * Create a conversion from x87 state register to general purpose.
1932 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1933 ia32_code_gen_t *cg = env->cg;
1934 entity *ent = cg->gp_to_fp;
1935 ir_graph *irg = env->irg;
1936 ir_node *block = env->block;
1937 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1938 ir_node *nomem = get_irg_no_mem(irg);
1939 ir_node *op = get_Conv_op(env->irn);
1940 ir_node *fild, *store, *mem;
1944 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
1945 ent = cg->gp_to_fp =
1946 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
1949 /* first convert to 32 bit */
1950 src_bits = get_mode_size_bits(src_mode);
1951 if (src_bits == 8) {
1952 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
1953 op = new_r_Proj(irg, block, op, mode_Is, 0);
1955 else if (src_bits < 32) {
1956 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
1957 op = new_r_Proj(irg, block, op, mode_Is, 0);
1961 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
1963 set_ia32_frame_ent(store, ent);
1964 set_ia32_use_frame(store);
1966 set_ia32_am_support(store, ia32_am_Dest);
1967 set_ia32_op_type(store, ia32_AddrModeD);
1968 set_ia32_am_flavour(store, ia32_B);
1969 set_ia32_ls_mode(store, mode_Is);
1971 mem = new_r_Proj(irg, block, store, mode_M, 0);
1974 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1976 set_ia32_frame_ent(fild, ent);
1977 set_ia32_use_frame(fild);
1978 set_ia32_am_support(fild, ia32_am_Source);
1979 set_ia32_op_type(fild, ia32_AddrModeS);
1980 set_ia32_am_flavour(fild, ia32_B);
1981 set_ia32_ls_mode(fild, mode_F);
1983 return new_r_Proj(irg, block, fild, mode_F, 0);
1987 * Transforms a Conv node.
1989 * @param env The transformation environment
1990 * @return The created ia32 Conv node
1992 static ir_node *gen_Conv(ia32_transform_env_t *env) {
1993 dbg_info *dbg = env->dbg;
1994 ir_graph *irg = env->irg;
1995 ir_node *op = get_Conv_op(env->irn);
1996 ir_mode *src_mode = get_irn_mode(op);
1997 ir_mode *tgt_mode = env->mode;
1998 int src_bits = get_mode_size_bits(src_mode);
1999 int tgt_bits = get_mode_size_bits(tgt_mode);
2002 ir_node *block = env->block;
2003 ir_node *new_op = NULL;
2004 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2005 ir_node *nomem = new_rd_NoMem(irg);
2007 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
2009 if (src_mode == tgt_mode) {
2010 /* this can happen when changing mode_P to mode_Is */
2011 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
2012 edges_reroute(env->irn, op, irg);
2014 else if (mode_is_float(src_mode)) {
2015 /* we convert from float ... */
2016 if (mode_is_float(tgt_mode)) {
2018 if (USE_SSE2(env->cg)) {
2019 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
2020 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
2021 pn = pn_ia32_Conv_FP2FP_res;
2024 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
2026 remark: we create a intermediate conv here, so modes will be spread correctly
2027 these convs will be killed later
2029 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
2030 pn = pn_ia32_Conv_FP2FP_res;
2036 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
2037 if (USE_SSE2(env->cg)) {
2038 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
2039 pn = pn_ia32_Conv_FP2I_res;
2042 return gen_x87_fp_to_gp(env, tgt_mode);
2044 /* if target mode is not int: add an additional downscale convert */
2045 if (tgt_bits < 32) {
2046 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2047 set_ia32_am_support(new_op, ia32_am_Source);
2048 set_ia32_tgt_mode(new_op, tgt_mode);
2049 set_ia32_src_mode(new_op, src_mode);
2051 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, pn_ia32_Conv_FP2I_res);
2053 if (tgt_bits == 8 || src_bits == 8) {
2054 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
2055 pn = pn_ia32_Conv_I2I8Bit_res;
2058 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
2059 pn = pn_ia32_Conv_I2I_res;
2065 /* we convert from int ... */
2066 if (mode_is_float(tgt_mode)) {
2069 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
2070 if (USE_SSE2(env->cg)) {
2071 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
2072 pn = pn_ia32_Conv_I2FP_res;
2075 return gen_x87_gp_to_fp(env, src_mode);
2079 if (get_mode_size_bits(src_mode) == tgt_bits) {
2080 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
2082 remark: we create a intermediate conv here, so modes will be spread correctly
2083 these convs will be killed later
2085 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
2086 pn = pn_ia32_Conv_I2I_res;
2090 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2091 if (tgt_bits == 8 || src_bits == 8) {
2092 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
2093 pn = pn_ia32_Conv_I2I8Bit_res;
2096 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
2097 pn = pn_ia32_Conv_I2I_res;
2104 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2105 set_ia32_tgt_mode(new_op, tgt_mode);
2106 set_ia32_src_mode(new_op, src_mode);
2108 set_ia32_am_support(new_op, ia32_am_Source);
2110 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, pn);
2113 nodeset_insert(env->cg->kill_conv, new_op);
2121 /********************************************
2124 * | |__ ___ _ __ ___ __| | ___ ___
2125 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2126 * | |_) | __/ | | | (_) | (_| | __/\__ \
2127 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2129 ********************************************/
2132 * Decides in which block the transformed StackParam should be placed.
2133 * If the StackParam has more than one user, the dominator block of
2134 * the users will be returned. In case of only one user, this is either
2135 * the user block or, in case of a Phi, the predecessor block of the Phi.
2137 static ir_node *get_block_transformed_stack_param(ir_node *irn) {
2138 ir_node *dom_bl = NULL;
2140 if (get_irn_n_edges(irn) == 1) {
2141 ir_node *src = get_edge_src_irn(get_irn_out_edge_first(irn));
2143 if (! is_Phi(src)) {
2144 dom_bl = get_nodes_block(src);
2147 /* Determine on which in position of the Phi the irn is */
2148 /* and get the corresponding cfg predecessor block. */
2150 int i = get_irn_pred_pos(src, irn);
2151 assert(i >= 0 && "kaputt");
2152 dom_bl = get_Block_cfgpred_block(get_nodes_block(src), i);
2156 dom_bl = node_users_smallest_common_dominator(irn, 1);
2159 assert(dom_bl && "dominator block not found");
2164 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
2165 ir_node *new_op = NULL;
2166 ir_node *node = env->irn;
2167 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2168 ir_node *mem = new_rd_NoMem(env->irg);
2169 ir_node *ptr = get_irn_n(node, 0);
2170 entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2171 ir_mode *mode = env->mode;
2173 /* choose the block where to place the load */
2174 env->block = get_block_transformed_stack_param(node);
2176 if (mode_is_float(mode)) {
2178 if (USE_SSE2(env->cg))
2179 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2181 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2184 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2187 set_ia32_frame_ent(new_op, ent);
2188 set_ia32_use_frame(new_op);
2190 set_ia32_am_support(new_op, ia32_am_Source);
2191 set_ia32_op_type(new_op, ia32_AddrModeS);
2192 set_ia32_am_flavour(new_op, ia32_B);
2193 set_ia32_ls_mode(new_op, mode);
2194 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2196 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2198 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
2202 * Transforms a FrameAddr into an ia32 Add.
2204 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
2205 ir_node *new_op = NULL;
2206 ir_node *node = env->irn;
2207 ir_node *op = get_irn_n(node, 0);
2208 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2209 ir_node *nomem = new_rd_NoMem(env->irg);
2211 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
2212 set_ia32_frame_ent(new_op, arch_get_frame_entity(env->cg->arch_env, node));
2213 set_ia32_am_support(new_op, ia32_am_Full);
2214 set_ia32_use_frame(new_op);
2215 set_ia32_immop_type(new_op, ia32_ImmConst);
2216 set_ia32_commutative(new_op);
2218 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2220 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
2224 * Transforms a FrameLoad into an ia32 Load.
2226 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
2227 ir_node *new_op = NULL;
2228 ir_node *node = env->irn;
2229 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2230 ir_node *mem = get_irn_n(node, 0);
2231 ir_node *ptr = get_irn_n(node, 1);
2232 entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2233 ir_mode *mode = get_type_mode(get_entity_type(ent));
2235 if (mode_is_float(mode)) {
2237 if (USE_SSE2(env->cg))
2238 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2240 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2243 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2245 set_ia32_frame_ent(new_op, ent);
2246 set_ia32_use_frame(new_op);
2248 set_ia32_am_support(new_op, ia32_am_Source);
2249 set_ia32_op_type(new_op, ia32_AddrModeS);
2250 set_ia32_am_flavour(new_op, ia32_B);
2251 set_ia32_ls_mode(new_op, mode);
2253 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2260 * Transforms a FrameStore into an ia32 Store.
2262 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
2263 ir_node *new_op = NULL;
2264 ir_node *node = env->irn;
2265 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2266 ir_node *mem = get_irn_n(node, 0);
2267 ir_node *ptr = get_irn_n(node, 1);
2268 ir_node *val = get_irn_n(node, 2);
2269 entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2270 ir_mode *mode = get_irn_mode(val);
2272 if (mode_is_float(mode)) {
2274 if (USE_SSE2(env->cg))
2275 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2277 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2279 else if (get_mode_size_bits(mode) == 8) {
2280 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2283 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2286 set_ia32_frame_ent(new_op, ent);
2287 set_ia32_use_frame(new_op);
2289 set_ia32_am_support(new_op, ia32_am_Dest);
2290 set_ia32_op_type(new_op, ia32_AddrModeD);
2291 set_ia32_am_flavour(new_op, ia32_B);
2292 set_ia32_ls_mode(new_op, mode);
2294 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2300 * In case SSE is used we need to copy the result from FPU TOS.
2302 static ir_node *gen_be_Call(ia32_transform_env_t *env) {
2303 ir_node *call_res = get_proj_for_pn(env->irn, pn_be_Call_first_res);
2304 ir_node *call_mem = get_proj_for_pn(env->irn, pn_be_Call_M_regular);
2307 if (! call_res || ! USE_SSE2(env->cg))
2310 mode = get_irn_mode(call_res);
2312 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
2314 call_mem = new_r_Proj(env->irg, env->block, env->irn, mode_M, pn_be_Call_M_regular);
2316 if (mode_is_float(mode)) {
2317 /* store st(0) onto stack */
2318 ir_node *frame = get_irg_frame(env->irg);
2319 ir_node *fstp = new_rd_ia32_GetST0(env->dbg, env->irg, env->block, frame, call_mem);
2320 ir_node *mproj = new_r_Proj(env->irg, env->block, fstp, mode_M, pn_ia32_GetST0_M);
2321 entity *ent = frame_alloc_area(get_irg_frame_type(env->irg), get_mode_size_bytes(mode), 16, 0);
2324 set_ia32_ls_mode(fstp, mode);
2325 set_ia32_op_type(fstp, ia32_AddrModeD);
2326 set_ia32_use_frame(fstp);
2327 set_ia32_frame_ent(fstp, ent);
2328 set_ia32_am_flavour(fstp, ia32_B);
2329 set_ia32_am_support(fstp, ia32_am_Dest);
2331 /* load into SSE register */
2332 sse_load = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, frame, ia32_new_NoReg_gp(env->cg), mproj);
2333 set_ia32_ls_mode(sse_load, mode);
2334 set_ia32_op_type(sse_load, ia32_AddrModeS);
2335 set_ia32_use_frame(sse_load);
2336 set_ia32_frame_ent(sse_load, ent);
2337 set_ia32_am_flavour(sse_load, ia32_B);
2338 set_ia32_am_support(sse_load, ia32_am_Source);
2339 sse_load = new_r_Proj(env->irg, env->block, sse_load, mode, pn_ia32_xLoad_res);
2341 /* reroute all users of the result proj to the sse load */
2342 edges_reroute(call_res, sse_load, env->irg);
2349 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2351 static ir_node *gen_be_Return(ia32_transform_env_t *env) {
2352 ir_node *ret_val = get_irn_n(env->irn, be_pos_Return_val);
2353 ir_node *ret_mem = get_irn_n(env->irn, be_pos_Return_mem);
2354 entity *ent = get_irg_entity(get_irn_irg(ret_val));
2355 ir_type *tp = get_entity_type(ent);
2357 if (be_Return_get_n_rets(env->irn) < 1 || ! ret_val || ! USE_SSE2(env->cg))
2361 if (get_method_n_ress(tp) == 1) {
2362 ir_type *res_type = get_method_res_type(tp, 0);
2365 if(is_Primitive_type(res_type)) {
2366 mode = get_type_mode(res_type);
2367 if(mode_is_float(mode)) {
2368 ir_node *frame = get_irg_frame(env->irg);
2369 entity *ent = frame_alloc_area(get_irg_frame_type(env->irg), get_mode_size_bytes(mode), 16, 0);
2370 ir_node *sse_store, *fld, *mproj;
2372 /* store xmm0 onto stack */
2373 sse_store = new_rd_ia32_xStoreSimple(env->dbg, env->irg, env->block, frame, ret_val, ret_mem);
2374 set_ia32_ls_mode(sse_store, mode);
2375 set_ia32_op_type(sse_store, ia32_AddrModeD);
2376 set_ia32_use_frame(sse_store);
2377 set_ia32_frame_ent(sse_store, ent);
2378 set_ia32_am_flavour(sse_store, ia32_B);
2379 set_ia32_am_support(sse_store, ia32_am_Dest);
2380 sse_store = new_r_Proj(env->irg, env->block, sse_store, mode_M, pn_ia32_xStore_M);
2383 fld = new_rd_ia32_SetST0(env->dbg, env->irg, env->block, frame, sse_store);
2384 set_ia32_ls_mode(fld, mode);
2385 set_ia32_op_type(fld, ia32_AddrModeS);
2386 set_ia32_use_frame(fld);
2387 set_ia32_frame_ent(fld, ent);
2388 set_ia32_am_flavour(fld, ia32_B);
2389 set_ia32_am_support(fld, ia32_am_Source);
2390 mproj = new_r_Proj(env->irg, env->block, fld, mode_M, pn_ia32_SetST0_M);
2391 fld = new_r_Proj(env->irg, env->block, fld, mode, pn_ia32_SetST0_res);
2393 /* set new return value */
2394 set_irn_n(env->irn, be_pos_Return_val, fld);
2395 set_irn_n(env->irn, be_pos_Return_mem, mproj);
2404 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2406 static ir_node *gen_be_AddSP(ia32_transform_env_t *env) {
2408 const ir_edge_t *edge;
2409 ir_node *sz = get_irn_n(env->irn, be_pos_AddSP_size);
2410 ir_node *sp = get_irn_n(env->irn, be_pos_AddSP_old_sp);
2412 new_op = new_rd_ia32_AddSP(env->dbg, env->irg, env->block, sp, sz);
2414 if (is_ia32_Const(sz)) {
2415 set_ia32_Immop_attr(new_op, sz);
2416 set_irn_n(new_op, 1, ia32_new_NoReg_gp(env->cg));
2418 else if (is_ia32_Load(sz) && get_ia32_am_flavour(sz) == ia32_O) {
2419 set_ia32_immop_type(new_op, ia32_ImmSymConst);
2420 set_ia32_op_type(new_op, ia32_AddrModeS);
2421 set_ia32_am_sc(new_op, get_ia32_am_sc(sz));
2422 add_ia32_am_offs(new_op, get_ia32_am_offs(sz));
2423 set_irn_n(new_op, 1, ia32_new_NoReg_gp(env->cg));
2427 foreach_out_edge(env->irn, edge) {
2428 ir_node *proj = get_edge_src_irn(edge);
2430 assert(is_Proj(proj));
2432 if (get_Proj_proj(proj) == pn_be_AddSP_res) {
2433 /* the node is not yet exchanged: we need to set the register manually */
2434 ia32_attr_t *attr = get_ia32_attr(new_op);
2435 attr->slots[pn_ia32_AddSP_stack] = &ia32_gp_regs[REG_ESP];
2436 set_Proj_proj(proj, pn_ia32_AddSP_stack);
2438 else if (get_Proj_proj(proj) == pn_be_AddSP_M) {
2439 set_Proj_proj(proj, pn_ia32_AddSP_M);
2446 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2452 * This function just sets the register for the Unknown node
2453 * as this is not done during register allocation because Unknown
2454 * is an "ignore" node.
2456 static ir_node *gen_Unknown(ia32_transform_env_t *env) {
2457 ir_mode *mode = env->mode;
2458 ir_node *irn = env->irn;
2460 if (mode_is_float(mode)) {
2461 if (USE_SSE2(env->cg))
2462 arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
2464 arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
2466 else if (mode_is_int(mode) || mode_is_reference(mode)) {
2467 arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
2470 assert(0 && "unsupported Unknown-Mode");
2476 /**********************************************************************
2479 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2480 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2481 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2482 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2484 **********************************************************************/
2486 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2488 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2491 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2492 ir_node *val, ir_node *mem);
2495 * Transforms a lowered Load into a "real" one.
2497 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, construct_load_func func, char fp_unit) {
2498 ir_node *node = env->irn;
2499 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2500 ir_mode *mode = get_ia32_ls_mode(node);
2503 ia32_am_flavour_t am_flav = ia32_B;
2506 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2507 lowering we have x87 nodes, so we need to enforce simulation.
2509 if (mode_is_float(mode)) {
2511 if (fp_unit == fp_x87)
2515 new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1));
2516 am_offs = get_ia32_am_offs(node);
2520 add_ia32_am_offs(new_op, am_offs);
2523 set_ia32_am_support(new_op, ia32_am_Source);
2524 set_ia32_op_type(new_op, ia32_AddrModeS);
2525 set_ia32_am_flavour(new_op, am_flav);
2526 set_ia32_ls_mode(new_op, mode);
2527 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2528 set_ia32_use_frame(new_op);
2530 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2536 * Transforms a lowered Store into a "real" one.
2538 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, construct_store_func func, char fp_unit) {
2539 ir_node *node = env->irn;
2540 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2541 ir_mode *mode = get_ia32_ls_mode(node);
2544 ia32_am_flavour_t am_flav = ia32_B;
2547 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2548 lowering we have x87 nodes, so we need to enforce simulation.
2550 if (mode_is_float(mode)) {
2552 if (fp_unit == fp_x87)
2556 new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1), get_irn_n(node, 2));
2558 if ((am_offs = get_ia32_am_offs(node)) != NULL) {
2560 add_ia32_am_offs(new_op, am_offs);
2563 set_ia32_am_support(new_op, ia32_am_Dest);
2564 set_ia32_op_type(new_op, ia32_AddrModeD);
2565 set_ia32_am_flavour(new_op, am_flav);
2566 set_ia32_ls_mode(new_op, mode);
2567 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2568 set_ia32_use_frame(new_op);
2570 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2577 * Transforms an ia32_l_XXX into a "real" XXX node
2579 * @param env The transformation environment
2580 * @return the created ia32 XXX node
2582 #define GEN_LOWERED_OP(op) \
2583 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2584 if (mode_is_float(env->mode)) \
2586 return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2589 #define GEN_LOWERED_x87_OP(op) \
2590 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2592 FORCE_x87(env->cg); \
2593 new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2594 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_None); \
2598 #define GEN_LOWERED_UNOP(op) \
2599 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2600 return gen_unop(env, get_unop_op(env->irn), new_rd_ia32_##op); \
2603 #define GEN_LOWERED_SHIFT_OP(op) \
2604 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2605 return gen_shift_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2608 #define GEN_LOWERED_LOAD(op, fp_unit) \
2609 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2610 return gen_lowered_Load(env, new_rd_ia32_##op, fp_unit); \
2613 #define GEN_LOWERED_STORE(op, fp_unit) \
2614 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2615 return gen_lowered_Store(env, new_rd_ia32_##op, fp_unit); \
2618 GEN_LOWERED_OP(AddC)
2620 GEN_LOWERED_OP(SubC)
2624 GEN_LOWERED_x87_OP(vfdiv)
2625 GEN_LOWERED_x87_OP(vfmul)
2626 GEN_LOWERED_x87_OP(vfsub)
2628 GEN_LOWERED_UNOP(Minus)
2630 GEN_LOWERED_LOAD(vfild, fp_x87)
2631 GEN_LOWERED_LOAD(Load, fp_none)
2632 GEN_LOWERED_STORE(vfist, fp_x87)
2633 GEN_LOWERED_STORE(Store, fp_none)
2636 * Transforms a l_MulS into a "real" MulS node.
2638 * @param env The transformation environment
2639 * @return the created ia32 MulS node
2641 static ir_node *gen_ia32_l_MulS(ia32_transform_env_t *env) {
2643 /* l_MulS is already a mode_T node, so we create the MulS in the normal way */
2644 /* and then skip the result Proj, because all needed Projs are already there. */
2646 ir_node *new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_MulS);
2647 ir_node *muls = get_Proj_pred(new_op);
2649 /* MulS cannot have AM for destination */
2650 if (get_ia32_am_support(muls) != ia32_am_None)
2651 set_ia32_am_support(muls, ia32_am_Source);
2656 GEN_LOWERED_SHIFT_OP(Shl)
2657 GEN_LOWERED_SHIFT_OP(Shr)
2658 GEN_LOWERED_SHIFT_OP(Shrs)
2661 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
2662 * op1 - target to be shifted
2663 * op2 - contains bits to be shifted into target
2665 * Only op3 can be an immediate.
2667 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, ir_node *count) {
2668 ir_node *new_op = NULL;
2669 ir_mode *mode = env->mode;
2670 dbg_info *dbg = env->dbg;
2671 ir_graph *irg = env->irg;
2672 ir_node *block = env->block;
2673 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2674 ir_node *nomem = new_NoMem();
2677 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
2679 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
2681 /* Check if immediate optimization is on and */
2682 /* if it's an operation with immediate. */
2683 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, count) : NULL;
2685 /* Limit imm_op within range imm8 */
2687 tv = get_ia32_Immop_tarval(imm_op);
2690 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
2691 set_ia32_Immop_tarval(imm_op, tv);
2698 /* integer operations */
2700 /* This is ShiftD with const */
2701 DB((mod, LEVEL_1, "ShiftD with immediate ..."));
2703 if (is_ia32_l_ShlD(env->irn))
2704 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, op1, op2, noreg, nomem);
2706 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, op1, op2, noreg, nomem);
2707 set_ia32_Immop_attr(new_op, imm_op);
2710 /* This is a normal ShiftD */
2711 DB((mod, LEVEL_1, "ShiftD binop ..."));
2712 if (is_ia32_l_ShlD(env->irn))
2713 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, op1, op2, count, nomem);
2715 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, op1, op2, count, nomem);
2718 /* set AM support */
2719 set_ia32_am_support(new_op, ia32_am_Dest);
2721 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2723 set_ia32_res_mode(new_op, mode);
2724 set_ia32_emit_cl(new_op);
2726 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
2729 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env) {
2730 return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2));
2733 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env) {
2734 return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2));
2738 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
2740 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env) {
2741 ia32_code_gen_t *cg = env->cg;
2742 ir_node *res = NULL;
2743 ir_node *ptr = get_irn_n(env->irn, 0);
2744 ir_node *val = get_irn_n(env->irn, 1);
2745 ir_node *mem = get_irn_n(env->irn, 2);
2748 ir_node *noreg = ia32_new_NoReg_gp(cg);
2750 /* Store x87 -> MEM */
2751 res = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2752 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2753 set_ia32_use_frame(res);
2754 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2755 set_ia32_am_support(res, ia32_am_Dest);
2756 set_ia32_am_flavour(res, ia32_B);
2757 res = new_rd_Proj(env->dbg, env->irg, env->block, res, mode_M, pn_ia32_vfst_M);
2759 /* Load MEM -> SSE */
2760 res = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, res);
2761 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2762 set_ia32_use_frame(res);
2763 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2764 set_ia32_am_support(res, ia32_am_Source);
2765 set_ia32_am_flavour(res, ia32_B);
2766 res = new_rd_Proj(env->dbg, env->irg, env->block, res, get_ia32_ls_mode(env->irn), pn_ia32_xLoad_res);
2769 /* SSE unit is not used -> skip this node. */
2772 edges_reroute(env->irn, val, env->irg);
2773 for (i = get_irn_arity(env->irn) - 1; i >= 0; i--)
2774 set_irn_n(env->irn, i, get_irg_bad(env->irg));
2781 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
2783 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env) {
2784 ia32_code_gen_t *cg = env->cg;
2785 ir_node *res = NULL;
2786 ir_node *ptr = get_irn_n(env->irn, 0);
2787 ir_node *val = get_irn_n(env->irn, 1);
2788 ir_node *mem = get_irn_n(env->irn, 2);
2791 ir_node *noreg = ia32_new_NoReg_gp(cg);
2793 /* Store SSE -> MEM */
2794 res = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2795 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2796 set_ia32_use_frame(res);
2797 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2798 set_ia32_am_support(res, ia32_am_Dest);
2799 set_ia32_am_flavour(res, ia32_B);
2800 res = new_rd_Proj(env->dbg, env->irg, env->block, res, mode_M, pn_ia32_xStore_M);
2802 /* Load MEM -> x87 */
2803 res = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2804 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2805 set_ia32_use_frame(res);
2806 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2807 set_ia32_am_support(res, ia32_am_Source);
2808 set_ia32_am_flavour(res, ia32_B);
2809 res = new_rd_Proj(env->dbg, env->irg, env->block, res, get_ia32_ls_mode(env->irn), pn_ia32_vfld_res);
2812 /* SSE unit is not used -> skip this node. */
2815 edges_reroute(env->irn, val, env->irg);
2816 for (i = get_irn_arity(env->irn) - 1; i >= 0; i--)
2817 set_irn_n(env->irn, i, get_irg_bad(env->irg));
2823 /*********************************************************
2826 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
2827 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
2828 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
2829 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
2831 *********************************************************/
2834 * the BAD transformer.
2836 static ir_node *bad_transform(ia32_transform_env_t *env) {
2837 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2843 * Enters all transform functions into the generic pointer
2845 void ia32_register_transformers(void) {
2846 ir_op *op_Max, *op_Min, *op_Mulh;
2848 /* first clear the generic function pointer for all ops */
2849 clear_irp_opcodes_generic_func();
2851 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2852 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
2886 /* transform ops from intrinsic lowering */
2907 GEN(ia32_l_X87toSSE);
2908 GEN(ia32_l_SSEtoX87);
2923 /* constant transformation happens earlier */
2928 /* we should never see these nodes */
2943 /* handle generic backend nodes */
2952 /* set the register for all Unknown nodes */
2955 op_Max = get_op_Max();
2958 op_Min = get_op_Min();
2961 op_Mulh = get_op_Mulh();
2970 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
2973 * Transforms the given firm node (and maybe some other related nodes)
2974 * into one or more assembler nodes.
2976 * @param node the firm node
2977 * @param env the debug module
2979 void ia32_transform_node(ir_node *node, void *env) {
2980 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2981 ir_op *op = get_irn_op(node);
2982 ir_node *asm_node = NULL;
2988 /* link arguments pointing to Unknown to the UNKNOWN Proj */
2989 for (i = get_irn_arity(node) - 1; i >= 0; i--) {
2990 if (is_Unknown(get_irn_n(node, i)))
2991 set_irn_n(node, i, be_get_unknown_for_mode(cg, get_irn_mode(get_irn_n(node, i))));
2994 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
2995 if (op->ops.generic) {
2996 ia32_transform_env_t tenv;
2997 transform_func *transform = (transform_func *)op->ops.generic;
2999 tenv.block = get_nodes_block(node);
3000 tenv.dbg = get_irn_dbg_info(node);
3001 tenv.irg = current_ir_graph;
3003 tenv.mode = get_irn_mode(node);
3005 DEBUG_ONLY(tenv.mod = cg->mod;)
3007 asm_node = (*transform)(&tenv);
3010 /* exchange nodes if a new one was generated */
3012 exchange(node, asm_node);
3013 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
3016 DB((cg->mod, LEVEL_1, "ignored\n"));
3021 * Transforms a psi condition.
3023 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
3026 /* if the mode is target mode, we have already seen this part of the tree */
3027 if (get_irn_mode(cond) == mode)
3030 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
3032 set_irn_mode(cond, mode);
3034 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
3035 ir_node *in = get_irn_n(cond, i);
3037 /* if in is a compare: transform into Set/xCmp */
3039 ir_node *new_op = NULL;
3040 ir_node *cmp = get_Proj_pred(in);
3041 ir_node *cmp_a = get_Cmp_left(cmp);
3042 ir_node *cmp_b = get_Cmp_right(cmp);
3043 dbg_info *dbg = get_irn_dbg_info(cmp);
3044 ir_graph *irg = get_irn_irg(cmp);
3045 ir_node *block = get_nodes_block(cmp);
3046 ir_node *noreg = ia32_new_NoReg_gp(cg);
3047 ir_node *nomem = new_rd_NoMem(irg);
3048 int pnc = get_Proj_proj(in);
3050 /* this is a compare */
3051 if (mode_is_float(mode)) {
3052 /* Psi is float, we need a floating point compare */
3056 if (! mode_is_float(get_irn_mode(cmp_a))) {
3057 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
3058 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
3062 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
3063 set_ia32_pncode(new_op, pnc);
3064 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
3073 ia32_transform_env_t tenv;
3074 construct_binop_func *set_func = NULL;
3076 if (mode_is_float(get_irn_mode(cmp_a))) {
3077 /* 1st case: compare operands are floats */
3082 set_func = new_rd_ia32_xCmpSet;
3086 set_func = new_rd_ia32_vfCmpSet;
3089 pnc &= 7; /* fp compare -> int compare */
3092 /* 2nd case: compare operand are integer too */
3093 set_func = new_rd_ia32_CmpSet;
3104 new_op = gen_binop(&tenv, cmp_a, cmp_b, set_func);
3105 set_ia32_pncode(get_Proj_pred(new_op), pnc);
3106 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
3109 /* the the new compare as in */
3110 set_irn_n(cond, i, new_op);
3113 /* another complex condition */
3114 transform_psi_cond(in, mode, cg);
3120 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
3121 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
3122 * compare, which causes the compare result to be stores in a register. The
3123 * "And"s and "Or"s are transformed later, we just have to set their mode right.
3125 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
3126 ia32_code_gen_t *cg = env;
3127 ir_node *psi_sel, *new_cmp, *block;
3132 if (get_irn_opcode(node) != iro_Psi)
3135 psi_sel = get_Psi_cond(node, 0);
3137 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
3138 if (is_Proj(psi_sel))
3141 mode = get_irn_mode(node);
3143 transform_psi_cond(psi_sel, mode, cg);
3145 irg = get_irn_irg(node);
3146 block = get_nodes_block(node);
3148 /* we need to compare the evaluated condition tree with 0 */
3150 /* BEWARE: new_r_Const_long works for floating point as well */
3151 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
3152 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne + (mode_is_float(mode) ? pn_Cmp_Uo : 0));
3154 set_Psi_cond(node, 0, new_cmp);