2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
98 static transform_config_t transform_config;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
108 ir_node *op1, ir_node *op2, ir_node *flags);
110 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *op1, ir_node *op2);
113 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
118 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
120 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
122 ir_node *op1, ir_node *op2, ir_node *fpcw);
124 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
125 ir_node *block, ir_node *op);
127 /****************************************************************************************************
129 * | | | | / _| | | (_)
130 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
131 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
132 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
133 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
135 ****************************************************************************************************/
137 static ir_node *try_create_Immediate(ir_node *node,
138 char immediate_constraint_type);
140 static ir_node *create_immediate_or_transform(ir_node *node,
141 char immediate_constraint_type);
143 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
144 dbg_info *dbgi, ir_node *block,
145 ir_node *op, ir_node *orig_node);
148 * Return true if a mode can be stored in the GP register set
150 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
151 if(mode == mode_fpcw)
153 if(get_mode_size_bits(mode) > 32)
155 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
159 * creates a unique ident by adding a number to a tag
161 * @param tag the tag string, must contain a %d if a number
164 static ident *unique_id(const char *tag)
166 static unsigned id = 0;
169 snprintf(str, sizeof(str), tag, ++id);
170 return new_id_from_str(str);
174 * Get a primitive type for a mode.
176 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
178 pmap_entry *e = pmap_find(types, mode);
183 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
184 res = new_type_primitive(new_id_from_str(buf), mode);
185 set_type_alignment_bytes(res, 16);
186 pmap_insert(types, mode, res);
194 * Get an atomic entity that is initialized with a tarval
196 static ir_entity *create_float_const_entity(ir_node *cnst)
198 ia32_isa_t *isa = env_cg->isa;
199 tarval *tv = get_Const_tarval(cnst);
200 pmap_entry *e = pmap_find(isa->tv_ent, tv);
205 ir_mode *mode = get_irn_mode(cnst);
206 ir_type *tp = get_Const_type(cnst);
207 if (tp == firm_unknown_type)
208 tp = get_prim_type(isa->types, mode);
210 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
212 set_entity_ld_ident(res, get_entity_ident(res));
213 set_entity_visibility(res, visibility_local);
214 set_entity_variability(res, variability_constant);
215 set_entity_allocation(res, allocation_static);
217 /* we create a new entity here: It's initialization must resist on the
219 rem = current_ir_graph;
220 current_ir_graph = get_const_code_irg();
221 set_atomic_ent_value(res, new_Const_type(tv, tp));
222 current_ir_graph = rem;
224 pmap_insert(isa->tv_ent, tv, res);
232 static int is_Const_0(ir_node *node) {
233 return is_Const(node) && is_Const_null(node);
236 static int is_Const_1(ir_node *node) {
237 return is_Const(node) && is_Const_one(node);
240 static int is_Const_Minus_1(ir_node *node) {
241 return is_Const(node) && is_Const_all_one(node);
245 * returns true if constant can be created with a simple float command
247 static int is_simple_x87_Const(ir_node *node)
249 tarval *tv = get_Const_tarval(node);
251 if(tarval_is_null(tv) || tarval_is_one(tv))
254 /* TODO: match all the other float constants */
259 * Transforms a Const.
261 static ir_node *gen_Const(ir_node *node) {
262 ir_graph *irg = current_ir_graph;
263 ir_node *old_block = get_nodes_block(node);
264 ir_node *block = be_transform_node(old_block);
265 dbg_info *dbgi = get_irn_dbg_info(node);
266 ir_mode *mode = get_irn_mode(node);
268 if (mode_is_float(mode)) {
270 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
271 ir_node *nomem = new_NoMem();
275 if (USE_SSE2(env_cg)) {
276 if (is_Const_null(node)) {
277 load = new_rd_ia32_xZero(dbgi, irg, block);
278 set_ia32_ls_mode(load, mode);
281 floatent = create_float_const_entity(node);
283 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
285 set_ia32_op_type(load, ia32_AddrModeS);
286 set_ia32_am_sc(load, floatent);
287 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
288 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
291 if (is_Const_null(node)) {
292 load = new_rd_ia32_vfldz(dbgi, irg, block);
294 } else if (is_Const_one(node)) {
295 load = new_rd_ia32_vfld1(dbgi, irg, block);
298 floatent = create_float_const_entity(node);
300 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
301 set_ia32_op_type(load, ia32_AddrModeS);
302 set_ia32_am_sc(load, floatent);
303 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
304 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
306 set_ia32_ls_mode(load, mode);
309 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
311 /* Const Nodes before the initial IncSP are a bad idea, because
312 * they could be spilled and we have no SP ready at that point yet.
313 * So add a dependency to the initial frame pointer calculation to
314 * avoid that situation.
316 if (get_irg_start_block(irg) == block) {
317 add_irn_dep(load, get_irg_frame(irg));
320 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
324 tarval *tv = get_Const_tarval(node);
327 tv = tarval_convert_to(tv, mode_Iu);
329 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
331 panic("couldn't convert constant tarval (%+F)", node);
333 val = get_tarval_long(tv);
335 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
339 if (get_irg_start_block(irg) == block) {
340 add_irn_dep(cnst, get_irg_frame(irg));
348 * Transforms a SymConst.
350 static ir_node *gen_SymConst(ir_node *node) {
351 ir_graph *irg = current_ir_graph;
352 ir_node *old_block = get_nodes_block(node);
353 ir_node *block = be_transform_node(old_block);
354 dbg_info *dbgi = get_irn_dbg_info(node);
355 ir_mode *mode = get_irn_mode(node);
358 if (mode_is_float(mode)) {
359 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
360 ir_node *nomem = new_NoMem();
362 if (USE_SSE2(env_cg))
363 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
365 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
366 set_ia32_am_sc(cnst, get_SymConst_entity(node));
367 set_ia32_use_frame(cnst);
371 if(get_SymConst_kind(node) != symconst_addr_ent) {
372 panic("backend only support symconst_addr_ent (at %+F)", node);
374 entity = get_SymConst_entity(node);
375 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
378 /* Const Nodes before the initial IncSP are a bad idea, because
379 * they could be spilled and we have no SP ready at that point yet
381 if (get_irg_start_block(irg) == block) {
382 add_irn_dep(cnst, get_irg_frame(irg));
385 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
390 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
391 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
392 static const struct {
394 const char *ent_name;
395 const char *cnst_str;
398 } names [ia32_known_const_max] = {
399 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
400 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
401 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
402 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
403 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
405 static ir_entity *ent_cache[ia32_known_const_max];
407 const char *tp_name, *ent_name, *cnst_str;
415 ent_name = names[kct].ent_name;
416 if (! ent_cache[kct]) {
417 tp_name = names[kct].tp_name;
418 cnst_str = names[kct].cnst_str;
420 switch (names[kct].mode) {
421 case 0: mode = mode_Iu; break;
422 case 1: mode = mode_Lu; break;
423 default: mode = mode_F; break;
425 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
426 tp = new_type_primitive(new_id_from_str(tp_name), mode);
427 /* set the specified alignment */
428 set_type_alignment_bytes(tp, names[kct].align);
430 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
432 set_entity_ld_ident(ent, get_entity_ident(ent));
433 set_entity_visibility(ent, visibility_local);
434 set_entity_variability(ent, variability_constant);
435 set_entity_allocation(ent, allocation_static);
437 /* we create a new entity here: It's initialization must resist on the
439 rem = current_ir_graph;
440 current_ir_graph = get_const_code_irg();
441 cnst = new_Const(mode, tv);
442 current_ir_graph = rem;
444 set_atomic_ent_value(ent, cnst);
446 /* cache the entry */
447 ent_cache[kct] = ent;
450 return ent_cache[kct];
455 * Prints the old node name on cg obst and returns a pointer to it.
457 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
458 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
460 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
461 obstack_1grow(isa->name_obst, 0);
462 return obstack_finish(isa->name_obst);
466 int use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
468 ir_mode *mode = get_irn_mode(node);
472 /* float constants are always available */
473 if(is_Const(node) && mode_is_float(mode)
474 && !is_simple_x87_Const(node) && get_irn_n_edges(node) == 1) {
480 load = get_Proj_pred(node);
481 pn = get_Proj_proj(node);
482 if(!is_Load(load) || pn != pn_Load_res)
484 if(get_nodes_block(load) != block)
486 /* we only use address mode if we're the only user of the load */
487 if(get_irn_n_edges(node) > 1)
490 if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
493 /* don't do AM if other node inputs depend on the load (via mem-proj) */
494 if(other != NULL && get_nodes_block(other) == block
495 && heights_reachable_in_block(heights, other, load))
501 typedef struct ia32_address_mode_t ia32_address_mode_t;
502 struct ia32_address_mode_t {
506 ia32_op_type_t op_type;
514 static void build_address(ia32_address_mode_t *am, ir_node *node)
516 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
517 ia32_address_t *addr = &am->addr;
526 ir_entity *entity = create_float_const_entity(node);
527 addr->base = noreg_gp;
528 addr->index = noreg_gp;
529 addr->mem = new_NoMem();
530 addr->symconst_ent = entity;
532 am->ls_mode = get_irn_mode(node);
533 am->pinned = op_pin_state_floats;
537 load = get_Proj_pred(node);
538 ptr = get_Load_ptr(load);
539 mem = get_Load_mem(load);
540 new_mem = be_transform_node(mem);
541 am->pinned = get_irn_pinned(load);
542 am->ls_mode = get_Load_mode(load);
543 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
545 /* construct load address */
546 ia32_create_address_mode(addr, ptr, 0);
553 base = be_transform_node(base);
559 index = be_transform_node(index);
567 static void set_address(ir_node *node, ia32_address_t *addr)
569 set_ia32_am_scale(node, addr->scale);
570 set_ia32_am_sc(node, addr->symconst_ent);
571 set_ia32_am_offs_int(node, addr->offset);
572 if(addr->symconst_sign)
573 set_ia32_am_sc_sign(node);
575 set_ia32_use_frame(node);
576 set_ia32_frame_ent(node, addr->frame_entity);
579 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
581 set_address(node, &am->addr);
583 set_ia32_op_type(node, am->op_type);
584 set_ia32_ls_mode(node, am->ls_mode);
585 if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) {
586 set_irn_pinned(node, am->pinned);
589 set_ia32_commutative(node);
593 match_commutative = 1 << 0,
594 match_am_and_immediates = 1 << 1,
595 match_no_am = 1 << 2,
596 match_8_bit_am = 1 << 3,
597 match_16_bit_am = 1 << 4,
598 match_no_immediate = 1 << 5,
599 match_force_32bit_op = 1 << 6
602 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
603 ir_node *op1, ir_node *op2, match_flags_t flags)
605 ia32_address_t *addr = &am->addr;
606 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
609 ir_mode *mode = get_irn_mode(op2);
612 int use_am_and_immediates;
614 int mode_bits = get_mode_size_bits(mode);
616 memset(am, 0, sizeof(am[0]));
618 commutative = (flags & match_commutative) != 0;
619 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
620 use_am = ! (flags & match_no_am);
621 use_immediate = !(flags & match_no_immediate);
624 assert(!commutative || op1 != NULL);
626 if(mode_bits == 8 && !(flags & match_8_bit_am)) {
628 } else if(mode_bits == 16 && !(flags & match_16_bit_am)) {
632 new_op2 = (use_immediate ? try_create_Immediate(op2, 0) : NULL);
633 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
634 build_address(am, op2);
635 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
636 if(mode_is_float(mode)) {
637 new_op2 = ia32_new_NoReg_vfp(env_cg);
641 am->op_type = ia32_AddrModeS;
642 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
643 use_am && use_source_address_mode(block, op1, op2)) {
645 build_address(am, op1);
647 if(mode_is_float(mode)) {
648 noreg = ia32_new_NoReg_vfp(env_cg);
653 if(new_op2 != NULL) {
656 new_op1 = be_transform_node(op2);
658 am->ins_permuted = 1;
660 am->op_type = ia32_AddrModeS;
662 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
664 new_op2 = be_transform_node(op2);
665 am->op_type = ia32_Normal;
666 if(flags & match_force_32bit_op) {
667 am->ls_mode = mode_Iu;
669 am->ls_mode = get_irn_mode(op2);
672 if(addr->base == NULL)
673 addr->base = noreg_gp;
674 if(addr->index == NULL)
675 addr->index = noreg_gp;
676 if(addr->mem == NULL)
677 addr->mem = new_NoMem();
679 am->new_op1 = new_op1;
680 am->new_op2 = new_op2;
681 am->commutative = commutative;
684 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
686 ir_graph *irg = current_ir_graph;
690 if(am->mem_proj == NULL)
693 /* we have to create a mode_T so the old MemProj can attach to us */
694 mode = get_irn_mode(node);
695 load = get_Proj_pred(am->mem_proj);
697 mark_irn_visited(load);
698 be_set_transformed_node(load, node);
701 set_irn_mode(node, mode_T);
702 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
709 * Construct a standard binary operation, set AM and immediate if required.
711 * @param op1 The first operand
712 * @param op2 The second operand
713 * @param func The node constructor function
714 * @return The constructed ia32 node.
716 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
717 construct_binop_func *func, match_flags_t flags)
719 ir_node *block = get_nodes_block(node);
720 ir_node *new_block = be_transform_node(block);
721 ir_graph *irg = current_ir_graph;
722 dbg_info *dbgi = get_irn_dbg_info(node);
724 ia32_address_mode_t am;
725 ia32_address_t *addr = &am.addr;
727 flags |= match_force_32bit_op;
729 match_arguments(&am, block, op1, op2, flags);
731 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
732 am.new_op1, am.new_op2);
733 set_am_attributes(new_node, &am);
734 /* we can't use source address mode anymore when using immediates */
735 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
736 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
737 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
739 new_node = fix_mem_proj(new_node, &am);
746 n_ia32_l_binop_right,
747 n_ia32_l_binop_eflags
749 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
750 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
751 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
752 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left)
753 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right)
754 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
757 * Construct a binary operation which also consumes the eflags.
759 * @param node The node to transform
760 * @param func The node constructor function
761 * @param flags The match flags
762 * @return The constructor ia32 node
764 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
767 ir_node *src_block = get_nodes_block(node);
768 ir_node *block = be_transform_node(src_block);
769 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
770 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
771 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
772 ir_node *new_eflags = be_transform_node(eflags);
773 ir_graph *irg = current_ir_graph;
774 dbg_info *dbgi = get_irn_dbg_info(node);
776 ia32_address_mode_t am;
777 ia32_address_t *addr = &am.addr;
779 match_arguments(&am, src_block, op1, op2, flags);
781 new_node = func(dbgi, irg, block, addr->base, addr->index,
782 addr->mem, am.new_op1, am.new_op2, new_eflags);
783 set_am_attributes(new_node, &am);
784 /* we can't use source address mode anymore when using immediates */
785 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
786 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
787 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
789 new_node = fix_mem_proj(new_node, &am);
795 * Construct a standard binary operation, set AM and immediate if required.
797 * @param op1 The first operand
798 * @param op2 The second operand
799 * @param func The node constructor function
800 * @return The constructed ia32 node.
802 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
803 construct_binop_func *func,
806 ir_node *block = get_nodes_block(node);
807 ir_node *new_block = be_transform_node(block);
808 dbg_info *dbgi = get_irn_dbg_info(node);
809 ir_graph *irg = current_ir_graph;
811 ia32_address_mode_t am;
812 ia32_address_t *addr = &am.addr;
814 match_arguments(&am, block, op1, op2, flags);
816 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
817 am.new_op1, am.new_op2);
818 set_am_attributes(new_node, &am);
820 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
822 new_node = fix_mem_proj(new_node, &am);
827 static ir_node *get_fpcw(void)
830 if(initial_fpcw != NULL)
833 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
834 &ia32_fp_cw_regs[REG_FPCW]);
835 initial_fpcw = be_transform_node(fpcw);
841 * Construct a standard binary operation, set AM and immediate if required.
843 * @param op1 The first operand
844 * @param op2 The second operand
845 * @param func The node constructor function
846 * @return The constructed ia32 node.
848 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
849 construct_binop_float_func *func,
852 ir_graph *irg = current_ir_graph;
853 dbg_info *dbgi = get_irn_dbg_info(node);
854 ir_node *block = get_nodes_block(node);
855 ir_node *new_block = be_transform_node(block);
857 ia32_address_mode_t am;
858 ia32_address_t *addr = &am.addr;
860 match_arguments(&am, block, op1, op2, flags);
862 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
863 am.new_op1, am.new_op2, get_fpcw());
864 set_am_attributes(new_node, &am);
866 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
868 new_node = fix_mem_proj(new_node, &am);
874 * Construct a shift/rotate binary operation, sets AM and immediate if required.
876 * @param op1 The first operand
877 * @param op2 The second operand
878 * @param func The node constructor function
879 * @return The constructed ia32 node.
881 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
882 construct_shift_func *func)
884 dbg_info *dbgi = get_irn_dbg_info(node);
885 ir_graph *irg = current_ir_graph;
886 ir_node *block = get_nodes_block(node);
887 ir_node *new_block = be_transform_node(block);
888 ir_node *new_op1 = be_transform_node(op1);
889 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
892 assert(! mode_is_float(get_irn_mode(node))
893 && "Shift/Rotate with float not supported");
895 new_node = func(dbgi, irg, new_block, new_op1, new_op2);
896 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
898 /* lowered shift instruction may have a dependency operand, handle it here */
899 if (get_irn_arity(node) == 3) {
900 /* we have a dependency */
901 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
902 add_irn_dep(new_node, new_dep);
910 * Construct a standard unary operation, set AM and immediate if required.
912 * @param op The operand
913 * @param func The node constructor function
914 * @return The constructed ia32 node.
916 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
918 ir_node *block = be_transform_node(get_nodes_block(node));
919 ir_node *new_op = be_transform_node(op);
920 ir_node *new_node = NULL;
921 ir_graph *irg = current_ir_graph;
922 dbg_info *dbgi = get_irn_dbg_info(node);
924 new_node = func(dbgi, irg, block, new_op);
926 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
931 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
932 ia32_address_t *addr)
934 ir_graph *irg = current_ir_graph;
935 ir_node *base = addr->base;
936 ir_node *index = addr->index;
940 base = ia32_new_NoReg_gp(env_cg);
942 base = be_transform_node(base);
946 index = ia32_new_NoReg_gp(env_cg);
948 index = be_transform_node(index);
951 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
952 set_address(res, addr);
957 static int am_has_immediates(const ia32_address_t *addr)
959 return addr->offset != 0 || addr->symconst_ent != NULL
960 || addr->frame_entity || addr->use_frame;
964 * Creates an ia32 Add.
966 * @return the created ia32 Add node
968 static ir_node *gen_Add(ir_node *node) {
969 ir_graph *irg = current_ir_graph;
970 dbg_info *dbgi = get_irn_dbg_info(node);
971 ir_node *block = get_nodes_block(node);
972 ir_node *new_block = be_transform_node(block);
973 ir_node *op1 = get_Add_left(node);
974 ir_node *op2 = get_Add_right(node);
975 ir_mode *mode = get_irn_mode(node);
976 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
979 ir_node *add_immediate_op;
981 ia32_address_mode_t am;
983 if (mode_is_float(mode)) {
984 if (USE_SSE2(env_cg))
985 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd, match_commutative);
987 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd, match_commutative);
992 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
993 * 1. Add with immediate -> Lea
994 * 2. Add with possible source address mode -> Add
995 * 3. Otherwise -> Lea
997 memset(&addr, 0, sizeof(addr));
998 ia32_create_address_mode(&addr, node, 1);
999 add_immediate_op = NULL;
1001 if(addr.base == NULL && addr.index == NULL) {
1002 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
1003 addr.symconst_sign, addr.offset);
1004 add_irn_dep(new_node, get_irg_frame(irg));
1005 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1008 /* add with immediate? */
1009 if(addr.index == NULL) {
1010 add_immediate_op = addr.base;
1011 } else if(addr.base == NULL && addr.scale == 0) {
1012 add_immediate_op = addr.index;
1015 if(add_immediate_op != NULL) {
1016 if(!am_has_immediates(&addr)) {
1017 #ifdef DEBUG_libfirm
1018 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1021 return be_transform_node(add_immediate_op);
1024 new_node = create_lea_from_address(dbgi, new_block, &addr);
1025 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1029 /* test if we can use source address mode */
1030 memset(&am, 0, sizeof(am));
1032 if(use_source_address_mode(block, op2, op1)) {
1033 build_address(&am, op2);
1034 new_op1 = be_transform_node(op1);
1035 } else if(use_source_address_mode(block, op1, op2)) {
1036 build_address(&am, op1);
1037 new_op1 = be_transform_node(op2);
1039 /* construct an Add with source address mode */
1040 if(new_op1 != NULL) {
1041 ia32_address_t *am_addr = &am.addr;
1042 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
1043 am_addr->index, am_addr->mem, new_op1, noreg);
1044 set_address(new_node, am_addr);
1045 set_ia32_op_type(new_node, ia32_AddrModeS);
1046 set_ia32_ls_mode(new_node, am.ls_mode);
1047 set_ia32_commutative(new_node);
1048 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1050 new_node = fix_mem_proj(new_node, &am);
1055 /* otherwise construct a lea */
1056 new_node = create_lea_from_address(dbgi, new_block, &addr);
1057 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1062 * Creates an ia32 Mul.
1064 * @return the created ia32 Mul node
1066 static ir_node *gen_Mul(ir_node *node) {
1067 ir_node *op1 = get_Mul_left(node);
1068 ir_node *op2 = get_Mul_right(node);
1069 ir_mode *mode = get_irn_mode(node);
1071 if (mode_is_float(mode)) {
1072 if (USE_SSE2(env_cg))
1073 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul, match_commutative);
1075 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul, match_commutative);
1079 for the lower 32bit of the result it doesn't matter whether we use
1080 signed or unsigned multiplication so we use IMul as it has fewer
1083 return gen_binop(node, op1, op2, new_rd_ia32_IMul, match_commutative);
1087 * Creates an ia32 Mulh.
1088 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1089 * this result while Mul returns the lower 32 bit.
1091 * @return the created ia32 Mulh node
1093 static ir_node *gen_Mulh(ir_node *node)
1095 ir_node *block = get_nodes_block(node);
1096 ir_node *new_block = be_transform_node(block);
1097 ir_graph *irg = current_ir_graph;
1098 dbg_info *dbgi = get_irn_dbg_info(node);
1099 ir_mode *mode = get_irn_mode(node);
1100 ir_node *op1 = get_Mulh_left(node);
1101 ir_node *op2 = get_Mulh_right(node);
1104 match_flags_t flags;
1105 ia32_address_mode_t am;
1106 ia32_address_t *addr = &am.addr;
1108 flags = match_force_32bit_op | match_commutative | match_no_immediate;
1110 assert(!mode_is_float(mode) && "Mulh with float not supported");
1112 match_arguments(&am, block, op1, op2, flags);
1114 if (mode_is_signed(mode)) {
1115 new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base,
1116 addr->index, addr->mem, am.new_op1,
1119 new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base,
1120 addr->index, addr->mem, am.new_op1,
1124 set_am_attributes(new_node, &am);
1125 /* we can't use source address mode anymore when using immediates */
1126 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
1127 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
1128 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1130 assert(get_irn_mode(new_node) == mode_T);
1132 fix_mem_proj(new_node, &am);
1134 assert(pn_ia32_IMul1OP_EDX == pn_ia32_Mul_EDX);
1135 proj_EDX = new_rd_Proj(dbgi, irg, block, new_node,
1136 mode_Iu, pn_ia32_IMul1OP_EDX);
1144 * Creates an ia32 And.
1146 * @return The created ia32 And node
1148 static ir_node *gen_And(ir_node *node) {
1149 ir_node *op1 = get_And_left(node);
1150 ir_node *op2 = get_And_right(node);
1151 assert(! mode_is_float(get_irn_mode(node)));
1153 /* is it a zero extension? */
1154 if (is_Const(op2)) {
1155 tarval *tv = get_Const_tarval(op2);
1156 long v = get_tarval_long(tv);
1158 if (v == 0xFF || v == 0xFFFF) {
1159 dbg_info *dbgi = get_irn_dbg_info(node);
1160 ir_node *block = get_nodes_block(node);
1167 assert(v == 0xFFFF);
1170 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1176 return gen_binop(node, op1, op2, new_rd_ia32_And, match_commutative);
1182 * Creates an ia32 Or.
1184 * @return The created ia32 Or node
1186 static ir_node *gen_Or(ir_node *node) {
1187 ir_node *op1 = get_Or_left(node);
1188 ir_node *op2 = get_Or_right(node);
1190 assert (! mode_is_float(get_irn_mode(node)));
1191 return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative);
1197 * Creates an ia32 Eor.
1199 * @return The created ia32 Eor node
1201 static ir_node *gen_Eor(ir_node *node) {
1202 ir_node *op1 = get_Eor_left(node);
1203 ir_node *op2 = get_Eor_right(node);
1205 assert(! mode_is_float(get_irn_mode(node)));
1206 return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative);
1211 * Creates an ia32 Sub.
1213 * @return The created ia32 Sub node
1215 static ir_node *gen_Sub(ir_node *node) {
1216 ir_node *op1 = get_Sub_left(node);
1217 ir_node *op2 = get_Sub_right(node);
1218 ir_mode *mode = get_irn_mode(node);
1220 if (mode_is_float(mode)) {
1221 if (USE_SSE2(env_cg))
1222 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub, 0);
1224 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub, 0);
1228 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1232 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1235 typedef enum { flavour_Div = 1, flavour_Mod, flavour_DivMod } ia32_op_flavour_t;
1238 * Generates an ia32 DivMod with additional infrastructure for the
1239 * register allocator if needed.
1241 * @param dividend -no comment- :)
1242 * @param divisor -no comment- :)
1243 * @param dm_flav flavour_Div/Mod/DivMod
1244 * @return The created ia32 DivMod node
1246 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1247 ir_node *divisor, ia32_op_flavour_t dm_flav)
1249 ir_node *block = be_transform_node(get_nodes_block(node));
1250 ir_node *new_dividend = be_transform_node(dividend);
1251 ir_node *new_divisor = be_transform_node(divisor);
1252 ir_graph *irg = current_ir_graph;
1253 dbg_info *dbgi = get_irn_dbg_info(node);
1254 ir_mode *mode = get_irn_mode(node);
1255 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1256 ir_node *res, *proj_div, *proj_mod;
1257 ir_node *sign_extension;
1258 ir_node *mem, *new_mem;
1261 proj_div = proj_mod = NULL;
1265 mem = get_Div_mem(node);
1266 mode = get_Div_resmode(node);
1267 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1268 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1271 mem = get_Mod_mem(node);
1272 mode = get_Mod_resmode(node);
1273 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1274 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1276 case flavour_DivMod:
1277 mem = get_DivMod_mem(node);
1278 mode = get_DivMod_resmode(node);
1279 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1280 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1281 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1284 panic("invalid divmod flavour!");
1286 new_mem = be_transform_node(mem);
1288 if (mode_is_signed(mode)) {
1289 /* in signed mode, we need to sign extend the dividend */
1290 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1291 add_irn_dep(produceval, get_irg_frame(irg));
1292 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1295 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1296 set_ia32_flags(sign_extension, get_ia32_flags(sign_extension) | arch_irn_flags_modify_flags);
1297 add_irn_dep(sign_extension, get_irg_frame(irg));
1300 if (mode_is_signed(mode)) {
1301 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
1302 new_dividend, sign_extension, new_divisor);
1304 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem,
1305 new_dividend, sign_extension, new_divisor);
1308 set_ia32_exc_label(res, has_exc);
1309 set_irn_pinned(res, get_irn_pinned(node));
1311 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1318 * Wrapper for generate_DivMod. Sets flavour_Mod.
1321 static ir_node *gen_Mod(ir_node *node) {
1322 return generate_DivMod(node, get_Mod_left(node),
1323 get_Mod_right(node), flavour_Mod);
1327 * Wrapper for generate_DivMod. Sets flavour_Div.
1330 static ir_node *gen_Div(ir_node *node) {
1331 return generate_DivMod(node, get_Div_left(node),
1332 get_Div_right(node), flavour_Div);
1336 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1338 static ir_node *gen_DivMod(ir_node *node) {
1339 return generate_DivMod(node, get_DivMod_left(node),
1340 get_DivMod_right(node), flavour_DivMod);
1346 * Creates an ia32 floating Div.
1348 * @return The created ia32 xDiv node
1350 static ir_node *gen_Quot(ir_node *node)
1352 ir_node *op1 = get_Quot_left(node);
1353 ir_node *op2 = get_Quot_right(node);
1355 if (USE_SSE2(env_cg)) {
1356 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xDiv, 0);
1358 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, 0);
1364 * Creates an ia32 Shl.
1366 * @return The created ia32 Shl node
1368 static ir_node *gen_Shl(ir_node *node) {
1369 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1376 * Creates an ia32 Shr.
1378 * @return The created ia32 Shr node
1380 static ir_node *gen_Shr(ir_node *node) {
1381 return gen_shift_binop(node, get_Shr_left(node),
1382 get_Shr_right(node), new_rd_ia32_Shr);
1388 * Creates an ia32 Sar.
1390 * @return The created ia32 Shrs node
1392 static ir_node *gen_Shrs(ir_node *node) {
1393 ir_node *left = get_Shrs_left(node);
1394 ir_node *right = get_Shrs_right(node);
1395 ir_mode *mode = get_irn_mode(node);
1396 if(is_Const(right) && mode == mode_Is) {
1397 tarval *tv = get_Const_tarval(right);
1398 long val = get_tarval_long(tv);
1400 /* this is a sign extension */
1401 ir_graph *irg = current_ir_graph;
1402 dbg_info *dbgi = get_irn_dbg_info(node);
1403 ir_node *block = be_transform_node(get_nodes_block(node));
1405 ir_node *new_op = be_transform_node(op);
1406 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1407 add_irn_dep(pval, get_irg_frame(irg));
1409 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1413 /* 8 or 16 bit sign extension? */
1414 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1415 ir_node *shl_left = get_Shl_left(left);
1416 ir_node *shl_right = get_Shl_right(left);
1417 if(is_Const(shl_right)) {
1418 tarval *tv1 = get_Const_tarval(right);
1419 tarval *tv2 = get_Const_tarval(shl_right);
1420 if(tv1 == tv2 && tarval_is_long(tv1)) {
1421 long val = get_tarval_long(tv1);
1422 if(val == 16 || val == 24) {
1423 dbg_info *dbgi = get_irn_dbg_info(node);
1424 ir_node *block = get_nodes_block(node);
1434 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1443 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1449 * Creates an ia32 RotL.
1451 * @param op1 The first operator
1452 * @param op2 The second operator
1453 * @return The created ia32 RotL node
1455 static ir_node *gen_RotL(ir_node *node,
1456 ir_node *op1, ir_node *op2) {
1457 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1463 * Creates an ia32 RotR.
1464 * NOTE: There is no RotR with immediate because this would always be a RotL
1465 * "imm-mode_size_bits" which can be pre-calculated.
1467 * @param op1 The first operator
1468 * @param op2 The second operator
1469 * @return The created ia32 RotR node
1471 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1473 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1479 * Creates an ia32 RotR or RotL (depending on the found pattern).
1481 * @return The created ia32 RotL or RotR node
1483 static ir_node *gen_Rot(ir_node *node) {
1484 ir_node *rotate = NULL;
1485 ir_node *op1 = get_Rot_left(node);
1486 ir_node *op2 = get_Rot_right(node);
1488 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1489 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1490 that means we can create a RotR instead of an Add and a RotL */
1492 if (get_irn_op(op2) == op_Add) {
1494 ir_node *left = get_Add_left(add);
1495 ir_node *right = get_Add_right(add);
1496 if (is_Const(right)) {
1497 tarval *tv = get_Const_tarval(right);
1498 ir_mode *mode = get_irn_mode(node);
1499 long bits = get_mode_size_bits(mode);
1501 if (get_irn_op(left) == op_Minus &&
1502 tarval_is_long(tv) &&
1503 get_tarval_long(tv) == bits)
1505 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1506 rotate = gen_RotR(node, op1, get_Minus_op(left));
1511 if (rotate == NULL) {
1512 rotate = gen_RotL(node, op1, op2);
1521 * Transforms a Minus node.
1523 * @return The created ia32 Minus node
1525 static ir_node *gen_Minus(ir_node *node)
1527 ir_node *op = get_Minus_op(node);
1528 ir_node *block = be_transform_node(get_nodes_block(node));
1529 ir_graph *irg = current_ir_graph;
1530 dbg_info *dbgi = get_irn_dbg_info(node);
1531 ir_mode *mode = get_irn_mode(node);
1536 if (mode_is_float(mode)) {
1537 ir_node *new_op = be_transform_node(op);
1538 if (USE_SSE2(env_cg)) {
1539 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1540 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1541 ir_node *nomem = new_rd_NoMem(irg);
1543 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1546 size = get_mode_size_bits(mode);
1547 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1549 set_ia32_am_sc(res, ent);
1550 set_ia32_op_type(res, ia32_AddrModeS);
1551 set_ia32_ls_mode(res, mode);
1553 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1556 res = gen_unop(node, op, new_rd_ia32_Neg);
1559 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1565 * Transforms a Not node.
1567 * @return The created ia32 Not node
1569 static ir_node *gen_Not(ir_node *node) {
1570 ir_node *op = get_Not_op(node);
1571 ir_mode *mode = get_irn_mode(node);
1573 assert(mode != mode_b); /* should be lowered already */
1575 assert (! mode_is_float(get_irn_mode(node)));
1576 return gen_unop(node, op, new_rd_ia32_Not);
1582 * Transforms an Abs node.
1584 * @return The created ia32 Abs node
1586 static ir_node *gen_Abs(ir_node *node)
1588 ir_node *block = be_transform_node(get_nodes_block(node));
1589 ir_node *op = get_Abs_op(node);
1590 ir_node *new_op = be_transform_node(op);
1591 ir_graph *irg = current_ir_graph;
1592 dbg_info *dbgi = get_irn_dbg_info(node);
1593 ir_mode *mode = get_irn_mode(node);
1594 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1595 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1596 ir_node *nomem = new_NoMem();
1601 if (mode_is_float(mode)) {
1602 if (USE_SSE2(env_cg)) {
1603 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
1605 size = get_mode_size_bits(mode);
1606 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1608 set_ia32_am_sc(res, ent);
1610 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1612 set_ia32_op_type(res, ia32_AddrModeS);
1613 set_ia32_ls_mode(res, mode);
1615 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1616 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1620 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1621 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1624 add_irn_dep(pval, get_irg_frame(irg));
1625 SET_IA32_ORIG_NODE(sign_extension,
1626 ia32_get_old_node_name(env_cg, node));
1628 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
1630 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1632 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
1634 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1641 * Transforms a Load.
1643 * @return the created ia32 Load node
1645 static ir_node *gen_Load(ir_node *node) {
1646 ir_node *old_block = get_nodes_block(node);
1647 ir_node *block = be_transform_node(old_block);
1648 ir_node *ptr = get_Load_ptr(node);
1649 ir_node *mem = get_Load_mem(node);
1650 ir_node *new_mem = be_transform_node(mem);
1653 ir_graph *irg = current_ir_graph;
1654 dbg_info *dbgi = get_irn_dbg_info(node);
1655 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1656 ir_mode *mode = get_Load_mode(node);
1659 ia32_address_t addr;
1661 /* construct load address */
1662 memset(&addr, 0, sizeof(addr));
1663 ia32_create_address_mode(&addr, ptr, 0);
1670 base = be_transform_node(base);
1676 index = be_transform_node(index);
1679 if (mode_is_float(mode)) {
1680 if (USE_SSE2(env_cg)) {
1681 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1683 res_mode = mode_xmm;
1685 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1687 res_mode = mode_vfp;
1693 /* create a conv node with address mode for smaller modes */
1694 if(get_mode_size_bits(mode) < 32) {
1695 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1696 new_mem, noreg, mode);
1698 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1703 set_irn_pinned(new_op, get_irn_pinned(node));
1704 set_ia32_op_type(new_op, ia32_AddrModeS);
1705 set_ia32_ls_mode(new_op, mode);
1706 set_address(new_op, &addr);
1708 /* make sure we are scheduled behind the initial IncSP/Barrier
1709 * to avoid spills being placed before it
1711 if (block == get_irg_start_block(irg)) {
1712 add_irn_dep(new_op, get_irg_frame(irg));
1715 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1716 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1721 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1722 ir_node *ptr, ir_mode *mode, ir_node *other)
1729 /* we only use address mode if we're the only user of the load */
1730 if(get_irn_n_edges(node) > 1)
1733 load = get_Proj_pred(node);
1736 if(get_nodes_block(load) != block)
1739 /* Store should be attached to the load */
1740 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1742 /* store should have the same pointer as the load */
1743 if(get_Load_ptr(load) != ptr)
1746 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1747 if(other != NULL && get_nodes_block(other) == block
1748 && heights_reachable_in_block(heights, other, load))
1751 assert(get_Load_mode(load) == mode);
1756 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1757 ir_node *mem, ir_node *ptr, ir_mode *mode,
1758 construct_binop_dest_func *func,
1759 construct_binop_dest_func *func8bit,
1762 ir_node *src_block = get_nodes_block(node);
1764 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1765 ir_graph *irg = current_ir_graph;
1769 ia32_address_mode_t am;
1770 ia32_address_t *addr = &am.addr;
1771 memset(&am, 0, sizeof(am));
1773 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1774 build_address(&am, op1);
1775 new_op = create_immediate_or_transform(op2, 0);
1776 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1777 build_address(&am, op2);
1778 new_op = create_immediate_or_transform(op1, 0);
1783 if(addr->base == NULL)
1784 addr->base = noreg_gp;
1785 if(addr->index == NULL)
1786 addr->index = noreg_gp;
1787 if(addr->mem == NULL)
1788 addr->mem = new_NoMem();
1790 dbgi = get_irn_dbg_info(node);
1791 block = be_transform_node(src_block);
1792 if(get_mode_size_bits(mode) == 8) {
1793 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1796 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1799 set_address(new_node, addr);
1800 set_ia32_op_type(new_node, ia32_AddrModeD);
1801 set_ia32_ls_mode(new_node, mode);
1802 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1807 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1808 ir_node *ptr, ir_mode *mode,
1809 construct_unop_dest_func *func)
1811 ir_node *src_block = get_nodes_block(node);
1813 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1814 ir_graph *irg = current_ir_graph;
1817 ia32_address_mode_t am;
1818 ia32_address_t *addr = &am.addr;
1819 memset(&am, 0, sizeof(am));
1821 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1824 build_address(&am, op);
1826 if(addr->base == NULL)
1827 addr->base = noreg_gp;
1828 if(addr->index == NULL)
1829 addr->index = noreg_gp;
1830 if(addr->mem == NULL)
1831 addr->mem = new_NoMem();
1833 dbgi = get_irn_dbg_info(node);
1834 block = be_transform_node(src_block);
1835 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1836 set_address(new_node, addr);
1837 set_ia32_op_type(new_node, ia32_AddrModeD);
1838 set_ia32_ls_mode(new_node, mode);
1839 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1844 static ir_node *try_create_dest_am(ir_node *node) {
1845 ir_node *val = get_Store_value(node);
1846 ir_node *mem = get_Store_mem(node);
1847 ir_node *ptr = get_Store_ptr(node);
1848 ir_mode *mode = get_irn_mode(val);
1853 /* handle only GP modes for now... */
1854 if(!mode_needs_gp_reg(mode))
1857 /* store must be the only user of the val node */
1858 if(get_irn_n_edges(val) > 1)
1861 switch(get_irn_opcode(val)) {
1863 op1 = get_Add_left(val);
1864 op2 = get_Add_right(val);
1865 if(is_Const_1(op2)) {
1866 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1867 new_rd_ia32_IncMem);
1869 } else if(is_Const_Minus_1(op2)) {
1870 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1871 new_rd_ia32_DecMem);
1874 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1875 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, 1);
1878 op1 = get_Sub_left(val);
1879 op2 = get_Sub_right(val);
1881 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
1884 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1885 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, 0);
1888 op1 = get_And_left(val);
1889 op2 = get_And_right(val);
1890 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1891 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, 1);
1894 op1 = get_Or_left(val);
1895 op2 = get_Or_right(val);
1896 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1897 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, 1);
1900 op1 = get_Eor_left(val);
1901 op2 = get_Eor_right(val);
1902 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1903 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, 1);
1906 op1 = get_Shl_left(val);
1907 op2 = get_Shl_right(val);
1908 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1909 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, 0);
1912 op1 = get_Shr_left(val);
1913 op2 = get_Shr_right(val);
1914 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1915 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, 0);
1918 op1 = get_Shrs_left(val);
1919 op2 = get_Shrs_right(val);
1920 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1921 new_rd_ia32_SarMem, new_rd_ia32_SarMem, 0);
1924 op1 = get_Rot_left(val);
1925 op2 = get_Rot_right(val);
1926 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1927 new_rd_ia32_RolMem, new_rd_ia32_RolMem, 0);
1929 /* TODO: match ROR patterns... */
1931 op1 = get_Minus_op(val);
1932 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1935 /* should be lowered already */
1936 assert(mode != mode_b);
1937 op1 = get_Not_op(val);
1938 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1948 * Transforms a Store.
1950 * @return the created ia32 Store node
1952 static ir_node *gen_Store(ir_node *node) {
1953 ir_node *block = be_transform_node(get_nodes_block(node));
1954 ir_node *ptr = get_Store_ptr(node);
1957 ir_node *val = get_Store_value(node);
1959 ir_node *mem = get_Store_mem(node);
1960 ir_node *new_mem = be_transform_node(mem);
1961 ir_graph *irg = current_ir_graph;
1962 dbg_info *dbgi = get_irn_dbg_info(node);
1963 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1964 ir_mode *mode = get_irn_mode(val);
1966 ia32_address_t addr;
1968 /* check for destination address mode */
1969 new_op = try_create_dest_am(node);
1973 /* construct store address */
1974 memset(&addr, 0, sizeof(addr));
1975 ia32_create_address_mode(&addr, ptr, 0);
1982 base = be_transform_node(base);
1988 index = be_transform_node(index);
1991 if (mode_is_float(mode)) {
1992 /* convs (and strict-convs) before stores are unnecessary if the mode
1994 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
1995 val = get_Conv_op(val);
1997 new_val = be_transform_node(val);
1998 if (USE_SSE2(env_cg)) {
1999 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
2002 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
2006 new_val = create_immediate_or_transform(val, 0);
2010 if (get_mode_size_bits(mode) == 8) {
2011 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
2014 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
2019 set_irn_pinned(new_op, get_irn_pinned(node));
2020 set_ia32_op_type(new_op, ia32_AddrModeD);
2021 set_ia32_ls_mode(new_op, mode);
2023 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
2024 set_address(new_op, &addr);
2025 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2030 static ir_node *create_Switch(ir_node *node)
2032 ir_graph *irg = current_ir_graph;
2033 dbg_info *dbgi = get_irn_dbg_info(node);
2034 ir_node *block = be_transform_node(get_nodes_block(node));
2035 ir_node *sel = get_Cond_selector(node);
2036 ir_node *new_sel = be_transform_node(sel);
2038 int switch_min = INT_MAX;
2039 const ir_edge_t *edge;
2041 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2043 /* determine the smallest switch case value */
2044 foreach_out_edge(node, edge) {
2045 ir_node *proj = get_edge_src_irn(edge);
2046 int pn = get_Proj_proj(proj);
2051 if (switch_min != 0) {
2052 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2054 /* if smallest switch case is not 0 we need an additional sub */
2055 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2056 add_ia32_am_offs_int(new_sel, -switch_min);
2057 set_ia32_op_type(new_sel, ia32_AddrModeS);
2059 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2062 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
2063 set_ia32_pncode(res, get_Cond_defaultProj(node));
2065 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2070 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
2072 ir_graph *irg = current_ir_graph;
2080 /* we have a Cmp as input */
2082 ir_node *pred = get_Proj_pred(node);
2084 flags = be_transform_node(pred);
2085 *pnc_out = get_Proj_proj(node);
2090 /* a mode_b value, we have to compare it against 0 */
2091 dbgi = get_irn_dbg_info(node);
2092 new_block = be_transform_node(get_nodes_block(node));
2093 new_op = be_transform_node(node);
2094 noreg = ia32_new_NoReg_gp(env_cg);
2095 nomem = new_NoMem();
2096 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
2097 new_op, new_op, 0, 0);
2098 *pnc_out = pn_Cmp_Lg;
2102 static ir_node *gen_Cond(ir_node *node) {
2103 ir_node *block = get_nodes_block(node);
2104 ir_node *new_block = be_transform_node(block);
2105 ir_graph *irg = current_ir_graph;
2106 dbg_info *dbgi = get_irn_dbg_info(node);
2107 ir_node *sel = get_Cond_selector(node);
2108 ir_mode *sel_mode = get_irn_mode(sel);
2110 ir_node *flags = NULL;
2113 if (sel_mode != mode_b) {
2114 return create_Switch(node);
2117 /* we get flags from a cmp */
2118 flags = get_flags_node(sel, &pnc);
2120 res = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2121 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2129 * Transforms a CopyB node.
2131 * @return The transformed node.
2133 static ir_node *gen_CopyB(ir_node *node) {
2134 ir_node *block = be_transform_node(get_nodes_block(node));
2135 ir_node *src = get_CopyB_src(node);
2136 ir_node *new_src = be_transform_node(src);
2137 ir_node *dst = get_CopyB_dst(node);
2138 ir_node *new_dst = be_transform_node(dst);
2139 ir_node *mem = get_CopyB_mem(node);
2140 ir_node *new_mem = be_transform_node(mem);
2141 ir_node *res = NULL;
2142 ir_graph *irg = current_ir_graph;
2143 dbg_info *dbgi = get_irn_dbg_info(node);
2144 int size = get_type_size_bytes(get_CopyB_type(node));
2147 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2148 /* then we need the size explicitly in ECX. */
2149 if (size >= 32 * 4) {
2150 rem = size & 0x3; /* size % 4 */
2153 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2155 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2157 set_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);
2159 add_irn_dep(res, get_irg_frame(irg));
2161 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2162 /* we misuse the pncode field for the copyb size */
2163 set_ia32_pncode(res, rem);
2165 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2166 set_ia32_pncode(res, size);
2169 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2174 static ir_node *gen_be_Copy(ir_node *node)
2176 ir_node *result = be_duplicate_node(node);
2177 ir_mode *mode = get_irn_mode(result);
2179 if (mode_needs_gp_reg(mode)) {
2180 set_irn_mode(result, mode_Iu);
2187 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2188 * to fold an and into a test node
2190 static int can_fold_test_and(ir_node *node)
2192 const ir_edge_t *edge;
2194 /** we can only have eq and lg projs */
2195 foreach_out_edge(node, edge) {
2196 ir_node *proj = get_edge_src_irn(edge);
2197 pn_Cmp pnc = get_Proj_proj(proj);
2198 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2205 static ir_node *try_create_Test(ir_node *node)
2207 ir_graph *irg = current_ir_graph;
2208 dbg_info *dbgi = get_irn_dbg_info(node);
2209 ir_node *block = get_nodes_block(node);
2210 ir_node *new_block = be_transform_node(block);
2211 ir_node *cmp_left = get_Cmp_left(node);
2212 ir_node *cmp_right = get_Cmp_right(node);
2217 ia32_address_mode_t am;
2218 ia32_address_t *addr = &am.addr;
2221 /* can we use a test instruction? */
2222 if(!is_Const_0(cmp_right))
2225 if(is_And(cmp_left) && get_irn_n_edges(cmp_left) == 1 &&
2226 can_fold_test_and(node)) {
2227 ir_node *and_left = get_And_left(cmp_left);
2228 ir_node *and_right = get_And_right(cmp_left);
2230 mode = get_irn_mode(and_left);
2234 mode = get_irn_mode(cmp_left);
2239 assert(get_mode_size_bits(mode) <= 32);
2241 match_arguments(&am, block, left, right, match_commutative |
2242 match_8_bit_am | match_16_bit_am | match_am_and_immediates);
2244 cmp_unsigned = !mode_is_signed(mode);
2245 if(get_mode_size_bits(mode) == 8) {
2246 res = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2247 addr->index, addr->mem, am.new_op1,
2248 am.new_op2, am.ins_permuted, cmp_unsigned);
2250 res = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, addr->index,
2251 addr->mem, am.new_op1, am.new_op2,
2252 am.ins_permuted, cmp_unsigned);
2254 set_am_attributes(res, &am);
2255 assert(mode != NULL);
2256 set_ia32_ls_mode(res, mode);
2258 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2260 res = fix_mem_proj(res, &am);
2264 static ir_node *create_Fucom(ir_node *node)
2266 ir_graph *irg = current_ir_graph;
2267 dbg_info *dbgi = get_irn_dbg_info(node);
2268 ir_node *block = get_nodes_block(node);
2269 ir_node *new_block = be_transform_node(block);
2270 ir_node *left = get_Cmp_left(node);
2271 ir_node *new_left = be_transform_node(left);
2272 ir_node *right = get_Cmp_right(node);
2276 if(transform_config.use_fucomi) {
2277 new_right = be_transform_node(right);
2278 res = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left, new_right, 0);
2279 set_ia32_commutative(res);
2280 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2282 if(transform_config.use_ftst && is_Const_null(right)) {
2283 res = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left, 0);
2285 new_right = be_transform_node(right);
2286 res = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2290 set_ia32_commutative(res);
2292 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2294 res = new_rd_ia32_Sahf(dbgi, irg, new_block, res);
2295 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2301 static ir_node *create_Ucomi(ir_node *node)
2303 ir_graph *irg = current_ir_graph;
2304 dbg_info *dbgi = get_irn_dbg_info(node);
2305 ir_node *src_block = get_nodes_block(node);
2306 ir_node *new_block = be_transform_node(src_block);
2307 ir_node *left = get_Cmp_left(node);
2308 ir_node *right = get_Cmp_right(node);
2310 ia32_address_mode_t am;
2311 ia32_address_t *addr = &am.addr;
2313 match_arguments(&am, src_block, left, right, match_commutative);
2315 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2316 addr->mem, am.new_op1, am.new_op2,
2318 set_am_attributes(new_node, &am);
2320 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2322 new_node = fix_mem_proj(new_node, &am);
2327 static ir_node *gen_Cmp(ir_node *node)
2329 ir_graph *irg = current_ir_graph;
2330 dbg_info *dbgi = get_irn_dbg_info(node);
2331 ir_node *block = get_nodes_block(node);
2332 ir_node *new_block = be_transform_node(block);
2333 ir_node *left = get_Cmp_left(node);
2334 ir_node *right = get_Cmp_right(node);
2335 ir_mode *cmp_mode = get_irn_mode(left);
2337 ia32_address_mode_t am;
2338 ia32_address_t *addr = &am.addr;
2341 if(mode_is_float(cmp_mode)) {
2342 if (USE_SSE2(env_cg)) {
2343 return create_Ucomi(node);
2345 return create_Fucom(node);
2349 assert(mode_needs_gp_reg(cmp_mode));
2351 /* we prefer the Test instruction where possible except cases where
2352 * we can use SourceAM */
2353 if(!use_source_address_mode(block, left, right) &&
2354 !use_source_address_mode(block, right, left)) {
2355 res = try_create_Test(node);
2360 match_arguments(&am, block, left, right,
2361 match_commutative | match_8_bit_am | match_16_bit_am |
2362 match_am_and_immediates);
2364 cmp_unsigned = !mode_is_signed(get_irn_mode(left));
2365 if(get_mode_size_bits(cmp_mode) == 8) {
2366 res = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, addr->index,
2367 addr->mem, am.new_op1, am.new_op2,
2368 am.ins_permuted, cmp_unsigned);
2370 res = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, addr->index,
2371 addr->mem, am.new_op1, am.new_op2,
2372 am.ins_permuted, cmp_unsigned);
2374 set_am_attributes(res, &am);
2375 assert(cmp_mode != NULL);
2376 set_ia32_ls_mode(res, cmp_mode);
2378 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2380 res = fix_mem_proj(res, &am);
2385 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2387 ir_graph *irg = current_ir_graph;
2388 dbg_info *dbgi = get_irn_dbg_info(node);
2389 ir_node *block = get_nodes_block(node);
2390 ir_node *new_block = be_transform_node(block);
2391 ir_node *val_true = get_Psi_val(node, 0);
2392 ir_node *val_false = get_Psi_default(node);
2394 match_flags_t match_flags;
2395 ia32_address_mode_t am;
2396 ia32_address_t *addr;
2398 assert(transform_config.use_cmov);
2399 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2403 match_flags = match_commutative | match_no_immediate | match_16_bit_am
2404 | match_force_32bit_op;
2406 match_arguments(&am, block, val_false, val_true, match_flags);
2408 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2409 addr->mem, am.new_op1, am.new_op2, new_flags,
2410 am.ins_permuted, pnc);
2411 set_am_attributes(new_node, &am);
2413 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2415 new_node = fix_mem_proj(new_node, &am);
2422 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2423 ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
2426 ir_graph *irg = current_ir_graph;
2427 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2428 ir_node *nomem = new_NoMem();
2431 res = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
2432 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2433 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2434 nomem, res, mode_Bu);
2435 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2441 * Transforms a Psi node into CMov.
2443 * @return The transformed node.
2445 static ir_node *gen_Psi(ir_node *node)
2447 dbg_info *dbgi = get_irn_dbg_info(node);
2448 ir_node *block = get_nodes_block(node);
2449 ir_node *new_block = be_transform_node(block);
2450 ir_node *psi_true = get_Psi_val(node, 0);
2451 ir_node *psi_default = get_Psi_default(node);
2452 ir_node *cond = get_Psi_cond(node, 0);
2453 ir_node *flags = NULL;
2457 assert(get_Psi_n_conds(node) == 1);
2458 assert(get_irn_mode(cond) == mode_b);
2459 assert(mode_needs_gp_reg(get_irn_mode(node)));
2461 flags = get_flags_node(cond, &pnc);
2463 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2464 res = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
2465 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2466 res = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
2468 res = create_CMov(node, flags, pnc);
2475 * Create a conversion from x87 state register to general purpose.
2477 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2478 ir_node *block = be_transform_node(get_nodes_block(node));
2479 ir_node *op = get_Conv_op(node);
2480 ir_node *new_op = be_transform_node(op);
2481 ia32_code_gen_t *cg = env_cg;
2482 ir_graph *irg = current_ir_graph;
2483 dbg_info *dbgi = get_irn_dbg_info(node);
2484 ir_node *noreg = ia32_new_NoReg_gp(cg);
2485 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2486 ir_mode *mode = get_irn_mode(node);
2487 ir_node *fist, *load;
2490 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2491 new_NoMem(), new_op, trunc_mode);
2493 set_irn_pinned(fist, op_pin_state_floats);
2494 set_ia32_use_frame(fist);
2495 set_ia32_op_type(fist, ia32_AddrModeD);
2497 assert(get_mode_size_bits(mode) <= 32);
2498 /* exception we can only store signed 32 bit integers, so for unsigned
2499 we store a 64bit (signed) integer and load the lower bits */
2500 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2501 set_ia32_ls_mode(fist, mode_Ls);
2503 set_ia32_ls_mode(fist, mode_Is);
2505 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2508 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2510 set_irn_pinned(load, op_pin_state_floats);
2511 set_ia32_use_frame(load);
2512 set_ia32_op_type(load, ia32_AddrModeS);
2513 set_ia32_ls_mode(load, mode_Is);
2514 if(get_ia32_ls_mode(fist) == mode_Ls) {
2515 ia32_attr_t *attr = get_ia32_attr(load);
2516 attr->data.need_64bit_stackent = 1;
2518 ia32_attr_t *attr = get_ia32_attr(load);
2519 attr->data.need_32bit_stackent = 1;
2521 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2523 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2527 * Creates a x87 strict Conv by placing a Sore and a Load
2529 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2531 ir_node *block = get_nodes_block(node);
2532 ir_graph *irg = current_ir_graph;
2533 dbg_info *dbgi = get_irn_dbg_info(node);
2534 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2535 ir_node *nomem = new_NoMem();
2536 ir_node *frame = get_irg_frame(irg);
2537 ir_node *store, *load;
2540 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2542 set_ia32_use_frame(store);
2543 set_ia32_op_type(store, ia32_AddrModeD);
2544 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2546 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2548 set_ia32_use_frame(load);
2549 set_ia32_op_type(load, ia32_AddrModeS);
2550 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2552 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2556 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2558 ir_graph *irg = current_ir_graph;
2559 ir_node *start_block = get_irg_start_block(irg);
2560 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2561 symconst, symconst_sign, val);
2562 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2568 * Create a conversion from general purpose to x87 register
2570 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2571 ir_node *src_block = get_nodes_block(node);
2572 ir_node *block = be_transform_node(src_block);
2573 ir_graph *irg = current_ir_graph;
2574 dbg_info *dbgi = get_irn_dbg_info(node);
2575 ir_node *op = get_Conv_op(node);
2580 ir_mode *store_mode;
2586 /* fild can use source AM if the operand is a signed 32bit integer */
2587 if (src_mode == mode_Is) {
2588 ia32_address_mode_t am;
2590 match_arguments(&am, src_block, NULL, op, match_no_immediate);
2591 if (am.op_type == ia32_AddrModeS) {
2592 ia32_address_t *addr = &am.addr;
2594 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base, addr->index, addr->mem);
2595 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2597 set_am_attributes(fild, &am);
2598 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2600 fix_mem_proj(fild, &am);
2604 new_op = am.new_op2;
2606 new_op = be_transform_node(op);
2609 noreg = ia32_new_NoReg_gp(env_cg);
2610 nomem = new_NoMem();
2611 mode = get_irn_mode(op);
2613 /* first convert to 32 bit signed if necessary */
2614 src_bits = get_mode_size_bits(src_mode);
2615 if (src_bits == 8) {
2616 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2618 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2620 } else if (src_bits < 32) {
2621 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2623 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2627 assert(get_mode_size_bits(mode) == 32);
2630 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2633 set_ia32_use_frame(store);
2634 set_ia32_op_type(store, ia32_AddrModeD);
2635 set_ia32_ls_mode(store, mode_Iu);
2637 /* exception for 32bit unsigned, do a 64bit spill+load */
2638 if(!mode_is_signed(mode)) {
2641 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2643 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2644 get_irg_frame(irg), noreg, nomem,
2647 set_ia32_use_frame(zero_store);
2648 set_ia32_op_type(zero_store, ia32_AddrModeD);
2649 add_ia32_am_offs_int(zero_store, 4);
2650 set_ia32_ls_mode(zero_store, mode_Iu);
2655 store = new_rd_Sync(dbgi, irg, block, 2, in);
2656 store_mode = mode_Ls;
2658 store_mode = mode_Is;
2662 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2664 set_ia32_use_frame(fild);
2665 set_ia32_op_type(fild, ia32_AddrModeS);
2666 set_ia32_ls_mode(fild, store_mode);
2668 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2674 * Crete a conversion from one integer mode into another one
2676 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2677 dbg_info *dbgi, ir_node *block, ir_node *op,
2680 ir_graph *irg = current_ir_graph;
2681 int src_bits = get_mode_size_bits(src_mode);
2682 int tgt_bits = get_mode_size_bits(tgt_mode);
2683 ir_node *new_block = be_transform_node(block);
2684 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2687 ir_mode *smaller_mode;
2689 ia32_address_mode_t am;
2690 ia32_address_t *addr = &am.addr;
2692 if (src_bits < tgt_bits) {
2693 smaller_mode = src_mode;
2694 smaller_bits = src_bits;
2696 smaller_mode = tgt_mode;
2697 smaller_bits = tgt_bits;
2700 memset(&am, 0, sizeof(am));
2701 if(use_source_address_mode(block, op, NULL)) {
2702 build_address(&am, op);
2704 am.op_type = ia32_AddrModeS;
2706 new_op = be_transform_node(op);
2707 am.op_type = ia32_Normal;
2709 if(addr->base == NULL)
2711 if(addr->index == NULL)
2712 addr->index = noreg;
2713 if(addr->mem == NULL)
2714 addr->mem = new_NoMem();
2716 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2717 if (smaller_bits == 8) {
2718 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2719 addr->index, addr->mem, new_op,
2722 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2723 addr->index, addr->mem, new_op,
2727 set_am_attributes(res, &am);
2728 set_ia32_ls_mode(res, smaller_mode);
2729 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2730 res = fix_mem_proj(res, &am);
2736 * Transforms a Conv node.
2738 * @return The created ia32 Conv node
2740 static ir_node *gen_Conv(ir_node *node) {
2741 ir_node *block = get_nodes_block(node);
2742 ir_node *new_block = be_transform_node(block);
2743 ir_node *op = get_Conv_op(node);
2744 ir_node *new_op = NULL;
2745 ir_graph *irg = current_ir_graph;
2746 dbg_info *dbgi = get_irn_dbg_info(node);
2747 ir_mode *src_mode = get_irn_mode(op);
2748 ir_mode *tgt_mode = get_irn_mode(node);
2749 int src_bits = get_mode_size_bits(src_mode);
2750 int tgt_bits = get_mode_size_bits(tgt_mode);
2751 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2752 ir_node *nomem = new_rd_NoMem(irg);
2753 ir_node *res = NULL;
2755 if (src_mode == mode_b) {
2756 assert(mode_is_int(tgt_mode));
2757 /* nothing to do, we already model bools as 0/1 ints */
2758 return be_transform_node(op);
2761 if (src_mode == tgt_mode) {
2762 if (get_Conv_strict(node)) {
2763 if (USE_SSE2(env_cg)) {
2764 /* when we are in SSE mode, we can kill all strict no-op conversion */
2765 return be_transform_node(op);
2768 /* this should be optimized already, but who knows... */
2769 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2770 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2771 return be_transform_node(op);
2775 if (mode_is_float(src_mode)) {
2776 new_op = be_transform_node(op);
2777 /* we convert from float ... */
2778 if (mode_is_float(tgt_mode)) {
2779 if(src_mode == mode_E && tgt_mode == mode_D
2780 && !get_Conv_strict(node)) {
2781 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2786 if (USE_SSE2(env_cg)) {
2787 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2788 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2790 set_ia32_ls_mode(res, tgt_mode);
2792 if(get_Conv_strict(node)) {
2793 res = gen_x87_strict_conv(tgt_mode, new_op);
2794 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2797 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2802 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2803 if (USE_SSE2(env_cg)) {
2804 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2806 set_ia32_ls_mode(res, src_mode);
2808 return gen_x87_fp_to_gp(node);
2812 /* we convert from int ... */
2813 if (mode_is_float(tgt_mode)) {
2815 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2816 if (USE_SSE2(env_cg)) {
2817 new_op = be_transform_node(op);
2818 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2820 set_ia32_ls_mode(res, tgt_mode);
2822 res = gen_x87_gp_to_fp(node, src_mode);
2823 if(get_Conv_strict(node)) {
2824 res = gen_x87_strict_conv(tgt_mode, res);
2825 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2826 ia32_get_old_node_name(env_cg, node));
2830 } else if(tgt_mode == mode_b) {
2831 /* mode_b lowering already took care that we only have 0/1 values */
2832 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2833 src_mode, tgt_mode));
2834 return be_transform_node(op);
2837 if (src_bits == tgt_bits) {
2838 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2839 src_mode, tgt_mode));
2840 return be_transform_node(op);
2843 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2851 static int check_immediate_constraint(long val, char immediate_constraint_type)
2853 switch (immediate_constraint_type) {
2857 return val >= 0 && val <= 32;
2859 return val >= 0 && val <= 63;
2861 return val >= -128 && val <= 127;
2863 return val == 0xff || val == 0xffff;
2865 return val >= 0 && val <= 3;
2867 return val >= 0 && val <= 255;
2869 return val >= 0 && val <= 127;
2873 panic("Invalid immediate constraint found");
2877 static ir_node *try_create_Immediate(ir_node *node,
2878 char immediate_constraint_type)
2881 tarval *offset = NULL;
2882 int offset_sign = 0;
2884 ir_entity *symconst_ent = NULL;
2885 int symconst_sign = 0;
2887 ir_node *cnst = NULL;
2888 ir_node *symconst = NULL;
2891 mode = get_irn_mode(node);
2892 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2896 if(is_Minus(node)) {
2898 node = get_Minus_op(node);
2901 if(is_Const(node)) {
2904 offset_sign = minus;
2905 } else if(is_SymConst(node)) {
2908 symconst_sign = minus;
2909 } else if(is_Add(node)) {
2910 ir_node *left = get_Add_left(node);
2911 ir_node *right = get_Add_right(node);
2912 if(is_Const(left) && is_SymConst(right)) {
2915 symconst_sign = minus;
2916 offset_sign = minus;
2917 } else if(is_SymConst(left) && is_Const(right)) {
2920 symconst_sign = minus;
2921 offset_sign = minus;
2923 } else if(is_Sub(node)) {
2924 ir_node *left = get_Sub_left(node);
2925 ir_node *right = get_Sub_right(node);
2926 if(is_Const(left) && is_SymConst(right)) {
2929 symconst_sign = !minus;
2930 offset_sign = minus;
2931 } else if(is_SymConst(left) && is_Const(right)) {
2934 symconst_sign = minus;
2935 offset_sign = !minus;
2942 offset = get_Const_tarval(cnst);
2943 if(tarval_is_long(offset)) {
2944 val = get_tarval_long(offset);
2946 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2951 if(!check_immediate_constraint(val, immediate_constraint_type))
2954 if(symconst != NULL) {
2955 if(immediate_constraint_type != 0) {
2956 /* we need full 32bits for symconsts */
2960 /* unfortunately the assembler/linker doesn't support -symconst */
2964 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2966 symconst_ent = get_SymConst_entity(symconst);
2968 if(cnst == NULL && symconst == NULL)
2971 if(offset_sign && offset != NULL) {
2972 offset = tarval_neg(offset);
2975 res = create_Immediate(symconst_ent, symconst_sign, val);
2980 static ir_node *create_immediate_or_transform(ir_node *node,
2981 char immediate_constraint_type)
2983 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2984 if (new_node == NULL) {
2985 new_node = be_transform_node(node);
2990 static const arch_register_req_t no_register_req = {
2991 arch_register_req_type_none,
2992 NULL, /* regclass */
2993 NULL, /* limit bitset */
2994 { -1, -1 }, /* same pos */
2995 -1 /* different pos */
2999 * An assembler constraint.
3001 typedef struct constraint_t constraint_t;
3002 struct constraint_t {
3005 const arch_register_req_t **out_reqs;
3007 const arch_register_req_t *req;
3008 unsigned immediate_possible;
3009 char immediate_type;
3012 static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
3014 int immediate_possible = 0;
3015 char immediate_type = 0;
3016 unsigned limited = 0;
3017 const arch_register_class_t *cls = NULL;
3018 ir_graph *irg = current_ir_graph;
3019 struct obstack *obst = get_irg_obstack(irg);
3020 arch_register_req_t *req;
3021 unsigned *limited_ptr;
3025 /* TODO: replace all the asserts with nice error messages */
3028 /* a memory constraint: no need to do anything in backend about it
3029 * (the dependencies are already respected by the memory edge of
3031 constraint->req = &no_register_req;
3043 assert(cls == NULL ||
3044 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3045 cls = &ia32_reg_classes[CLASS_ia32_gp];
3046 limited |= 1 << REG_EAX;
3049 assert(cls == NULL ||
3050 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3051 cls = &ia32_reg_classes[CLASS_ia32_gp];
3052 limited |= 1 << REG_EBX;
3055 assert(cls == NULL ||
3056 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3057 cls = &ia32_reg_classes[CLASS_ia32_gp];
3058 limited |= 1 << REG_ECX;
3061 assert(cls == NULL ||
3062 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3063 cls = &ia32_reg_classes[CLASS_ia32_gp];
3064 limited |= 1 << REG_EDX;
3067 assert(cls == NULL ||
3068 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3069 cls = &ia32_reg_classes[CLASS_ia32_gp];
3070 limited |= 1 << REG_EDI;
3073 assert(cls == NULL ||
3074 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3075 cls = &ia32_reg_classes[CLASS_ia32_gp];
3076 limited |= 1 << REG_ESI;
3079 case 'q': /* q means lower part of the regs only, this makes no
3080 * difference to Q for us (we only assigne whole registers) */
3081 assert(cls == NULL ||
3082 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3083 cls = &ia32_reg_classes[CLASS_ia32_gp];
3084 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3088 assert(cls == NULL ||
3089 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3090 cls = &ia32_reg_classes[CLASS_ia32_gp];
3091 limited |= 1 << REG_EAX | 1 << REG_EDX;
3094 assert(cls == NULL ||
3095 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3096 cls = &ia32_reg_classes[CLASS_ia32_gp];
3097 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3098 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3105 assert(cls == NULL);
3106 cls = &ia32_reg_classes[CLASS_ia32_gp];
3112 /* TODO: mark values so the x87 simulator knows about t and u */
3113 assert(cls == NULL);
3114 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3119 assert(cls == NULL);
3120 /* TODO: check that sse2 is supported */
3121 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3131 assert(!immediate_possible);
3132 immediate_possible = 1;
3133 immediate_type = *c;
3137 assert(!immediate_possible);
3138 immediate_possible = 1;
3142 assert(!immediate_possible && cls == NULL);
3143 immediate_possible = 1;
3144 cls = &ia32_reg_classes[CLASS_ia32_gp];
3157 assert(constraint->is_in && "can only specify same constraint "
3160 sscanf(c, "%d%n", &same_as, &p);
3168 /* memory constraint no need to do anything in backend about it
3169 * (the dependencies are already respected by the memory edge of
3171 constraint->req = &no_register_req;
3174 case 'E': /* no float consts yet */
3175 case 'F': /* no float consts yet */
3176 case 's': /* makes no sense on x86 */
3177 case 'X': /* we can't support that in firm */
3180 case '<': /* no autodecrement on x86 */
3181 case '>': /* no autoincrement on x86 */
3182 case 'C': /* sse constant not supported yet */
3183 case 'G': /* 80387 constant not supported yet */
3184 case 'y': /* we don't support mmx registers yet */
3185 case 'Z': /* not available in 32 bit mode */
3186 case 'e': /* not available in 32 bit mode */
3187 panic("unsupported asm constraint '%c' found in (%+F)",
3188 *c, current_ir_graph);
3191 panic("unknown asm constraint '%c' found in (%+F)", *c,
3199 const arch_register_req_t *other_constr;
3201 assert(cls == NULL && "same as and register constraint not supported");
3202 assert(!immediate_possible && "same as and immediate constraint not "
3204 assert(same_as < constraint->n_outs && "wrong constraint number in "
3205 "same_as constraint");
3207 other_constr = constraint->out_reqs[same_as];
3209 req = obstack_alloc(obst, sizeof(req[0]));
3210 req->cls = other_constr->cls;
3211 req->type = arch_register_req_type_should_be_same;
3212 req->limited = NULL;
3213 req->other_same[0] = pos;
3214 req->other_same[1] = -1;
3215 req->other_different = -1;
3217 /* switch constraints. This is because in firm we have same_as
3218 * constraints on the output constraints while in the gcc asm syntax
3219 * they are specified on the input constraints */
3220 constraint->req = other_constr;
3221 constraint->out_reqs[same_as] = req;
3222 constraint->immediate_possible = 0;
3226 if(immediate_possible && cls == NULL) {
3227 cls = &ia32_reg_classes[CLASS_ia32_gp];
3229 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3230 assert(cls != NULL);
3232 if(immediate_possible) {
3233 assert(constraint->is_in
3234 && "immediate make no sense for output constraints");
3236 /* todo: check types (no float input on 'r' constrained in and such... */
3239 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3240 limited_ptr = (unsigned*) (req+1);
3242 req = obstack_alloc(obst, sizeof(req[0]));
3244 memset(req, 0, sizeof(req[0]));
3247 req->type = arch_register_req_type_limited;
3248 *limited_ptr = limited;
3249 req->limited = limited_ptr;
3251 req->type = arch_register_req_type_normal;
3255 constraint->req = req;
3256 constraint->immediate_possible = immediate_possible;
3257 constraint->immediate_type = immediate_type;
3260 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3267 panic("Clobbers not supported yet");
3270 static int is_memory_op(const ir_asm_constraint *constraint)
3272 ident *id = constraint->constraint;
3273 const char *str = get_id_str(id);
3276 for(c = str; *c != '\0'; ++c) {
3285 * generates code for a ASM node
3287 static ir_node *gen_ASM(ir_node *node)
3290 ir_graph *irg = current_ir_graph;
3291 ir_node *block = get_nodes_block(node);
3292 ir_node *new_block = be_transform_node(block);
3293 dbg_info *dbgi = get_irn_dbg_info(node);
3297 int n_out_constraints;
3299 const arch_register_req_t **out_reg_reqs;
3300 const arch_register_req_t **in_reg_reqs;
3301 ia32_asm_reg_t *register_map;
3302 unsigned reg_map_size = 0;
3303 struct obstack *obst;
3304 const ir_asm_constraint *in_constraints;
3305 const ir_asm_constraint *out_constraints;
3307 constraint_t parsed_constraint;
3309 arity = get_irn_arity(node);
3310 in = alloca(arity * sizeof(in[0]));
3311 memset(in, 0, arity * sizeof(in[0]));
3313 n_out_constraints = get_ASM_n_output_constraints(node);
3314 n_clobbers = get_ASM_n_clobbers(node);
3315 out_arity = n_out_constraints + n_clobbers;
3317 in_constraints = get_ASM_input_constraints(node);
3318 out_constraints = get_ASM_output_constraints(node);
3319 clobbers = get_ASM_clobbers(node);
3321 /* construct output constraints */
3322 obst = get_irg_obstack(irg);
3323 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
3324 parsed_constraint.out_reqs = out_reg_reqs;
3325 parsed_constraint.n_outs = n_out_constraints;
3326 parsed_constraint.is_in = 0;
3328 for(i = 0; i < out_arity; ++i) {
3331 if(i < n_out_constraints) {
3332 const ir_asm_constraint *constraint = &out_constraints[i];
3333 c = get_id_str(constraint->constraint);
3334 parse_asm_constraint(i, &parsed_constraint, c);
3336 if(constraint->pos > reg_map_size)
3337 reg_map_size = constraint->pos;
3339 ident *glob_id = clobbers [i - n_out_constraints];
3340 c = get_id_str(glob_id);
3341 parse_clobber(node, i, &parsed_constraint, c);
3344 out_reg_reqs[i] = parsed_constraint.req;
3347 /* construct input constraints */
3348 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
3349 parsed_constraint.is_in = 1;
3350 for(i = 0; i < arity; ++i) {
3351 const ir_asm_constraint *constraint = &in_constraints[i];
3352 ident *constr_id = constraint->constraint;
3353 const char *c = get_id_str(constr_id);
3355 parse_asm_constraint(i, &parsed_constraint, c);
3356 in_reg_reqs[i] = parsed_constraint.req;
3358 if(constraint->pos > reg_map_size)
3359 reg_map_size = constraint->pos;
3361 if(parsed_constraint.immediate_possible) {
3362 ir_node *pred = get_irn_n(node, i);
3363 char imm_type = parsed_constraint.immediate_type;
3364 ir_node *immediate = try_create_Immediate(pred, imm_type);
3366 if(immediate != NULL) {
3373 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
3374 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
3376 for(i = 0; i < n_out_constraints; ++i) {
3377 const ir_asm_constraint *constraint = &out_constraints[i];
3378 unsigned pos = constraint->pos;
3380 assert(pos < reg_map_size);
3381 register_map[pos].use_input = 0;
3382 register_map[pos].valid = 1;
3383 register_map[pos].memory = is_memory_op(constraint);
3384 register_map[pos].inout_pos = i;
3385 register_map[pos].mode = constraint->mode;
3388 /* transform inputs */
3389 for(i = 0; i < arity; ++i) {
3390 const ir_asm_constraint *constraint = &in_constraints[i];
3391 unsigned pos = constraint->pos;
3392 ir_node *pred = get_irn_n(node, i);
3393 ir_node *transformed;
3395 assert(pos < reg_map_size);
3396 register_map[pos].use_input = 1;
3397 register_map[pos].valid = 1;
3398 register_map[pos].memory = is_memory_op(constraint);
3399 register_map[pos].inout_pos = i;
3400 register_map[pos].mode = constraint->mode;
3405 transformed = be_transform_node(pred);
3406 in[i] = transformed;
3409 res = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
3410 get_ASM_text(node), register_map);
3412 set_ia32_out_req_all(res, out_reg_reqs);
3413 set_ia32_in_req_all(res, in_reg_reqs);
3415 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3420 /********************************************
3423 * | |__ ___ _ __ ___ __| | ___ ___
3424 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3425 * | |_) | __/ | | | (_) | (_| | __/\__ \
3426 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3428 ********************************************/
3431 * Transforms a FrameAddr into an ia32 Add.
3433 static ir_node *gen_be_FrameAddr(ir_node *node) {
3434 ir_node *block = be_transform_node(get_nodes_block(node));
3435 ir_node *op = be_get_FrameAddr_frame(node);
3436 ir_node *new_op = be_transform_node(op);
3437 ir_graph *irg = current_ir_graph;
3438 dbg_info *dbgi = get_irn_dbg_info(node);
3439 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3442 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3443 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3444 set_ia32_use_frame(res);
3446 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3452 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3454 static ir_node *gen_be_Return(ir_node *node) {
3455 ir_graph *irg = current_ir_graph;
3456 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3457 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3458 ir_entity *ent = get_irg_entity(irg);
3459 ir_type *tp = get_entity_type(ent);
3464 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3465 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3468 int pn_ret_val, pn_ret_mem, arity, i;
3470 assert(ret_val != NULL);
3471 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3472 return be_duplicate_node(node);
3475 res_type = get_method_res_type(tp, 0);
3477 if (! is_Primitive_type(res_type)) {
3478 return be_duplicate_node(node);
3481 mode = get_type_mode(res_type);
3482 if (! mode_is_float(mode)) {
3483 return be_duplicate_node(node);
3486 assert(get_method_n_ress(tp) == 1);
3488 pn_ret_val = get_Proj_proj(ret_val);
3489 pn_ret_mem = get_Proj_proj(ret_mem);
3491 /* get the Barrier */
3492 barrier = get_Proj_pred(ret_val);
3494 /* get result input of the Barrier */
3495 ret_val = get_irn_n(barrier, pn_ret_val);
3496 new_ret_val = be_transform_node(ret_val);
3498 /* get memory input of the Barrier */
3499 ret_mem = get_irn_n(barrier, pn_ret_mem);
3500 new_ret_mem = be_transform_node(ret_mem);
3502 frame = get_irg_frame(irg);
3504 dbgi = get_irn_dbg_info(barrier);
3505 block = be_transform_node(get_nodes_block(barrier));
3507 noreg = ia32_new_NoReg_gp(env_cg);
3509 /* store xmm0 onto stack */
3510 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3511 new_ret_mem, new_ret_val);
3512 set_ia32_ls_mode(sse_store, mode);
3513 set_ia32_op_type(sse_store, ia32_AddrModeD);
3514 set_ia32_use_frame(sse_store);
3516 /* load into x87 register */
3517 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3518 set_ia32_op_type(fld, ia32_AddrModeS);
3519 set_ia32_use_frame(fld);
3521 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3522 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3524 /* create a new barrier */
3525 arity = get_irn_arity(barrier);
3526 in = alloca(arity * sizeof(in[0]));
3527 for (i = 0; i < arity; ++i) {
3530 if (i == pn_ret_val) {
3532 } else if (i == pn_ret_mem) {
3535 ir_node *in = get_irn_n(barrier, i);
3536 new_in = be_transform_node(in);
3541 new_barrier = new_ir_node(dbgi, irg, block,
3542 get_irn_op(barrier), get_irn_mode(barrier),
3544 copy_node_attr(barrier, new_barrier);
3545 be_duplicate_deps(barrier, new_barrier);
3546 be_set_transformed_node(barrier, new_barrier);
3547 mark_irn_visited(barrier);
3549 /* transform normally */
3550 return be_duplicate_node(node);
3554 * Transform a be_AddSP into an ia32_SubSP.
3556 static ir_node *gen_be_AddSP(ir_node *node)
3558 ir_node *src_block = get_nodes_block(node);
3559 ir_node *new_block = be_transform_node(src_block);
3560 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3561 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3562 ir_graph *irg = current_ir_graph;
3563 dbg_info *dbgi = get_irn_dbg_info(node);
3565 ia32_address_mode_t am;
3566 ia32_address_t *addr = &am.addr;
3567 match_flags_t flags = 0;
3569 match_arguments(&am, src_block, sp, sz, flags);
3571 new_node = new_rd_ia32_SubSP(dbgi, irg, new_block, addr->base, addr->index,
3572 addr->mem, am.new_op1, am.new_op2);
3573 set_am_attributes(new_node, &am);
3574 /* we can't use source address mode anymore when using immediates */
3575 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3576 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3577 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3579 new_node = fix_mem_proj(new_node, &am);
3585 * Transform a be_SubSP into an ia32_AddSP
3587 static ir_node *gen_be_SubSP(ir_node *node)
3589 ir_node *src_block = get_nodes_block(node);
3590 ir_node *new_block = be_transform_node(src_block);
3591 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3592 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3593 ir_graph *irg = current_ir_graph;
3594 dbg_info *dbgi = get_irn_dbg_info(node);
3596 ia32_address_mode_t am;
3597 ia32_address_t *addr = &am.addr;
3598 match_flags_t flags = 0;
3600 match_arguments(&am, src_block, sp, sz, flags);
3602 new_node = new_rd_ia32_AddSP(dbgi, irg, new_block, addr->base, addr->index,
3603 addr->mem, am.new_op1, am.new_op2);
3604 set_am_attributes(new_node, &am);
3605 /* we can't use source address mode anymore when using immediates */
3606 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3607 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3608 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3610 new_node = fix_mem_proj(new_node, &am);
3616 * This function just sets the register for the Unknown node
3617 * as this is not done during register allocation because Unknown
3618 * is an "ignore" node.
3620 static ir_node *gen_Unknown(ir_node *node) {
3621 ir_mode *mode = get_irn_mode(node);
3623 if (mode_is_float(mode)) {
3624 if (USE_SSE2(env_cg)) {
3625 return ia32_new_Unknown_xmm(env_cg);
3627 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3628 ir_graph *irg = current_ir_graph;
3629 dbg_info *dbgi = get_irn_dbg_info(node);
3630 ir_node *block = get_irg_start_block(irg);
3631 return new_rd_ia32_vfldz(dbgi, irg, block);
3633 } else if (mode_needs_gp_reg(mode)) {
3634 return ia32_new_Unknown_gp(env_cg);
3636 assert(0 && "unsupported Unknown-Mode");
3643 * Change some phi modes
3645 static ir_node *gen_Phi(ir_node *node) {
3646 ir_node *block = be_transform_node(get_nodes_block(node));
3647 ir_graph *irg = current_ir_graph;
3648 dbg_info *dbgi = get_irn_dbg_info(node);
3649 ir_mode *mode = get_irn_mode(node);
3652 if(mode_needs_gp_reg(mode)) {
3653 /* we shouldn't have any 64bit stuff around anymore */
3654 assert(get_mode_size_bits(mode) <= 32);
3655 /* all integer operations are on 32bit registers now */
3657 } else if(mode_is_float(mode)) {
3658 if (USE_SSE2(env_cg)) {
3665 /* phi nodes allow loops, so we use the old arguments for now
3666 * and fix this later */
3667 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3668 get_irn_in(node) + 1);
3669 copy_node_attr(node, phi);
3670 be_duplicate_deps(node, phi);
3672 be_set_transformed_node(node, phi);
3673 be_enqueue_preds(node);
3681 static ir_node *gen_IJmp(ir_node *node)
3683 ir_node *block = get_nodes_block(node);
3684 ir_node *new_block = be_transform_node(block);
3685 ir_graph *irg = current_ir_graph;
3686 dbg_info *dbgi = get_irn_dbg_info(node);
3687 ir_node *op = get_IJmp_target(node);
3689 ia32_address_mode_t am;
3690 ia32_address_t *addr = &am.addr;
3691 match_flags_t flags;
3693 flags = match_force_32bit_op | match_no_immediate;
3695 match_arguments(&am, block, NULL, op, flags);
3697 new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index,
3698 addr->mem, am.new_op2);
3699 set_am_attributes(new_node, &am);
3700 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3702 new_node = fix_mem_proj(new_node, &am);
3708 /**********************************************************************
3711 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3712 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3713 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3714 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3716 **********************************************************************/
3718 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3720 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3723 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3724 ir_node *val, ir_node *mem);
3727 * Transforms a lowered Load into a "real" one.
3729 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3731 ir_node *block = be_transform_node(get_nodes_block(node));
3732 ir_node *ptr = get_irn_n(node, 0);
3733 ir_node *new_ptr = be_transform_node(ptr);
3734 ir_node *mem = get_irn_n(node, 1);
3735 ir_node *new_mem = be_transform_node(mem);
3736 ir_graph *irg = current_ir_graph;
3737 dbg_info *dbgi = get_irn_dbg_info(node);
3738 ir_mode *mode = get_ia32_ls_mode(node);
3739 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3742 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3744 set_ia32_op_type(new_op, ia32_AddrModeS);
3745 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3746 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3747 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3748 if (is_ia32_am_sc_sign(node))
3749 set_ia32_am_sc_sign(new_op);
3750 set_ia32_ls_mode(new_op, mode);
3751 if (is_ia32_use_frame(node)) {
3752 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3753 set_ia32_use_frame(new_op);
3756 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3762 * Transforms a lowered Store into a "real" one.
3764 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3766 ir_node *block = be_transform_node(get_nodes_block(node));
3767 ir_node *ptr = get_irn_n(node, 0);
3768 ir_node *new_ptr = be_transform_node(ptr);
3769 ir_node *val = get_irn_n(node, 1);
3770 ir_node *new_val = be_transform_node(val);
3771 ir_node *mem = get_irn_n(node, 2);
3772 ir_node *new_mem = be_transform_node(mem);
3773 ir_graph *irg = current_ir_graph;
3774 dbg_info *dbgi = get_irn_dbg_info(node);
3775 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3776 ir_mode *mode = get_ia32_ls_mode(node);
3780 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3782 am_offs = get_ia32_am_offs_int(node);
3783 add_ia32_am_offs_int(new_op, am_offs);
3785 set_ia32_op_type(new_op, ia32_AddrModeD);
3786 set_ia32_ls_mode(new_op, mode);
3787 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3788 set_ia32_use_frame(new_op);
3790 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3797 * Transforms an ia32_l_XXX into a "real" XXX node
3799 * @param node The node to transform
3800 * @return the created ia32 XXX node
3802 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3803 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3804 return gen_shift_binop(node, get_irn_n(node, 0), \
3805 get_irn_n(node, 1), new_rd_ia32_##op); \
3808 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3809 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3810 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3812 static ir_node *gen_ia32_l_Add(ir_node *node) {
3813 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3814 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3815 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, match_commutative);
3817 if(is_Proj(lowered)) {
3818 lowered = get_Proj_pred(lowered);
3820 assert(is_ia32_Add(lowered));
3821 set_irn_mode(lowered, mode_T);
3827 static ir_node *gen_ia32_l_Adc(ir_node *node)
3829 return gen_binop_flags(node, new_rd_ia32_Adc, match_commutative);
3833 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3835 * @param node The node to transform
3836 * @return the created ia32 Neg node
3838 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3839 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3843 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3845 * @param node The node to transform
3846 * @return the created ia32 vfild node
3848 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3849 return gen_lowered_Load(node, new_rd_ia32_vfild);
3853 * Transforms an ia32_l_Load into a "real" ia32_Load node
3855 * @param node The node to transform
3856 * @return the created ia32 Load node
3858 static ir_node *gen_ia32_l_Load(ir_node *node) {
3859 return gen_lowered_Load(node, new_rd_ia32_Load);
3863 * Transforms an ia32_l_Store into a "real" ia32_Store node
3865 * @param node The node to transform
3866 * @return the created ia32 Store node
3868 static ir_node *gen_ia32_l_Store(ir_node *node) {
3869 return gen_lowered_Store(node, new_rd_ia32_Store);
3873 * Transforms a l_vfist into a "real" vfist node.
3875 * @param node The node to transform
3876 * @return the created ia32 vfist node
3878 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3879 ir_node *block = be_transform_node(get_nodes_block(node));
3880 ir_node *ptr = get_irn_n(node, 0);
3881 ir_node *new_ptr = be_transform_node(ptr);
3882 ir_node *val = get_irn_n(node, 1);
3883 ir_node *new_val = be_transform_node(val);
3884 ir_node *mem = get_irn_n(node, 2);
3885 ir_node *new_mem = be_transform_node(mem);
3886 ir_graph *irg = current_ir_graph;
3887 dbg_info *dbgi = get_irn_dbg_info(node);
3888 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3889 ir_mode *mode = get_ia32_ls_mode(node);
3890 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3894 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3895 new_val, trunc_mode);
3897 am_offs = get_ia32_am_offs_int(node);
3898 add_ia32_am_offs_int(new_op, am_offs);
3900 set_ia32_op_type(new_op, ia32_AddrModeD);
3901 set_ia32_ls_mode(new_op, mode);
3902 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3903 set_ia32_use_frame(new_op);
3905 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3911 * Transforms a l_MulS into a "real" MulS node.
3913 * @return the created ia32 Mul node
3915 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3916 ir_node *left = get_binop_left(node);
3917 ir_node *right = get_binop_right(node);
3919 return gen_binop(node, left, right, new_rd_ia32_Mul,
3920 match_commutative | match_no_immediate);
3924 * Transforms a l_IMulS into a "real" IMul1OPS node.
3926 * @return the created ia32 IMul1OP node
3928 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3929 ir_node *left = get_binop_left(node);
3930 ir_node *right = get_binop_right(node);
3932 return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
3933 match_commutative | match_no_immediate);
3936 static ir_node *gen_ia32_l_Sub(ir_node *node) {
3937 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
3938 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
3939 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, 0);
3941 if(is_Proj(lowered)) {
3942 lowered = get_Proj_pred(lowered);
3944 assert(is_ia32_Sub(lowered));
3945 set_irn_mode(lowered, mode_T);
3951 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
3952 return gen_binop_flags(node, new_rd_ia32_Sbb, 0);
3956 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3957 * op1 - target to be shifted
3958 * op2 - contains bits to be shifted into target
3960 * Only op3 can be an immediate.
3962 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3963 ir_node *op2, ir_node *count)
3965 ir_node *block = be_transform_node(get_nodes_block(node));
3966 ir_node *new_op = NULL;
3967 ir_graph *irg = current_ir_graph;
3968 dbg_info *dbgi = get_irn_dbg_info(node);
3969 ir_node *new_op1 = be_transform_node(op1);
3970 ir_node *new_op2 = be_transform_node(op2);
3971 ir_node *new_count = create_immediate_or_transform(count, 'I');
3973 /* TODO proper AM support */
3975 if (is_ia32_l_ShlD(node))
3976 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3978 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3980 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3985 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3986 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3987 get_irn_n(node, 1), get_irn_n(node, 2));
3990 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3991 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3992 get_irn_n(node, 1), get_irn_n(node, 2));
3996 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3998 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3999 ir_node *block = be_transform_node(get_nodes_block(node));
4000 ir_node *val = get_irn_n(node, 1);
4001 ir_node *new_val = be_transform_node(val);
4002 ia32_code_gen_t *cg = env_cg;
4003 ir_node *res = NULL;
4004 ir_graph *irg = current_ir_graph;
4006 ir_node *noreg, *new_ptr, *new_mem;
4013 mem = get_irn_n(node, 2);
4014 new_mem = be_transform_node(mem);
4015 ptr = get_irn_n(node, 0);
4016 new_ptr = be_transform_node(ptr);
4017 noreg = ia32_new_NoReg_gp(cg);
4018 dbgi = get_irn_dbg_info(node);
4020 /* Store x87 -> MEM */
4021 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
4022 get_ia32_ls_mode(node));
4023 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4024 set_ia32_use_frame(res);
4025 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
4026 set_ia32_op_type(res, ia32_AddrModeD);
4028 /* Load MEM -> SSE */
4029 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
4030 get_ia32_ls_mode(node));
4031 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4032 set_ia32_use_frame(res);
4033 set_ia32_op_type(res, ia32_AddrModeS);
4034 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
4040 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
4042 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
4043 ir_node *block = be_transform_node(get_nodes_block(node));
4044 ir_node *val = get_irn_n(node, 1);
4045 ir_node *new_val = be_transform_node(val);
4046 ia32_code_gen_t *cg = env_cg;
4047 ir_graph *irg = current_ir_graph;
4048 ir_node *res = NULL;
4049 ir_entity *fent = get_ia32_frame_ent(node);
4050 ir_mode *lsmode = get_ia32_ls_mode(node);
4052 ir_node *noreg, *new_ptr, *new_mem;
4056 if (! USE_SSE2(cg)) {
4057 /* SSE unit is not used -> skip this node. */
4061 ptr = get_irn_n(node, 0);
4062 new_ptr = be_transform_node(ptr);
4063 mem = get_irn_n(node, 2);
4064 new_mem = be_transform_node(mem);
4065 noreg = ia32_new_NoReg_gp(cg);
4066 dbgi = get_irn_dbg_info(node);
4068 /* Store SSE -> MEM */
4069 if (is_ia32_xLoad(skip_Proj(new_val))) {
4070 ir_node *ld = skip_Proj(new_val);
4072 /* we can vfld the value directly into the fpu */
4073 fent = get_ia32_frame_ent(ld);
4074 ptr = get_irn_n(ld, 0);
4075 offs = get_ia32_am_offs_int(ld);
4077 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
4079 set_ia32_frame_ent(res, fent);
4080 set_ia32_use_frame(res);
4081 set_ia32_ls_mode(res, lsmode);
4082 set_ia32_op_type(res, ia32_AddrModeD);
4086 /* Load MEM -> x87 */
4087 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4088 set_ia32_frame_ent(res, fent);
4089 set_ia32_use_frame(res);
4090 add_ia32_am_offs_int(res, offs);
4091 set_ia32_op_type(res, ia32_AddrModeS);
4092 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4097 /*********************************************************
4100 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
4101 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
4102 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4103 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4105 *********************************************************/
4108 * the BAD transformer.
4110 static ir_node *bad_transform(ir_node *node) {
4111 panic("No transform function for %+F available.\n", node);
4116 * Transform the Projs of an AddSP.
4118 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4119 ir_node *block = be_transform_node(get_nodes_block(node));
4120 ir_node *pred = get_Proj_pred(node);
4121 ir_node *new_pred = be_transform_node(pred);
4122 ir_graph *irg = current_ir_graph;
4123 dbg_info *dbgi = get_irn_dbg_info(node);
4124 long proj = get_Proj_proj(node);
4126 if (proj == pn_be_AddSP_sp) {
4127 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4128 pn_ia32_SubSP_stack);
4129 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4131 } else if(proj == pn_be_AddSP_res) {
4132 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4133 pn_ia32_SubSP_addr);
4134 } else if (proj == pn_be_AddSP_M) {
4135 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4139 return new_rd_Unknown(irg, get_irn_mode(node));
4143 * Transform the Projs of a SubSP.
4145 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4146 ir_node *block = be_transform_node(get_nodes_block(node));
4147 ir_node *pred = get_Proj_pred(node);
4148 ir_node *new_pred = be_transform_node(pred);
4149 ir_graph *irg = current_ir_graph;
4150 dbg_info *dbgi = get_irn_dbg_info(node);
4151 long proj = get_Proj_proj(node);
4153 if (proj == pn_be_SubSP_sp) {
4154 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4155 pn_ia32_AddSP_stack);
4156 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4158 } else if (proj == pn_be_SubSP_M) {
4159 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4163 return new_rd_Unknown(irg, get_irn_mode(node));
4167 * Transform and renumber the Projs from a Load.
4169 static ir_node *gen_Proj_Load(ir_node *node) {
4171 ir_node *block = be_transform_node(get_nodes_block(node));
4172 ir_node *pred = get_Proj_pred(node);
4173 ir_graph *irg = current_ir_graph;
4174 dbg_info *dbgi = get_irn_dbg_info(node);
4175 long proj = get_Proj_proj(node);
4178 /* loads might be part of source address mode matches, so we don't
4179 transform the ProjMs yet (with the exception of loads whose result is
4182 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4185 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4187 /* this is needed, because sometimes we have loops that are only
4188 reachable through the ProjM */
4189 be_enqueue_preds(node);
4190 /* do it in 2 steps, to silence firm verifier */
4191 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4192 set_Proj_proj(res, pn_ia32_Load_M);
4196 /* renumber the proj */
4197 new_pred = be_transform_node(pred);
4198 if (is_ia32_Load(new_pred)) {
4199 if (proj == pn_Load_res) {
4200 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4202 } else if (proj == pn_Load_M) {
4203 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4206 } else if(is_ia32_Conv_I2I(new_pred)) {
4207 set_irn_mode(new_pred, mode_T);
4208 if (proj == pn_Load_res) {
4209 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4210 } else if (proj == pn_Load_M) {
4211 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4213 } else if (is_ia32_xLoad(new_pred)) {
4214 if (proj == pn_Load_res) {
4215 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4217 } else if (proj == pn_Load_M) {
4218 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4221 } else if (is_ia32_vfld(new_pred)) {
4222 if (proj == pn_Load_res) {
4223 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4225 } else if (proj == pn_Load_M) {
4226 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4230 /* can happen for ProJMs when source address mode happened for the
4233 /* however it should not be the result proj, as that would mean the
4234 load had multiple users and should not have been used for
4236 if(proj != pn_Load_M) {
4237 panic("internal error: transformed node not a Load");
4239 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4243 return new_rd_Unknown(irg, get_irn_mode(node));
4247 * Transform and renumber the Projs from a DivMod like instruction.
4249 static ir_node *gen_Proj_DivMod(ir_node *node) {
4250 ir_node *block = be_transform_node(get_nodes_block(node));
4251 ir_node *pred = get_Proj_pred(node);
4252 ir_node *new_pred = be_transform_node(pred);
4253 ir_graph *irg = current_ir_graph;
4254 dbg_info *dbgi = get_irn_dbg_info(node);
4255 ir_mode *mode = get_irn_mode(node);
4256 long proj = get_Proj_proj(node);
4258 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4260 switch (get_irn_opcode(pred)) {
4264 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4266 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4274 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4276 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4284 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4285 case pn_DivMod_res_div:
4286 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4287 case pn_DivMod_res_mod:
4288 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4298 return new_rd_Unknown(irg, mode);
4302 * Transform and renumber the Projs from a CopyB.
4304 static ir_node *gen_Proj_CopyB(ir_node *node) {
4305 ir_node *block = be_transform_node(get_nodes_block(node));
4306 ir_node *pred = get_Proj_pred(node);
4307 ir_node *new_pred = be_transform_node(pred);
4308 ir_graph *irg = current_ir_graph;
4309 dbg_info *dbgi = get_irn_dbg_info(node);
4310 ir_mode *mode = get_irn_mode(node);
4311 long proj = get_Proj_proj(node);
4314 case pn_CopyB_M_regular:
4315 if (is_ia32_CopyB_i(new_pred)) {
4316 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4317 } else if (is_ia32_CopyB(new_pred)) {
4318 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4326 return new_rd_Unknown(irg, mode);
4330 * Transform and renumber the Projs from a Quot.
4332 static ir_node *gen_Proj_Quot(ir_node *node) {
4333 ir_node *block = be_transform_node(get_nodes_block(node));
4334 ir_node *pred = get_Proj_pred(node);
4335 ir_node *new_pred = be_transform_node(pred);
4336 ir_graph *irg = current_ir_graph;
4337 dbg_info *dbgi = get_irn_dbg_info(node);
4338 ir_mode *mode = get_irn_mode(node);
4339 long proj = get_Proj_proj(node);
4343 if (is_ia32_xDiv(new_pred)) {
4344 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4345 } else if (is_ia32_vfdiv(new_pred)) {
4346 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4350 if (is_ia32_xDiv(new_pred)) {
4351 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4352 } else if (is_ia32_vfdiv(new_pred)) {
4353 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4361 return new_rd_Unknown(irg, mode);
4365 * Transform the Thread Local Storage Proj.
4367 static ir_node *gen_Proj_tls(ir_node *node) {
4368 ir_node *block = be_transform_node(get_nodes_block(node));
4369 ir_graph *irg = current_ir_graph;
4370 dbg_info *dbgi = NULL;
4371 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4376 static ir_node *gen_be_Call(ir_node *node) {
4377 ir_node *res = be_duplicate_node(node);
4378 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4383 static ir_node *gen_be_IncSP(ir_node *node) {
4384 ir_node *res = be_duplicate_node(node);
4385 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4391 * Transform the Projs from a be_Call.
4393 static ir_node *gen_Proj_be_Call(ir_node *node) {
4394 ir_node *block = be_transform_node(get_nodes_block(node));
4395 ir_node *call = get_Proj_pred(node);
4396 ir_node *new_call = be_transform_node(call);
4397 ir_graph *irg = current_ir_graph;
4398 dbg_info *dbgi = get_irn_dbg_info(node);
4399 ir_type *method_type = be_Call_get_type(call);
4400 int n_res = get_method_n_ress(method_type);
4401 long proj = get_Proj_proj(node);
4402 ir_mode *mode = get_irn_mode(node);
4404 const arch_register_class_t *cls;
4406 /* The following is kinda tricky: If we're using SSE, then we have to
4407 * move the result value of the call in floating point registers to an
4408 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4409 * after the call, we have to make sure to correctly make the
4410 * MemProj and the result Proj use these 2 nodes
4412 if (proj == pn_be_Call_M_regular) {
4413 // get new node for result, are we doing the sse load/store hack?
4414 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4415 ir_node *call_res_new;
4416 ir_node *call_res_pred = NULL;
4418 if (call_res != NULL) {
4419 call_res_new = be_transform_node(call_res);
4420 call_res_pred = get_Proj_pred(call_res_new);
4423 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4424 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4425 pn_be_Call_M_regular);
4427 assert(is_ia32_xLoad(call_res_pred));
4428 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4432 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4433 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4434 && USE_SSE2(env_cg)) {
4436 ir_node *frame = get_irg_frame(irg);
4437 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4439 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4442 /* in case there is no memory output: create one to serialize the copy
4444 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4445 pn_be_Call_M_regular);
4446 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4447 pn_be_Call_first_res);
4449 /* store st(0) onto stack */
4450 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4452 set_ia32_op_type(fstp, ia32_AddrModeD);
4453 set_ia32_use_frame(fstp);
4455 /* load into SSE register */
4456 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4458 set_ia32_op_type(sse_load, ia32_AddrModeS);
4459 set_ia32_use_frame(sse_load);
4461 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4467 /* transform call modes */
4468 if (mode_is_data(mode)) {
4469 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4473 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4477 * Transform the Projs from a Cmp.
4479 static ir_node *gen_Proj_Cmp(ir_node *node)
4481 /* normally Cmps are processed when looking at Cond nodes, but this case
4482 * can happen in complicated Psi conditions */
4483 dbg_info *dbgi = get_irn_dbg_info(node);
4484 ir_node *block = get_nodes_block(node);
4485 ir_node *new_block = be_transform_node(block);
4486 ir_node *cmp = get_Proj_pred(node);
4487 ir_node *new_cmp = be_transform_node(cmp);
4488 long pnc = get_Proj_proj(node);
4491 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node, 0);
4497 * Transform and potentially renumber Proj nodes.
4499 static ir_node *gen_Proj(ir_node *node) {
4500 ir_graph *irg = current_ir_graph;
4501 dbg_info *dbgi = get_irn_dbg_info(node);
4502 ir_node *pred = get_Proj_pred(node);
4503 long proj = get_Proj_proj(node);
4505 if (is_Store(pred)) {
4506 if (proj == pn_Store_M) {
4507 return be_transform_node(pred);
4510 return new_r_Bad(irg);
4512 } else if (is_Load(pred)) {
4513 return gen_Proj_Load(node);
4514 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4515 return gen_Proj_DivMod(node);
4516 } else if (is_CopyB(pred)) {
4517 return gen_Proj_CopyB(node);
4518 } else if (is_Quot(pred)) {
4519 return gen_Proj_Quot(node);
4520 } else if (be_is_SubSP(pred)) {
4521 return gen_Proj_be_SubSP(node);
4522 } else if (be_is_AddSP(pred)) {
4523 return gen_Proj_be_AddSP(node);
4524 } else if (be_is_Call(pred)) {
4525 return gen_Proj_be_Call(node);
4526 } else if (is_Cmp(pred)) {
4527 return gen_Proj_Cmp(node);
4528 } else if (get_irn_op(pred) == op_Start) {
4529 if (proj == pn_Start_X_initial_exec) {
4530 ir_node *block = get_nodes_block(pred);
4533 /* we exchange the ProjX with a jump */
4534 block = be_transform_node(block);
4535 jump = new_rd_Jmp(dbgi, irg, block);
4538 if (node == be_get_old_anchor(anchor_tls)) {
4539 return gen_Proj_tls(node);
4542 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4546 ir_node *new_pred = be_transform_node(pred);
4547 ir_node *block = be_transform_node(get_nodes_block(node));
4548 ir_mode *mode = get_irn_mode(node);
4549 if (mode_needs_gp_reg(mode)) {
4550 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4551 get_Proj_proj(node));
4552 #ifdef DEBUG_libfirm
4553 new_proj->node_nr = node->node_nr;
4559 return be_duplicate_node(node);
4563 * Enters all transform functions into the generic pointer
4565 static void register_transformers(void)
4569 /* first clear the generic function pointer for all ops */
4570 clear_irp_opcodes_generic_func();
4572 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4573 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4611 /* transform ops from intrinsic lowering */
4628 GEN(ia32_l_X87toSSE);
4629 GEN(ia32_l_SSEtoX87);
4635 /* we should never see these nodes */
4650 /* handle generic backend nodes */
4659 op_Mulh = get_op_Mulh();
4668 * Pre-transform all unknown and noreg nodes.
4670 static void ia32_pretransform_node(void *arch_cg) {
4671 ia32_code_gen_t *cg = arch_cg;
4673 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4674 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4675 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4676 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4677 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4678 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4683 * Walker, checks if all ia32 nodes producing more than one result have
4684 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4686 static void add_missing_keep_walker(ir_node *node, void *data)
4689 unsigned found_projs = 0;
4690 const ir_edge_t *edge;
4691 ir_mode *mode = get_irn_mode(node);
4696 if(!is_ia32_irn(node))
4699 n_outs = get_ia32_n_res(node);
4702 if(is_ia32_SwitchJmp(node))
4705 assert(n_outs < (int) sizeof(unsigned) * 8);
4706 foreach_out_edge(node, edge) {
4707 ir_node *proj = get_edge_src_irn(edge);
4708 int pn = get_Proj_proj(proj);
4710 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4711 found_projs |= 1 << pn;
4715 /* are keeps missing? */
4717 for(i = 0; i < n_outs; ++i) {
4720 const arch_register_req_t *req;
4721 const arch_register_class_t *class;
4723 if(found_projs & (1 << i)) {
4727 req = get_ia32_out_req(node, i);
4732 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4736 block = get_nodes_block(node);
4737 in[0] = new_r_Proj(current_ir_graph, block, node,
4738 arch_register_class_mode(class), i);
4739 if(last_keep != NULL) {
4740 be_Keep_add_node(last_keep, class, in[0]);
4742 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4743 if(sched_is_scheduled(node)) {
4744 sched_add_after(node, last_keep);
4751 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4754 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4756 ir_graph *irg = be_get_birg_irg(cg->birg);
4757 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4760 /* do the transformation */
4761 void ia32_transform_graph(ia32_code_gen_t *cg) {
4763 ir_graph *irg = cg->irg;
4765 /* TODO: look at cpu and fill transform config in with that... */
4766 transform_config.use_incdec = 1;
4767 transform_config.use_sse2 = 0;
4768 transform_config.use_ffreep = 0;
4769 transform_config.use_ftst = 0;
4770 transform_config.use_femms = 0;
4771 transform_config.use_fucomi = 1;
4772 transform_config.use_cmov = 1;
4774 register_transformers();
4776 initial_fpcw = NULL;
4778 heights = heights_new(irg);
4779 calculate_non_address_mode_nodes(irg);
4781 /* the transform phase is not safe for CSE (yet) because several nodes get
4782 * attributes set after their creation */
4783 cse_last = get_opt_cse();
4786 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4788 set_opt_cse(cse_last);
4790 free_non_address_mode_nodes();
4791 heights_free(heights);
4795 void ia32_init_transform(void)
4797 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");