2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * This file implements the IR transformation from firm into ia32-Firm.
22 * @author Christian Wuerdig
33 #include "irgraph_t.h"
38 #include "iredges_t.h"
49 #include "archop.h" /* we need this for Min and Max nodes */
56 #include "../benode_t.h"
57 #include "../besched.h"
59 #include "../beutil.h"
60 #include "../beirg_t.h"
62 #include "bearch_ia32_t.h"
63 #include "ia32_nodes_attr.h"
64 #include "ia32_transform.h"
65 #include "ia32_new_nodes.h"
66 #include "ia32_map_regs.h"
67 #include "ia32_dbg_stat.h"
68 #include "ia32_optimize.h"
69 #include "ia32_util.h"
71 #include "gen_ia32_regalloc_if.h"
73 #define SFP_SIGN "0x80000000"
74 #define DFP_SIGN "0x8000000000000000"
75 #define SFP_ABS "0x7FFFFFFF"
76 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
78 #define TP_SFP_SIGN "ia32_sfp_sign"
79 #define TP_DFP_SIGN "ia32_dfp_sign"
80 #define TP_SFP_ABS "ia32_sfp_abs"
81 #define TP_DFP_ABS "ia32_dfp_abs"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
88 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
89 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
91 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
93 typedef struct ia32_transform_env_t {
94 ir_graph *irg; /**< The irg, the node should be created in */
95 ia32_code_gen_t *cg; /**< The code generator */
96 int visited; /**< visited count that indicates whether a
97 node is already transformed */
98 pdeq *worklist; /**< worklist of nodes that still need to be
100 ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/
101 } ia32_transform_env_t;
103 extern ir_op *get_op_Mulh(void);
105 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
106 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
107 ir_node *op2, ir_node *mem);
109 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
110 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
113 typedef ir_node *(transform_func)(ia32_transform_env_t *env, ir_node *node);
115 /****************************************************************************************************
117 * | | | | / _| | | (_)
118 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
119 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
120 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
121 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
123 ****************************************************************************************************/
125 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node);
126 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node);
127 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
130 static INLINE int mode_needs_gp_reg(ir_mode *mode)
132 if(mode == mode_fpcw)
135 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
138 static INLINE void set_new_node(ir_node *old_node, ir_node *new_node)
140 set_irn_link(old_node, new_node);
143 static INLINE ir_node *get_new_node(ir_node *old_node)
145 assert(irn_visited(old_node));
146 return (ir_node*) get_irn_link(old_node);
150 * Returns 1 if irn is a Const representing 0, 0 otherwise
152 static INLINE int is_ia32_Const_0(ir_node *irn) {
153 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
154 && tarval_is_null(get_ia32_Immop_tarval(irn));
158 * Returns 1 if irn is a Const representing 1, 0 otherwise
160 static INLINE int is_ia32_Const_1(ir_node *irn) {
161 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
162 && tarval_is_one(get_ia32_Immop_tarval(irn));
166 * Collects all Projs of a node into the node array. Index is the projnum.
167 * BEWARE: The caller has to assure the appropriate array size!
169 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
170 const ir_edge_t *edge;
171 assert(get_irn_mode(irn) == mode_T && "need mode_T");
173 memset(projs, 0, size * sizeof(projs[0]));
175 foreach_out_edge(irn, edge) {
176 ir_node *proj = get_edge_src_irn(edge);
177 int proj_proj = get_Proj_proj(proj);
178 assert(proj_proj < size);
179 projs[proj_proj] = proj;
184 * Renumbers the proj having pn_old in the array tp pn_new
185 * and removes the proj from the array.
187 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
188 fprintf(stderr, "Warning: renumber_Proj used!\n");
190 set_Proj_proj(projs[pn_old], pn_new);
191 projs[pn_old] = NULL;
196 * creates a unique ident by adding a number to a tag
198 * @param tag the tag string, must contain a %d if a number
201 static ident *unique_id(const char *tag)
203 static unsigned id = 0;
206 snprintf(str, sizeof(str), tag, ++id);
207 return new_id_from_str(str);
211 * Get a primitive type for a mode.
213 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
215 pmap_entry *e = pmap_find(types, mode);
220 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
221 res = new_type_primitive(new_id_from_str(buf), mode);
222 pmap_insert(types, mode, res);
230 * Get an entity that is initialized with a tarval
232 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
234 tarval *tv = get_Const_tarval(cnst);
235 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
240 ir_mode *mode = get_irn_mode(cnst);
241 ir_type *tp = get_Const_type(cnst);
242 if (tp == firm_unknown_type)
243 tp = get_prim_type(cg->isa->types, mode);
245 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
247 set_entity_ld_ident(res, get_entity_ident(res));
248 set_entity_visibility(res, visibility_local);
249 set_entity_variability(res, variability_constant);
250 set_entity_allocation(res, allocation_static);
252 /* we create a new entity here: It's initialization must resist on the
254 rem = current_ir_graph;
255 current_ir_graph = get_const_code_irg();
256 set_atomic_ent_value(res, new_Const_type(tv, tp));
257 current_ir_graph = rem;
259 pmap_insert(cg->isa->tv_ent, tv, res);
268 * Transforms a Const.
270 static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) {
271 ir_graph *irg = env->irg;
272 dbg_info *dbgi = get_irn_dbg_info(node);
273 ir_mode *mode = get_irn_mode(node);
274 ir_node *block = transform_node(env, get_nodes_block(node));
276 if (mode_is_float(mode)) {
279 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
280 ir_node *nomem = new_NoMem();
284 if (! USE_SSE2(env->cg)) {
285 cnst_classify_t clss = classify_Const(node);
287 if (clss == CNST_NULL) {
288 load = new_rd_ia32_vfldz(dbgi, irg, block);
290 } else if (clss == CNST_ONE) {
291 load = new_rd_ia32_vfld1(dbgi, irg, block);
294 floatent = get_entity_for_tv(env->cg, node);
296 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem);
297 set_ia32_am_support(load, ia32_am_Source);
298 set_ia32_op_type(load, ia32_AddrModeS);
299 set_ia32_am_flavour(load, ia32_am_N);
300 set_ia32_am_sc(load, floatent);
301 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
303 set_ia32_ls_mode(load, mode);
305 floatent = get_entity_for_tv(env->cg, node);
307 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
308 set_ia32_am_support(load, ia32_am_Source);
309 set_ia32_op_type(load, ia32_AddrModeS);
310 set_ia32_am_flavour(load, ia32_am_N);
311 set_ia32_am_sc(load, floatent);
312 set_ia32_ls_mode(load, mode);
314 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
317 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
319 /* Const Nodes before the initial IncSP are a bad idea, because
320 * they could be spilled and we have no SP ready at that point yet
322 if (get_irg_start_block(irg) == block) {
323 add_irn_dep(load, get_irg_frame(irg));
326 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
329 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
332 if (get_irg_start_block(irg) == block) {
333 add_irn_dep(cnst, get_irg_frame(irg));
336 set_ia32_Const_attr(cnst, node);
337 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
342 return new_r_Bad(irg);
346 * Transforms a SymConst.
348 static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) {
349 ir_graph *irg = env->irg;
350 dbg_info *dbgi = get_irn_dbg_info(node);
351 ir_mode *mode = get_irn_mode(node);
352 ir_node *block = transform_node(env, get_nodes_block(node));
355 if (mode_is_float(mode)) {
357 if (USE_SSE2(env->cg))
358 cnst = new_rd_ia32_xConst(dbgi, irg, block);
360 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
361 set_ia32_ls_mode(cnst, mode);
363 cnst = new_rd_ia32_Const(dbgi, irg, block);
366 /* Const Nodes before the initial IncSP are a bad idea, because
367 * they could be spilled and we have no SP ready at that point yet
369 if (get_irg_start_block(irg) == block) {
370 add_irn_dep(cnst, get_irg_frame(irg));
373 set_ia32_Const_attr(cnst, node);
374 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
380 * SSE convert of an integer node into a floating point node.
382 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbgi,
383 ir_graph *irg, ir_node *block,
384 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
386 ir_node *noreg = ia32_new_NoReg_gp(cg);
387 ir_node *nomem = new_rd_NoMem(irg);
388 ir_node *old_pred = get_Cmp_left(old_node);
389 ir_mode *in_mode = get_irn_mode(old_pred);
390 int in_bits = get_mode_size_bits(in_mode);
392 ir_node *conv = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, in, nomem);
393 set_ia32_ls_mode(conv, tgt_mode);
395 set_ia32_am_support(conv, ia32_am_Source);
397 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
403 * SSE convert of an float node into a double node.
405 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbgi,
406 ir_graph *irg, ir_node *block,
407 ir_node *in, ir_node *old_node)
409 ir_node *noreg = ia32_new_NoReg_gp(cg);
410 ir_node *nomem = new_rd_NoMem(irg);
412 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, in, nomem);
413 set_ia32_am_support(conv, ia32_am_Source);
414 set_ia32_ls_mode(conv, mode_xmm);
415 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
420 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
421 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
422 static const struct {
424 const char *ent_name;
425 const char *cnst_str;
426 } names [ia32_known_const_max] = {
427 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
428 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
429 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
430 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
432 static ir_entity *ent_cache[ia32_known_const_max];
434 const char *tp_name, *ent_name, *cnst_str;
442 ent_name = names[kct].ent_name;
443 if (! ent_cache[kct]) {
444 tp_name = names[kct].tp_name;
445 cnst_str = names[kct].cnst_str;
447 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
449 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
450 tp = new_type_primitive(new_id_from_str(tp_name), mode);
451 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
453 set_entity_ld_ident(ent, get_entity_ident(ent));
454 set_entity_visibility(ent, visibility_local);
455 set_entity_variability(ent, variability_constant);
456 set_entity_allocation(ent, allocation_static);
458 /* we create a new entity here: It's initialization must resist on the
460 rem = current_ir_graph;
461 current_ir_graph = get_const_code_irg();
462 cnst = new_Const(mode, tv);
463 current_ir_graph = rem;
465 set_atomic_ent_value(ent, cnst);
467 /* cache the entry */
468 ent_cache[kct] = ent;
471 return ent_cache[kct];
476 * Prints the old node name on cg obst and returns a pointer to it.
478 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
479 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
481 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
482 obstack_1grow(isa->name_obst, 0);
483 return obstack_finish(isa->name_obst);
487 /* determine if one operator is an Imm */
488 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
490 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
492 return is_ia32_Cnst(op2) ? op2 : NULL;
496 /* determine if one operator is not an Imm */
497 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
498 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
501 static void fold_immediate(ia32_transform_env_t *env, ir_node *node, int in1, int in2) {
505 if(! (env->cg->opt & IA32_OPT_IMMOPS))
508 left = get_irn_n(node, in1);
509 right = get_irn_n(node, in2);
510 if(!is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
511 /* we can only set right operand to immediate */
512 if(!is_ia32_commutative(node))
514 /* exchange left/right */
515 set_irn_n(node, in1, right);
516 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
517 copy_ia32_Immop_attr(node, left);
518 } else if(is_ia32_Cnst(right)) {
519 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
520 copy_ia32_Immop_attr(node, right);
525 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
529 * Construct a standard binary operation, set AM and immediate if required.
531 * @param env The transformation environment
532 * @param op1 The first operand
533 * @param op2 The second operand
534 * @param func The node constructor function
535 * @return The constructed ia32 node.
537 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *node,
538 ir_node *op1, ir_node *op2,
539 construct_binop_func *func) {
540 ir_node *new_node = NULL;
541 ir_graph *irg = env->irg;
542 dbg_info *dbgi = get_irn_dbg_info(node);
543 ir_node *block = transform_node(env, get_nodes_block(node));
544 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
545 ir_node *nomem = new_NoMem();
546 ir_node *new_op1 = transform_node(env, op1);
547 ir_node *new_op2 = transform_node(env, op2);
549 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
550 if(func == new_rd_ia32_IMul) {
551 set_ia32_am_support(new_node, ia32_am_Source);
553 set_ia32_am_support(new_node, ia32_am_Full);
556 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
557 if (is_op_commutative(get_irn_op(node))) {
558 set_ia32_commutative(new_node);
560 fold_immediate(env, new_node, 2, 3);
566 * Construct a standard binary operation, set AM and immediate if required.
568 * @param env The transformation environment
569 * @param op1 The first operand
570 * @param op2 The second operand
571 * @param func The node constructor function
572 * @return The constructed ia32 node.
574 static ir_node *gen_binop_float(ia32_transform_env_t *env, ir_node *node,
575 ir_node *op1, ir_node *op2,
576 construct_binop_func *func)
578 ir_node *new_node = NULL;
579 dbg_info *dbgi = get_irn_dbg_info(node);
580 ir_graph *irg = env->irg;
581 ir_mode *mode = get_irn_mode(node);
582 ir_node *block = transform_node(env, get_nodes_block(node));
583 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
584 ir_node *nomem = new_NoMem();
585 ir_node *new_op1 = transform_node(env, op1);
586 ir_node *new_op2 = transform_node(env, op2);
588 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
589 set_ia32_am_support(new_node, ia32_am_Source);
590 if (is_op_commutative(get_irn_op(node))) {
591 set_ia32_commutative(new_node);
593 if (USE_SSE2(env->cg)) {
594 set_ia32_ls_mode(new_node, mode);
597 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
604 * Construct a shift/rotate binary operation, sets AM and immediate if required.
606 * @param env The transformation environment
607 * @param op1 The first operand
608 * @param op2 The second operand
609 * @param func The node constructor function
610 * @return The constructed ia32 node.
612 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node,
613 ir_node *op1, ir_node *op2,
614 construct_binop_func *func) {
615 ir_node *new_op = NULL;
616 dbg_info *dbgi = get_irn_dbg_info(node);
617 ir_graph *irg = env->irg;
618 ir_node *block = transform_node(env, get_nodes_block(node));
619 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
620 ir_node *nomem = new_NoMem();
623 ir_node *new_op1 = transform_node(env, op1);
624 ir_node *new_op2 = transform_node(env, op2);
627 assert(! mode_is_float(get_irn_mode(node))
628 && "Shift/Rotate with float not supported");
630 /* Check if immediate optimization is on and */
631 /* if it's an operation with immediate. */
632 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
633 expr_op = get_expr_op(new_op1, new_op2);
635 assert((expr_op || imm_op) && "invalid operands");
638 /* We have two consts here: not yet supported */
642 /* Limit imm_op within range imm8 */
644 tv = get_ia32_Immop_tarval(imm_op);
647 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
648 set_ia32_Immop_tarval(imm_op, tv);
655 /* integer operations */
657 /* This is shift/rot with const */
658 DB((dbg, LEVEL_1, "Shift/Rot with immediate ..."));
660 new_op = func(dbgi, irg, block, noreg, noreg, expr_op, noreg, nomem);
661 copy_ia32_Immop_attr(new_op, imm_op);
663 /* This is a normal shift/rot */
664 DB((dbg, LEVEL_1, "Shift/Rot binop ..."));
665 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
669 set_ia32_am_support(new_op, ia32_am_Dest);
671 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
673 set_ia32_emit_cl(new_op);
680 * Construct a standard unary operation, set AM and immediate if required.
682 * @param env The transformation environment
683 * @param op The operand
684 * @param func The node constructor function
685 * @return The constructed ia32 node.
687 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *node, ir_node *op,
688 construct_unop_func *func) {
689 ir_node *new_node = NULL;
690 ir_graph *irg = env->irg;
691 dbg_info *dbgi = get_irn_dbg_info(node);
692 ir_node *block = transform_node(env, get_nodes_block(node));
693 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
694 ir_node *nomem = new_NoMem();
695 ir_node *new_op = transform_node(env, op);
697 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
698 DB((dbg, LEVEL_1, "INT unop ..."));
699 set_ia32_am_support(new_node, ia32_am_Dest);
701 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
708 * Creates an ia32 Add.
710 * @param env The transformation environment
711 * @return the created ia32 Add node
713 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) {
714 ir_node *new_op = NULL;
715 ir_graph *irg = env->irg;
716 dbg_info *dbgi = get_irn_dbg_info(node);
717 ir_mode *mode = get_irn_mode(node);
718 ir_node *block = transform_node(env, get_nodes_block(node));
719 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
720 ir_node *nomem = new_NoMem();
721 ir_node *expr_op, *imm_op;
722 ir_node *op1 = get_Add_left(node);
723 ir_node *op2 = get_Add_right(node);
724 ir_node *new_op1 = transform_node(env, op1);
725 ir_node *new_op2 = transform_node(env, op2);
727 /* Check if immediate optimization is on and */
728 /* if it's an operation with immediate. */
729 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
730 expr_op = get_expr_op(new_op1, new_op2);
732 assert((expr_op || imm_op) && "invalid operands");
734 if (mode_is_float(mode)) {
736 if (USE_SSE2(env->cg))
737 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xAdd);
739 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfadd);
744 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
745 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
747 /* No expr_op means, that we have two const - one symconst and */
748 /* one tarval or another symconst - because this case is not */
749 /* covered by constant folding */
750 /* We need to check for: */
751 /* 1) symconst + const -> becomes a LEA */
752 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
753 /* linker doesn't support two symconsts */
755 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
756 /* this is the 2nd case */
757 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
758 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
759 set_ia32_am_flavour(new_op, ia32_am_OB);
760 set_ia32_am_support(new_op, ia32_am_Source);
761 set_ia32_op_type(new_op, ia32_AddrModeS);
763 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
764 } else if (tp1 == ia32_ImmSymConst) {
765 tarval *tv = get_ia32_Immop_tarval(new_op2);
766 long offs = get_tarval_long(tv);
768 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
769 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
771 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
772 add_ia32_am_offs_int(new_op, offs);
773 set_ia32_am_flavour(new_op, ia32_am_O);
774 set_ia32_am_support(new_op, ia32_am_Source);
775 set_ia32_op_type(new_op, ia32_AddrModeS);
776 } else if (tp2 == ia32_ImmSymConst) {
777 tarval *tv = get_ia32_Immop_tarval(new_op1);
778 long offs = get_tarval_long(tv);
780 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
781 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
783 add_ia32_am_offs_int(new_op, offs);
784 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
785 set_ia32_am_flavour(new_op, ia32_am_O);
786 set_ia32_am_support(new_op, ia32_am_Source);
787 set_ia32_op_type(new_op, ia32_AddrModeS);
789 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
790 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
791 tarval *restv = tarval_add(tv1, tv2);
793 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
795 new_op = new_rd_ia32_Const(dbgi, irg, block);
796 set_ia32_Const_tarval(new_op, restv);
797 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
800 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
803 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
804 tarval_classification_t class_tv, class_negtv;
805 tarval *tv = get_ia32_Immop_tarval(imm_op);
807 /* optimize tarvals */
808 class_tv = classify_tarval(tv);
809 class_negtv = classify_tarval(tarval_neg(tv));
811 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
812 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
813 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
814 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
816 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
817 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
818 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
819 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
825 /* This is a normal add */
826 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
829 set_ia32_am_support(new_op, ia32_am_Full);
830 set_ia32_commutative(new_op);
832 fold_immediate(env, new_op, 2, 3);
834 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
840 static ir_node *create_ia32_Mul(ia32_transform_env_t *env, ir_node *node) {
841 ir_graph *irg = env->irg;
842 dbg_info *dbgi = get_irn_dbg_info(node);
843 ir_node *block = transform_node(env, get_nodes_block(node));
844 ir_node *op1 = get_Mul_left(node);
845 ir_node *op2 = get_Mul_right(node);
846 ir_node *new_op1 = transform_node(env, op1);
847 ir_node *new_op2 = transform_node(env, op2);
848 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
849 ir_node *proj_EAX, *proj_EDX, *res;
852 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
853 set_ia32_commutative(res);
854 set_ia32_am_support(res, ia32_am_Source);
856 /* imediates are not supported, so no fold_immediate */
857 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
858 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
862 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
870 * Creates an ia32 Mul.
872 * @param env The transformation environment
873 * @return the created ia32 Mul node
875 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) {
876 ir_node *op1 = get_Mul_left(node);
877 ir_node *op2 = get_Mul_right(node);
878 ir_mode *mode = get_irn_mode(node);
880 if (mode_is_float(mode)) {
882 if (USE_SSE2(env->cg))
883 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul);
885 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul);
888 // for the lower 32bit of the result it doesn't matter whether we use
889 // signed or unsigned multiplication so we use IMul as it has fewer
891 return gen_binop(env, node, op1, op2, new_rd_ia32_IMul);
895 * Creates an ia32 Mulh.
896 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
897 * this result while Mul returns the lower 32 bit.
899 * @param env The transformation environment
900 * @return the created ia32 Mulh node
902 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) {
903 ir_graph *irg = env->irg;
904 dbg_info *dbgi = get_irn_dbg_info(node);
905 ir_node *block = transform_node(env, get_nodes_block(node));
906 ir_node *op1 = get_irn_n(node, 0);
907 ir_node *op2 = get_irn_n(node, 1);
908 ir_node *new_op1 = transform_node(env, op1);
909 ir_node *new_op2 = transform_node(env, op2);
910 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
911 ir_node *proj_EAX, *proj_EDX, *res;
912 ir_mode *mode = get_irn_mode(node);
915 assert(!mode_is_float(mode) && "Mulh with float not supported");
916 if(mode_is_signed(mode)) {
917 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
919 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
922 set_ia32_commutative(res);
923 set_ia32_am_support(res, ia32_am_Source);
925 set_ia32_am_support(res, ia32_am_Source);
927 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
928 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
932 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
940 * Creates an ia32 And.
942 * @param env The transformation environment
943 * @return The created ia32 And node
945 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *node) {
946 ir_node *op1 = get_And_left(node);
947 ir_node *op2 = get_And_right(node);
949 assert (! mode_is_float(get_irn_mode(node)));
950 return gen_binop(env, node, op1, op2, new_rd_ia32_And);
956 * Creates an ia32 Or.
958 * @param env The transformation environment
959 * @return The created ia32 Or node
961 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *node) {
962 ir_node *op1 = get_Or_left(node);
963 ir_node *op2 = get_Or_right(node);
965 assert (! mode_is_float(get_irn_mode(node)));
966 return gen_binop(env, node, op1, op2, new_rd_ia32_Or);
972 * Creates an ia32 Eor.
974 * @param env The transformation environment
975 * @return The created ia32 Eor node
977 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *node) {
978 ir_node *op1 = get_Eor_left(node);
979 ir_node *op2 = get_Eor_right(node);
981 assert(! mode_is_float(get_irn_mode(node)));
982 return gen_binop(env, node, op1, op2, new_rd_ia32_Xor);
988 * Creates an ia32 Max.
990 * @param env The transformation environment
991 * @return the created ia32 Max node
993 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *node) {
994 ir_graph *irg = env->irg;
996 ir_mode *mode = get_irn_mode(node);
997 dbg_info *dbgi = get_irn_dbg_info(node);
998 ir_node *block = transform_node(env, get_nodes_block(node));
999 ir_node *op1 = get_irn_n(node, 0);
1000 ir_node *op2 = get_irn_n(node, 1);
1001 ir_node *new_op1 = transform_node(env, op1);
1002 ir_node *new_op2 = transform_node(env, op2);
1003 ir_mode *op_mode = get_irn_mode(op1);
1005 assert(get_mode_size_bits(mode) == 32);
1007 if (mode_is_float(mode)) {
1009 if (USE_SSE2(env->cg)) {
1010 new_op = gen_binop_float(env, node, new_op1, new_op2, new_rd_ia32_xMax);
1012 panic("Can't create Max node");
1015 long pnc = pn_Cmp_Gt;
1016 if(!mode_is_signed(op_mode)) {
1017 pnc |= ia32_pn_Cmp_Unsigned;
1019 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1020 set_ia32_pncode(new_op, pnc);
1021 set_ia32_am_support(new_op, ia32_am_None);
1023 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1029 * Creates an ia32 Min.
1031 * @param env The transformation environment
1032 * @return the created ia32 Min node
1034 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *node) {
1035 ir_graph *irg = env->irg;
1037 ir_mode *mode = get_irn_mode(node);
1038 dbg_info *dbgi = get_irn_dbg_info(node);
1039 ir_node *block = transform_node(env, get_nodes_block(node));
1040 ir_node *op1 = get_irn_n(node, 0);
1041 ir_node *op2 = get_irn_n(node, 1);
1042 ir_node *new_op1 = transform_node(env, op1);
1043 ir_node *new_op2 = transform_node(env, op2);
1044 ir_mode *op_mode = get_irn_mode(op1);
1046 assert(get_mode_size_bits(mode) == 32);
1048 if (mode_is_float(mode)) {
1050 if (USE_SSE2(env->cg)) {
1051 new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMin);
1053 panic("can't create Min node");
1056 long pnc = pn_Cmp_Lt;
1057 if(!mode_is_signed(op_mode)) {
1058 pnc |= ia32_pn_Cmp_Unsigned;
1060 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1061 set_ia32_pncode(new_op, pnc);
1062 set_ia32_am_support(new_op, ia32_am_None);
1064 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1071 * Creates an ia32 Sub.
1073 * @param env The transformation environment
1074 * @return The created ia32 Sub node
1076 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) {
1077 ir_node *new_op = NULL;
1078 ir_graph *irg = env->irg;
1079 dbg_info *dbgi = get_irn_dbg_info(node);
1080 ir_mode *mode = get_irn_mode(node);
1081 ir_node *block = transform_node(env, get_nodes_block(node));
1082 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1083 ir_node *nomem = new_NoMem();
1084 ir_node *op1 = get_Sub_left(node);
1085 ir_node *op2 = get_Sub_right(node);
1086 ir_node *new_op1 = transform_node(env, op1);
1087 ir_node *new_op2 = transform_node(env, op2);
1088 ir_node *expr_op, *imm_op;
1090 /* Check if immediate optimization is on and */
1091 /* if it's an operation with immediate. */
1092 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1093 expr_op = get_expr_op(new_op1, new_op2);
1095 assert((expr_op || imm_op) && "invalid operands");
1097 if (mode_is_float(mode)) {
1099 if (USE_SSE2(env->cg))
1100 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xSub);
1102 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfsub);
1107 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1108 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1110 /* No expr_op means, that we have two const - one symconst and */
1111 /* one tarval or another symconst - because this case is not */
1112 /* covered by constant folding */
1113 /* We need to check for: */
1114 /* 1) symconst - const -> becomes a LEA */
1115 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1116 /* linker doesn't support two symconsts */
1117 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1118 /* this is the 2nd case */
1119 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1120 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1121 set_ia32_am_sc_sign(new_op);
1122 set_ia32_am_flavour(new_op, ia32_am_OB);
1124 DBG_OPT_LEA3(op1, op2, node, new_op);
1125 } else if (tp1 == ia32_ImmSymConst) {
1126 tarval *tv = get_ia32_Immop_tarval(new_op2);
1127 long offs = get_tarval_long(tv);
1129 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1130 DBG_OPT_LEA3(op1, op2, node, new_op);
1132 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1133 add_ia32_am_offs_int(new_op, -offs);
1134 set_ia32_am_flavour(new_op, ia32_am_O);
1135 set_ia32_am_support(new_op, ia32_am_Source);
1136 set_ia32_op_type(new_op, ia32_AddrModeS);
1137 } else if (tp2 == ia32_ImmSymConst) {
1138 tarval *tv = get_ia32_Immop_tarval(new_op1);
1139 long offs = get_tarval_long(tv);
1141 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1142 DBG_OPT_LEA3(op1, op2, node, new_op);
1144 add_ia32_am_offs_int(new_op, offs);
1145 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1146 set_ia32_am_sc_sign(new_op);
1147 set_ia32_am_flavour(new_op, ia32_am_O);
1148 set_ia32_am_support(new_op, ia32_am_Source);
1149 set_ia32_op_type(new_op, ia32_AddrModeS);
1151 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1152 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1153 tarval *restv = tarval_sub(tv1, tv2);
1155 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1157 new_op = new_rd_ia32_Const(dbgi, irg, block);
1158 set_ia32_Const_tarval(new_op, restv);
1159 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1162 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1164 } else if (imm_op) {
1165 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1166 tarval_classification_t class_tv, class_negtv;
1167 tarval *tv = get_ia32_Immop_tarval(imm_op);
1169 /* optimize tarvals */
1170 class_tv = classify_tarval(tv);
1171 class_negtv = classify_tarval(tarval_neg(tv));
1173 if (class_tv == TV_CLASSIFY_ONE) {
1174 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1175 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1176 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1178 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1179 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1180 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1181 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1187 /* This is a normal sub */
1188 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1190 /* set AM support */
1191 set_ia32_am_support(new_op, ia32_am_Full);
1193 fold_immediate(env, new_op, 2, 3);
1195 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1203 * Generates an ia32 DivMod with additional infrastructure for the
1204 * register allocator if needed.
1206 * @param env The transformation environment
1207 * @param dividend -no comment- :)
1208 * @param divisor -no comment- :)
1209 * @param dm_flav flavour_Div/Mod/DivMod
1210 * @return The created ia32 DivMod node
1212 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *node,
1213 ir_node *dividend, ir_node *divisor,
1214 ia32_op_flavour_t dm_flav) {
1215 ir_graph *irg = env->irg;
1216 dbg_info *dbgi = get_irn_dbg_info(node);
1217 ir_mode *mode = get_irn_mode(node);
1218 ir_node *block = transform_node(env, get_nodes_block(node));
1219 ir_node *res, *proj_div, *proj_mod;
1220 ir_node *edx_node, *cltd;
1221 ir_node *in_keep[1];
1222 ir_node *mem, *new_mem;
1223 ir_node *projs[pn_DivMod_max];
1224 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1225 ir_node *new_dividend = transform_node(env, dividend);
1226 ir_node *new_divisor = transform_node(env, divisor);
1228 ia32_collect_Projs(node, projs, pn_DivMod_max);
1232 mem = get_Div_mem(node);
1233 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Div_res));
1236 mem = get_Mod_mem(node);
1237 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Mod_res));
1239 case flavour_DivMod:
1240 mem = get_DivMod_mem(node);
1241 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1242 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1243 mode = proj_div ? get_irn_mode(proj_div) : get_irn_mode(proj_mod);
1246 panic("invalid divmod flavour!");
1248 new_mem = transform_node(env, mem);
1250 if (mode_is_signed(mode)) {
1251 /* in signed mode, we need to sign extend the dividend */
1252 cltd = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1253 new_dividend = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1254 edx_node = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1256 edx_node = new_rd_ia32_Const(dbgi, irg, block);
1257 add_irn_dep(edx_node, be_abi_get_start_barrier(env->cg->birg->abi));
1258 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1261 if(mode_is_signed(mode)) {
1262 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1264 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1267 /* Matze: code can't handle this at the moment... */
1269 /* set AM support */
1270 set_ia32_am_support(res, ia32_am_Source);
1273 set_ia32_n_res(res, 2);
1275 /* Only one proj is used -> We must add a second proj and */
1276 /* connect this one to a Keep node to eat up the second */
1277 /* destroyed register. */
1278 /* We also renumber the Firm projs into ia32 projs. */
1280 switch (get_irn_opcode(node)) {
1282 /* add Proj-Keep for mod res */
1283 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1284 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1287 /* add Proj-Keep for div res */
1288 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1289 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1292 /* check, which Proj-Keep, we need to add */
1293 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1294 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1296 if (proj_div && proj_mod) {
1297 /* nothing to be done */
1299 else if (! proj_div && ! proj_mod) {
1300 assert(0 && "Missing DivMod result proj");
1302 else if (! proj_div) {
1303 /* We have only mod result: add div res Proj-Keep */
1304 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1305 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1308 /* We have only div result: add mod res Proj-Keep */
1309 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1310 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1314 assert(0 && "Div, Mod, or DivMod expected.");
1318 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1325 * Wrapper for generate_DivMod. Sets flavour_Mod.
1327 * @param env The transformation environment
1329 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *node) {
1330 return generate_DivMod(env, node, get_Mod_left(node),
1331 get_Mod_right(node), flavour_Mod);
1335 * Wrapper for generate_DivMod. Sets flavour_Div.
1337 * @param env The transformation environment
1339 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *node) {
1340 return generate_DivMod(env, node, get_Div_left(node),
1341 get_Div_right(node), flavour_Div);
1345 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1347 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *node) {
1348 return generate_DivMod(env, node, get_DivMod_left(node),
1349 get_DivMod_right(node), flavour_DivMod);
1355 * Creates an ia32 floating Div.
1357 * @param env The transformation environment
1358 * @return The created ia32 xDiv node
1360 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *node) {
1361 ir_graph *irg = env->irg;
1362 dbg_info *dbgi = get_irn_dbg_info(node);
1363 ir_node *block = transform_node(env, get_nodes_block(node));
1364 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1366 ir_node *nomem = new_rd_NoMem(env->irg);
1367 ir_node *op1 = get_Quot_left(node);
1368 ir_node *op2 = get_Quot_right(node);
1369 ir_node *new_op1 = transform_node(env, op1);
1370 ir_node *new_op2 = transform_node(env, op2);
1373 if (USE_SSE2(env->cg)) {
1374 ir_mode *mode = get_irn_mode(op1);
1375 if (is_ia32_xConst(new_op2)) {
1376 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1377 set_ia32_am_support(new_op, ia32_am_None);
1378 copy_ia32_Immop_attr(new_op, new_op2);
1380 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1381 // Matze: disabled for now, spillslot coalescer fails
1382 //set_ia32_am_support(new_op, ia32_am_Source);
1384 set_ia32_ls_mode(new_op, mode);
1386 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1387 // Matze: disabled for now (spillslot coalescer fails)
1388 //set_ia32_am_support(new_op, ia32_am_Source);
1390 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1396 * Creates an ia32 Shl.
1398 * @param env The transformation environment
1399 * @return The created ia32 Shl node
1401 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *node) {
1402 return gen_shift_binop(env, node, get_Shl_left(node), get_Shl_right(node),
1409 * Creates an ia32 Shr.
1411 * @param env The transformation environment
1412 * @return The created ia32 Shr node
1414 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *node) {
1415 return gen_shift_binop(env, node, get_Shr_left(node),
1416 get_Shr_right(node), new_rd_ia32_Shr);
1422 * Creates an ia32 Sar.
1424 * @param env The transformation environment
1425 * @return The created ia32 Shrs node
1427 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) {
1428 return gen_shift_binop(env, node, get_Shrs_left(node),
1429 get_Shrs_right(node), new_rd_ia32_Sar);
1435 * Creates an ia32 RotL.
1437 * @param env The transformation environment
1438 * @param op1 The first operator
1439 * @param op2 The second operator
1440 * @return The created ia32 RotL node
1442 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node,
1443 ir_node *op1, ir_node *op2) {
1444 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Rol);
1450 * Creates an ia32 RotR.
1451 * NOTE: There is no RotR with immediate because this would always be a RotL
1452 * "imm-mode_size_bits" which can be pre-calculated.
1454 * @param env The transformation environment
1455 * @param op1 The first operator
1456 * @param op2 The second operator
1457 * @return The created ia32 RotR node
1459 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1,
1461 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Ror);
1467 * Creates an ia32 RotR or RotL (depending on the found pattern).
1469 * @param env The transformation environment
1470 * @return The created ia32 RotL or RotR node
1472 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) {
1473 ir_node *rotate = NULL;
1474 ir_node *op1 = get_Rot_left(node);
1475 ir_node *op2 = get_Rot_right(node);
1477 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1478 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1479 that means we can create a RotR instead of an Add and a RotL */
1481 if (get_irn_op(op2) == op_Add) {
1483 ir_node *left = get_Add_left(add);
1484 ir_node *right = get_Add_right(add);
1485 if (is_Const(right)) {
1486 tarval *tv = get_Const_tarval(right);
1487 ir_mode *mode = get_irn_mode(node);
1488 long bits = get_mode_size_bits(mode);
1490 if (get_irn_op(left) == op_Minus &&
1491 tarval_is_long(tv) &&
1492 get_tarval_long(tv) == bits)
1494 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1495 rotate = gen_RotR(env, node, op1, get_Minus_op(left));
1500 if (rotate == NULL) {
1501 rotate = gen_RotL(env, node, op1, op2);
1510 * Transforms a Minus node.
1512 * @param env The transformation environment
1513 * @param op The Minus operand
1514 * @return The created ia32 Minus node
1516 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *node, ir_node *op) {
1519 ir_graph *irg = env->irg;
1520 dbg_info *dbgi = get_irn_dbg_info(node);
1521 ir_node *block = transform_node(env, get_nodes_block(node));
1522 ir_mode *mode = get_irn_mode(node);
1525 if (mode_is_float(mode)) {
1526 ir_node *new_op = transform_node(env, op);
1528 if (USE_SSE2(env->cg)) {
1529 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1530 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1531 ir_node *nomem = new_rd_NoMem(irg);
1533 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1535 size = get_mode_size_bits(mode);
1536 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1538 set_ia32_am_sc(res, ent);
1539 set_ia32_op_type(res, ia32_AddrModeS);
1540 set_ia32_ls_mode(res, mode);
1542 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1545 res = gen_unop(env, node, op, new_rd_ia32_Neg);
1548 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1554 * Transforms a Minus node.
1556 * @param env The transformation environment
1557 * @return The created ia32 Minus node
1559 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *node) {
1560 return gen_Minus_ex(env, node, get_Minus_op(node));
1565 * Transforms a Not node.
1567 * @param env The transformation environment
1568 * @return The created ia32 Not node
1570 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *node) {
1571 ir_node *op = get_Not_op(node);
1573 assert (! mode_is_float(get_irn_mode(node)));
1574 return gen_unop(env, node, op, new_rd_ia32_Not);
1580 * Transforms an Abs node.
1582 * @param env The transformation environment
1583 * @return The created ia32 Abs node
1585 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *node) {
1586 ir_node *res, *p_eax, *p_edx;
1587 ir_graph *irg = env->irg;
1588 dbg_info *dbgi = get_irn_dbg_info(node);
1589 ir_node *block = transform_node(env, get_nodes_block(node));
1590 ir_mode *mode = get_irn_mode(node);
1591 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1592 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1593 ir_node *nomem = new_NoMem();
1594 ir_node *op = get_Abs_op(node);
1595 ir_node *new_op = transform_node(env, op);
1599 if (mode_is_float(mode)) {
1601 if (USE_SSE2(env->cg)) {
1602 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1604 size = get_mode_size_bits(mode);
1605 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1607 set_ia32_am_sc(res, ent);
1609 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1611 set_ia32_op_type(res, ia32_AddrModeS);
1612 set_ia32_ls_mode(res, mode);
1615 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1616 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1620 res = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1621 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1623 p_eax = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
1624 p_edx = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1626 res = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1627 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1629 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1630 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1639 * Transforms a Load.
1641 * @param env The transformation environment
1642 * @return the created ia32 Load node
1644 static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) {
1645 ir_graph *irg = env->irg;
1646 dbg_info *dbgi = get_irn_dbg_info(node);
1647 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1648 ir_mode *mode = get_Load_mode(node);
1649 ir_node *block = transform_node(env, get_nodes_block(node));
1650 ir_node *ptr = get_Load_ptr(node);
1651 ir_node *new_ptr = transform_node(env, ptr);
1652 ir_node *lptr = new_ptr;
1653 ir_node *mem = get_Load_mem(node);
1654 ir_node *new_mem = transform_node(env, mem);
1657 ia32_am_flavour_t am_flav = ia32_am_B;
1658 ir_node *projs[pn_Load_max];
1660 ia32_collect_Projs(node, projs, pn_Load_max);
1663 check for special case: the loaded value might not be used (optimized, volatile, ...)
1664 we add a Proj + Keep for volatile loads and ignore all other cases
1666 if (! be_get_Proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1667 /* add a result proj and a Keep to produce a pseudo use */
1668 ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res);
1669 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), irg, block, 1, &proj);
1672 /* address might be a constant (symconst or absolute address) */
1673 if (is_ia32_Const(new_ptr)) {
1678 if (mode_is_float(mode)) {
1680 if (USE_SSE2(env->cg)) {
1681 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1683 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem);
1686 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1689 /* base is a constant address */
1691 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1692 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1693 am_flav = ia32_am_N;
1695 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1696 long offs = get_tarval_long(tv);
1698 add_ia32_am_offs_int(new_op, offs);
1699 am_flav = ia32_am_O;
1703 set_ia32_am_support(new_op, ia32_am_Source);
1704 set_ia32_op_type(new_op, ia32_AddrModeS);
1705 set_ia32_am_flavour(new_op, am_flav);
1706 set_ia32_ls_mode(new_op, mode);
1708 /* make sure we are scheduled behind the intial IncSP/Barrier
1709 * to avoid spills being placed before it
1711 if(block == get_irg_start_block(irg)) {
1712 add_irn_dep(new_op, get_irg_frame(irg));
1715 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1723 * Transforms a Store.
1725 * @param env The transformation environment
1726 * @return the created ia32 Store node
1728 static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) {
1729 ir_graph *irg = env->irg;
1730 dbg_info *dbgi = get_irn_dbg_info(node);
1731 ir_node *block = transform_node(env, get_nodes_block(node));
1732 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1733 ir_node *ptr = get_Store_ptr(node);
1734 ir_node *new_ptr = transform_node(env, ptr);
1735 ir_node *sptr = new_ptr;
1736 ir_node *val = get_Store_value(node);
1737 ir_node *new_val = transform_node(env, val);
1738 ir_node *mem = get_Store_mem(node);
1739 ir_node *new_mem = transform_node(env, mem);
1740 ir_mode *mode = get_irn_mode(val);
1741 ir_node *sval = new_val;
1744 ia32_am_flavour_t am_flav = ia32_am_B;
1746 if (is_ia32_Const(new_val)) {
1747 assert(!mode_is_float(mode));
1751 /* address might be a constant (symconst or absolute address) */
1752 if (is_ia32_Const(new_ptr)) {
1757 if (mode_is_float(mode)) {
1759 if (USE_SSE2(env->cg)) {
1760 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, sval, new_mem);
1762 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, sval, new_mem);
1764 } else if (get_mode_size_bits(mode) == 8) {
1765 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg, sval, new_mem);
1767 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, sval, new_mem);
1770 /* stored const is an immediate value */
1771 if (is_ia32_Const(new_val)) {
1772 assert(!mode_is_float(mode));
1773 copy_ia32_Immop_attr(new_op, new_val);
1776 /* base is an constant address */
1778 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1779 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1780 am_flav = ia32_am_N;
1782 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1783 long offs = get_tarval_long(tv);
1785 add_ia32_am_offs_int(new_op, offs);
1786 am_flav = ia32_am_O;
1790 set_ia32_am_support(new_op, ia32_am_Dest);
1791 set_ia32_op_type(new_op, ia32_AddrModeD);
1792 set_ia32_am_flavour(new_op, am_flav);
1793 set_ia32_ls_mode(new_op, mode);
1795 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1803 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1805 * @param env The transformation environment
1806 * @return The transformed node.
1808 static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) {
1809 ir_graph *irg = env->irg;
1810 dbg_info *dbgi = get_irn_dbg_info(node);
1811 ir_node *block = transform_node(env, get_nodes_block(node));
1812 ir_node *sel = get_Cond_selector(node);
1813 ir_mode *sel_mode = get_irn_mode(sel);
1814 ir_node *res = NULL;
1815 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1816 ir_node *cnst, *expr;
1818 if (is_Proj(sel) && sel_mode == mode_b) {
1819 ir_node *nomem = new_NoMem();
1820 ir_node *pred = get_Proj_pred(sel);
1821 ir_node *cmp_a = get_Cmp_left(pred);
1822 ir_node *new_cmp_a = transform_node(env, cmp_a);
1823 ir_node *cmp_b = get_Cmp_right(pred);
1824 ir_node *new_cmp_b = transform_node(env, cmp_b);
1825 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1827 int pnc = get_Proj_proj(sel);
1828 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1829 pnc |= ia32_pn_Cmp_Unsigned;
1832 /* check if we can use a CondJmp with immediate */
1833 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1834 expr = get_expr_op(new_cmp_a, new_cmp_b);
1836 if (cnst != NULL && expr != NULL) {
1837 /* immop has to be the right operand, we might need to flip pnc */
1838 if(cnst != new_cmp_b) {
1839 pnc = get_inversed_pnc(pnc);
1842 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_needs_gp_reg(get_irn_mode(expr))) {
1843 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1844 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1846 /* a Cmp A =/!= 0 */
1847 ir_node *op1 = expr;
1848 ir_node *op2 = expr;
1851 /* check, if expr is an only once used And operation */
1852 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1853 op1 = get_irn_n(expr, 2);
1854 op2 = get_irn_n(expr, 3);
1856 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1858 res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2);
1859 set_ia32_pncode(res, pnc);
1862 copy_ia32_Immop_attr(res, expr);
1865 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1870 if (mode_is_float(cmp_mode)) {
1872 if (USE_SSE2(env->cg)) {
1873 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1874 set_ia32_ls_mode(res, cmp_mode);
1880 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1882 copy_ia32_Immop_attr(res, cnst);
1885 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1887 if (mode_is_float(cmp_mode)) {
1889 if (USE_SSE2(env->cg)) {
1890 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1891 set_ia32_ls_mode(res, cmp_mode);
1894 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1895 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1896 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1900 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1901 set_ia32_commutative(res);
1905 set_ia32_pncode(res, pnc);
1906 // Matze: disabled for now, because the default collect_spills_walker
1907 // is not able to detect the mode of the spilled value
1908 // moreover, the lea optimize phase freely exchanges left/right
1909 // without updating the pnc
1910 //set_ia32_am_support(res, ia32_am_Source);
1913 /* determine the smallest switch case value */
1914 int switch_min = INT_MAX;
1915 const ir_edge_t *edge;
1916 ir_node *new_sel = transform_node(env, sel);
1918 foreach_out_edge(node, edge) {
1919 int pn = get_Proj_proj(get_edge_src_irn(edge));
1920 switch_min = pn < switch_min ? pn : switch_min;
1924 /* if smallest switch case is not 0 we need an additional sub */
1925 res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1926 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1927 add_ia32_am_offs_int(res, -switch_min);
1928 set_ia32_am_flavour(res, ia32_am_OB);
1929 set_ia32_am_support(res, ia32_am_Source);
1930 set_ia32_op_type(res, ia32_AddrModeS);
1933 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T);
1934 set_ia32_pncode(res, get_Cond_defaultProj(node));
1937 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1944 * Transforms a CopyB node.
1946 * @param env The transformation environment
1947 * @return The transformed node.
1949 static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) {
1950 ir_node *res = NULL;
1951 ir_graph *irg = env->irg;
1952 dbg_info *dbgi = get_irn_dbg_info(node);
1953 ir_node *block = transform_node(env, get_nodes_block(node));
1954 ir_node *src = get_CopyB_src(node);
1955 ir_node *new_src = transform_node(env, src);
1956 ir_node *dst = get_CopyB_dst(node);
1957 ir_node *new_dst = transform_node(env, dst);
1958 ir_node *mem = get_CopyB_mem(node);
1959 ir_node *new_mem = transform_node(env, mem);
1960 int size = get_type_size_bytes(get_CopyB_type(node));
1961 ir_mode *dst_mode = get_irn_mode(dst);
1962 ir_mode *src_mode = get_irn_mode(src);
1966 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1967 /* then we need the size explicitly in ECX. */
1968 if (size >= 32 * 4) {
1969 rem = size & 0x3; /* size % 4 */
1972 res = new_rd_ia32_Const(dbgi, irg, block);
1973 add_irn_dep(res, be_abi_get_start_barrier(env->cg->birg->abi));
1974 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1976 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1977 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1979 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1980 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1981 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1982 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1983 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1986 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1987 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1989 /* ok: now attach Proj's because movsd will destroy esi and edi */
1990 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1991 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1992 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1995 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2003 * Transforms a Mux node into CMov.
2005 * @param env The transformation environment
2006 * @return The transformed node.
2008 static ir_node *gen_Mux(ia32_transform_env_t *env, ir_node *node) {
2009 ir_node *new_op = new_rd_ia32_CMov(env->dbgi, env->irg, env->block, \
2010 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
2012 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2018 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
2019 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
2020 ir_node *psi_default);
2023 * Transforms a Psi node into CMov.
2025 * @param env The transformation environment
2026 * @return The transformed node.
2028 static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) {
2029 ia32_code_gen_t *cg = env->cg;
2030 ir_graph *irg = env->irg;
2031 dbg_info *dbgi = get_irn_dbg_info(node);
2032 ir_mode *mode = get_irn_mode(node);
2033 ir_node *block = transform_node(env, get_nodes_block(node));
2034 ir_node *cmp_proj = get_Mux_sel(node);
2035 ir_node *psi_true = get_Psi_val(node, 0);
2036 ir_node *psi_default = get_Psi_default(node);
2037 ir_node *new_psi_true = transform_node(env, psi_true);
2038 ir_node *new_psi_default = transform_node(env, psi_default);
2039 ir_node *noreg = ia32_new_NoReg_gp(cg);
2040 ir_node *nomem = new_rd_NoMem(irg);
2041 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
2042 ir_node *new_cmp_a, *new_cmp_b;
2046 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
2048 cmp = get_Proj_pred(cmp_proj);
2049 cmp_a = get_Cmp_left(cmp);
2050 cmp_b = get_Cmp_right(cmp);
2051 cmp_mode = get_irn_mode(cmp_a);
2052 new_cmp_a = transform_node(env, cmp_a);
2053 new_cmp_b = transform_node(env, cmp_b);
2055 pnc = get_Proj_proj(cmp_proj);
2056 if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2057 pnc |= ia32_pn_Cmp_Unsigned;
2060 if (mode_is_float(mode)) {
2061 /* floating point psi */
2064 /* 1st case: compare operands are float too */
2066 /* psi(cmp(a, b), t, f) can be done as: */
2067 /* tmp = cmp a, b */
2068 /* tmp2 = t and tmp */
2069 /* tmp3 = f and not tmp */
2070 /* res = tmp2 or tmp3 */
2072 /* in case the compare operands are int, we move them into xmm register */
2073 if (! mode_is_float(get_irn_mode(cmp_a))) {
2074 new_cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_a, node, mode_xmm);
2075 new_cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_b, node, mode_xmm);
2077 pnc |= 8; /* transform integer compare to fp compare */
2080 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2081 set_ia32_pncode(new_op, pnc);
2082 set_ia32_am_support(new_op, ia32_am_Source);
2083 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2085 and1 = new_rd_ia32_xAnd(dbgi, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2086 set_ia32_am_support(and1, ia32_am_None);
2087 set_ia32_commutative(and1);
2088 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2090 and2 = new_rd_ia32_xAndNot(dbgi, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2091 set_ia32_am_support(and2, ia32_am_None);
2092 set_ia32_commutative(and2);
2093 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2095 new_op = new_rd_ia32_xOr(dbgi, irg, block, noreg, noreg, and1, and2, nomem);
2096 set_ia32_am_support(new_op, ia32_am_None);
2097 set_ia32_commutative(new_op);
2098 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2102 new_op = new_rd_ia32_vfCMov(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2103 set_ia32_pncode(new_op, pnc);
2104 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2109 construct_binop_func *set_func = NULL;
2110 cmov_func_t *cmov_func = NULL;
2112 if (mode_is_float(get_irn_mode(cmp_a))) {
2113 /* 1st case: compare operands are floats */
2118 set_func = new_rd_ia32_xCmpSet;
2119 cmov_func = new_rd_ia32_xCmpCMov;
2123 set_func = new_rd_ia32_vfCmpSet;
2124 cmov_func = new_rd_ia32_vfCmpCMov;
2127 pnc &= ~0x8; /* fp compare -> int compare */
2130 /* 2nd case: compare operand are integer too */
2131 set_func = new_rd_ia32_CmpSet;
2132 cmov_func = new_rd_ia32_CmpCMov;
2135 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2136 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2137 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2138 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2139 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2140 set_ia32_pncode(new_op, pnc);
2142 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2143 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2144 /* we invert condition and set default to 0 */
2145 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2146 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2149 /* otherwise: use CMOVcc */
2150 new_op = new_rd_ia32_PsiCondCMov(dbgi, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2151 set_ia32_pncode(new_op, pnc);
2154 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2157 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2158 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2159 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2160 set_ia32_pncode(new_op, pnc);
2161 set_ia32_am_support(new_op, ia32_am_Source);
2163 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2164 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2165 /* we invert condition and set default to 0 */
2166 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2167 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2168 set_ia32_am_support(new_op, ia32_am_Source);
2171 /* otherwise: use CMOVcc */
2172 new_op = cmov_func(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2173 set_ia32_pncode(new_op, pnc);
2174 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2184 * Following conversion rules apply:
2188 * 1) n bit -> m bit n > m (downscale)
2190 * 2) n bit -> m bit n == m (sign change)
2192 * 3) n bit -> m bit n < m (upscale)
2193 * a) source is signed: movsx
2194 * b) source is unsigned: and with lower bits sets
2198 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2202 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2206 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2207 * x87 is mode_E internally, conversions happen only at load and store
2208 * in non-strict semantic
2212 * Create a conversion from x87 state register to general purpose.
2214 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) {
2215 ia32_code_gen_t *cg = env->cg;
2216 ir_graph *irg = env->irg;
2217 dbg_info *dbgi = get_irn_dbg_info(node);
2218 ir_node *block = transform_node(env, get_nodes_block(node));
2219 ir_node *noreg = ia32_new_NoReg_gp(cg);
2220 ir_node *op = get_Conv_op(node);
2221 ir_node *new_op = transform_node(env, op);
2222 ir_node *fist, *load;
2223 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2226 fist = new_rd_ia32_vfist(dbgi, irg, block,
2227 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2229 set_ia32_use_frame(fist);
2230 set_ia32_am_support(fist, ia32_am_Dest);
2231 set_ia32_op_type(fist, ia32_AddrModeD);
2232 set_ia32_am_flavour(fist, ia32_am_B);
2233 set_ia32_ls_mode(fist, mode_Iu);
2234 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2237 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2239 set_ia32_use_frame(load);
2240 set_ia32_am_support(load, ia32_am_Source);
2241 set_ia32_op_type(load, ia32_AddrModeS);
2242 set_ia32_am_flavour(load, ia32_am_B);
2243 set_ia32_ls_mode(load, mode_Iu);
2244 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2246 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2250 * Create a conversion from general purpose to x87 register
2252 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mode *src_mode) {
2254 ia32_code_gen_t *cg = env->cg;
2256 ir_graph *irg = env->irg;
2257 dbg_info *dbgi = get_irn_dbg_info(node);
2258 ir_node *block = transform_node(env, get_nodes_block(node));
2259 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2260 ir_node *nomem = new_NoMem();
2261 ir_node *op = get_Conv_op(node);
2262 ir_node *new_op = transform_node(env, op);
2263 ir_node *fild, *store;
2266 /* first convert to 32 bit if necessary */
2267 src_bits = get_mode_size_bits(src_mode);
2268 if (src_bits == 8) {
2269 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2270 set_ia32_am_support(new_op, ia32_am_Source);
2271 set_ia32_ls_mode(new_op, src_mode);
2272 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2273 } else if (src_bits < 32) {
2274 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2275 set_ia32_am_support(new_op, ia32_am_Source);
2276 set_ia32_ls_mode(new_op, src_mode);
2277 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2281 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2283 set_ia32_use_frame(store);
2284 set_ia32_am_support(store, ia32_am_Dest);
2285 set_ia32_op_type(store, ia32_AddrModeD);
2286 set_ia32_am_flavour(store, ia32_am_OB);
2287 set_ia32_ls_mode(store, mode_Iu);
2290 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2292 set_ia32_use_frame(fild);
2293 set_ia32_am_support(fild, ia32_am_Source);
2294 set_ia32_op_type(fild, ia32_AddrModeS);
2295 set_ia32_am_flavour(fild, ia32_am_OB);
2296 set_ia32_ls_mode(fild, mode_Iu);
2298 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2302 * Transforms a Conv node.
2304 * @param env The transformation environment
2305 * @return The created ia32 Conv node
2307 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) {
2308 ir_graph *irg = env->irg;
2309 dbg_info *dbgi = get_irn_dbg_info(node);
2310 ir_node *op = get_Conv_op(node);
2311 ir_mode *src_mode = get_irn_mode(op);
2312 ir_mode *tgt_mode = get_irn_mode(node);
2313 int src_bits = get_mode_size_bits(src_mode);
2314 int tgt_bits = get_mode_size_bits(tgt_mode);
2315 ir_node *block = transform_node(env, get_nodes_block(node));
2317 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2318 ir_node *nomem = new_rd_NoMem(irg);
2319 ir_node *new_op = transform_node(env, op);
2321 if (src_mode == tgt_mode) {
2322 if (get_Conv_strict(node)) {
2323 if (USE_SSE2(env->cg)) {
2324 /* when we are in SSE mode, we can kill all strict no-op conversion */
2328 /* this should be optimized already, but who knows... */
2329 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2330 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2335 if (mode_is_float(src_mode)) {
2336 /* we convert from float ... */
2337 if (mode_is_float(tgt_mode)) {
2339 if (USE_SSE2(env->cg)) {
2340 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2341 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2342 set_ia32_ls_mode(res, tgt_mode);
2344 // Matze: TODO what about strict convs?
2345 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: strict conv %+F ignored yet\n", node));
2346 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2351 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2352 if (USE_SSE2(env->cg)) {
2353 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2354 set_ia32_ls_mode(res, src_mode);
2356 return gen_x87_fp_to_gp(env, node);
2360 /* we convert from int ... */
2361 if (mode_is_float(tgt_mode)) {
2364 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2365 if (USE_SSE2(env->cg)) {
2366 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2367 set_ia32_ls_mode(res, tgt_mode);
2368 if(src_bits == 32) {
2369 set_ia32_am_support(res, ia32_am_Source);
2372 return gen_x87_gp_to_fp(env, node, src_mode);
2376 ir_mode *smaller_mode;
2379 if (src_bits == tgt_bits) {
2380 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2384 if(src_bits < tgt_bits) {
2385 smaller_mode = src_mode;
2386 smaller_bits = src_bits;
2388 smaller_mode = tgt_mode;
2389 smaller_bits = tgt_bits;
2392 // The following is not correct, we can't change the mode,
2393 // maybe others are using the load too
2394 // better move this to a separate phase!
2397 if(is_Proj(new_op)) {
2398 /* load operations do already sign/zero extend, so we have
2399 * nothing left to do */
2400 ir_node *pred = get_Proj_pred(new_op);
2401 if(is_ia32_Load(pred)) {
2402 set_ia32_ls_mode(pred, smaller_mode);
2408 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2409 if (smaller_bits == 8) {
2410 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2411 set_ia32_ls_mode(res, smaller_mode);
2413 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2414 set_ia32_ls_mode(res, smaller_mode);
2416 set_ia32_am_support(res, ia32_am_Source);
2420 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2427 /********************************************
2430 * | |__ ___ _ __ ___ __| | ___ ___
2431 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2432 * | |_) | __/ | | | (_) | (_| | __/\__ \
2433 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2435 ********************************************/
2437 static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) {
2438 ir_node *new_op = NULL;
2439 ir_graph *irg = env->irg;
2440 dbg_info *dbgi = get_irn_dbg_info(node);
2441 ir_node *block = transform_node(env, get_nodes_block(node));
2442 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2443 ir_node *nomem = new_rd_NoMem(env->irg);
2444 ir_node *ptr = get_irn_n(node, 0);
2445 ir_node *new_ptr = transform_node(env, ptr);
2446 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2447 ir_mode *load_mode = get_irn_mode(node);
2451 if (mode_is_float(load_mode)) {
2453 if (USE_SSE2(env->cg)) {
2454 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2455 pn_res = pn_ia32_xLoad_res;
2456 proj_mode = mode_xmm;
2458 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem);
2459 pn_res = pn_ia32_vfld_res;
2460 proj_mode = mode_vfp;
2463 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2464 proj_mode = mode_Iu;
2465 pn_res = pn_ia32_Load_res;
2468 set_ia32_frame_ent(new_op, ent);
2469 set_ia32_use_frame(new_op);
2471 set_ia32_am_support(new_op, ia32_am_Source);
2472 set_ia32_op_type(new_op, ia32_AddrModeS);
2473 set_ia32_am_flavour(new_op, ia32_am_B);
2474 set_ia32_ls_mode(new_op, load_mode);
2475 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2477 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2479 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2483 * Transforms a FrameAddr into an ia32 Add.
2485 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) {
2486 ir_graph *irg = env->irg;
2487 dbg_info *dbgi = get_irn_dbg_info(node);
2488 ir_node *block = transform_node(env, get_nodes_block(node));
2489 ir_node *op = get_irn_n(node, 0);
2490 ir_node *new_op = transform_node(env, op);
2492 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2494 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2495 set_ia32_frame_ent(res, arch_get_frame_entity(env->cg->arch_env, node));
2496 set_ia32_am_support(res, ia32_am_Full);
2497 set_ia32_use_frame(res);
2498 set_ia32_am_flavour(res, ia32_am_OB);
2500 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2506 * Transforms a FrameLoad into an ia32 Load.
2508 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) {
2509 ir_node *new_op = NULL;
2510 ir_graph *irg = env->irg;
2511 dbg_info *dbgi = get_irn_dbg_info(node);
2512 ir_node *block = transform_node(env, get_nodes_block(node));
2513 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2514 ir_node *mem = get_irn_n(node, 0);
2515 ir_node *ptr = get_irn_n(node, 1);
2516 ir_node *new_mem = transform_node(env, mem);
2517 ir_node *new_ptr = transform_node(env, ptr);
2518 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2519 ir_mode *mode = get_type_mode(get_entity_type(ent));
2520 ir_node *projs[pn_Load_max];
2522 ia32_collect_Projs(node, projs, pn_Load_max);
2524 if (mode_is_float(mode)) {
2526 if (USE_SSE2(env->cg)) {
2527 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2530 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
2534 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2537 set_ia32_frame_ent(new_op, ent);
2538 set_ia32_use_frame(new_op);
2540 set_ia32_am_support(new_op, ia32_am_Source);
2541 set_ia32_op_type(new_op, ia32_AddrModeS);
2542 set_ia32_am_flavour(new_op, ia32_am_B);
2543 set_ia32_ls_mode(new_op, mode);
2545 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2552 * Transforms a FrameStore into an ia32 Store.
2554 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) {
2555 ir_node *new_op = NULL;
2556 ir_graph *irg = env->irg;
2557 dbg_info *dbgi = get_irn_dbg_info(node);
2558 ir_node *block = transform_node(env, get_nodes_block(node));
2559 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2560 ir_node *mem = get_irn_n(node, 0);
2561 ir_node *ptr = get_irn_n(node, 1);
2562 ir_node *val = get_irn_n(node, 2);
2563 ir_node *new_mem = transform_node(env, mem);
2564 ir_node *new_ptr = transform_node(env, ptr);
2565 ir_node *new_val = transform_node(env, val);
2566 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2567 ir_mode *mode = get_irn_mode(val);
2569 if (mode_is_float(mode)) {
2571 if (USE_SSE2(env->cg)) {
2572 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2574 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2576 } else if (get_mode_size_bits(mode) == 8) {
2577 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2579 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2582 set_ia32_frame_ent(new_op, ent);
2583 set_ia32_use_frame(new_op);
2585 set_ia32_am_support(new_op, ia32_am_Dest);
2586 set_ia32_op_type(new_op, ia32_AddrModeD);
2587 set_ia32_am_flavour(new_op, ia32_am_B);
2588 set_ia32_ls_mode(new_op, mode);
2590 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2596 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2598 static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
2599 ir_graph *irg = env->irg;
2602 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2603 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2604 ir_entity *ent = get_irg_entity(irg);
2605 ir_type *tp = get_entity_type(ent);
2608 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2609 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2611 int pn_ret_val, pn_ret_mem, arity, i;
2613 assert(ret_val != NULL);
2614 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env->cg)) {
2615 return duplicate_node(env, node);
2618 res_type = get_method_res_type(tp, 0);
2620 if (!is_Primitive_type(res_type)) {
2621 return duplicate_node(env, node);
2624 mode = get_type_mode(res_type);
2625 if (!mode_is_float(mode)) {
2626 return duplicate_node(env, node);
2629 assert(get_method_n_ress(tp) == 1);
2631 pn_ret_val = get_Proj_proj(ret_val);
2632 pn_ret_mem = get_Proj_proj(ret_mem);
2634 /* get the Barrier */
2635 barrier = get_Proj_pred(ret_val);
2637 /* get result input of the Barrier */
2638 ret_val = get_irn_n(barrier, pn_ret_val);
2639 new_ret_val = transform_node(env, ret_val);
2641 /* get memory input of the Barrier */
2642 ret_mem = get_irn_n(barrier, pn_ret_mem);
2643 new_ret_mem = transform_node(env, ret_mem);
2645 frame = get_irg_frame(irg);
2647 dbgi = get_irn_dbg_info(barrier);
2648 block = transform_node(env, get_nodes_block(barrier));
2650 /* store xmm0 onto stack */
2651 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, new_ret_val, new_ret_mem);
2652 set_ia32_ls_mode(sse_store, mode);
2653 set_ia32_op_type(sse_store, ia32_AddrModeD);
2654 set_ia32_use_frame(sse_store);
2655 set_ia32_am_flavour(sse_store, ia32_am_B);
2656 set_ia32_am_support(sse_store, ia32_am_Dest);
2659 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, sse_store);
2660 set_ia32_ls_mode(fld, mode);
2661 set_ia32_op_type(fld, ia32_AddrModeS);
2662 set_ia32_use_frame(fld);
2663 set_ia32_am_flavour(fld, ia32_am_B);
2664 set_ia32_am_support(fld, ia32_am_Source);
2666 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
2667 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
2668 arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2670 /* create a new barrier */
2671 arity = get_irn_arity(barrier);
2672 in = alloca(arity * sizeof(in[0]));
2673 for(i = 0; i < arity; ++i) {
2675 if(i == pn_ret_val) {
2677 } else if(i == pn_ret_mem) {
2680 ir_node *in = get_irn_n(barrier, i);
2681 new_in = transform_node(env, in);
2686 new_barrier = new_ir_node(dbgi, irg, block,
2687 get_irn_op(barrier), get_irn_mode(barrier),
2689 copy_node_attr(barrier, new_barrier);
2690 duplicate_deps(env, barrier, new_barrier);
2691 set_new_node(barrier, new_barrier);
2692 mark_irn_visited(barrier);
2694 /* transform normally */
2695 return duplicate_node(env, node);
2699 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2701 static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
2703 ir_graph *irg = env->irg;
2704 dbg_info *dbgi = get_irn_dbg_info(node);
2705 ir_node *block = transform_node(env, get_nodes_block(node));
2706 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
2707 ir_node *new_sz = transform_node(env, sz);
2708 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
2709 ir_node *new_sp = transform_node(env, sp);
2710 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2711 ir_node *nomem = new_NoMem();
2713 /* ia32 stack grows in reverse direction, make a SubSP */
2714 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2715 set_ia32_am_support(new_op, ia32_am_Source);
2716 fold_immediate(env, new_op, 2, 3);
2718 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2724 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
2726 static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
2728 ir_graph *irg = env->irg;
2729 dbg_info *dbgi = get_irn_dbg_info(node);
2730 ir_node *block = transform_node(env, get_nodes_block(node));
2731 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
2732 ir_node *new_sz = transform_node(env, sz);
2733 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
2734 ir_node *new_sp = transform_node(env, sp);
2735 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2736 ir_node *nomem = new_NoMem();
2738 /* ia32 stack grows in reverse direction, make an AddSP */
2739 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2740 set_ia32_am_support(new_op, ia32_am_Source);
2741 fold_immediate(env, new_op, 2, 3);
2743 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2749 * This function just sets the register for the Unknown node
2750 * as this is not done during register allocation because Unknown
2751 * is an "ignore" node.
2753 static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) {
2754 ir_mode *mode = get_irn_mode(node);
2756 if (mode_is_float(mode)) {
2757 if (USE_SSE2(env->cg))
2758 return ia32_new_Unknown_xmm(env->cg);
2760 return ia32_new_Unknown_vfp(env->cg);
2761 } else if (mode_needs_gp_reg(mode)) {
2762 return ia32_new_Unknown_gp(env->cg);
2764 assert(0 && "unsupported Unknown-Mode");
2771 * Change some phi modes
2773 static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
2774 ir_graph *irg = env->irg;
2775 dbg_info *dbgi = get_irn_dbg_info(node);
2776 ir_mode *mode = get_irn_mode(node);
2777 ir_node *block = transform_node(env, get_nodes_block(node));
2781 if(mode_needs_gp_reg(mode)) {
2782 // we shouldn't have any 64bit stuff around anymore
2783 assert(get_mode_size_bits(mode) <= 32);
2784 // all integer operations are on 32bit registers now
2786 } else if(mode_is_float(mode)) {
2787 assert(mode == mode_D || mode == mode_F);
2788 if (USE_SSE2(env->cg)) {
2795 /* phi nodes allow loops, so we use the old arguments for now
2796 * and fix this later */
2797 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
2798 get_irn_in(node) + 1);
2799 copy_node_attr(node, phi);
2800 duplicate_deps(env, node, phi);
2802 set_new_node(node, phi);
2804 /* put the preds in the worklist */
2805 arity = get_irn_arity(node);
2806 for(i = 0; i < arity; ++i) {
2807 ir_node *pred = get_irn_n(node, i);
2808 pdeq_putr(env->worklist, pred);
2814 /**********************************************************************
2817 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2818 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2819 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2820 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2822 **********************************************************************/
2824 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2826 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2829 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2830 ir_node *val, ir_node *mem);
2833 * Transforms a lowered Load into a "real" one.
2835 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) {
2836 ir_graph *irg = env->irg;
2837 dbg_info *dbgi = get_irn_dbg_info(node);
2838 ir_node *block = transform_node(env, get_nodes_block(node));
2839 ir_mode *mode = get_ia32_ls_mode(node);
2841 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2842 ir_node *ptr = get_irn_n(node, 0);
2843 ir_node *mem = get_irn_n(node, 1);
2844 ir_node *new_ptr = transform_node(env, ptr);
2845 ir_node *new_mem = transform_node(env, mem);
2848 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2849 lowering we have x87 nodes, so we need to enforce simulation.
2851 if (mode_is_float(mode)) {
2853 if (fp_unit == fp_x87)
2857 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
2859 set_ia32_am_support(new_op, ia32_am_Source);
2860 set_ia32_op_type(new_op, ia32_AddrModeS);
2861 set_ia32_am_flavour(new_op, ia32_am_OB);
2862 set_ia32_am_offs_int(new_op, 0);
2863 set_ia32_am_scale(new_op, 1);
2864 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
2865 if(is_ia32_am_sc_sign(node))
2866 set_ia32_am_sc_sign(new_op);
2867 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
2868 if(is_ia32_use_frame(node)) {
2869 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2870 set_ia32_use_frame(new_op);
2873 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2879 * Transforms a lowered Store into a "real" one.
2881 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) {
2882 ir_graph *irg = env->irg;
2883 dbg_info *dbgi = get_irn_dbg_info(node);
2884 ir_node *block = transform_node(env, get_nodes_block(node));
2885 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2886 ir_mode *mode = get_ia32_ls_mode(node);
2889 ia32_am_flavour_t am_flav = ia32_B;
2890 ir_node *ptr = get_irn_n(node, 0);
2891 ir_node *val = get_irn_n(node, 1);
2892 ir_node *mem = get_irn_n(node, 2);
2893 ir_node *new_ptr = transform_node(env, ptr);
2894 ir_node *new_val = transform_node(env, val);
2895 ir_node *new_mem = transform_node(env, mem);
2898 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2899 lowering we have x87 nodes, so we need to enforce simulation.
2901 if (mode_is_float(mode)) {
2903 if (fp_unit == fp_x87)
2907 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2909 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
2911 add_ia32_am_offs_int(new_op, am_offs);
2914 set_ia32_am_support(new_op, ia32_am_Dest);
2915 set_ia32_op_type(new_op, ia32_AddrModeD);
2916 set_ia32_am_flavour(new_op, am_flav);
2917 set_ia32_ls_mode(new_op, mode);
2918 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2919 set_ia32_use_frame(new_op);
2921 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2928 * Transforms an ia32_l_XXX into a "real" XXX node
2930 * @param env The transformation environment
2931 * @return the created ia32 XXX node
2933 #define GEN_LOWERED_OP(op) \
2934 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2935 ir_mode *mode = get_irn_mode(node); \
2936 if (mode_is_float(mode)) \
2938 return gen_binop(env, node, get_binop_left(node), \
2939 get_binop_right(node), new_rd_ia32_##op); \
2942 #define GEN_LOWERED_x87_OP(op) \
2943 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2945 FORCE_x87(env->cg); \
2946 new_op = gen_binop_float(env, node, get_binop_left(node), \
2947 get_binop_right(node), new_rd_ia32_##op); \
2951 #define GEN_LOWERED_UNOP(op) \
2952 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2953 return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \
2956 #define GEN_LOWERED_SHIFT_OP(op) \
2957 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2958 return gen_shift_binop(env, node, get_binop_left(node), \
2959 get_binop_right(node), new_rd_ia32_##op); \
2962 #define GEN_LOWERED_LOAD(op, fp_unit) \
2963 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2964 return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \
2967 #define GEN_LOWERED_STORE(op, fp_unit) \
2968 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2969 return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \
2976 GEN_LOWERED_OP(IMul)
2978 GEN_LOWERED_x87_OP(vfprem)
2979 GEN_LOWERED_x87_OP(vfmul)
2980 GEN_LOWERED_x87_OP(vfsub)
2982 GEN_LOWERED_UNOP(Neg)
2984 GEN_LOWERED_LOAD(vfild, fp_x87)
2985 GEN_LOWERED_LOAD(Load, fp_none)
2986 /*GEN_LOWERED_STORE(vfist, fp_x87)
2989 GEN_LOWERED_STORE(Store, fp_none)
2991 static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
2992 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2993 ir_graph *irg = env->irg;
2994 dbg_info *dbgi = get_irn_dbg_info(node);
2995 ir_node *block = transform_node(env, get_nodes_block(node));
2996 ir_node *left = get_binop_left(node);
2997 ir_node *right = get_binop_right(node);
2998 ir_node *new_left = transform_node(env, left);
2999 ir_node *new_right = transform_node(env, right);
3002 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3003 clear_ia32_commutative(vfdiv);
3004 set_ia32_am_support(vfdiv, ia32_am_Source);
3005 fold_immediate(env, vfdiv, 2, 3);
3007 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env->cg, node));
3015 * Transforms a l_MulS into a "real" MulS node.
3017 * @param env The transformation environment
3018 * @return the created ia32 Mul node
3020 static ir_node *gen_ia32_l_Mul(ia32_transform_env_t *env, ir_node *node) {
3021 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3022 ir_graph *irg = env->irg;
3023 dbg_info *dbgi = get_irn_dbg_info(node);
3024 ir_node *block = transform_node(env, get_nodes_block(node));
3025 ir_node *left = get_binop_left(node);
3026 ir_node *right = get_binop_right(node);
3027 ir_node *new_left = transform_node(env, left);
3028 ir_node *new_right = transform_node(env, right);
3031 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3032 /* and then skip the result Proj, because all needed Projs are already there. */
3033 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3034 clear_ia32_commutative(muls);
3035 set_ia32_am_support(muls, ia32_am_Source);
3036 fold_immediate(env, muls, 2, 3);
3038 /* check if EAX and EDX proj exist, add missing one */
3039 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3040 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3041 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3043 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env->cg, node));
3048 GEN_LOWERED_SHIFT_OP(Shl)
3049 GEN_LOWERED_SHIFT_OP(Shr)
3050 GEN_LOWERED_SHIFT_OP(Sar)
3053 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3054 * op1 - target to be shifted
3055 * op2 - contains bits to be shifted into target
3057 * Only op3 can be an immediate.
3059 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *node,
3060 ir_node *op1, ir_node *op2,
3062 ir_node *new_op = NULL;
3063 ir_graph *irg = env->irg;
3064 dbg_info *dbgi = get_irn_dbg_info(node);
3065 ir_node *block = transform_node(env, get_nodes_block(node));
3066 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3067 ir_node *nomem = new_NoMem();
3069 ir_node *new_op1 = transform_node(env, op1);
3070 ir_node *new_op2 = transform_node(env, op2);
3071 ir_node *new_count = transform_node(env, count);
3074 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3076 /* Check if immediate optimization is on and */
3077 /* if it's an operation with immediate. */
3078 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3080 /* Limit imm_op within range imm8 */
3082 tv = get_ia32_Immop_tarval(imm_op);
3085 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3086 set_ia32_Immop_tarval(imm_op, tv);
3093 /* integer operations */
3095 /* This is ShiftD with const */
3096 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3098 if (is_ia32_l_ShlD(node))
3099 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3100 new_op1, new_op2, noreg, nomem);
3102 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3103 new_op1, new_op2, noreg, nomem);
3104 copy_ia32_Immop_attr(new_op, imm_op);
3107 /* This is a normal ShiftD */
3108 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3109 if (is_ia32_l_ShlD(node))
3110 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3111 new_op1, new_op2, new_count, nomem);
3113 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3114 new_op1, new_op2, new_count, nomem);
3117 /* set AM support */
3118 // Matze: node has unsupported format (6inputs)
3119 //set_ia32_am_support(new_op, ia32_am_Dest);
3121 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3123 set_ia32_emit_cl(new_op);
3128 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env, ir_node *node) {
3129 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3130 get_irn_n(node, 1), get_irn_n(node, 2));
3133 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env, ir_node *node) {
3134 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3135 get_irn_n(node, 1), get_irn_n(node, 2));
3139 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3141 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) {
3142 ia32_code_gen_t *cg = env->cg;
3143 ir_node *res = NULL;
3144 ir_graph *irg = env->irg;
3145 dbg_info *dbgi = get_irn_dbg_info(node);
3146 ir_node *block = transform_node(env, get_nodes_block(node));
3147 ir_node *ptr = get_irn_n(node, 0);
3148 ir_node *val = get_irn_n(node, 1);
3149 ir_node *new_val = transform_node(env, val);
3150 ir_node *mem = get_irn_n(node, 2);
3151 ir_node *noreg, *new_ptr, *new_mem;
3157 noreg = ia32_new_NoReg_gp(cg);
3158 new_mem = transform_node(env, mem);
3159 new_ptr = transform_node(env, ptr);
3161 /* Store x87 -> MEM */
3162 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3163 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3164 set_ia32_use_frame(res);
3165 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3166 set_ia32_am_support(res, ia32_am_Dest);
3167 set_ia32_am_flavour(res, ia32_B);
3168 set_ia32_op_type(res, ia32_AddrModeD);
3170 /* Load MEM -> SSE */
3171 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3172 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3173 set_ia32_use_frame(res);
3174 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3175 set_ia32_am_support(res, ia32_am_Source);
3176 set_ia32_am_flavour(res, ia32_B);
3177 set_ia32_op_type(res, ia32_AddrModeS);
3178 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3184 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3186 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) {
3187 ia32_code_gen_t *cg = env->cg;
3188 ir_graph *irg = env->irg;
3189 dbg_info *dbgi = get_irn_dbg_info(node);
3190 ir_node *block = transform_node(env, get_nodes_block(node));
3191 ir_node *res = NULL;
3192 ir_node *ptr = get_irn_n(node, 0);
3193 ir_node *val = get_irn_n(node, 1);
3194 ir_node *mem = get_irn_n(node, 2);
3195 ir_entity *fent = get_ia32_frame_ent(node);
3196 ir_mode *lsmode = get_ia32_ls_mode(node);
3197 ir_node *new_val = transform_node(env, val);
3198 ir_node *noreg, *new_ptr, *new_mem;
3201 if (!USE_SSE2(cg)) {
3202 /* SSE unit is not used -> skip this node. */
3206 noreg = ia32_new_NoReg_gp(cg);
3207 new_val = transform_node(env, val);
3208 new_ptr = transform_node(env, ptr);
3209 new_mem = transform_node(env, mem);
3211 /* Store SSE -> MEM */
3212 if (is_ia32_xLoad(skip_Proj(new_val))) {
3213 ir_node *ld = skip_Proj(new_val);
3215 /* we can vfld the value directly into the fpu */
3216 fent = get_ia32_frame_ent(ld);
3217 ptr = get_irn_n(ld, 0);
3218 offs = get_ia32_am_offs_int(ld);
3220 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3221 set_ia32_frame_ent(res, fent);
3222 set_ia32_use_frame(res);
3223 set_ia32_ls_mode(res, lsmode);
3224 set_ia32_am_support(res, ia32_am_Dest);
3225 set_ia32_am_flavour(res, ia32_B);
3226 set_ia32_op_type(res, ia32_AddrModeD);
3230 /* Load MEM -> x87 */
3231 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
3232 set_ia32_frame_ent(res, fent);
3233 set_ia32_use_frame(res);
3234 set_ia32_ls_mode(res, lsmode);
3235 add_ia32_am_offs_int(res, offs);
3236 set_ia32_am_support(res, ia32_am_Source);
3237 set_ia32_am_flavour(res, ia32_B);
3238 set_ia32_op_type(res, ia32_AddrModeS);
3239 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3244 /*********************************************************
3247 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3248 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3249 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3250 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3252 *********************************************************/
3255 * the BAD transformer.
3257 static ir_node *bad_transform(ia32_transform_env_t *env, ir_node *node) {
3258 panic("No transform function for %+F available.\n", node);
3262 static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) {
3263 /* end has to be duplicated manually because we need a dynamic in array */
3264 ir_graph *irg = env->irg;
3265 dbg_info *dbgi = get_irn_dbg_info(node);
3266 ir_node *block = transform_node(env, get_nodes_block(node));
3270 new_end = new_ir_node(dbgi, irg, block, op_End, mode_X, -1, NULL);
3271 copy_node_attr(node, new_end);
3272 duplicate_deps(env, node, new_end);
3274 set_irg_end(irg, new_end);
3275 set_new_node(new_end, new_end);
3277 /* transform preds */
3278 arity = get_irn_arity(node);
3279 for(i = 0; i < arity; ++i) {
3280 ir_node *in = get_irn_n(node, i);
3281 ir_node *new_in = transform_node(env, in);
3283 add_End_keepalive(new_end, new_in);
3289 static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) {
3290 ir_graph *irg = env->irg;
3291 dbg_info *dbgi = get_irn_dbg_info(node);
3292 ir_node *start_block = env->old_anchors[anchor_start_block];
3297 * We replace the ProjX from the start node with a jump,
3298 * so the startblock has no preds anymore now
3300 if(node == start_block) {
3301 return new_rd_Block(dbgi, irg, 0, NULL);
3304 /* we use the old blocks for now, because jumps allow cycles in the graph
3305 * we have to fix this later */
3306 block = new_ir_node(dbgi, irg, NULL, get_irn_op(node), get_irn_mode(node),
3307 get_irn_arity(node), get_irn_in(node) + 1);
3308 copy_node_attr(node, block);
3310 #ifdef DEBUG_libfirm
3311 block->node_nr = node->node_nr;
3313 set_new_node(node, block);
3315 /* put the preds in the worklist */
3316 arity = get_irn_arity(node);
3317 for(i = 0; i < arity; ++i) {
3318 ir_node *in = get_irn_n(node, i);
3319 pdeq_putr(env->worklist, in);
3325 static ir_node *gen_Proj_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
3326 ir_graph *irg = env->irg;
3327 ir_node *block = transform_node(env, get_nodes_block(node));
3328 dbg_info *dbgi = get_irn_dbg_info(node);
3329 ir_node *pred = get_Proj_pred(node);
3330 ir_node *new_pred = transform_node(env, pred);
3331 long proj = get_Proj_proj(node);
3333 if(proj == pn_be_AddSP_res) {
3334 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3335 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3337 } else if(proj == pn_be_AddSP_M) {
3338 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3342 return new_rd_Unknown(irg, get_irn_mode(node));
3345 static ir_node *gen_Proj_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
3346 ir_graph *irg = env->irg;
3347 ir_node *block = transform_node(env, get_nodes_block(node));
3348 dbg_info *dbgi = get_irn_dbg_info(node);
3349 ir_node *pred = get_Proj_pred(node);
3350 ir_node *new_pred = transform_node(env, pred);
3351 long proj = get_Proj_proj(node);
3353 if(proj == pn_be_SubSP_res) {
3354 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3355 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3357 } else if(proj == pn_be_SubSP_M) {
3358 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3362 return new_rd_Unknown(irg, get_irn_mode(node));
3365 static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) {
3366 ir_graph *irg = env->irg;
3367 ir_node *block = transform_node(env, get_nodes_block(node));
3368 dbg_info *dbgi = get_irn_dbg_info(node);
3369 ir_node *pred = get_Proj_pred(node);
3370 ir_node *new_pred = transform_node(env, pred);
3371 long proj = get_Proj_proj(node);
3373 /* renumber the proj */
3374 if(is_ia32_Load(new_pred)) {
3375 if(proj == pn_Load_res) {
3376 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3377 } else if(proj == pn_Load_M) {
3378 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3380 } else if(is_ia32_xLoad(new_pred)) {
3381 if(proj == pn_Load_res) {
3382 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3383 } else if(proj == pn_Load_M) {
3384 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3386 } else if(is_ia32_vfld(new_pred)) {
3387 if(proj == pn_Load_res) {
3388 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3389 } else if(proj == pn_Load_M) {
3390 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3395 return new_rd_Unknown(irg, get_irn_mode(node));
3398 static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) {
3399 ir_graph *irg = env->irg;
3400 dbg_info *dbgi = get_irn_dbg_info(node);
3401 ir_node *block = transform_node(env, get_nodes_block(node));
3402 ir_mode *mode = get_irn_mode(node);
3404 ir_node *pred = get_Proj_pred(node);
3405 ir_node *new_pred = transform_node(env, pred);
3406 long proj = get_Proj_proj(node);
3408 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3410 switch(get_irn_opcode(pred)) {
3414 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3416 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3424 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3426 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3434 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3435 case pn_DivMod_res_div:
3436 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3437 case pn_DivMod_res_mod:
3438 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3448 return new_rd_Unknown(irg, mode);
3451 static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node)
3453 ir_graph *irg = env->irg;
3454 dbg_info *dbgi = get_irn_dbg_info(node);
3455 ir_node *block = transform_node(env, get_nodes_block(node));
3456 ir_mode *mode = get_irn_mode(node);
3458 ir_node *pred = get_Proj_pred(node);
3459 ir_node *new_pred = transform_node(env, pred);
3460 long proj = get_Proj_proj(node);
3463 case pn_CopyB_M_regular:
3464 if(is_ia32_CopyB_i(new_pred)) {
3465 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3467 } else if(is_ia32_CopyB(new_pred)) {
3468 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3477 return new_rd_Unknown(irg, mode);
3480 static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node)
3482 ir_graph *irg = env->irg;
3483 dbg_info *dbgi = get_irn_dbg_info(node);
3484 ir_node *block = transform_node(env, get_nodes_block(node));
3485 ir_mode *mode = get_irn_mode(node);
3487 ir_node *pred = get_Proj_pred(node);
3488 ir_node *new_pred = transform_node(env, pred);
3489 long proj = get_Proj_proj(node);
3492 case pn_ia32_l_vfdiv_M:
3493 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3494 case pn_ia32_l_vfdiv_res:
3495 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3500 return new_rd_Unknown(irg, mode);
3503 static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node)
3505 ir_graph *irg = env->irg;
3506 dbg_info *dbgi = get_irn_dbg_info(node);
3507 ir_node *block = transform_node(env, get_nodes_block(node));
3508 ir_mode *mode = get_irn_mode(node);
3510 ir_node *pred = get_Proj_pred(node);
3511 ir_node *new_pred = transform_node(env, pred);
3512 long proj = get_Proj_proj(node);
3516 if(is_ia32_xDiv(new_pred)) {
3517 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3519 } else if(is_ia32_vfdiv(new_pred)) {
3520 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3525 if(is_ia32_xDiv(new_pred)) {
3526 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
3528 } else if(is_ia32_vfdiv(new_pred)) {
3529 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
3538 return new_rd_Unknown(irg, mode);
3541 static ir_node *gen_Proj_tls(ia32_transform_env_t *env, ir_node *node) {
3542 ir_graph *irg = env->irg;
3543 //dbg_info *dbgi = get_irn_dbg_info(node);
3544 dbg_info *dbgi = NULL;
3545 ir_node *block = transform_node(env, get_nodes_block(node));
3547 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3552 static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) {
3553 ir_graph *irg = env->irg;
3554 dbg_info *dbgi = get_irn_dbg_info(node);
3555 long proj = get_Proj_proj(node);
3556 ir_mode *mode = get_irn_mode(node);
3557 ir_node *block = transform_node(env, get_nodes_block(node));
3559 ir_node *call = get_Proj_pred(node);
3560 ir_node *new_call = transform_node(env, call);
3561 const arch_register_class_t *cls;
3563 /* The following is kinda tricky: If we're using SSE, then we have to
3564 * move the result value of the call in floating point registers to an
3565 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3566 * after the call, we have to make sure to correctly make the
3567 * MemProj and the result Proj use these 2 nodes
3569 if(proj == pn_be_Call_M_regular) {
3570 // get new node for result, are we doing the sse load/store hack?
3571 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3572 ir_node *call_res_new;
3573 ir_node *call_res_pred = NULL;
3575 if(call_res != NULL) {
3576 call_res_new = transform_node(env, call_res);
3577 call_res_pred = get_Proj_pred(call_res_new);
3580 if(call_res_pred == NULL || be_is_Call(call_res_pred)) {
3581 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3583 assert(is_ia32_xLoad(call_res_pred));
3584 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3587 if(proj == pn_be_Call_first_res && mode_is_float(mode)
3588 && USE_SSE2(env->cg)) {
3590 ir_node *frame = get_irg_frame(irg);
3591 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3593 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3595 const arch_register_class_t *cls;
3597 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3598 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3600 /* store st(0) onto stack */
3601 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3603 set_ia32_ls_mode(fstp, mode);
3604 set_ia32_op_type(fstp, ia32_AddrModeD);
3605 set_ia32_use_frame(fstp);
3606 set_ia32_am_flavour(fstp, ia32_am_B);
3607 set_ia32_am_support(fstp, ia32_am_Dest);
3609 /* load into SSE register */
3610 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3611 set_ia32_ls_mode(sse_load, mode);
3612 set_ia32_op_type(sse_load, ia32_AddrModeS);
3613 set_ia32_use_frame(sse_load);
3614 set_ia32_am_flavour(sse_load, ia32_am_B);
3615 set_ia32_am_support(sse_load, ia32_am_Source);
3617 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3619 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3621 /* get a Proj representing a caller save register */
3622 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3623 assert(is_Proj(p) && "Proj expected.");
3625 /* user of the the proj is the Keep */
3626 p = get_edge_src_irn(get_irn_out_edge_first(p));
3627 assert(be_is_Keep(p) && "Keep expected.");
3629 /* keep the result */
3630 cls = arch_get_irn_reg_class(env->cg->arch_env, sse_load, -1);
3631 keepin[0] = sse_load;
3632 be_new_Keep(cls, irg, block, 1, keepin);
3637 /* transform call modes */
3638 if (mode_is_data(mode)) {
3639 cls = arch_get_irn_reg_class(env->cg->arch_env, node, -1);
3643 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3646 static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) {
3647 ir_graph *irg = env->irg;
3648 dbg_info *dbgi = get_irn_dbg_info(node);
3649 ir_node *pred = get_Proj_pred(node);
3650 long proj = get_Proj_proj(node);
3652 if(is_Store(pred) || be_is_FrameStore(pred)) {
3653 if(proj == pn_Store_M) {
3654 return transform_node(env, pred);
3657 return new_r_Bad(irg);
3659 } else if(is_Load(pred) || be_is_FrameLoad(pred)) {
3660 return gen_Proj_Load(env, node);
3661 } else if(is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3662 return gen_Proj_DivMod(env, node);
3663 } else if(is_CopyB(pred)) {
3664 return gen_Proj_CopyB(env, node);
3665 } else if(is_Quot(pred)) {
3666 return gen_Proj_Quot(env, node);
3667 } else if(is_ia32_l_vfdiv(pred)) {
3668 return gen_Proj_l_vfdiv(env, node);
3669 } else if(be_is_SubSP(pred)) {
3670 return gen_Proj_be_SubSP(env, node);
3671 } else if(be_is_AddSP(pred)) {
3672 return gen_Proj_be_AddSP(env, node);
3673 } else if(be_is_Call(pred)) {
3674 return gen_Proj_be_Call(env, node);
3675 } else if(get_irn_op(pred) == op_Start) {
3676 if(proj == pn_Start_X_initial_exec) {
3677 ir_node *block = get_nodes_block(pred);
3680 block = transform_node(env, block);
3681 // we exchange the ProjX with a jump
3682 jump = new_rd_Jmp(dbgi, irg, block);
3683 ir_fprintf(stderr, "created jump: %+F\n", jump);
3686 if(node == env->old_anchors[anchor_tls]) {
3687 return gen_Proj_tls(env, node);
3690 ir_node *new_pred = transform_node(env, pred);
3691 ir_node *block = transform_node(env, get_nodes_block(node));
3692 ir_mode *mode = get_irn_mode(node);
3693 if (mode_needs_gp_reg(mode)) {
3694 return new_r_Proj(irg, block, new_pred, mode_Iu, get_Proj_proj(node));
3698 return duplicate_node(env, node);
3702 * Enters all transform functions into the generic pointer
3704 static void register_transformers(void) {
3705 ir_op *op_Max, *op_Min, *op_Mulh;
3707 /* first clear the generic function pointer for all ops */
3708 clear_irp_opcodes_generic_func();
3710 #define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3711 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
3750 /* transform ops from intrinsic lowering */
3770 /* GEN(ia32_l_vfist); TODO */
3772 GEN(ia32_l_X87toSSE);
3773 GEN(ia32_l_SSEtoX87);
3778 /* we should never see these nodes */
3793 /* handle generic backend nodes */
3803 /* set the register for all Unknown nodes */
3806 op_Max = get_op_Max();
3809 op_Min = get_op_Min();
3812 op_Mulh = get_op_Mulh();
3820 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
3824 int deps = get_irn_deps(old_node);
3826 for(i = 0; i < deps; ++i) {
3827 ir_node *dep = get_irn_dep(old_node, i);
3828 ir_node *new_dep = transform_node(env, dep);
3830 add_irn_dep(new_node, new_dep);
3834 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node)
3836 ir_graph *irg = env->irg;
3837 dbg_info *dbgi = get_irn_dbg_info(node);
3838 ir_mode *mode = get_irn_mode(node);
3839 ir_op *op = get_irn_op(node);
3844 block = transform_node(env, get_nodes_block(node));
3846 arity = get_irn_arity(node);
3847 if(op->opar == oparity_dynamic) {
3848 new_node = new_ir_node(dbgi, irg, block, op, mode, -1, NULL);
3849 for(i = 0; i < arity; ++i) {
3850 ir_node *in = get_irn_n(node, i);
3851 in = transform_node(env, in);
3852 add_irn_n(new_node, in);
3855 ir_node **ins = alloca(arity * sizeof(ins[0]));
3856 for(i = 0; i < arity; ++i) {
3857 ir_node *in = get_irn_n(node, i);
3858 ins[i] = transform_node(env, in);
3861 new_node = new_ir_node(dbgi, irg, block, op, mode, arity, ins);
3864 copy_node_attr(node, new_node);
3865 duplicate_deps(env, node, new_node);
3870 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node)
3873 ir_op *op = get_irn_op(node);
3875 if(irn_visited(node)) {
3876 assert(get_new_node(node) != NULL);
3877 return get_new_node(node);
3880 mark_irn_visited(node);
3881 DEBUG_ONLY(set_new_node(node, NULL));
3883 if (op->ops.generic) {
3884 transform_func *transform = (transform_func *)op->ops.generic;
3886 new_node = (*transform)(env, node);
3887 assert(new_node != NULL);
3889 new_node = duplicate_node(env, node);
3891 //ir_fprintf(stderr, "%+F -> %+F\n", node, new_node);
3893 set_new_node(node, new_node);
3894 mark_irn_visited(new_node);
3895 hook_dead_node_elim_subst(current_ir_graph, node, new_node);
3899 static void fix_loops(ia32_transform_env_t *env, ir_node *node)
3903 if(irn_visited(node))
3905 mark_irn_visited(node);
3907 assert(node_is_in_irgs_storage(env->irg, node));
3909 if(!is_Block(node)) {
3910 ir_node *block = get_nodes_block(node);
3911 ir_node *new_block = (ir_node*) get_irn_link(block);
3913 if(new_block != NULL) {
3914 set_nodes_block(node, new_block);
3918 fix_loops(env, block);
3921 arity = get_irn_arity(node);
3922 for(i = 0; i < arity; ++i) {
3923 ir_node *in = get_irn_n(node, i);
3924 ir_node *new = (ir_node*) get_irn_link(in);
3926 if(new != NULL && new != in) {
3927 set_irn_n(node, i, new);
3934 arity = get_irn_deps(node);
3935 for(i = 0; i < arity; ++i) {
3936 ir_node *in = get_irn_dep(node, i);
3937 ir_node *new = (ir_node*) get_irn_link(in);
3939 if(new != NULL && new != in) {
3940 set_irn_dep(node, i, new);
3948 static void pre_transform_node(ir_node **place, ia32_transform_env_t *env)
3953 *place = transform_node(env, *place);
3956 static void transform_nodes(ia32_code_gen_t *cg)
3959 ir_graph *irg = cg->irg;
3961 ia32_transform_env_t env;
3963 hook_dead_node_elim(irg, 1);
3965 inc_irg_visited(irg);
3969 env.visited = get_irg_visited(irg);
3970 env.worklist = new_pdeq();
3971 env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
3973 old_end = get_irg_end(irg);
3975 /* put all anchor nodes in the worklist */
3976 for(i = 0; i < anchor_max; ++i) {
3977 ir_node *anchor = irg->anchors[i];
3980 pdeq_putr(env.worklist, anchor);
3983 env.old_anchors[i] = anchor;
3984 // and set it to NULL to make sure we don't accidently use it
3985 irg->anchors[i] = NULL;
3988 // pre transform some anchors (so they are available in the other transform
3990 set_irg_bad(irg, transform_node(&env, env.old_anchors[anchor_bad]));
3991 set_irg_no_mem(irg, transform_node(&env, env.old_anchors[anchor_no_mem]));
3992 set_irg_start_block(irg, transform_node(&env, env.old_anchors[anchor_start_block]));
3993 set_irg_start(irg, transform_node(&env, env.old_anchors[anchor_start]));
3994 set_irg_frame(irg, transform_node(&env, env.old_anchors[anchor_frame]));
3996 pre_transform_node(&cg->unknown_gp, &env);
3997 pre_transform_node(&cg->unknown_vfp, &env);
3998 pre_transform_node(&cg->unknown_xmm, &env);
3999 pre_transform_node(&cg->noreg_gp, &env);
4000 pre_transform_node(&cg->noreg_vfp, &env);
4001 pre_transform_node(&cg->noreg_xmm, &env);
4003 /* process worklist (this should transform all nodes in the graph) */
4004 while(!pdeq_empty(env.worklist)) {
4005 ir_node *node = pdeq_getl(env.worklist);
4006 transform_node(&env, node);
4009 /* fix loops and set new anchors*/
4010 inc_irg_visited(irg);
4011 for(i = 0; i < anchor_max; ++i) {
4012 ir_node *anchor = env.old_anchors[i];
4016 anchor = get_irn_link(anchor);
4017 fix_loops(&env, anchor);
4018 assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
4019 irg->anchors[i] = anchor;
4022 del_pdeq(env.worklist);
4024 hook_dead_node_elim(irg, 0);
4027 void ia32_transform_graph(ia32_code_gen_t *cg)
4029 ir_graph *irg = cg->irg;
4030 be_irg_t *birg = cg->birg;
4031 ir_graph *old_current_ir_graph = current_ir_graph;
4032 int old_interprocedural_view = get_interprocedural_view();
4033 struct obstack *old_obst = NULL;
4034 struct obstack *new_obst = NULL;
4036 current_ir_graph = irg;
4037 set_interprocedural_view(0);
4038 register_transformers();
4040 /* most analysis info is wrong after transformation */
4041 free_callee_info(irg);
4043 irg->outs_state = outs_none;
4045 free_loop_information(irg);
4046 set_irg_doms_inconsistent(irg);
4047 be_invalidate_liveness(birg);
4048 be_invalidate_dom_front(birg);
4050 /* create a new obstack */
4051 old_obst = irg->obst;
4052 new_obst = xmalloc(sizeof(*new_obst));
4053 obstack_init(new_obst);
4054 irg->obst = new_obst;
4055 irg->last_node_idx = 0;
4057 /* create new value table for CSE */
4058 del_identities(irg->value_table);
4059 irg->value_table = new_identities();
4061 /* do the main transformation */
4062 transform_nodes(cg);
4064 /* we don't want the globals anchor anymore */
4065 set_irg_globals(irg, new_r_Bad(irg));
4067 /* free the old obstack */
4068 obstack_free(old_obst, 0);
4072 current_ir_graph = old_current_ir_graph;
4073 set_interprocedural_view(old_interprocedural_view);
4075 /* recalculate edges */
4076 edges_deactivate(irg);
4077 edges_activate(irg);
4081 * Transforms a psi condition.
4083 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
4086 /* if the mode is target mode, we have already seen this part of the tree */
4087 if (get_irn_mode(cond) == mode)
4090 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
4092 set_irn_mode(cond, mode);
4094 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
4095 ir_node *in = get_irn_n(cond, i);
4097 /* if in is a compare: transform into Set/xCmp */
4099 ir_node *new_op = NULL;
4100 ir_node *cmp = get_Proj_pred(in);
4101 ir_node *cmp_a = get_Cmp_left(cmp);
4102 ir_node *cmp_b = get_Cmp_right(cmp);
4103 dbg_info *dbgi = get_irn_dbg_info(cmp);
4104 ir_graph *irg = get_irn_irg(cmp);
4105 ir_node *block = get_nodes_block(cmp);
4106 ir_node *noreg = ia32_new_NoReg_gp(cg);
4107 ir_node *nomem = new_rd_NoMem(irg);
4108 int pnc = get_Proj_proj(in);
4110 /* this is a compare */
4111 if (mode_is_float(mode)) {
4112 /* Psi is float, we need a floating point compare */
4115 ir_mode *m = get_irn_mode(cmp_a);
4117 if (! mode_is_float(m)) {
4118 cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_a, cmp_a, mode);
4119 cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_b, cmp_b, mode);
4120 } else if (m == mode_F) {
4121 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
4122 cmp_a = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_a, cmp_a);
4123 cmp_b = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_b, cmp_b);
4126 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4127 set_ia32_pncode(new_op, pnc);
4128 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
4135 construct_binop_func *set_func = NULL;
4137 if (mode_is_float(get_irn_mode(cmp_a))) {
4138 /* 1st case: compare operands are floats */
4143 set_func = new_rd_ia32_xCmpSet;
4146 set_func = new_rd_ia32_vfCmpSet;
4149 pnc &= 7; /* fp compare -> int compare */
4151 /* 2nd case: compare operand are integer too */
4152 set_func = new_rd_ia32_CmpSet;
4155 new_op = set_func(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4156 if(!mode_is_signed(mode))
4157 pnc |= ia32_pn_Cmp_Unsigned;
4159 set_ia32_pncode(new_op, pnc);
4160 set_ia32_am_support(new_op, ia32_am_Source);
4163 /* the the new compare as in */
4164 set_irn_n(cond, i, new_op);
4166 /* another complex condition */
4167 transform_psi_cond(in, mode, cg);
4173 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
4174 * We create a Set node, respectively a xCmp in case the Psi is a float, for
4175 * each compare, which causes the compare result to be stored in a register. The
4176 * "And"s and "Or"s are transformed later, we just have to set their mode right.
4178 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
4179 ia32_code_gen_t *cg = env;
4180 ir_node *psi_sel, *new_cmp, *block;
4185 if (get_irn_opcode(node) != iro_Psi)
4188 psi_sel = get_Psi_cond(node, 0);
4190 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
4191 if (is_Proj(psi_sel)) {
4192 assert(is_Cmp(get_Proj_pred(psi_sel)));
4196 //mode = get_irn_mode(node);
4197 // TODO probably wrong...
4200 transform_psi_cond(psi_sel, mode, cg);
4202 irg = get_irn_irg(node);
4203 block = get_nodes_block(node);
4205 /* we need to compare the evaluated condition tree with 0 */
4206 mode = get_irn_mode(node);
4207 if (mode_is_float(mode)) {
4208 /* BEWARE: new_r_Const_long works for floating point as well */
4209 ir_node *zero = new_r_Const_long(irg, block, mode, 0);
4211 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
4212 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4213 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
4215 ir_node *zero = new_r_Const_long(irg, block, mode_Iu, 0);
4216 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4217 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
4220 set_Psi_cond(node, 0, new_cmp);
4223 void ia32_init_transform(void)
4225 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");