2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
33 #include "irgraph_t.h"
38 #include "iredges_t.h"
55 #include "betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_common_transform.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_address_mode.h"
66 #include "ia32_architecture.h"
68 #include "gen_ia32_regalloc_if.h"
70 /* define this to construct SSE constants instead of load them */
71 #undef CONSTRUCT_SSE_CONST
73 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
74 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
76 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
78 static ir_node *old_initial_fpcw = NULL;
79 static ir_node *initial_fpcw = NULL;
80 int ia32_no_pic_adjust;
82 typedef ir_node *construct_binop_func(dbg_info *db, ir_node *block,
83 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1,
86 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_node *block,
87 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2,
90 typedef ir_node *construct_shift_func(dbg_info *db, ir_node *block,
91 ir_node *op1, ir_node *op2);
93 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_node *block,
94 ir_node *base, ir_node *index, ir_node *mem, ir_node *op);
96 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_node *block,
97 ir_node *base, ir_node *index, ir_node *mem);
99 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_node *block,
100 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2,
103 typedef ir_node *construct_unop_func(dbg_info *db, ir_node *block, ir_node *op);
105 static ir_node *create_immediate_or_transform(ir_node *node,
106 char immediate_constraint_type);
108 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
109 dbg_info *dbgi, ir_node *block,
110 ir_node *op, ir_node *orig_node);
112 /* its enough to have those once */
113 static ir_node *nomem, *noreg_GP;
115 /** a list to postprocess all calls */
116 static ir_node **call_list;
117 static ir_type **call_types;
119 /** Return non-zero is a node represents the 0 constant. */
120 static bool is_Const_0(ir_node *node)
122 return is_Const(node) && is_Const_null(node);
125 /** Return non-zero is a node represents the 1 constant. */
126 static bool is_Const_1(ir_node *node)
128 return is_Const(node) && is_Const_one(node);
131 /** Return non-zero is a node represents the -1 constant. */
132 static bool is_Const_Minus_1(ir_node *node)
134 return is_Const(node) && is_Const_all_one(node);
138 * returns true if constant can be created with a simple float command
140 static bool is_simple_x87_Const(ir_node *node)
142 ir_tarval *tv = get_Const_tarval(node);
143 if (tarval_is_null(tv) || tarval_is_one(tv))
146 /* TODO: match all the other float constants */
151 * returns true if constant can be created with a simple float command
153 static bool is_simple_sse_Const(ir_node *node)
155 ir_tarval *tv = get_Const_tarval(node);
156 ir_mode *mode = get_tarval_mode(tv);
161 if (tarval_is_null(tv)
162 #ifdef CONSTRUCT_SSE_CONST
167 #ifdef CONSTRUCT_SSE_CONST
168 if (mode == mode_D) {
169 unsigned val = get_tarval_sub_bits(tv, 0) |
170 (get_tarval_sub_bits(tv, 1) << 8) |
171 (get_tarval_sub_bits(tv, 2) << 16) |
172 (get_tarval_sub_bits(tv, 3) << 24);
174 /* lower 32bit are zero, really a 32bit constant */
177 #endif /* CONSTRUCT_SSE_CONST */
178 /* TODO: match all the other float constants */
183 * return NoREG or pic_base in case of PIC.
184 * This is necessary as base address for newly created symbols
186 static ir_node *get_symconst_base(void)
188 ir_graph *irg = current_ir_graph;
190 if (be_options.pic) {
191 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
192 return arch_env->impl->get_pic_base(irg);
199 * Transforms a Const.
201 static ir_node *gen_Const(ir_node *node)
203 ir_node *old_block = get_nodes_block(node);
204 ir_node *block = be_transform_node(old_block);
205 dbg_info *dbgi = get_irn_dbg_info(node);
206 ir_mode *mode = get_irn_mode(node);
207 ir_tarval *tv = get_Const_tarval(node);
209 assert(is_Const(node));
211 if (mode_is_float(mode)) {
212 ir_graph *irg = get_irn_irg(node);
213 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
214 ia32_isa_t *isa = (ia32_isa_t*) arch_env;
219 if (ia32_cg_config.use_sse2) {
220 if (tarval_is_null(tv)) {
221 load = new_bd_ia32_xZero(dbgi, block);
222 set_ia32_ls_mode(load, mode);
224 #ifdef CONSTRUCT_SSE_CONST
225 } else if (tarval_is_one(tv)) {
226 int cnst = mode == mode_F ? 26 : 55;
227 ir_node *imm1 = ia32_create_Immediate(NULL, 0, cnst);
228 ir_node *imm2 = ia32_create_Immediate(NULL, 0, 2);
229 ir_node *pslld, *psrld;
231 load = new_bd_ia32_xAllOnes(dbgi, block);
232 set_ia32_ls_mode(load, mode);
233 pslld = new_bd_ia32_xPslld(dbgi, block, load, imm1);
234 set_ia32_ls_mode(pslld, mode);
235 psrld = new_bd_ia32_xPsrld(dbgi, block, pslld, imm2);
236 set_ia32_ls_mode(psrld, mode);
238 #endif /* CONSTRUCT_SSE_CONST */
239 } else if (mode == mode_F) {
240 /* we can place any 32bit constant by using a movd gp, sse */
241 unsigned val = get_tarval_sub_bits(tv, 0) |
242 (get_tarval_sub_bits(tv, 1) << 8) |
243 (get_tarval_sub_bits(tv, 2) << 16) |
244 (get_tarval_sub_bits(tv, 3) << 24);
245 ir_node *cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
246 load = new_bd_ia32_xMovd(dbgi, block, cnst);
247 set_ia32_ls_mode(load, mode);
251 #ifdef CONSTRUCT_SSE_CONST
252 if (mode == mode_D) {
253 unsigned val = get_tarval_sub_bits(tv, 0) |
254 (get_tarval_sub_bits(tv, 1) << 8) |
255 (get_tarval_sub_bits(tv, 2) << 16) |
256 (get_tarval_sub_bits(tv, 3) << 24);
258 ir_node *imm32 = ia32_create_Immediate(NULL, 0, 32);
259 ir_node *cnst, *psllq;
261 /* fine, lower 32bit are zero, produce 32bit value */
262 val = get_tarval_sub_bits(tv, 4) |
263 (get_tarval_sub_bits(tv, 5) << 8) |
264 (get_tarval_sub_bits(tv, 6) << 16) |
265 (get_tarval_sub_bits(tv, 7) << 24);
266 cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
267 load = new_bd_ia32_xMovd(dbgi, block, cnst);
268 set_ia32_ls_mode(load, mode);
269 psllq = new_bd_ia32_xPsllq(dbgi, block, load, imm32);
270 set_ia32_ls_mode(psllq, mode);
275 #endif /* CONSTRUCT_SSE_CONST */
276 floatent = ia32_create_float_const_entity(isa, tv, NULL);
278 base = get_symconst_base();
279 load = new_bd_ia32_xLoad(dbgi, block, base, noreg_GP, nomem,
281 set_ia32_op_type(load, ia32_AddrModeS);
282 set_ia32_am_sc(load, floatent);
283 arch_add_irn_flags(load, arch_irn_flags_rematerializable);
284 res = new_r_Proj(load, mode_xmm, pn_ia32_xLoad_res);
287 if (tarval_is_null(tv)) {
288 load = new_bd_ia32_vfldz(dbgi, block);
290 set_ia32_ls_mode(load, mode);
291 } else if (tarval_is_one(tv)) {
292 load = new_bd_ia32_vfld1(dbgi, block);
294 set_ia32_ls_mode(load, mode);
299 floatent = ia32_create_float_const_entity(isa, tv, NULL);
300 /* create_float_const_ent is smart and sometimes creates
302 ls_mode = get_type_mode(get_entity_type(floatent));
303 base = get_symconst_base();
304 load = new_bd_ia32_vfld(dbgi, block, base, noreg_GP, nomem,
306 set_ia32_op_type(load, ia32_AddrModeS);
307 set_ia32_am_sc(load, floatent);
308 arch_add_irn_flags(load, arch_irn_flags_rematerializable);
309 res = new_r_Proj(load, mode_vfp, pn_ia32_vfld_res);
312 #ifdef CONSTRUCT_SSE_CONST
314 #endif /* CONSTRUCT_SSE_CONST */
315 SET_IA32_ORIG_NODE(load, node);
317 } else { /* non-float mode */
321 tv = tarval_convert_to(tv, mode_Iu);
323 if (tv == get_tarval_bad() || tv == get_tarval_undefined() ||
325 panic("couldn't convert constant tarval (%+F)", node);
327 val = get_tarval_long(tv);
329 cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
330 SET_IA32_ORIG_NODE(cnst, node);
337 * Transforms a SymConst.
339 static ir_node *gen_SymConst(ir_node *node)
341 ir_node *old_block = get_nodes_block(node);
342 ir_node *block = be_transform_node(old_block);
343 dbg_info *dbgi = get_irn_dbg_info(node);
344 ir_mode *mode = get_irn_mode(node);
347 if (mode_is_float(mode)) {
348 if (ia32_cg_config.use_sse2)
349 cnst = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode_D);
351 cnst = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem, ia32_mode_E);
352 set_ia32_am_sc(cnst, get_SymConst_entity(node));
353 set_ia32_use_frame(cnst);
357 if (get_SymConst_kind(node) != symconst_addr_ent) {
358 panic("backend only support symconst_addr_ent (at %+F)", node);
360 entity = get_SymConst_entity(node);
361 if (get_entity_owner(entity) == get_tls_type()) {
362 ir_node *tls_base = new_bd_ia32_LdTls(NULL, block);
363 ir_node *lea = new_bd_ia32_Lea(dbgi, block, tls_base, noreg_GP);
364 set_ia32_am_sc(lea, entity);
367 cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0, 0);
371 SET_IA32_ORIG_NODE(cnst, node);
376 static ir_type *make_array_type(ir_type *tp)
378 unsigned alignment = get_type_alignment_bytes(tp);
379 unsigned size = get_type_size_bytes(tp);
380 ir_type *res = new_type_array(1, tp);
381 set_type_alignment_bytes(res, alignment);
382 set_array_bounds_int(res, 0, 0, 2);
383 if (alignment > size)
385 set_type_size_bytes(res, 2 * size);
386 set_type_state(res, layout_fixed);
391 * Create a float[2] array type for the given atomic type.
393 * @param tp the atomic type
395 static ir_type *ia32_create_float_array(ir_type *tp)
397 ir_mode *mode = get_type_mode(tp);
400 if (mode == mode_F) {
401 static ir_type *float_F;
405 arr = float_F = make_array_type(tp);
406 } else if (mode == mode_D) {
407 static ir_type *float_D;
411 arr = float_D = make_array_type(tp);
413 static ir_type *float_E;
417 arr = float_E = make_array_type(tp);
422 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
423 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct)
425 static const struct {
427 const char *cnst_str;
429 } names [ia32_known_const_max] = {
430 { "C_sfp_sign", "0x80000000", 0 },
431 { "C_dfp_sign", "0x8000000000000000", 1 },
432 { "C_sfp_abs", "0x7FFFFFFF", 0 },
433 { "C_dfp_abs", "0x7FFFFFFFFFFFFFFF", 1 },
434 { "C_ull_bias", "0x10000000000000000", 2 }
436 static ir_entity *ent_cache[ia32_known_const_max];
438 ir_entity *ent = ent_cache[kct];
441 ir_graph *irg = current_ir_graph;
442 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
443 ia32_isa_t *isa = (ia32_isa_t*) arch_env;
444 const char *cnst_str = names[kct].cnst_str;
445 ident *name = new_id_from_str(names[kct].name);
448 switch (names[kct].mode) {
449 case 0: mode = mode_Iu; break;
450 case 1: mode = mode_Lu; break;
451 case 2: mode = mode_F; break;
452 default: panic("internal compiler error");
454 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
456 if (kct == ia32_ULLBIAS) {
457 ir_type *type = ia32_get_prim_type(mode_F);
458 ir_type *atype = ia32_create_float_array(type);
459 ir_initializer_t *initializer;
461 ent = new_entity(get_glob_type(), name, atype);
463 set_entity_ld_ident(ent, name);
464 set_entity_visibility(ent, ir_visibility_private);
465 add_entity_linkage(ent, IR_LINKAGE_CONSTANT);
467 initializer = create_initializer_compound(2);
468 set_initializer_compound_value(initializer, 0,
469 create_initializer_tarval(get_mode_null(mode)));
470 set_initializer_compound_value(initializer, 1,
471 create_initializer_tarval(tv));
472 set_entity_initializer(ent, initializer);
474 ent = ia32_create_float_const_entity(isa, tv, name);
476 /* cache the entry */
477 ent_cache[kct] = ent;
480 return ent_cache[kct];
484 * return true if the node is a Proj(Load) and could be used in source address
485 * mode for another node. Will return only true if the @p other node is not
486 * dependent on the memory of the Load (for binary operations use the other
487 * input here, for unary operations use NULL).
489 static int ia32_use_source_address_mode(ir_node *block, ir_node *node,
490 ir_node *other, ir_node *other2,
497 /* float constants are always available */
498 if (is_Const(node)) {
499 mode = get_irn_mode(node);
500 if (mode_is_float(mode)) {
501 ir_tarval *tv = get_Const_tarval(node);
502 if (!tarval_ieee754_can_conv_lossless(tv, mode_D))
504 if (ia32_cg_config.use_sse2) {
505 if (is_simple_sse_Const(node))
508 if (is_simple_x87_Const(node))
511 if (get_irn_n_edges(node) > 1)
520 load = get_Proj_pred(node);
521 pn = get_Proj_proj(node);
522 if (!is_Load(load) || pn != pn_Load_res)
524 if (get_nodes_block(load) != block)
526 mode = get_irn_mode(node);
527 /* we can't fold mode_E AM */
528 if (mode == ia32_mode_E)
530 /* we only use address mode if we're the only user of the load */
531 if (get_irn_n_edges(node) != (flags & match_two_users ? 2 : 1))
533 /* in some edge cases with address mode we might reach the load normally
534 * and through some AM sequence, if it is already materialized then we
535 * can't create an AM node from it */
536 if (be_is_transformed(node))
539 /* don't do AM if other node inputs depend on the load (via mem-proj) */
540 if (other != NULL && ia32_prevents_AM(block, load, other))
543 if (other2 != NULL && ia32_prevents_AM(block, load, other2))
549 typedef struct ia32_address_mode_t ia32_address_mode_t;
550 struct ia32_address_mode_t {
555 ia32_op_type_t op_type;
559 unsigned commutative : 1;
560 unsigned ins_permuted : 1;
563 static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
565 /* construct load address */
566 memset(addr, 0, sizeof(addr[0]));
567 ia32_create_address_mode(addr, ptr, ia32_create_am_normal);
569 addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP;
570 addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP;
571 addr->mem = be_transform_node(mem);
574 static void build_address(ia32_address_mode_t *am, ir_node *node,
575 ia32_create_am_flags_t flags)
577 ia32_address_t *addr = &am->addr;
583 /* floating point immediates */
584 if (is_Const(node)) {
585 ir_graph *irg = get_irn_irg(node);
586 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
587 ia32_isa_t *isa = (ia32_isa_t*) arch_env;
588 ir_tarval *tv = get_Const_tarval(node);
589 ir_entity *entity = ia32_create_float_const_entity(isa, tv, NULL);
590 addr->base = get_symconst_base();
591 addr->index = noreg_GP;
593 addr->symconst_ent = entity;
594 addr->tls_segment = false;
596 am->ls_mode = get_type_mode(get_entity_type(entity));
597 am->pinned = op_pin_state_floats;
601 load = get_Proj_pred(node);
602 ptr = get_Load_ptr(load);
603 mem = get_Load_mem(load);
604 new_mem = be_transform_node(mem);
605 am->pinned = get_irn_pinned(load);
606 am->ls_mode = get_Load_mode(load);
607 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
610 /* construct load address */
611 ia32_create_address_mode(addr, ptr, flags);
613 addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP;
614 addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP;
618 static void set_address(ir_node *node, const ia32_address_t *addr)
620 set_ia32_am_scale(node, addr->scale);
621 set_ia32_am_sc(node, addr->symconst_ent);
622 set_ia32_am_offs_int(node, addr->offset);
623 set_ia32_am_tls_segment(node, addr->tls_segment);
624 if (addr->symconst_sign)
625 set_ia32_am_sc_sign(node);
627 set_ia32_use_frame(node);
628 set_ia32_frame_ent(node, addr->frame_entity);
632 * Apply attributes of a given address mode to a node.
634 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
636 set_address(node, &am->addr);
638 set_ia32_op_type(node, am->op_type);
639 set_ia32_ls_mode(node, am->ls_mode);
640 if (am->pinned == op_pin_state_pinned) {
641 /* beware: some nodes are already pinned and did not allow to change the state */
642 if (get_irn_pinned(node) != op_pin_state_pinned)
643 set_irn_pinned(node, op_pin_state_pinned);
646 set_ia32_commutative(node);
650 * Check, if a given node is a Down-Conv, ie. a integer Conv
651 * from a mode with a mode with more bits to a mode with lesser bits.
652 * Moreover, we return only true if the node has not more than 1 user.
654 * @param node the node
655 * @return non-zero if node is a Down-Conv
657 static int is_downconv(const ir_node *node)
665 src_mode = get_irn_mode(get_Conv_op(node));
666 dest_mode = get_irn_mode(node);
668 ia32_mode_needs_gp_reg(src_mode) &&
669 ia32_mode_needs_gp_reg(dest_mode) &&
670 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
673 /** Skip all Down-Conv's on a given node and return the resulting node. */
674 ir_node *ia32_skip_downconv(ir_node *node)
676 while (is_downconv(node)) {
677 /* we only want to skip the conv when we're the only user
678 * (because this test is used in the context of address-mode selection
679 * and we don't want to use address mode for multiple users) */
680 if (get_irn_n_edges(node) > 1)
683 node = get_Conv_op(node);
689 static bool is_sameconv(ir_node *node)
697 /* we only want to skip the conv when we're the only user
698 * (because this test is used in the context of address-mode selection
699 * and we don't want to use address mode for multiple users) */
700 if (get_irn_n_edges(node) > 1)
703 src_mode = get_irn_mode(get_Conv_op(node));
704 dest_mode = get_irn_mode(node);
706 ia32_mode_needs_gp_reg(src_mode) &&
707 ia32_mode_needs_gp_reg(dest_mode) &&
708 get_mode_size_bits(dest_mode) == get_mode_size_bits(src_mode);
711 /** Skip all signedness convs */
712 static ir_node *ia32_skip_sameconv(ir_node *node)
714 while (is_sameconv(node)) {
715 node = get_Conv_op(node);
721 static ir_node *transform_sext(ir_node *node, ir_node *orig_node)
723 ir_mode *mode = get_irn_mode(node);
724 ir_node *block = get_nodes_block(node);
725 dbg_info *dbgi = get_irn_dbg_info(node);
726 return create_I2I_Conv(mode, mode_Is, dbgi, block, node, orig_node);
729 static ir_node *transform_zext(ir_node *node, ir_node *orig_node)
731 ir_mode *mode = get_irn_mode(node);
732 ir_node *block = get_nodes_block(node);
733 dbg_info *dbgi = get_irn_dbg_info(node);
734 /* normalize to an unsigned mode */
735 switch (get_mode_size_bits(mode)) {
736 case 8: mode = mode_Bu; break;
737 case 16: mode = mode_Hu; break;
739 panic("ia32: invalid mode in zest: %+F", node);
741 return create_I2I_Conv(mode, mode_Iu, dbgi, block, node, orig_node);
744 static ir_node *transform_upconv(ir_node *node, ir_node *orig_node)
746 ir_mode *mode = get_irn_mode(node);
747 if (mode_is_signed(mode)) {
748 return transform_sext(node, orig_node);
750 return transform_zext(node, orig_node);
755 * matches operands of a node into ia32 addressing/operand modes. This covers
756 * usage of source address mode, immediates, operations with non 32-bit modes,
758 * The resulting data is filled into the @p am struct. block is the block
759 * of the node whose arguments are matched. op1, op2 are the first and second
760 * input that are matched (op1 may be NULL). other_op is another unrelated
761 * input that is not matched! but which is needed sometimes to check if AM
762 * for op1/op2 is legal.
763 * @p flags describes the supported modes of the operation in detail.
765 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
766 ir_node *op1, ir_node *op2, ir_node *other_op,
769 ia32_address_t *addr = &am->addr;
770 ir_mode *mode = get_irn_mode(op2);
771 int mode_bits = get_mode_size_bits(mode);
772 ir_node *new_op1, *new_op2;
774 unsigned commutative;
775 int use_am_and_immediates;
778 memset(am, 0, sizeof(am[0]));
780 commutative = (flags & match_commutative) != 0;
781 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
782 use_am = (flags & match_am) != 0;
783 use_immediate = (flags & match_immediate) != 0;
784 assert(!use_am_and_immediates || use_immediate);
787 assert(!commutative || op1 != NULL);
788 assert(use_am || !(flags & match_8bit_am));
789 assert(use_am || !(flags & match_16bit_am));
791 if ((mode_bits == 8 && !(flags & match_8bit_am)) ||
792 (mode_bits == 16 && !(flags & match_16bit_am))) {
796 /* we can simply skip downconvs for mode neutral nodes: the upper bits
797 * can be random for these operations */
798 if (flags & match_mode_neutral) {
799 op2 = ia32_skip_downconv(op2);
801 op1 = ia32_skip_downconv(op1);
804 op2 = ia32_skip_sameconv(op2);
806 op1 = ia32_skip_sameconv(op1);
810 /* match immediates. firm nodes are normalized: constants are always on the
813 if (!(flags & match_try_am) && use_immediate) {
814 new_op2 = ia32_try_create_Immediate(op2, 0);
817 if (new_op2 == NULL &&
818 use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) {
819 build_address(am, op2, ia32_create_am_normal);
820 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
821 if (mode_is_float(mode)) {
822 new_op2 = ia32_new_NoReg_vfp(current_ir_graph);
826 am->op_type = ia32_AddrModeS;
827 } else if (commutative && (new_op2 == NULL || use_am_and_immediates) &&
829 ia32_use_source_address_mode(block, op1, op2, other_op, flags)) {
831 build_address(am, op1, ia32_create_am_normal);
833 if (mode_is_float(mode)) {
834 noreg = ia32_new_NoReg_vfp(current_ir_graph);
839 if (new_op2 != NULL) {
842 new_op1 = be_transform_node(op2);
844 am->ins_permuted = true;
846 am->op_type = ia32_AddrModeS;
848 am->op_type = ia32_Normal;
850 if (flags & match_try_am) {
856 mode = get_irn_mode(op2);
857 if (get_mode_size_bits(mode) != 32
858 && (flags & (match_mode_neutral | match_upconv | match_zero_ext))) {
859 if (flags & match_upconv) {
860 new_op1 = (op1 == NULL ? NULL : transform_upconv(op1, op1));
862 new_op2 = transform_upconv(op2, op2);
863 } else if (flags & match_zero_ext) {
864 new_op1 = (op1 == NULL ? NULL : transform_zext(op1, op1));
866 new_op2 = transform_zext(op2, op2);
868 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
870 new_op2 = be_transform_node(op2);
871 assert(flags & match_mode_neutral);
875 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
877 new_op2 = be_transform_node(op2);
881 if (addr->base == NULL)
882 addr->base = noreg_GP;
883 if (addr->index == NULL)
884 addr->index = noreg_GP;
885 if (addr->mem == NULL)
888 am->new_op1 = new_op1;
889 am->new_op2 = new_op2;
890 am->commutative = commutative;
894 * "Fixes" a node that uses address mode by turning it into mode_T
895 * and returning a pn_ia32_res Proj.
897 * @param node the node
898 * @param am its address mode
900 * @return a Proj(pn_ia32_res) if a memory address mode is used,
903 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
908 if (am->mem_proj == NULL)
911 /* we have to create a mode_T so the old MemProj can attach to us */
912 mode = get_irn_mode(node);
913 load = get_Proj_pred(am->mem_proj);
915 be_set_transformed_node(load, node);
917 if (mode != mode_T) {
918 set_irn_mode(node, mode_T);
919 return new_rd_Proj(NULL, node, mode, pn_ia32_res);
926 * Construct a standard binary operation, set AM and immediate if required.
928 * @param node The original node for which the binop is created
929 * @param op1 The first operand
930 * @param op2 The second operand
931 * @param func The node constructor function
932 * @return The constructed ia32 node.
934 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
935 construct_binop_func *func, match_flags_t flags)
938 ir_node *block, *new_block, *new_node;
939 ia32_address_mode_t am;
940 ia32_address_t *addr = &am.addr;
942 block = get_nodes_block(node);
943 match_arguments(&am, block, op1, op2, NULL, flags);
945 dbgi = get_irn_dbg_info(node);
946 new_block = be_transform_node(block);
947 new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem,
948 am.new_op1, am.new_op2);
949 set_am_attributes(new_node, &am);
950 /* we can't use source address mode anymore when using immediates */
951 if (!(flags & match_am_and_immediates) &&
952 (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)))
953 set_ia32_am_support(new_node, ia32_am_none);
954 SET_IA32_ORIG_NODE(new_node, node);
956 new_node = fix_mem_proj(new_node, &am);
962 * Generic names for the inputs of an ia32 binary op.
965 n_ia32_l_binop_left, /**< ia32 left input */
966 n_ia32_l_binop_right, /**< ia32 right input */
967 n_ia32_l_binop_eflags /**< ia32 eflags input */
969 COMPILETIME_ASSERT((int)n_ia32_l_binop_left == (int)n_ia32_l_Adc_left, n_Adc_left)
970 COMPILETIME_ASSERT((int)n_ia32_l_binop_right == (int)n_ia32_l_Adc_right, n_Adc_right)
971 COMPILETIME_ASSERT((int)n_ia32_l_binop_eflags == (int)n_ia32_l_Adc_eflags, n_Adc_eflags)
972 COMPILETIME_ASSERT((int)n_ia32_l_binop_left == (int)n_ia32_l_Sbb_minuend, n_Sbb_minuend)
973 COMPILETIME_ASSERT((int)n_ia32_l_binop_right == (int)n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend)
974 COMPILETIME_ASSERT((int)n_ia32_l_binop_eflags == (int)n_ia32_l_Sbb_eflags, n_Sbb_eflags)
977 * Construct a binary operation which also consumes the eflags.
979 * @param node The node to transform
980 * @param func The node constructor function
981 * @param flags The match flags
982 * @return The constructor ia32 node
984 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
987 ir_node *src_block = get_nodes_block(node);
988 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
989 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
990 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
992 ir_node *block, *new_node, *new_eflags;
993 ia32_address_mode_t am;
994 ia32_address_t *addr = &am.addr;
996 match_arguments(&am, src_block, op1, op2, eflags, flags);
998 dbgi = get_irn_dbg_info(node);
999 block = be_transform_node(src_block);
1000 new_eflags = be_transform_node(eflags);
1001 new_node = func(dbgi, block, addr->base, addr->index, addr->mem,
1002 am.new_op1, am.new_op2, new_eflags);
1003 set_am_attributes(new_node, &am);
1004 /* we can't use source address mode anymore when using immediates */
1005 if (!(flags & match_am_and_immediates) &&
1006 (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)))
1007 set_ia32_am_support(new_node, ia32_am_none);
1008 SET_IA32_ORIG_NODE(new_node, node);
1010 new_node = fix_mem_proj(new_node, &am);
1015 static ir_node *get_fpcw(void)
1017 if (initial_fpcw != NULL)
1018 return initial_fpcw;
1020 initial_fpcw = be_transform_node(old_initial_fpcw);
1021 return initial_fpcw;
1024 static ir_node *skip_float_upconv(ir_node *node)
1026 ir_mode *mode = get_irn_mode(node);
1027 assert(mode_is_float(mode));
1029 while (is_Conv(node)) {
1030 ir_node *pred = get_Conv_op(node);
1031 ir_mode *pred_mode = get_irn_mode(pred);
1034 * suboptimal, but without this check the address mode matcher
1035 * can incorrectly think that something has only 1 user
1037 if (get_irn_n_edges(node) > 1)
1040 if (!mode_is_float(pred_mode)
1041 || get_mode_size_bits(pred_mode) > get_mode_size_bits(mode))
1049 static void check_x87_floatmode(ir_mode *mode)
1051 if (mode != ia32_mode_E) {
1052 panic("ia32: x87 only supports x86 extended float mode");
1057 * Construct a standard binary operation, set AM and immediate if required.
1059 * @param op1 The first operand
1060 * @param op2 The second operand
1061 * @param func The node constructor function
1062 * @return The constructed ia32 node.
1064 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
1065 construct_binop_float_func *func)
1071 ia32_address_mode_t am;
1072 ia32_address_t *addr = &am.addr;
1073 ia32_x87_attr_t *attr;
1074 /* All operations are considered commutative, because there are reverse
1076 match_flags_t flags = match_commutative | match_am;
1078 = is_Div(node) ? get_Div_resmode(node) : get_irn_mode(node);
1079 check_x87_floatmode(mode);
1081 op1 = skip_float_upconv(op1);
1082 op2 = skip_float_upconv(op2);
1084 block = get_nodes_block(node);
1085 match_arguments(&am, block, op1, op2, NULL, flags);
1087 dbgi = get_irn_dbg_info(node);
1088 new_block = be_transform_node(block);
1089 new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem,
1090 am.new_op1, am.new_op2, get_fpcw());
1091 set_am_attributes(new_node, &am);
1093 attr = get_ia32_x87_attr(new_node);
1094 attr->attr.data.ins_permuted = am.ins_permuted;
1096 SET_IA32_ORIG_NODE(new_node, node);
1098 new_node = fix_mem_proj(new_node, &am);
1104 * Construct a shift/rotate binary operation, sets AM and immediate if required.
1106 * @param op1 The first operand
1107 * @param op2 The second operand
1108 * @param func The node constructor function
1109 * @return The constructed ia32 node.
1111 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
1112 construct_shift_func *func,
1113 match_flags_t flags)
1115 ir_mode *mode = get_irn_mode(node);
1117 assert(! mode_is_float(mode));
1118 assert(flags & match_immediate);
1119 assert((flags & ~(match_mode_neutral | match_zero_ext | match_upconv | match_immediate)) == 0);
1121 if (get_mode_modulo_shift(mode) != 32) {
1122 /* TODO: implement special cases for non-modulo shifts */
1123 panic("modulo shift!=32 not supported by ia32 backend");
1128 if (flags & match_mode_neutral) {
1129 op1 = ia32_skip_downconv(op1);
1130 new_op1 = be_transform_node(op1);
1132 op1 = ia32_skip_sameconv(op1);
1133 if (get_mode_size_bits(mode) != 32) {
1134 if (flags & match_upconv) {
1135 new_op1 = transform_upconv(op1, node);
1136 } else if (flags & match_zero_ext) {
1137 new_op1 = transform_zext(op1, node);
1139 /* match_mode_neutral not handled here because it makes no
1140 * sense for shift operations */
1141 panic("ia32 code selection failed for %+F", node);
1144 new_op1 = be_transform_node(op1);
1148 /* the shift amount can be any mode that is bigger than 5 bits, since all
1149 * other bits are ignored anyway */
1150 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
1151 ir_node *const op = get_Conv_op(op2);
1152 if (mode_is_float(get_irn_mode(op)))
1155 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
1157 new_op2 = create_immediate_or_transform(op2, 0);
1159 dbg_info *dbgi = get_irn_dbg_info(node);
1160 ir_node *block = get_nodes_block(node);
1161 ir_node *new_block = be_transform_node(block);
1162 ir_node *new_node = func(dbgi, new_block, new_op1, new_op2);
1163 SET_IA32_ORIG_NODE(new_node, node);
1165 /* lowered shift instruction may have a dependency operand, handle it here */
1166 if (get_irn_arity(node) == 3) {
1167 /* we have a dependency */
1168 ir_node* dep = get_irn_n(node, 2);
1169 if (get_irn_n_edges(dep) > 1) {
1170 /* ... which has at least one user other than 'node' */
1171 ir_node *new_dep = be_transform_node(dep);
1172 add_irn_dep(new_node, new_dep);
1181 * Construct a standard unary operation, set AM and immediate if required.
1183 * @param op The operand
1184 * @param func The node constructor function
1185 * @return The constructed ia32 node.
1187 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
1188 match_flags_t flags)
1191 ir_node *block, *new_block, *new_op, *new_node;
1193 assert(flags == 0 || flags == match_mode_neutral);
1194 if (flags & match_mode_neutral) {
1195 op = ia32_skip_downconv(op);
1198 new_op = be_transform_node(op);
1199 dbgi = get_irn_dbg_info(node);
1200 block = get_nodes_block(node);
1201 new_block = be_transform_node(block);
1202 new_node = func(dbgi, new_block, new_op);
1204 SET_IA32_ORIG_NODE(new_node, node);
1209 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
1210 ia32_address_t *addr)
1220 base = be_transform_node(base);
1227 idx = be_transform_node(idx);
1230 /* segment overrides are ineffective for Leas :-( so we have to patch
1232 if (addr->tls_segment) {
1233 ir_node *tls_base = new_bd_ia32_LdTls(NULL, block);
1234 assert(addr->symconst_ent != NULL);
1235 if (base == noreg_GP)
1238 base = new_bd_ia32_Lea(dbgi, block, tls_base, base);
1239 addr->tls_segment = false;
1242 res = new_bd_ia32_Lea(dbgi, block, base, idx);
1243 set_address(res, addr);
1249 * Returns non-zero if a given address mode has a symbolic or
1250 * numerical offset != 0.
1252 static int am_has_immediates(const ia32_address_t *addr)
1254 return addr->offset != 0 || addr->symconst_ent != NULL
1255 || addr->frame_entity || addr->use_frame;
1258 typedef ir_node* (*new_shiftd_func)(dbg_info *dbgi, ir_node *block,
1259 ir_node *high, ir_node *low,
1263 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
1264 * op1 - target to be shifted
1265 * op2 - contains bits to be shifted into target
1267 * Only op3 can be an immediate.
1269 static ir_node *gen_64bit_shifts(dbg_info *dbgi, ir_node *block,
1270 ir_node *high, ir_node *low, ir_node *count,
1271 new_shiftd_func func)
1273 ir_node *new_block = be_transform_node(block);
1274 ir_node *new_high = be_transform_node(high);
1275 ir_node *new_low = be_transform_node(low);
1279 /* the shift amount can be any mode that is bigger than 5 bits, since all
1280 * other bits are ignored anyway */
1281 while (is_Conv(count) &&
1282 get_irn_n_edges(count) == 1 &&
1283 mode_is_int(get_irn_mode(count))) {
1284 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
1285 count = get_Conv_op(count);
1287 new_count = create_immediate_or_transform(count, 0);
1289 new_node = func(dbgi, new_block, new_high, new_low, new_count);
1294 * test wether 2 values result in 'x' and '32-x' when interpreted as a shift
1297 static bool is_complementary_shifts(ir_node *value1, ir_node *value2)
1299 if (is_Const(value1) && is_Const(value2)) {
1300 ir_tarval *tv1 = get_Const_tarval(value1);
1301 ir_tarval *tv2 = get_Const_tarval(value2);
1302 if (tarval_is_long(tv1) && tarval_is_long(tv2)) {
1303 long v1 = get_tarval_long(tv1);
1304 long v2 = get_tarval_long(tv2);
1305 return v1 <= v2 && v2 == 32-v1;
1311 static ir_node *match_64bit_shift(ir_node *node)
1313 ir_node *op1 = get_binop_left(node);
1314 ir_node *op2 = get_binop_right(node);
1315 assert(is_Or(node) || is_Add(node));
1323 /* match ShlD operation */
1324 if (is_Shl(op1) && is_Shr(op2)) {
1325 ir_node *shl_right = get_Shl_right(op1);
1326 ir_node *shl_left = get_Shl_left(op1);
1327 ir_node *shr_right = get_Shr_right(op2);
1328 ir_node *shr_left = get_Shr_left(op2);
1329 /* constant ShlD operation */
1330 if (is_complementary_shifts(shl_right, shr_right)) {
1331 dbg_info *dbgi = get_irn_dbg_info(node);
1332 ir_node *block = get_nodes_block(node);
1333 return gen_64bit_shifts(dbgi, block, shl_left, shr_left, shl_right,
1336 /* constant ShrD operation */
1337 if (is_complementary_shifts(shr_right, shl_right)) {
1338 dbg_info *dbgi = get_irn_dbg_info(node);
1339 ir_node *block = get_nodes_block(node);
1340 return gen_64bit_shifts(dbgi, block, shr_left, shl_left, shr_right,
1343 /* lower_dw produces the following for ShlD:
1344 * Or(Shr(Shr(high,1),Not(c)),Shl(low,c)) */
1345 if (is_Shr(shr_left) && is_Not(shr_right)
1346 && is_Const_1(get_Shr_right(shr_left))
1347 && get_Not_op(shr_right) == shl_right) {
1348 dbg_info *dbgi = get_irn_dbg_info(node);
1349 ir_node *block = get_nodes_block(node);
1350 ir_node *val_h = get_Shr_left(shr_left);
1351 return gen_64bit_shifts(dbgi, block, shl_left, val_h, shl_right,
1354 /* lower_dw produces the following for ShrD:
1355 * Or(Shl(Shl(high,1),Not(c)), Shr(low,c)) */
1356 if (is_Shl(shl_left) && is_Not(shl_right)
1357 && is_Const_1(get_Shl_right(shl_left))
1358 && get_Not_op(shl_right) == shr_right) {
1359 dbg_info *dbgi = get_irn_dbg_info(node);
1360 ir_node *block = get_nodes_block(node);
1361 ir_node *val_h = get_Shl_left(shl_left);
1362 return gen_64bit_shifts(dbgi, block, shr_left, val_h, shr_right,
1371 * Creates an ia32 Add.
1373 * @return the created ia32 Add node
1375 static ir_node *gen_Add(ir_node *node)
1377 ir_mode *mode = get_irn_mode(node);
1378 ir_node *op1 = get_Add_left(node);
1379 ir_node *op2 = get_Add_right(node);
1381 ir_node *block, *new_block, *new_node, *add_immediate_op;
1382 ia32_address_t addr;
1383 ia32_address_mode_t am;
1385 new_node = match_64bit_shift(node);
1386 if (new_node != NULL)
1389 if (mode_is_float(mode)) {
1390 if (ia32_cg_config.use_sse2)
1391 return gen_binop(node, op1, op2, new_bd_ia32_xAdd,
1392 match_commutative | match_am);
1394 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfadd);
1397 ia32_mark_non_am(node);
1401 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1402 * 1. Add with immediate -> Lea
1403 * 2. Add with possible source address mode -> Add
1404 * 3. Otherwise -> Lea
1406 memset(&addr, 0, sizeof(addr));
1407 ia32_create_address_mode(&addr, node, ia32_create_am_force);
1408 add_immediate_op = NULL;
1410 dbgi = get_irn_dbg_info(node);
1411 block = get_nodes_block(node);
1412 new_block = be_transform_node(block);
1415 if (addr.base == NULL && addr.index == NULL) {
1416 new_node = new_bd_ia32_Const(dbgi, new_block, addr.symconst_ent,
1417 addr.symconst_sign, 0, addr.offset);
1418 SET_IA32_ORIG_NODE(new_node, node);
1421 /* add with immediate? */
1422 if (addr.index == NULL) {
1423 add_immediate_op = addr.base;
1424 } else if (addr.base == NULL && addr.scale == 0) {
1425 add_immediate_op = addr.index;
1428 if (add_immediate_op != NULL) {
1429 if (!am_has_immediates(&addr)) {
1430 #ifdef DEBUG_libfirm
1431 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1434 return be_transform_node(add_immediate_op);
1437 new_node = create_lea_from_address(dbgi, new_block, &addr);
1438 SET_IA32_ORIG_NODE(new_node, node);
1442 /* test if we can use source address mode */
1443 match_arguments(&am, block, op1, op2, NULL, match_commutative
1444 | match_mode_neutral | match_am | match_immediate | match_try_am);
1446 /* construct an Add with source address mode */
1447 if (am.op_type == ia32_AddrModeS) {
1448 ia32_address_t *am_addr = &am.addr;
1449 new_node = new_bd_ia32_Add(dbgi, new_block, am_addr->base,
1450 am_addr->index, am_addr->mem, am.new_op1,
1452 set_am_attributes(new_node, &am);
1453 SET_IA32_ORIG_NODE(new_node, node);
1455 new_node = fix_mem_proj(new_node, &am);
1460 /* otherwise construct a lea */
1461 new_node = create_lea_from_address(dbgi, new_block, &addr);
1462 SET_IA32_ORIG_NODE(new_node, node);
1467 * Creates an ia32 Mul.
1469 * @return the created ia32 Mul node
1471 static ir_node *gen_Mul(ir_node *node)
1473 ir_node *op1 = get_Mul_left(node);
1474 ir_node *op2 = get_Mul_right(node);
1475 ir_mode *mode = get_irn_mode(node);
1477 if (mode_is_float(mode)) {
1478 if (ia32_cg_config.use_sse2)
1479 return gen_binop(node, op1, op2, new_bd_ia32_xMul,
1480 match_commutative | match_am);
1482 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfmul);
1484 return gen_binop(node, op1, op2, new_bd_ia32_IMul,
1485 match_commutative | match_am | match_mode_neutral |
1486 match_immediate | match_am_and_immediates);
1490 * Creates an ia32 Mulh.
1491 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1492 * this result while Mul returns the lower 32 bit.
1494 * @return the created ia32 Mulh node
1496 static ir_node *gen_Mulh(ir_node *node)
1498 dbg_info *dbgi = get_irn_dbg_info(node);
1499 ir_node *op1 = get_Mulh_left(node);
1500 ir_node *op2 = get_Mulh_right(node);
1501 ir_mode *mode = get_irn_mode(node);
1503 ir_node *proj_res_high;
1505 if (get_mode_size_bits(mode) != 32) {
1506 panic("Mulh without 32bit size not supported in ia32 backend (%+F)", node);
1509 if (mode_is_signed(mode)) {
1510 new_node = gen_binop(node, op1, op2, new_bd_ia32_IMul1OP, match_commutative | match_am);
1511 proj_res_high = new_rd_Proj(dbgi, new_node, mode_Iu, pn_ia32_IMul1OP_res_high);
1513 new_node = gen_binop(node, op1, op2, new_bd_ia32_Mul, match_commutative | match_am);
1514 proj_res_high = new_rd_Proj(dbgi, new_node, mode_Iu, pn_ia32_Mul_res_high);
1516 return proj_res_high;
1520 * Creates an ia32 And.
1522 * @return The created ia32 And node
1524 static ir_node *gen_And(ir_node *node)
1526 ir_node *op1 = get_And_left(node);
1527 ir_node *op2 = get_And_right(node);
1528 assert(! mode_is_float(get_irn_mode(node)));
1530 /* is it a zero extension? */
1531 if (is_Const(op2)) {
1532 ir_tarval *tv = get_Const_tarval(op2);
1533 long v = get_tarval_long(tv);
1535 if (v == 0xFF || v == 0xFFFF) {
1536 dbg_info *dbgi = get_irn_dbg_info(node);
1537 ir_node *block = get_nodes_block(node);
1544 assert(v == 0xFFFF);
1547 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1552 return gen_binop(node, op1, op2, new_bd_ia32_And,
1553 match_commutative | match_mode_neutral | match_am | match_immediate);
1557 * Creates an ia32 Or.
1559 * @return The created ia32 Or node
1561 static ir_node *gen_Or(ir_node *node)
1563 ir_node *op1 = get_Or_left(node);
1564 ir_node *op2 = get_Or_right(node);
1567 res = match_64bit_shift(node);
1571 assert (! mode_is_float(get_irn_mode(node)));
1572 return gen_binop(node, op1, op2, new_bd_ia32_Or, match_commutative
1573 | match_mode_neutral | match_am | match_immediate);
1579 * Creates an ia32 Eor.
1581 * @return The created ia32 Eor node
1583 static ir_node *gen_Eor(ir_node *node)
1585 ir_node *op1 = get_Eor_left(node);
1586 ir_node *op2 = get_Eor_right(node);
1588 assert(! mode_is_float(get_irn_mode(node)));
1589 return gen_binop(node, op1, op2, new_bd_ia32_Xor, match_commutative
1590 | match_mode_neutral | match_am | match_immediate);
1595 * Creates an ia32 Sub.
1597 * @return The created ia32 Sub node
1599 static ir_node *gen_Sub(ir_node *node)
1601 ir_node *op1 = get_Sub_left(node);
1602 ir_node *op2 = get_Sub_right(node);
1603 ir_mode *mode = get_irn_mode(node);
1605 if (mode_is_float(mode)) {
1606 if (ia32_cg_config.use_sse2)
1607 return gen_binop(node, op1, op2, new_bd_ia32_xSub, match_am);
1609 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfsub);
1612 if (is_Const(op2)) {
1613 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1617 return gen_binop(node, op1, op2, new_bd_ia32_Sub, match_mode_neutral
1618 | match_am | match_immediate);
1621 static ir_node *transform_AM_mem(ir_node *const block,
1622 ir_node *const src_val,
1623 ir_node *const src_mem,
1624 ir_node *const am_mem)
1626 if (is_NoMem(am_mem)) {
1627 return be_transform_node(src_mem);
1628 } else if (is_Proj(src_val) &&
1630 get_Proj_pred(src_val) == get_Proj_pred(src_mem)) {
1631 /* avoid memory loop */
1633 } else if (is_Proj(src_val) && is_Sync(src_mem)) {
1634 ir_node *const ptr_pred = get_Proj_pred(src_val);
1635 int const arity = get_Sync_n_preds(src_mem);
1640 NEW_ARR_A(ir_node*, ins, arity + 1);
1642 /* NOTE: This sometimes produces dead-code because the old sync in
1643 * src_mem might not be used anymore, we should detect this case
1644 * and kill the sync... */
1645 for (i = arity - 1; i >= 0; --i) {
1646 ir_node *const pred = get_Sync_pred(src_mem, i);
1648 /* avoid memory loop */
1649 if (is_Proj(pred) && get_Proj_pred(pred) == ptr_pred)
1652 ins[n++] = be_transform_node(pred);
1655 if (n==1 && ins[0] == am_mem) {
1657 /* creating a new Sync and relying on CSE may fail,
1658 * if am_mem is a ProjM, which does not yet verify. */
1662 return new_r_Sync(block, n, ins);
1666 ins[0] = be_transform_node(src_mem);
1668 return new_r_Sync(block, 2, ins);
1673 * Create a 32bit to 64bit signed extension.
1675 * @param dbgi debug info
1676 * @param block the block where node nodes should be placed
1677 * @param val the value to extend
1678 * @param orig the original node
1680 static ir_node *create_sex_32_64(dbg_info *dbgi, ir_node *block,
1681 ir_node *val, const ir_node *orig)
1686 if (ia32_cg_config.use_short_sex_eax) {
1687 ir_node *pval = new_bd_ia32_ProduceVal(dbgi, block);
1688 res = new_bd_ia32_Cltd(dbgi, block, val, pval);
1690 ir_node *imm31 = ia32_create_Immediate(NULL, 0, 31);
1691 res = new_bd_ia32_Sar(dbgi, block, val, imm31);
1693 SET_IA32_ORIG_NODE(res, orig);
1698 * Generates an ia32 Div with additional infrastructure for the
1699 * register allocator if needed.
1701 static ir_node *create_Div(ir_node *node)
1703 dbg_info *dbgi = get_irn_dbg_info(node);
1704 ir_node *block = get_nodes_block(node);
1705 ir_node *new_block = be_transform_node(block);
1706 int throws_exception = ir_throws_exception(node);
1713 ir_node *sign_extension;
1714 ia32_address_mode_t am;
1715 ia32_address_t *addr = &am.addr;
1717 /* the upper bits have random contents for smaller modes */
1718 switch (get_irn_opcode(node)) {
1720 op1 = get_Div_left(node);
1721 op2 = get_Div_right(node);
1722 mem = get_Div_mem(node);
1723 mode = get_Div_resmode(node);
1726 op1 = get_Mod_left(node);
1727 op2 = get_Mod_right(node);
1728 mem = get_Mod_mem(node);
1729 mode = get_Mod_resmode(node);
1732 panic("invalid divmod node %+F", node);
1735 match_arguments(&am, block, op1, op2, NULL, match_am | match_upconv);
1737 /* Beware: We don't need a Sync, if the memory predecessor of the Div node
1738 is the memory of the consumed address. We can have only the second op as address
1739 in Div nodes, so check only op2. */
1740 new_mem = transform_AM_mem(block, op2, mem, addr->mem);
1742 if (mode_is_signed(mode)) {
1743 sign_extension = create_sex_32_64(dbgi, new_block, am.new_op1, node);
1744 new_node = new_bd_ia32_IDiv(dbgi, new_block, addr->base,
1745 addr->index, new_mem, am.new_op2, am.new_op1, sign_extension);
1747 sign_extension = new_bd_ia32_Const(dbgi, new_block, NULL, 0, 0, 0);
1749 new_node = new_bd_ia32_Div(dbgi, new_block, addr->base,
1750 addr->index, new_mem, am.new_op2,
1751 am.new_op1, sign_extension);
1753 ir_set_throws_exception(new_node, throws_exception);
1755 set_irn_pinned(new_node, get_irn_pinned(node));
1757 set_am_attributes(new_node, &am);
1758 SET_IA32_ORIG_NODE(new_node, node);
1760 new_node = fix_mem_proj(new_node, &am);
1766 * Generates an ia32 Mod.
1768 static ir_node *gen_Mod(ir_node *node)
1770 return create_Div(node);
1774 * Generates an ia32 Div.
1776 static ir_node *gen_Div(ir_node *node)
1778 ir_mode *mode = get_Div_resmode(node);
1779 if (mode_is_float(mode)) {
1780 ir_node *op1 = get_Div_left(node);
1781 ir_node *op2 = get_Div_right(node);
1783 if (ia32_cg_config.use_sse2) {
1784 return gen_binop(node, op1, op2, new_bd_ia32_xDiv, match_am);
1786 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfdiv);
1790 return create_Div(node);
1794 * Creates an ia32 Shl.
1796 * @return The created ia32 Shl node
1798 static ir_node *gen_Shl(ir_node *node)
1800 ir_node *left = get_Shl_left(node);
1801 ir_node *right = get_Shl_right(node);
1803 return gen_shift_binop(node, left, right, new_bd_ia32_Shl,
1804 match_mode_neutral | match_immediate);
1808 * Creates an ia32 Shr.
1810 * @return The created ia32 Shr node
1812 static ir_node *gen_Shr(ir_node *node)
1814 ir_node *left = get_Shr_left(node);
1815 ir_node *right = get_Shr_right(node);
1817 return gen_shift_binop(node, left, right, new_bd_ia32_Shr,
1818 match_immediate | match_zero_ext);
1822 * Creates an ia32 Sar.
1824 * @return The created ia32 Shrs node
1826 static ir_node *gen_Shrs(ir_node *node)
1828 ir_node *left = get_Shrs_left(node);
1829 ir_node *right = get_Shrs_right(node);
1831 if (is_Const(right)) {
1832 ir_tarval *tv = get_Const_tarval(right);
1833 long val = get_tarval_long(tv);
1835 /* this is a sign extension */
1836 dbg_info *dbgi = get_irn_dbg_info(node);
1837 ir_node *block = be_transform_node(get_nodes_block(node));
1838 ir_node *new_op = be_transform_node(left);
1840 return create_sex_32_64(dbgi, block, new_op, node);
1844 /* 8 or 16 bit sign extension? */
1845 if (is_Const(right) && is_Shl(left)) {
1846 ir_node *shl_left = get_Shl_left(left);
1847 ir_node *shl_right = get_Shl_right(left);
1848 if (is_Const(shl_right)) {
1849 ir_tarval *tv1 = get_Const_tarval(right);
1850 ir_tarval *tv2 = get_Const_tarval(shl_right);
1851 if (tv1 == tv2 && tarval_is_long(tv1)) {
1852 long val = get_tarval_long(tv1);
1853 if (val == 16 || val == 24) {
1854 dbg_info *dbgi = get_irn_dbg_info(node);
1855 ir_node *block = get_nodes_block(node);
1865 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1874 return gen_shift_binop(node, left, right, new_bd_ia32_Sar,
1875 match_immediate | match_upconv);
1881 * Creates an ia32 Rol.
1883 * @param op1 The first operator
1884 * @param op2 The second operator
1885 * @return The created ia32 RotL node
1887 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
1889 return gen_shift_binop(node, op1, op2, new_bd_ia32_Rol, match_immediate);
1895 * Creates an ia32 Ror.
1896 * NOTE: There is no RotR with immediate because this would always be a RotL
1897 * "imm-mode_size_bits" which can be pre-calculated.
1899 * @param op1 The first operator
1900 * @param op2 The second operator
1901 * @return The created ia32 RotR node
1903 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
1905 return gen_shift_binop(node, op1, op2, new_bd_ia32_Ror, match_immediate);
1911 * Creates an ia32 RotR or RotL (depending on the found pattern).
1913 * @return The created ia32 RotL or RotR node
1915 static ir_node *gen_Rotl(ir_node *node)
1917 ir_node *op1 = get_Rotl_left(node);
1918 ir_node *op2 = get_Rotl_right(node);
1920 if (is_Minus(op2)) {
1921 return gen_Ror(node, op1, get_Minus_op(op2));
1924 return gen_Rol(node, op1, op2);
1930 * Transforms a Minus node.
1932 * @return The created ia32 Minus node
1934 static ir_node *gen_Minus(ir_node *node)
1936 ir_node *op = get_Minus_op(node);
1937 ir_node *block = be_transform_node(get_nodes_block(node));
1938 dbg_info *dbgi = get_irn_dbg_info(node);
1939 ir_mode *mode = get_irn_mode(node);
1944 if (mode_is_float(mode)) {
1945 ir_node *new_op = be_transform_node(op);
1946 if (ia32_cg_config.use_sse2) {
1947 /* TODO: non-optimal... if we have many xXors, then we should
1948 * rather create a load for the const and use that instead of
1949 * several AM nodes... */
1950 ir_node *noreg_xmm = ia32_new_NoReg_xmm(current_ir_graph);
1952 new_node = new_bd_ia32_xXor(dbgi, block, get_symconst_base(),
1953 noreg_GP, nomem, new_op, noreg_xmm);
1955 size = get_mode_size_bits(mode);
1956 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1958 set_ia32_am_sc(new_node, ent);
1959 set_ia32_op_type(new_node, ia32_AddrModeS);
1960 set_ia32_ls_mode(new_node, mode);
1962 check_x87_floatmode(mode);
1963 new_node = new_bd_ia32_vfchs(dbgi, block, new_op);
1966 new_node = gen_unop(node, op, new_bd_ia32_Neg, match_mode_neutral);
1969 SET_IA32_ORIG_NODE(new_node, node);
1975 * Transforms a Not node.
1977 * @return The created ia32 Not node
1979 static ir_node *gen_Not(ir_node *node)
1981 ir_node *op = get_Not_op(node);
1983 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1984 assert (! mode_is_float(get_irn_mode(node)));
1986 return gen_unop(node, op, new_bd_ia32_Not, match_mode_neutral);
1989 static ir_node *create_float_abs(dbg_info *dbgi, ir_node *block, ir_node *op,
1990 bool negate, ir_node *node)
1992 ir_node *new_block = be_transform_node(block);
1993 ir_mode *mode = get_irn_mode(op);
1994 ir_node *new_op = be_transform_node(op);
1999 assert(mode_is_float(mode));
2001 if (ia32_cg_config.use_sse2) {
2002 ir_node *noreg_fp = ia32_new_NoReg_xmm(current_ir_graph);
2003 new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(),
2004 noreg_GP, nomem, new_op, noreg_fp);
2006 size = get_mode_size_bits(mode);
2007 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
2009 set_ia32_am_sc(new_node, ent);
2011 SET_IA32_ORIG_NODE(new_node, node);
2013 set_ia32_op_type(new_node, ia32_AddrModeS);
2014 set_ia32_ls_mode(new_node, mode);
2016 /* TODO, implement -Abs case */
2019 check_x87_floatmode(mode);
2020 new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op);
2021 SET_IA32_ORIG_NODE(new_node, node);
2023 new_node = new_bd_ia32_vfchs(dbgi, new_block, new_node);
2024 SET_IA32_ORIG_NODE(new_node, node);
2032 * Create a bt instruction for x & (1 << n) and place it into the block of cmp.
2034 static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n)
2036 dbg_info *dbgi = get_irn_dbg_info(cmp);
2037 ir_node *block = get_nodes_block(cmp);
2038 ir_node *new_block = be_transform_node(block);
2039 ir_node *op1 = be_transform_node(x);
2040 ir_node *op2 = be_transform_node(n);
2042 return new_bd_ia32_Bt(dbgi, new_block, op1, op2);
2045 static ia32_condition_code_t relation_to_condition_code(ir_relation relation,
2047 bool overflow_possible)
2049 if (mode_is_float(mode)) {
2051 case ir_relation_equal: return ia32_cc_float_equal;
2052 case ir_relation_less: return ia32_cc_float_below;
2053 case ir_relation_less_equal: return ia32_cc_float_below_equal;
2054 case ir_relation_greater: return ia32_cc_float_above;
2055 case ir_relation_greater_equal: return ia32_cc_float_above_equal;
2056 case ir_relation_less_greater: return ia32_cc_not_equal;
2057 case ir_relation_less_equal_greater: return ia32_cc_not_parity;
2058 case ir_relation_unordered: return ia32_cc_parity;
2059 case ir_relation_unordered_equal: return ia32_cc_equal;
2060 case ir_relation_unordered_less: return ia32_cc_float_unordered_below;
2061 case ir_relation_unordered_less_equal:
2062 return ia32_cc_float_unordered_below_equal;
2063 case ir_relation_unordered_greater:
2064 return ia32_cc_float_unordered_above;
2065 case ir_relation_unordered_greater_equal:
2066 return ia32_cc_float_unordered_above_equal;
2067 case ir_relation_unordered_less_greater:
2068 return ia32_cc_float_not_equal;
2069 case ir_relation_false:
2070 case ir_relation_true:
2071 /* should we introduce a jump always/jump never? */
2074 panic("Unexpected float pnc");
2075 } else if (mode_is_signed(mode)) {
2077 case ir_relation_unordered_equal:
2078 case ir_relation_equal: return ia32_cc_equal;
2079 case ir_relation_unordered_less:
2080 case ir_relation_less:
2081 return overflow_possible ? ia32_cc_less : ia32_cc_sign;
2082 case ir_relation_unordered_less_equal:
2083 case ir_relation_less_equal: return ia32_cc_less_equal;
2084 case ir_relation_unordered_greater:
2085 case ir_relation_greater: return ia32_cc_greater;
2086 case ir_relation_unordered_greater_equal:
2087 case ir_relation_greater_equal:
2088 return overflow_possible ? ia32_cc_greater_equal : ia32_cc_not_sign;
2089 case ir_relation_unordered_less_greater:
2090 case ir_relation_less_greater: return ia32_cc_not_equal;
2091 case ir_relation_less_equal_greater:
2092 case ir_relation_unordered:
2093 case ir_relation_false:
2094 case ir_relation_true:
2095 /* introduce jump always/jump never? */
2098 panic("Unexpected pnc");
2101 case ir_relation_unordered_equal:
2102 case ir_relation_equal: return ia32_cc_equal;
2103 case ir_relation_unordered_less:
2104 case ir_relation_less: return ia32_cc_below;
2105 case ir_relation_unordered_less_equal:
2106 case ir_relation_less_equal: return ia32_cc_below_equal;
2107 case ir_relation_unordered_greater:
2108 case ir_relation_greater: return ia32_cc_above;
2109 case ir_relation_unordered_greater_equal:
2110 case ir_relation_greater_equal: return ia32_cc_above_equal;
2111 case ir_relation_unordered_less_greater:
2112 case ir_relation_less_greater: return ia32_cc_not_equal;
2113 case ir_relation_less_equal_greater:
2114 case ir_relation_unordered:
2115 case ir_relation_false:
2116 case ir_relation_true:
2117 /* introduce jump always/jump never? */
2120 panic("Unexpected pnc");
2124 static ir_node *get_flags_node(ir_node *cmp, ia32_condition_code_t *cc_out)
2126 /* must have a Cmp as input */
2127 ir_relation relation = get_Cmp_relation(cmp);
2128 ir_node *l = get_Cmp_left(cmp);
2129 ir_node *r = get_Cmp_right(cmp);
2130 ir_mode *mode = get_irn_mode(l);
2131 bool overflow_possible;
2134 /* check for bit-test */
2135 if (ia32_cg_config.use_bt
2136 && (relation == ir_relation_equal
2137 || (mode_is_signed(mode) && relation == ir_relation_less_greater)
2138 || (!mode_is_signed(mode) && ((relation & ir_relation_greater_equal) == ir_relation_greater)))
2140 ir_node *la = get_And_left(l);
2141 ir_node *ra = get_And_right(l);
2148 ir_node *c = get_Shl_left(la);
2149 if (is_Const_1(c) && is_Const_0(r)) {
2150 /* (1 << n) & ra) */
2151 ir_node *n = get_Shl_right(la);
2152 flags = gen_bt(cmp, ra, n);
2153 /* the bit is copied into the CF flag */
2154 if (relation & ir_relation_equal)
2155 *cc_out = ia32_cc_above_equal; /* test for CF=0 */
2157 *cc_out = ia32_cc_below; /* test for CF=1 */
2163 /* the middle-end tries to eliminate impossible relations, so a ptr <> 0
2164 * test becomes ptr > 0. But for x86 an equal comparison is preferable to
2165 * a >0 (we can sometimes eliminate the cmp in favor of flags produced by
2166 * a predecessor node). So add the < bit.
2167 * (Note that we do not want to produce <=> (which can happen for
2168 * unoptimized code), because no x86 flag can represent that */
2169 if (!(relation & ir_relation_equal) && relation & ir_relation_less_greater)
2170 relation |= get_negated_relation(ir_get_possible_cmp_relations(l, r)) & ir_relation_less_greater;
2172 overflow_possible = true;
2173 if (is_Const(r) && is_Const_null(r))
2174 overflow_possible = false;
2176 /* just do a normal transformation of the Cmp */
2177 *cc_out = relation_to_condition_code(relation, mode, overflow_possible);
2178 flags = be_transform_node(cmp);
2183 * Transforms a Load.
2185 * @return the created ia32 Load node
2187 static ir_node *gen_Load(ir_node *node)
2189 ir_node *old_block = get_nodes_block(node);
2190 ir_node *block = be_transform_node(old_block);
2191 ir_node *ptr = get_Load_ptr(node);
2192 ir_node *mem = get_Load_mem(node);
2193 ir_node *new_mem = be_transform_node(mem);
2194 dbg_info *dbgi = get_irn_dbg_info(node);
2195 ir_mode *mode = get_Load_mode(node);
2196 int throws_exception = ir_throws_exception(node);
2200 ia32_address_t addr;
2202 /* construct load address */
2203 memset(&addr, 0, sizeof(addr));
2204 ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
2211 base = be_transform_node(base);
2217 idx = be_transform_node(idx);
2220 if (mode_is_float(mode)) {
2221 if (ia32_cg_config.use_sse2) {
2222 new_node = new_bd_ia32_xLoad(dbgi, block, base, idx, new_mem,
2225 new_node = new_bd_ia32_vfld(dbgi, block, base, idx, new_mem,
2229 assert(mode != mode_b);
2231 /* create a conv node with address mode for smaller modes */
2232 if (get_mode_size_bits(mode) < 32) {
2233 new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, idx,
2234 new_mem, noreg_GP, mode);
2236 new_node = new_bd_ia32_Load(dbgi, block, base, idx, new_mem);
2239 ir_set_throws_exception(new_node, throws_exception);
2241 set_irn_pinned(new_node, get_irn_pinned(node));
2242 set_ia32_op_type(new_node, ia32_AddrModeS);
2243 set_ia32_ls_mode(new_node, mode);
2244 set_address(new_node, &addr);
2246 if (get_irn_pinned(node) == op_pin_state_floats) {
2247 assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
2248 && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
2249 && (int)pn_ia32_Load_res == (int)pn_ia32_res);
2250 arch_add_irn_flags(new_node, arch_irn_flags_rematerializable);
2253 SET_IA32_ORIG_NODE(new_node, node);
2258 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
2259 ir_node *ptr, ir_node *other)
2266 /* we only use address mode if we're the only user of the load */
2267 if (get_irn_n_edges(node) > 1)
2270 load = get_Proj_pred(node);
2273 if (get_nodes_block(load) != block)
2276 /* store should have the same pointer as the load */
2277 if (get_Load_ptr(load) != ptr)
2280 /* don't do AM if other node inputs depend on the load (via mem-proj) */
2281 if (other != NULL &&
2282 get_nodes_block(other) == block &&
2283 heights_reachable_in_block(ia32_heights, other, load)) {
2287 if (ia32_prevents_AM(block, load, mem))
2289 /* Store should be attached to the load via mem */
2290 assert(heights_reachable_in_block(ia32_heights, mem, load));
2295 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
2296 ir_node *mem, ir_node *ptr, ir_mode *mode,
2297 construct_binop_dest_func *func,
2298 construct_binop_dest_func *func8bit,
2299 match_flags_t flags)
2301 ir_node *src_block = get_nodes_block(node);
2309 ia32_address_mode_t am;
2310 ia32_address_t *addr = &am.addr;
2311 memset(&am, 0, sizeof(am));
2313 assert(flags & match_immediate); /* there is no destam node without... */
2314 commutative = (flags & match_commutative) != 0;
2316 if (use_dest_am(src_block, op1, mem, ptr, op2)) {
2317 build_address(&am, op1, ia32_create_am_double_use);
2318 new_op = create_immediate_or_transform(op2, 0);
2319 } else if (commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
2320 build_address(&am, op2, ia32_create_am_double_use);
2321 new_op = create_immediate_or_transform(op1, 0);
2326 if (addr->base == NULL)
2327 addr->base = noreg_GP;
2328 if (addr->index == NULL)
2329 addr->index = noreg_GP;
2330 if (addr->mem == NULL)
2333 dbgi = get_irn_dbg_info(node);
2334 block = be_transform_node(src_block);
2335 new_mem = transform_AM_mem(block, am.am_node, mem, addr->mem);
2337 if (get_mode_size_bits(mode) == 8) {
2338 new_node = func8bit(dbgi, block, addr->base, addr->index, new_mem, new_op);
2340 new_node = func(dbgi, block, addr->base, addr->index, new_mem, new_op);
2342 set_address(new_node, addr);
2343 set_ia32_op_type(new_node, ia32_AddrModeD);
2344 set_ia32_ls_mode(new_node, mode);
2345 SET_IA32_ORIG_NODE(new_node, node);
2347 be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
2348 mem_proj = be_transform_node(am.mem_proj);
2349 be_set_transformed_node(am.mem_proj, new_node);
2350 be_set_transformed_node(mem_proj, new_node);
2355 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
2356 ir_node *ptr, ir_mode *mode,
2357 construct_unop_dest_func *func)
2359 ir_node *src_block = get_nodes_block(node);
2365 ia32_address_mode_t am;
2366 ia32_address_t *addr = &am.addr;
2368 if (!use_dest_am(src_block, op, mem, ptr, NULL))
2371 memset(&am, 0, sizeof(am));
2372 build_address(&am, op, ia32_create_am_double_use);
2374 dbgi = get_irn_dbg_info(node);
2375 block = be_transform_node(src_block);
2376 new_mem = transform_AM_mem(block, am.am_node, mem, addr->mem);
2377 new_node = func(dbgi, block, addr->base, addr->index, new_mem);
2378 set_address(new_node, addr);
2379 set_ia32_op_type(new_node, ia32_AddrModeD);
2380 set_ia32_ls_mode(new_node, mode);
2381 SET_IA32_ORIG_NODE(new_node, node);
2383 be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
2384 mem_proj = be_transform_node(am.mem_proj);
2385 be_set_transformed_node(am.mem_proj, new_node);
2386 be_set_transformed_node(mem_proj, new_node);
2391 static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem)
2393 ir_mode *mode = get_irn_mode(node);
2394 ir_node *mux_true = get_Mux_true(node);
2395 ir_node *mux_false = get_Mux_false(node);
2403 ia32_condition_code_t cc;
2404 ia32_address_t addr;
2406 if (get_mode_size_bits(mode) != 8)
2409 if (is_Const_1(mux_true) && is_Const_0(mux_false)) {
2411 } else if (is_Const_0(mux_true) && is_Const_1(mux_false)) {
2417 cond = get_Mux_sel(node);
2418 flags = get_flags_node(cond, &cc);
2419 /* we can't handle the float special cases with SetM */
2420 if (cc & ia32_cc_additional_float_cases)
2423 cc = ia32_negate_condition_code(cc);
2425 build_address_ptr(&addr, ptr, mem);
2427 dbgi = get_irn_dbg_info(node);
2428 block = get_nodes_block(node);
2429 new_block = be_transform_node(block);
2430 new_node = new_bd_ia32_SetccMem(dbgi, new_block, addr.base,
2431 addr.index, addr.mem, flags, cc);
2432 set_address(new_node, &addr);
2433 set_ia32_op_type(new_node, ia32_AddrModeD);
2434 set_ia32_ls_mode(new_node, mode);
2435 SET_IA32_ORIG_NODE(new_node, node);
2440 static ir_node *try_create_dest_am(ir_node *node)
2442 ir_node *val = get_Store_value(node);
2443 ir_node *mem = get_Store_mem(node);
2444 ir_node *ptr = get_Store_ptr(node);
2445 ir_mode *mode = get_irn_mode(val);
2446 unsigned bits = get_mode_size_bits(mode);
2451 /* handle only GP modes for now... */
2452 if (!ia32_mode_needs_gp_reg(mode))
2456 /* store must be the only user of the val node */
2457 if (get_irn_n_edges(val) > 1)
2459 /* skip pointless convs */
2461 ir_node *conv_op = get_Conv_op(val);
2462 ir_mode *pred_mode = get_irn_mode(conv_op);
2463 if (!ia32_mode_needs_gp_reg(pred_mode))
2465 if (pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
2473 /* value must be in the same block */
2474 if (get_nodes_block(node) != get_nodes_block(val))
2477 switch (get_irn_opcode(val)) {
2479 op1 = get_Add_left(val);
2480 op2 = get_Add_right(val);
2481 if (ia32_cg_config.use_incdec) {
2482 if (is_Const_1(op2)) {
2483 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_IncMem);
2485 } else if (is_Const_Minus_1(op2)) {
2486 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_DecMem);
2490 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2491 new_bd_ia32_AddMem, new_bd_ia32_AddMem8Bit,
2492 match_commutative | match_immediate);
2495 op1 = get_Sub_left(val);
2496 op2 = get_Sub_right(val);
2497 if (is_Const(op2)) {
2498 ir_fprintf(stderr, "Optimisation warning: not-normalized sub ,C found\n");
2500 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2501 new_bd_ia32_SubMem, new_bd_ia32_SubMem8Bit,
2505 op1 = get_And_left(val);
2506 op2 = get_And_right(val);
2507 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2508 new_bd_ia32_AndMem, new_bd_ia32_AndMem8Bit,
2509 match_commutative | match_immediate);
2512 op1 = get_Or_left(val);
2513 op2 = get_Or_right(val);
2514 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2515 new_bd_ia32_OrMem, new_bd_ia32_OrMem8Bit,
2516 match_commutative | match_immediate);
2519 op1 = get_Eor_left(val);
2520 op2 = get_Eor_right(val);
2521 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2522 new_bd_ia32_XorMem, new_bd_ia32_XorMem8Bit,
2523 match_commutative | match_immediate);
2526 op1 = get_Shl_left(val);
2527 op2 = get_Shl_right(val);
2528 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2529 new_bd_ia32_ShlMem, new_bd_ia32_ShlMem,
2533 op1 = get_Shr_left(val);
2534 op2 = get_Shr_right(val);
2535 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2536 new_bd_ia32_ShrMem, new_bd_ia32_ShrMem,
2540 op1 = get_Shrs_left(val);
2541 op2 = get_Shrs_right(val);
2542 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2543 new_bd_ia32_SarMem, new_bd_ia32_SarMem,
2547 op1 = get_Rotl_left(val);
2548 op2 = get_Rotl_right(val);
2549 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2550 new_bd_ia32_RolMem, new_bd_ia32_RolMem,
2553 /* TODO: match ROR patterns... */
2555 new_node = try_create_SetMem(val, ptr, mem);
2559 op1 = get_Minus_op(val);
2560 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NegMem);
2563 /* should be lowered already */
2564 assert(mode != mode_b);
2565 op1 = get_Not_op(val);
2566 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NotMem);
2572 if (new_node != NULL) {
2573 if (get_irn_pinned(new_node) != op_pin_state_pinned &&
2574 get_irn_pinned(node) == op_pin_state_pinned) {
2575 set_irn_pinned(new_node, op_pin_state_pinned);
2582 static bool possible_int_mode_for_fp(ir_mode *mode)
2586 if (!mode_is_signed(mode))
2588 size = get_mode_size_bits(mode);
2589 if (size != 16 && size != 32)
2594 static int is_float_to_int_conv(const ir_node *node)
2596 ir_mode *mode = get_irn_mode(node);
2600 if (!possible_int_mode_for_fp(mode))
2605 conv_op = get_Conv_op(node);
2606 conv_mode = get_irn_mode(conv_op);
2608 if (!mode_is_float(conv_mode))
2615 * Transform a Store(floatConst) into a sequence of
2618 * @return the created ia32 Store node
2620 static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns)
2622 ir_mode *mode = get_irn_mode(cns);
2623 unsigned size = get_mode_size_bytes(mode);
2624 ir_tarval *tv = get_Const_tarval(cns);
2625 ir_node *block = get_nodes_block(node);
2626 ir_node *new_block = be_transform_node(block);
2627 ir_node *ptr = get_Store_ptr(node);
2628 ir_node *mem = get_Store_mem(node);
2629 dbg_info *dbgi = get_irn_dbg_info(node);
2632 int throws_exception = ir_throws_exception(node);
2634 ia32_address_t addr;
2636 build_address_ptr(&addr, ptr, mem);
2643 val= get_tarval_sub_bits(tv, ofs) |
2644 (get_tarval_sub_bits(tv, ofs + 1) << 8) |
2645 (get_tarval_sub_bits(tv, ofs + 2) << 16) |
2646 (get_tarval_sub_bits(tv, ofs + 3) << 24);
2649 } else if (size >= 2) {
2650 val= get_tarval_sub_bits(tv, ofs) |
2651 (get_tarval_sub_bits(tv, ofs + 1) << 8);
2655 panic("invalid size of Store float to mem (%+F)", node);
2657 ir_node *imm = ia32_create_Immediate(NULL, 0, val);
2659 ir_node *new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
2660 addr.index, addr.mem, imm);
2661 ir_node *new_mem = new_r_Proj(new_node, mode_M, pn_ia32_Store_M);
2663 ir_set_throws_exception(new_node, throws_exception);
2664 set_irn_pinned(new_node, get_irn_pinned(node));
2665 set_ia32_op_type(new_node, ia32_AddrModeD);
2666 set_ia32_ls_mode(new_node, mode);
2667 set_address(new_node, &addr);
2668 SET_IA32_ORIG_NODE(new_node, node);
2675 addr.offset += delta;
2676 } while (size != 0);
2679 return new_rd_Sync(dbgi, new_block, i, ins);
2681 return get_Proj_pred(ins[0]);
2686 * Generate a vfist or vfisttp instruction.
2688 static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base,
2689 ir_node *index, ir_node *mem, ir_node *val)
2691 if (ia32_cg_config.use_fisttp) {
2692 /* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied
2693 if other users exists */
2694 ir_node *vfisttp = new_bd_ia32_vfisttp(dbgi, block, base, index, mem, val);
2695 ir_node *value = new_r_Proj(vfisttp, ia32_mode_E, pn_ia32_vfisttp_res);
2696 be_new_Keep(block, 1, &value);
2700 ir_node *trunc_mode = ia32_new_Fpu_truncate(current_ir_graph);
2703 ir_node *vfist = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode);
2709 * Transforms a general (no special case) Store.
2711 * @return the created ia32 Store node
2713 static ir_node *gen_general_Store(ir_node *node)
2715 ir_node *val = get_Store_value(node);
2716 ir_mode *mode = get_irn_mode(val);
2717 ir_node *block = get_nodes_block(node);
2718 ir_node *new_block = be_transform_node(block);
2719 ir_node *ptr = get_Store_ptr(node);
2720 ir_node *mem = get_Store_mem(node);
2721 dbg_info *dbgi = get_irn_dbg_info(node);
2722 int throws_exception = ir_throws_exception(node);
2725 ia32_address_t addr;
2727 /* check for destination address mode */
2728 new_node = try_create_dest_am(node);
2729 if (new_node != NULL)
2732 /* construct store address */
2733 memset(&addr, 0, sizeof(addr));
2734 ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
2736 if (addr.base == NULL) {
2737 addr.base = noreg_GP;
2739 addr.base = be_transform_node(addr.base);
2742 if (addr.index == NULL) {
2743 addr.index = noreg_GP;
2745 addr.index = be_transform_node(addr.index);
2747 addr.mem = be_transform_node(mem);
2749 if (mode_is_float(mode)) {
2750 new_val = be_transform_node(val);
2751 if (ia32_cg_config.use_sse2) {
2752 new_node = new_bd_ia32_xStore(dbgi, new_block, addr.base,
2753 addr.index, addr.mem, new_val);
2755 new_node = new_bd_ia32_vfst(dbgi, new_block, addr.base,
2756 addr.index, addr.mem, new_val, mode);
2758 } else if (!ia32_cg_config.use_sse2 && is_float_to_int_conv(val)) {
2759 val = get_Conv_op(val);
2760 new_val = be_transform_node(val);
2761 new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val);
2763 unsigned dest_bits = get_mode_size_bits(mode);
2764 while (is_downconv(val)
2765 && get_mode_size_bits(get_irn_mode(val)) >= dest_bits) {
2766 val = get_Conv_op(val);
2768 new_val = create_immediate_or_transform(val, 0);
2769 assert(mode != mode_b);
2771 if (dest_bits == 8) {
2772 new_node = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
2773 addr.index, addr.mem, new_val);
2775 new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
2776 addr.index, addr.mem, new_val);
2779 ir_set_throws_exception(new_node, throws_exception);
2781 set_irn_pinned(new_node, get_irn_pinned(node));
2782 set_ia32_op_type(new_node, ia32_AddrModeD);
2783 set_ia32_ls_mode(new_node, mode);
2785 set_address(new_node, &addr);
2786 SET_IA32_ORIG_NODE(new_node, node);
2792 * Transforms a Store.
2794 * @return the created ia32 Store node
2796 static ir_node *gen_Store(ir_node *node)
2798 ir_node *val = get_Store_value(node);
2799 ir_mode *mode = get_irn_mode(val);
2801 if (mode_is_float(mode) && is_Const(val)) {
2802 /* We can transform every floating const store
2803 into a sequence of integer stores.
2804 If the constant is already in a register,
2805 it would be better to use it, but we don't
2806 have this information here. */
2807 return gen_float_const_Store(node, val);
2809 return gen_general_Store(node);
2813 * Transforms a Switch.
2815 * @return the created ia32 SwitchJmp node
2817 static ir_node *gen_Switch(ir_node *node)
2819 dbg_info *dbgi = get_irn_dbg_info(node);
2820 ir_graph *irg = get_irn_irg(node);
2821 ir_node *block = be_transform_node(get_nodes_block(node));
2822 ir_node *sel = get_Switch_selector(node);
2823 ir_node *new_sel = be_transform_node(sel);
2824 ir_mode *sel_mode = get_irn_mode(sel);
2825 const ir_switch_table *table = get_Switch_table(node);
2826 unsigned n_outs = get_Switch_n_outs(node);
2830 assert(get_mode_size_bits(sel_mode) <= 32);
2831 assert(!mode_is_float(sel_mode));
2832 sel = ia32_skip_sameconv(sel);
2833 if (get_mode_size_bits(sel_mode) < 32)
2834 new_sel = transform_upconv(sel, node);
2836 entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type());
2837 set_entity_visibility(entity, ir_visibility_private);
2838 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
2840 table = ir_switch_table_duplicate(irg, table);
2842 new_node = new_bd_ia32_SwitchJmp(dbgi, block, noreg_GP, new_sel, n_outs, table);
2843 set_ia32_am_scale(new_node, 2);
2844 set_ia32_am_sc(new_node, entity);
2845 set_ia32_op_type(new_node, ia32_AddrModeS);
2846 set_ia32_ls_mode(new_node, mode_Iu);
2847 SET_IA32_ORIG_NODE(new_node, node);
2848 // FIXME This seems wrong. GCC uses PIC for switch on OS X.
2849 get_ia32_attr(new_node)->data.am_sc_no_pic_adjust = true;
2855 * Transform a Cond node.
2857 static ir_node *gen_Cond(ir_node *node)
2859 ir_node *block = get_nodes_block(node);
2860 ir_node *new_block = be_transform_node(block);
2861 dbg_info *dbgi = get_irn_dbg_info(node);
2862 ir_node *sel = get_Cond_selector(node);
2863 ir_node *flags = NULL;
2865 ia32_condition_code_t cc;
2867 /* we get flags from a Cmp */
2868 flags = get_flags_node(sel, &cc);
2870 new_node = new_bd_ia32_Jcc(dbgi, new_block, flags, cc);
2871 SET_IA32_ORIG_NODE(new_node, node);
2877 * Transform a be_Copy.
2879 static ir_node *gen_be_Copy(ir_node *node)
2881 ir_node *new_node = be_duplicate_node(node);
2882 ir_mode *mode = get_irn_mode(new_node);
2884 if (ia32_mode_needs_gp_reg(mode)) {
2885 set_irn_mode(new_node, mode_Iu);
2891 static ir_node *create_Fucom(ir_node *node)
2893 dbg_info *dbgi = get_irn_dbg_info(node);
2894 ir_node *block = get_nodes_block(node);
2895 ir_node *new_block = be_transform_node(block);
2896 ir_node *left = get_Cmp_left(node);
2897 ir_node *new_left = be_transform_node(left);
2898 ir_node *right = get_Cmp_right(node);
2899 ir_mode *cmp_mode = get_irn_mode(left);
2902 check_x87_floatmode(cmp_mode);
2904 if (ia32_cg_config.use_fucomi) {
2905 new_right = be_transform_node(right);
2906 new_node = new_bd_ia32_vFucomi(dbgi, new_block, new_left,
2908 set_ia32_commutative(new_node);
2909 SET_IA32_ORIG_NODE(new_node, node);
2911 if (is_Const_0(right)) {
2912 new_node = new_bd_ia32_vFtstFnstsw(dbgi, new_block, new_left, 0);
2914 new_right = be_transform_node(right);
2915 new_node = new_bd_ia32_vFucomFnstsw(dbgi, new_block, new_left, new_right, 0);
2916 set_ia32_commutative(new_node);
2919 SET_IA32_ORIG_NODE(new_node, node);
2921 new_node = new_bd_ia32_Sahf(dbgi, new_block, new_node);
2922 SET_IA32_ORIG_NODE(new_node, node);
2928 static ir_node *create_Ucomi(ir_node *node)
2930 dbg_info *dbgi = get_irn_dbg_info(node);
2931 ir_node *src_block = get_nodes_block(node);
2932 ir_node *new_block = be_transform_node(src_block);
2933 ir_node *left = get_Cmp_left(node);
2934 ir_node *right = get_Cmp_right(node);
2936 ia32_address_mode_t am;
2937 ia32_address_t *addr = &am.addr;
2939 match_arguments(&am, src_block, left, right, NULL,
2940 match_commutative | match_am);
2942 new_node = new_bd_ia32_Ucomi(dbgi, new_block, addr->base, addr->index,
2943 addr->mem, am.new_op1, am.new_op2,
2945 set_am_attributes(new_node, &am);
2947 SET_IA32_ORIG_NODE(new_node, node);
2949 new_node = fix_mem_proj(new_node, &am);
2954 static bool ia32_mux_upper_bits_clean(const ir_node *node, ir_mode *mode)
2956 ir_node *mux_true = get_Mux_true(node);
2957 ir_node *mux_false = get_Mux_false(node);
2958 ir_mode *mux_mode = get_irn_mode(node);
2959 /* mux nodes which get transformed to the set instruction are not clean */
2960 if (is_Const(mux_true) && is_Const(mux_false)
2961 && get_mode_size_bits(mux_mode) == 8) {
2964 return be_upper_bits_clean(mux_true, mode)
2965 && be_upper_bits_clean(mux_false, mode);
2969 * Generate code for a Cmp.
2971 static ir_node *gen_Cmp(ir_node *node)
2973 dbg_info *dbgi = get_irn_dbg_info(node);
2974 ir_node *block = get_nodes_block(node);
2975 ir_node *new_block = be_transform_node(block);
2976 ir_node *left = get_Cmp_left(node);
2977 ir_node *right = get_Cmp_right(node);
2978 ir_mode *cmp_mode = get_irn_mode(left);
2980 ia32_address_mode_t am;
2981 ia32_address_t *addr = &am.addr;
2983 if (mode_is_float(cmp_mode)) {
2984 if (ia32_cg_config.use_sse2) {
2985 return create_Ucomi(node);
2987 return create_Fucom(node);
2991 assert(ia32_mode_needs_gp_reg(cmp_mode));
2993 /* Prefer the Test instruction, when encountering (x & y) ==/!= 0 */
2994 if (is_Const_0(right) &&
2996 get_irn_n_edges(left) == 1) {
2997 /* Test(and_left, and_right) */
2998 ir_node *and_left = get_And_left(left);
2999 ir_node *and_right = get_And_right(left);
3001 /* matze: code here used mode instead of cmd_mode, I think it is always
3002 * the same as cmp_mode, but I leave this here to see if this is really
3005 assert(get_irn_mode(and_left) == cmp_mode);
3007 match_arguments(&am, block, and_left, and_right, NULL,
3009 match_am | match_8bit_am | match_16bit_am |
3010 match_am_and_immediates | match_immediate);
3012 /* use 32bit compare mode if possible since the opcode is smaller */
3013 if (am.op_type == ia32_Normal &&
3014 be_upper_bits_clean(and_left, cmp_mode) &&
3015 be_upper_bits_clean(and_right, cmp_mode)) {
3016 cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
3019 if (get_mode_size_bits(cmp_mode) == 8) {
3020 new_node = new_bd_ia32_Test8Bit(dbgi, new_block, addr->base,
3021 addr->index, addr->mem,
3022 am.new_op1, am.new_op2,
3025 new_node = new_bd_ia32_Test(dbgi, new_block, addr->base,
3026 addr->index, addr->mem, am.new_op1,
3027 am.new_op2, am.ins_permuted);
3030 /* Cmp(left, right) */
3031 match_arguments(&am, block, left, right, NULL,
3033 match_am | match_8bit_am | match_16bit_am |
3034 match_am_and_immediates | match_immediate);
3035 /* use 32bit compare mode if possible since the opcode is smaller */
3036 if (am.op_type == ia32_Normal &&
3037 be_upper_bits_clean(left, cmp_mode) &&
3038 be_upper_bits_clean(right, cmp_mode)) {
3039 cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
3042 if (get_mode_size_bits(cmp_mode) == 8) {
3043 new_node = new_bd_ia32_Cmp8Bit(dbgi, new_block, addr->base,
3044 addr->index, addr->mem, am.new_op1,
3045 am.new_op2, am.ins_permuted);
3047 new_node = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index,
3048 addr->mem, am.new_op1, am.new_op2,
3052 set_am_attributes(new_node, &am);
3053 set_ia32_ls_mode(new_node, cmp_mode);
3055 SET_IA32_ORIG_NODE(new_node, node);
3057 new_node = fix_mem_proj(new_node, &am);
3062 static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags,
3063 ia32_condition_code_t cc)
3065 dbg_info *dbgi = get_irn_dbg_info(node);
3066 ir_node *block = get_nodes_block(node);
3067 ir_node *new_block = be_transform_node(block);
3068 ir_node *val_true = get_Mux_true(node);
3069 ir_node *val_false = get_Mux_false(node);
3071 ia32_address_mode_t am;
3072 ia32_address_t *addr;
3074 assert(ia32_cg_config.use_cmov);
3075 assert(ia32_mode_needs_gp_reg(get_irn_mode(val_true)));
3079 match_arguments(&am, block, val_false, val_true, flags,
3080 match_commutative | match_am | match_16bit_am | match_mode_neutral);
3082 if (am.ins_permuted)
3083 cc = ia32_negate_condition_code(cc);
3085 new_node = new_bd_ia32_CMovcc(dbgi, new_block, addr->base, addr->index,
3086 addr->mem, am.new_op1, am.new_op2, new_flags,
3088 set_am_attributes(new_node, &am);
3090 SET_IA32_ORIG_NODE(new_node, node);
3092 new_node = fix_mem_proj(new_node, &am);
3098 * Creates a ia32 Setcc instruction.
3100 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
3101 ir_node *flags, ia32_condition_code_t cc,
3104 ir_mode *mode = get_irn_mode(orig_node);
3107 new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, cc);
3108 SET_IA32_ORIG_NODE(new_node, orig_node);
3110 /* we might need to conv the result up */
3111 if (get_mode_size_bits(mode) > 8) {
3112 new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP,
3113 nomem, new_node, mode_Bu);
3114 SET_IA32_ORIG_NODE(new_node, orig_node);
3121 * Create instruction for an unsigned Difference or Zero.
3123 static ir_node *create_doz(ir_node *psi, ir_node *a, ir_node *b)
3125 ir_mode *mode = get_irn_mode(psi);
3135 new_node = gen_binop(psi, a, b, new_bd_ia32_Sub,
3136 match_mode_neutral | match_am | match_immediate | match_two_users);
3138 block = get_nodes_block(new_node);
3140 if (is_Proj(new_node)) {
3141 sub = get_Proj_pred(new_node);
3144 set_irn_mode(sub, mode_T);
3145 new_node = new_rd_Proj(NULL, sub, mode, pn_ia32_res);
3147 assert(is_ia32_Sub(sub));
3148 eflags = new_rd_Proj(NULL, sub, mode_Iu, pn_ia32_Sub_flags);
3150 dbgi = get_irn_dbg_info(psi);
3151 sbb = new_bd_ia32_Sbb0(dbgi, block, eflags);
3152 set_ia32_ls_mode(sbb, mode_Iu);
3153 notn = new_bd_ia32_Not(dbgi, block, sbb);
3155 new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, notn);
3156 set_ia32_ls_mode(new_node, mode_Iu);
3157 set_ia32_commutative(new_node);
3162 * Create an const array of two float consts.
3164 * @param c0 the first constant
3165 * @param c1 the second constant
3166 * @param new_mode IN/OUT for the mode of the constants, if NULL
3167 * smallest possible mode will be used
3169 static ir_entity *ia32_create_const_array(ir_node *c0, ir_node *c1, ir_mode **new_mode)
3172 ir_mode *mode = *new_mode;
3174 ir_initializer_t *initializer;
3175 ir_tarval *tv0 = get_Const_tarval(c0);
3176 ir_tarval *tv1 = get_Const_tarval(c1);
3179 /* detect the best mode for the constants */
3180 mode = get_tarval_mode(tv0);
3182 if (mode != mode_F) {
3183 if (tarval_ieee754_can_conv_lossless(tv0, mode_F) &&
3184 tarval_ieee754_can_conv_lossless(tv1, mode_F)) {
3186 tv0 = tarval_convert_to(tv0, mode);
3187 tv1 = tarval_convert_to(tv1, mode);
3188 } else if (mode != mode_D) {
3189 if (tarval_ieee754_can_conv_lossless(tv0, mode_D) &&
3190 tarval_ieee754_can_conv_lossless(tv1, mode_D)) {
3192 tv0 = tarval_convert_to(tv0, mode);
3193 tv1 = tarval_convert_to(tv1, mode);
3200 tp = ia32_get_prim_type(mode);
3201 tp = ia32_create_float_array(tp);
3203 ent = new_entity(get_glob_type(), id_unique("C%u"), tp);
3205 set_entity_ld_ident(ent, get_entity_ident(ent));
3206 set_entity_visibility(ent, ir_visibility_private);
3207 add_entity_linkage(ent, IR_LINKAGE_CONSTANT);
3209 initializer = create_initializer_compound(2);
3211 set_initializer_compound_value(initializer, 0, create_initializer_tarval(tv0));
3212 set_initializer_compound_value(initializer, 1, create_initializer_tarval(tv1));
3214 set_entity_initializer(ent, initializer);
3221 * Possible transformations for creating a Setcc.
3223 enum setcc_transform_insn {
3235 typedef struct setcc_transform {
3237 ia32_condition_code_t cc;
3239 enum setcc_transform_insn transform;
3243 } setcc_transform_t;
3246 * Setcc can only handle 0 and 1 result.
3247 * Find a transformation that creates 0 and 1 from
3250 static void find_const_transform(ia32_condition_code_t cc,
3251 ir_tarval *t, ir_tarval *f,
3252 setcc_transform_t *res)
3258 if (tarval_is_null(t)) {
3262 cc = ia32_negate_condition_code(cc);
3263 } else if (tarval_cmp(t, f) == ir_relation_less) {
3264 // now, t is the bigger one
3268 cc = ia32_negate_condition_code(cc);
3272 if (! tarval_is_null(f)) {
3273 ir_tarval *t_sub = tarval_sub(t, f, NULL);
3276 res->steps[step].transform = SETCC_TR_ADD;
3278 if (t == tarval_bad)
3279 panic("constant subtract failed");
3280 if (! tarval_is_long(f))
3281 panic("tarval is not long");
3283 res->steps[step].val = get_tarval_long(f);
3285 f = tarval_sub(f, f, NULL);
3286 assert(tarval_is_null(f));
3289 if (tarval_is_one(t)) {
3290 res->steps[step].transform = SETCC_TR_SET;
3291 res->num_steps = ++step;
3295 if (tarval_is_minus_one(t)) {
3296 res->steps[step].transform = SETCC_TR_NEG;
3298 res->steps[step].transform = SETCC_TR_SET;
3299 res->num_steps = ++step;
3302 if (tarval_is_long(t)) {
3303 long v = get_tarval_long(t);
3305 res->steps[step].val = 0;
3308 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3310 res->steps[step].transform = SETCC_TR_LEAxx;
3311 res->steps[step].scale = 3; /* (a << 3) + a */
3314 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3316 res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA;
3317 res->steps[step].scale = 3; /* (a << 3) */
3320 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3322 res->steps[step].transform = SETCC_TR_LEAxx;
3323 res->steps[step].scale = 2; /* (a << 2) + a */
3326 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3328 res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA;
3329 res->steps[step].scale = 2; /* (a << 2) */
3332 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3334 res->steps[step].transform = SETCC_TR_LEAxx;
3335 res->steps[step].scale = 1; /* (a << 1) + a */
3338 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3340 res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA;
3341 res->steps[step].scale = 1; /* (a << 1) */
3344 res->num_steps = step;
3347 if (! tarval_is_single_bit(t)) {
3348 res->steps[step].transform = SETCC_TR_AND;
3349 res->steps[step].val = v;
3351 res->steps[step].transform = SETCC_TR_NEG;
3353 int val = get_tarval_lowest_bit(t);
3356 res->steps[step].transform = SETCC_TR_SHL;
3357 res->steps[step].scale = val;
3361 res->steps[step].transform = SETCC_TR_SET;
3362 res->num_steps = ++step;
3365 panic("tarval is not long");
3369 * Transforms a Mux node into some code sequence.
3371 * @return The transformed node.
3373 static ir_node *gen_Mux(ir_node *node)
3375 dbg_info *dbgi = get_irn_dbg_info(node);
3376 ir_node *block = get_nodes_block(node);
3377 ir_node *new_block = be_transform_node(block);
3378 ir_node *mux_true = get_Mux_true(node);
3379 ir_node *mux_false = get_Mux_false(node);
3380 ir_node *sel = get_Mux_sel(node);
3381 ir_mode *mode = get_irn_mode(node);
3385 ia32_condition_code_t cc;
3387 assert(get_irn_mode(sel) == mode_b);
3389 is_abs = ir_mux_is_abs(sel, mux_false, mux_true);
3391 if (ia32_mode_needs_gp_reg(mode)) {
3392 ir_fprintf(stderr, "Optimisation warning: Integer abs %+F not transformed\n",
3395 ir_node *op = ir_get_abs_op(sel, mux_false, mux_true);
3396 return create_float_abs(dbgi, block, op, is_abs < 0, node);
3400 /* Note: a Mux node uses a Load two times IFF it's used in the compare AND in the result */
3401 if (mode_is_float(mode)) {
3402 ir_node *cmp_left = get_Cmp_left(sel);
3403 ir_node *cmp_right = get_Cmp_right(sel);
3404 ir_relation relation = get_Cmp_relation(sel);
3406 if (ia32_cg_config.use_sse2) {
3407 if (relation == ir_relation_less || relation == ir_relation_less_equal) {
3408 if (cmp_left == mux_true && cmp_right == mux_false) {
3409 /* Mux(a <= b, a, b) => MIN */
3410 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
3411 match_commutative | match_am | match_two_users);
3412 } else if (cmp_left == mux_false && cmp_right == mux_true) {
3413 /* Mux(a <= b, b, a) => MAX */
3414 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
3415 match_commutative | match_am | match_two_users);
3417 } else if (relation == ir_relation_greater || relation == ir_relation_greater_equal) {
3418 if (cmp_left == mux_true && cmp_right == mux_false) {
3419 /* Mux(a >= b, a, b) => MAX */
3420 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
3421 match_commutative | match_am | match_two_users);
3422 } else if (cmp_left == mux_false && cmp_right == mux_true) {
3423 /* Mux(a >= b, b, a) => MIN */
3424 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
3425 match_commutative | match_am | match_two_users);
3430 if (is_Const(mux_true) && is_Const(mux_false)) {
3431 ia32_address_mode_t am;
3436 flags = get_flags_node(sel, &cc);
3437 new_node = create_set_32bit(dbgi, new_block, flags, cc, node);
3439 if (ia32_cg_config.use_sse2) {
3440 /* cannot load from different mode on SSE */
3443 /* x87 can load any mode */
3447 am.addr.symconst_ent = ia32_create_const_array(mux_false, mux_true, &new_mode);
3449 if (new_mode == mode_F) {
3451 } else if (new_mode == mode_D) {
3453 } else if (new_mode == ia32_mode_E) {
3454 /* arg, shift 16 NOT supported */
3456 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3458 panic("Unsupported constant size");
3461 am.ls_mode = new_mode;
3462 am.addr.base = get_symconst_base();
3463 am.addr.index = new_node;
3464 am.addr.mem = nomem;
3466 am.addr.scale = scale;
3467 am.addr.use_frame = 0;
3468 am.addr.tls_segment = false;
3469 am.addr.frame_entity = NULL;
3470 am.addr.symconst_sign = 0;
3471 am.mem_proj = am.addr.mem;
3472 am.op_type = ia32_AddrModeS;
3475 am.pinned = op_pin_state_floats;
3477 am.ins_permuted = false;
3479 if (ia32_cg_config.use_sse2)
3480 load = new_bd_ia32_xLoad(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
3482 load = new_bd_ia32_vfld(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
3483 set_am_attributes(load, &am);
3485 return new_rd_Proj(NULL, load, mode_vfp, pn_ia32_res);
3487 panic("cannot transform floating point Mux");
3490 assert(ia32_mode_needs_gp_reg(mode));
3493 ir_node *cmp_left = get_Cmp_left(sel);
3494 ir_node *cmp_right = get_Cmp_right(sel);
3495 ir_relation relation = get_Cmp_relation(sel);
3496 ir_node *val_true = mux_true;
3497 ir_node *val_false = mux_false;
3499 if (is_Const(val_true) && is_Const_null(val_true)) {
3500 ir_node *tmp = val_false;
3501 val_false = val_true;
3503 relation = get_negated_relation(relation);
3505 if (is_Const_0(val_false) && is_Sub(val_true)) {
3506 if ((relation & ir_relation_greater)
3507 && get_Sub_left(val_true) == cmp_left
3508 && get_Sub_right(val_true) == cmp_right) {
3509 return create_doz(node, cmp_left, cmp_right);
3511 if ((relation & ir_relation_less)
3512 && get_Sub_left(val_true) == cmp_right
3513 && get_Sub_right(val_true) == cmp_left) {
3514 return create_doz(node, cmp_right, cmp_left);
3519 flags = get_flags_node(sel, &cc);
3521 if (is_Const(mux_true) && is_Const(mux_false)) {
3522 /* both are const, good */
3523 ir_tarval *tv_true = get_Const_tarval(mux_true);
3524 ir_tarval *tv_false = get_Const_tarval(mux_false);
3525 setcc_transform_t res;
3528 find_const_transform(cc, tv_true, tv_false, &res);
3530 for (step = (int)res.num_steps - 1; step >= 0; --step) {
3533 switch (res.steps[step].transform) {
3535 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, noreg_GP);
3536 add_ia32_am_offs_int(new_node, res.steps[step].val);
3538 case SETCC_TR_ADDxx:
3539 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3542 new_node = new_bd_ia32_Lea(dbgi, new_block, noreg_GP, new_node);
3543 set_ia32_am_scale(new_node, res.steps[step].scale);
3544 set_ia32_am_offs_int(new_node, res.steps[step].val);
3546 case SETCC_TR_LEAxx:
3547 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3548 set_ia32_am_scale(new_node, res.steps[step].scale);
3549 set_ia32_am_offs_int(new_node, res.steps[step].val);
3552 imm = ia32_immediate_from_long(res.steps[step].scale);
3553 new_node = new_bd_ia32_Shl(dbgi, new_block, new_node, imm);
3556 new_node = new_bd_ia32_Neg(dbgi, new_block, new_node);
3559 new_node = new_bd_ia32_Not(dbgi, new_block, new_node);
3562 imm = ia32_immediate_from_long(res.steps[step].val);
3563 new_node = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, imm);
3566 new_node = create_set_32bit(dbgi, new_block, flags, res.cc, node);
3569 panic("unknown setcc transform");
3573 new_node = create_CMov(node, sel, flags, cc);
3580 * Create a conversion from x87 state register to general purpose.
3582 static ir_node *gen_x87_fp_to_gp(ir_node *node)
3584 ir_node *block = be_transform_node(get_nodes_block(node));
3585 ir_node *op = get_Conv_op(node);
3586 ir_node *new_op = be_transform_node(op);
3587 ir_graph *irg = current_ir_graph;
3588 dbg_info *dbgi = get_irn_dbg_info(node);
3589 ir_mode *mode = get_irn_mode(node);
3590 ir_node *frame = get_irg_frame(irg);
3591 ir_node *fist, *load, *mem;
3593 fist = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_op);
3594 set_irn_pinned(fist, op_pin_state_floats);
3595 set_ia32_use_frame(fist);
3596 set_ia32_op_type(fist, ia32_AddrModeD);
3598 assert((long)pn_ia32_vfist_M == (long) pn_ia32_vfisttp_M);
3599 mem = new_r_Proj(fist, mode_M, pn_ia32_vfist_M);
3601 assert(get_mode_size_bits(mode) <= 32);
3602 /* exception we can only store signed 32 bit integers, so for unsigned
3603 we store a 64bit (signed) integer and load the lower bits */
3604 if (get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
3605 set_ia32_ls_mode(fist, mode_Ls);
3607 set_ia32_ls_mode(fist, mode_Is);
3609 SET_IA32_ORIG_NODE(fist, node);
3612 load = new_bd_ia32_Load(dbgi, block, get_irg_frame(irg), noreg_GP, mem);
3614 set_irn_pinned(load, op_pin_state_floats);
3615 set_ia32_use_frame(load);
3616 set_ia32_op_type(load, ia32_AddrModeS);
3617 set_ia32_ls_mode(load, mode_Is);
3618 if (get_ia32_ls_mode(fist) == mode_Ls) {
3619 ia32_attr_t *attr = get_ia32_attr(load);
3620 attr->data.need_64bit_stackent = 1;
3622 ia32_attr_t *attr = get_ia32_attr(load);
3623 attr->data.need_32bit_stackent = 1;
3625 SET_IA32_ORIG_NODE(load, node);
3627 return new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
3631 * Creates a x87 Conv by placing a Store and a Load
3633 static ir_node *gen_x87_conv(ir_mode *tgt_mode, ir_node *node)
3635 ir_node *block = get_nodes_block(node);
3636 ir_graph *irg = get_Block_irg(block);
3637 dbg_info *dbgi = get_irn_dbg_info(node);
3638 ir_node *frame = get_irg_frame(irg);
3640 ir_node *store, *load;
3643 store = new_bd_ia32_vfst(dbgi, block, frame, noreg_GP, nomem, node, tgt_mode);
3644 set_ia32_use_frame(store);
3645 set_ia32_op_type(store, ia32_AddrModeD);
3646 SET_IA32_ORIG_NODE(store, node);
3648 store_mem = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
3650 load = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store_mem, tgt_mode);
3651 set_ia32_use_frame(load);
3652 set_ia32_op_type(load, ia32_AddrModeS);
3653 SET_IA32_ORIG_NODE(load, node);
3655 new_node = new_r_Proj(load, ia32_mode_E, pn_ia32_vfld_res);
3659 static ir_node *create_Conv_I2I(dbg_info *dbgi, ir_node *block, ir_node *base,
3660 ir_node *index, ir_node *mem, ir_node *val, ir_mode *mode)
3662 ir_node *(*func)(dbg_info*, ir_node*, ir_node*, ir_node*, ir_node*, ir_node*, ir_mode*);
3664 func = get_mode_size_bits(mode) == 8 ?
3665 new_bd_ia32_Conv_I2I8Bit : new_bd_ia32_Conv_I2I;
3666 return func(dbgi, block, base, index, mem, val, mode);
3670 * Create a conversion from general purpose to x87 register
3672 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode)
3674 ir_node *src_block = get_nodes_block(node);
3675 ir_node *block = be_transform_node(src_block);
3676 ir_graph *irg = get_Block_irg(block);
3677 dbg_info *dbgi = get_irn_dbg_info(node);
3678 ir_node *op = get_Conv_op(node);
3679 ir_node *new_op = NULL;
3681 ir_mode *store_mode;
3687 /* fild can use source AM if the operand is a signed 16bit or 32bit integer */
3688 if (possible_int_mode_for_fp(src_mode)) {
3689 ia32_address_mode_t am;
3691 match_arguments(&am, src_block, NULL, op, NULL, match_am | match_try_am | match_16bit_am | match_upconv);
3692 if (am.op_type == ia32_AddrModeS) {
3693 ia32_address_t *addr = &am.addr;
3695 fild = new_bd_ia32_vfild(dbgi, block, addr->base, addr->index, addr->mem);
3696 new_node = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
3698 set_am_attributes(fild, &am);
3699 SET_IA32_ORIG_NODE(fild, node);
3701 fix_mem_proj(fild, &am);
3706 if (new_op == NULL) {
3707 new_op = be_transform_node(op);
3710 mode = get_irn_mode(op);
3712 /* first convert to 32 bit signed if necessary */
3713 if (get_mode_size_bits(src_mode) < 32) {
3714 if (!be_upper_bits_clean(op, src_mode)) {
3715 new_op = create_Conv_I2I(dbgi, block, noreg_GP, noreg_GP, nomem, new_op, src_mode);
3716 SET_IA32_ORIG_NODE(new_op, node);
3721 assert(get_mode_size_bits(mode) == 32);
3724 store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, new_op);
3726 set_ia32_use_frame(store);
3727 set_ia32_op_type(store, ia32_AddrModeD);
3728 set_ia32_ls_mode(store, mode_Iu);
3730 store_mem = new_r_Proj(store, mode_M, pn_ia32_Store_M);
3732 /* exception for 32bit unsigned, do a 64bit spill+load */
3733 if (!mode_is_signed(mode)) {
3736 ir_node *zero_const = ia32_create_Immediate(NULL, 0, 0);
3738 ir_node *zero_store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg),
3739 noreg_GP, nomem, zero_const);
3740 ir_node *zero_store_mem = new_r_Proj(zero_store, mode_M, pn_ia32_Store_M);
3742 set_ia32_use_frame(zero_store);
3743 set_ia32_op_type(zero_store, ia32_AddrModeD);
3744 add_ia32_am_offs_int(zero_store, 4);
3745 set_ia32_ls_mode(zero_store, mode_Iu);
3747 in[0] = zero_store_mem;
3750 store_mem = new_rd_Sync(dbgi, block, 2, in);
3751 store_mode = mode_Ls;
3753 store_mode = mode_Is;
3757 fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg_GP, store_mem);
3759 set_ia32_use_frame(fild);
3760 set_ia32_op_type(fild, ia32_AddrModeS);
3761 set_ia32_ls_mode(fild, store_mode);
3763 new_node = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
3769 * Create a conversion from one integer mode into another one
3771 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
3772 dbg_info *dbgi, ir_node *block, ir_node *op,
3775 ir_node *new_block = be_transform_node(block);
3777 ia32_address_mode_t am;
3778 ia32_address_t *addr = &am.addr;
3781 assert(get_mode_size_bits(src_mode) < get_mode_size_bits(tgt_mode));
3783 #ifdef DEBUG_libfirm
3785 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
3790 if (be_upper_bits_clean(op, src_mode)) {
3791 return be_transform_node(op);
3794 match_arguments(&am, block, NULL, op, NULL,
3795 match_am | match_8bit_am | match_16bit_am);
3797 new_node = create_Conv_I2I(dbgi, new_block, addr->base, addr->index,
3798 addr->mem, am.new_op2, src_mode);
3799 set_am_attributes(new_node, &am);
3800 /* match_arguments assume that out-mode = in-mode, this isn't true here
3802 set_ia32_ls_mode(new_node, src_mode);
3803 SET_IA32_ORIG_NODE(new_node, node);
3804 new_node = fix_mem_proj(new_node, &am);
3809 * Transforms a Conv node.
3811 * @return The created ia32 Conv node
3813 static ir_node *gen_Conv(ir_node *node)
3815 ir_node *block = get_nodes_block(node);
3816 ir_node *new_block = be_transform_node(block);
3817 ir_node *op = get_Conv_op(node);
3818 ir_node *new_op = NULL;
3819 dbg_info *dbgi = get_irn_dbg_info(node);
3820 ir_mode *src_mode = get_irn_mode(op);
3821 ir_mode *tgt_mode = get_irn_mode(node);
3822 int src_bits = get_mode_size_bits(src_mode);
3823 int tgt_bits = get_mode_size_bits(tgt_mode);
3824 ir_node *res = NULL;
3826 assert(!mode_is_int(src_mode) || src_bits <= 32);
3827 assert(!mode_is_int(tgt_mode) || tgt_bits <= 32);
3829 /* modeB -> X should already be lowered by the lower_mode_b pass */
3830 if (src_mode == mode_b) {
3831 panic("ConvB not lowered %+F", node);
3834 if (src_mode == tgt_mode) {
3835 /* this should be optimized already, but who knows... */
3836 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node);)
3837 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
3838 return be_transform_node(op);
3841 if (mode_is_float(src_mode)) {
3842 new_op = be_transform_node(op);
3843 /* we convert from float ... */
3844 if (mode_is_float(tgt_mode)) {
3846 if (ia32_cg_config.use_sse2) {
3847 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
3848 res = new_bd_ia32_Conv_FP2FP(dbgi, new_block, noreg_GP, noreg_GP,
3850 set_ia32_ls_mode(res, tgt_mode);
3852 if (src_bits < tgt_bits) {
3853 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3856 res = gen_x87_conv(tgt_mode, new_op);
3857 SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
3863 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
3864 if (ia32_cg_config.use_sse2) {
3865 res = new_bd_ia32_Conv_FP2I(dbgi, new_block, noreg_GP, noreg_GP,
3867 set_ia32_ls_mode(res, src_mode);
3869 return gen_x87_fp_to_gp(node);
3873 /* we convert from int ... */
3874 if (mode_is_float(tgt_mode)) {
3876 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
3877 if (ia32_cg_config.use_sse2) {
3878 new_op = be_transform_node(op);
3879 res = new_bd_ia32_Conv_I2FP(dbgi, new_block, noreg_GP, noreg_GP,
3881 set_ia32_ls_mode(res, tgt_mode);
3883 unsigned int_mantissa = get_mode_size_bits(src_mode) - (mode_is_signed(src_mode) ? 1 : 0);
3884 unsigned float_mantissa = get_mode_mantissa_size(tgt_mode);
3885 res = gen_x87_gp_to_fp(node, src_mode);
3887 /* we need a float-conv, if the int mode has more bits than the
3889 if (float_mantissa < int_mantissa) {
3890 res = gen_x87_conv(tgt_mode, res);
3891 SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
3895 } else if (tgt_mode == mode_b) {
3896 /* mode_b lowering already took care that we only have 0/1 values */
3897 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3898 src_mode, tgt_mode));
3899 return be_transform_node(op);
3902 if (src_bits >= tgt_bits) {
3903 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3904 src_mode, tgt_mode));
3905 return be_transform_node(op);
3908 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
3916 static ir_node *create_immediate_or_transform(ir_node *node,
3917 char immediate_constraint_type)
3919 ir_node *new_node = ia32_try_create_Immediate(node, immediate_constraint_type);
3920 if (new_node == NULL) {
3921 new_node = be_transform_node(node);
3927 * Transforms a FrameAddr into an ia32 Add.
3929 static ir_node *gen_be_FrameAddr(ir_node *node)
3931 ir_node *block = be_transform_node(get_nodes_block(node));
3932 ir_node *op = be_get_FrameAddr_frame(node);
3933 ir_node *new_op = be_transform_node(op);
3934 dbg_info *dbgi = get_irn_dbg_info(node);
3937 new_node = new_bd_ia32_Lea(dbgi, block, new_op, noreg_GP);
3938 set_ia32_frame_ent(new_node, arch_get_frame_entity(node));
3939 set_ia32_use_frame(new_node);
3941 SET_IA32_ORIG_NODE(new_node, node);
3947 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3949 static ir_node *gen_be_Return(ir_node *node)
3951 ir_graph *irg = current_ir_graph;
3952 ir_node *ret_val = get_irn_n(node, n_be_Return_val);
3953 ir_node *ret_mem = get_irn_n(node, n_be_Return_mem);
3954 ir_node *new_ret_val = be_transform_node(ret_val);
3955 ir_node *new_ret_mem = be_transform_node(ret_mem);
3956 ir_entity *ent = get_irg_entity(irg);
3957 ir_type *tp = get_entity_type(ent);
3958 dbg_info *dbgi = get_irn_dbg_info(node);
3959 ir_node *block = be_transform_node(get_nodes_block(node));
3973 assert(ret_val != NULL);
3974 if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) {
3975 return be_duplicate_node(node);
3978 res_type = get_method_res_type(tp, 0);
3980 if (! is_Primitive_type(res_type)) {
3981 return be_duplicate_node(node);
3984 mode = get_type_mode(res_type);
3985 if (! mode_is_float(mode)) {
3986 return be_duplicate_node(node);
3989 assert(get_method_n_ress(tp) == 1);
3991 frame = get_irg_frame(irg);
3993 /* store xmm0 onto stack */
3994 sse_store = new_bd_ia32_xStoreSimple(dbgi, block, frame, noreg_GP,
3995 new_ret_mem, new_ret_val);
3996 set_ia32_ls_mode(sse_store, mode);
3997 set_ia32_op_type(sse_store, ia32_AddrModeD);
3998 set_ia32_use_frame(sse_store);
3999 store_mem = new_r_Proj(sse_store, mode_M, pn_ia32_xStoreSimple_M);
4001 /* load into x87 register */
4002 fld = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store_mem, mode);
4003 set_ia32_op_type(fld, ia32_AddrModeS);
4004 set_ia32_use_frame(fld);
4006 mproj = new_r_Proj(fld, mode_M, pn_ia32_vfld_M);
4007 fld = new_r_Proj(fld, mode_vfp, pn_ia32_vfld_res);
4009 /* create a new return */
4010 arity = get_irn_arity(node);
4011 in = ALLOCAN(ir_node*, arity);
4012 pop = be_Return_get_pop(node);
4013 for (i = 0; i < arity; ++i) {
4014 ir_node *op = get_irn_n(node, i);
4015 if (op == ret_val) {
4017 } else if (op == ret_mem) {
4020 in[i] = be_transform_node(op);
4023 new_node = be_new_Return(dbgi, irg, block, arity, pop, arity, in);
4024 copy_node_attr(irg, node, new_node);
4030 * Transform a be_AddSP into an ia32_SubSP.
4032 static ir_node *gen_be_AddSP(ir_node *node)
4034 ir_node *sz = get_irn_n(node, n_be_AddSP_size);
4035 ir_node *sp = get_irn_n(node, n_be_AddSP_old_sp);
4037 ir_node *new_node = gen_binop(node, sp, sz, new_bd_ia32_SubSP,
4038 match_am | match_immediate);
4039 assert(is_ia32_SubSP(new_node));
4040 arch_set_irn_register_out(new_node, pn_ia32_SubSP_stack,
4041 &ia32_registers[REG_ESP]);
4046 * Transform a be_SubSP into an ia32_AddSP
4048 static ir_node *gen_be_SubSP(ir_node *node)
4050 ir_node *sz = get_irn_n(node, n_be_SubSP_size);
4051 ir_node *sp = get_irn_n(node, n_be_SubSP_old_sp);
4053 ir_node *new_node = gen_binop(node, sp, sz, new_bd_ia32_AddSP,
4054 match_am | match_immediate);
4055 assert(is_ia32_AddSP(new_node));
4056 arch_set_irn_register_out(new_node, pn_ia32_AddSP_stack,
4057 &ia32_registers[REG_ESP]);
4061 static ir_node *gen_Phi(ir_node *node)
4063 ir_mode *mode = get_irn_mode(node);
4064 const arch_register_req_t *req;
4065 if (ia32_mode_needs_gp_reg(mode)) {
4066 /* we shouldn't have any 64bit stuff around anymore */
4067 assert(get_mode_size_bits(mode) <= 32);
4068 /* all integer operations are on 32bit registers now */
4070 req = ia32_reg_classes[CLASS_ia32_gp].class_req;
4071 } else if (mode_is_float(mode)) {
4072 if (ia32_cg_config.use_sse2) {
4074 req = ia32_reg_classes[CLASS_ia32_xmm].class_req;
4077 req = ia32_reg_classes[CLASS_ia32_vfp].class_req;
4080 req = arch_no_register_req;
4083 return be_transform_phi(node, req);
4086 static ir_node *gen_Jmp(ir_node *node)
4088 ir_node *block = get_nodes_block(node);
4089 ir_node *new_block = be_transform_node(block);
4090 dbg_info *dbgi = get_irn_dbg_info(node);
4093 new_node = new_bd_ia32_Jmp(dbgi, new_block);
4094 SET_IA32_ORIG_NODE(new_node, node);
4102 static ir_node *gen_IJmp(ir_node *node)
4104 ir_node *block = get_nodes_block(node);
4105 ir_node *new_block = be_transform_node(block);
4106 dbg_info *dbgi = get_irn_dbg_info(node);
4107 ir_node *op = get_IJmp_target(node);
4109 ia32_address_mode_t am;
4110 ia32_address_t *addr = &am.addr;
4112 assert(get_irn_mode(op) == mode_P);
4114 match_arguments(&am, block, NULL, op, NULL,
4115 match_am | match_immediate | match_upconv);
4117 new_node = new_bd_ia32_IJmp(dbgi, new_block, addr->base, addr->index,
4118 addr->mem, am.new_op2);
4119 set_am_attributes(new_node, &am);
4120 SET_IA32_ORIG_NODE(new_node, node);
4122 new_node = fix_mem_proj(new_node, &am);
4127 static ir_node *gen_ia32_l_Add(ir_node *node)
4129 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
4130 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
4131 ir_node *lowered = gen_binop(node, left, right, new_bd_ia32_Add,
4132 match_commutative | match_am | match_immediate |
4133 match_mode_neutral);
4135 if (is_Proj(lowered)) {
4136 lowered = get_Proj_pred(lowered);
4138 assert(is_ia32_Add(lowered));
4139 set_irn_mode(lowered, mode_T);
4145 static ir_node *gen_ia32_l_Adc(ir_node *node)
4147 return gen_binop_flags(node, new_bd_ia32_Adc,
4148 match_commutative | match_am | match_immediate |
4149 match_mode_neutral);
4153 * Transforms a l_MulS into a "real" MulS node.
4155 * @return the created ia32 Mul node
4157 static ir_node *gen_ia32_l_Mul(ir_node *node)
4159 ir_node *left = get_binop_left(node);
4160 ir_node *right = get_binop_right(node);
4162 return gen_binop(node, left, right, new_bd_ia32_Mul,
4163 match_commutative | match_am | match_mode_neutral);
4167 * Transforms a l_IMulS into a "real" IMul1OPS node.
4169 * @return the created ia32 IMul1OP node
4171 static ir_node *gen_ia32_l_IMul(ir_node *node)
4173 ir_node *left = get_binop_left(node);
4174 ir_node *right = get_binop_right(node);
4176 return gen_binop(node, left, right, new_bd_ia32_IMul1OP,
4177 match_commutative | match_am | match_mode_neutral);
4180 static ir_node *gen_ia32_l_Sub(ir_node *node)
4182 ir_node *left = get_irn_n(node, n_ia32_l_Sub_minuend);
4183 ir_node *right = get_irn_n(node, n_ia32_l_Sub_subtrahend);
4184 ir_node *lowered = gen_binop(node, left, right, new_bd_ia32_Sub,
4185 match_am | match_immediate | match_mode_neutral);
4187 if (is_Proj(lowered)) {
4188 lowered = get_Proj_pred(lowered);
4190 assert(is_ia32_Sub(lowered));
4191 set_irn_mode(lowered, mode_T);
4197 static ir_node *gen_ia32_l_Sbb(ir_node *node)
4199 return gen_binop_flags(node, new_bd_ia32_Sbb,
4200 match_am | match_immediate | match_mode_neutral);
4203 static ir_node *gen_ia32_l_LLtoFloat(ir_node *node)
4205 ir_node *src_block = get_nodes_block(node);
4206 ir_node *block = be_transform_node(src_block);
4207 ir_graph *irg = current_ir_graph;
4208 dbg_info *dbgi = get_irn_dbg_info(node);
4209 ir_node *frame = get_irg_frame(irg);
4210 ir_node *val_low = get_irn_n(node, n_ia32_l_LLtoFloat_val_low);
4211 ir_node *val_high = get_irn_n(node, n_ia32_l_LLtoFloat_val_high);
4212 ir_node *new_val_low = be_transform_node(val_low);
4213 ir_node *new_val_high = be_transform_node(val_high);
4215 ir_node *sync, *fild, *res;
4217 ir_node *store_high;
4221 if (ia32_cg_config.use_sse2) {
4222 panic("not implemented for SSE2");
4226 store_low = new_bd_ia32_Store(dbgi, block, frame, noreg_GP, nomem,
4228 store_high = new_bd_ia32_Store(dbgi, block, frame, noreg_GP, nomem,
4230 SET_IA32_ORIG_NODE(store_low, node);
4231 SET_IA32_ORIG_NODE(store_high, node);
4233 mem_low = new_r_Proj(store_low, mode_M, pn_ia32_Store_M);
4234 mem_high = new_r_Proj(store_high, mode_M, pn_ia32_Store_M);
4236 set_ia32_use_frame(store_low);
4237 set_ia32_use_frame(store_high);
4238 set_ia32_op_type(store_low, ia32_AddrModeD);
4239 set_ia32_op_type(store_high, ia32_AddrModeD);
4240 set_ia32_ls_mode(store_low, mode_Iu);
4241 set_ia32_ls_mode(store_high, mode_Is);
4242 add_ia32_am_offs_int(store_high, 4);
4246 sync = new_rd_Sync(dbgi, block, 2, in);
4249 fild = new_bd_ia32_vfild(dbgi, block, frame, noreg_GP, sync);
4251 set_ia32_use_frame(fild);
4252 set_ia32_op_type(fild, ia32_AddrModeS);
4253 set_ia32_ls_mode(fild, mode_Ls);
4255 SET_IA32_ORIG_NODE(fild, node);
4257 res = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
4259 if (! mode_is_signed(get_irn_mode(val_high))) {
4260 ia32_address_mode_t am;
4262 ir_node *count = ia32_create_Immediate(NULL, 0, 31);
4265 am.addr.base = get_symconst_base();
4266 am.addr.index = new_bd_ia32_Shr(dbgi, block, new_val_high, count);
4267 am.addr.mem = nomem;
4270 am.addr.symconst_ent = ia32_gen_fp_known_const(ia32_ULLBIAS);
4271 am.addr.tls_segment = false;
4272 am.addr.use_frame = 0;
4273 am.addr.frame_entity = NULL;
4274 am.addr.symconst_sign = 0;
4275 am.ls_mode = mode_F;
4276 am.mem_proj = nomem;
4277 am.op_type = ia32_AddrModeS;
4279 am.new_op2 = ia32_new_NoReg_vfp(current_ir_graph);
4280 am.pinned = op_pin_state_floats;
4282 am.ins_permuted = false;
4284 fadd = new_bd_ia32_vfadd(dbgi, block, am.addr.base, am.addr.index, am.addr.mem,
4285 am.new_op1, am.new_op2, get_fpcw());
4286 set_am_attributes(fadd, &am);
4288 set_irn_mode(fadd, mode_T);
4289 res = new_rd_Proj(NULL, fadd, mode_vfp, pn_ia32_res);
4294 static ir_node *gen_ia32_l_FloattoLL(ir_node *node)
4296 ir_node *src_block = get_nodes_block(node);
4297 ir_node *block = be_transform_node(src_block);
4298 ir_graph *irg = get_Block_irg(block);
4299 dbg_info *dbgi = get_irn_dbg_info(node);
4300 ir_node *frame = get_irg_frame(irg);
4301 ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val);
4302 ir_node *new_val = be_transform_node(val);
4305 fist = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_val);
4306 SET_IA32_ORIG_NODE(fist, node);
4307 set_ia32_use_frame(fist);
4308 set_ia32_op_type(fist, ia32_AddrModeD);
4309 set_ia32_ls_mode(fist, mode_Ls);
4311 assert((long)pn_ia32_vfist_M == (long) pn_ia32_vfisttp_M);
4312 return new_r_Proj(fist, mode_M, pn_ia32_vfist_M);
4315 static ir_node *gen_Proj_l_FloattoLL(ir_node *node)
4317 ir_node *block = be_transform_node(get_nodes_block(node));
4318 ir_graph *irg = get_Block_irg(block);
4319 ir_node *pred = get_Proj_pred(node);
4320 ir_node *new_pred = be_transform_node(pred);
4321 ir_node *frame = get_irg_frame(irg);
4322 dbg_info *dbgi = get_irn_dbg_info(node);
4323 long pn = get_Proj_proj(node);
4328 load = new_bd_ia32_Load(dbgi, block, frame, noreg_GP, new_pred);
4329 SET_IA32_ORIG_NODE(load, node);
4330 set_ia32_use_frame(load);
4331 set_ia32_op_type(load, ia32_AddrModeS);
4332 set_ia32_ls_mode(load, mode_Iu);
4333 /* we need a 64bit stackslot (fist stores 64bit) even though we only load
4334 * 32 bit from it with this particular load */
4335 attr = get_ia32_attr(load);
4336 attr->data.need_64bit_stackent = 1;
4338 if (pn == pn_ia32_l_FloattoLL_res_high) {
4339 add_ia32_am_offs_int(load, 4);
4341 assert(pn == pn_ia32_l_FloattoLL_res_low);
4344 proj = new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
4350 * Transform the Projs of an AddSP.
4352 static ir_node *gen_Proj_be_AddSP(ir_node *node)
4354 ir_node *pred = get_Proj_pred(node);
4355 ir_node *new_pred = be_transform_node(pred);
4356 dbg_info *dbgi = get_irn_dbg_info(node);
4357 long proj = get_Proj_proj(node);
4359 if (proj == pn_be_AddSP_sp) {
4360 ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu,
4361 pn_ia32_SubSP_stack);
4362 arch_set_irn_register(res, &ia32_registers[REG_ESP]);
4364 } else if (proj == pn_be_AddSP_res) {
4365 return new_rd_Proj(dbgi, new_pred, mode_Iu,
4366 pn_ia32_SubSP_addr);
4367 } else if (proj == pn_be_AddSP_M) {
4368 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_SubSP_M);
4371 panic("No idea how to transform proj->AddSP");
4375 * Transform the Projs of a SubSP.
4377 static ir_node *gen_Proj_be_SubSP(ir_node *node)
4379 ir_node *pred = get_Proj_pred(node);
4380 ir_node *new_pred = be_transform_node(pred);
4381 dbg_info *dbgi = get_irn_dbg_info(node);
4382 long proj = get_Proj_proj(node);
4384 if (proj == pn_be_SubSP_sp) {
4385 ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu,
4386 pn_ia32_AddSP_stack);
4387 arch_set_irn_register(res, &ia32_registers[REG_ESP]);
4389 } else if (proj == pn_be_SubSP_M) {
4390 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_AddSP_M);
4393 panic("No idea how to transform proj->SubSP");
4397 * Transform and renumber the Projs from a Load.
4399 static ir_node *gen_Proj_Load(ir_node *node)
4402 ir_node *pred = get_Proj_pred(node);
4403 dbg_info *dbgi = get_irn_dbg_info(node);
4404 long proj = get_Proj_proj(node);
4406 /* loads might be part of source address mode matches, so we don't
4407 * transform the ProjMs yet (with the exception of loads whose result is
4410 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4413 /* this is needed, because sometimes we have loops that are only
4414 reachable through the ProjM */
4415 be_enqueue_preds(node);
4416 /* do it in 2 steps, to silence firm verifier */
4417 res = new_rd_Proj(dbgi, pred, mode_M, pn_Load_M);
4418 set_Proj_proj(res, pn_ia32_mem);
4422 /* renumber the proj */
4423 new_pred = be_transform_node(pred);
4424 if (is_ia32_Load(new_pred)) {
4425 switch ((pn_Load)proj) {
4427 return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Load_res);
4429 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Load_M);
4430 case pn_Load_X_except:
4431 /* This Load might raise an exception. Mark it. */
4432 set_ia32_exc_label(new_pred, 1);
4433 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_except);
4434 case pn_Load_X_regular:
4435 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_regular);
4437 } else if (is_ia32_Conv_I2I(new_pred) ||
4438 is_ia32_Conv_I2I8Bit(new_pred)) {
4439 set_irn_mode(new_pred, mode_T);
4440 switch ((pn_Load)proj) {
4442 return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_res);
4444 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_mem);
4445 case pn_Load_X_except:
4446 /* This Load might raise an exception. Mark it. */
4447 set_ia32_exc_label(new_pred, 1);
4448 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Conv_I2I_X_except);
4449 case pn_Load_X_regular:
4450 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Conv_I2I_X_regular);
4452 } else if (is_ia32_xLoad(new_pred)) {
4453 switch ((pn_Load)proj) {
4455 return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xLoad_res);
4457 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xLoad_M);
4458 case pn_Load_X_except:
4459 /* This Load might raise an exception. Mark it. */
4460 set_ia32_exc_label(new_pred, 1);
4461 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_except);
4462 case pn_Load_X_regular:
4463 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_regular);
4465 } else if (is_ia32_vfld(new_pred)) {
4466 switch ((pn_Load)proj) {
4468 return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfld_res);
4470 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfld_M);
4471 case pn_Load_X_except:
4472 /* This Load might raise an exception. Mark it. */
4473 set_ia32_exc_label(new_pred, 1);
4474 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_except);
4475 case pn_Load_X_regular:
4476 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_regular);
4479 /* can happen for ProJMs when source address mode happened for the
4482 /* however it should not be the result proj, as that would mean the
4483 load had multiple users and should not have been used for
4485 if (proj != pn_Load_M) {
4486 panic("internal error: transformed node not a Load");
4488 return new_rd_Proj(dbgi, new_pred, mode_M, 1);
4491 panic("No idea how to transform Proj(Load) %+F", node);
4494 static ir_node *gen_Proj_Store(ir_node *node)
4496 ir_node *pred = get_Proj_pred(node);
4497 ir_node *new_pred = be_transform_node(pred);
4498 dbg_info *dbgi = get_irn_dbg_info(node);
4499 long pn = get_Proj_proj(node);
4501 if (is_ia32_Store(new_pred) || is_ia32_Store8Bit(new_pred)) {
4502 switch ((pn_Store)pn) {
4504 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Store_M);
4505 case pn_Store_X_except:
4506 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Store_X_except);
4507 case pn_Store_X_regular:
4508 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Store_X_regular);
4510 } else if (is_ia32_vfist(new_pred)) {
4511 switch ((pn_Store)pn) {
4513 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfist_M);
4514 case pn_Store_X_except:
4515 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfist_X_except);
4516 case pn_Store_X_regular:
4517 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfist_X_regular);
4519 } else if (is_ia32_vfisttp(new_pred)) {
4520 switch ((pn_Store)pn) {
4522 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfisttp_M);
4523 case pn_Store_X_except:
4524 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfisttp_X_except);
4525 case pn_Store_X_regular:
4526 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfisttp_X_regular);
4528 } else if (is_ia32_vfst(new_pred)) {
4529 switch ((pn_Store)pn) {
4531 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfst_M);
4532 case pn_Store_X_except:
4533 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfst_X_except);
4534 case pn_Store_X_regular:
4535 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfst_X_regular);
4537 } else if (is_ia32_xStore(new_pred)) {
4538 switch ((pn_Store)pn) {
4540 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xStore_M);
4541 case pn_Store_X_except:
4542 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xStore_X_except);
4543 case pn_Store_X_regular:
4544 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xStore_X_regular);
4546 } else if (is_Sync(new_pred)) {
4547 /* hack for the case that gen_float_const_Store produced a Sync */
4548 if (pn == pn_Store_M) {
4551 panic("exception control flow not implemented yet");
4552 } else if (get_ia32_op_type(new_pred) == ia32_AddrModeD) {
4553 /* destination address mode */
4554 if (pn == pn_Store_M) {
4557 panic("exception control flow for destination AM not implemented yet");
4560 panic("No idea how to transform Proj(Store) %+F", node);
4564 * Transform and renumber the Projs from a Div or Mod instruction.
4566 static ir_node *gen_Proj_Div(ir_node *node)
4568 ir_node *pred = get_Proj_pred(node);
4569 ir_node *new_pred = be_transform_node(pred);
4570 dbg_info *dbgi = get_irn_dbg_info(node);
4571 long proj = get_Proj_proj(node);
4573 assert((long)pn_ia32_Div_M == (long)pn_ia32_IDiv_M);
4574 assert((long)pn_ia32_Div_div_res == (long)pn_ia32_IDiv_div_res);
4576 switch ((pn_Div)proj) {
4578 if (is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)) {
4579 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M);
4580 } else if (is_ia32_xDiv(new_pred)) {
4581 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xDiv_M);
4582 } else if (is_ia32_vfdiv(new_pred)) {
4583 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfdiv_M);
4585 panic("Div transformed to unexpected thing %+F", new_pred);
4588 if (is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)) {
4589 return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_div_res);
4590 } else if (is_ia32_xDiv(new_pred)) {
4591 return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xDiv_res);
4592 } else if (is_ia32_vfdiv(new_pred)) {
4593 return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4595 panic("Div transformed to unexpected thing %+F", new_pred);
4597 case pn_Div_X_except:
4598 set_ia32_exc_label(new_pred, 1);
4599 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_except);
4600 case pn_Div_X_regular:
4601 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_regular);
4604 panic("No idea how to transform proj->Div");
4608 * Transform and renumber the Projs from a Div or Mod instruction.
4610 static ir_node *gen_Proj_Mod(ir_node *node)
4612 ir_node *pred = get_Proj_pred(node);
4613 ir_node *new_pred = be_transform_node(pred);
4614 dbg_info *dbgi = get_irn_dbg_info(node);
4615 long proj = get_Proj_proj(node);
4617 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4618 assert((long)pn_ia32_Div_M == (long)pn_ia32_IDiv_M);
4619 assert((long)pn_ia32_Div_mod_res == (long)pn_ia32_IDiv_mod_res);
4621 switch ((pn_Mod)proj) {
4623 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M);
4625 return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4626 case pn_Mod_X_except:
4627 set_ia32_exc_label(new_pred, 1);
4628 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_except);
4629 case pn_Mod_X_regular:
4630 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_regular);
4632 panic("No idea how to transform proj->Mod");
4636 * Transform and renumber the Projs from a CopyB.
4638 static ir_node *gen_Proj_CopyB(ir_node *node)
4640 ir_node *pred = get_Proj_pred(node);
4641 ir_node *new_pred = be_transform_node(pred);
4642 dbg_info *dbgi = get_irn_dbg_info(node);
4643 long proj = get_Proj_proj(node);
4645 switch ((pn_CopyB)proj) {
4647 if (is_ia32_CopyB_i(new_pred)) {
4648 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_i_M);
4649 } else if (is_ia32_CopyB(new_pred)) {
4650 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_M);
4653 case pn_CopyB_X_regular:
4654 if (is_ia32_CopyB_i(new_pred)) {
4655 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_i_X_regular);
4656 } else if (is_ia32_CopyB(new_pred)) {
4657 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_X_regular);
4660 case pn_CopyB_X_except:
4661 if (is_ia32_CopyB_i(new_pred)) {
4662 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_i_X_except);
4663 } else if (is_ia32_CopyB(new_pred)) {
4664 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_X_except);
4669 panic("No idea how to transform proj->CopyB");
4672 static ir_node *gen_be_Call(ir_node *node)
4674 dbg_info *const dbgi = get_irn_dbg_info(node);
4675 ir_node *const src_block = get_nodes_block(node);
4676 ir_node *const block = be_transform_node(src_block);
4677 ir_node *const src_mem = get_irn_n(node, n_be_Call_mem);
4678 ir_node *const src_sp = get_irn_n(node, n_be_Call_sp);
4679 ir_node *const sp = be_transform_node(src_sp);
4680 ir_node *const src_ptr = get_irn_n(node, n_be_Call_ptr);
4681 ia32_address_mode_t am;
4682 ia32_address_t *const addr = &am.addr;
4687 ir_node * eax = noreg_GP;
4688 ir_node * ecx = noreg_GP;
4689 ir_node * edx = noreg_GP;
4690 unsigned const pop = be_Call_get_pop(node);
4691 ir_type *const call_tp = be_Call_get_type(node);
4692 int old_no_pic_adjust;
4693 int throws_exception = ir_throws_exception(node);
4695 /* Run the x87 simulator if the call returns a float value */
4696 if (get_method_n_ress(call_tp) > 0) {
4697 ir_type *const res_type = get_method_res_type(call_tp, 0);
4698 ir_mode *const res_mode = get_type_mode(res_type);
4700 if (res_mode != NULL && mode_is_float(res_mode)) {
4701 ir_graph *irg = current_ir_graph;
4702 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
4703 irg_data->do_x87_sim = 1;
4707 /* We do not want be_Call direct calls */
4708 assert(be_Call_get_entity(node) == NULL);
4710 /* special case for PIC trampoline calls */
4711 old_no_pic_adjust = ia32_no_pic_adjust;
4712 ia32_no_pic_adjust = be_options.pic;
4714 match_arguments(&am, src_block, NULL, src_ptr, src_mem,
4715 match_am | match_immediate | match_upconv);
4717 ia32_no_pic_adjust = old_no_pic_adjust;
4719 i = get_irn_arity(node) - 1;
4720 fpcw = be_transform_node(get_irn_n(node, i--));
4721 for (; i >= n_be_Call_first_arg; --i) {
4722 arch_register_req_t const *const req
4723 = arch_get_irn_register_req_in(node, i);
4724 ir_node *const reg_parm = be_transform_node(get_irn_n(node, i));
4726 assert(req->type == arch_register_req_type_limited);
4727 assert(req->cls == &ia32_reg_classes[CLASS_ia32_gp]);
4729 switch (*req->limited) {
4730 case 1 << REG_GP_EAX: assert(eax == noreg_GP); eax = reg_parm; break;
4731 case 1 << REG_GP_ECX: assert(ecx == noreg_GP); ecx = reg_parm; break;
4732 case 1 << REG_GP_EDX: assert(edx == noreg_GP); edx = reg_parm; break;
4733 default: panic("Invalid GP register for register parameter");
4737 mem = transform_AM_mem(block, src_ptr, src_mem, addr->mem);
4738 call = new_bd_ia32_Call(dbgi, block, addr->base, addr->index, mem,
4739 am.new_op2, sp, fpcw, eax, ecx, edx, pop, call_tp);
4740 ir_set_throws_exception(call, throws_exception);
4741 set_am_attributes(call, &am);
4742 call = fix_mem_proj(call, &am);
4744 if (get_irn_pinned(node) == op_pin_state_pinned)
4745 set_irn_pinned(call, op_pin_state_pinned);
4747 SET_IA32_ORIG_NODE(call, node);
4749 if (ia32_cg_config.use_sse2) {
4750 /* remember this call for post-processing */
4751 ARR_APP1(ir_node *, call_list, call);
4752 ARR_APP1(ir_type *, call_types, be_Call_get_type(node));
4759 * Transform Builtin trap
4761 static ir_node *gen_trap(ir_node *node)
4763 dbg_info *dbgi = get_irn_dbg_info(node);
4764 ir_node *block = be_transform_node(get_nodes_block(node));
4765 ir_node *mem = be_transform_node(get_Builtin_mem(node));
4767 return new_bd_ia32_UD2(dbgi, block, mem);
4771 * Transform Builtin debugbreak
4773 static ir_node *gen_debugbreak(ir_node *node)
4775 dbg_info *dbgi = get_irn_dbg_info(node);
4776 ir_node *block = be_transform_node(get_nodes_block(node));
4777 ir_node *mem = be_transform_node(get_Builtin_mem(node));
4779 return new_bd_ia32_Breakpoint(dbgi, block, mem);
4783 * Transform Builtin return_address
4785 static ir_node *gen_return_address(ir_node *node)
4787 ir_node *param = get_Builtin_param(node, 0);
4788 ir_node *frame = get_Builtin_param(node, 1);
4789 dbg_info *dbgi = get_irn_dbg_info(node);
4790 ir_tarval *tv = get_Const_tarval(param);
4791 ir_graph *irg = get_irn_irg(node);
4792 unsigned long value = get_tarval_long(tv);
4794 ir_node *block = be_transform_node(get_nodes_block(node));
4795 ir_node *ptr = be_transform_node(frame);
4799 ir_node *cnt = new_bd_ia32_ProduceVal(dbgi, block);
4800 ir_node *res = new_bd_ia32_ProduceVal(dbgi, block);
4801 ptr = new_bd_ia32_ClimbFrame(dbgi, block, ptr, cnt, res, value);
4804 /* load the return address from this frame */
4805 load = new_bd_ia32_Load(dbgi, block, ptr, noreg_GP, nomem);
4807 set_irn_pinned(load, get_irn_pinned(node));
4808 set_ia32_op_type(load, ia32_AddrModeS);
4809 set_ia32_ls_mode(load, mode_Iu);
4811 set_ia32_am_offs_int(load, 0);
4812 set_ia32_use_frame(load);
4813 set_ia32_frame_ent(load, ia32_get_return_address_entity(irg));
4815 if (get_irn_pinned(node) == op_pin_state_floats) {
4816 assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
4817 && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
4818 && (int)pn_ia32_Load_res == (int)pn_ia32_res);
4819 arch_add_irn_flags(load, arch_irn_flags_rematerializable);
4822 SET_IA32_ORIG_NODE(load, node);
4823 return new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
4827 * Transform Builtin frame_address
4829 static ir_node *gen_frame_address(ir_node *node)
4831 ir_node *param = get_Builtin_param(node, 0);
4832 ir_node *frame = get_Builtin_param(node, 1);
4833 dbg_info *dbgi = get_irn_dbg_info(node);
4834 ir_tarval *tv = get_Const_tarval(param);
4835 ir_graph *irg = get_irn_irg(node);
4836 unsigned long value = get_tarval_long(tv);
4838 ir_node *block = be_transform_node(get_nodes_block(node));
4839 ir_node *ptr = be_transform_node(frame);
4844 ir_node *cnt = new_bd_ia32_ProduceVal(dbgi, block);
4845 ir_node *res = new_bd_ia32_ProduceVal(dbgi, block);
4846 ptr = new_bd_ia32_ClimbFrame(dbgi, block, ptr, cnt, res, value);
4849 /* load the frame address from this frame */
4850 load = new_bd_ia32_Load(dbgi, block, ptr, noreg_GP, nomem);
4852 set_irn_pinned(load, get_irn_pinned(node));
4853 set_ia32_op_type(load, ia32_AddrModeS);
4854 set_ia32_ls_mode(load, mode_Iu);
4856 ent = ia32_get_frame_address_entity(irg);
4858 set_ia32_am_offs_int(load, 0);
4859 set_ia32_use_frame(load);
4860 set_ia32_frame_ent(load, ent);
4862 /* will fail anyway, but gcc does this: */
4863 set_ia32_am_offs_int(load, 0);
4866 if (get_irn_pinned(node) == op_pin_state_floats) {
4867 assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
4868 && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
4869 && (int)pn_ia32_Load_res == (int)pn_ia32_res);
4870 arch_add_irn_flags(load, arch_irn_flags_rematerializable);
4873 SET_IA32_ORIG_NODE(load, node);
4874 return new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
4878 * Transform Builtin frame_address
4880 static ir_node *gen_prefetch(ir_node *node)
4883 ir_node *ptr, *block, *mem, *base, *idx;
4884 ir_node *param, *new_node;
4887 ia32_address_t addr;
4889 if (!ia32_cg_config.use_sse_prefetch && !ia32_cg_config.use_3dnow_prefetch) {
4890 /* no prefetch at all, route memory */
4891 return be_transform_node(get_Builtin_mem(node));
4894 param = get_Builtin_param(node, 1);
4895 tv = get_Const_tarval(param);
4896 rw = get_tarval_long(tv);
4898 /* construct load address */
4899 memset(&addr, 0, sizeof(addr));
4900 ptr = get_Builtin_param(node, 0);
4901 ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
4908 base = be_transform_node(base);
4914 idx = be_transform_node(idx);
4917 dbgi = get_irn_dbg_info(node);
4918 block = be_transform_node(get_nodes_block(node));
4919 mem = be_transform_node(get_Builtin_mem(node));
4921 if (rw == 1 && ia32_cg_config.use_3dnow_prefetch) {
4922 /* we have 3DNow!, this was already checked above */
4923 new_node = new_bd_ia32_PrefetchW(dbgi, block, base, idx, mem);
4924 } else if (ia32_cg_config.use_sse_prefetch) {
4925 /* note: rw == 1 is IGNORED in that case */
4926 param = get_Builtin_param(node, 2);
4927 tv = get_Const_tarval(param);
4928 locality = get_tarval_long(tv);
4930 /* SSE style prefetch */
4933 new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, idx, mem);
4936 new_node = new_bd_ia32_Prefetch2(dbgi, block, base, idx, mem);
4939 new_node = new_bd_ia32_Prefetch1(dbgi, block, base, idx, mem);
4942 new_node = new_bd_ia32_Prefetch0(dbgi, block, base, idx, mem);
4946 assert(ia32_cg_config.use_3dnow_prefetch);
4947 /* 3DNow! style prefetch */
4948 new_node = new_bd_ia32_Prefetch(dbgi, block, base, idx, mem);
4951 set_irn_pinned(new_node, get_irn_pinned(node));
4952 set_ia32_op_type(new_node, ia32_AddrModeS);
4953 set_ia32_ls_mode(new_node, mode_Bu);
4954 set_address(new_node, &addr);
4956 SET_IA32_ORIG_NODE(new_node, node);
4958 return new_r_Proj(new_node, mode_M, pn_ia32_Prefetch_M);
4962 * Transform bsf like node
4964 static ir_node *gen_unop_AM(ir_node *node, construct_binop_dest_func *func)
4966 ir_node *param = get_Builtin_param(node, 0);
4967 dbg_info *dbgi = get_irn_dbg_info(node);
4969 ir_node *block = get_nodes_block(node);
4970 ir_node *new_block = be_transform_node(block);
4972 ia32_address_mode_t am;
4973 ia32_address_t *addr = &am.addr;
4976 match_arguments(&am, block, NULL, param, NULL, match_am);
4978 cnt = func(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2);
4979 set_am_attributes(cnt, &am);
4980 set_ia32_ls_mode(cnt, get_irn_mode(param));
4982 SET_IA32_ORIG_NODE(cnt, node);
4983 return fix_mem_proj(cnt, &am);
4987 * Transform builtin ffs.
4989 static ir_node *gen_ffs(ir_node *node)
4991 ir_node *bsf = gen_unop_AM(node, new_bd_ia32_Bsf);
4992 ir_node *real = skip_Proj(bsf);
4993 dbg_info *dbgi = get_irn_dbg_info(real);
4994 ir_node *block = get_nodes_block(real);
4995 ir_node *flag, *set, *conv, *neg, *orn, *add;
4998 if (get_irn_mode(real) != mode_T) {
4999 set_irn_mode(real, mode_T);
5000 bsf = new_r_Proj(real, mode_Iu, pn_ia32_res);
5003 flag = new_r_Proj(real, mode_b, pn_ia32_flags);
5006 set = new_bd_ia32_Setcc(dbgi, block, flag, ia32_cc_equal);
5007 SET_IA32_ORIG_NODE(set, node);
5010 conv = new_bd_ia32_Conv_I2I8Bit(dbgi, block, noreg_GP, noreg_GP, nomem, set, mode_Bu);
5011 SET_IA32_ORIG_NODE(conv, node);
5014 neg = new_bd_ia32_Neg(dbgi, block, conv);
5017 orn = new_bd_ia32_Or(dbgi, block, noreg_GP, noreg_GP, nomem, bsf, neg);
5018 set_ia32_ls_mode(orn, mode_Iu);
5019 set_ia32_commutative(orn);
5022 add = new_bd_ia32_Lea(dbgi, block, orn, noreg_GP);
5023 add_ia32_am_offs_int(add, 1);
5028 * Transform builtin clz.
5030 static ir_node *gen_clz(ir_node *node)
5032 ir_node *bsr = gen_unop_AM(node, new_bd_ia32_Bsr);
5033 ir_node *real = skip_Proj(bsr);
5034 dbg_info *dbgi = get_irn_dbg_info(real);
5035 ir_node *block = get_nodes_block(real);
5036 ir_node *imm = ia32_create_Immediate(NULL, 0, 31);
5038 return new_bd_ia32_Xor(dbgi, block, noreg_GP, noreg_GP, nomem, bsr, imm);
5042 * Transform builtin ctz.
5044 static ir_node *gen_ctz(ir_node *node)
5046 return gen_unop_AM(node, new_bd_ia32_Bsf);
5050 * Transform builtin parity.
5052 static ir_node *gen_parity(ir_node *node)
5054 dbg_info *dbgi = get_irn_dbg_info(node);
5055 ir_node *block = get_nodes_block(node);
5056 ir_node *new_block = be_transform_node(block);
5057 ir_node *param = get_Builtin_param(node, 0);
5058 ir_node *new_param = be_transform_node(param);
5061 /* the x86 parity bit is stupid: it only looks at the lowest byte,
5062 * so we have to do complicated xoring first.
5063 * (we should also better lower this before the backend so we still have a
5064 * chance for CSE, constant folding and other goodies for some of these
5067 ir_node *count = ia32_create_Immediate(NULL, 0, 16);
5068 ir_node *shr = new_bd_ia32_Shr(dbgi, new_block, new_param, count);
5069 ir_node *xorn = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, nomem,
5071 ir_node *xor2 = new_bd_ia32_XorHighLow(dbgi, new_block, xorn);
5074 set_ia32_ls_mode(xorn, mode_Iu);
5075 set_ia32_commutative(xorn);
5077 set_irn_mode(xor2, mode_T);
5078 flags = new_r_Proj(xor2, mode_Iu, pn_ia32_XorHighLow_flags);
5081 new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, ia32_cc_not_parity);
5082 SET_IA32_ORIG_NODE(new_node, node);
5085 new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP,
5086 nomem, new_node, mode_Bu);
5087 SET_IA32_ORIG_NODE(new_node, node);
5092 * Transform builtin popcount
5094 static ir_node *gen_popcount(ir_node *node)
5096 ir_node *param = get_Builtin_param(node, 0);
5097 dbg_info *dbgi = get_irn_dbg_info(node);
5099 ir_node *block = get_nodes_block(node);
5100 ir_node *new_block = be_transform_node(block);
5103 ir_node *imm, *simm, *m1, *s1, *s2, *s3, *s4, *s5, *m2, *m3, *m4, *m5, *m6, *m7, *m8, *m9, *m10, *m11, *m12, *m13;
5105 /* check for SSE4.2 or SSE4a and use the popcnt instruction */
5106 if (ia32_cg_config.use_popcnt) {
5107 ia32_address_mode_t am;
5108 ia32_address_t *addr = &am.addr;
5111 match_arguments(&am, block, NULL, param, NULL, match_am | match_16bit_am | match_upconv);
5113 cnt = new_bd_ia32_Popcnt(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2);
5114 set_am_attributes(cnt, &am);
5115 set_ia32_ls_mode(cnt, get_irn_mode(param));
5117 SET_IA32_ORIG_NODE(cnt, node);
5118 return fix_mem_proj(cnt, &am);
5121 new_param = be_transform_node(param);
5123 /* do the standard popcount algo */
5124 /* TODO: This is stupid, we should transform this before the backend,
5125 * to get CSE, localopts, etc. for the operations
5126 * TODO: This is also not the optimal algorithm (it is just the starting
5127 * example in hackers delight, they optimize it more on the following page)
5128 * But I'm too lazy to fix this now, as the code should get lowered before
5129 * the backend anyway.
5132 /* m1 = x & 0x55555555 */
5133 imm = ia32_create_Immediate(NULL, 0, 0x55555555);
5134 m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_param, imm);
5137 simm = ia32_create_Immediate(NULL, 0, 1);
5138 s1 = new_bd_ia32_Shr(dbgi, new_block, new_param, simm);
5140 /* m2 = s1 & 0x55555555 */
5141 m2 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s1, imm);
5144 m3 = new_bd_ia32_Lea(dbgi, new_block, m2, m1);
5146 /* m4 = m3 & 0x33333333 */
5147 imm = ia32_create_Immediate(NULL, 0, 0x33333333);
5148 m4 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m3, imm);
5151 simm = ia32_create_Immediate(NULL, 0, 2);
5152 s2 = new_bd_ia32_Shr(dbgi, new_block, m3, simm);
5154 /* m5 = s2 & 0x33333333 */
5155 m5 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, imm);
5158 m6 = new_bd_ia32_Lea(dbgi, new_block, m4, m5);
5160 /* m7 = m6 & 0x0F0F0F0F */
5161 imm = ia32_create_Immediate(NULL, 0, 0x0F0F0F0F);
5162 m7 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m6, imm);
5165 simm = ia32_create_Immediate(NULL, 0, 4);
5166 s3 = new_bd_ia32_Shr(dbgi, new_block, m6, simm);
5168 /* m8 = s3 & 0x0F0F0F0F */
5169 m8 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, imm);
5172 m9 = new_bd_ia32_Lea(dbgi, new_block, m7, m8);
5174 /* m10 = m9 & 0x00FF00FF */
5175 imm = ia32_create_Immediate(NULL, 0, 0x00FF00FF);
5176 m10 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m9, imm);
5179 simm = ia32_create_Immediate(NULL, 0, 8);
5180 s4 = new_bd_ia32_Shr(dbgi, new_block, m9, simm);
5182 /* m11 = s4 & 0x00FF00FF */
5183 m11 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s4, imm);
5185 /* m12 = m10 + m11 */
5186 m12 = new_bd_ia32_Lea(dbgi, new_block, m10, m11);
5188 /* m13 = m12 & 0x0000FFFF */
5189 imm = ia32_create_Immediate(NULL, 0, 0x0000FFFF);
5190 m13 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m12, imm);
5192 /* s5 = m12 >> 16 */
5193 simm = ia32_create_Immediate(NULL, 0, 16);
5194 s5 = new_bd_ia32_Shr(dbgi, new_block, m12, simm);
5196 /* res = m13 + s5 */
5197 return new_bd_ia32_Lea(dbgi, new_block, m13, s5);
5201 * Transform builtin byte swap.
5203 static ir_node *gen_bswap(ir_node *node)
5205 ir_node *param = be_transform_node(get_Builtin_param(node, 0));
5206 dbg_info *dbgi = get_irn_dbg_info(node);
5208 ir_node *block = get_nodes_block(node);
5209 ir_node *new_block = be_transform_node(block);
5210 ir_mode *mode = get_irn_mode(param);
5211 unsigned size = get_mode_size_bits(mode);
5215 if (ia32_cg_config.use_bswap) {
5216 /* swap available */
5217 return new_bd_ia32_Bswap(dbgi, new_block, param);
5219 ir_node *i8 = ia32_create_Immediate(NULL, 0, 8);
5220 ir_node *rol1 = new_bd_ia32_Rol(dbgi, new_block, param, i8);
5221 ir_node *i16 = ia32_create_Immediate(NULL, 0, 16);
5222 ir_node *rol2 = new_bd_ia32_Rol(dbgi, new_block, rol1, i16);
5223 ir_node *rol3 = new_bd_ia32_Rol(dbgi, new_block, rol2, i8);
5224 set_ia32_ls_mode(rol1, mode_Hu);
5225 set_ia32_ls_mode(rol2, mode_Iu);
5226 set_ia32_ls_mode(rol3, mode_Hu);
5231 /* swap16 always available */
5232 return new_bd_ia32_Bswap16(dbgi, new_block, param);
5235 panic("Invalid bswap size (%d)", size);
5240 * Transform builtin outport.
5242 static ir_node *gen_outport(ir_node *node)
5244 ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0);
5245 ir_node *oldv = get_Builtin_param(node, 1);
5246 ir_mode *mode = get_irn_mode(oldv);
5247 ir_node *value = be_transform_node(oldv);
5248 ir_node *block = be_transform_node(get_nodes_block(node));
5249 ir_node *mem = be_transform_node(get_Builtin_mem(node));
5250 dbg_info *dbgi = get_irn_dbg_info(node);
5252 ir_node *res = new_bd_ia32_Outport(dbgi, block, port, value, mem);
5253 set_ia32_ls_mode(res, mode);
5258 * Transform builtin inport.
5260 static ir_node *gen_inport(ir_node *node)
5262 ir_type *tp = get_Builtin_type(node);
5263 ir_type *rstp = get_method_res_type(tp, 0);
5264 ir_mode *mode = get_type_mode(rstp);
5265 ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0);
5266 ir_node *block = be_transform_node(get_nodes_block(node));
5267 ir_node *mem = be_transform_node(get_Builtin_mem(node));
5268 dbg_info *dbgi = get_irn_dbg_info(node);
5270 ir_node *res = new_bd_ia32_Inport(dbgi, block, port, mem);
5271 set_ia32_ls_mode(res, mode);
5273 /* check for missing Result Proj */
5278 * Transform a builtin inner trampoline
5280 static ir_node *gen_inner_trampoline(ir_node *node)
5282 ir_node *ptr = get_Builtin_param(node, 0);
5283 ir_node *callee = get_Builtin_param(node, 1);
5284 ir_node *env = be_transform_node(get_Builtin_param(node, 2));
5285 ir_node *mem = get_Builtin_mem(node);
5286 ir_node *block = get_nodes_block(node);
5287 ir_node *new_block = be_transform_node(block);
5291 ir_node *trampoline;
5293 dbg_info *dbgi = get_irn_dbg_info(node);
5294 ia32_address_t addr;
5296 /* construct store address */
5297 memset(&addr, 0, sizeof(addr));
5298 ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
5300 if (addr.base == NULL) {
5301 addr.base = noreg_GP;
5303 addr.base = be_transform_node(addr.base);
5306 if (addr.index == NULL) {
5307 addr.index = noreg_GP;
5309 addr.index = be_transform_node(addr.index);
5311 addr.mem = be_transform_node(mem);
5313 /* mov ecx, <env> */
5314 val = ia32_create_Immediate(NULL, 0, 0xB9);
5315 store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
5316 addr.index, addr.mem, val);
5317 set_irn_pinned(store, get_irn_pinned(node));
5318 set_ia32_op_type(store, ia32_AddrModeD);
5319 set_ia32_ls_mode(store, mode_Bu);
5320 set_address(store, &addr);
5324 store = new_bd_ia32_Store(dbgi, new_block, addr.base,
5325 addr.index, addr.mem, env);
5326 set_irn_pinned(store, get_irn_pinned(node));
5327 set_ia32_op_type(store, ia32_AddrModeD);
5328 set_ia32_ls_mode(store, mode_Iu);
5329 set_address(store, &addr);
5333 /* jmp rel <callee> */
5334 val = ia32_create_Immediate(NULL, 0, 0xE9);
5335 store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
5336 addr.index, addr.mem, val);
5337 set_irn_pinned(store, get_irn_pinned(node));
5338 set_ia32_op_type(store, ia32_AddrModeD);
5339 set_ia32_ls_mode(store, mode_Bu);
5340 set_address(store, &addr);
5344 trampoline = be_transform_node(ptr);
5346 /* the callee is typically an immediate */
5347 if (is_SymConst(callee)) {
5348 rel = new_bd_ia32_Const(dbgi, new_block, get_SymConst_entity(callee), 0, 0, -10);
5350 rel = new_bd_ia32_Lea(dbgi, new_block, be_transform_node(callee), noreg_GP);
5351 add_ia32_am_offs_int(rel, -10);
5353 rel = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, nomem, rel, trampoline);
5355 store = new_bd_ia32_Store(dbgi, new_block, addr.base,
5356 addr.index, addr.mem, rel);
5357 set_irn_pinned(store, get_irn_pinned(node));
5358 set_ia32_op_type(store, ia32_AddrModeD);
5359 set_ia32_ls_mode(store, mode_Iu);
5360 set_address(store, &addr);
5365 return new_r_Tuple(new_block, 2, in);
5369 * Transform Builtin node.
5371 static ir_node *gen_Builtin(ir_node *node)
5373 ir_builtin_kind kind = get_Builtin_kind(node);
5377 return gen_trap(node);
5378 case ir_bk_debugbreak:
5379 return gen_debugbreak(node);
5380 case ir_bk_return_address:
5381 return gen_return_address(node);
5382 case ir_bk_frame_address:
5383 return gen_frame_address(node);
5384 case ir_bk_prefetch:
5385 return gen_prefetch(node);
5387 return gen_ffs(node);
5389 return gen_clz(node);
5391 return gen_ctz(node);
5393 return gen_parity(node);
5394 case ir_bk_popcount:
5395 return gen_popcount(node);
5397 return gen_bswap(node);
5399 return gen_outport(node);
5401 return gen_inport(node);
5402 case ir_bk_inner_trampoline:
5403 return gen_inner_trampoline(node);
5405 panic("Builtin %s not implemented", get_builtin_kind_name(kind));
5409 * Transform Proj(Builtin) node.
5411 static ir_node *gen_Proj_Builtin(ir_node *proj)
5413 ir_node *node = get_Proj_pred(proj);
5414 ir_node *new_node = be_transform_node(node);
5415 ir_builtin_kind kind = get_Builtin_kind(node);
5418 case ir_bk_return_address:
5419 case ir_bk_frame_address:
5424 case ir_bk_popcount:
5426 assert(get_Proj_proj(proj) == pn_Builtin_max+1);
5429 case ir_bk_debugbreak:
5430 case ir_bk_prefetch:
5432 assert(get_Proj_proj(proj) == pn_Builtin_M);
5435 if (get_Proj_proj(proj) == pn_Builtin_max+1) {
5436 return new_r_Proj(new_node, get_irn_mode(proj), pn_ia32_Inport_res);
5438 assert(get_Proj_proj(proj) == pn_Builtin_M);
5439 return new_r_Proj(new_node, mode_M, pn_ia32_Inport_M);
5441 case ir_bk_inner_trampoline:
5442 if (get_Proj_proj(proj) == pn_Builtin_max+1) {
5443 return get_Tuple_pred(new_node, 1);
5445 assert(get_Proj_proj(proj) == pn_Builtin_M);
5446 return get_Tuple_pred(new_node, 0);
5449 panic("Builtin %s not implemented", get_builtin_kind_name(kind));
5452 static ir_node *gen_be_IncSP(ir_node *node)
5454 ir_node *res = be_duplicate_node(node);
5455 arch_add_irn_flags(res, arch_irn_flags_modify_flags);
5461 * Transform the Projs from a be_Call.
5463 static ir_node *gen_Proj_be_Call(ir_node *node)
5465 ir_node *call = get_Proj_pred(node);
5466 ir_node *new_call = be_transform_node(call);
5467 dbg_info *dbgi = get_irn_dbg_info(node);
5468 long proj = get_Proj_proj(node);
5469 ir_mode *mode = get_irn_mode(node);
5472 if (proj == pn_be_Call_M) {
5473 return new_rd_Proj(dbgi, new_call, mode_M, n_ia32_Call_mem);
5475 /* transform call modes */
5476 if (mode_is_data(mode)) {
5477 const arch_register_class_t *cls = arch_get_irn_reg_class(node);
5481 /* Map from be_Call to ia32_Call proj number */
5482 if (proj == pn_be_Call_sp) {
5483 proj = pn_ia32_Call_stack;
5484 } else if (proj == pn_be_Call_M) {
5485 proj = pn_ia32_Call_M;
5486 } else if (proj == pn_be_Call_X_except) {
5487 proj = pn_ia32_Call_X_except;
5488 } else if (proj == pn_be_Call_X_regular) {
5489 proj = pn_ia32_Call_X_regular;
5491 arch_register_req_t const *const req = arch_get_irn_register_req(node);
5492 int const n_outs = arch_get_irn_n_outs(new_call);
5495 assert(proj >= pn_be_Call_first_res);
5496 assert(req->type & arch_register_req_type_limited);
5498 for (i = 0; i < n_outs; ++i) {
5499 arch_register_req_t const *const new_req
5500 = arch_get_irn_register_req_out(new_call, i);
5502 if (!(new_req->type & arch_register_req_type_limited) ||
5503 new_req->cls != req->cls ||
5504 *new_req->limited != *req->limited)
5513 res = new_rd_Proj(dbgi, new_call, mode, proj);
5515 /* TODO arch_set_irn_register() only operates on Projs, need variant with index */
5517 case pn_ia32_Call_stack:
5518 arch_set_irn_register(res, &ia32_registers[REG_ESP]);
5521 case pn_ia32_Call_fpcw:
5522 arch_set_irn_register(res, &ia32_registers[REG_FPCW]);
5529 static ir_node *gen_Proj_ASM(ir_node *node)
5531 ir_mode *mode = get_irn_mode(node);
5532 ir_node *pred = get_Proj_pred(node);
5533 ir_node *new_pred = be_transform_node(pred);
5534 long pos = get_Proj_proj(node);
5536 if (mode == mode_M) {
5537 pos = arch_get_irn_n_outs(new_pred)-1;
5538 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
5540 } else if (mode_is_float(mode)) {
5543 panic("unexpected proj mode at ASM");
5546 return new_r_Proj(new_pred, mode, pos);
5550 * Transform and potentially renumber Proj nodes.
5552 static ir_node *gen_Proj(ir_node *node)
5554 ir_node *pred = get_Proj_pred(node);
5557 switch (get_irn_opcode(pred)) {
5559 return gen_Proj_Load(node);
5561 return gen_Proj_Store(node);
5563 return gen_Proj_ASM(node);
5565 return gen_Proj_Builtin(node);
5567 return gen_Proj_Div(node);
5569 return gen_Proj_Mod(node);
5571 return gen_Proj_CopyB(node);
5573 return gen_Proj_be_SubSP(node);
5575 return gen_Proj_be_AddSP(node);
5577 return gen_Proj_be_Call(node);
5579 proj = get_Proj_proj(node);
5581 case pn_Start_X_initial_exec: {
5582 ir_node *block = get_nodes_block(pred);
5583 ir_node *new_block = be_transform_node(block);
5584 dbg_info *dbgi = get_irn_dbg_info(node);
5585 /* we exchange the ProjX with a jump */
5586 ir_node *jump = new_rd_Jmp(dbgi, new_block);
5594 if (is_ia32_l_FloattoLL(pred)) {
5595 return gen_Proj_l_FloattoLL(node);
5597 } else if (!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
5601 ir_mode *mode = get_irn_mode(node);
5602 if (ia32_mode_needs_gp_reg(mode)) {
5603 ir_node *new_pred = be_transform_node(pred);
5604 ir_node *new_proj = new_r_Proj(new_pred, mode_Iu,
5605 get_Proj_proj(node));
5606 new_proj->node_nr = node->node_nr;
5611 return be_duplicate_node(node);
5615 * Enters all transform functions into the generic pointer
5617 static void register_transformers(void)
5619 /* first clear the generic function pointer for all ops */
5620 be_start_transform_setup();
5622 be_set_transform_function(op_Add, gen_Add);
5623 be_set_transform_function(op_And, gen_And);
5624 be_set_transform_function(op_ASM, ia32_gen_ASM);
5625 be_set_transform_function(op_be_AddSP, gen_be_AddSP);
5626 be_set_transform_function(op_be_Call, gen_be_Call);
5627 be_set_transform_function(op_be_Copy, gen_be_Copy);
5628 be_set_transform_function(op_be_FrameAddr, gen_be_FrameAddr);
5629 be_set_transform_function(op_be_IncSP, gen_be_IncSP);
5630 be_set_transform_function(op_be_Return, gen_be_Return);
5631 be_set_transform_function(op_be_SubSP, gen_be_SubSP);
5632 be_set_transform_function(op_Builtin, gen_Builtin);
5633 be_set_transform_function(op_Cmp, gen_Cmp);
5634 be_set_transform_function(op_Cond, gen_Cond);
5635 be_set_transform_function(op_Const, gen_Const);
5636 be_set_transform_function(op_Conv, gen_Conv);
5637 be_set_transform_function(op_CopyB, ia32_gen_CopyB);
5638 be_set_transform_function(op_Div, gen_Div);
5639 be_set_transform_function(op_Eor, gen_Eor);
5640 be_set_transform_function(op_ia32_l_Adc, gen_ia32_l_Adc);
5641 be_set_transform_function(op_ia32_l_Add, gen_ia32_l_Add);
5642 be_set_transform_function(op_ia32_Leave, be_duplicate_node);
5643 be_set_transform_function(op_ia32_l_FloattoLL, gen_ia32_l_FloattoLL);
5644 be_set_transform_function(op_ia32_l_IMul, gen_ia32_l_IMul);
5645 be_set_transform_function(op_ia32_l_LLtoFloat, gen_ia32_l_LLtoFloat);
5646 be_set_transform_function(op_ia32_l_Mul, gen_ia32_l_Mul);
5647 be_set_transform_function(op_ia32_l_Sbb, gen_ia32_l_Sbb);
5648 be_set_transform_function(op_ia32_l_Sub, gen_ia32_l_Sub);
5649 be_set_transform_function(op_ia32_GetEIP, be_duplicate_node);
5650 be_set_transform_function(op_ia32_Minus64Bit, be_duplicate_node);
5651 be_set_transform_function(op_ia32_NoReg_GP, be_duplicate_node);
5652 be_set_transform_function(op_ia32_NoReg_VFP, be_duplicate_node);
5653 be_set_transform_function(op_ia32_NoReg_XMM, be_duplicate_node);
5654 be_set_transform_function(op_ia32_PopEbp, be_duplicate_node);
5655 be_set_transform_function(op_ia32_Push, be_duplicate_node);
5656 be_set_transform_function(op_IJmp, gen_IJmp);
5657 be_set_transform_function(op_Jmp, gen_Jmp);
5658 be_set_transform_function(op_Load, gen_Load);
5659 be_set_transform_function(op_Minus, gen_Minus);
5660 be_set_transform_function(op_Mod, gen_Mod);
5661 be_set_transform_function(op_Mul, gen_Mul);
5662 be_set_transform_function(op_Mulh, gen_Mulh);
5663 be_set_transform_function(op_Mux, gen_Mux);
5664 be_set_transform_function(op_Not, gen_Not);
5665 be_set_transform_function(op_Or, gen_Or);
5666 be_set_transform_function(op_Phi, gen_Phi);
5667 be_set_transform_function(op_Proj, gen_Proj);
5668 be_set_transform_function(op_Rotl, gen_Rotl);
5669 be_set_transform_function(op_Shl, gen_Shl);
5670 be_set_transform_function(op_Shr, gen_Shr);
5671 be_set_transform_function(op_Shrs, gen_Shrs);
5672 be_set_transform_function(op_Store, gen_Store);
5673 be_set_transform_function(op_Sub, gen_Sub);
5674 be_set_transform_function(op_Switch, gen_Switch);
5675 be_set_transform_function(op_SymConst, gen_SymConst);
5676 be_set_transform_function(op_Unknown, ia32_gen_Unknown);
5678 be_set_upper_bits_clean_function(op_Mux, ia32_mux_upper_bits_clean);
5682 * Pre-transform all unknown and noreg nodes.
5684 static void ia32_pretransform_node(void)
5686 ir_graph *irg = current_ir_graph;
5687 ia32_irg_data_t *irg_data = ia32_get_irg_data(current_ir_graph);
5689 irg_data->noreg_gp = be_pre_transform_node(irg_data->noreg_gp);
5690 irg_data->noreg_vfp = be_pre_transform_node(irg_data->noreg_vfp);
5691 irg_data->noreg_xmm = be_pre_transform_node(irg_data->noreg_xmm);
5692 irg_data->get_eip = be_pre_transform_node(irg_data->get_eip);
5693 irg_data->fpu_trunc_mode = be_pre_transform_node(irg_data->fpu_trunc_mode);
5695 nomem = get_irg_no_mem(irg);
5696 noreg_GP = ia32_new_NoReg_gp(irg);
5700 * Post-process all calls if we are in SSE mode.
5701 * The ABI requires that the results are in st0, copy them
5702 * to a xmm register.
5704 static void postprocess_fp_call_results(void)
5708 for (i = 0, n = ARR_LEN(call_list); i < n; ++i) {
5709 ir_node *call = call_list[i];
5710 ir_type *mtp = call_types[i];
5713 for (j = get_method_n_ress(mtp) - 1; j >= 0; --j) {
5714 ir_type *res_tp = get_method_res_type(mtp, j);
5715 ir_node *res, *new_res;
5718 if (! is_atomic_type(res_tp)) {
5719 /* no floating point return */
5722 res_mode = get_type_mode(res_tp);
5723 if (! mode_is_float(res_mode)) {
5724 /* no floating point return */
5728 res = be_get_Proj_for_pn(call, pn_ia32_Call_vf0 + j);
5731 /* now patch the users */
5732 foreach_out_edge_safe(res, edge) {
5733 ir_node *succ = get_edge_src_irn(edge);
5736 if (be_is_Keep(succ))
5739 if (is_ia32_xStore(succ)) {
5740 /* an xStore can be patched into an vfst */
5741 dbg_info *db = get_irn_dbg_info(succ);
5742 ir_node *block = get_nodes_block(succ);
5743 ir_node *base = get_irn_n(succ, n_ia32_xStore_base);
5744 ir_node *idx = get_irn_n(succ, n_ia32_xStore_index);
5745 ir_node *mem = get_irn_n(succ, n_ia32_xStore_mem);
5746 ir_node *value = get_irn_n(succ, n_ia32_xStore_val);
5747 ir_mode *mode = get_ia32_ls_mode(succ);
5749 ir_node *st = new_bd_ia32_vfst(db, block, base, idx, mem, value, mode);
5750 //ir_node *mem = new_r_Proj(st, mode_M, pn_ia32_vfst_M);
5751 set_ia32_am_offs_int(st, get_ia32_am_offs_int(succ));
5752 if (is_ia32_use_frame(succ))
5753 set_ia32_use_frame(st);
5754 set_ia32_frame_ent(st, get_ia32_frame_ent(succ));
5755 set_irn_pinned(st, get_irn_pinned(succ));
5756 set_ia32_op_type(st, ia32_AddrModeD);
5758 assert((long)pn_ia32_xStore_M == (long)pn_ia32_vfst_M);
5759 assert((long)pn_ia32_xStore_X_regular == (long)pn_ia32_vfst_X_regular);
5760 assert((long)pn_ia32_xStore_X_except == (long)pn_ia32_vfst_X_except);
5767 if (new_res == NULL) {
5768 dbg_info *db = get_irn_dbg_info(call);
5769 ir_node *block = get_nodes_block(call);
5770 ir_node *frame = get_irg_frame(current_ir_graph);
5771 ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M);
5772 ir_node *call_mem = new_r_Proj(call, mode_M, pn_ia32_Call_M);
5773 ir_node *vfst, *xld, *new_mem;
5776 /* store st(0) on stack */
5777 vfst = new_bd_ia32_vfst(db, block, frame, noreg_GP, call_mem,
5779 set_ia32_op_type(vfst, ia32_AddrModeD);
5780 set_ia32_use_frame(vfst);
5782 vfst_mem = new_r_Proj(vfst, mode_M, pn_ia32_vfst_M);
5784 /* load into SSE register */
5785 xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst_mem,
5787 set_ia32_op_type(xld, ia32_AddrModeS);
5788 set_ia32_use_frame(xld);
5790 new_res = new_r_Proj(xld, res_mode, pn_ia32_xLoad_res);
5791 new_mem = new_r_Proj(xld, mode_M, pn_ia32_xLoad_M);
5793 if (old_mem != NULL) {
5794 edges_reroute(old_mem, new_mem);
5798 set_irn_n(succ, get_edge_src_pos(edge), new_res);
5804 /* do the transformation */
5805 void ia32_transform_graph(ir_graph *irg)
5809 register_transformers();
5810 initial_fpcw = NULL;
5811 ia32_no_pic_adjust = 0;
5813 old_initial_fpcw = be_get_initial_reg_value(irg, &ia32_registers[REG_FPCW]);
5815 be_timer_push(T_HEIGHTS);
5816 ia32_heights = heights_new(irg);
5817 be_timer_pop(T_HEIGHTS);
5818 ia32_calculate_non_address_mode_nodes(irg);
5820 /* the transform phase is not safe for CSE (yet) because several nodes get
5821 * attributes set after their creation */
5822 cse_last = get_opt_cse();
5825 call_list = NEW_ARR_F(ir_node *, 0);
5826 call_types = NEW_ARR_F(ir_type *, 0);
5827 be_transform_graph(irg, ia32_pretransform_node);
5829 if (ia32_cg_config.use_sse2)
5830 postprocess_fp_call_results();
5831 DEL_ARR_F(call_types);
5832 DEL_ARR_F(call_list);
5834 set_opt_cse(cse_last);
5836 ia32_free_non_address_mode_nodes();
5837 heights_free(ia32_heights);
5838 ia32_heights = NULL;
5841 void ia32_init_transform(void)
5843 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");