2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
98 static transform_config_t transform_config;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
108 ir_node *op1, ir_node *op2, ir_node *flags);
110 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *op1, ir_node *op2);
113 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
118 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
120 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
122 ir_node *op1, ir_node *op2, ir_node *fpcw);
124 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
125 ir_node *block, ir_node *op);
127 /****************************************************************************************************
129 * | | | | / _| | | (_)
130 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
131 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
132 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
133 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
135 ****************************************************************************************************/
137 static ir_node *try_create_Immediate(ir_node *node,
138 char immediate_constraint_type);
140 static ir_node *create_immediate_or_transform(ir_node *node,
141 char immediate_constraint_type);
143 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
144 dbg_info *dbgi, ir_node *block,
145 ir_node *op, ir_node *orig_node);
148 * Return true if a mode can be stored in the GP register set
150 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
151 if(mode == mode_fpcw)
153 if(get_mode_size_bits(mode) > 32)
155 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
159 * creates a unique ident by adding a number to a tag
161 * @param tag the tag string, must contain a %d if a number
164 static ident *unique_id(const char *tag)
166 static unsigned id = 0;
169 snprintf(str, sizeof(str), tag, ++id);
170 return new_id_from_str(str);
174 * Get a primitive type for a mode.
176 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
178 pmap_entry *e = pmap_find(types, mode);
183 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
184 res = new_type_primitive(new_id_from_str(buf), mode);
185 set_type_alignment_bytes(res, 16);
186 pmap_insert(types, mode, res);
194 * Get an atomic entity that is initialized with a tarval
196 static ir_entity *create_float_const_entity(ir_node *cnst)
198 ia32_isa_t *isa = env_cg->isa;
199 tarval *tv = get_Const_tarval(cnst);
200 pmap_entry *e = pmap_find(isa->tv_ent, tv);
205 ir_mode *mode = get_irn_mode(cnst);
206 ir_type *tp = get_Const_type(cnst);
207 if (tp == firm_unknown_type)
208 tp = get_prim_type(isa->types, mode);
210 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
212 set_entity_ld_ident(res, get_entity_ident(res));
213 set_entity_visibility(res, visibility_local);
214 set_entity_variability(res, variability_constant);
215 set_entity_allocation(res, allocation_static);
217 /* we create a new entity here: It's initialization must resist on the
219 rem = current_ir_graph;
220 current_ir_graph = get_const_code_irg();
221 set_atomic_ent_value(res, new_Const_type(tv, tp));
222 current_ir_graph = rem;
224 pmap_insert(isa->tv_ent, tv, res);
232 static int is_Const_0(ir_node *node) {
233 return is_Const(node) && is_Const_null(node);
236 static int is_Const_1(ir_node *node) {
237 return is_Const(node) && is_Const_one(node);
240 static int is_Const_Minus_1(ir_node *node) {
241 return is_Const(node) && is_Const_all_one(node);
245 * returns true if constant can be created with a simple float command
247 static int is_simple_x87_Const(ir_node *node)
249 tarval *tv = get_Const_tarval(node);
251 if(tarval_is_null(tv) || tarval_is_one(tv))
254 /* TODO: match all the other float constants */
259 * Transforms a Const.
261 static ir_node *gen_Const(ir_node *node) {
262 ir_graph *irg = current_ir_graph;
263 ir_node *old_block = get_nodes_block(node);
264 ir_node *block = be_transform_node(old_block);
265 dbg_info *dbgi = get_irn_dbg_info(node);
266 ir_mode *mode = get_irn_mode(node);
268 if (mode_is_float(mode)) {
270 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
271 ir_node *nomem = new_NoMem();
275 if (USE_SSE2(env_cg)) {
276 if (is_Const_null(node)) {
277 load = new_rd_ia32_xZero(dbgi, irg, block);
278 set_ia32_ls_mode(load, mode);
281 floatent = create_float_const_entity(node);
283 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
285 set_ia32_op_type(load, ia32_AddrModeS);
286 set_ia32_am_sc(load, floatent);
287 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
288 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
291 if (is_Const_null(node)) {
292 load = new_rd_ia32_vfldz(dbgi, irg, block);
294 } else if (is_Const_one(node)) {
295 load = new_rd_ia32_vfld1(dbgi, irg, block);
298 floatent = create_float_const_entity(node);
300 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
301 set_ia32_op_type(load, ia32_AddrModeS);
302 set_ia32_am_sc(load, floatent);
303 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
304 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
306 set_ia32_ls_mode(load, mode);
309 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
311 /* Const Nodes before the initial IncSP are a bad idea, because
312 * they could be spilled and we have no SP ready at that point yet.
313 * So add a dependency to the initial frame pointer calculation to
314 * avoid that situation.
316 if (get_irg_start_block(irg) == block) {
317 add_irn_dep(load, get_irg_frame(irg));
320 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
324 tarval *tv = get_Const_tarval(node);
327 tv = tarval_convert_to(tv, mode_Iu);
329 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
331 panic("couldn't convert constant tarval (%+F)", node);
333 val = get_tarval_long(tv);
335 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
339 if (get_irg_start_block(irg) == block) {
340 add_irn_dep(cnst, get_irg_frame(irg));
348 * Transforms a SymConst.
350 static ir_node *gen_SymConst(ir_node *node) {
351 ir_graph *irg = current_ir_graph;
352 ir_node *old_block = get_nodes_block(node);
353 ir_node *block = be_transform_node(old_block);
354 dbg_info *dbgi = get_irn_dbg_info(node);
355 ir_mode *mode = get_irn_mode(node);
358 if (mode_is_float(mode)) {
359 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
360 ir_node *nomem = new_NoMem();
362 if (USE_SSE2(env_cg))
363 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
365 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
366 set_ia32_am_sc(cnst, get_SymConst_entity(node));
367 set_ia32_use_frame(cnst);
371 if(get_SymConst_kind(node) != symconst_addr_ent) {
372 panic("backend only support symconst_addr_ent (at %+F)", node);
374 entity = get_SymConst_entity(node);
375 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
378 /* Const Nodes before the initial IncSP are a bad idea, because
379 * they could be spilled and we have no SP ready at that point yet
381 if (get_irg_start_block(irg) == block) {
382 add_irn_dep(cnst, get_irg_frame(irg));
385 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
390 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
391 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
392 static const struct {
394 const char *ent_name;
395 const char *cnst_str;
398 } names [ia32_known_const_max] = {
399 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
400 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
401 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
402 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
403 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
405 static ir_entity *ent_cache[ia32_known_const_max];
407 const char *tp_name, *ent_name, *cnst_str;
415 ent_name = names[kct].ent_name;
416 if (! ent_cache[kct]) {
417 tp_name = names[kct].tp_name;
418 cnst_str = names[kct].cnst_str;
420 switch (names[kct].mode) {
421 case 0: mode = mode_Iu; break;
422 case 1: mode = mode_Lu; break;
423 default: mode = mode_F; break;
425 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
426 tp = new_type_primitive(new_id_from_str(tp_name), mode);
427 /* set the specified alignment */
428 set_type_alignment_bytes(tp, names[kct].align);
430 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
432 set_entity_ld_ident(ent, get_entity_ident(ent));
433 set_entity_visibility(ent, visibility_local);
434 set_entity_variability(ent, variability_constant);
435 set_entity_allocation(ent, allocation_static);
437 /* we create a new entity here: It's initialization must resist on the
439 rem = current_ir_graph;
440 current_ir_graph = get_const_code_irg();
441 cnst = new_Const(mode, tv);
442 current_ir_graph = rem;
444 set_atomic_ent_value(ent, cnst);
446 /* cache the entry */
447 ent_cache[kct] = ent;
450 return ent_cache[kct];
455 * Prints the old node name on cg obst and returns a pointer to it.
457 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
458 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
460 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
461 obstack_1grow(isa->name_obst, 0);
462 return obstack_finish(isa->name_obst);
466 int ia32_use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
468 ir_mode *mode = get_irn_mode(node);
472 /* float constants are always available */
473 if(is_Const(node) && mode_is_float(mode)) {
474 if(!is_simple_x87_Const(node))
476 if(get_irn_n_edges(node) > 1)
483 load = get_Proj_pred(node);
484 pn = get_Proj_proj(node);
485 if(!is_Load(load) || pn != pn_Load_res)
487 if(get_nodes_block(load) != block)
489 /* we only use address mode if we're the only user of the load */
490 if(get_irn_n_edges(node) > 1)
492 /* in some edge cases with address mode we might reach the load normally
493 * and through some AM sequence, if it is already materialized then we
494 * can't create an AM node from it */
495 if(be_is_transformed(node))
498 /* don't do AM if other node inputs depend on the load (via mem-proj) */
499 if(other != NULL && get_nodes_block(other) == block
500 && heights_reachable_in_block(heights, other, load))
506 typedef struct ia32_address_mode_t ia32_address_mode_t;
507 struct ia32_address_mode_t {
511 ia32_op_type_t op_type;
515 unsigned commutative : 1;
516 unsigned ins_permuted : 1;
519 static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
521 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
523 /* construct load address */
524 memset(addr, 0, sizeof(addr[0]));
525 ia32_create_address_mode(addr, ptr, /*force=*/0);
527 addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
528 addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
529 addr->mem = be_transform_node(mem);
532 static void build_address(ia32_address_mode_t *am, ir_node *node)
534 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
535 ia32_address_t *addr = &am->addr;
542 ir_entity *entity = create_float_const_entity(node);
543 addr->base = noreg_gp;
544 addr->index = noreg_gp;
545 addr->mem = new_NoMem();
546 addr->symconst_ent = entity;
548 am->ls_mode = get_irn_mode(node);
549 am->pinned = op_pin_state_floats;
553 load = get_Proj_pred(node);
554 ptr = get_Load_ptr(load);
555 mem = get_Load_mem(load);
556 new_mem = be_transform_node(mem);
557 am->pinned = get_irn_pinned(load);
558 am->ls_mode = get_Load_mode(load);
559 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
561 /* construct load address */
562 ia32_create_address_mode(addr, ptr, /*force=*/0);
564 addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
565 addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
569 static void set_address(ir_node *node, const ia32_address_t *addr)
571 set_ia32_am_scale(node, addr->scale);
572 set_ia32_am_sc(node, addr->symconst_ent);
573 set_ia32_am_offs_int(node, addr->offset);
574 if(addr->symconst_sign)
575 set_ia32_am_sc_sign(node);
577 set_ia32_use_frame(node);
578 set_ia32_frame_ent(node, addr->frame_entity);
581 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
583 set_address(node, &am->addr);
585 set_ia32_op_type(node, am->op_type);
586 set_ia32_ls_mode(node, am->ls_mode);
587 if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) {
588 set_irn_pinned(node, am->pinned);
591 set_ia32_commutative(node);
595 * Check, if a given node is a Down-Conv, ie. a integer Conv
596 * from a mode with a mode with more bits to a mode with lesser bits.
597 * Moreover, we return only true if the node has not more than 1 user.
599 * @param node the node
600 * @return non-zero if node is a Down-Conv
602 static int is_downconv(const ir_node *node)
610 /* we only want to skip the conv when we're the only user
611 * (not optimal but for now...)
613 if(get_irn_n_edges(node) > 1)
616 src_mode = get_irn_mode(get_Conv_op(node));
617 dest_mode = get_irn_mode(node);
618 return mode_needs_gp_reg(src_mode)
619 && mode_needs_gp_reg(dest_mode)
620 && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode);
623 /* Skip all Down-Conv's on a given node and return the resulting node. */
624 ir_node *ia32_skip_downconv(ir_node *node) {
625 while (is_downconv(node))
626 node = get_Conv_op(node);
632 static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
634 ir_mode *mode = get_irn_mode(node);
639 if(mode_is_signed(mode)) {
644 block = get_nodes_block(node);
645 dbgi = get_irn_dbg_info(node);
647 return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
651 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
652 ir_node *op1, ir_node *op2, match_flags_t flags)
654 ia32_address_t *addr = &am->addr;
655 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
658 ir_mode *mode = get_irn_mode(op2);
660 unsigned commutative;
661 int use_am_and_immediates;
663 int mode_bits = get_mode_size_bits(mode);
665 memset(am, 0, sizeof(am[0]));
667 commutative = (flags & match_commutative) != 0;
668 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
669 use_am = (flags & match_am) != 0;
670 use_immediate = (flags & match_immediate) != 0;
671 assert(!use_am_and_immediates || use_immediate);
674 assert(!commutative || op1 != NULL);
675 assert(use_am || !(flags & match_8bit_am));
676 assert(use_am || !(flags & match_16bit_am));
679 if (! (flags & match_8bit_am))
681 assert((flags & match_mode_neutral) || (flags & match_8bit));
682 } else if(mode_bits == 16) {
683 if(! (flags & match_16bit_am))
685 assert((flags & match_mode_neutral) || (flags & match_16bit));
688 /* we can simply skip downconvs for mode neutral nodes: the upper bits
689 * can be random for these operations */
690 if(flags & match_mode_neutral) {
691 op2 = ia32_skip_downconv(op2);
693 op1 = ia32_skip_downconv(op1);
697 if(! (flags & match_try_am) && use_immediate)
698 new_op2 = try_create_Immediate(op2, 0);
702 if(new_op2 == NULL && use_am && ia32_use_source_address_mode(block, op2, op1)) {
703 build_address(am, op2);
704 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
705 if(mode_is_float(mode)) {
706 new_op2 = ia32_new_NoReg_vfp(env_cg);
710 am->op_type = ia32_AddrModeS;
711 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
712 use_am && ia32_use_source_address_mode(block, op1, op2)) {
714 build_address(am, op1);
716 if(mode_is_float(mode)) {
717 noreg = ia32_new_NoReg_vfp(env_cg);
722 if(new_op2 != NULL) {
725 new_op1 = be_transform_node(op2);
727 am->ins_permuted = 1;
729 am->op_type = ia32_AddrModeS;
731 if(flags & match_try_am) {
734 am->op_type = ia32_Normal;
738 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
740 new_op2 = be_transform_node(op2);
741 am->op_type = ia32_Normal;
742 am->ls_mode = get_irn_mode(op2);
743 if(flags & match_mode_neutral)
744 am->ls_mode = mode_Iu;
746 if(addr->base == NULL)
747 addr->base = noreg_gp;
748 if(addr->index == NULL)
749 addr->index = noreg_gp;
750 if(addr->mem == NULL)
751 addr->mem = new_NoMem();
753 am->new_op1 = new_op1;
754 am->new_op2 = new_op2;
755 am->commutative = commutative;
758 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
760 ir_graph *irg = current_ir_graph;
764 if(am->mem_proj == NULL)
767 /* we have to create a mode_T so the old MemProj can attach to us */
768 mode = get_irn_mode(node);
769 load = get_Proj_pred(am->mem_proj);
771 mark_irn_visited(load);
772 be_set_transformed_node(load, node);
775 set_irn_mode(node, mode_T);
776 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
783 * Construct a standard binary operation, set AM and immediate if required.
785 * @param op1 The first operand
786 * @param op2 The second operand
787 * @param func The node constructor function
788 * @return The constructed ia32 node.
790 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
791 construct_binop_func *func, match_flags_t flags)
793 ir_node *block = get_nodes_block(node);
794 ir_node *new_block = be_transform_node(block);
795 ir_graph *irg = current_ir_graph;
796 dbg_info *dbgi = get_irn_dbg_info(node);
798 ia32_address_mode_t am;
799 ia32_address_t *addr = &am.addr;
801 match_arguments(&am, block, op1, op2, flags);
803 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
804 am.new_op1, am.new_op2);
805 set_am_attributes(new_node, &am);
806 /* we can't use source address mode anymore when using immediates */
807 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
808 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
809 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
811 new_node = fix_mem_proj(new_node, &am);
818 n_ia32_l_binop_right,
819 n_ia32_l_binop_eflags
821 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
822 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
823 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
824 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left)
825 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right)
826 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
829 * Construct a binary operation which also consumes the eflags.
831 * @param node The node to transform
832 * @param func The node constructor function
833 * @param flags The match flags
834 * @return The constructor ia32 node
836 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
839 ir_node *src_block = get_nodes_block(node);
840 ir_node *block = be_transform_node(src_block);
841 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
842 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
843 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
844 ir_node *new_eflags = be_transform_node(eflags);
845 ir_graph *irg = current_ir_graph;
846 dbg_info *dbgi = get_irn_dbg_info(node);
848 ia32_address_mode_t am;
849 ia32_address_t *addr = &am.addr;
851 match_arguments(&am, src_block, op1, op2, flags);
853 new_node = func(dbgi, irg, block, addr->base, addr->index,
854 addr->mem, am.new_op1, am.new_op2, new_eflags);
855 set_am_attributes(new_node, &am);
856 /* we can't use source address mode anymore when using immediates */
857 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
858 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
859 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
861 new_node = fix_mem_proj(new_node, &am);
866 static ir_node *get_fpcw(void)
869 if(initial_fpcw != NULL)
872 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
873 &ia32_fp_cw_regs[REG_FPCW]);
874 initial_fpcw = be_transform_node(fpcw);
880 * Construct a standard binary operation, set AM and immediate if required.
882 * @param op1 The first operand
883 * @param op2 The second operand
884 * @param func The node constructor function
885 * @return The constructed ia32 node.
887 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
888 construct_binop_float_func *func,
891 ir_graph *irg = current_ir_graph;
892 dbg_info *dbgi = get_irn_dbg_info(node);
893 ir_node *block = get_nodes_block(node);
894 ir_node *new_block = be_transform_node(block);
895 ir_mode *mode = get_irn_mode(node);
897 ia32_address_mode_t am;
898 ia32_address_t *addr = &am.addr;
900 /* cannot use addresmode with long double on x87 */
901 if (get_mode_size_bits(mode) > 64) flags &= ~match_am;
903 match_arguments(&am, block, op1, op2, flags);
905 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
906 am.new_op1, am.new_op2, get_fpcw());
907 set_am_attributes(new_node, &am);
909 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
911 new_node = fix_mem_proj(new_node, &am);
917 * Construct a shift/rotate binary operation, sets AM and immediate if required.
919 * @param op1 The first operand
920 * @param op2 The second operand
921 * @param func The node constructor function
922 * @return The constructed ia32 node.
924 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
925 construct_shift_func *func,
928 dbg_info *dbgi = get_irn_dbg_info(node);
929 ir_graph *irg = current_ir_graph;
930 ir_node *block = get_nodes_block(node);
931 ir_node *new_block = be_transform_node(block);
932 ir_mode *mode = get_irn_mode(node);
937 assert(! mode_is_float(mode));
938 assert(flags & match_immediate);
939 assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
941 if(flags & match_mode_neutral) {
942 op1 = ia32_skip_downconv(op1);
944 new_op1 = be_transform_node(op1);
946 /* the shift amount can be any mode that is bigger than 5 bits, since all
947 * other bits are ignored anyway */
948 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
949 op2 = get_Conv_op(op2);
950 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
952 new_op2 = create_immediate_or_transform(op2, 0);
954 new_node = func(dbgi, irg, new_block, new_op1, new_op2);
955 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
957 /* lowered shift instruction may have a dependency operand, handle it here */
958 if (get_irn_arity(node) == 3) {
959 /* we have a dependency */
960 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
961 add_irn_dep(new_node, new_dep);
969 * Construct a standard unary operation, set AM and immediate if required.
971 * @param op The operand
972 * @param func The node constructor function
973 * @return The constructed ia32 node.
975 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
978 ir_graph *irg = current_ir_graph;
979 dbg_info *dbgi = get_irn_dbg_info(node);
980 ir_node *block = get_nodes_block(node);
981 ir_node *new_block = be_transform_node(block);
985 assert(flags == 0 || flags == match_mode_neutral);
986 if(flags & match_mode_neutral) {
987 op = ia32_skip_downconv(op);
990 new_op = be_transform_node(op);
991 new_node = func(dbgi, irg, new_block, new_op);
993 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
998 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
999 ia32_address_t *addr)
1001 ir_graph *irg = current_ir_graph;
1002 ir_node *base = addr->base;
1003 ir_node *index = addr->index;
1007 base = ia32_new_NoReg_gp(env_cg);
1009 base = be_transform_node(base);
1013 index = ia32_new_NoReg_gp(env_cg);
1015 index = be_transform_node(index);
1018 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1019 set_address(res, addr);
1024 static int am_has_immediates(const ia32_address_t *addr)
1026 return addr->offset != 0 || addr->symconst_ent != NULL
1027 || addr->frame_entity || addr->use_frame;
1031 * Creates an ia32 Add.
1033 * @return the created ia32 Add node
1035 static ir_node *gen_Add(ir_node *node) {
1036 ir_graph *irg = current_ir_graph;
1037 dbg_info *dbgi = get_irn_dbg_info(node);
1038 ir_node *block = get_nodes_block(node);
1039 ir_node *new_block = be_transform_node(block);
1040 ir_node *op1 = get_Add_left(node);
1041 ir_node *op2 = get_Add_right(node);
1042 ir_mode *mode = get_irn_mode(node);
1044 ir_node *add_immediate_op;
1045 ia32_address_t addr;
1046 ia32_address_mode_t am;
1048 if (mode_is_float(mode)) {
1049 if (USE_SSE2(env_cg))
1050 return gen_binop(node, op1, op2, new_rd_ia32_xAdd,
1051 match_commutative | match_am);
1053 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd,
1054 match_commutative | match_am);
1057 ia32_mark_non_am(node);
1059 op2 = ia32_skip_downconv(op2);
1060 op1 = ia32_skip_downconv(op1);
1064 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1065 * 1. Add with immediate -> Lea
1066 * 2. Add with possible source address mode -> Add
1067 * 3. Otherwise -> Lea
1069 memset(&addr, 0, sizeof(addr));
1070 ia32_create_address_mode(&addr, node, /*force=*/1);
1071 add_immediate_op = NULL;
1073 if(addr.base == NULL && addr.index == NULL) {
1074 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
1075 addr.symconst_sign, addr.offset);
1076 add_irn_dep(new_node, get_irg_frame(irg));
1077 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1080 /* add with immediate? */
1081 if(addr.index == NULL) {
1082 add_immediate_op = addr.base;
1083 } else if(addr.base == NULL && addr.scale == 0) {
1084 add_immediate_op = addr.index;
1087 if(add_immediate_op != NULL) {
1088 if(!am_has_immediates(&addr)) {
1089 #ifdef DEBUG_libfirm
1090 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1093 return be_transform_node(add_immediate_op);
1096 new_node = create_lea_from_address(dbgi, new_block, &addr);
1097 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1101 /* test if we can use source address mode */
1102 match_arguments(&am, block, op1, op2, match_commutative
1103 | match_mode_neutral | match_am | match_immediate | match_try_am);
1105 /* construct an Add with source address mode */
1106 if (am.op_type == ia32_AddrModeS) {
1107 ia32_address_t *am_addr = &am.addr;
1108 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
1109 am_addr->index, am_addr->mem, am.new_op1,
1111 set_am_attributes(new_node, &am);
1112 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1114 new_node = fix_mem_proj(new_node, &am);
1119 /* otherwise construct a lea */
1120 new_node = create_lea_from_address(dbgi, new_block, &addr);
1121 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1126 * Creates an ia32 Mul.
1128 * @return the created ia32 Mul node
1130 static ir_node *gen_Mul(ir_node *node) {
1131 ir_node *op1 = get_Mul_left(node);
1132 ir_node *op2 = get_Mul_right(node);
1133 ir_mode *mode = get_irn_mode(node);
1135 if (mode_is_float(mode)) {
1136 if (USE_SSE2(env_cg))
1137 return gen_binop(node, op1, op2, new_rd_ia32_xMul,
1138 match_commutative | match_am);
1140 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul,
1141 match_commutative | match_am);
1145 for the lower 32bit of the result it doesn't matter whether we use
1146 signed or unsigned multiplication so we use IMul as it has fewer
1149 return gen_binop(node, op1, op2, new_rd_ia32_IMul,
1150 match_commutative | match_am | match_mode_neutral |
1151 match_immediate | match_am_and_immediates);
1155 * Creates an ia32 Mulh.
1156 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1157 * this result while Mul returns the lower 32 bit.
1159 * @return the created ia32 Mulh node
1161 static ir_node *gen_Mulh(ir_node *node)
1163 ir_node *block = get_nodes_block(node);
1164 ir_node *new_block = be_transform_node(block);
1165 ir_graph *irg = current_ir_graph;
1166 dbg_info *dbgi = get_irn_dbg_info(node);
1167 ir_mode *mode = get_irn_mode(node);
1168 ir_node *op1 = get_Mulh_left(node);
1169 ir_node *op2 = get_Mulh_right(node);
1172 ia32_address_mode_t am;
1173 ia32_address_t *addr = &am.addr;
1175 assert(!mode_is_float(mode) && "Mulh with float not supported");
1176 assert(get_mode_size_bits(mode) == 32);
1178 match_arguments(&am, block, op1, op2, match_commutative | match_am);
1180 if (mode_is_signed(mode)) {
1181 new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base,
1182 addr->index, addr->mem, am.new_op1,
1185 new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base,
1186 addr->index, addr->mem, am.new_op1,
1190 set_am_attributes(new_node, &am);
1191 /* we can't use source address mode anymore when using immediates */
1192 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
1193 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
1194 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1196 assert(get_irn_mode(new_node) == mode_T);
1198 fix_mem_proj(new_node, &am);
1200 assert(pn_ia32_IMul1OP_EDX == pn_ia32_Mul_EDX);
1201 proj_EDX = new_rd_Proj(dbgi, irg, block, new_node,
1202 mode_Iu, pn_ia32_IMul1OP_EDX);
1210 * Creates an ia32 And.
1212 * @return The created ia32 And node
1214 static ir_node *gen_And(ir_node *node) {
1215 ir_node *op1 = get_And_left(node);
1216 ir_node *op2 = get_And_right(node);
1217 assert(! mode_is_float(get_irn_mode(node)));
1219 /* is it a zero extension? */
1220 if (is_Const(op2)) {
1221 tarval *tv = get_Const_tarval(op2);
1222 long v = get_tarval_long(tv);
1224 if (v == 0xFF || v == 0xFFFF) {
1225 dbg_info *dbgi = get_irn_dbg_info(node);
1226 ir_node *block = get_nodes_block(node);
1233 assert(v == 0xFFFF);
1236 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1242 return gen_binop(node, op1, op2, new_rd_ia32_And,
1243 match_commutative | match_mode_neutral | match_am
1250 * Creates an ia32 Or.
1252 * @return The created ia32 Or node
1254 static ir_node *gen_Or(ir_node *node) {
1255 ir_node *op1 = get_Or_left(node);
1256 ir_node *op2 = get_Or_right(node);
1258 assert (! mode_is_float(get_irn_mode(node)));
1259 return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative
1260 | match_mode_neutral | match_am | match_immediate);
1266 * Creates an ia32 Eor.
1268 * @return The created ia32 Eor node
1270 static ir_node *gen_Eor(ir_node *node) {
1271 ir_node *op1 = get_Eor_left(node);
1272 ir_node *op2 = get_Eor_right(node);
1274 assert(! mode_is_float(get_irn_mode(node)));
1275 return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative
1276 | match_mode_neutral | match_am | match_immediate);
1281 * Creates an ia32 Sub.
1283 * @return The created ia32 Sub node
1285 static ir_node *gen_Sub(ir_node *node) {
1286 ir_node *op1 = get_Sub_left(node);
1287 ir_node *op2 = get_Sub_right(node);
1288 ir_mode *mode = get_irn_mode(node);
1290 if (mode_is_float(mode)) {
1291 if (USE_SSE2(env_cg))
1292 return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am);
1294 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub,
1299 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1303 return gen_binop(node, op1, op2, new_rd_ia32_Sub, match_mode_neutral
1304 | match_am | match_immediate);
1308 * Generates an ia32 DivMod with additional infrastructure for the
1309 * register allocator if needed.
1311 static ir_node *create_Div(ir_node *node)
1313 ir_graph *irg = current_ir_graph;
1314 dbg_info *dbgi = get_irn_dbg_info(node);
1315 ir_node *block = get_nodes_block(node);
1316 ir_node *new_block = be_transform_node(block);
1323 ir_node *sign_extension;
1325 ia32_address_mode_t am;
1326 ia32_address_t *addr = &am.addr;
1328 /* the upper bits have random contents for smaller modes */
1330 switch (get_irn_opcode(node)) {
1332 op1 = get_Div_left(node);
1333 op2 = get_Div_right(node);
1334 mem = get_Div_mem(node);
1335 mode = get_Div_resmode(node);
1336 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1339 op1 = get_Mod_left(node);
1340 op2 = get_Mod_right(node);
1341 mem = get_Mod_mem(node);
1342 mode = get_Mod_resmode(node);
1343 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1346 op1 = get_DivMod_left(node);
1347 op2 = get_DivMod_right(node);
1348 mem = get_DivMod_mem(node);
1349 mode = get_DivMod_resmode(node);
1350 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1353 panic("invalid divmod node %+F", node);
1356 match_arguments(&am, block, op1, op2, match_am);
1358 if(!is_NoMem(mem)) {
1359 new_mem = be_transform_node(mem);
1360 if(!is_NoMem(addr->mem)) {
1364 new_mem = new_rd_Sync(dbgi, irg, new_block, 2, in);
1367 new_mem = addr->mem;
1370 if (mode_is_signed(mode)) {
1371 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1372 add_irn_dep(produceval, get_irg_frame(irg));
1373 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1,
1376 new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base,
1377 addr->index, new_mem, am.new_op1,
1378 sign_extension, am.new_op2);
1380 sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0);
1381 add_irn_dep(sign_extension, get_irg_frame(irg));
1383 new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base,
1384 addr->index, new_mem, am.new_op1,
1385 sign_extension, am.new_op2);
1388 set_ia32_exc_label(new_node, has_exc);
1389 set_irn_pinned(new_node, get_irn_pinned(node));
1391 set_am_attributes(new_node, &am);
1392 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1394 new_node = fix_mem_proj(new_node, &am);
1400 static ir_node *gen_Mod(ir_node *node) {
1401 return create_Div(node);
1404 static ir_node *gen_Div(ir_node *node) {
1405 return create_Div(node);
1408 static ir_node *gen_DivMod(ir_node *node) {
1409 return create_Div(node);
1415 * Creates an ia32 floating Div.
1417 * @return The created ia32 xDiv node
1419 static ir_node *gen_Quot(ir_node *node)
1421 ir_node *op1 = get_Quot_left(node);
1422 ir_node *op2 = get_Quot_right(node);
1424 if (USE_SSE2(env_cg)) {
1425 return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am);
1427 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, match_am);
1433 * Creates an ia32 Shl.
1435 * @return The created ia32 Shl node
1437 static ir_node *gen_Shl(ir_node *node) {
1438 ir_node *left = get_Shl_left(node);
1439 ir_node *right = get_Shl_right(node);
1441 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
1442 match_mode_neutral | match_immediate);
1446 * Creates an ia32 Shr.
1448 * @return The created ia32 Shr node
1450 static ir_node *gen_Shr(ir_node *node) {
1451 ir_node *left = get_Shr_left(node);
1452 ir_node *right = get_Shr_right(node);
1454 return gen_shift_binop(node, left, right, new_rd_ia32_Shr, match_immediate);
1460 * Creates an ia32 Sar.
1462 * @return The created ia32 Shrs node
1464 static ir_node *gen_Shrs(ir_node *node) {
1465 ir_node *left = get_Shrs_left(node);
1466 ir_node *right = get_Shrs_right(node);
1467 ir_mode *mode = get_irn_mode(node);
1469 if(is_Const(right) && mode == mode_Is) {
1470 tarval *tv = get_Const_tarval(right);
1471 long val = get_tarval_long(tv);
1473 /* this is a sign extension */
1474 ir_graph *irg = current_ir_graph;
1475 dbg_info *dbgi = get_irn_dbg_info(node);
1476 ir_node *block = be_transform_node(get_nodes_block(node));
1478 ir_node *new_op = be_transform_node(op);
1479 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1480 add_irn_dep(pval, get_irg_frame(irg));
1482 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1486 /* 8 or 16 bit sign extension? */
1487 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1488 ir_node *shl_left = get_Shl_left(left);
1489 ir_node *shl_right = get_Shl_right(left);
1490 if(is_Const(shl_right)) {
1491 tarval *tv1 = get_Const_tarval(right);
1492 tarval *tv2 = get_Const_tarval(shl_right);
1493 if(tv1 == tv2 && tarval_is_long(tv1)) {
1494 long val = get_tarval_long(tv1);
1495 if(val == 16 || val == 24) {
1496 dbg_info *dbgi = get_irn_dbg_info(node);
1497 ir_node *block = get_nodes_block(node);
1507 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1516 return gen_shift_binop(node, left, right, new_rd_ia32_Sar, match_immediate);
1522 * Creates an ia32 RotL.
1524 * @param op1 The first operator
1525 * @param op2 The second operator
1526 * @return The created ia32 RotL node
1528 static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) {
1529 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate);
1535 * Creates an ia32 RotR.
1536 * NOTE: There is no RotR with immediate because this would always be a RotL
1537 * "imm-mode_size_bits" which can be pre-calculated.
1539 * @param op1 The first operator
1540 * @param op2 The second operator
1541 * @return The created ia32 RotR node
1543 static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) {
1544 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate);
1550 * Creates an ia32 RotR or RotL (depending on the found pattern).
1552 * @return The created ia32 RotL or RotR node
1554 static ir_node *gen_Rot(ir_node *node) {
1555 ir_node *rotate = NULL;
1556 ir_node *op1 = get_Rot_left(node);
1557 ir_node *op2 = get_Rot_right(node);
1559 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1560 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1561 that means we can create a RotR instead of an Add and a RotL */
1563 if (get_irn_op(op2) == op_Add) {
1565 ir_node *left = get_Add_left(add);
1566 ir_node *right = get_Add_right(add);
1567 if (is_Const(right)) {
1568 tarval *tv = get_Const_tarval(right);
1569 ir_mode *mode = get_irn_mode(node);
1570 long bits = get_mode_size_bits(mode);
1572 if (get_irn_op(left) == op_Minus &&
1573 tarval_is_long(tv) &&
1574 get_tarval_long(tv) == bits &&
1577 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1578 rotate = gen_RotR(node, op1, get_Minus_op(left));
1583 if (rotate == NULL) {
1584 rotate = gen_RotL(node, op1, op2);
1593 * Transforms a Minus node.
1595 * @return The created ia32 Minus node
1597 static ir_node *gen_Minus(ir_node *node)
1599 ir_node *op = get_Minus_op(node);
1600 ir_node *block = be_transform_node(get_nodes_block(node));
1601 ir_graph *irg = current_ir_graph;
1602 dbg_info *dbgi = get_irn_dbg_info(node);
1603 ir_mode *mode = get_irn_mode(node);
1608 if (mode_is_float(mode)) {
1609 ir_node *new_op = be_transform_node(op);
1610 if (USE_SSE2(env_cg)) {
1611 /* TODO: non-optimal... if we have many xXors, then we should
1612 * rather create a load for the const and use that instead of
1613 * several AM nodes... */
1614 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1615 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1616 ir_node *nomem = new_rd_NoMem(irg);
1618 new_node = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp,
1619 nomem, new_op, noreg_xmm);
1621 size = get_mode_size_bits(mode);
1622 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1624 set_ia32_am_sc(new_node, ent);
1625 set_ia32_op_type(new_node, ia32_AddrModeS);
1626 set_ia32_ls_mode(new_node, mode);
1628 new_node = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1631 new_node = gen_unop(node, op, new_rd_ia32_Neg, match_mode_neutral);
1634 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1640 * Transforms a Not node.
1642 * @return The created ia32 Not node
1644 static ir_node *gen_Not(ir_node *node) {
1645 ir_node *op = get_Not_op(node);
1647 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1648 assert (! mode_is_float(get_irn_mode(node)));
1650 return gen_unop(node, op, new_rd_ia32_Not, match_mode_neutral);
1656 * Transforms an Abs node.
1658 * @return The created ia32 Abs node
1660 static ir_node *gen_Abs(ir_node *node)
1662 ir_node *block = get_nodes_block(node);
1663 ir_node *new_block = be_transform_node(block);
1664 ir_node *op = get_Abs_op(node);
1665 ir_graph *irg = current_ir_graph;
1666 dbg_info *dbgi = get_irn_dbg_info(node);
1667 ir_mode *mode = get_irn_mode(node);
1668 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1669 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1670 ir_node *nomem = new_NoMem();
1676 if (mode_is_float(mode)) {
1677 new_op = be_transform_node(op);
1679 if (USE_SSE2(env_cg)) {
1680 new_node = new_rd_ia32_xAnd(dbgi,irg, new_block, noreg_gp, noreg_gp,
1681 nomem, new_op, noreg_fp);
1683 size = get_mode_size_bits(mode);
1684 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1686 set_ia32_am_sc(new_node, ent);
1688 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1690 set_ia32_op_type(new_node, ia32_AddrModeS);
1691 set_ia32_ls_mode(new_node, mode);
1693 new_node = new_rd_ia32_vfabs(dbgi, irg, new_block, new_op);
1694 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1697 ir_node *xor, *pval, *sign_extension;
1699 if (get_mode_size_bits(mode) == 32) {
1700 new_op = be_transform_node(op);
1702 new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node);
1705 pval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1706 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block,
1709 add_irn_dep(pval, get_irg_frame(irg));
1710 SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node));
1712 xor = new_rd_ia32_Xor(dbgi, irg, new_block, noreg_gp, noreg_gp,
1713 nomem, new_op, sign_extension);
1714 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1716 new_node = new_rd_ia32_Sub(dbgi, irg, new_block, noreg_gp, noreg_gp,
1717 nomem, xor, sign_extension);
1718 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1724 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
1726 ir_graph *irg = current_ir_graph;
1734 /* we have a Cmp as input */
1736 ir_node *pred = get_Proj_pred(node);
1738 flags = be_transform_node(pred);
1739 *pnc_out = get_Proj_proj(node);
1744 /* a mode_b value, we have to compare it against 0 */
1745 dbgi = get_irn_dbg_info(node);
1746 new_block = be_transform_node(get_nodes_block(node));
1747 new_op = be_transform_node(node);
1748 noreg = ia32_new_NoReg_gp(env_cg);
1749 nomem = new_NoMem();
1750 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
1751 new_op, new_op, 0, 0);
1752 *pnc_out = pn_Cmp_Lg;
1757 * Transforms a Load.
1759 * @return the created ia32 Load node
1761 static ir_node *gen_Load(ir_node *node) {
1762 ir_node *old_block = get_nodes_block(node);
1763 ir_node *block = be_transform_node(old_block);
1764 ir_node *ptr = get_Load_ptr(node);
1765 ir_node *mem = get_Load_mem(node);
1766 ir_node *new_mem = be_transform_node(mem);
1769 ir_graph *irg = current_ir_graph;
1770 dbg_info *dbgi = get_irn_dbg_info(node);
1771 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1772 ir_mode *mode = get_Load_mode(node);
1775 ia32_address_t addr;
1777 /* construct load address */
1778 memset(&addr, 0, sizeof(addr));
1779 ia32_create_address_mode(&addr, ptr, /*force=*/0);
1786 base = be_transform_node(base);
1792 index = be_transform_node(index);
1795 if (mode_is_float(mode)) {
1796 if (USE_SSE2(env_cg)) {
1797 new_node = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1799 res_mode = mode_xmm;
1801 new_node = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1803 res_mode = mode_vfp;
1806 assert(mode != mode_b);
1808 /* create a conv node with address mode for smaller modes */
1809 if(get_mode_size_bits(mode) < 32) {
1810 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1811 new_mem, noreg, mode);
1813 new_node = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1818 set_irn_pinned(new_node, get_irn_pinned(node));
1819 set_ia32_op_type(new_node, ia32_AddrModeS);
1820 set_ia32_ls_mode(new_node, mode);
1821 set_address(new_node, &addr);
1823 if(get_irn_pinned(node) == op_pin_state_floats) {
1824 add_ia32_flags(new_node, arch_irn_flags_rematerializable);
1827 /* make sure we are scheduled behind the initial IncSP/Barrier
1828 * to avoid spills being placed before it
1830 if (block == get_irg_start_block(irg)) {
1831 add_irn_dep(new_node, get_irg_frame(irg));
1834 set_ia32_exc_label(new_node,
1835 be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1836 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1841 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1842 ir_node *ptr, ir_node *other)
1849 /* we only use address mode if we're the only user of the load */
1850 if(get_irn_n_edges(node) > 1)
1853 load = get_Proj_pred(node);
1856 if(get_nodes_block(load) != block)
1859 /* Store should be attached to the load */
1860 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1862 /* store should have the same pointer as the load */
1863 if(get_Load_ptr(load) != ptr)
1866 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1867 if(other != NULL && get_nodes_block(other) == block
1868 && heights_reachable_in_block(heights, other, load))
1874 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1875 ir_node *mem, ir_node *ptr, ir_mode *mode,
1876 construct_binop_dest_func *func,
1877 construct_binop_dest_func *func8bit,
1878 match_flags_t flags)
1880 ir_node *src_block = get_nodes_block(node);
1882 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1883 ir_graph *irg = current_ir_graph;
1888 ia32_address_mode_t am;
1889 ia32_address_t *addr = &am.addr;
1890 memset(&am, 0, sizeof(am));
1892 assert(flags & match_dest_am);
1893 assert(flags & match_immediate); /* there is no destam node without... */
1894 commutative = (flags & match_commutative) != 0;
1896 if(use_dest_am(src_block, op1, mem, ptr, op2)) {
1897 build_address(&am, op1);
1898 new_op = create_immediate_or_transform(op2, 0);
1899 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
1900 build_address(&am, op2);
1901 new_op = create_immediate_or_transform(op1, 0);
1906 if(addr->base == NULL)
1907 addr->base = noreg_gp;
1908 if(addr->index == NULL)
1909 addr->index = noreg_gp;
1910 if(addr->mem == NULL)
1911 addr->mem = new_NoMem();
1913 dbgi = get_irn_dbg_info(node);
1914 block = be_transform_node(src_block);
1915 if(get_mode_size_bits(mode) == 8) {
1916 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1919 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1922 set_address(new_node, addr);
1923 set_ia32_op_type(new_node, ia32_AddrModeD);
1924 set_ia32_ls_mode(new_node, mode);
1925 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1930 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1931 ir_node *ptr, ir_mode *mode,
1932 construct_unop_dest_func *func)
1934 ir_graph *irg = current_ir_graph;
1935 ir_node *src_block = get_nodes_block(node);
1939 ia32_address_mode_t am;
1940 ia32_address_t *addr = &am.addr;
1941 memset(&am, 0, sizeof(am));
1943 if(!use_dest_am(src_block, op, mem, ptr, NULL))
1946 build_address(&am, op);
1948 dbgi = get_irn_dbg_info(node);
1949 block = be_transform_node(src_block);
1950 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1951 set_address(new_node, addr);
1952 set_ia32_op_type(new_node, ia32_AddrModeD);
1953 set_ia32_ls_mode(new_node, mode);
1954 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1959 static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) {
1960 ir_mode *mode = get_irn_mode(node);
1961 ir_node *psi_true = get_Psi_val(node, 0);
1962 ir_node *psi_default = get_Psi_default(node);
1973 ia32_address_t addr;
1975 if(get_mode_size_bits(mode) != 8)
1978 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
1980 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
1986 build_address_ptr(&addr, ptr, mem);
1988 irg = current_ir_graph;
1989 dbgi = get_irn_dbg_info(node);
1990 block = get_nodes_block(node);
1991 new_block = be_transform_node(block);
1992 cond = get_Psi_cond(node, 0);
1993 flags = get_flags_node(cond, &pnc);
1994 new_mem = be_transform_node(mem);
1995 new_node = new_rd_ia32_SetMem(dbgi, irg, new_block, addr.base,
1996 addr.index, addr.mem, flags, pnc, negated);
1997 set_address(new_node, &addr);
1998 set_ia32_op_type(new_node, ia32_AddrModeD);
1999 set_ia32_ls_mode(new_node, mode);
2000 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2005 static ir_node *try_create_dest_am(ir_node *node) {
2006 ir_node *val = get_Store_value(node);
2007 ir_node *mem = get_Store_mem(node);
2008 ir_node *ptr = get_Store_ptr(node);
2009 ir_mode *mode = get_irn_mode(val);
2010 int bits = get_mode_size_bits(mode);
2015 /* handle only GP modes for now... */
2016 if(!mode_needs_gp_reg(mode))
2020 /* store must be the only user of the val node */
2021 if(get_irn_n_edges(val) > 1)
2023 /* skip pointless convs */
2025 ir_node *conv_op = get_Conv_op(val);
2026 ir_mode *pred_mode = get_irn_mode(conv_op);
2027 if(pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
2035 /* value must be in the same block */
2036 if(get_nodes_block(node) != get_nodes_block(val))
2039 switch(get_irn_opcode(val)) {
2041 op1 = get_Add_left(val);
2042 op2 = get_Add_right(val);
2043 if(is_Const_1(op2)) {
2044 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2045 new_rd_ia32_IncMem);
2047 } else if(is_Const_Minus_1(op2)) {
2048 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2049 new_rd_ia32_DecMem);
2052 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2053 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit,
2054 match_dest_am | match_commutative |
2058 op1 = get_Sub_left(val);
2059 op2 = get_Sub_right(val);
2061 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
2064 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2065 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit,
2066 match_dest_am | match_immediate |
2070 op1 = get_And_left(val);
2071 op2 = get_And_right(val);
2072 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2073 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit,
2074 match_dest_am | match_commutative |
2078 op1 = get_Or_left(val);
2079 op2 = get_Or_right(val);
2080 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2081 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit,
2082 match_dest_am | match_commutative |
2086 op1 = get_Eor_left(val);
2087 op2 = get_Eor_right(val);
2088 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2089 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit,
2090 match_dest_am | match_commutative |
2094 op1 = get_Shl_left(val);
2095 op2 = get_Shl_right(val);
2096 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2097 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem,
2098 match_dest_am | match_immediate);
2101 op1 = get_Shr_left(val);
2102 op2 = get_Shr_right(val);
2103 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2104 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem,
2105 match_dest_am | match_immediate);
2108 op1 = get_Shrs_left(val);
2109 op2 = get_Shrs_right(val);
2110 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2111 new_rd_ia32_SarMem, new_rd_ia32_SarMem,
2112 match_dest_am | match_immediate);
2115 op1 = get_Rot_left(val);
2116 op2 = get_Rot_right(val);
2117 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2118 new_rd_ia32_RolMem, new_rd_ia32_RolMem,
2119 match_dest_am | match_immediate);
2121 /* TODO: match ROR patterns... */
2123 new_node = try_create_SetMem(val, ptr, mem);
2126 op1 = get_Minus_op(val);
2127 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
2130 /* should be lowered already */
2131 assert(mode != mode_b);
2132 op1 = get_Not_op(val);
2133 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
2139 if(new_node != NULL) {
2140 if(get_irn_pinned(new_node) != op_pin_state_pinned &&
2141 get_irn_pinned(node) == op_pin_state_pinned) {
2142 set_irn_pinned(new_node, op_pin_state_pinned);
2149 static int is_float_to_int32_conv(const ir_node *node)
2151 ir_mode *mode = get_irn_mode(node);
2155 if(get_mode_size_bits(mode) != 32 || !mode_needs_gp_reg(mode))
2160 conv_op = get_Conv_op(node);
2161 conv_mode = get_irn_mode(conv_op);
2163 if(!mode_is_float(conv_mode))
2170 * Transforms a Store.
2172 * @return the created ia32 Store node
2174 static ir_node *gen_Store(ir_node *node)
2176 ir_node *block = get_nodes_block(node);
2177 ir_node *new_block = be_transform_node(block);
2178 ir_node *ptr = get_Store_ptr(node);
2179 ir_node *val = get_Store_value(node);
2180 ir_node *mem = get_Store_mem(node);
2181 ir_graph *irg = current_ir_graph;
2182 dbg_info *dbgi = get_irn_dbg_info(node);
2183 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2184 ir_mode *mode = get_irn_mode(val);
2187 ia32_address_t addr;
2189 /* check for destination address mode */
2190 new_node = try_create_dest_am(node);
2191 if(new_node != NULL)
2194 /* construct store address */
2195 memset(&addr, 0, sizeof(addr));
2196 ia32_create_address_mode(&addr, ptr, /*force=*/0);
2198 if(addr.base == NULL) {
2201 addr.base = be_transform_node(addr.base);
2204 if(addr.index == NULL) {
2207 addr.index = be_transform_node(addr.index);
2209 addr.mem = be_transform_node(mem);
2211 if (mode_is_float(mode)) {
2212 /* convs (and strict-convs) before stores are unnecessary if the mode
2214 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2215 val = get_Conv_op(val);
2217 new_val = be_transform_node(val);
2218 if (USE_SSE2(env_cg)) {
2219 new_node = new_rd_ia32_xStore(dbgi, irg, new_block, addr.base,
2220 addr.index, addr.mem, new_val);
2222 new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base,
2223 addr.index, addr.mem, new_val, mode);
2225 } else if(is_float_to_int32_conv(val)) {
2226 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
2227 val = get_Conv_op(val);
2229 /* convs (and strict-convs) before stores are unnecessary if the mode
2231 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2232 val = get_Conv_op(val);
2234 new_val = be_transform_node(val);
2236 new_node = new_rd_ia32_vfist(dbgi, irg, new_block, addr.base,
2237 addr.index, addr.mem, new_val, trunc_mode);
2239 new_val = create_immediate_or_transform(val, 0);
2240 assert(mode != mode_b);
2242 if (get_mode_size_bits(mode) == 8) {
2243 new_node = new_rd_ia32_Store8Bit(dbgi, irg, new_block, addr.base,
2244 addr.index, addr.mem, new_val);
2246 new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
2247 addr.index, addr.mem, new_val);
2251 set_irn_pinned(new_node, get_irn_pinned(node));
2252 set_ia32_op_type(new_node, ia32_AddrModeD);
2253 set_ia32_ls_mode(new_node, mode);
2255 set_ia32_exc_label(new_node,
2256 be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
2257 set_address(new_node, &addr);
2258 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2263 static ir_node *create_Switch(ir_node *node)
2265 ir_graph *irg = current_ir_graph;
2266 dbg_info *dbgi = get_irn_dbg_info(node);
2267 ir_node *block = be_transform_node(get_nodes_block(node));
2268 ir_node *sel = get_Cond_selector(node);
2269 ir_node *new_sel = be_transform_node(sel);
2270 int switch_min = INT_MAX;
2272 const ir_edge_t *edge;
2274 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2276 /* determine the smallest switch case value */
2277 foreach_out_edge(node, edge) {
2278 ir_node *proj = get_edge_src_irn(edge);
2279 int pn = get_Proj_proj(proj);
2284 if (switch_min != 0) {
2285 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2287 /* if smallest switch case is not 0 we need an additional sub */
2288 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2289 add_ia32_am_offs_int(new_sel, -switch_min);
2290 set_ia32_op_type(new_sel, ia32_AddrModeS);
2292 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2295 new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel,
2296 get_Cond_defaultProj(node));
2297 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2302 static ir_node *gen_Cond(ir_node *node) {
2303 ir_node *block = get_nodes_block(node);
2304 ir_node *new_block = be_transform_node(block);
2305 ir_graph *irg = current_ir_graph;
2306 dbg_info *dbgi = get_irn_dbg_info(node);
2307 ir_node *sel = get_Cond_selector(node);
2308 ir_mode *sel_mode = get_irn_mode(sel);
2309 ir_node *flags = NULL;
2313 if (sel_mode != mode_b) {
2314 return create_Switch(node);
2317 /* we get flags from a cmp */
2318 flags = get_flags_node(sel, &pnc);
2320 new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2321 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2329 * Transforms a CopyB node.
2331 * @return The transformed node.
2333 static ir_node *gen_CopyB(ir_node *node) {
2334 ir_node *block = be_transform_node(get_nodes_block(node));
2335 ir_node *src = get_CopyB_src(node);
2336 ir_node *new_src = be_transform_node(src);
2337 ir_node *dst = get_CopyB_dst(node);
2338 ir_node *new_dst = be_transform_node(dst);
2339 ir_node *mem = get_CopyB_mem(node);
2340 ir_node *new_mem = be_transform_node(mem);
2341 ir_node *res = NULL;
2342 ir_graph *irg = current_ir_graph;
2343 dbg_info *dbgi = get_irn_dbg_info(node);
2344 int size = get_type_size_bytes(get_CopyB_type(node));
2347 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2348 /* then we need the size explicitly in ECX. */
2349 if (size >= 32 * 4) {
2350 rem = size & 0x3; /* size % 4 */
2353 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2354 add_irn_dep(res, get_irg_frame(irg));
2356 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
2359 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2362 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
2365 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2370 static ir_node *gen_be_Copy(ir_node *node)
2372 ir_node *new_node = be_duplicate_node(node);
2373 ir_mode *mode = get_irn_mode(new_node);
2375 if (mode_needs_gp_reg(mode)) {
2376 set_irn_mode(new_node, mode_Iu);
2382 static ir_node *create_Fucom(ir_node *node)
2384 ir_graph *irg = current_ir_graph;
2385 dbg_info *dbgi = get_irn_dbg_info(node);
2386 ir_node *block = get_nodes_block(node);
2387 ir_node *new_block = be_transform_node(block);
2388 ir_node *left = get_Cmp_left(node);
2389 ir_node *new_left = be_transform_node(left);
2390 ir_node *right = get_Cmp_right(node);
2394 if(transform_config.use_fucomi) {
2395 new_right = be_transform_node(right);
2396 new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left,
2398 set_ia32_commutative(new_node);
2399 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2401 if(transform_config.use_ftst && is_Const_null(right)) {
2402 new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left,
2405 new_right = be_transform_node(right);
2406 new_node = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2410 set_ia32_commutative(new_node);
2412 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2414 new_node = new_rd_ia32_Sahf(dbgi, irg, new_block, new_node);
2415 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2421 static ir_node *create_Ucomi(ir_node *node)
2423 ir_graph *irg = current_ir_graph;
2424 dbg_info *dbgi = get_irn_dbg_info(node);
2425 ir_node *src_block = get_nodes_block(node);
2426 ir_node *new_block = be_transform_node(src_block);
2427 ir_node *left = get_Cmp_left(node);
2428 ir_node *right = get_Cmp_right(node);
2430 ia32_address_mode_t am;
2431 ia32_address_t *addr = &am.addr;
2433 match_arguments(&am, src_block, left, right, match_commutative | match_am);
2435 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2436 addr->mem, am.new_op1, am.new_op2,
2438 set_am_attributes(new_node, &am);
2440 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2442 new_node = fix_mem_proj(new_node, &am);
2448 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2449 * to fold an and into a test node
2451 static int can_fold_test_and(ir_node *node)
2453 const ir_edge_t *edge;
2455 /** we can only have eq and lg projs */
2456 foreach_out_edge(node, edge) {
2457 ir_node *proj = get_edge_src_irn(edge);
2458 pn_Cmp pnc = get_Proj_proj(proj);
2459 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2466 static ir_node *gen_Cmp(ir_node *node)
2468 ir_graph *irg = current_ir_graph;
2469 dbg_info *dbgi = get_irn_dbg_info(node);
2470 ir_node *block = get_nodes_block(node);
2471 ir_node *new_block = be_transform_node(block);
2472 ir_node *left = get_Cmp_left(node);
2473 ir_node *right = get_Cmp_right(node);
2474 ir_mode *cmp_mode = get_irn_mode(left);
2476 ia32_address_mode_t am;
2477 ia32_address_t *addr = &am.addr;
2480 if(mode_is_float(cmp_mode)) {
2481 if (USE_SSE2(env_cg)) {
2482 return create_Ucomi(node);
2484 return create_Fucom(node);
2488 assert(mode_needs_gp_reg(cmp_mode));
2490 /* we prefer the Test instruction where possible except cases where
2491 * we can use SourceAM */
2492 cmp_unsigned = !mode_is_signed(cmp_mode);
2493 if (is_Const_0(right)) {
2495 get_irn_n_edges(left) == 1 &&
2496 can_fold_test_and(node)) {
2497 /* Test(and_left, and_right) */
2498 ir_node *and_left = get_And_left(left);
2499 ir_node *and_right = get_And_right(left);
2500 ir_mode *mode = get_irn_mode(and_left);
2502 match_arguments(&am, block, and_left, and_right, match_commutative |
2503 match_am | match_8bit_am | match_16bit_am |
2504 match_am_and_immediates | match_immediate |
2505 match_8bit | match_16bit);
2506 if (get_mode_size_bits(mode) == 8) {
2507 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2508 addr->index, addr->mem, am.new_op1,
2509 am.new_op2, am.ins_permuted,
2512 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2513 addr->index, addr->mem, am.new_op1,
2514 am.new_op2, am.ins_permuted, cmp_unsigned);
2517 match_arguments(&am, block, NULL, left, match_am | match_8bit_am |
2518 match_16bit_am | match_8bit | match_16bit);
2519 if (am.op_type == ia32_AddrModeS) {
2521 ir_node *imm_zero = try_create_Immediate(right, 0);
2522 if (get_mode_size_bits(cmp_mode) == 8) {
2523 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2524 addr->index, addr->mem, am.new_op2,
2525 imm_zero, am.ins_permuted,
2528 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2529 addr->index, addr->mem, am.new_op2,
2530 imm_zero, am.ins_permuted, cmp_unsigned);
2533 /* Test(left, left) */
2534 if (get_mode_size_bits(cmp_mode) == 8) {
2535 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2536 addr->index, addr->mem, am.new_op2,
2537 am.new_op2, am.ins_permuted,
2540 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2541 addr->index, addr->mem, am.new_op2,
2542 am.new_op2, am.ins_permuted,
2548 /* Cmp(left, right) */
2549 match_arguments(&am, block, left, right, match_commutative | match_am |
2550 match_8bit_am | match_16bit_am | match_am_and_immediates |
2551 match_immediate | match_8bit | match_16bit);
2552 if (get_mode_size_bits(cmp_mode) == 8) {
2553 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2554 addr->index, addr->mem, am.new_op1,
2555 am.new_op2, am.ins_permuted,
2558 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2559 addr->index, addr->mem, am.new_op1,
2560 am.new_op2, am.ins_permuted, cmp_unsigned);
2563 set_am_attributes(new_node, &am);
2564 assert(cmp_mode != NULL);
2565 set_ia32_ls_mode(new_node, cmp_mode);
2567 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2569 new_node = fix_mem_proj(new_node, &am);
2574 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2576 ir_graph *irg = current_ir_graph;
2577 dbg_info *dbgi = get_irn_dbg_info(node);
2578 ir_node *block = get_nodes_block(node);
2579 ir_node *new_block = be_transform_node(block);
2580 ir_node *val_true = get_Psi_val(node, 0);
2581 ir_node *val_false = get_Psi_default(node);
2583 match_flags_t match_flags;
2584 ia32_address_mode_t am;
2585 ia32_address_t *addr;
2587 assert(transform_config.use_cmov);
2588 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2592 match_flags = match_commutative | match_am | match_16bit_am |
2595 match_arguments(&am, block, val_false, val_true, match_flags);
2597 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2598 addr->mem, am.new_op1, am.new_op2, new_flags,
2599 am.ins_permuted, pnc);
2600 set_am_attributes(new_node, &am);
2602 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2604 new_node = fix_mem_proj(new_node, &am);
2611 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2612 ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
2615 ir_graph *irg = current_ir_graph;
2616 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2617 ir_node *nomem = new_NoMem();
2618 ir_mode *mode = get_irn_mode(orig_node);
2621 new_node = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
2622 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2624 /* we might need to conv the result up */
2625 if(get_mode_size_bits(mode) > 8) {
2626 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2627 nomem, new_node, mode_Bu);
2628 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2635 * Transforms a Psi node into CMov.
2637 * @return The transformed node.
2639 static ir_node *gen_Psi(ir_node *node)
2641 dbg_info *dbgi = get_irn_dbg_info(node);
2642 ir_node *block = get_nodes_block(node);
2643 ir_node *new_block = be_transform_node(block);
2644 ir_node *psi_true = get_Psi_val(node, 0);
2645 ir_node *psi_default = get_Psi_default(node);
2646 ir_node *cond = get_Psi_cond(node, 0);
2647 ir_node *flags = NULL;
2651 assert(get_Psi_n_conds(node) == 1);
2652 assert(get_irn_mode(cond) == mode_b);
2653 assert(mode_needs_gp_reg(get_irn_mode(node)));
2655 flags = get_flags_node(cond, &pnc);
2657 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2658 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
2659 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2660 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
2662 new_node = create_CMov(node, flags, pnc);
2669 * Create a conversion from x87 state register to general purpose.
2671 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2672 ir_node *block = be_transform_node(get_nodes_block(node));
2673 ir_node *op = get_Conv_op(node);
2674 ir_node *new_op = be_transform_node(op);
2675 ia32_code_gen_t *cg = env_cg;
2676 ir_graph *irg = current_ir_graph;
2677 dbg_info *dbgi = get_irn_dbg_info(node);
2678 ir_node *noreg = ia32_new_NoReg_gp(cg);
2679 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2680 ir_mode *mode = get_irn_mode(node);
2681 ir_node *fist, *load;
2684 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2685 new_NoMem(), new_op, trunc_mode);
2687 set_irn_pinned(fist, op_pin_state_floats);
2688 set_ia32_use_frame(fist);
2689 set_ia32_op_type(fist, ia32_AddrModeD);
2691 assert(get_mode_size_bits(mode) <= 32);
2692 /* exception we can only store signed 32 bit integers, so for unsigned
2693 we store a 64bit (signed) integer and load the lower bits */
2694 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2695 set_ia32_ls_mode(fist, mode_Ls);
2697 set_ia32_ls_mode(fist, mode_Is);
2699 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2702 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2704 set_irn_pinned(load, op_pin_state_floats);
2705 set_ia32_use_frame(load);
2706 set_ia32_op_type(load, ia32_AddrModeS);
2707 set_ia32_ls_mode(load, mode_Is);
2708 if(get_ia32_ls_mode(fist) == mode_Ls) {
2709 ia32_attr_t *attr = get_ia32_attr(load);
2710 attr->data.need_64bit_stackent = 1;
2712 ia32_attr_t *attr = get_ia32_attr(load);
2713 attr->data.need_32bit_stackent = 1;
2715 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2717 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2721 * Creates a x87 strict Conv by placing a Sore and a Load
2723 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2725 ir_node *block = get_nodes_block(node);
2726 ir_graph *irg = current_ir_graph;
2727 dbg_info *dbgi = get_irn_dbg_info(node);
2728 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2729 ir_node *nomem = new_NoMem();
2730 ir_node *frame = get_irg_frame(irg);
2731 ir_node *store, *load;
2734 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2736 set_ia32_use_frame(store);
2737 set_ia32_op_type(store, ia32_AddrModeD);
2738 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2740 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2742 set_ia32_use_frame(load);
2743 set_ia32_op_type(load, ia32_AddrModeS);
2744 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2746 new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2750 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2752 ir_graph *irg = current_ir_graph;
2753 ir_node *start_block = get_irg_start_block(irg);
2754 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2755 symconst, symconst_sign, val);
2756 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2762 * Create a conversion from general purpose to x87 register
2764 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2765 ir_node *src_block = get_nodes_block(node);
2766 ir_node *block = be_transform_node(src_block);
2767 ir_graph *irg = current_ir_graph;
2768 dbg_info *dbgi = get_irn_dbg_info(node);
2769 ir_node *op = get_Conv_op(node);
2770 ir_node *new_op = NULL;
2774 ir_mode *store_mode;
2780 /* fild can use source AM if the operand is a signed 32bit integer */
2781 if (src_mode == mode_Is) {
2782 ia32_address_mode_t am;
2784 match_arguments(&am, src_block, NULL, op, match_am | match_try_am);
2785 if (am.op_type == ia32_AddrModeS) {
2786 ia32_address_t *addr = &am.addr;
2788 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base,
2789 addr->index, addr->mem);
2790 new_node = new_r_Proj(irg, block, fild, mode_vfp,
2793 set_am_attributes(fild, &am);
2794 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2796 fix_mem_proj(fild, &am);
2801 if(new_op == NULL) {
2802 new_op = be_transform_node(op);
2805 noreg = ia32_new_NoReg_gp(env_cg);
2806 nomem = new_NoMem();
2807 mode = get_irn_mode(op);
2809 /* first convert to 32 bit signed if necessary */
2810 src_bits = get_mode_size_bits(src_mode);
2811 if (src_bits == 8) {
2812 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2814 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2816 } else if (src_bits < 32) {
2817 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2819 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2823 assert(get_mode_size_bits(mode) == 32);
2826 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2829 set_ia32_use_frame(store);
2830 set_ia32_op_type(store, ia32_AddrModeD);
2831 set_ia32_ls_mode(store, mode_Iu);
2833 /* exception for 32bit unsigned, do a 64bit spill+load */
2834 if(!mode_is_signed(mode)) {
2837 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2839 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2840 get_irg_frame(irg), noreg, nomem,
2843 set_ia32_use_frame(zero_store);
2844 set_ia32_op_type(zero_store, ia32_AddrModeD);
2845 add_ia32_am_offs_int(zero_store, 4);
2846 set_ia32_ls_mode(zero_store, mode_Iu);
2851 store = new_rd_Sync(dbgi, irg, block, 2, in);
2852 store_mode = mode_Ls;
2854 store_mode = mode_Is;
2858 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2860 set_ia32_use_frame(fild);
2861 set_ia32_op_type(fild, ia32_AddrModeS);
2862 set_ia32_ls_mode(fild, store_mode);
2864 new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2870 * Create a conversion from one integer mode into another one
2872 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2873 dbg_info *dbgi, ir_node *block, ir_node *op,
2876 ir_graph *irg = current_ir_graph;
2877 int src_bits = get_mode_size_bits(src_mode);
2878 int tgt_bits = get_mode_size_bits(tgt_mode);
2879 ir_node *new_block = be_transform_node(block);
2881 ir_mode *smaller_mode;
2883 ia32_address_mode_t am;
2884 ia32_address_t *addr = &am.addr;
2886 if (src_bits < tgt_bits) {
2887 smaller_mode = src_mode;
2888 smaller_bits = src_bits;
2890 smaller_mode = tgt_mode;
2891 smaller_bits = tgt_bits;
2894 #ifdef DEBUG_libfirm
2896 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
2901 match_arguments(&am, block, NULL, op, match_8bit | match_16bit | match_am |
2902 match_8bit_am | match_16bit_am);
2903 if (smaller_bits == 8) {
2904 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2905 addr->index, addr->mem, am.new_op2,
2908 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2909 addr->index, addr->mem, am.new_op2,
2912 set_am_attributes(new_node, &am);
2913 /* match_arguments assume that out-mode = in-mode, this isn't true here
2915 set_ia32_ls_mode(new_node, smaller_mode);
2916 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2917 new_node = fix_mem_proj(new_node, &am);
2922 * Transforms a Conv node.
2924 * @return The created ia32 Conv node
2926 static ir_node *gen_Conv(ir_node *node) {
2927 ir_node *block = get_nodes_block(node);
2928 ir_node *new_block = be_transform_node(block);
2929 ir_node *op = get_Conv_op(node);
2930 ir_node *new_op = NULL;
2931 ir_graph *irg = current_ir_graph;
2932 dbg_info *dbgi = get_irn_dbg_info(node);
2933 ir_mode *src_mode = get_irn_mode(op);
2934 ir_mode *tgt_mode = get_irn_mode(node);
2935 int src_bits = get_mode_size_bits(src_mode);
2936 int tgt_bits = get_mode_size_bits(tgt_mode);
2937 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2938 ir_node *nomem = new_rd_NoMem(irg);
2939 ir_node *res = NULL;
2941 if (src_mode == mode_b) {
2942 assert(mode_is_int(tgt_mode));
2943 /* nothing to do, we already model bools as 0/1 ints */
2944 return be_transform_node(op);
2947 if (src_mode == tgt_mode) {
2948 if (get_Conv_strict(node)) {
2949 if (USE_SSE2(env_cg)) {
2950 /* when we are in SSE mode, we can kill all strict no-op conversion */
2951 return be_transform_node(op);
2954 /* this should be optimized already, but who knows... */
2955 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2956 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2957 return be_transform_node(op);
2961 if (mode_is_float(src_mode)) {
2962 new_op = be_transform_node(op);
2963 /* we convert from float ... */
2964 if (mode_is_float(tgt_mode)) {
2965 if(src_mode == mode_E && tgt_mode == mode_D
2966 && !get_Conv_strict(node)) {
2967 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2972 if (USE_SSE2(env_cg)) {
2973 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2974 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2976 set_ia32_ls_mode(res, tgt_mode);
2978 if(get_Conv_strict(node)) {
2979 res = gen_x87_strict_conv(tgt_mode, new_op);
2980 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2983 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2988 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2989 if (USE_SSE2(env_cg)) {
2990 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2992 set_ia32_ls_mode(res, src_mode);
2994 return gen_x87_fp_to_gp(node);
2998 /* we convert from int ... */
2999 if (mode_is_float(tgt_mode)) {
3001 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
3002 if (USE_SSE2(env_cg)) {
3003 new_op = be_transform_node(op);
3004 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
3006 set_ia32_ls_mode(res, tgt_mode);
3008 res = gen_x87_gp_to_fp(node, src_mode);
3009 if(get_Conv_strict(node)) {
3010 res = gen_x87_strict_conv(tgt_mode, res);
3011 SET_IA32_ORIG_NODE(get_Proj_pred(res),
3012 ia32_get_old_node_name(env_cg, node));
3016 } else if(tgt_mode == mode_b) {
3017 /* mode_b lowering already took care that we only have 0/1 values */
3018 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3019 src_mode, tgt_mode));
3020 return be_transform_node(op);
3023 if (src_bits == tgt_bits) {
3024 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3025 src_mode, tgt_mode));
3026 return be_transform_node(op);
3029 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
3037 static int check_immediate_constraint(long val, char immediate_constraint_type)
3039 switch (immediate_constraint_type) {
3043 return val >= 0 && val <= 32;
3045 return val >= 0 && val <= 63;
3047 return val >= -128 && val <= 127;
3049 return val == 0xff || val == 0xffff;
3051 return val >= 0 && val <= 3;
3053 return val >= 0 && val <= 255;
3055 return val >= 0 && val <= 127;
3059 panic("Invalid immediate constraint found");
3063 static ir_node *try_create_Immediate(ir_node *node,
3064 char immediate_constraint_type)
3067 tarval *offset = NULL;
3068 int offset_sign = 0;
3070 ir_entity *symconst_ent = NULL;
3071 int symconst_sign = 0;
3073 ir_node *cnst = NULL;
3074 ir_node *symconst = NULL;
3077 mode = get_irn_mode(node);
3078 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
3082 if(is_Minus(node)) {
3084 node = get_Minus_op(node);
3087 if(is_Const(node)) {
3090 offset_sign = minus;
3091 } else if(is_SymConst(node)) {
3094 symconst_sign = minus;
3095 } else if(is_Add(node)) {
3096 ir_node *left = get_Add_left(node);
3097 ir_node *right = get_Add_right(node);
3098 if(is_Const(left) && is_SymConst(right)) {
3101 symconst_sign = minus;
3102 offset_sign = minus;
3103 } else if(is_SymConst(left) && is_Const(right)) {
3106 symconst_sign = minus;
3107 offset_sign = minus;
3109 } else if(is_Sub(node)) {
3110 ir_node *left = get_Sub_left(node);
3111 ir_node *right = get_Sub_right(node);
3112 if(is_Const(left) && is_SymConst(right)) {
3115 symconst_sign = !minus;
3116 offset_sign = minus;
3117 } else if(is_SymConst(left) && is_Const(right)) {
3120 symconst_sign = minus;
3121 offset_sign = !minus;
3128 offset = get_Const_tarval(cnst);
3129 if(tarval_is_long(offset)) {
3130 val = get_tarval_long(offset);
3132 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
3137 if(!check_immediate_constraint(val, immediate_constraint_type))
3140 if(symconst != NULL) {
3141 if(immediate_constraint_type != 0) {
3142 /* we need full 32bits for symconsts */
3146 /* unfortunately the assembler/linker doesn't support -symconst */
3150 if(get_SymConst_kind(symconst) != symconst_addr_ent)
3152 symconst_ent = get_SymConst_entity(symconst);
3154 if(cnst == NULL && symconst == NULL)
3157 if(offset_sign && offset != NULL) {
3158 offset = tarval_neg(offset);
3161 new_node = create_Immediate(symconst_ent, symconst_sign, val);
3166 static ir_node *create_immediate_or_transform(ir_node *node,
3167 char immediate_constraint_type)
3169 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
3170 if (new_node == NULL) {
3171 new_node = be_transform_node(node);
3176 static const arch_register_req_t no_register_req = {
3177 arch_register_req_type_none,
3178 NULL, /* regclass */
3179 NULL, /* limit bitset */
3181 0 /* different pos */
3185 * An assembler constraint.
3187 typedef struct constraint_t constraint_t;
3188 struct constraint_t {
3191 const arch_register_req_t **out_reqs;
3193 const arch_register_req_t *req;
3194 unsigned immediate_possible;
3195 char immediate_type;
3198 static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
3200 int immediate_possible = 0;
3201 char immediate_type = 0;
3202 unsigned limited = 0;
3203 const arch_register_class_t *cls = NULL;
3204 ir_graph *irg = current_ir_graph;
3205 struct obstack *obst = get_irg_obstack(irg);
3206 arch_register_req_t *req;
3207 unsigned *limited_ptr = NULL;
3211 /* TODO: replace all the asserts with nice error messages */
3214 /* a memory constraint: no need to do anything in backend about it
3215 * (the dependencies are already respected by the memory edge of
3217 constraint->req = &no_register_req;
3229 assert(cls == NULL ||
3230 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3231 cls = &ia32_reg_classes[CLASS_ia32_gp];
3232 limited |= 1 << REG_EAX;
3235 assert(cls == NULL ||
3236 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3237 cls = &ia32_reg_classes[CLASS_ia32_gp];
3238 limited |= 1 << REG_EBX;
3241 assert(cls == NULL ||
3242 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3243 cls = &ia32_reg_classes[CLASS_ia32_gp];
3244 limited |= 1 << REG_ECX;
3247 assert(cls == NULL ||
3248 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3249 cls = &ia32_reg_classes[CLASS_ia32_gp];
3250 limited |= 1 << REG_EDX;
3253 assert(cls == NULL ||
3254 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3255 cls = &ia32_reg_classes[CLASS_ia32_gp];
3256 limited |= 1 << REG_EDI;
3259 assert(cls == NULL ||
3260 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3261 cls = &ia32_reg_classes[CLASS_ia32_gp];
3262 limited |= 1 << REG_ESI;
3265 case 'q': /* q means lower part of the regs only, this makes no
3266 * difference to Q for us (we only assigne whole registers) */
3267 assert(cls == NULL ||
3268 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3269 cls = &ia32_reg_classes[CLASS_ia32_gp];
3270 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3274 assert(cls == NULL ||
3275 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3276 cls = &ia32_reg_classes[CLASS_ia32_gp];
3277 limited |= 1 << REG_EAX | 1 << REG_EDX;
3280 assert(cls == NULL ||
3281 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3282 cls = &ia32_reg_classes[CLASS_ia32_gp];
3283 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3284 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3291 assert(cls == NULL);
3292 cls = &ia32_reg_classes[CLASS_ia32_gp];
3298 /* TODO: mark values so the x87 simulator knows about t and u */
3299 assert(cls == NULL);
3300 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3305 assert(cls == NULL);
3306 /* TODO: check that sse2 is supported */
3307 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3317 assert(!immediate_possible);
3318 immediate_possible = 1;
3319 immediate_type = *c;
3323 assert(!immediate_possible);
3324 immediate_possible = 1;
3328 assert(!immediate_possible && cls == NULL);
3329 immediate_possible = 1;
3330 cls = &ia32_reg_classes[CLASS_ia32_gp];
3343 assert(constraint->is_in && "can only specify same constraint "
3346 sscanf(c, "%d%n", &same_as, &p);
3354 /* memory constraint no need to do anything in backend about it
3355 * (the dependencies are already respected by the memory edge of
3357 constraint->req = &no_register_req;
3360 case 'E': /* no float consts yet */
3361 case 'F': /* no float consts yet */
3362 case 's': /* makes no sense on x86 */
3363 case 'X': /* we can't support that in firm */
3366 case '<': /* no autodecrement on x86 */
3367 case '>': /* no autoincrement on x86 */
3368 case 'C': /* sse constant not supported yet */
3369 case 'G': /* 80387 constant not supported yet */
3370 case 'y': /* we don't support mmx registers yet */
3371 case 'Z': /* not available in 32 bit mode */
3372 case 'e': /* not available in 32 bit mode */
3373 panic("unsupported asm constraint '%c' found in (%+F)",
3374 *c, current_ir_graph);
3377 panic("unknown asm constraint '%c' found in (%+F)", *c,
3385 const arch_register_req_t *other_constr;
3387 assert(cls == NULL && "same as and register constraint not supported");
3388 assert(!immediate_possible && "same as and immediate constraint not "
3390 assert(same_as < constraint->n_outs && "wrong constraint number in "
3391 "same_as constraint");
3393 other_constr = constraint->out_reqs[same_as];
3395 req = obstack_alloc(obst, sizeof(req[0]));
3396 req->cls = other_constr->cls;
3397 req->type = arch_register_req_type_should_be_same;
3398 req->limited = NULL;
3399 req->other_same = 1U << pos;
3400 req->other_different = 0;
3402 /* switch constraints. This is because in firm we have same_as
3403 * constraints on the output constraints while in the gcc asm syntax
3404 * they are specified on the input constraints */
3405 constraint->req = other_constr;
3406 constraint->out_reqs[same_as] = req;
3407 constraint->immediate_possible = 0;
3411 if(immediate_possible && cls == NULL) {
3412 cls = &ia32_reg_classes[CLASS_ia32_gp];
3414 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3415 assert(cls != NULL);
3417 if(immediate_possible) {
3418 assert(constraint->is_in
3419 && "immediate make no sense for output constraints");
3421 /* todo: check types (no float input on 'r' constrained in and such... */
3424 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3425 limited_ptr = (unsigned*) (req+1);
3427 req = obstack_alloc(obst, sizeof(req[0]));
3429 memset(req, 0, sizeof(req[0]));
3432 req->type = arch_register_req_type_limited;
3433 *limited_ptr = limited;
3434 req->limited = limited_ptr;
3436 req->type = arch_register_req_type_normal;
3440 constraint->req = req;
3441 constraint->immediate_possible = immediate_possible;
3442 constraint->immediate_type = immediate_type;
3445 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3452 panic("Clobbers not supported yet");
3455 static int is_memory_op(const ir_asm_constraint *constraint)
3457 ident *id = constraint->constraint;
3458 const char *str = get_id_str(id);
3461 for(c = str; *c != '\0'; ++c) {
3470 * generates code for a ASM node
3472 static ir_node *gen_ASM(ir_node *node)
3475 ir_graph *irg = current_ir_graph;
3476 ir_node *block = get_nodes_block(node);
3477 ir_node *new_block = be_transform_node(block);
3478 dbg_info *dbgi = get_irn_dbg_info(node);
3482 int n_out_constraints;
3484 const arch_register_req_t **out_reg_reqs;
3485 const arch_register_req_t **in_reg_reqs;
3486 ia32_asm_reg_t *register_map;
3487 unsigned reg_map_size = 0;
3488 struct obstack *obst;
3489 const ir_asm_constraint *in_constraints;
3490 const ir_asm_constraint *out_constraints;
3492 constraint_t parsed_constraint;
3494 arity = get_irn_arity(node);
3495 in = alloca(arity * sizeof(in[0]));
3496 memset(in, 0, arity * sizeof(in[0]));
3498 n_out_constraints = get_ASM_n_output_constraints(node);
3499 n_clobbers = get_ASM_n_clobbers(node);
3500 out_arity = n_out_constraints + n_clobbers;
3502 in_constraints = get_ASM_input_constraints(node);
3503 out_constraints = get_ASM_output_constraints(node);
3504 clobbers = get_ASM_clobbers(node);
3506 /* construct output constraints */
3507 obst = get_irg_obstack(irg);
3508 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
3509 parsed_constraint.out_reqs = out_reg_reqs;
3510 parsed_constraint.n_outs = n_out_constraints;
3511 parsed_constraint.is_in = 0;
3513 for(i = 0; i < out_arity; ++i) {
3516 if(i < n_out_constraints) {
3517 const ir_asm_constraint *constraint = &out_constraints[i];
3518 c = get_id_str(constraint->constraint);
3519 parse_asm_constraint(i, &parsed_constraint, c);
3521 if(constraint->pos > reg_map_size)
3522 reg_map_size = constraint->pos;
3524 ident *glob_id = clobbers [i - n_out_constraints];
3525 c = get_id_str(glob_id);
3526 parse_clobber(node, i, &parsed_constraint, c);
3529 out_reg_reqs[i] = parsed_constraint.req;
3532 /* construct input constraints */
3533 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
3534 parsed_constraint.is_in = 1;
3535 for(i = 0; i < arity; ++i) {
3536 const ir_asm_constraint *constraint = &in_constraints[i];
3537 ident *constr_id = constraint->constraint;
3538 const char *c = get_id_str(constr_id);
3540 parse_asm_constraint(i, &parsed_constraint, c);
3541 in_reg_reqs[i] = parsed_constraint.req;
3543 if(constraint->pos > reg_map_size)
3544 reg_map_size = constraint->pos;
3546 if(parsed_constraint.immediate_possible) {
3547 ir_node *pred = get_irn_n(node, i);
3548 char imm_type = parsed_constraint.immediate_type;
3549 ir_node *immediate = try_create_Immediate(pred, imm_type);
3551 if(immediate != NULL) {
3558 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
3559 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
3561 for(i = 0; i < n_out_constraints; ++i) {
3562 const ir_asm_constraint *constraint = &out_constraints[i];
3563 unsigned pos = constraint->pos;
3565 assert(pos < reg_map_size);
3566 register_map[pos].use_input = 0;
3567 register_map[pos].valid = 1;
3568 register_map[pos].memory = is_memory_op(constraint);
3569 register_map[pos].inout_pos = i;
3570 register_map[pos].mode = constraint->mode;
3573 /* transform inputs */
3574 for(i = 0; i < arity; ++i) {
3575 const ir_asm_constraint *constraint = &in_constraints[i];
3576 unsigned pos = constraint->pos;
3577 ir_node *pred = get_irn_n(node, i);
3578 ir_node *transformed;
3580 assert(pos < reg_map_size);
3581 register_map[pos].use_input = 1;
3582 register_map[pos].valid = 1;
3583 register_map[pos].memory = is_memory_op(constraint);
3584 register_map[pos].inout_pos = i;
3585 register_map[pos].mode = constraint->mode;
3590 transformed = be_transform_node(pred);
3591 in[i] = transformed;
3594 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
3595 get_ASM_text(node), register_map);
3597 set_ia32_out_req_all(new_node, out_reg_reqs);
3598 set_ia32_in_req_all(new_node, in_reg_reqs);
3600 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3605 /********************************************
3608 * | |__ ___ _ __ ___ __| | ___ ___
3609 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3610 * | |_) | __/ | | | (_) | (_| | __/\__ \
3611 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3613 ********************************************/
3616 * Transforms a FrameAddr into an ia32 Add.
3618 static ir_node *gen_be_FrameAddr(ir_node *node) {
3619 ir_node *block = be_transform_node(get_nodes_block(node));
3620 ir_node *op = be_get_FrameAddr_frame(node);
3621 ir_node *new_op = be_transform_node(op);
3622 ir_graph *irg = current_ir_graph;
3623 dbg_info *dbgi = get_irn_dbg_info(node);
3624 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3627 new_node = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3628 set_ia32_frame_ent(new_node, arch_get_frame_entity(env_cg->arch_env, node));
3629 set_ia32_use_frame(new_node);
3631 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3637 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3639 static ir_node *gen_be_Return(ir_node *node) {
3640 ir_graph *irg = current_ir_graph;
3641 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3642 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3643 ir_entity *ent = get_irg_entity(irg);
3644 ir_type *tp = get_entity_type(ent);
3649 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3650 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3653 int pn_ret_val, pn_ret_mem, arity, i;
3655 assert(ret_val != NULL);
3656 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3657 return be_duplicate_node(node);
3660 res_type = get_method_res_type(tp, 0);
3662 if (! is_Primitive_type(res_type)) {
3663 return be_duplicate_node(node);
3666 mode = get_type_mode(res_type);
3667 if (! mode_is_float(mode)) {
3668 return be_duplicate_node(node);
3671 assert(get_method_n_ress(tp) == 1);
3673 pn_ret_val = get_Proj_proj(ret_val);
3674 pn_ret_mem = get_Proj_proj(ret_mem);
3676 /* get the Barrier */
3677 barrier = get_Proj_pred(ret_val);
3679 /* get result input of the Barrier */
3680 ret_val = get_irn_n(barrier, pn_ret_val);
3681 new_ret_val = be_transform_node(ret_val);
3683 /* get memory input of the Barrier */
3684 ret_mem = get_irn_n(barrier, pn_ret_mem);
3685 new_ret_mem = be_transform_node(ret_mem);
3687 frame = get_irg_frame(irg);
3689 dbgi = get_irn_dbg_info(barrier);
3690 block = be_transform_node(get_nodes_block(barrier));
3692 noreg = ia32_new_NoReg_gp(env_cg);
3694 /* store xmm0 onto stack */
3695 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3696 new_ret_mem, new_ret_val);
3697 set_ia32_ls_mode(sse_store, mode);
3698 set_ia32_op_type(sse_store, ia32_AddrModeD);
3699 set_ia32_use_frame(sse_store);
3701 /* load into x87 register */
3702 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3703 set_ia32_op_type(fld, ia32_AddrModeS);
3704 set_ia32_use_frame(fld);
3706 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3707 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3709 /* create a new barrier */
3710 arity = get_irn_arity(barrier);
3711 in = alloca(arity * sizeof(in[0]));
3712 for (i = 0; i < arity; ++i) {
3715 if (i == pn_ret_val) {
3717 } else if (i == pn_ret_mem) {
3720 ir_node *in = get_irn_n(barrier, i);
3721 new_in = be_transform_node(in);
3726 new_barrier = new_ir_node(dbgi, irg, block,
3727 get_irn_op(barrier), get_irn_mode(barrier),
3729 copy_node_attr(barrier, new_barrier);
3730 be_duplicate_deps(barrier, new_barrier);
3731 be_set_transformed_node(barrier, new_barrier);
3732 mark_irn_visited(barrier);
3734 /* transform normally */
3735 return be_duplicate_node(node);
3739 * Transform a be_AddSP into an ia32_SubSP.
3741 static ir_node *gen_be_AddSP(ir_node *node)
3743 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3744 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3746 return gen_binop(node, sp, sz, new_rd_ia32_SubSP, match_am);
3750 * Transform a be_SubSP into an ia32_AddSP
3752 static ir_node *gen_be_SubSP(ir_node *node)
3754 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3755 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3757 return gen_binop(node, sp, sz, new_rd_ia32_AddSP, match_am);
3761 * This function just sets the register for the Unknown node
3762 * as this is not done during register allocation because Unknown
3763 * is an "ignore" node.
3765 static ir_node *gen_Unknown(ir_node *node) {
3766 ir_mode *mode = get_irn_mode(node);
3768 if (mode_is_float(mode)) {
3769 if (USE_SSE2(env_cg)) {
3770 return ia32_new_Unknown_xmm(env_cg);
3772 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3773 ir_graph *irg = current_ir_graph;
3774 dbg_info *dbgi = get_irn_dbg_info(node);
3775 ir_node *block = get_irg_start_block(irg);
3776 return new_rd_ia32_vfldz(dbgi, irg, block);
3778 } else if (mode_needs_gp_reg(mode)) {
3779 return ia32_new_Unknown_gp(env_cg);
3781 panic("unsupported Unknown-Mode");
3787 * Change some phi modes
3789 static ir_node *gen_Phi(ir_node *node) {
3790 ir_node *block = be_transform_node(get_nodes_block(node));
3791 ir_graph *irg = current_ir_graph;
3792 dbg_info *dbgi = get_irn_dbg_info(node);
3793 ir_mode *mode = get_irn_mode(node);
3796 if(mode_needs_gp_reg(mode)) {
3797 /* we shouldn't have any 64bit stuff around anymore */
3798 assert(get_mode_size_bits(mode) <= 32);
3799 /* all integer operations are on 32bit registers now */
3801 } else if(mode_is_float(mode)) {
3802 if (USE_SSE2(env_cg)) {
3809 /* phi nodes allow loops, so we use the old arguments for now
3810 * and fix this later */
3811 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3812 get_irn_in(node) + 1);
3813 copy_node_attr(node, phi);
3814 be_duplicate_deps(node, phi);
3816 be_set_transformed_node(node, phi);
3817 be_enqueue_preds(node);
3825 static ir_node *gen_IJmp(ir_node *node)
3827 ir_node *block = get_nodes_block(node);
3828 ir_node *new_block = be_transform_node(block);
3829 ir_graph *irg = current_ir_graph;
3830 dbg_info *dbgi = get_irn_dbg_info(node);
3831 ir_node *op = get_IJmp_target(node);
3833 ia32_address_mode_t am;
3834 ia32_address_t *addr = &am.addr;
3836 assert(get_irn_mode(op) == mode_P);
3838 match_arguments(&am, block, NULL, op,
3839 match_am | match_8bit_am | match_16bit_am |
3840 match_immediate | match_8bit | match_16bit);
3842 new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index,
3843 addr->mem, am.new_op2);
3844 set_am_attributes(new_node, &am);
3845 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3847 new_node = fix_mem_proj(new_node, &am);
3853 /**********************************************************************
3856 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3857 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3858 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3859 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3861 **********************************************************************/
3863 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3865 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3868 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3869 ir_node *val, ir_node *mem);
3872 * Transforms a lowered Load into a "real" one.
3874 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3876 ir_node *block = be_transform_node(get_nodes_block(node));
3877 ir_node *ptr = get_irn_n(node, 0);
3878 ir_node *new_ptr = be_transform_node(ptr);
3879 ir_node *mem = get_irn_n(node, 1);
3880 ir_node *new_mem = be_transform_node(mem);
3881 ir_graph *irg = current_ir_graph;
3882 dbg_info *dbgi = get_irn_dbg_info(node);
3883 ir_mode *mode = get_ia32_ls_mode(node);
3884 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3887 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3889 set_ia32_op_type(new_op, ia32_AddrModeS);
3890 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3891 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3892 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3893 if (is_ia32_am_sc_sign(node))
3894 set_ia32_am_sc_sign(new_op);
3895 set_ia32_ls_mode(new_op, mode);
3896 if (is_ia32_use_frame(node)) {
3897 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3898 set_ia32_use_frame(new_op);
3901 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3907 * Transforms a lowered Store into a "real" one.
3909 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3911 ir_node *block = be_transform_node(get_nodes_block(node));
3912 ir_node *ptr = get_irn_n(node, 0);
3913 ir_node *new_ptr = be_transform_node(ptr);
3914 ir_node *val = get_irn_n(node, 1);
3915 ir_node *new_val = be_transform_node(val);
3916 ir_node *mem = get_irn_n(node, 2);
3917 ir_node *new_mem = be_transform_node(mem);
3918 ir_graph *irg = current_ir_graph;
3919 dbg_info *dbgi = get_irn_dbg_info(node);
3920 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3921 ir_mode *mode = get_ia32_ls_mode(node);
3925 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3927 am_offs = get_ia32_am_offs_int(node);
3928 add_ia32_am_offs_int(new_op, am_offs);
3930 set_ia32_op_type(new_op, ia32_AddrModeD);
3931 set_ia32_ls_mode(new_op, mode);
3932 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3933 set_ia32_use_frame(new_op);
3935 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3940 static ir_node *gen_ia32_l_ShlDep(ir_node *node)
3942 ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_left);
3943 ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_right);
3945 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
3946 match_immediate | match_mode_neutral);
3949 static ir_node *gen_ia32_l_ShrDep(ir_node *node)
3951 ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_left);
3952 ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_right);
3953 return gen_shift_binop(node, left, right, new_rd_ia32_Shr,
3957 static ir_node *gen_ia32_l_SarDep(ir_node *node)
3959 ir_node *left = get_irn_n(node, n_ia32_l_SarDep_left);
3960 ir_node *right = get_irn_n(node, n_ia32_l_SarDep_right);
3961 return gen_shift_binop(node, left, right, new_rd_ia32_Sar,
3965 static ir_node *gen_ia32_l_Add(ir_node *node) {
3966 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3967 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3968 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add,
3969 match_commutative | match_am | match_immediate |
3970 match_mode_neutral);
3972 if(is_Proj(lowered)) {
3973 lowered = get_Proj_pred(lowered);
3975 assert(is_ia32_Add(lowered));
3976 set_irn_mode(lowered, mode_T);
3982 static ir_node *gen_ia32_l_Adc(ir_node *node)
3984 return gen_binop_flags(node, new_rd_ia32_Adc,
3985 match_commutative | match_am | match_immediate |
3986 match_mode_neutral);
3990 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3992 * @param node The node to transform
3993 * @return the created ia32 vfild node
3995 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3996 return gen_lowered_Load(node, new_rd_ia32_vfild);
4000 * Transforms an ia32_l_Load into a "real" ia32_Load node
4002 * @param node The node to transform
4003 * @return the created ia32 Load node
4005 static ir_node *gen_ia32_l_Load(ir_node *node) {
4006 return gen_lowered_Load(node, new_rd_ia32_Load);
4010 * Transforms an ia32_l_Store into a "real" ia32_Store node
4012 * @param node The node to transform
4013 * @return the created ia32 Store node
4015 static ir_node *gen_ia32_l_Store(ir_node *node) {
4016 return gen_lowered_Store(node, new_rd_ia32_Store);
4020 * Transforms a l_vfist into a "real" vfist node.
4022 * @param node The node to transform
4023 * @return the created ia32 vfist node
4025 static ir_node *gen_ia32_l_vfist(ir_node *node) {
4026 ir_node *block = be_transform_node(get_nodes_block(node));
4027 ir_node *ptr = get_irn_n(node, 0);
4028 ir_node *new_ptr = be_transform_node(ptr);
4029 ir_node *val = get_irn_n(node, 1);
4030 ir_node *new_val = be_transform_node(val);
4031 ir_node *mem = get_irn_n(node, 2);
4032 ir_node *new_mem = be_transform_node(mem);
4033 ir_graph *irg = current_ir_graph;
4034 dbg_info *dbgi = get_irn_dbg_info(node);
4035 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4036 ir_mode *mode = get_ia32_ls_mode(node);
4037 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
4041 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
4042 new_val, trunc_mode);
4044 am_offs = get_ia32_am_offs_int(node);
4045 add_ia32_am_offs_int(new_op, am_offs);
4047 set_ia32_op_type(new_op, ia32_AddrModeD);
4048 set_ia32_ls_mode(new_op, mode);
4049 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
4050 set_ia32_use_frame(new_op);
4052 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
4058 * Transforms a l_MulS into a "real" MulS node.
4060 * @return the created ia32 Mul node
4062 static ir_node *gen_ia32_l_Mul(ir_node *node) {
4063 ir_node *left = get_binop_left(node);
4064 ir_node *right = get_binop_right(node);
4066 return gen_binop(node, left, right, new_rd_ia32_Mul,
4067 match_commutative | match_am | match_mode_neutral);
4071 * Transforms a l_IMulS into a "real" IMul1OPS node.
4073 * @return the created ia32 IMul1OP node
4075 static ir_node *gen_ia32_l_IMul(ir_node *node) {
4076 ir_node *left = get_binop_left(node);
4077 ir_node *right = get_binop_right(node);
4079 return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
4080 match_commutative | match_am | match_mode_neutral);
4083 static ir_node *gen_ia32_l_Sub(ir_node *node) {
4084 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
4085 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
4086 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub,
4087 match_am | match_immediate | match_mode_neutral);
4089 if(is_Proj(lowered)) {
4090 lowered = get_Proj_pred(lowered);
4092 assert(is_ia32_Sub(lowered));
4093 set_irn_mode(lowered, mode_T);
4099 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
4100 return gen_binop_flags(node, new_rd_ia32_Sbb,
4101 match_am | match_immediate | match_mode_neutral);
4105 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
4106 * op1 - target to be shifted
4107 * op2 - contains bits to be shifted into target
4109 * Only op3 can be an immediate.
4111 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
4112 ir_node *low, ir_node *count)
4114 ir_node *block = get_nodes_block(node);
4115 ir_node *new_block = be_transform_node(block);
4116 ir_graph *irg = current_ir_graph;
4117 dbg_info *dbgi = get_irn_dbg_info(node);
4118 ir_node *new_high = be_transform_node(high);
4119 ir_node *new_low = be_transform_node(low);
4123 /* the shift amount can be any mode that is bigger than 5 bits, since all
4124 * other bits are ignored anyway */
4125 while (is_Conv(count) && get_irn_n_edges(count) == 1) {
4126 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
4127 count = get_Conv_op(count);
4129 new_count = create_immediate_or_transform(count, 0);
4131 if (is_ia32_l_ShlD(node)) {
4132 new_node = new_rd_ia32_ShlD(dbgi, irg, new_block, new_high, new_low,
4135 new_node = new_rd_ia32_ShrD(dbgi, irg, new_block, new_high, new_low,
4138 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
4143 static ir_node *gen_ia32_l_ShlD(ir_node *node)
4145 ir_node *high = get_irn_n(node, n_ia32_l_ShlD_high);
4146 ir_node *low = get_irn_n(node, n_ia32_l_ShlD_low);
4147 ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
4148 return gen_lowered_64bit_shifts(node, high, low, count);
4151 static ir_node *gen_ia32_l_ShrD(ir_node *node)
4153 ir_node *high = get_irn_n(node, n_ia32_l_ShrD_high);
4154 ir_node *low = get_irn_n(node, n_ia32_l_ShrD_low);
4155 ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
4156 return gen_lowered_64bit_shifts(node, high, low, count);
4160 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
4162 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
4163 ir_node *block = be_transform_node(get_nodes_block(node));
4164 ir_node *val = get_irn_n(node, 1);
4165 ir_node *new_val = be_transform_node(val);
4166 ia32_code_gen_t *cg = env_cg;
4167 ir_node *res = NULL;
4168 ir_graph *irg = current_ir_graph;
4170 ir_node *noreg, *new_ptr, *new_mem;
4177 mem = get_irn_n(node, 2);
4178 new_mem = be_transform_node(mem);
4179 ptr = get_irn_n(node, 0);
4180 new_ptr = be_transform_node(ptr);
4181 noreg = ia32_new_NoReg_gp(cg);
4182 dbgi = get_irn_dbg_info(node);
4184 /* Store x87 -> MEM */
4185 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
4186 get_ia32_ls_mode(node));
4187 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4188 set_ia32_use_frame(res);
4189 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
4190 set_ia32_op_type(res, ia32_AddrModeD);
4192 /* Load MEM -> SSE */
4193 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
4194 get_ia32_ls_mode(node));
4195 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4196 set_ia32_use_frame(res);
4197 set_ia32_op_type(res, ia32_AddrModeS);
4198 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
4204 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
4206 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
4207 ir_node *block = be_transform_node(get_nodes_block(node));
4208 ir_node *val = get_irn_n(node, 1);
4209 ir_node *new_val = be_transform_node(val);
4210 ia32_code_gen_t *cg = env_cg;
4211 ir_graph *irg = current_ir_graph;
4212 ir_node *res = NULL;
4213 ir_entity *fent = get_ia32_frame_ent(node);
4214 ir_mode *lsmode = get_ia32_ls_mode(node);
4216 ir_node *noreg, *new_ptr, *new_mem;
4220 if (! USE_SSE2(cg)) {
4221 /* SSE unit is not used -> skip this node. */
4225 ptr = get_irn_n(node, 0);
4226 new_ptr = be_transform_node(ptr);
4227 mem = get_irn_n(node, 2);
4228 new_mem = be_transform_node(mem);
4229 noreg = ia32_new_NoReg_gp(cg);
4230 dbgi = get_irn_dbg_info(node);
4232 /* Store SSE -> MEM */
4233 if (is_ia32_xLoad(skip_Proj(new_val))) {
4234 ir_node *ld = skip_Proj(new_val);
4236 /* we can vfld the value directly into the fpu */
4237 fent = get_ia32_frame_ent(ld);
4238 ptr = get_irn_n(ld, 0);
4239 offs = get_ia32_am_offs_int(ld);
4241 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
4243 set_ia32_frame_ent(res, fent);
4244 set_ia32_use_frame(res);
4245 set_ia32_ls_mode(res, lsmode);
4246 set_ia32_op_type(res, ia32_AddrModeD);
4250 /* Load MEM -> x87 */
4251 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4252 set_ia32_frame_ent(res, fent);
4253 set_ia32_use_frame(res);
4254 add_ia32_am_offs_int(res, offs);
4255 set_ia32_op_type(res, ia32_AddrModeS);
4256 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4261 /*********************************************************
4264 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
4265 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
4266 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4267 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4269 *********************************************************/
4272 * the BAD transformer.
4274 static ir_node *bad_transform(ir_node *node) {
4275 panic("No transform function for %+F available.\n", node);
4280 * Transform the Projs of an AddSP.
4282 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4283 ir_node *block = be_transform_node(get_nodes_block(node));
4284 ir_node *pred = get_Proj_pred(node);
4285 ir_node *new_pred = be_transform_node(pred);
4286 ir_graph *irg = current_ir_graph;
4287 dbg_info *dbgi = get_irn_dbg_info(node);
4288 long proj = get_Proj_proj(node);
4290 if (proj == pn_be_AddSP_sp) {
4291 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4292 pn_ia32_SubSP_stack);
4293 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4295 } else if(proj == pn_be_AddSP_res) {
4296 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4297 pn_ia32_SubSP_addr);
4298 } else if (proj == pn_be_AddSP_M) {
4299 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4303 return new_rd_Unknown(irg, get_irn_mode(node));
4307 * Transform the Projs of a SubSP.
4309 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4310 ir_node *block = be_transform_node(get_nodes_block(node));
4311 ir_node *pred = get_Proj_pred(node);
4312 ir_node *new_pred = be_transform_node(pred);
4313 ir_graph *irg = current_ir_graph;
4314 dbg_info *dbgi = get_irn_dbg_info(node);
4315 long proj = get_Proj_proj(node);
4317 if (proj == pn_be_SubSP_sp) {
4318 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4319 pn_ia32_AddSP_stack);
4320 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4322 } else if (proj == pn_be_SubSP_M) {
4323 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4327 return new_rd_Unknown(irg, get_irn_mode(node));
4331 * Transform and renumber the Projs from a Load.
4333 static ir_node *gen_Proj_Load(ir_node *node) {
4335 ir_node *block = be_transform_node(get_nodes_block(node));
4336 ir_node *pred = get_Proj_pred(node);
4337 ir_graph *irg = current_ir_graph;
4338 dbg_info *dbgi = get_irn_dbg_info(node);
4339 long proj = get_Proj_proj(node);
4342 /* loads might be part of source address mode matches, so we don't
4343 transform the ProjMs yet (with the exception of loads whose result is
4346 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4349 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4351 /* this is needed, because sometimes we have loops that are only
4352 reachable through the ProjM */
4353 be_enqueue_preds(node);
4354 /* do it in 2 steps, to silence firm verifier */
4355 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4356 set_Proj_proj(res, pn_ia32_Load_M);
4360 /* renumber the proj */
4361 new_pred = be_transform_node(pred);
4362 if (is_ia32_Load(new_pred)) {
4363 if (proj == pn_Load_res) {
4364 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4366 } else if (proj == pn_Load_M) {
4367 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4370 } else if(is_ia32_Conv_I2I(new_pred)
4371 || is_ia32_Conv_I2I8Bit(new_pred)) {
4372 set_irn_mode(new_pred, mode_T);
4373 if (proj == pn_Load_res) {
4374 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4375 } else if (proj == pn_Load_M) {
4376 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4378 } else if (is_ia32_xLoad(new_pred)) {
4379 if (proj == pn_Load_res) {
4380 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4382 } else if (proj == pn_Load_M) {
4383 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4386 } else if (is_ia32_vfld(new_pred)) {
4387 if (proj == pn_Load_res) {
4388 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4390 } else if (proj == pn_Load_M) {
4391 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4395 /* can happen for ProJMs when source address mode happened for the
4398 /* however it should not be the result proj, as that would mean the
4399 load had multiple users and should not have been used for
4401 if(proj != pn_Load_M) {
4402 panic("internal error: transformed node not a Load");
4404 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4408 return new_rd_Unknown(irg, get_irn_mode(node));
4412 * Transform and renumber the Projs from a DivMod like instruction.
4414 static ir_node *gen_Proj_DivMod(ir_node *node) {
4415 ir_node *block = be_transform_node(get_nodes_block(node));
4416 ir_node *pred = get_Proj_pred(node);
4417 ir_node *new_pred = be_transform_node(pred);
4418 ir_graph *irg = current_ir_graph;
4419 dbg_info *dbgi = get_irn_dbg_info(node);
4420 ir_mode *mode = get_irn_mode(node);
4421 long proj = get_Proj_proj(node);
4423 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4425 switch (get_irn_opcode(pred)) {
4429 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4431 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4439 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4441 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4449 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4450 case pn_DivMod_res_div:
4451 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4452 case pn_DivMod_res_mod:
4453 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4463 return new_rd_Unknown(irg, mode);
4467 * Transform and renumber the Projs from a CopyB.
4469 static ir_node *gen_Proj_CopyB(ir_node *node) {
4470 ir_node *block = be_transform_node(get_nodes_block(node));
4471 ir_node *pred = get_Proj_pred(node);
4472 ir_node *new_pred = be_transform_node(pred);
4473 ir_graph *irg = current_ir_graph;
4474 dbg_info *dbgi = get_irn_dbg_info(node);
4475 ir_mode *mode = get_irn_mode(node);
4476 long proj = get_Proj_proj(node);
4479 case pn_CopyB_M_regular:
4480 if (is_ia32_CopyB_i(new_pred)) {
4481 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4482 } else if (is_ia32_CopyB(new_pred)) {
4483 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4491 return new_rd_Unknown(irg, mode);
4495 * Transform and renumber the Projs from a Quot.
4497 static ir_node *gen_Proj_Quot(ir_node *node) {
4498 ir_node *block = be_transform_node(get_nodes_block(node));
4499 ir_node *pred = get_Proj_pred(node);
4500 ir_node *new_pred = be_transform_node(pred);
4501 ir_graph *irg = current_ir_graph;
4502 dbg_info *dbgi = get_irn_dbg_info(node);
4503 ir_mode *mode = get_irn_mode(node);
4504 long proj = get_Proj_proj(node);
4508 if (is_ia32_xDiv(new_pred)) {
4509 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4510 } else if (is_ia32_vfdiv(new_pred)) {
4511 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4515 if (is_ia32_xDiv(new_pred)) {
4516 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4517 } else if (is_ia32_vfdiv(new_pred)) {
4518 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4526 return new_rd_Unknown(irg, mode);
4530 * Transform the Thread Local Storage Proj.
4532 static ir_node *gen_Proj_tls(ir_node *node) {
4533 ir_node *block = be_transform_node(get_nodes_block(node));
4534 ir_graph *irg = current_ir_graph;
4535 dbg_info *dbgi = NULL;
4536 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4541 static ir_node *gen_be_Call(ir_node *node) {
4542 ir_node *res = be_duplicate_node(node);
4543 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4548 static ir_node *gen_be_IncSP(ir_node *node) {
4549 ir_node *res = be_duplicate_node(node);
4550 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4556 * Transform the Projs from a be_Call.
4558 static ir_node *gen_Proj_be_Call(ir_node *node) {
4559 ir_node *block = be_transform_node(get_nodes_block(node));
4560 ir_node *call = get_Proj_pred(node);
4561 ir_node *new_call = be_transform_node(call);
4562 ir_graph *irg = current_ir_graph;
4563 dbg_info *dbgi = get_irn_dbg_info(node);
4564 ir_type *method_type = be_Call_get_type(call);
4565 int n_res = get_method_n_ress(method_type);
4566 long proj = get_Proj_proj(node);
4567 ir_mode *mode = get_irn_mode(node);
4569 const arch_register_class_t *cls;
4571 /* The following is kinda tricky: If we're using SSE, then we have to
4572 * move the result value of the call in floating point registers to an
4573 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4574 * after the call, we have to make sure to correctly make the
4575 * MemProj and the result Proj use these 2 nodes
4577 if (proj == pn_be_Call_M_regular) {
4578 // get new node for result, are we doing the sse load/store hack?
4579 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4580 ir_node *call_res_new;
4581 ir_node *call_res_pred = NULL;
4583 if (call_res != NULL) {
4584 call_res_new = be_transform_node(call_res);
4585 call_res_pred = get_Proj_pred(call_res_new);
4588 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4589 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4590 pn_be_Call_M_regular);
4592 assert(is_ia32_xLoad(call_res_pred));
4593 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4597 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4598 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4599 && USE_SSE2(env_cg)) {
4601 ir_node *frame = get_irg_frame(irg);
4602 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4604 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4607 /* in case there is no memory output: create one to serialize the copy
4609 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4610 pn_be_Call_M_regular);
4611 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4612 pn_be_Call_first_res);
4614 /* store st(0) onto stack */
4615 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4617 set_ia32_op_type(fstp, ia32_AddrModeD);
4618 set_ia32_use_frame(fstp);
4620 /* load into SSE register */
4621 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4623 set_ia32_op_type(sse_load, ia32_AddrModeS);
4624 set_ia32_use_frame(sse_load);
4626 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4632 /* transform call modes */
4633 if (mode_is_data(mode)) {
4634 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4638 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4642 * Transform the Projs from a Cmp.
4644 static ir_node *gen_Proj_Cmp(ir_node *node)
4647 panic("not all mode_b nodes are lowered");
4650 /* normally Cmps are processed when looking at Cond nodes, but this case
4651 * can happen in complicated Psi conditions */
4652 dbg_info *dbgi = get_irn_dbg_info(node);
4653 ir_node *block = get_nodes_block(node);
4654 ir_node *new_block = be_transform_node(block);
4655 ir_node *cmp = get_Proj_pred(node);
4656 ir_node *new_cmp = be_transform_node(cmp);
4657 long pnc = get_Proj_proj(node);
4660 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node, 0);
4667 * Transform and potentially renumber Proj nodes.
4669 static ir_node *gen_Proj(ir_node *node) {
4670 ir_graph *irg = current_ir_graph;
4671 dbg_info *dbgi = get_irn_dbg_info(node);
4672 ir_node *pred = get_Proj_pred(node);
4673 long proj = get_Proj_proj(node);
4675 if (is_Store(pred)) {
4676 if (proj == pn_Store_M) {
4677 return be_transform_node(pred);
4680 return new_r_Bad(irg);
4682 } else if (is_Load(pred)) {
4683 return gen_Proj_Load(node);
4684 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4685 return gen_Proj_DivMod(node);
4686 } else if (is_CopyB(pred)) {
4687 return gen_Proj_CopyB(node);
4688 } else if (is_Quot(pred)) {
4689 return gen_Proj_Quot(node);
4690 } else if (be_is_SubSP(pred)) {
4691 return gen_Proj_be_SubSP(node);
4692 } else if (be_is_AddSP(pred)) {
4693 return gen_Proj_be_AddSP(node);
4694 } else if (be_is_Call(pred)) {
4695 return gen_Proj_be_Call(node);
4696 } else if (is_Cmp(pred)) {
4697 return gen_Proj_Cmp(node);
4698 } else if (get_irn_op(pred) == op_Start) {
4699 if (proj == pn_Start_X_initial_exec) {
4700 ir_node *block = get_nodes_block(pred);
4703 /* we exchange the ProjX with a jump */
4704 block = be_transform_node(block);
4705 jump = new_rd_Jmp(dbgi, irg, block);
4708 if (node == be_get_old_anchor(anchor_tls)) {
4709 return gen_Proj_tls(node);
4712 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4716 ir_node *new_pred = be_transform_node(pred);
4717 ir_node *block = be_transform_node(get_nodes_block(node));
4718 ir_mode *mode = get_irn_mode(node);
4719 if (mode_needs_gp_reg(mode)) {
4720 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4721 get_Proj_proj(node));
4722 #ifdef DEBUG_libfirm
4723 new_proj->node_nr = node->node_nr;
4729 return be_duplicate_node(node);
4733 * Enters all transform functions into the generic pointer
4735 static void register_transformers(void)
4739 /* first clear the generic function pointer for all ops */
4740 clear_irp_opcodes_generic_func();
4742 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4743 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4781 /* transform ops from intrinsic lowering */
4797 GEN(ia32_l_X87toSSE);
4798 GEN(ia32_l_SSEtoX87);
4804 /* we should never see these nodes */
4819 /* handle generic backend nodes */
4828 op_Mulh = get_op_Mulh();
4837 * Pre-transform all unknown and noreg nodes.
4839 static void ia32_pretransform_node(void *arch_cg) {
4840 ia32_code_gen_t *cg = arch_cg;
4842 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4843 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4844 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4845 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4846 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4847 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4852 * Walker, checks if all ia32 nodes producing more than one result have
4853 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4855 static void add_missing_keep_walker(ir_node *node, void *data)
4858 unsigned found_projs = 0;
4859 const ir_edge_t *edge;
4860 ir_mode *mode = get_irn_mode(node);
4865 if(!is_ia32_irn(node))
4868 n_outs = get_ia32_n_res(node);
4871 if(is_ia32_SwitchJmp(node))
4874 assert(n_outs < (int) sizeof(unsigned) * 8);
4875 foreach_out_edge(node, edge) {
4876 ir_node *proj = get_edge_src_irn(edge);
4877 int pn = get_Proj_proj(proj);
4879 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4880 found_projs |= 1 << pn;
4884 /* are keeps missing? */
4886 for(i = 0; i < n_outs; ++i) {
4889 const arch_register_req_t *req;
4890 const arch_register_class_t *class;
4892 if(found_projs & (1 << i)) {
4896 req = get_ia32_out_req(node, i);
4901 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4905 block = get_nodes_block(node);
4906 in[0] = new_r_Proj(current_ir_graph, block, node,
4907 arch_register_class_mode(class), i);
4908 if(last_keep != NULL) {
4909 be_Keep_add_node(last_keep, class, in[0]);
4911 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4912 if(sched_is_scheduled(node)) {
4913 sched_add_after(node, last_keep);
4920 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4923 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4925 ir_graph *irg = be_get_birg_irg(cg->birg);
4926 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4929 /* do the transformation */
4930 void ia32_transform_graph(ia32_code_gen_t *cg) {
4932 ir_graph *irg = cg->irg;
4933 int opt_arch = cg->isa->opt_arch;
4934 int arch = cg->isa->arch;
4936 /* TODO: look at cpu and fill transform config in with that... */
4937 transform_config.use_incdec = 1;
4938 transform_config.use_sse2 = 0;
4939 transform_config.use_ffreep = ARCH_ATHLON(opt_arch);
4940 transform_config.use_ftst = 0;
4941 transform_config.use_femms = ARCH_ATHLON(opt_arch) && ARCH_MMX(arch) && ARCH_AMD(arch);
4942 transform_config.use_fucomi = 1;
4943 transform_config.use_cmov = IS_P6_ARCH(arch);
4945 register_transformers();
4947 initial_fpcw = NULL;
4949 heights = heights_new(irg);
4950 ia32_calculate_non_address_mode_nodes(cg->birg);
4952 /* the transform phase is not safe for CSE (yet) because several nodes get
4953 * attributes set after their creation */
4954 cse_last = get_opt_cse();
4957 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4959 set_opt_cse(cse_last);
4961 ia32_free_non_address_mode_nodes();
4962 heights_free(heights);
4966 void ia32_init_transform(void)
4968 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");