2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
99 extern ir_op *get_op_Mulh(void);
101 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
102 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
103 ir_node *op1, ir_node *op2);
105 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
106 ir_node *block, ir_node *op1, ir_node *op2);
108 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
109 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
112 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
113 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
115 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
116 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 ir_node *op1, ir_node *op2, ir_node *fpcw);
119 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
120 ir_node *block, ir_node *op);
122 /****************************************************************************************************
124 * | | | | / _| | | (_)
125 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
126 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
127 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
128 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
130 ****************************************************************************************************/
132 static ir_node *try_create_Immediate(ir_node *node,
133 char immediate_constraint_type);
135 static ir_node *create_immediate_or_transform(ir_node *node,
136 char immediate_constraint_type);
138 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
139 dbg_info *dbgi, ir_node *block,
140 ir_node *op, ir_node *orig_node);
143 * Return true if a mode can be stored in the GP register set
145 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
146 if(mode == mode_fpcw)
148 if(get_mode_size_bits(mode) > 32)
150 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
154 * creates a unique ident by adding a number to a tag
156 * @param tag the tag string, must contain a %d if a number
159 static ident *unique_id(const char *tag)
161 static unsigned id = 0;
164 snprintf(str, sizeof(str), tag, ++id);
165 return new_id_from_str(str);
169 * Get a primitive type for a mode.
171 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
173 pmap_entry *e = pmap_find(types, mode);
178 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
179 res = new_type_primitive(new_id_from_str(buf), mode);
180 set_type_alignment_bytes(res, 16);
181 pmap_insert(types, mode, res);
189 * Get an atomic entity that is initialized with a tarval
191 static ir_entity *ia32_get_entity_for_tv(ia32_isa_t *isa, ir_node *cnst)
193 tarval *tv = get_Const_tarval(cnst);
194 pmap_entry *e = pmap_find(isa->tv_ent, tv);
199 ir_mode *mode = get_irn_mode(cnst);
200 ir_type *tp = get_Const_type(cnst);
201 if (tp == firm_unknown_type)
202 tp = get_prim_type(isa->types, mode);
204 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
206 set_entity_ld_ident(res, get_entity_ident(res));
207 set_entity_visibility(res, visibility_local);
208 set_entity_variability(res, variability_constant);
209 set_entity_allocation(res, allocation_static);
211 /* we create a new entity here: It's initialization must resist on the
213 rem = current_ir_graph;
214 current_ir_graph = get_const_code_irg();
215 set_atomic_ent_value(res, new_Const_type(tv, tp));
216 current_ir_graph = rem;
218 pmap_insert(isa->tv_ent, tv, res);
226 static int is_Const_0(ir_node *node) {
227 return is_Const(node) && is_Const_null(node);
230 static int is_Const_1(ir_node *node) {
231 return is_Const(node) && is_Const_one(node);
234 static int is_Const_Minus_1(ir_node *node) {
235 return is_Const(node) && is_Const_all_one(node);
239 * Transforms a Const.
241 static ir_node *gen_Const(ir_node *node) {
242 ir_graph *irg = current_ir_graph;
243 ir_node *old_block = get_nodes_block(node);
244 ir_node *block = be_transform_node(old_block);
245 dbg_info *dbgi = get_irn_dbg_info(node);
246 ir_mode *mode = get_irn_mode(node);
248 if (mode_is_float(mode)) {
250 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
251 ir_node *nomem = new_NoMem();
255 if (USE_SSE2(env_cg)) {
256 if (is_Const_null(node)) {
257 load = new_rd_ia32_xZero(dbgi, irg, block);
258 set_ia32_ls_mode(load, mode);
261 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
263 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
265 set_ia32_op_type(load, ia32_AddrModeS);
266 set_ia32_am_sc(load, floatent);
267 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
268 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
271 if (is_Const_null(node)) {
272 load = new_rd_ia32_vfldz(dbgi, irg, block);
274 } else if (is_Const_one(node)) {
275 load = new_rd_ia32_vfld1(dbgi, irg, block);
278 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
280 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
281 set_ia32_op_type(load, ia32_AddrModeS);
282 set_ia32_am_sc(load, floatent);
283 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
284 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
286 set_ia32_ls_mode(load, mode);
289 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
291 /* Const Nodes before the initial IncSP are a bad idea, because
292 * they could be spilled and we have no SP ready at that point yet.
293 * So add a dependency to the initial frame pointer calculation to
294 * avoid that situation.
296 if (get_irg_start_block(irg) == block) {
297 add_irn_dep(load, get_irg_frame(irg));
300 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
304 tarval *tv = get_Const_tarval(node);
307 tv = tarval_convert_to(tv, mode_Iu);
309 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
311 panic("couldn't convert constant tarval (%+F)", node);
313 val = get_tarval_long(tv);
315 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
316 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
319 get_ia32_flags(cnst) | arch_irn_flags_modify_flags);
323 if (get_irg_start_block(irg) == block) {
324 add_irn_dep(cnst, get_irg_frame(irg));
332 * Transforms a SymConst.
334 static ir_node *gen_SymConst(ir_node *node) {
335 ir_graph *irg = current_ir_graph;
336 ir_node *old_block = get_nodes_block(node);
337 ir_node *block = be_transform_node(old_block);
338 dbg_info *dbgi = get_irn_dbg_info(node);
339 ir_mode *mode = get_irn_mode(node);
342 if (mode_is_float(mode)) {
343 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
344 ir_node *nomem = new_NoMem();
346 if (USE_SSE2(env_cg))
347 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
349 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
350 set_ia32_am_sc(cnst, get_SymConst_entity(node));
351 set_ia32_use_frame(cnst);
355 if(get_SymConst_kind(node) != symconst_addr_ent) {
356 panic("backend only support symconst_addr_ent (at %+F)", node);
358 entity = get_SymConst_entity(node);
359 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
362 /* Const Nodes before the initial IncSP are a bad idea, because
363 * they could be spilled and we have no SP ready at that point yet
365 if (get_irg_start_block(irg) == block) {
366 add_irn_dep(cnst, get_irg_frame(irg));
369 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
374 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
375 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
376 static const struct {
378 const char *ent_name;
379 const char *cnst_str;
382 } names [ia32_known_const_max] = {
383 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
384 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
385 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
386 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
387 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
389 static ir_entity *ent_cache[ia32_known_const_max];
391 const char *tp_name, *ent_name, *cnst_str;
399 ent_name = names[kct].ent_name;
400 if (! ent_cache[kct]) {
401 tp_name = names[kct].tp_name;
402 cnst_str = names[kct].cnst_str;
404 switch (names[kct].mode) {
405 case 0: mode = mode_Iu; break;
406 case 1: mode = mode_Lu; break;
407 default: mode = mode_F; break;
409 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
410 tp = new_type_primitive(new_id_from_str(tp_name), mode);
411 /* set the specified alignment */
412 set_type_alignment_bytes(tp, names[kct].align);
414 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
416 set_entity_ld_ident(ent, get_entity_ident(ent));
417 set_entity_visibility(ent, visibility_local);
418 set_entity_variability(ent, variability_constant);
419 set_entity_allocation(ent, allocation_static);
421 /* we create a new entity here: It's initialization must resist on the
423 rem = current_ir_graph;
424 current_ir_graph = get_const_code_irg();
425 cnst = new_Const(mode, tv);
426 current_ir_graph = rem;
428 set_atomic_ent_value(ent, cnst);
430 /* cache the entry */
431 ent_cache[kct] = ent;
434 return ent_cache[kct];
439 * Prints the old node name on cg obst and returns a pointer to it.
441 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
442 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
444 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
445 obstack_1grow(isa->name_obst, 0);
446 return obstack_finish(isa->name_obst);
450 int use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
458 load = get_Proj_pred(node);
459 pn = get_Proj_proj(node);
460 if(!is_Load(load) || pn != pn_Load_res)
462 if(get_nodes_block(load) != block)
464 /* we only use address mode if we're the only user of the load */
465 if(get_irn_n_edges(node) > 1)
468 mode = get_irn_mode(node);
469 if(!mode_needs_gp_reg(mode))
471 if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
474 /* don't do AM if other node inputs depend on the load (via mem-proj) */
475 if(other != NULL && get_nodes_block(other) == block
476 && heights_reachable_in_block(heights, other, load))
482 typedef struct ia32_address_mode_t ia32_address_mode_t;
483 struct ia32_address_mode_t {
487 ia32_op_type_t op_type;
494 static void build_address(ia32_address_mode_t *am, ir_node *node)
496 ia32_address_t *addr = &am->addr;
497 ir_node *load = get_Proj_pred(node);
498 ir_node *ptr = get_Load_ptr(load);
499 ir_node *mem = get_Load_mem(load);
500 ir_node *new_mem = be_transform_node(mem);
504 am->ls_mode = get_Load_mode(load);
505 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
507 /* construct load address */
508 ia32_create_address_mode(addr, ptr, 0);
513 base = ia32_new_NoReg_gp(env_cg);
515 base = be_transform_node(base);
519 index = ia32_new_NoReg_gp(env_cg);
521 index = be_transform_node(index);
529 static void set_address(ir_node *node, ia32_address_t *addr)
531 set_ia32_am_scale(node, addr->scale);
532 set_ia32_am_sc(node, addr->symconst_ent);
533 set_ia32_am_offs_int(node, addr->offset);
534 if(addr->symconst_sign)
535 set_ia32_am_sc_sign(node);
537 set_ia32_use_frame(node);
538 set_ia32_frame_ent(node, addr->frame_entity);
541 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
543 set_address(node, &am->addr);
545 set_ia32_op_type(node, am->op_type);
546 set_ia32_ls_mode(node, am->ls_mode);
548 set_ia32_commutative(node);
552 match_commutative = 1 << 0,
553 match_am_and_immediates = 1 << 1,
554 match_no_am = 1 << 2,
555 match_8_16_bit_am = 1 << 3,
556 match_no_immediate = 1 << 4
559 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
560 ir_node *op1, ir_node *op2, match_flags_t flags)
562 ia32_address_t *addr = &am->addr;
563 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
568 int use_am_and_immediates;
571 memset(am, 0, sizeof(am[0]));
573 commutative = (flags & match_commutative) != 0;
574 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
575 use_am = ! (flags & match_no_am);
576 use_immediate = !(flags & match_no_immediate);
579 assert(!commutative || op1 != NULL);
581 if(!(flags & match_8_16_bit_am)
583 && get_mode_size_bits(get_irn_mode(op1)) < 32)
586 new_op2 = (use_immediate ? try_create_Immediate(op2, 0) : NULL);
587 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
588 build_address(am, op2);
589 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
591 am->op_type = ia32_AddrModeS;
592 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
593 use_am && use_source_address_mode(block, op1, op2)) {
594 build_address(am, op1);
595 if(new_op2 != NULL) {
598 new_op1 = be_transform_node(op2);
602 am->op_type = ia32_AddrModeS;
604 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
606 new_op2 = be_transform_node(op2);
607 am->op_type = ia32_Normal;
609 if(addr->base == NULL)
610 addr->base = noreg_gp;
611 if(addr->index == NULL)
612 addr->index = noreg_gp;
613 if(addr->mem == NULL)
614 addr->mem = new_NoMem();
616 am->new_op1 = new_op1;
617 am->new_op2 = new_op2;
618 am->commutative = commutative;
621 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
623 ir_graph *irg = current_ir_graph;
627 if(am->mem_proj == NULL)
630 /* we have to create a mode_T so the old MemProj can attach to us */
631 mode = get_irn_mode(node);
632 load = get_Proj_pred(am->mem_proj);
634 mark_irn_visited(load);
635 be_set_transformed_node(load, node);
638 set_irn_mode(node, mode_T);
639 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
646 * Construct a standard binary operation, set AM and immediate if required.
648 * @param op1 The first operand
649 * @param op2 The second operand
650 * @param func The node constructor function
651 * @return The constructed ia32 node.
653 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
654 construct_binop_func *func, int commutative)
656 ir_node *src_block = get_nodes_block(node);
657 ir_node *block = be_transform_node(src_block);
658 ir_graph *irg = current_ir_graph;
659 dbg_info *dbgi = get_irn_dbg_info(node);
661 ia32_address_mode_t am;
662 ia32_address_t *addr = &am.addr;
663 match_flags_t flags = 0;
666 flags |= match_commutative;
668 match_arguments(&am, src_block, op1, op2, flags);
670 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
671 am.new_op1, am.new_op2);
672 set_am_attributes(new_node, &am);
673 /* we can't use source address mode anymore when using immediates */
674 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
675 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
676 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
678 new_node = fix_mem_proj(new_node, &am);
684 * Construct a standard binary operation, set AM and immediate if required.
686 * @param op1 The first operand
687 * @param op2 The second operand
688 * @param func The node constructor function
689 * @return The constructed ia32 node.
691 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
692 construct_binop_func *func)
694 ir_node *block = be_transform_node(get_nodes_block(node));
695 ir_node *new_op1 = be_transform_node(op1);
696 ir_node *new_op2 = be_transform_node(op2);
697 ir_node *new_node = NULL;
698 dbg_info *dbgi = get_irn_dbg_info(node);
699 ir_graph *irg = current_ir_graph;
700 ir_mode *mode = get_irn_mode(node);
701 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
702 ir_node *nomem = new_NoMem();
704 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1,
706 if (is_op_commutative(get_irn_op(node))) {
707 set_ia32_commutative(new_node);
709 set_ia32_ls_mode(new_node, mode);
711 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
716 static ir_node *get_fpcw(void)
719 if(initial_fpcw != NULL)
722 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
723 &ia32_fp_cw_regs[REG_FPCW]);
724 initial_fpcw = be_transform_node(fpcw);
730 * Construct a standard binary operation, set AM and immediate if required.
732 * @param op1 The first operand
733 * @param op2 The second operand
734 * @param func The node constructor function
735 * @return The constructed ia32 node.
737 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
738 construct_binop_float_func *func)
740 ir_node *block = be_transform_node(get_nodes_block(node));
741 ir_node *new_op1 = be_transform_node(op1);
742 ir_node *new_op2 = be_transform_node(op2);
743 ir_node *new_node = NULL;
744 dbg_info *dbgi = get_irn_dbg_info(node);
745 ir_graph *irg = current_ir_graph;
746 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
747 ir_node *nomem = new_NoMem();
749 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1, new_op2,
751 if (is_op_commutative(get_irn_op(node))) {
752 set_ia32_commutative(new_node);
755 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
761 * Construct a shift/rotate binary operation, sets AM and immediate if required.
763 * @param op1 The first operand
764 * @param op2 The second operand
765 * @param func The node constructor function
766 * @return The constructed ia32 node.
768 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
769 construct_shift_func *func)
771 dbg_info *dbgi = get_irn_dbg_info(node);
772 ir_graph *irg = current_ir_graph;
773 ir_node *block = get_nodes_block(node);
774 ir_node *new_block = be_transform_node(block);
775 ir_node *new_op1 = be_transform_node(op1);
776 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
779 assert(! mode_is_float(get_irn_mode(node))
780 && "Shift/Rotate with float not supported");
782 res = func(dbgi, irg, new_block, new_op1, new_op2);
783 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
785 /* lowered shift instruction may have a dependency operand, handle it here */
786 if (get_irn_arity(node) == 3) {
787 /* we have a dependency */
788 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
789 add_irn_dep(res, new_dep);
797 * Construct a standard unary operation, set AM and immediate if required.
799 * @param op The operand
800 * @param func The node constructor function
801 * @return The constructed ia32 node.
803 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
805 ir_node *block = be_transform_node(get_nodes_block(node));
806 ir_node *new_op = be_transform_node(op);
807 ir_node *new_node = NULL;
808 ir_graph *irg = current_ir_graph;
809 dbg_info *dbgi = get_irn_dbg_info(node);
811 new_node = func(dbgi, irg, block, new_op);
813 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
818 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
819 ia32_address_t *addr)
821 ir_graph *irg = current_ir_graph;
822 ir_node *base = addr->base;
823 ir_node *index = addr->index;
827 base = ia32_new_NoReg_gp(env_cg);
829 base = be_transform_node(base);
833 index = ia32_new_NoReg_gp(env_cg);
835 index = be_transform_node(index);
838 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
839 set_address(res, addr);
844 static int am_has_immediates(const ia32_address_t *addr)
846 return addr->offset != 0 || addr->symconst_ent != NULL
847 || addr->frame_entity || addr->use_frame;
851 * Creates an ia32 Add.
853 * @return the created ia32 Add node
855 static ir_node *gen_Add(ir_node *node) {
856 ir_node *block = be_transform_node(get_nodes_block(node));
857 ir_node *op1 = get_Add_left(node);
858 ir_node *op2 = get_Add_right(node);
861 ir_graph *irg = current_ir_graph;
862 dbg_info *dbgi = get_irn_dbg_info(node);
863 ir_mode *mode = get_irn_mode(node);
864 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
865 ir_node *src_block = get_nodes_block(node);
866 ir_node *add_immediate_op;
868 ia32_address_mode_t am;
870 if (mode_is_float(mode)) {
871 if (USE_SSE2(env_cg))
872 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
874 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
879 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
880 * 1. Add with immediate -> Lea
881 * 2. Add with possible source address mode -> Add
882 * 3. Otherwise -> Lea
884 memset(&addr, 0, sizeof(addr));
885 ia32_create_address_mode(&addr, node, 1);
886 add_immediate_op = NULL;
888 if(addr.base == NULL && addr.index == NULL) {
889 new_op = new_rd_ia32_Const(dbgi, irg, block, addr.symconst_ent,
890 addr.symconst_sign, addr.offset);
891 add_irn_dep(new_op, get_irg_frame(irg));
892 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
895 /* add with immediate? */
896 if(addr.index == NULL) {
897 add_immediate_op = addr.base;
898 } else if(addr.base == NULL && addr.scale == 0) {
899 add_immediate_op = addr.index;
902 if(add_immediate_op != NULL) {
903 if(!am_has_immediates(&addr)) {
905 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
908 return be_transform_node(add_immediate_op);
911 new_op = create_lea_from_address(dbgi, block, &addr);
912 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
916 /* test if we can use source address mode */
917 memset(&am, 0, sizeof(am));
919 if(use_source_address_mode(src_block, op2, op1)) {
920 build_address(&am, op2);
921 new_op1 = be_transform_node(op1);
922 } else if(use_source_address_mode(src_block, op1, op2)) {
923 build_address(&am, op1);
924 new_op1 = be_transform_node(op2);
926 /* construct an Add with source address mode */
927 if(new_op1 != NULL) {
928 ia32_address_t *am_addr = &am.addr;
929 new_op = new_rd_ia32_Add(dbgi, irg, block, am_addr->base, am_addr->index,
930 am_addr->mem, new_op1, noreg);
931 set_address(new_op, am_addr);
932 set_ia32_op_type(new_op, ia32_AddrModeS);
933 set_ia32_ls_mode(new_op, am.ls_mode);
934 set_ia32_commutative(new_op);
935 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
937 new_op = fix_mem_proj(new_op, &am);
942 /* otherwise construct a lea */
943 new_op = create_lea_from_address(dbgi, block, &addr);
944 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
949 * Creates an ia32 Mul.
951 * @return the created ia32 Mul node
953 static ir_node *gen_Mul(ir_node *node) {
954 ir_node *op1 = get_Mul_left(node);
955 ir_node *op2 = get_Mul_right(node);
956 ir_mode *mode = get_irn_mode(node);
958 if (mode_is_float(mode)) {
959 if (USE_SSE2(env_cg))
960 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
962 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
966 for the lower 32bit of the result it doesn't matter whether we use
967 signed or unsigned multiplication so we use IMul as it has fewer
970 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
974 * Creates an ia32 Mulh.
975 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
976 * this result while Mul returns the lower 32 bit.
978 * @return the created ia32 Mulh node
980 static ir_node *gen_Mulh(ir_node *node) {
981 ir_node *block = be_transform_node(get_nodes_block(node));
982 ir_node *op1 = get_irn_n(node, 0);
983 ir_node *new_op1 = be_transform_node(op1);
984 ir_node *op2 = get_irn_n(node, 1);
985 ir_node *new_op2 = be_transform_node(op2);
986 ir_graph *irg = current_ir_graph;
987 dbg_info *dbgi = get_irn_dbg_info(node);
988 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
989 ir_mode *mode = get_irn_mode(node);
990 ir_node *proj_EDX, *res;
992 assert(!mode_is_float(mode) && "Mulh with float not supported");
993 if (mode_is_signed(mode)) {
994 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_NoMem(),
997 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(), new_op1,
1001 set_ia32_commutative(res);
1003 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1011 * Creates an ia32 And.
1013 * @return The created ia32 And node
1015 static ir_node *gen_And(ir_node *node) {
1016 ir_node *op1 = get_And_left(node);
1017 ir_node *op2 = get_And_right(node);
1018 assert(! mode_is_float(get_irn_mode(node)));
1020 /* is it a zero extension? */
1021 if (is_Const(op2)) {
1022 tarval *tv = get_Const_tarval(op2);
1023 long v = get_tarval_long(tv);
1025 if (v == 0xFF || v == 0xFFFF) {
1026 dbg_info *dbgi = get_irn_dbg_info(node);
1027 ir_node *block = get_nodes_block(node);
1034 assert(v == 0xFFFF);
1037 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1043 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
1049 * Creates an ia32 Or.
1051 * @return The created ia32 Or node
1053 static ir_node *gen_Or(ir_node *node) {
1054 ir_node *op1 = get_Or_left(node);
1055 ir_node *op2 = get_Or_right(node);
1057 assert (! mode_is_float(get_irn_mode(node)));
1058 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
1064 * Creates an ia32 Eor.
1066 * @return The created ia32 Eor node
1068 static ir_node *gen_Eor(ir_node *node) {
1069 ir_node *op1 = get_Eor_left(node);
1070 ir_node *op2 = get_Eor_right(node);
1072 assert(! mode_is_float(get_irn_mode(node)));
1073 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
1078 * Creates an ia32 Sub.
1080 * @return The created ia32 Sub node
1082 static ir_node *gen_Sub(ir_node *node) {
1083 ir_node *op1 = get_Sub_left(node);
1084 ir_node *op2 = get_Sub_right(node);
1085 ir_mode *mode = get_irn_mode(node);
1087 if (mode_is_float(mode)) {
1088 if (USE_SSE2(env_cg))
1089 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1091 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1095 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1099 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1105 * Generates an ia32 DivMod with additional infrastructure for the
1106 * register allocator if needed.
1108 * @param dividend -no comment- :)
1109 * @param divisor -no comment- :)
1110 * @param dm_flav flavour_Div/Mod/DivMod
1111 * @return The created ia32 DivMod node
1113 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1114 ir_node *divisor, ia32_op_flavour_t dm_flav)
1116 ir_node *block = be_transform_node(get_nodes_block(node));
1117 ir_node *new_dividend = be_transform_node(dividend);
1118 ir_node *new_divisor = be_transform_node(divisor);
1119 ir_graph *irg = current_ir_graph;
1120 dbg_info *dbgi = get_irn_dbg_info(node);
1121 ir_mode *mode = get_irn_mode(node);
1122 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1123 ir_node *res, *proj_div, *proj_mod;
1124 ir_node *sign_extension;
1125 ir_node *mem, *new_mem;
1128 proj_div = proj_mod = NULL;
1132 mem = get_Div_mem(node);
1133 mode = get_Div_resmode(node);
1134 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1135 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1138 mem = get_Mod_mem(node);
1139 mode = get_Mod_resmode(node);
1140 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1141 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1143 case flavour_DivMod:
1144 mem = get_DivMod_mem(node);
1145 mode = get_DivMod_resmode(node);
1146 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1147 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1148 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1151 panic("invalid divmod flavour!");
1153 new_mem = be_transform_node(mem);
1155 if (mode_is_signed(mode)) {
1156 /* in signed mode, we need to sign extend the dividend */
1157 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1158 add_irn_dep(produceval, get_irg_frame(irg));
1159 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1162 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1163 set_ia32_flags(sign_extension, get_ia32_flags(sign_extension) | arch_irn_flags_modify_flags);
1164 add_irn_dep(sign_extension, get_irg_frame(irg));
1167 if (mode_is_signed(mode)) {
1168 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
1169 new_dividend, sign_extension, new_divisor, dm_flav);
1171 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem, new_dividend,
1172 sign_extension, new_divisor, dm_flav);
1175 set_ia32_exc_label(res, has_exc);
1176 set_irn_pinned(res, get_irn_pinned(node));
1178 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1185 * Wrapper for generate_DivMod. Sets flavour_Mod.
1188 static ir_node *gen_Mod(ir_node *node) {
1189 return generate_DivMod(node, get_Mod_left(node),
1190 get_Mod_right(node), flavour_Mod);
1194 * Wrapper for generate_DivMod. Sets flavour_Div.
1197 static ir_node *gen_Div(ir_node *node) {
1198 return generate_DivMod(node, get_Div_left(node),
1199 get_Div_right(node), flavour_Div);
1203 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1205 static ir_node *gen_DivMod(ir_node *node) {
1206 return generate_DivMod(node, get_DivMod_left(node),
1207 get_DivMod_right(node), flavour_DivMod);
1213 * Creates an ia32 floating Div.
1215 * @return The created ia32 xDiv node
1217 static ir_node *gen_Quot(ir_node *node) {
1218 ir_node *block = be_transform_node(get_nodes_block(node));
1219 ir_node *op1 = get_Quot_left(node);
1220 ir_node *new_op1 = be_transform_node(op1);
1221 ir_node *op2 = get_Quot_right(node);
1222 ir_node *new_op2 = be_transform_node(op2);
1223 ir_graph *irg = current_ir_graph;
1224 dbg_info *dbgi = get_irn_dbg_info(node);
1225 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1226 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1229 if (USE_SSE2(env_cg)) {
1230 ir_mode *mode = get_irn_mode(op1);
1231 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, nomem, new_op1,
1233 set_ia32_ls_mode(new_op, mode);
1235 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, nomem, new_op1,
1236 new_op2, get_fpcw());
1238 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1244 * Creates an ia32 Shl.
1246 * @return The created ia32 Shl node
1248 static ir_node *gen_Shl(ir_node *node) {
1249 ir_node *right = get_Shl_right(node);
1251 /* test whether we can build a lea */
1252 if(is_Const(right)) {
1253 tarval *tv = get_Const_tarval(right);
1254 if(tarval_is_long(tv)) {
1255 long val = get_tarval_long(tv);
1256 if(val >= 0 && val <= 3) {
1257 ir_graph *irg = current_ir_graph;
1258 dbg_info *dbgi = get_irn_dbg_info(node);
1259 ir_node *block = be_transform_node(get_nodes_block(node));
1260 ir_node *base = ia32_new_NoReg_gp(env_cg);
1261 ir_node *index = be_transform_node(get_Shl_left(node));
1262 ir_node *res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1263 set_ia32_am_scale(res, val);
1264 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1270 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1277 * Creates an ia32 Shr.
1279 * @return The created ia32 Shr node
1281 static ir_node *gen_Shr(ir_node *node) {
1282 return gen_shift_binop(node, get_Shr_left(node),
1283 get_Shr_right(node), new_rd_ia32_Shr);
1289 * Creates an ia32 Sar.
1291 * @return The created ia32 Shrs node
1293 static ir_node *gen_Shrs(ir_node *node) {
1294 ir_node *left = get_Shrs_left(node);
1295 ir_node *right = get_Shrs_right(node);
1296 ir_mode *mode = get_irn_mode(node);
1297 if(is_Const(right) && mode == mode_Is) {
1298 tarval *tv = get_Const_tarval(right);
1299 long val = get_tarval_long(tv);
1301 /* this is a sign extension */
1302 ir_graph *irg = current_ir_graph;
1303 dbg_info *dbgi = get_irn_dbg_info(node);
1304 ir_node *block = be_transform_node(get_nodes_block(node));
1306 ir_node *new_op = be_transform_node(op);
1307 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1308 add_irn_dep(pval, get_irg_frame(irg));
1310 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1314 /* 8 or 16 bit sign extension? */
1315 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1316 ir_node *shl_left = get_Shl_left(left);
1317 ir_node *shl_right = get_Shl_right(left);
1318 if(is_Const(shl_right)) {
1319 tarval *tv1 = get_Const_tarval(right);
1320 tarval *tv2 = get_Const_tarval(shl_right);
1321 if(tv1 == tv2 && tarval_is_long(tv1)) {
1322 long val = get_tarval_long(tv1);
1323 if(val == 16 || val == 24) {
1324 dbg_info *dbgi = get_irn_dbg_info(node);
1325 ir_node *block = get_nodes_block(node);
1335 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1344 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1350 * Creates an ia32 RotL.
1352 * @param op1 The first operator
1353 * @param op2 The second operator
1354 * @return The created ia32 RotL node
1356 static ir_node *gen_RotL(ir_node *node,
1357 ir_node *op1, ir_node *op2) {
1358 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1364 * Creates an ia32 RotR.
1365 * NOTE: There is no RotR with immediate because this would always be a RotL
1366 * "imm-mode_size_bits" which can be pre-calculated.
1368 * @param op1 The first operator
1369 * @param op2 The second operator
1370 * @return The created ia32 RotR node
1372 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1374 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1380 * Creates an ia32 RotR or RotL (depending on the found pattern).
1382 * @return The created ia32 RotL or RotR node
1384 static ir_node *gen_Rot(ir_node *node) {
1385 ir_node *rotate = NULL;
1386 ir_node *op1 = get_Rot_left(node);
1387 ir_node *op2 = get_Rot_right(node);
1389 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1390 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1391 that means we can create a RotR instead of an Add and a RotL */
1393 if (get_irn_op(op2) == op_Add) {
1395 ir_node *left = get_Add_left(add);
1396 ir_node *right = get_Add_right(add);
1397 if (is_Const(right)) {
1398 tarval *tv = get_Const_tarval(right);
1399 ir_mode *mode = get_irn_mode(node);
1400 long bits = get_mode_size_bits(mode);
1402 if (get_irn_op(left) == op_Minus &&
1403 tarval_is_long(tv) &&
1404 get_tarval_long(tv) == bits)
1406 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1407 rotate = gen_RotR(node, op1, get_Minus_op(left));
1412 if (rotate == NULL) {
1413 rotate = gen_RotL(node, op1, op2);
1422 * Transforms a Minus node.
1424 * @return The created ia32 Minus node
1426 static ir_node *gen_Minus(ir_node *node)
1428 ir_node *op = get_Minus_op(node);
1429 ir_node *block = be_transform_node(get_nodes_block(node));
1430 ir_graph *irg = current_ir_graph;
1431 dbg_info *dbgi = get_irn_dbg_info(node);
1432 ir_mode *mode = get_irn_mode(node);
1437 if (mode_is_float(mode)) {
1438 ir_node *new_op = be_transform_node(op);
1439 if (USE_SSE2(env_cg)) {
1440 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1441 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1442 ir_node *nomem = new_rd_NoMem(irg);
1444 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1447 size = get_mode_size_bits(mode);
1448 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1450 set_ia32_am_sc(res, ent);
1451 set_ia32_op_type(res, ia32_AddrModeS);
1452 set_ia32_ls_mode(res, mode);
1454 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1457 res = gen_unop(node, op, new_rd_ia32_Neg);
1460 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1466 * Transforms a Not node.
1468 * @return The created ia32 Not node
1470 static ir_node *gen_Not(ir_node *node) {
1471 ir_node *op = get_Not_op(node);
1472 ir_mode *mode = get_irn_mode(node);
1474 assert(mode != mode_b); /* should be lowered already */
1476 assert (! mode_is_float(get_irn_mode(node)));
1477 return gen_unop(node, op, new_rd_ia32_Not);
1483 * Transforms an Abs node.
1485 * @return The created ia32 Abs node
1487 static ir_node *gen_Abs(ir_node *node) {
1488 ir_node *block = be_transform_node(get_nodes_block(node));
1489 ir_node *op = get_Abs_op(node);
1490 ir_node *new_op = be_transform_node(op);
1491 ir_graph *irg = current_ir_graph;
1492 dbg_info *dbgi = get_irn_dbg_info(node);
1493 ir_mode *mode = get_irn_mode(node);
1494 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1495 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1496 ir_node *nomem = new_NoMem();
1501 if (mode_is_float(mode)) {
1502 if (USE_SSE2(env_cg)) {
1503 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
1505 size = get_mode_size_bits(mode);
1506 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1508 set_ia32_am_sc(res, ent);
1510 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1512 set_ia32_op_type(res, ia32_AddrModeS);
1513 set_ia32_ls_mode(res, mode);
1516 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1517 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1521 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1522 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1525 add_irn_dep(pval, get_irg_frame(irg));
1526 SET_IA32_ORIG_NODE(sign_extension,
1527 ia32_get_old_node_name(env_cg, node));
1529 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
1531 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1533 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
1535 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1542 * Transforms a Load.
1544 * @return the created ia32 Load node
1546 static ir_node *gen_Load(ir_node *node) {
1547 ir_node *old_block = get_nodes_block(node);
1548 ir_node *block = be_transform_node(old_block);
1549 ir_node *ptr = get_Load_ptr(node);
1550 ir_node *mem = get_Load_mem(node);
1551 ir_node *new_mem = be_transform_node(mem);
1554 ir_graph *irg = current_ir_graph;
1555 dbg_info *dbgi = get_irn_dbg_info(node);
1556 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1557 ir_mode *mode = get_Load_mode(node);
1560 ia32_address_t addr;
1562 /* construct load address */
1563 memset(&addr, 0, sizeof(addr));
1564 ia32_create_address_mode(&addr, ptr, 0);
1571 base = be_transform_node(base);
1577 index = be_transform_node(index);
1580 if (mode_is_float(mode)) {
1581 if (USE_SSE2(env_cg)) {
1582 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1584 res_mode = mode_xmm;
1586 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1588 res_mode = mode_vfp;
1594 /* create a conv node with address mode for smaller modes */
1595 if(get_mode_size_bits(mode) < 32) {
1596 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1597 new_mem, noreg, mode);
1599 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1604 set_irn_pinned(new_op, get_irn_pinned(node));
1605 set_ia32_op_type(new_op, ia32_AddrModeS);
1606 set_ia32_ls_mode(new_op, mode);
1607 set_address(new_op, &addr);
1609 /* make sure we are scheduled behind the initial IncSP/Barrier
1610 * to avoid spills being placed before it
1612 if (block == get_irg_start_block(irg)) {
1613 add_irn_dep(new_op, get_irg_frame(irg));
1616 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1617 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1622 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1623 ir_node *ptr, ir_mode *mode, ir_node *other)
1630 /* we only use address mode if we're the only user of the load */
1631 if(get_irn_n_edges(node) > 1)
1634 load = get_Proj_pred(node);
1637 if(get_nodes_block(load) != block)
1640 /* Store should be attached to the load */
1641 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1643 /* store should have the same pointer as the load */
1644 if(get_Load_ptr(load) != ptr)
1647 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1648 if(other != NULL && get_nodes_block(other) == block
1649 && heights_reachable_in_block(heights, other, load))
1652 assert(get_Load_mode(load) == mode);
1657 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1658 ir_node *mem, ir_node *ptr, ir_mode *mode,
1659 construct_binop_dest_func *func,
1660 construct_binop_dest_func *func8bit,
1663 ir_node *src_block = get_nodes_block(node);
1665 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1666 ir_graph *irg = current_ir_graph;
1670 ia32_address_mode_t am;
1671 ia32_address_t *addr = &am.addr;
1672 memset(&am, 0, sizeof(am));
1674 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1675 build_address(&am, op1);
1676 new_op = create_immediate_or_transform(op2, 0);
1677 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1678 build_address(&am, op2);
1679 new_op = create_immediate_or_transform(op1, 0);
1684 if(addr->base == NULL)
1685 addr->base = noreg_gp;
1686 if(addr->index == NULL)
1687 addr->index = noreg_gp;
1688 if(addr->mem == NULL)
1689 addr->mem = new_NoMem();
1691 dbgi = get_irn_dbg_info(node);
1692 block = be_transform_node(src_block);
1693 if(get_mode_size_bits(mode) == 8) {
1694 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1697 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1700 set_address(new_node, addr);
1701 set_ia32_op_type(new_node, ia32_AddrModeD);
1702 set_ia32_ls_mode(new_node, mode);
1703 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1708 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1709 ir_node *ptr, ir_mode *mode,
1710 construct_unop_dest_func *func)
1712 ir_node *src_block = get_nodes_block(node);
1714 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1715 ir_graph *irg = current_ir_graph;
1718 ia32_address_mode_t am;
1719 ia32_address_t *addr = &am.addr;
1720 memset(&am, 0, sizeof(am));
1722 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1725 build_address(&am, op);
1727 if(addr->base == NULL)
1728 addr->base = noreg_gp;
1729 if(addr->index == NULL)
1730 addr->index = noreg_gp;
1731 if(addr->mem == NULL)
1732 addr->mem = new_NoMem();
1734 dbgi = get_irn_dbg_info(node);
1735 block = be_transform_node(src_block);
1736 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1737 set_address(new_node, addr);
1738 set_ia32_op_type(new_node, ia32_AddrModeD);
1739 set_ia32_ls_mode(new_node, mode);
1740 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1745 static ir_node *try_create_dest_am(ir_node *node) {
1746 ir_node *val = get_Store_value(node);
1747 ir_node *mem = get_Store_mem(node);
1748 ir_node *ptr = get_Store_ptr(node);
1749 ir_mode *mode = get_irn_mode(val);
1754 /* handle only GP modes for now... */
1755 if(!mode_needs_gp_reg(mode))
1758 /* store must be the only user of the val node */
1759 if(get_irn_n_edges(val) > 1)
1762 switch(get_irn_opcode(val)) {
1764 op1 = get_Add_left(val);
1765 op2 = get_Add_right(val);
1766 if(is_Const_1(op2)) {
1767 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1768 new_rd_ia32_IncMem);
1770 } else if(is_Const_Minus_1(op2)) {
1771 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1772 new_rd_ia32_DecMem);
1775 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1776 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, 1);
1779 op1 = get_Sub_left(val);
1780 op2 = get_Sub_right(val);
1782 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
1785 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1786 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, 0);
1789 op1 = get_And_left(val);
1790 op2 = get_And_right(val);
1791 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1792 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, 1);
1795 op1 = get_Or_left(val);
1796 op2 = get_Or_right(val);
1797 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1798 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, 1);
1801 op1 = get_Eor_left(val);
1802 op2 = get_Eor_right(val);
1803 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1804 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, 1);
1807 op1 = get_Shl_left(val);
1808 op2 = get_Shl_right(val);
1809 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1810 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, 0);
1813 op1 = get_Shr_left(val);
1814 op2 = get_Shr_right(val);
1815 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1816 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, 0);
1819 op1 = get_Shrs_left(val);
1820 op2 = get_Shrs_right(val);
1821 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1822 new_rd_ia32_SarMem, new_rd_ia32_SarMem, 0);
1825 op1 = get_Rot_left(val);
1826 op2 = get_Rot_right(val);
1827 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1828 new_rd_ia32_RolMem, new_rd_ia32_RolMem, 0);
1830 /* TODO: match ROR patterns... */
1832 op1 = get_Minus_op(val);
1833 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1836 /* should be lowered already */
1837 assert(mode != mode_b);
1838 op1 = get_Not_op(val);
1839 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1849 * Transforms a Store.
1851 * @return the created ia32 Store node
1853 static ir_node *gen_Store(ir_node *node) {
1854 ir_node *block = be_transform_node(get_nodes_block(node));
1855 ir_node *ptr = get_Store_ptr(node);
1858 ir_node *val = get_Store_value(node);
1860 ir_node *mem = get_Store_mem(node);
1861 ir_node *new_mem = be_transform_node(mem);
1862 ir_graph *irg = current_ir_graph;
1863 dbg_info *dbgi = get_irn_dbg_info(node);
1864 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1865 ir_mode *mode = get_irn_mode(val);
1867 ia32_address_t addr;
1869 /* check for destination address mode */
1870 new_op = try_create_dest_am(node);
1874 /* construct store address */
1875 memset(&addr, 0, sizeof(addr));
1876 ia32_create_address_mode(&addr, ptr, 0);
1883 base = be_transform_node(base);
1889 index = be_transform_node(index);
1892 if (mode_is_float(mode)) {
1893 new_val = be_transform_node(val);
1894 if (USE_SSE2(env_cg)) {
1895 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
1898 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
1902 new_val = create_immediate_or_transform(val, 0);
1906 if (get_mode_size_bits(mode) == 8) {
1907 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
1910 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
1915 set_irn_pinned(new_op, get_irn_pinned(node));
1916 set_ia32_op_type(new_op, ia32_AddrModeD);
1917 set_ia32_ls_mode(new_op, mode);
1919 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1920 set_address(new_op, &addr);
1921 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1926 static ir_node *create_Switch(ir_node *node)
1928 ir_graph *irg = current_ir_graph;
1929 dbg_info *dbgi = get_irn_dbg_info(node);
1930 ir_node *block = be_transform_node(get_nodes_block(node));
1931 ir_node *sel = get_Cond_selector(node);
1932 ir_node *new_sel = be_transform_node(sel);
1934 int switch_min = INT_MAX;
1935 const ir_edge_t *edge;
1937 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1939 /* determine the smallest switch case value */
1940 foreach_out_edge(node, edge) {
1941 ir_node *proj = get_edge_src_irn(edge);
1942 int pn = get_Proj_proj(proj);
1947 if (switch_min != 0) {
1948 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1950 /* if smallest switch case is not 0 we need an additional sub */
1951 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1952 add_ia32_am_offs_int(new_sel, -switch_min);
1953 set_ia32_op_type(new_sel, ia32_AddrModeS);
1955 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1958 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1959 set_ia32_pncode(res, get_Cond_defaultProj(node));
1961 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1966 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
1968 ir_graph *irg = current_ir_graph;
1976 /* we have a Cmp as input */
1978 ir_node *pred = get_Proj_pred(node);
1980 flags = be_transform_node(pred);
1981 *pnc_out = get_Proj_proj(node);
1986 /* a mode_b value, we have to compare it against 0 */
1987 dbgi = get_irn_dbg_info(node);
1988 new_block = be_transform_node(get_nodes_block(node));
1989 new_op = be_transform_node(node);
1990 noreg = ia32_new_NoReg_gp(env_cg);
1991 nomem = new_NoMem();
1992 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
1993 new_op, new_op, 0, 0);
1994 *pnc_out = pn_Cmp_Lg;
1998 static ir_node *gen_Cond(ir_node *node) {
1999 ir_node *block = get_nodes_block(node);
2000 ir_node *new_block = be_transform_node(block);
2001 ir_graph *irg = current_ir_graph;
2002 dbg_info *dbgi = get_irn_dbg_info(node);
2003 ir_node *sel = get_Cond_selector(node);
2004 ir_mode *sel_mode = get_irn_mode(sel);
2006 ir_node *flags = NULL;
2009 if (sel_mode != mode_b) {
2010 return create_Switch(node);
2013 /* we get flags from a cmp */
2014 flags = get_flags_node(sel, &pnc);
2016 res = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2017 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2025 * Transforms a CopyB node.
2027 * @return The transformed node.
2029 static ir_node *gen_CopyB(ir_node *node) {
2030 ir_node *block = be_transform_node(get_nodes_block(node));
2031 ir_node *src = get_CopyB_src(node);
2032 ir_node *new_src = be_transform_node(src);
2033 ir_node *dst = get_CopyB_dst(node);
2034 ir_node *new_dst = be_transform_node(dst);
2035 ir_node *mem = get_CopyB_mem(node);
2036 ir_node *new_mem = be_transform_node(mem);
2037 ir_node *res = NULL;
2038 ir_graph *irg = current_ir_graph;
2039 dbg_info *dbgi = get_irn_dbg_info(node);
2040 int size = get_type_size_bytes(get_CopyB_type(node));
2043 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2044 /* then we need the size explicitly in ECX. */
2045 if (size >= 32 * 4) {
2046 rem = size & 0x3; /* size % 4 */
2049 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2051 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2053 set_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);
2055 add_irn_dep(res, get_irg_frame(irg));
2057 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2058 /* we misuse the pncode field for the copyb size */
2059 set_ia32_pncode(res, rem);
2061 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2062 set_ia32_pncode(res, size);
2065 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2070 static ir_node *gen_be_Copy(ir_node *node)
2072 ir_node *result = be_duplicate_node(node);
2073 ir_mode *mode = get_irn_mode(result);
2075 if (mode_needs_gp_reg(mode)) {
2076 set_irn_mode(result, mode_Iu);
2083 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2084 * to fold an and into a test node
2086 static int can_fold_test_and(ir_node *node)
2088 const ir_edge_t *edge;
2090 /** we can only have eq and lg projs */
2091 foreach_out_edge(node, edge) {
2092 ir_node *proj = get_edge_src_irn(edge);
2093 pn_Cmp pnc = get_Proj_proj(proj);
2094 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2101 static ir_node *try_create_Test(ir_node *node)
2103 ir_graph *irg = current_ir_graph;
2104 dbg_info *dbgi = get_irn_dbg_info(node);
2105 ir_node *block = get_nodes_block(node);
2106 ir_node *new_block = be_transform_node(block);
2107 ir_node *cmp_left = get_Cmp_left(node);
2108 ir_node *cmp_right = get_Cmp_right(node);
2113 ia32_address_mode_t am;
2114 ia32_address_t *addr = &am.addr;
2117 /* can we use a test instruction? */
2118 if(!is_Const_0(cmp_right))
2121 if(is_And(cmp_left) && get_irn_n_edges(cmp_left) == 1 &&
2122 can_fold_test_and(node)) {
2123 ir_node *and_left = get_And_left(cmp_left);
2124 ir_node *and_right = get_And_right(cmp_left);
2126 mode = get_irn_mode(and_left);
2130 mode = get_irn_mode(cmp_left);
2135 assert(get_mode_size_bits(mode) <= 32);
2137 match_arguments(&am, block, left, right, match_commutative |
2138 match_8_16_bit_am | match_am_and_immediates);
2140 cmp_unsigned = !mode_is_signed(mode);
2141 if(get_mode_size_bits(mode) == 8) {
2142 res = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2143 addr->index, addr->mem, am.new_op1,
2144 am.new_op2, am.flipped, cmp_unsigned);
2146 res = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, addr->index,
2147 addr->mem, am.new_op1, am.new_op2, am.flipped,
2150 set_am_attributes(res, &am);
2151 assert(mode != NULL);
2152 set_ia32_ls_mode(res, mode);
2154 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2156 res = fix_mem_proj(res, &am);
2160 static ir_node *create_Fucom(ir_node *node)
2162 ir_graph *irg = current_ir_graph;
2163 dbg_info *dbgi = get_irn_dbg_info(node);
2164 ir_node *block = get_nodes_block(node);
2165 ir_node *new_block = be_transform_node(block);
2166 ir_node *left = get_Cmp_left(node);
2167 ir_node *new_left = be_transform_node(left);
2168 ir_node *right = get_Cmp_right(node);
2169 ir_node *new_right = be_transform_node(right);
2172 res = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left, new_right,
2174 set_ia32_commutative(res);
2176 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2178 res = new_rd_ia32_Sahf(dbgi, irg, new_block, res);
2179 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2184 static ir_node *create_Ucomi(ir_node *node)
2186 ir_graph *irg = current_ir_graph;
2187 dbg_info *dbgi = get_irn_dbg_info(node);
2188 ir_node *block = get_nodes_block(node);
2189 ir_node *new_block = be_transform_node(block);
2190 ir_node *left = get_Cmp_left(node);
2191 ir_node *new_left = be_transform_node(left);
2192 ir_node *right = get_Cmp_right(node);
2193 ir_node *new_right = be_transform_node(right);
2194 ir_mode *mode = get_irn_mode(left);
2195 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2196 ir_node *nomem = new_NoMem();
2199 res = new_rd_ia32_Ucomi(dbgi, irg, new_block, noreg, noreg, nomem, new_left,
2201 set_ia32_commutative(res);
2202 set_ia32_ls_mode(res, mode);
2204 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2209 static ir_node *gen_Cmp(ir_node *node)
2211 ir_graph *irg = current_ir_graph;
2212 dbg_info *dbgi = get_irn_dbg_info(node);
2213 ir_node *block = get_nodes_block(node);
2214 ir_node *new_block = be_transform_node(block);
2215 ir_node *left = get_Cmp_left(node);
2216 ir_node *right = get_Cmp_right(node);
2217 ir_mode *cmp_mode = get_irn_mode(left);
2219 ia32_address_mode_t am;
2220 ia32_address_t *addr = &am.addr;
2223 if(mode_is_float(cmp_mode)) {
2224 if (USE_SSE2(env_cg)) {
2225 return create_Ucomi(node);
2227 return create_Fucom(node);
2231 assert(mode_needs_gp_reg(cmp_mode));
2233 /* we prefer the Test instruction where possible except cases where
2234 * we can use SourceAM */
2235 if(!use_source_address_mode(block, left, right) &&
2236 !use_source_address_mode(block, right, left)) {
2237 res = try_create_Test(node);
2242 match_arguments(&am, block, left, right,
2243 match_commutative | match_8_16_bit_am |
2244 match_am_and_immediates);
2246 cmp_unsigned = !mode_is_signed(get_irn_mode(left));
2247 if(get_mode_size_bits(cmp_mode) == 8) {
2248 res = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, addr->index,
2249 addr->mem, am.new_op1, am.new_op2,
2250 am.flipped, cmp_unsigned);
2252 res = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, addr->index,
2253 addr->mem, am.new_op1, am.new_op2, am.flipped,
2256 set_am_attributes(res, &am);
2257 assert(cmp_mode != NULL);
2258 set_ia32_ls_mode(res, cmp_mode);
2260 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2262 res = fix_mem_proj(res, &am);
2267 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2269 ir_graph *irg = current_ir_graph;
2270 dbg_info *dbgi = get_irn_dbg_info(node);
2271 ir_node *block = get_nodes_block(node);
2272 ir_node *new_block = be_transform_node(block);
2273 ir_node *val_true = get_Psi_val(node, 0);
2274 ir_node *new_val_true = be_transform_node(val_true);
2275 ir_node *val_false = get_Psi_default(node);
2276 ir_node *new_val_false = be_transform_node(val_false);
2277 ir_mode *mode = get_irn_mode(node);
2278 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2279 ir_node *nomem = new_NoMem();
2282 assert(mode_needs_gp_reg(mode));
2284 res = new_rd_ia32_CMov(dbgi, irg, new_block, noreg, noreg, nomem,
2285 new_val_false, new_val_true, new_flags, pnc);
2286 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2293 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2294 ir_node *flags, pn_Cmp pnc, ir_node *orig_node)
2296 ir_graph *irg = current_ir_graph;
2297 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2298 ir_node *nomem = new_NoMem();
2301 res = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc);
2302 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2303 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2304 nomem, res, mode_Bu);
2305 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2311 * Transforms a Psi node into CMov.
2313 * @return The transformed node.
2315 static ir_node *gen_Psi(ir_node *node)
2317 dbg_info *dbgi = get_irn_dbg_info(node);
2318 ir_node *block = get_nodes_block(node);
2319 ir_node *new_block = be_transform_node(block);
2320 ir_node *psi_true = get_Psi_val(node, 0);
2321 ir_node *psi_default = get_Psi_default(node);
2322 ir_node *cond = get_Psi_cond(node, 0);
2323 ir_node *flags = NULL;
2328 assert(get_Psi_n_conds(node) == 1);
2329 assert(get_irn_mode(cond) == mode_b);
2330 assert(mode_needs_gp_reg(get_irn_mode(node)));
2332 flags = get_flags_node(cond, &pnc);
2334 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2335 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2336 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2337 pnc = get_negated_pnc(pnc, cmp_mode);
2338 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2340 res = create_CMov(node, flags, pnc);
2347 * Create a conversion from x87 state register to general purpose.
2349 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2350 ir_node *block = be_transform_node(get_nodes_block(node));
2351 ir_node *op = get_Conv_op(node);
2352 ir_node *new_op = be_transform_node(op);
2353 ia32_code_gen_t *cg = env_cg;
2354 ir_graph *irg = current_ir_graph;
2355 dbg_info *dbgi = get_irn_dbg_info(node);
2356 ir_node *noreg = ia32_new_NoReg_gp(cg);
2357 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2358 ir_mode *mode = get_irn_mode(node);
2359 ir_node *fist, *load;
2362 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2363 new_NoMem(), new_op, trunc_mode);
2365 set_irn_pinned(fist, op_pin_state_floats);
2366 set_ia32_use_frame(fist);
2367 set_ia32_op_type(fist, ia32_AddrModeD);
2369 assert(get_mode_size_bits(mode) <= 32);
2370 /* exception we can only store signed 32 bit integers, so for unsigned
2371 we store a 64bit (signed) integer and load the lower bits */
2372 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2373 set_ia32_ls_mode(fist, mode_Ls);
2375 set_ia32_ls_mode(fist, mode_Is);
2377 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2380 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2382 set_irn_pinned(load, op_pin_state_floats);
2383 set_ia32_use_frame(load);
2384 set_ia32_op_type(load, ia32_AddrModeS);
2385 set_ia32_ls_mode(load, mode_Is);
2386 if(get_ia32_ls_mode(fist) == mode_Ls) {
2387 ia32_attr_t *attr = get_ia32_attr(load);
2388 attr->data.need_64bit_stackent = 1;
2390 ia32_attr_t *attr = get_ia32_attr(load);
2391 attr->data.need_32bit_stackent = 1;
2393 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2395 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2399 * Creates a x87 strict Conv by placing a Sore and a Load
2401 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2403 ir_node *block = get_nodes_block(node);
2404 ir_graph *irg = current_ir_graph;
2405 dbg_info *dbgi = get_irn_dbg_info(node);
2406 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2407 ir_node *nomem = new_NoMem();
2408 ir_node *frame = get_irg_frame(irg);
2409 ir_node *store, *load;
2412 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2414 set_ia32_use_frame(store);
2415 set_ia32_op_type(store, ia32_AddrModeD);
2416 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2418 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2420 set_ia32_use_frame(load);
2421 set_ia32_op_type(load, ia32_AddrModeS);
2422 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2424 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2428 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2430 ir_graph *irg = current_ir_graph;
2431 ir_node *start_block = get_irg_start_block(irg);
2432 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2433 symconst, symconst_sign, val);
2434 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2440 * Create a conversion from general purpose to x87 register
2442 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2443 ir_node *src_block = get_nodes_block(node);
2444 ir_node *block = be_transform_node(src_block);
2445 ir_graph *irg = current_ir_graph;
2446 dbg_info *dbgi = get_irn_dbg_info(node);
2447 ir_node *op = get_Conv_op(node);
2452 ir_mode *store_mode;
2458 /* fild can use source AM if the operand is a signed 32bit integer */
2459 if (src_mode == mode_Is) {
2460 ia32_address_mode_t am;
2462 match_arguments(&am, src_block, NULL, op, match_no_immediate);
2463 if (am.op_type == ia32_AddrModeS) {
2464 ia32_address_t *addr = &am.addr;
2466 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base, addr->index, addr->mem);
2467 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2469 set_am_attributes(fild, &am);
2470 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2472 fix_mem_proj(fild, &am);
2476 new_op = am.new_op2;
2478 new_op = be_transform_node(op);
2481 noreg = ia32_new_NoReg_gp(env_cg);
2482 nomem = new_NoMem();
2483 mode = get_irn_mode(op);
2485 /* first convert to 32 bit signed if necessary */
2486 src_bits = get_mode_size_bits(src_mode);
2487 if (src_bits == 8) {
2488 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2490 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2492 } else if (src_bits < 32) {
2493 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2495 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2499 assert(get_mode_size_bits(mode) == 32);
2502 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2505 set_ia32_use_frame(store);
2506 set_ia32_op_type(store, ia32_AddrModeD);
2507 set_ia32_ls_mode(store, mode_Iu);
2509 /* exception for 32bit unsigned, do a 64bit spill+load */
2510 if(!mode_is_signed(mode)) {
2513 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2515 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2516 get_irg_frame(irg), noreg, nomem,
2519 set_ia32_use_frame(zero_store);
2520 set_ia32_op_type(zero_store, ia32_AddrModeD);
2521 add_ia32_am_offs_int(zero_store, 4);
2522 set_ia32_ls_mode(zero_store, mode_Iu);
2527 store = new_rd_Sync(dbgi, irg, block, 2, in);
2528 store_mode = mode_Ls;
2530 store_mode = mode_Is;
2534 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2536 set_ia32_use_frame(fild);
2537 set_ia32_op_type(fild, ia32_AddrModeS);
2538 set_ia32_ls_mode(fild, store_mode);
2540 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2546 * Crete a conversion from one integer mode into another one
2548 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2549 dbg_info *dbgi, ir_node *block, ir_node *op,
2552 ir_graph *irg = current_ir_graph;
2553 int src_bits = get_mode_size_bits(src_mode);
2554 int tgt_bits = get_mode_size_bits(tgt_mode);
2555 ir_node *new_block = be_transform_node(block);
2556 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2559 ir_mode *smaller_mode;
2561 ia32_address_mode_t am;
2562 ia32_address_t *addr = &am.addr;
2564 if (src_bits < tgt_bits) {
2565 smaller_mode = src_mode;
2566 smaller_bits = src_bits;
2568 smaller_mode = tgt_mode;
2569 smaller_bits = tgt_bits;
2572 memset(&am, 0, sizeof(am));
2573 if(use_source_address_mode(block, op, NULL)) {
2574 build_address(&am, op);
2576 am.op_type = ia32_AddrModeS;
2578 new_op = be_transform_node(op);
2579 am.op_type = ia32_Normal;
2581 if(addr->base == NULL)
2583 if(addr->index == NULL)
2584 addr->index = noreg;
2585 if(addr->mem == NULL)
2586 addr->mem = new_NoMem();
2588 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2589 if (smaller_bits == 8) {
2590 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2591 addr->index, addr->mem, new_op,
2594 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2595 addr->index, addr->mem, new_op,
2599 set_am_attributes(res, &am);
2600 set_ia32_ls_mode(res, smaller_mode);
2601 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2602 res = fix_mem_proj(res, &am);
2608 * Transforms a Conv node.
2610 * @return The created ia32 Conv node
2612 static ir_node *gen_Conv(ir_node *node) {
2613 ir_node *block = get_nodes_block(node);
2614 ir_node *new_block = be_transform_node(block);
2615 ir_node *op = get_Conv_op(node);
2616 ir_node *new_op = NULL;
2617 ir_graph *irg = current_ir_graph;
2618 dbg_info *dbgi = get_irn_dbg_info(node);
2619 ir_mode *src_mode = get_irn_mode(op);
2620 ir_mode *tgt_mode = get_irn_mode(node);
2621 int src_bits = get_mode_size_bits(src_mode);
2622 int tgt_bits = get_mode_size_bits(tgt_mode);
2623 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2624 ir_node *nomem = new_rd_NoMem(irg);
2625 ir_node *res = NULL;
2627 if (src_mode == mode_b) {
2628 assert(mode_is_int(tgt_mode));
2629 /* nothing to do, we already model bools as 0/1 ints */
2630 return be_transform_node(op);
2633 if (src_mode == tgt_mode) {
2634 if (get_Conv_strict(node)) {
2635 if (USE_SSE2(env_cg)) {
2636 /* when we are in SSE mode, we can kill all strict no-op conversion */
2637 return be_transform_node(op);
2640 /* this should be optimized already, but who knows... */
2641 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2642 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2643 return be_transform_node(op);
2647 if (mode_is_float(src_mode)) {
2648 new_op = be_transform_node(op);
2649 /* we convert from float ... */
2650 if (mode_is_float(tgt_mode)) {
2651 if(src_mode == mode_E && tgt_mode == mode_D
2652 && !get_Conv_strict(node)) {
2653 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2658 if (USE_SSE2(env_cg)) {
2659 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2660 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2662 set_ia32_ls_mode(res, tgt_mode);
2664 if(get_Conv_strict(node)) {
2665 res = gen_x87_strict_conv(tgt_mode, new_op);
2666 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2669 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2674 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2675 if (USE_SSE2(env_cg)) {
2676 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2678 set_ia32_ls_mode(res, src_mode);
2680 return gen_x87_fp_to_gp(node);
2684 /* we convert from int ... */
2685 if (mode_is_float(tgt_mode)) {
2687 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2688 if (USE_SSE2(env_cg)) {
2689 new_op = be_transform_node(op);
2690 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2692 set_ia32_ls_mode(res, tgt_mode);
2694 res = gen_x87_gp_to_fp(node, src_mode);
2695 if(get_Conv_strict(node)) {
2696 res = gen_x87_strict_conv(tgt_mode, res);
2697 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2698 ia32_get_old_node_name(env_cg, node));
2702 } else if(tgt_mode == mode_b) {
2703 /* mode_b lowering already took care that we only have 0/1 values */
2704 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2705 src_mode, tgt_mode));
2706 return be_transform_node(op);
2709 if (src_bits == tgt_bits) {
2710 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2711 src_mode, tgt_mode));
2712 return be_transform_node(op);
2715 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2723 static int check_immediate_constraint(long val, char immediate_constraint_type)
2725 switch (immediate_constraint_type) {
2729 return val >= 0 && val <= 32;
2731 return val >= 0 && val <= 63;
2733 return val >= -128 && val <= 127;
2735 return val == 0xff || val == 0xffff;
2737 return val >= 0 && val <= 3;
2739 return val >= 0 && val <= 255;
2741 return val >= 0 && val <= 127;
2745 panic("Invalid immediate constraint found");
2749 static ir_node *try_create_Immediate(ir_node *node,
2750 char immediate_constraint_type)
2753 tarval *offset = NULL;
2754 int offset_sign = 0;
2756 ir_entity *symconst_ent = NULL;
2757 int symconst_sign = 0;
2759 ir_node *cnst = NULL;
2760 ir_node *symconst = NULL;
2763 mode = get_irn_mode(node);
2764 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2768 if(is_Minus(node)) {
2770 node = get_Minus_op(node);
2773 if(is_Const(node)) {
2776 offset_sign = minus;
2777 } else if(is_SymConst(node)) {
2780 symconst_sign = minus;
2781 } else if(is_Add(node)) {
2782 ir_node *left = get_Add_left(node);
2783 ir_node *right = get_Add_right(node);
2784 if(is_Const(left) && is_SymConst(right)) {
2787 symconst_sign = minus;
2788 offset_sign = minus;
2789 } else if(is_SymConst(left) && is_Const(right)) {
2792 symconst_sign = minus;
2793 offset_sign = minus;
2795 } else if(is_Sub(node)) {
2796 ir_node *left = get_Sub_left(node);
2797 ir_node *right = get_Sub_right(node);
2798 if(is_Const(left) && is_SymConst(right)) {
2801 symconst_sign = !minus;
2802 offset_sign = minus;
2803 } else if(is_SymConst(left) && is_Const(right)) {
2806 symconst_sign = minus;
2807 offset_sign = !minus;
2814 offset = get_Const_tarval(cnst);
2815 if(tarval_is_long(offset)) {
2816 val = get_tarval_long(offset);
2818 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2823 if(!check_immediate_constraint(val, immediate_constraint_type))
2826 if(symconst != NULL) {
2827 if(immediate_constraint_type != 0) {
2828 /* we need full 32bits for symconsts */
2832 /* unfortunately the assembler/linker doesn't support -symconst */
2836 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2838 symconst_ent = get_SymConst_entity(symconst);
2840 if(cnst == NULL && symconst == NULL)
2843 if(offset_sign && offset != NULL) {
2844 offset = tarval_neg(offset);
2847 res = create_Immediate(symconst_ent, symconst_sign, val);
2852 static ir_node *create_immediate_or_transform(ir_node *node,
2853 char immediate_constraint_type)
2855 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2856 if (new_node == NULL) {
2857 new_node = be_transform_node(node);
2862 typedef struct constraint_t constraint_t;
2863 struct constraint_t {
2866 const arch_register_req_t **out_reqs;
2868 const arch_register_req_t *req;
2869 unsigned immediate_possible;
2870 char immediate_type;
2873 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2875 int immediate_possible = 0;
2876 char immediate_type = 0;
2877 unsigned limited = 0;
2878 const arch_register_class_t *cls = NULL;
2879 ir_graph *irg = current_ir_graph;
2880 struct obstack *obst = get_irg_obstack(irg);
2881 arch_register_req_t *req;
2882 unsigned *limited_ptr;
2886 /* TODO: replace all the asserts with nice error messages */
2888 printf("Constraint: %s\n", c);
2898 assert(cls == NULL ||
2899 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2900 cls = &ia32_reg_classes[CLASS_ia32_gp];
2901 limited |= 1 << REG_EAX;
2904 assert(cls == NULL ||
2905 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2906 cls = &ia32_reg_classes[CLASS_ia32_gp];
2907 limited |= 1 << REG_EBX;
2910 assert(cls == NULL ||
2911 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2912 cls = &ia32_reg_classes[CLASS_ia32_gp];
2913 limited |= 1 << REG_ECX;
2916 assert(cls == NULL ||
2917 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2918 cls = &ia32_reg_classes[CLASS_ia32_gp];
2919 limited |= 1 << REG_EDX;
2922 assert(cls == NULL ||
2923 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2924 cls = &ia32_reg_classes[CLASS_ia32_gp];
2925 limited |= 1 << REG_EDI;
2928 assert(cls == NULL ||
2929 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2930 cls = &ia32_reg_classes[CLASS_ia32_gp];
2931 limited |= 1 << REG_ESI;
2934 case 'q': /* q means lower part of the regs only, this makes no
2935 * difference to Q for us (we only assigne whole registers) */
2936 assert(cls == NULL ||
2937 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2938 cls = &ia32_reg_classes[CLASS_ia32_gp];
2939 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2943 assert(cls == NULL ||
2944 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2945 cls = &ia32_reg_classes[CLASS_ia32_gp];
2946 limited |= 1 << REG_EAX | 1 << REG_EDX;
2949 assert(cls == NULL ||
2950 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2951 cls = &ia32_reg_classes[CLASS_ia32_gp];
2952 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2953 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2960 assert(cls == NULL);
2961 cls = &ia32_reg_classes[CLASS_ia32_gp];
2967 /* TODO: mark values so the x87 simulator knows about t and u */
2968 assert(cls == NULL);
2969 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2974 assert(cls == NULL);
2975 /* TODO: check that sse2 is supported */
2976 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2986 assert(!immediate_possible);
2987 immediate_possible = 1;
2988 immediate_type = *c;
2992 assert(!immediate_possible);
2993 immediate_possible = 1;
2997 assert(!immediate_possible && cls == NULL);
2998 immediate_possible = 1;
2999 cls = &ia32_reg_classes[CLASS_ia32_gp];
3012 assert(constraint->is_in && "can only specify same constraint "
3015 sscanf(c, "%d%n", &same_as, &p);
3022 case 'E': /* no float consts yet */
3023 case 'F': /* no float consts yet */
3024 case 's': /* makes no sense on x86 */
3025 case 'X': /* we can't support that in firm */
3029 case '<': /* no autodecrement on x86 */
3030 case '>': /* no autoincrement on x86 */
3031 case 'C': /* sse constant not supported yet */
3032 case 'G': /* 80387 constant not supported yet */
3033 case 'y': /* we don't support mmx registers yet */
3034 case 'Z': /* not available in 32 bit mode */
3035 case 'e': /* not available in 32 bit mode */
3036 panic("unsupported asm constraint '%c' found in (%+F)",
3037 *c, current_ir_graph);
3040 panic("unknown asm constraint '%c' found in (%+F)", *c,
3048 const arch_register_req_t *other_constr;
3050 assert(cls == NULL && "same as and register constraint not supported");
3051 assert(!immediate_possible && "same as and immediate constraint not "
3053 assert(same_as < constraint->n_outs && "wrong constraint number in "
3054 "same_as constraint");
3056 other_constr = constraint->out_reqs[same_as];
3058 req = obstack_alloc(obst, sizeof(req[0]));
3059 req->cls = other_constr->cls;
3060 req->type = arch_register_req_type_should_be_same;
3061 req->limited = NULL;
3062 req->other_same[0] = pos;
3063 req->other_same[1] = -1;
3064 req->other_different = -1;
3066 /* switch constraints. This is because in firm we have same_as
3067 * constraints on the output constraints while in the gcc asm syntax
3068 * they are specified on the input constraints */
3069 constraint->req = other_constr;
3070 constraint->out_reqs[same_as] = req;
3071 constraint->immediate_possible = 0;
3075 if(immediate_possible && cls == NULL) {
3076 cls = &ia32_reg_classes[CLASS_ia32_gp];
3078 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3079 assert(cls != NULL);
3081 if(immediate_possible) {
3082 assert(constraint->is_in
3083 && "imeediates make no sense for output constraints");
3085 /* todo: check types (no float input on 'r' constrained in and such... */
3088 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3089 limited_ptr = (unsigned*) (req+1);
3091 req = obstack_alloc(obst, sizeof(req[0]));
3093 memset(req, 0, sizeof(req[0]));
3096 req->type = arch_register_req_type_limited;
3097 *limited_ptr = limited;
3098 req->limited = limited_ptr;
3100 req->type = arch_register_req_type_normal;
3104 constraint->req = req;
3105 constraint->immediate_possible = immediate_possible;
3106 constraint->immediate_type = immediate_type;
3109 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3116 panic("Clobbers not supported yet");
3120 * generates code for a ASM node
3122 static ir_node *gen_ASM(ir_node *node)
3125 ir_graph *irg = current_ir_graph;
3126 ir_node *block = be_transform_node(get_nodes_block(node));
3127 dbg_info *dbgi = get_irn_dbg_info(node);
3134 ia32_asm_attr_t *attr;
3135 const arch_register_req_t **out_reqs;
3136 const arch_register_req_t **in_reqs;
3137 struct obstack *obst;
3138 constraint_t parsed_constraint;
3140 /* transform inputs */
3141 arity = get_irn_arity(node);
3142 in = alloca(arity * sizeof(in[0]));
3143 memset(in, 0, arity * sizeof(in[0]));
3145 n_outs = get_ASM_n_output_constraints(node);
3146 n_clobbers = get_ASM_n_clobbers(node);
3147 out_arity = n_outs + n_clobbers;
3149 /* construct register constraints */
3150 obst = get_irg_obstack(irg);
3151 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
3152 parsed_constraint.out_reqs = out_reqs;
3153 parsed_constraint.n_outs = n_outs;
3154 parsed_constraint.is_in = 0;
3155 for(i = 0; i < out_arity; ++i) {
3159 const ir_asm_constraint *constraint;
3160 constraint = & get_ASM_output_constraints(node) [i];
3161 c = get_id_str(constraint->constraint);
3162 parse_asm_constraint(i, &parsed_constraint, c);
3164 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
3165 c = get_id_str(glob_id);
3166 parse_clobber(node, i, &parsed_constraint, c);
3168 out_reqs[i] = parsed_constraint.req;
3171 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
3172 parsed_constraint.is_in = 1;
3173 for(i = 0; i < arity; ++i) {
3174 const ir_asm_constraint *constraint;
3178 constraint = & get_ASM_input_constraints(node) [i];
3179 constr_id = constraint->constraint;
3180 c = get_id_str(constr_id);
3181 parse_asm_constraint(i, &parsed_constraint, c);
3182 in_reqs[i] = parsed_constraint.req;
3184 if(parsed_constraint.immediate_possible) {
3185 ir_node *pred = get_irn_n(node, i);
3186 char imm_type = parsed_constraint.immediate_type;
3187 ir_node *immediate = try_create_Immediate(pred, imm_type);
3189 if(immediate != NULL) {
3195 /* transform inputs */
3196 for(i = 0; i < arity; ++i) {
3198 ir_node *transformed;
3203 pred = get_irn_n(node, i);
3204 transformed = be_transform_node(pred);
3205 in[i] = transformed;
3208 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
3210 generic_attr = get_irn_generic_attr(res);
3211 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
3212 attr->asm_text = get_ASM_text(node);
3213 set_ia32_out_req_all(res, out_reqs);
3214 set_ia32_in_req_all(res, in_reqs);
3216 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3221 /********************************************
3224 * | |__ ___ _ __ ___ __| | ___ ___
3225 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3226 * | |_) | __/ | | | (_) | (_| | __/\__ \
3227 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3229 ********************************************/
3232 * Transforms a FrameAddr into an ia32 Add.
3234 static ir_node *gen_be_FrameAddr(ir_node *node) {
3235 ir_node *block = be_transform_node(get_nodes_block(node));
3236 ir_node *op = be_get_FrameAddr_frame(node);
3237 ir_node *new_op = be_transform_node(op);
3238 ir_graph *irg = current_ir_graph;
3239 dbg_info *dbgi = get_irn_dbg_info(node);
3240 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3243 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3244 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3245 set_ia32_use_frame(res);
3247 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3253 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3255 static ir_node *gen_be_Return(ir_node *node) {
3256 ir_graph *irg = current_ir_graph;
3257 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3258 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3259 ir_entity *ent = get_irg_entity(irg);
3260 ir_type *tp = get_entity_type(ent);
3265 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3266 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3269 int pn_ret_val, pn_ret_mem, arity, i;
3271 assert(ret_val != NULL);
3272 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3273 return be_duplicate_node(node);
3276 res_type = get_method_res_type(tp, 0);
3278 if (! is_Primitive_type(res_type)) {
3279 return be_duplicate_node(node);
3282 mode = get_type_mode(res_type);
3283 if (! mode_is_float(mode)) {
3284 return be_duplicate_node(node);
3287 assert(get_method_n_ress(tp) == 1);
3289 pn_ret_val = get_Proj_proj(ret_val);
3290 pn_ret_mem = get_Proj_proj(ret_mem);
3292 /* get the Barrier */
3293 barrier = get_Proj_pred(ret_val);
3295 /* get result input of the Barrier */
3296 ret_val = get_irn_n(barrier, pn_ret_val);
3297 new_ret_val = be_transform_node(ret_val);
3299 /* get memory input of the Barrier */
3300 ret_mem = get_irn_n(barrier, pn_ret_mem);
3301 new_ret_mem = be_transform_node(ret_mem);
3303 frame = get_irg_frame(irg);
3305 dbgi = get_irn_dbg_info(barrier);
3306 block = be_transform_node(get_nodes_block(barrier));
3308 noreg = ia32_new_NoReg_gp(env_cg);
3310 /* store xmm0 onto stack */
3311 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3312 new_ret_mem, new_ret_val);
3313 set_ia32_ls_mode(sse_store, mode);
3314 set_ia32_op_type(sse_store, ia32_AddrModeD);
3315 set_ia32_use_frame(sse_store);
3317 /* load into x87 register */
3318 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3319 set_ia32_op_type(fld, ia32_AddrModeS);
3320 set_ia32_use_frame(fld);
3322 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3323 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3325 /* create a new barrier */
3326 arity = get_irn_arity(barrier);
3327 in = alloca(arity * sizeof(in[0]));
3328 for (i = 0; i < arity; ++i) {
3331 if (i == pn_ret_val) {
3333 } else if (i == pn_ret_mem) {
3336 ir_node *in = get_irn_n(barrier, i);
3337 new_in = be_transform_node(in);
3342 new_barrier = new_ir_node(dbgi, irg, block,
3343 get_irn_op(barrier), get_irn_mode(barrier),
3345 copy_node_attr(barrier, new_barrier);
3346 be_duplicate_deps(barrier, new_barrier);
3347 be_set_transformed_node(barrier, new_barrier);
3348 mark_irn_visited(barrier);
3350 /* transform normally */
3351 return be_duplicate_node(node);
3355 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3357 static ir_node *gen_be_AddSP(ir_node *node) {
3358 ir_node *block = be_transform_node(get_nodes_block(node));
3359 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3361 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3362 ir_node *new_sp = be_transform_node(sp);
3363 ir_graph *irg = current_ir_graph;
3364 dbg_info *dbgi = get_irn_dbg_info(node);
3365 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3366 ir_node *nomem = new_NoMem();
3369 new_sz = create_immediate_or_transform(sz, 0);
3371 /* ia32 stack grows in reverse direction, make a SubSP */
3372 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
3374 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3380 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3382 static ir_node *gen_be_SubSP(ir_node *node) {
3383 ir_node *block = be_transform_node(get_nodes_block(node));
3384 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3386 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3387 ir_node *new_sp = be_transform_node(sp);
3388 ir_graph *irg = current_ir_graph;
3389 dbg_info *dbgi = get_irn_dbg_info(node);
3390 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3391 ir_node *nomem = new_NoMem();
3394 new_sz = create_immediate_or_transform(sz, 0);
3396 /* ia32 stack grows in reverse direction, make an AddSP */
3397 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
3399 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3405 * This function just sets the register for the Unknown node
3406 * as this is not done during register allocation because Unknown
3407 * is an "ignore" node.
3409 static ir_node *gen_Unknown(ir_node *node) {
3410 ir_mode *mode = get_irn_mode(node);
3412 if (mode_is_float(mode)) {
3413 if (USE_SSE2(env_cg)) {
3414 return ia32_new_Unknown_xmm(env_cg);
3416 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3417 ir_graph *irg = current_ir_graph;
3418 dbg_info *dbgi = get_irn_dbg_info(node);
3419 ir_node *block = get_irg_start_block(irg);
3420 return new_rd_ia32_vfldz(dbgi, irg, block);
3422 } else if (mode_needs_gp_reg(mode)) {
3423 return ia32_new_Unknown_gp(env_cg);
3425 assert(0 && "unsupported Unknown-Mode");
3432 * Change some phi modes
3434 static ir_node *gen_Phi(ir_node *node) {
3435 ir_node *block = be_transform_node(get_nodes_block(node));
3436 ir_graph *irg = current_ir_graph;
3437 dbg_info *dbgi = get_irn_dbg_info(node);
3438 ir_mode *mode = get_irn_mode(node);
3441 if(mode_needs_gp_reg(mode)) {
3442 /* we shouldn't have any 64bit stuff around anymore */
3443 assert(get_mode_size_bits(mode) <= 32);
3444 /* all integer operations are on 32bit registers now */
3446 } else if(mode_is_float(mode)) {
3447 if (USE_SSE2(env_cg)) {
3454 /* phi nodes allow loops, so we use the old arguments for now
3455 * and fix this later */
3456 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3457 get_irn_in(node) + 1);
3458 copy_node_attr(node, phi);
3459 be_duplicate_deps(node, phi);
3461 be_set_transformed_node(node, phi);
3462 be_enqueue_preds(node);
3470 static ir_node *gen_IJmp(ir_node *node) {
3471 /* TODO: support AM */
3472 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3476 /**********************************************************************
3479 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3480 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3481 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3482 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3484 **********************************************************************/
3486 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3488 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3491 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3492 ir_node *val, ir_node *mem);
3495 * Transforms a lowered Load into a "real" one.
3497 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3499 ir_node *block = be_transform_node(get_nodes_block(node));
3500 ir_node *ptr = get_irn_n(node, 0);
3501 ir_node *new_ptr = be_transform_node(ptr);
3502 ir_node *mem = get_irn_n(node, 1);
3503 ir_node *new_mem = be_transform_node(mem);
3504 ir_graph *irg = current_ir_graph;
3505 dbg_info *dbgi = get_irn_dbg_info(node);
3506 ir_mode *mode = get_ia32_ls_mode(node);
3507 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3510 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3512 set_ia32_op_type(new_op, ia32_AddrModeS);
3513 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3514 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3515 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3516 if (is_ia32_am_sc_sign(node))
3517 set_ia32_am_sc_sign(new_op);
3518 set_ia32_ls_mode(new_op, mode);
3519 if (is_ia32_use_frame(node)) {
3520 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3521 set_ia32_use_frame(new_op);
3524 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3530 * Transforms a lowered Store into a "real" one.
3532 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3534 ir_node *block = be_transform_node(get_nodes_block(node));
3535 ir_node *ptr = get_irn_n(node, 0);
3536 ir_node *new_ptr = be_transform_node(ptr);
3537 ir_node *val = get_irn_n(node, 1);
3538 ir_node *new_val = be_transform_node(val);
3539 ir_node *mem = get_irn_n(node, 2);
3540 ir_node *new_mem = be_transform_node(mem);
3541 ir_graph *irg = current_ir_graph;
3542 dbg_info *dbgi = get_irn_dbg_info(node);
3543 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3544 ir_mode *mode = get_ia32_ls_mode(node);
3548 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3550 am_offs = get_ia32_am_offs_int(node);
3551 add_ia32_am_offs_int(new_op, am_offs);
3553 set_ia32_op_type(new_op, ia32_AddrModeD);
3554 set_ia32_ls_mode(new_op, mode);
3555 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3556 set_ia32_use_frame(new_op);
3558 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3565 * Transforms an ia32_l_XXX into a "real" XXX node
3567 * @param node The node to transform
3568 * @return the created ia32 XXX node
3570 #define GEN_LOWERED_OP(op) \
3571 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3572 return gen_binop(node, get_binop_left(node), \
3573 get_binop_right(node), new_rd_ia32_##op,0); \
3576 #define GEN_LOWERED_x87_OP(op) \
3577 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3579 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3580 get_binop_right(node), new_rd_ia32_##op); \
3584 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3585 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3586 return gen_shift_binop(node, get_irn_n(node, 0), \
3587 get_irn_n(node, 1), new_rd_ia32_##op); \
3590 GEN_LOWERED_x87_OP(vfprem)
3591 GEN_LOWERED_x87_OP(vfmul)
3592 GEN_LOWERED_x87_OP(vfsub)
3593 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3594 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3595 GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
3596 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3598 static ir_node *gen_ia32_l_Add(ir_node *node) {
3599 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3600 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3601 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, 1);
3603 if(is_Proj(lowered)) {
3604 lowered = get_Proj_pred(lowered);
3606 assert(is_ia32_Add(lowered));
3607 set_irn_mode(lowered, mode_T);
3613 static ir_node *gen_ia32_l_Adc(ir_node *node) {
3614 ir_node *src_block = get_nodes_block(node);
3615 ir_node *block = be_transform_node(src_block);
3616 ir_node *op1 = get_irn_n(node, n_ia32_l_Adc_left);
3617 ir_node *op2 = get_irn_n(node, n_ia32_l_Adc_right);
3618 ir_node *flags = get_irn_n(node, n_ia32_l_Adc_eflags);
3619 ir_node *new_flags = be_transform_node(flags);
3620 ir_graph *irg = current_ir_graph;
3621 dbg_info *dbgi = get_irn_dbg_info(node);
3623 ia32_address_mode_t am;
3624 ia32_address_t *addr = &am.addr;
3626 match_arguments(&am, src_block, op1, op2, match_commutative);
3628 new_node = new_rd_ia32_Adc(dbgi, irg, block, addr->base, addr->index,
3629 addr->mem, am.new_op1, am.new_op2, new_flags);
3630 set_am_attributes(new_node, &am);
3631 /* we can't use source address mode anymore when using immediates */
3632 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3633 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3634 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3636 new_node = fix_mem_proj(new_node, &am);
3642 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3644 * @param node The node to transform
3645 * @return the created ia32 Neg node
3647 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3648 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3652 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3654 * @param node The node to transform
3655 * @return the created ia32 vfild node
3657 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3658 return gen_lowered_Load(node, new_rd_ia32_vfild);
3662 * Transforms an ia32_l_Load into a "real" ia32_Load node
3664 * @param node The node to transform
3665 * @return the created ia32 Load node
3667 static ir_node *gen_ia32_l_Load(ir_node *node) {
3668 return gen_lowered_Load(node, new_rd_ia32_Load);
3672 * Transforms an ia32_l_Store into a "real" ia32_Store node
3674 * @param node The node to transform
3675 * @return the created ia32 Store node
3677 static ir_node *gen_ia32_l_Store(ir_node *node) {
3678 return gen_lowered_Store(node, new_rd_ia32_Store);
3682 * Transforms a l_vfist into a "real" vfist node.
3684 * @param node The node to transform
3685 * @return the created ia32 vfist node
3687 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3688 ir_node *block = be_transform_node(get_nodes_block(node));
3689 ir_node *ptr = get_irn_n(node, 0);
3690 ir_node *new_ptr = be_transform_node(ptr);
3691 ir_node *val = get_irn_n(node, 1);
3692 ir_node *new_val = be_transform_node(val);
3693 ir_node *mem = get_irn_n(node, 2);
3694 ir_node *new_mem = be_transform_node(mem);
3695 ir_graph *irg = current_ir_graph;
3696 dbg_info *dbgi = get_irn_dbg_info(node);
3697 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3698 ir_mode *mode = get_ia32_ls_mode(node);
3699 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3703 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3704 new_val, trunc_mode);
3706 am_offs = get_ia32_am_offs_int(node);
3707 add_ia32_am_offs_int(new_op, am_offs);
3709 set_ia32_op_type(new_op, ia32_AddrModeD);
3710 set_ia32_ls_mode(new_op, mode);
3711 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3712 set_ia32_use_frame(new_op);
3714 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3720 * Transforms a l_vfdiv into a "real" vfdiv node.
3722 * @param env The transformation environment
3723 * @return the created ia32 vfdiv node
3725 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3726 ir_node *block = be_transform_node(get_nodes_block(node));
3727 ir_node *left = get_binop_left(node);
3728 ir_node *new_left = be_transform_node(left);
3729 ir_node *right = get_binop_right(node);
3730 ir_node *new_right = be_transform_node(right);
3731 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3732 ir_graph *irg = current_ir_graph;
3733 dbg_info *dbgi = get_irn_dbg_info(node);
3734 ir_node *fpcw = get_fpcw();
3737 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_NoMem(),
3738 new_left, new_right, fpcw);
3739 clear_ia32_commutative(vfdiv);
3741 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3747 * Transforms a l_MulS into a "real" MulS node.
3749 * @param env The transformation environment
3750 * @return the created ia32 Mul node
3752 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3753 ir_node *block = be_transform_node(get_nodes_block(node));
3754 ir_node *left = get_binop_left(node);
3755 ir_node *new_left = be_transform_node(left);
3756 ir_node *right = get_binop_right(node);
3757 ir_node *new_right = be_transform_node(right);
3758 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3759 ir_graph *irg = current_ir_graph;
3760 dbg_info *dbgi = get_irn_dbg_info(node);
3762 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3763 /* and then skip the result Proj, because all needed Projs are already there. */
3764 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(),
3765 new_left, new_right);
3766 clear_ia32_commutative(muls);
3768 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3774 * Transforms a l_IMulS into a "real" IMul1OPS node.
3776 * @param env The transformation environment
3777 * @return the created ia32 IMul1OP node
3779 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3780 ir_node *block = be_transform_node(get_nodes_block(node));
3781 ir_node *left = get_binop_left(node);
3782 ir_node *new_left = be_transform_node(left);
3783 ir_node *right = get_binop_right(node);
3784 ir_node *new_right = be_transform_node(right);
3785 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3786 ir_graph *irg = current_ir_graph;
3787 dbg_info *dbgi = get_irn_dbg_info(node);
3789 /* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */
3790 /* and then skip the result Proj, because all needed Projs are already there. */
3791 ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg,
3792 new_NoMem(), new_left, new_right);
3793 clear_ia32_commutative(muls);
3795 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3800 static ir_node *gen_ia32_l_Sub(ir_node *node) {
3801 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
3802 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
3803 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, 0);
3805 if(is_Proj(lowered)) {
3806 lowered = get_Proj_pred(lowered);
3808 assert(is_ia32_Sub(lowered));
3809 set_irn_mode(lowered, mode_T);
3815 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
3816 ir_node *src_block = get_nodes_block(node);
3817 ir_node *block = be_transform_node(src_block);
3818 ir_node *op1 = get_irn_n(node, n_ia32_l_Sbb_left);
3819 ir_node *op2 = get_irn_n(node, n_ia32_l_Sbb_right);
3820 ir_node *flags = get_irn_n(node, n_ia32_l_Sbb_eflags);
3821 ir_node *new_flags = be_transform_node(flags);
3822 ir_graph *irg = current_ir_graph;
3823 dbg_info *dbgi = get_irn_dbg_info(node);
3825 ia32_address_mode_t am;
3826 ia32_address_t *addr = &am.addr;
3828 match_arguments(&am, src_block, op1, op2, match_commutative);
3830 new_node = new_rd_ia32_Sbb(dbgi, irg, block, addr->base, addr->index,
3831 addr->mem, am.new_op1, am.new_op2, new_flags);
3832 set_am_attributes(new_node, &am);
3833 /* we can't use source address mode anymore when using immediates */
3834 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3835 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3836 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3838 new_node = fix_mem_proj(new_node, &am);
3844 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3845 * op1 - target to be shifted
3846 * op2 - contains bits to be shifted into target
3848 * Only op3 can be an immediate.
3850 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3851 ir_node *op2, ir_node *count)
3853 ir_node *block = be_transform_node(get_nodes_block(node));
3854 ir_node *new_op = NULL;
3855 ir_graph *irg = current_ir_graph;
3856 dbg_info *dbgi = get_irn_dbg_info(node);
3857 ir_node *new_op1 = be_transform_node(op1);
3858 ir_node *new_op2 = be_transform_node(op2);
3859 ir_node *new_count = create_immediate_or_transform(count, 'I');
3861 /* TODO proper AM support */
3863 if (is_ia32_l_ShlD(node))
3864 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3866 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3868 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3873 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3874 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3875 get_irn_n(node, 1), get_irn_n(node, 2));
3878 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3879 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3880 get_irn_n(node, 1), get_irn_n(node, 2));
3884 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3886 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3887 ir_node *block = be_transform_node(get_nodes_block(node));
3888 ir_node *val = get_irn_n(node, 1);
3889 ir_node *new_val = be_transform_node(val);
3890 ia32_code_gen_t *cg = env_cg;
3891 ir_node *res = NULL;
3892 ir_graph *irg = current_ir_graph;
3894 ir_node *noreg, *new_ptr, *new_mem;
3901 mem = get_irn_n(node, 2);
3902 new_mem = be_transform_node(mem);
3903 ptr = get_irn_n(node, 0);
3904 new_ptr = be_transform_node(ptr);
3905 noreg = ia32_new_NoReg_gp(cg);
3906 dbgi = get_irn_dbg_info(node);
3908 /* Store x87 -> MEM */
3909 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
3910 get_ia32_ls_mode(node));
3911 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3912 set_ia32_use_frame(res);
3913 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3914 set_ia32_op_type(res, ia32_AddrModeD);
3916 /* Load MEM -> SSE */
3917 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
3918 get_ia32_ls_mode(node));
3919 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3920 set_ia32_use_frame(res);
3921 set_ia32_op_type(res, ia32_AddrModeS);
3922 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3928 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3930 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3931 ir_node *block = be_transform_node(get_nodes_block(node));
3932 ir_node *val = get_irn_n(node, 1);
3933 ir_node *new_val = be_transform_node(val);
3934 ia32_code_gen_t *cg = env_cg;
3935 ir_graph *irg = current_ir_graph;
3936 ir_node *res = NULL;
3937 ir_entity *fent = get_ia32_frame_ent(node);
3938 ir_mode *lsmode = get_ia32_ls_mode(node);
3940 ir_node *noreg, *new_ptr, *new_mem;
3944 if (! USE_SSE2(cg)) {
3945 /* SSE unit is not used -> skip this node. */
3949 ptr = get_irn_n(node, 0);
3950 new_ptr = be_transform_node(ptr);
3951 mem = get_irn_n(node, 2);
3952 new_mem = be_transform_node(mem);
3953 noreg = ia32_new_NoReg_gp(cg);
3954 dbgi = get_irn_dbg_info(node);
3956 /* Store SSE -> MEM */
3957 if (is_ia32_xLoad(skip_Proj(new_val))) {
3958 ir_node *ld = skip_Proj(new_val);
3960 /* we can vfld the value directly into the fpu */
3961 fent = get_ia32_frame_ent(ld);
3962 ptr = get_irn_n(ld, 0);
3963 offs = get_ia32_am_offs_int(ld);
3965 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
3967 set_ia32_frame_ent(res, fent);
3968 set_ia32_use_frame(res);
3969 set_ia32_ls_mode(res, lsmode);
3970 set_ia32_op_type(res, ia32_AddrModeD);
3974 /* Load MEM -> x87 */
3975 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3976 set_ia32_frame_ent(res, fent);
3977 set_ia32_use_frame(res);
3978 add_ia32_am_offs_int(res, offs);
3979 set_ia32_op_type(res, ia32_AddrModeS);
3980 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3985 /*********************************************************
3988 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3989 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3990 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3991 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3993 *********************************************************/
3996 * the BAD transformer.
3998 static ir_node *bad_transform(ir_node *node) {
3999 panic("No transform function for %+F available.\n", node);
4004 * Transform the Projs of an AddSP.
4006 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4007 ir_node *block = be_transform_node(get_nodes_block(node));
4008 ir_node *pred = get_Proj_pred(node);
4009 ir_node *new_pred = be_transform_node(pred);
4010 ir_graph *irg = current_ir_graph;
4011 dbg_info *dbgi = get_irn_dbg_info(node);
4012 long proj = get_Proj_proj(node);
4014 if (proj == pn_be_AddSP_sp) {
4015 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4016 pn_ia32_SubSP_stack);
4017 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4019 } else if(proj == pn_be_AddSP_res) {
4020 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4021 pn_ia32_SubSP_addr);
4022 } else if (proj == pn_be_AddSP_M) {
4023 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4027 return new_rd_Unknown(irg, get_irn_mode(node));
4031 * Transform the Projs of a SubSP.
4033 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4034 ir_node *block = be_transform_node(get_nodes_block(node));
4035 ir_node *pred = get_Proj_pred(node);
4036 ir_node *new_pred = be_transform_node(pred);
4037 ir_graph *irg = current_ir_graph;
4038 dbg_info *dbgi = get_irn_dbg_info(node);
4039 long proj = get_Proj_proj(node);
4041 if (proj == pn_be_SubSP_sp) {
4042 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4043 pn_ia32_AddSP_stack);
4044 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4046 } else if (proj == pn_be_SubSP_M) {
4047 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4051 return new_rd_Unknown(irg, get_irn_mode(node));
4055 * Transform and renumber the Projs from a Load.
4057 static ir_node *gen_Proj_Load(ir_node *node) {
4059 ir_node *block = be_transform_node(get_nodes_block(node));
4060 ir_node *pred = get_Proj_pred(node);
4061 ir_graph *irg = current_ir_graph;
4062 dbg_info *dbgi = get_irn_dbg_info(node);
4063 long proj = get_Proj_proj(node);
4066 /* loads might be part of source address mode matches, so we don't
4067 transform the ProjMs yet (with the exception of loads whose result is
4070 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4073 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4075 /* this is needed, because sometimes we have loops that are only
4076 reachable through the ProjM */
4077 be_enqueue_preds(node);
4078 /* do it in 2 steps, to silence firm verifier */
4079 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4080 set_Proj_proj(res, pn_ia32_Load_M);
4084 /* renumber the proj */
4085 new_pred = be_transform_node(pred);
4086 if (is_ia32_Load(new_pred)) {
4087 if (proj == pn_Load_res) {
4088 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4090 } else if (proj == pn_Load_M) {
4091 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4094 } else if(is_ia32_Conv_I2I(new_pred)) {
4095 set_irn_mode(new_pred, mode_T);
4096 if (proj == pn_Load_res) {
4097 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4098 } else if (proj == pn_Load_M) {
4099 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4101 } else if (is_ia32_xLoad(new_pred)) {
4102 if (proj == pn_Load_res) {
4103 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4105 } else if (proj == pn_Load_M) {
4106 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4109 } else if (is_ia32_vfld(new_pred)) {
4110 if (proj == pn_Load_res) {
4111 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4113 } else if (proj == pn_Load_M) {
4114 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4118 /* can happen for ProJMs when source address mode happened for the
4121 /* however it should not be the result proj, as that would mean the
4122 load had multiple users and should not have been used for
4124 if(proj != pn_Load_M) {
4125 panic("internal error: transformed node not a Load");
4127 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4131 return new_rd_Unknown(irg, get_irn_mode(node));
4135 * Transform and renumber the Projs from a DivMod like instruction.
4137 static ir_node *gen_Proj_DivMod(ir_node *node) {
4138 ir_node *block = be_transform_node(get_nodes_block(node));
4139 ir_node *pred = get_Proj_pred(node);
4140 ir_node *new_pred = be_transform_node(pred);
4141 ir_graph *irg = current_ir_graph;
4142 dbg_info *dbgi = get_irn_dbg_info(node);
4143 ir_mode *mode = get_irn_mode(node);
4144 long proj = get_Proj_proj(node);
4146 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4148 switch (get_irn_opcode(pred)) {
4152 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4154 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4162 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4164 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4172 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4173 case pn_DivMod_res_div:
4174 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4175 case pn_DivMod_res_mod:
4176 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4186 return new_rd_Unknown(irg, mode);
4190 * Transform and renumber the Projs from a CopyB.
4192 static ir_node *gen_Proj_CopyB(ir_node *node) {
4193 ir_node *block = be_transform_node(get_nodes_block(node));
4194 ir_node *pred = get_Proj_pred(node);
4195 ir_node *new_pred = be_transform_node(pred);
4196 ir_graph *irg = current_ir_graph;
4197 dbg_info *dbgi = get_irn_dbg_info(node);
4198 ir_mode *mode = get_irn_mode(node);
4199 long proj = get_Proj_proj(node);
4202 case pn_CopyB_M_regular:
4203 if (is_ia32_CopyB_i(new_pred)) {
4204 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4205 } else if (is_ia32_CopyB(new_pred)) {
4206 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4214 return new_rd_Unknown(irg, mode);
4218 * Transform and renumber the Projs from a vfdiv.
4220 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
4221 ir_node *block = be_transform_node(get_nodes_block(node));
4222 ir_node *pred = get_Proj_pred(node);
4223 ir_node *new_pred = be_transform_node(pred);
4224 ir_graph *irg = current_ir_graph;
4225 dbg_info *dbgi = get_irn_dbg_info(node);
4226 ir_mode *mode = get_irn_mode(node);
4227 long proj = get_Proj_proj(node);
4230 case pn_ia32_l_vfdiv_M:
4231 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4232 case pn_ia32_l_vfdiv_res:
4233 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4238 return new_rd_Unknown(irg, mode);
4242 * Transform and renumber the Projs from a Quot.
4244 static ir_node *gen_Proj_Quot(ir_node *node) {
4245 ir_node *block = be_transform_node(get_nodes_block(node));
4246 ir_node *pred = get_Proj_pred(node);
4247 ir_node *new_pred = be_transform_node(pred);
4248 ir_graph *irg = current_ir_graph;
4249 dbg_info *dbgi = get_irn_dbg_info(node);
4250 ir_mode *mode = get_irn_mode(node);
4251 long proj = get_Proj_proj(node);
4255 if (is_ia32_xDiv(new_pred)) {
4256 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4257 } else if (is_ia32_vfdiv(new_pred)) {
4258 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4262 if (is_ia32_xDiv(new_pred)) {
4263 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4264 } else if (is_ia32_vfdiv(new_pred)) {
4265 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4273 return new_rd_Unknown(irg, mode);
4277 * Transform the Thread Local Storage Proj.
4279 static ir_node *gen_Proj_tls(ir_node *node) {
4280 ir_node *block = be_transform_node(get_nodes_block(node));
4281 ir_graph *irg = current_ir_graph;
4282 dbg_info *dbgi = NULL;
4283 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4288 static ir_node *gen_be_Call(ir_node *node) {
4289 ir_node *res = be_duplicate_node(node);
4290 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4295 static ir_node *gen_be_IncSP(ir_node *node) {
4296 ir_node *res = be_duplicate_node(node);
4297 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4303 * Transform the Projs from a be_Call.
4305 static ir_node *gen_Proj_be_Call(ir_node *node) {
4306 ir_node *block = be_transform_node(get_nodes_block(node));
4307 ir_node *call = get_Proj_pred(node);
4308 ir_node *new_call = be_transform_node(call);
4309 ir_graph *irg = current_ir_graph;
4310 dbg_info *dbgi = get_irn_dbg_info(node);
4311 ir_type *method_type = be_Call_get_type(call);
4312 int n_res = get_method_n_ress(method_type);
4313 long proj = get_Proj_proj(node);
4314 ir_mode *mode = get_irn_mode(node);
4316 const arch_register_class_t *cls;
4318 /* The following is kinda tricky: If we're using SSE, then we have to
4319 * move the result value of the call in floating point registers to an
4320 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4321 * after the call, we have to make sure to correctly make the
4322 * MemProj and the result Proj use these 2 nodes
4324 if (proj == pn_be_Call_M_regular) {
4325 // get new node for result, are we doing the sse load/store hack?
4326 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4327 ir_node *call_res_new;
4328 ir_node *call_res_pred = NULL;
4330 if (call_res != NULL) {
4331 call_res_new = be_transform_node(call_res);
4332 call_res_pred = get_Proj_pred(call_res_new);
4335 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4336 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4337 pn_be_Call_M_regular);
4339 assert(is_ia32_xLoad(call_res_pred));
4340 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4344 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4345 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4346 && USE_SSE2(env_cg)) {
4348 ir_node *frame = get_irg_frame(irg);
4349 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4351 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4354 /* in case there is no memory output: create one to serialize the copy
4356 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4357 pn_be_Call_M_regular);
4358 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4359 pn_be_Call_first_res);
4361 /* store st(0) onto stack */
4362 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4364 set_ia32_op_type(fstp, ia32_AddrModeD);
4365 set_ia32_use_frame(fstp);
4367 /* load into SSE register */
4368 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4370 set_ia32_op_type(sse_load, ia32_AddrModeS);
4371 set_ia32_use_frame(sse_load);
4373 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4379 /* transform call modes */
4380 if (mode_is_data(mode)) {
4381 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4385 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4389 * Transform the Projs from a Cmp.
4391 static ir_node *gen_Proj_Cmp(ir_node *node)
4393 /* normally Cmps are processed when looking at Cond nodes, but this case
4394 * can happen in complicated Psi conditions */
4395 dbg_info *dbgi = get_irn_dbg_info(node);
4396 ir_node *block = get_nodes_block(node);
4397 ir_node *new_block = be_transform_node(block);
4398 ir_node *cmp = get_Proj_pred(node);
4399 ir_node *new_cmp = be_transform_node(cmp);
4400 long pnc = get_Proj_proj(node);
4403 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node);
4409 * Transform and potentially renumber Proj nodes.
4411 static ir_node *gen_Proj(ir_node *node) {
4412 ir_graph *irg = current_ir_graph;
4413 dbg_info *dbgi = get_irn_dbg_info(node);
4414 ir_node *pred = get_Proj_pred(node);
4415 long proj = get_Proj_proj(node);
4417 if (is_Store(pred)) {
4418 if (proj == pn_Store_M) {
4419 return be_transform_node(pred);
4422 return new_r_Bad(irg);
4424 } else if (is_Load(pred)) {
4425 return gen_Proj_Load(node);
4426 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4427 return gen_Proj_DivMod(node);
4428 } else if (is_CopyB(pred)) {
4429 return gen_Proj_CopyB(node);
4430 } else if (is_Quot(pred)) {
4431 return gen_Proj_Quot(node);
4432 } else if (is_ia32_l_vfdiv(pred)) {
4433 return gen_Proj_l_vfdiv(node);
4434 } else if (be_is_SubSP(pred)) {
4435 return gen_Proj_be_SubSP(node);
4436 } else if (be_is_AddSP(pred)) {
4437 return gen_Proj_be_AddSP(node);
4438 } else if (be_is_Call(pred)) {
4439 return gen_Proj_be_Call(node);
4440 } else if (is_Cmp(pred)) {
4441 return gen_Proj_Cmp(node);
4442 } else if (get_irn_op(pred) == op_Start) {
4443 if (proj == pn_Start_X_initial_exec) {
4444 ir_node *block = get_nodes_block(pred);
4447 /* we exchange the ProjX with a jump */
4448 block = be_transform_node(block);
4449 jump = new_rd_Jmp(dbgi, irg, block);
4452 if (node == be_get_old_anchor(anchor_tls)) {
4453 return gen_Proj_tls(node);
4456 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4460 ir_node *new_pred = be_transform_node(pred);
4461 ir_node *block = be_transform_node(get_nodes_block(node));
4462 ir_mode *mode = get_irn_mode(node);
4463 if (mode_needs_gp_reg(mode)) {
4464 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4465 get_Proj_proj(node));
4466 #ifdef DEBUG_libfirm
4467 new_proj->node_nr = node->node_nr;
4473 return be_duplicate_node(node);
4477 * Enters all transform functions into the generic pointer
4479 static void register_transformers(void)
4483 /* first clear the generic function pointer for all ops */
4484 clear_irp_opcodes_generic_func();
4486 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4487 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4525 /* transform ops from intrinsic lowering */
4547 GEN(ia32_l_X87toSSE);
4548 GEN(ia32_l_SSEtoX87);
4554 /* we should never see these nodes */
4569 /* handle generic backend nodes */
4578 op_Mulh = get_op_Mulh();
4587 * Pre-transform all unknown and noreg nodes.
4589 static void ia32_pretransform_node(void *arch_cg) {
4590 ia32_code_gen_t *cg = arch_cg;
4592 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4593 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4594 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4595 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4596 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4597 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4602 * Walker, checks if all ia32 nodes producing more than one result have
4603 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4605 static void add_missing_keep_walker(ir_node *node, void *data)
4608 unsigned found_projs = 0;
4609 const ir_edge_t *edge;
4610 ir_mode *mode = get_irn_mode(node);
4615 if(!is_ia32_irn(node))
4618 n_outs = get_ia32_n_res(node);
4621 if(is_ia32_SwitchJmp(node))
4624 assert(n_outs < (int) sizeof(unsigned) * 8);
4625 foreach_out_edge(node, edge) {
4626 ir_node *proj = get_edge_src_irn(edge);
4627 int pn = get_Proj_proj(proj);
4629 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4630 found_projs |= 1 << pn;
4634 /* are keeps missing? */
4636 for(i = 0; i < n_outs; ++i) {
4639 const arch_register_req_t *req;
4640 const arch_register_class_t *class;
4642 if(found_projs & (1 << i)) {
4646 req = get_ia32_out_req(node, i);
4651 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4655 block = get_nodes_block(node);
4656 in[0] = new_r_Proj(current_ir_graph, block, node,
4657 arch_register_class_mode(class), i);
4658 if(last_keep != NULL) {
4659 be_Keep_add_node(last_keep, class, in[0]);
4661 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4662 if(sched_is_scheduled(node)) {
4663 sched_add_after(node, last_keep);
4670 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4673 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4675 ir_graph *irg = be_get_birg_irg(cg->birg);
4676 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4679 /* do the transformation */
4680 void ia32_transform_graph(ia32_code_gen_t *cg) {
4681 ir_graph *irg = cg->irg;
4683 register_transformers();
4685 initial_fpcw = NULL;
4687 heights = heights_new(irg);
4688 calculate_non_address_mode_nodes(irg);
4690 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4692 free_non_address_mode_nodes();
4693 heights_free(heights);
4697 void ia32_init_transform(void)
4699 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");