2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
99 extern ir_op *get_op_Mulh(void);
101 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
102 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
103 ir_node *op1, ir_node *op2);
105 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
106 ir_node *block, ir_node *op1, ir_node *op2);
108 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
109 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
112 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
113 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
115 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
116 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 ir_node *op1, ir_node *op2, ir_node *fpcw);
119 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
120 ir_node *block, ir_node *op);
122 /****************************************************************************************************
124 * | | | | / _| | | (_)
125 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
126 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
127 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
128 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
130 ****************************************************************************************************/
132 static ir_node *try_create_Immediate(ir_node *node,
133 char immediate_constraint_type);
135 static ir_node *create_immediate_or_transform(ir_node *node,
136 char immediate_constraint_type);
138 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
139 dbg_info *dbgi, ir_node *block,
140 ir_node *op, ir_node *orig_node);
143 * Return true if a mode can be stored in the GP register set
145 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
146 if(mode == mode_fpcw)
148 if(get_mode_size_bits(mode) > 32)
150 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
154 * creates a unique ident by adding a number to a tag
156 * @param tag the tag string, must contain a %d if a number
159 static ident *unique_id(const char *tag)
161 static unsigned id = 0;
164 snprintf(str, sizeof(str), tag, ++id);
165 return new_id_from_str(str);
169 * Get a primitive type for a mode.
171 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
173 pmap_entry *e = pmap_find(types, mode);
178 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
179 res = new_type_primitive(new_id_from_str(buf), mode);
180 set_type_alignment_bytes(res, 16);
181 pmap_insert(types, mode, res);
189 * Get an atomic entity that is initialized with a tarval
191 static ir_entity *ia32_get_entity_for_tv(ia32_isa_t *isa, ir_node *cnst)
193 tarval *tv = get_Const_tarval(cnst);
194 pmap_entry *e = pmap_find(isa->tv_ent, tv);
199 ir_mode *mode = get_irn_mode(cnst);
200 ir_type *tp = get_Const_type(cnst);
201 if (tp == firm_unknown_type)
202 tp = get_prim_type(isa->types, mode);
204 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
206 set_entity_ld_ident(res, get_entity_ident(res));
207 set_entity_visibility(res, visibility_local);
208 set_entity_variability(res, variability_constant);
209 set_entity_allocation(res, allocation_static);
211 /* we create a new entity here: It's initialization must resist on the
213 rem = current_ir_graph;
214 current_ir_graph = get_const_code_irg();
215 set_atomic_ent_value(res, new_Const_type(tv, tp));
216 current_ir_graph = rem;
218 pmap_insert(isa->tv_ent, tv, res);
226 static int is_Const_0(ir_node *node) {
227 return is_Const(node) && is_Const_null(node);
230 static int is_Const_1(ir_node *node) {
231 return is_Const(node) && is_Const_one(node);
234 static int is_Const_Minus_1(ir_node *node) {
235 return is_Const(node) && is_Const_all_one(node);
239 * Transforms a Const.
241 static ir_node *gen_Const(ir_node *node) {
242 ir_graph *irg = current_ir_graph;
243 ir_node *old_block = get_nodes_block(node);
244 ir_node *block = be_transform_node(old_block);
245 dbg_info *dbgi = get_irn_dbg_info(node);
246 ir_mode *mode = get_irn_mode(node);
248 if (mode_is_float(mode)) {
250 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
251 ir_node *nomem = new_NoMem();
255 if (USE_SSE2(env_cg)) {
256 if (is_Const_null(node)) {
257 load = new_rd_ia32_xZero(dbgi, irg, block);
258 set_ia32_ls_mode(load, mode);
261 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
263 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
265 set_ia32_op_type(load, ia32_AddrModeS);
266 set_ia32_am_sc(load, floatent);
267 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
268 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
271 if (is_Const_null(node)) {
272 load = new_rd_ia32_vfldz(dbgi, irg, block);
274 } else if (is_Const_one(node)) {
275 load = new_rd_ia32_vfld1(dbgi, irg, block);
278 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
280 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
281 set_ia32_op_type(load, ia32_AddrModeS);
282 set_ia32_am_sc(load, floatent);
283 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
284 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
286 set_ia32_ls_mode(load, mode);
289 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
291 /* Const Nodes before the initial IncSP are a bad idea, because
292 * they could be spilled and we have no SP ready at that point yet.
293 * So add a dependency to the initial frame pointer calculation to
294 * avoid that situation.
296 if (get_irg_start_block(irg) == block) {
297 add_irn_dep(load, get_irg_frame(irg));
300 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
304 tarval *tv = get_Const_tarval(node);
307 tv = tarval_convert_to(tv, mode_Iu);
309 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
311 panic("couldn't convert constant tarval (%+F)", node);
313 val = get_tarval_long(tv);
315 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
316 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
319 get_ia32_flags(cnst) | arch_irn_flags_modify_flags);
323 if (get_irg_start_block(irg) == block) {
324 add_irn_dep(cnst, get_irg_frame(irg));
332 * Transforms a SymConst.
334 static ir_node *gen_SymConst(ir_node *node) {
335 ir_graph *irg = current_ir_graph;
336 ir_node *old_block = get_nodes_block(node);
337 ir_node *block = be_transform_node(old_block);
338 dbg_info *dbgi = get_irn_dbg_info(node);
339 ir_mode *mode = get_irn_mode(node);
342 if (mode_is_float(mode)) {
343 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
344 ir_node *nomem = new_NoMem();
346 if (USE_SSE2(env_cg))
347 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
349 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
350 set_ia32_am_sc(cnst, get_SymConst_entity(node));
351 set_ia32_use_frame(cnst);
355 if(get_SymConst_kind(node) != symconst_addr_ent) {
356 panic("backend only support symconst_addr_ent (at %+F)", node);
358 entity = get_SymConst_entity(node);
359 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
362 /* Const Nodes before the initial IncSP are a bad idea, because
363 * they could be spilled and we have no SP ready at that point yet
365 if (get_irg_start_block(irg) == block) {
366 add_irn_dep(cnst, get_irg_frame(irg));
369 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
374 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
375 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
376 static const struct {
378 const char *ent_name;
379 const char *cnst_str;
382 } names [ia32_known_const_max] = {
383 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
384 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
385 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
386 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
387 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
389 static ir_entity *ent_cache[ia32_known_const_max];
391 const char *tp_name, *ent_name, *cnst_str;
399 ent_name = names[kct].ent_name;
400 if (! ent_cache[kct]) {
401 tp_name = names[kct].tp_name;
402 cnst_str = names[kct].cnst_str;
404 switch (names[kct].mode) {
405 case 0: mode = mode_Iu; break;
406 case 1: mode = mode_Lu; break;
407 default: mode = mode_F; break;
409 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
410 tp = new_type_primitive(new_id_from_str(tp_name), mode);
411 /* set the specified alignment */
412 set_type_alignment_bytes(tp, names[kct].align);
414 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
416 set_entity_ld_ident(ent, get_entity_ident(ent));
417 set_entity_visibility(ent, visibility_local);
418 set_entity_variability(ent, variability_constant);
419 set_entity_allocation(ent, allocation_static);
421 /* we create a new entity here: It's initialization must resist on the
423 rem = current_ir_graph;
424 current_ir_graph = get_const_code_irg();
425 cnst = new_Const(mode, tv);
426 current_ir_graph = rem;
428 set_atomic_ent_value(ent, cnst);
430 /* cache the entry */
431 ent_cache[kct] = ent;
434 return ent_cache[kct];
439 * Prints the old node name on cg obst and returns a pointer to it.
441 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
442 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
444 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
445 obstack_1grow(isa->name_obst, 0);
446 return obstack_finish(isa->name_obst);
450 int use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
458 load = get_Proj_pred(node);
459 pn = get_Proj_proj(node);
460 if(!is_Load(load) || pn != pn_Load_res)
462 if(get_nodes_block(load) != block)
464 /* we only use address mode if we're the only user of the load */
465 if(get_irn_n_edges(node) > 1)
468 mode = get_irn_mode(node);
469 if(!mode_needs_gp_reg(mode))
471 if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
474 /* don't do AM if other node inputs depend on the load (via mem-proj) */
475 if(other != NULL && get_nodes_block(other) == block
476 && heights_reachable_in_block(heights, other, load))
482 typedef struct ia32_address_mode_t ia32_address_mode_t;
483 struct ia32_address_mode_t {
487 ia32_op_type_t op_type;
494 static void build_address(ia32_address_mode_t *am, ir_node *node)
496 ia32_address_t *addr = &am->addr;
497 ir_node *load = get_Proj_pred(node);
498 ir_node *ptr = get_Load_ptr(load);
499 ir_node *mem = get_Load_mem(load);
500 ir_node *new_mem = be_transform_node(mem);
504 am->ls_mode = get_Load_mode(load);
505 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
507 /* construct load address */
508 ia32_create_address_mode(addr, ptr, 0);
513 base = ia32_new_NoReg_gp(env_cg);
515 base = be_transform_node(base);
519 index = ia32_new_NoReg_gp(env_cg);
521 index = be_transform_node(index);
529 static void set_address(ir_node *node, ia32_address_t *addr)
531 set_ia32_am_scale(node, addr->scale);
532 set_ia32_am_sc(node, addr->symconst_ent);
533 set_ia32_am_offs_int(node, addr->offset);
534 if(addr->symconst_sign)
535 set_ia32_am_sc_sign(node);
537 set_ia32_use_frame(node);
538 set_ia32_frame_ent(node, addr->frame_entity);
541 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
543 set_address(node, &am->addr);
545 set_ia32_op_type(node, am->op_type);
546 set_ia32_ls_mode(node, am->ls_mode);
548 set_ia32_commutative(node);
552 match_commutative = 1 << 0,
553 match_am_and_immediates = 1 << 1,
554 match_no_am = 1 << 2,
555 match_8_16_bit_am = 1 << 3
558 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
559 ir_node *op1, ir_node *op2, match_flags_t flags)
561 ia32_address_t *addr = &am->addr;
562 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
567 int use_am_and_immediates;
569 memset(am, 0, sizeof(am[0]));
571 commutative = (flags & match_commutative) != 0;
572 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
573 use_am = ! (flags & match_no_am);
574 if(!(flags & match_8_16_bit_am)
575 && get_mode_size_bits(get_irn_mode(op1)) < 32)
578 new_op2 = try_create_Immediate(op2, 0);
579 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
580 build_address(am, op2);
581 new_op1 = be_transform_node(op1);
583 am->op_type = ia32_AddrModeS;
584 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
585 use_am && use_source_address_mode(block, op1, op2)) {
586 build_address(am, op1);
587 if(new_op2 != NULL) {
590 new_op1 = be_transform_node(op2);
594 am->op_type = ia32_AddrModeS;
596 new_op1 = be_transform_node(op1);
598 new_op2 = be_transform_node(op2);
599 am->op_type = ia32_Normal;
601 if(addr->base == NULL)
602 addr->base = noreg_gp;
603 if(addr->index == NULL)
604 addr->index = noreg_gp;
605 if(addr->mem == NULL)
606 addr->mem = new_NoMem();
608 am->new_op1 = new_op1;
609 am->new_op2 = new_op2;
610 am->commutative = commutative;
613 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
615 ir_graph *irg = current_ir_graph;
619 if(am->mem_proj == NULL)
622 /* we have to create a mode_T so the old MemProj can attach to us */
623 mode = get_irn_mode(node);
624 load = get_Proj_pred(am->mem_proj);
626 mark_irn_visited(load);
627 be_set_transformed_node(load, node);
630 set_irn_mode(node, mode_T);
631 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
638 * Construct a standard binary operation, set AM and immediate if required.
640 * @param op1 The first operand
641 * @param op2 The second operand
642 * @param func The node constructor function
643 * @return The constructed ia32 node.
645 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
646 construct_binop_func *func, int commutative)
648 ir_node *src_block = get_nodes_block(node);
649 ir_node *block = be_transform_node(src_block);
650 ir_graph *irg = current_ir_graph;
651 dbg_info *dbgi = get_irn_dbg_info(node);
653 ia32_address_mode_t am;
654 ia32_address_t *addr = &am.addr;
655 match_flags_t flags = 0;
658 flags |= match_commutative;
660 match_arguments(&am, src_block, op1, op2, flags);
662 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
663 am.new_op1, am.new_op2);
664 set_am_attributes(new_node, &am);
665 /* we can't use source address mode anymore when using immediates */
666 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
667 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
668 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
670 new_node = fix_mem_proj(new_node, &am);
676 * Construct a standard binary operation, set AM and immediate if required.
678 * @param op1 The first operand
679 * @param op2 The second operand
680 * @param func The node constructor function
681 * @return The constructed ia32 node.
683 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
684 construct_binop_func *func)
686 ir_node *block = be_transform_node(get_nodes_block(node));
687 ir_node *new_op1 = be_transform_node(op1);
688 ir_node *new_op2 = be_transform_node(op2);
689 ir_node *new_node = NULL;
690 dbg_info *dbgi = get_irn_dbg_info(node);
691 ir_graph *irg = current_ir_graph;
692 ir_mode *mode = get_irn_mode(node);
693 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
694 ir_node *nomem = new_NoMem();
696 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1,
698 if (is_op_commutative(get_irn_op(node))) {
699 set_ia32_commutative(new_node);
701 set_ia32_ls_mode(new_node, mode);
703 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
708 static ir_node *get_fpcw(void)
711 if(initial_fpcw != NULL)
714 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
715 &ia32_fp_cw_regs[REG_FPCW]);
716 initial_fpcw = be_transform_node(fpcw);
722 * Construct a standard binary operation, set AM and immediate if required.
724 * @param op1 The first operand
725 * @param op2 The second operand
726 * @param func The node constructor function
727 * @return The constructed ia32 node.
729 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
730 construct_binop_float_func *func)
732 ir_node *block = be_transform_node(get_nodes_block(node));
733 ir_node *new_op1 = be_transform_node(op1);
734 ir_node *new_op2 = be_transform_node(op2);
735 ir_node *new_node = NULL;
736 dbg_info *dbgi = get_irn_dbg_info(node);
737 ir_graph *irg = current_ir_graph;
738 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
739 ir_node *nomem = new_NoMem();
741 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1, new_op2,
743 if (is_op_commutative(get_irn_op(node))) {
744 set_ia32_commutative(new_node);
747 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
753 * Construct a shift/rotate binary operation, sets AM and immediate if required.
755 * @param op1 The first operand
756 * @param op2 The second operand
757 * @param func The node constructor function
758 * @return The constructed ia32 node.
760 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
761 construct_shift_func *func)
763 dbg_info *dbgi = get_irn_dbg_info(node);
764 ir_graph *irg = current_ir_graph;
765 ir_node *block = get_nodes_block(node);
766 ir_node *new_block = be_transform_node(block);
767 ir_node *new_op1 = be_transform_node(op1);
768 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
771 assert(! mode_is_float(get_irn_mode(node))
772 && "Shift/Rotate with float not supported");
774 res = func(dbgi, irg, new_block, new_op1, new_op2);
775 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
777 /* lowered shift instruction may have a dependency operand, handle it here */
778 if (get_irn_arity(node) == 3) {
779 /* we have a dependency */
780 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
781 add_irn_dep(res, new_dep);
789 * Construct a standard unary operation, set AM and immediate if required.
791 * @param op The operand
792 * @param func The node constructor function
793 * @return The constructed ia32 node.
795 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
797 ir_node *block = be_transform_node(get_nodes_block(node));
798 ir_node *new_op = be_transform_node(op);
799 ir_node *new_node = NULL;
800 ir_graph *irg = current_ir_graph;
801 dbg_info *dbgi = get_irn_dbg_info(node);
803 new_node = func(dbgi, irg, block, new_op);
805 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
810 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
811 ia32_address_t *addr)
813 ir_graph *irg = current_ir_graph;
814 ir_node *base = addr->base;
815 ir_node *index = addr->index;
819 base = ia32_new_NoReg_gp(env_cg);
821 base = be_transform_node(base);
825 index = ia32_new_NoReg_gp(env_cg);
827 index = be_transform_node(index);
830 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
831 set_address(res, addr);
836 static int am_has_immediates(const ia32_address_t *addr)
838 return addr->offset != 0 || addr->symconst_ent != NULL
839 || addr->frame_entity || addr->use_frame;
843 * Creates an ia32 Add.
845 * @return the created ia32 Add node
847 static ir_node *gen_Add(ir_node *node) {
848 ir_node *block = be_transform_node(get_nodes_block(node));
849 ir_node *op1 = get_Add_left(node);
850 ir_node *op2 = get_Add_right(node);
853 ir_graph *irg = current_ir_graph;
854 dbg_info *dbgi = get_irn_dbg_info(node);
855 ir_mode *mode = get_irn_mode(node);
856 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
857 ir_node *src_block = get_nodes_block(node);
858 ir_node *add_immediate_op;
860 ia32_address_mode_t am;
862 if (mode_is_float(mode)) {
863 if (USE_SSE2(env_cg))
864 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
866 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
871 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
872 * 1. Add with immediate -> Lea
873 * 2. Add with possible source address mode -> Add
874 * 3. Otherwise -> Lea
876 memset(&addr, 0, sizeof(addr));
877 ia32_create_address_mode(&addr, node, 1);
878 add_immediate_op = NULL;
880 if(addr.base == NULL && addr.index == NULL) {
881 new_op = new_rd_ia32_Const(dbgi, irg, block, addr.symconst_ent,
882 addr.symconst_sign, addr.offset);
883 add_irn_dep(new_op, get_irg_frame(irg));
884 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
887 /* add with immediate? */
888 if(addr.index == NULL) {
889 add_immediate_op = addr.base;
890 } else if(addr.base == NULL && addr.scale == 0) {
891 add_immediate_op = addr.index;
894 if(add_immediate_op != NULL) {
895 if(!am_has_immediates(&addr)) {
897 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
900 return be_transform_node(add_immediate_op);
903 new_op = create_lea_from_address(dbgi, block, &addr);
904 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
908 /* test if we can use source address mode */
909 memset(&am, 0, sizeof(am));
911 if(use_source_address_mode(src_block, op2, op1)) {
912 build_address(&am, op2);
913 new_op1 = be_transform_node(op1);
914 } else if(use_source_address_mode(src_block, op1, op2)) {
915 build_address(&am, op1);
916 new_op1 = be_transform_node(op2);
918 /* construct an Add with source address mode */
919 if(new_op1 != NULL) {
920 ia32_address_t *am_addr = &am.addr;
921 new_op = new_rd_ia32_Add(dbgi, irg, block, am_addr->base, am_addr->index,
922 am_addr->mem, new_op1, noreg);
923 set_address(new_op, am_addr);
924 set_ia32_op_type(new_op, ia32_AddrModeS);
925 set_ia32_ls_mode(new_op, am.ls_mode);
926 set_ia32_commutative(new_op);
927 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
929 new_op = fix_mem_proj(new_op, &am);
934 /* otherwise construct a lea */
935 new_op = create_lea_from_address(dbgi, block, &addr);
936 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
941 * Creates an ia32 Mul.
943 * @return the created ia32 Mul node
945 static ir_node *gen_Mul(ir_node *node) {
946 ir_node *op1 = get_Mul_left(node);
947 ir_node *op2 = get_Mul_right(node);
948 ir_mode *mode = get_irn_mode(node);
950 if (mode_is_float(mode)) {
951 if (USE_SSE2(env_cg))
952 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
954 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
958 for the lower 32bit of the result it doesn't matter whether we use
959 signed or unsigned multiplication so we use IMul as it has fewer
962 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
966 * Creates an ia32 Mulh.
967 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
968 * this result while Mul returns the lower 32 bit.
970 * @return the created ia32 Mulh node
972 static ir_node *gen_Mulh(ir_node *node) {
973 ir_node *block = be_transform_node(get_nodes_block(node));
974 ir_node *op1 = get_irn_n(node, 0);
975 ir_node *new_op1 = be_transform_node(op1);
976 ir_node *op2 = get_irn_n(node, 1);
977 ir_node *new_op2 = be_transform_node(op2);
978 ir_graph *irg = current_ir_graph;
979 dbg_info *dbgi = get_irn_dbg_info(node);
980 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
981 ir_mode *mode = get_irn_mode(node);
982 ir_node *proj_EDX, *res;
984 assert(!mode_is_float(mode) && "Mulh with float not supported");
985 if (mode_is_signed(mode)) {
986 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_NoMem(),
989 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(), new_op1,
993 set_ia32_commutative(res);
995 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1003 * Creates an ia32 And.
1005 * @return The created ia32 And node
1007 static ir_node *gen_And(ir_node *node) {
1008 ir_node *op1 = get_And_left(node);
1009 ir_node *op2 = get_And_right(node);
1010 assert(! mode_is_float(get_irn_mode(node)));
1012 /* is it a zero extension? */
1013 if (is_Const(op2)) {
1014 tarval *tv = get_Const_tarval(op2);
1015 long v = get_tarval_long(tv);
1017 if (v == 0xFF || v == 0xFFFF) {
1018 dbg_info *dbgi = get_irn_dbg_info(node);
1019 ir_node *block = get_nodes_block(node);
1026 assert(v == 0xFFFF);
1029 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1035 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
1041 * Creates an ia32 Or.
1043 * @return The created ia32 Or node
1045 static ir_node *gen_Or(ir_node *node) {
1046 ir_node *op1 = get_Or_left(node);
1047 ir_node *op2 = get_Or_right(node);
1049 assert (! mode_is_float(get_irn_mode(node)));
1050 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
1056 * Creates an ia32 Eor.
1058 * @return The created ia32 Eor node
1060 static ir_node *gen_Eor(ir_node *node) {
1061 ir_node *op1 = get_Eor_left(node);
1062 ir_node *op2 = get_Eor_right(node);
1064 assert(! mode_is_float(get_irn_mode(node)));
1065 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
1070 * Creates an ia32 Sub.
1072 * @return The created ia32 Sub node
1074 static ir_node *gen_Sub(ir_node *node) {
1075 ir_node *op1 = get_Sub_left(node);
1076 ir_node *op2 = get_Sub_right(node);
1077 ir_mode *mode = get_irn_mode(node);
1079 if (mode_is_float(mode)) {
1080 if (USE_SSE2(env_cg))
1081 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1083 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1087 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1091 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1097 * Generates an ia32 DivMod with additional infrastructure for the
1098 * register allocator if needed.
1100 * @param dividend -no comment- :)
1101 * @param divisor -no comment- :)
1102 * @param dm_flav flavour_Div/Mod/DivMod
1103 * @return The created ia32 DivMod node
1105 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1106 ir_node *divisor, ia32_op_flavour_t dm_flav)
1108 ir_node *block = be_transform_node(get_nodes_block(node));
1109 ir_node *new_dividend = be_transform_node(dividend);
1110 ir_node *new_divisor = be_transform_node(divisor);
1111 ir_graph *irg = current_ir_graph;
1112 dbg_info *dbgi = get_irn_dbg_info(node);
1113 ir_mode *mode = get_irn_mode(node);
1114 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1115 ir_node *res, *proj_div, *proj_mod;
1116 ir_node *sign_extension;
1117 ir_node *mem, *new_mem;
1120 proj_div = proj_mod = NULL;
1124 mem = get_Div_mem(node);
1125 mode = get_Div_resmode(node);
1126 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1127 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1130 mem = get_Mod_mem(node);
1131 mode = get_Mod_resmode(node);
1132 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1133 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1135 case flavour_DivMod:
1136 mem = get_DivMod_mem(node);
1137 mode = get_DivMod_resmode(node);
1138 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1139 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1140 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1143 panic("invalid divmod flavour!");
1145 new_mem = be_transform_node(mem);
1147 if (mode_is_signed(mode)) {
1148 /* in signed mode, we need to sign extend the dividend */
1149 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1150 add_irn_dep(produceval, get_irg_frame(irg));
1151 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1154 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1155 set_ia32_flags(sign_extension, get_ia32_flags(sign_extension) | arch_irn_flags_modify_flags);
1156 add_irn_dep(sign_extension, get_irg_frame(irg));
1159 if (mode_is_signed(mode)) {
1160 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
1161 new_dividend, sign_extension, new_divisor, dm_flav);
1163 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem, new_dividend,
1164 sign_extension, new_divisor, dm_flav);
1167 set_ia32_exc_label(res, has_exc);
1168 set_irn_pinned(res, get_irn_pinned(node));
1170 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1177 * Wrapper for generate_DivMod. Sets flavour_Mod.
1180 static ir_node *gen_Mod(ir_node *node) {
1181 return generate_DivMod(node, get_Mod_left(node),
1182 get_Mod_right(node), flavour_Mod);
1186 * Wrapper for generate_DivMod. Sets flavour_Div.
1189 static ir_node *gen_Div(ir_node *node) {
1190 return generate_DivMod(node, get_Div_left(node),
1191 get_Div_right(node), flavour_Div);
1195 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1197 static ir_node *gen_DivMod(ir_node *node) {
1198 return generate_DivMod(node, get_DivMod_left(node),
1199 get_DivMod_right(node), flavour_DivMod);
1205 * Creates an ia32 floating Div.
1207 * @return The created ia32 xDiv node
1209 static ir_node *gen_Quot(ir_node *node) {
1210 ir_node *block = be_transform_node(get_nodes_block(node));
1211 ir_node *op1 = get_Quot_left(node);
1212 ir_node *new_op1 = be_transform_node(op1);
1213 ir_node *op2 = get_Quot_right(node);
1214 ir_node *new_op2 = be_transform_node(op2);
1215 ir_graph *irg = current_ir_graph;
1216 dbg_info *dbgi = get_irn_dbg_info(node);
1217 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1218 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1221 if (USE_SSE2(env_cg)) {
1222 ir_mode *mode = get_irn_mode(op1);
1223 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, nomem, new_op1,
1225 set_ia32_ls_mode(new_op, mode);
1227 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, nomem, new_op1,
1228 new_op2, get_fpcw());
1230 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1236 * Creates an ia32 Shl.
1238 * @return The created ia32 Shl node
1240 static ir_node *gen_Shl(ir_node *node) {
1241 ir_node *right = get_Shl_right(node);
1243 /* test whether we can build a lea */
1244 if(is_Const(right)) {
1245 tarval *tv = get_Const_tarval(right);
1246 if(tarval_is_long(tv)) {
1247 long val = get_tarval_long(tv);
1248 if(val >= 0 && val <= 3) {
1249 ir_graph *irg = current_ir_graph;
1250 dbg_info *dbgi = get_irn_dbg_info(node);
1251 ir_node *block = be_transform_node(get_nodes_block(node));
1252 ir_node *base = ia32_new_NoReg_gp(env_cg);
1253 ir_node *index = be_transform_node(get_Shl_left(node));
1254 ir_node *res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1255 set_ia32_am_scale(res, val);
1256 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1262 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1269 * Creates an ia32 Shr.
1271 * @return The created ia32 Shr node
1273 static ir_node *gen_Shr(ir_node *node) {
1274 return gen_shift_binop(node, get_Shr_left(node),
1275 get_Shr_right(node), new_rd_ia32_Shr);
1281 * Creates an ia32 Sar.
1283 * @return The created ia32 Shrs node
1285 static ir_node *gen_Shrs(ir_node *node) {
1286 ir_node *left = get_Shrs_left(node);
1287 ir_node *right = get_Shrs_right(node);
1288 ir_mode *mode = get_irn_mode(node);
1289 if(is_Const(right) && mode == mode_Is) {
1290 tarval *tv = get_Const_tarval(right);
1291 long val = get_tarval_long(tv);
1293 /* this is a sign extension */
1294 ir_graph *irg = current_ir_graph;
1295 dbg_info *dbgi = get_irn_dbg_info(node);
1296 ir_node *block = be_transform_node(get_nodes_block(node));
1298 ir_node *new_op = be_transform_node(op);
1299 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1300 add_irn_dep(pval, get_irg_frame(irg));
1302 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1306 /* 8 or 16 bit sign extension? */
1307 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1308 ir_node *shl_left = get_Shl_left(left);
1309 ir_node *shl_right = get_Shl_right(left);
1310 if(is_Const(shl_right)) {
1311 tarval *tv1 = get_Const_tarval(right);
1312 tarval *tv2 = get_Const_tarval(shl_right);
1313 if(tv1 == tv2 && tarval_is_long(tv1)) {
1314 long val = get_tarval_long(tv1);
1315 if(val == 16 || val == 24) {
1316 dbg_info *dbgi = get_irn_dbg_info(node);
1317 ir_node *block = get_nodes_block(node);
1327 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1336 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1342 * Creates an ia32 RotL.
1344 * @param op1 The first operator
1345 * @param op2 The second operator
1346 * @return The created ia32 RotL node
1348 static ir_node *gen_RotL(ir_node *node,
1349 ir_node *op1, ir_node *op2) {
1350 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1356 * Creates an ia32 RotR.
1357 * NOTE: There is no RotR with immediate because this would always be a RotL
1358 * "imm-mode_size_bits" which can be pre-calculated.
1360 * @param op1 The first operator
1361 * @param op2 The second operator
1362 * @return The created ia32 RotR node
1364 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1366 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1372 * Creates an ia32 RotR or RotL (depending on the found pattern).
1374 * @return The created ia32 RotL or RotR node
1376 static ir_node *gen_Rot(ir_node *node) {
1377 ir_node *rotate = NULL;
1378 ir_node *op1 = get_Rot_left(node);
1379 ir_node *op2 = get_Rot_right(node);
1381 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1382 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1383 that means we can create a RotR instead of an Add and a RotL */
1385 if (get_irn_op(op2) == op_Add) {
1387 ir_node *left = get_Add_left(add);
1388 ir_node *right = get_Add_right(add);
1389 if (is_Const(right)) {
1390 tarval *tv = get_Const_tarval(right);
1391 ir_mode *mode = get_irn_mode(node);
1392 long bits = get_mode_size_bits(mode);
1394 if (get_irn_op(left) == op_Minus &&
1395 tarval_is_long(tv) &&
1396 get_tarval_long(tv) == bits)
1398 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1399 rotate = gen_RotR(node, op1, get_Minus_op(left));
1404 if (rotate == NULL) {
1405 rotate = gen_RotL(node, op1, op2);
1414 * Transforms a Minus node.
1416 * @param op The Minus operand
1417 * @return The created ia32 Minus node
1419 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1420 ir_node *block = be_transform_node(get_nodes_block(node));
1421 ir_graph *irg = current_ir_graph;
1422 dbg_info *dbgi = get_irn_dbg_info(node);
1423 ir_mode *mode = get_irn_mode(node);
1428 if (mode_is_float(mode)) {
1429 ir_node *new_op = be_transform_node(op);
1430 if (USE_SSE2(env_cg)) {
1431 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1432 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1433 ir_node *nomem = new_rd_NoMem(irg);
1435 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1438 size = get_mode_size_bits(mode);
1439 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1441 set_ia32_am_sc(res, ent);
1442 set_ia32_op_type(res, ia32_AddrModeS);
1443 set_ia32_ls_mode(res, mode);
1445 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1448 res = gen_unop(node, op, new_rd_ia32_Neg);
1451 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1457 * Transforms a Minus node.
1459 * @return The created ia32 Minus node
1461 static ir_node *gen_Minus(ir_node *node) {
1462 return gen_Minus_ex(node, get_Minus_op(node));
1465 static ir_node *create_Immediate_from_int(int val)
1467 ir_graph *irg = current_ir_graph;
1468 ir_node *start_block = get_irg_start_block(irg);
1469 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, 0, val);
1470 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
1475 static ir_node *gen_bin_Not(ir_node *node)
1477 ir_graph *irg = current_ir_graph;
1478 dbg_info *dbgi = get_irn_dbg_info(node);
1479 ir_node *block = be_transform_node(get_nodes_block(node));
1480 ir_node *op = get_Not_op(node);
1481 ir_node *new_op = be_transform_node(op);
1482 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1483 ir_node *nomem = new_NoMem();
1484 ir_node *one = create_Immediate_from_int(1);
1486 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, nomem, new_op, one);
1490 * Transforms a Not node.
1492 * @return The created ia32 Not node
1494 static ir_node *gen_Not(ir_node *node) {
1495 ir_node *op = get_Not_op(node);
1496 ir_mode *mode = get_irn_mode(node);
1498 if(mode == mode_b) {
1499 return gen_bin_Not(node);
1502 assert (! mode_is_float(get_irn_mode(node)));
1503 return gen_unop(node, op, new_rd_ia32_Not);
1509 * Transforms an Abs node.
1511 * @return The created ia32 Abs node
1513 static ir_node *gen_Abs(ir_node *node) {
1514 ir_node *block = be_transform_node(get_nodes_block(node));
1515 ir_node *op = get_Abs_op(node);
1516 ir_node *new_op = be_transform_node(op);
1517 ir_graph *irg = current_ir_graph;
1518 dbg_info *dbgi = get_irn_dbg_info(node);
1519 ir_mode *mode = get_irn_mode(node);
1520 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1521 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1522 ir_node *nomem = new_NoMem();
1527 if (mode_is_float(mode)) {
1528 if (USE_SSE2(env_cg)) {
1529 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
1531 size = get_mode_size_bits(mode);
1532 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1534 set_ia32_am_sc(res, ent);
1536 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1538 set_ia32_op_type(res, ia32_AddrModeS);
1539 set_ia32_ls_mode(res, mode);
1542 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1543 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1547 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1548 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1551 add_irn_dep(pval, get_irg_frame(irg));
1552 SET_IA32_ORIG_NODE(sign_extension,
1553 ia32_get_old_node_name(env_cg, node));
1555 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
1557 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1559 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
1561 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1568 * Transforms a Load.
1570 * @return the created ia32 Load node
1572 static ir_node *gen_Load(ir_node *node) {
1573 ir_node *old_block = get_nodes_block(node);
1574 ir_node *block = be_transform_node(old_block);
1575 ir_node *ptr = get_Load_ptr(node);
1576 ir_node *mem = get_Load_mem(node);
1577 ir_node *new_mem = be_transform_node(mem);
1580 ir_graph *irg = current_ir_graph;
1581 dbg_info *dbgi = get_irn_dbg_info(node);
1582 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1583 ir_mode *mode = get_Load_mode(node);
1586 ia32_address_t addr;
1588 /* construct load address */
1589 memset(&addr, 0, sizeof(addr));
1590 ia32_create_address_mode(&addr, ptr, 0);
1597 base = be_transform_node(base);
1603 index = be_transform_node(index);
1606 if (mode_is_float(mode)) {
1607 if (USE_SSE2(env_cg)) {
1608 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1610 res_mode = mode_xmm;
1612 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1614 res_mode = mode_vfp;
1620 /* create a conv node with address mode for smaller modes */
1621 if(get_mode_size_bits(mode) < 32) {
1622 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1623 new_mem, noreg, mode);
1625 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1630 set_irn_pinned(new_op, get_irn_pinned(node));
1631 set_ia32_op_type(new_op, ia32_AddrModeS);
1632 set_ia32_ls_mode(new_op, mode);
1633 set_address(new_op, &addr);
1635 /* make sure we are scheduled behind the initial IncSP/Barrier
1636 * to avoid spills being placed before it
1638 if (block == get_irg_start_block(irg)) {
1639 add_irn_dep(new_op, get_irg_frame(irg));
1642 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1643 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1648 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1649 ir_node *ptr, ir_mode *mode, ir_node *other)
1656 /* we only use address mode if we're the only user of the load */
1657 if(get_irn_n_edges(node) > 1)
1660 load = get_Proj_pred(node);
1663 if(get_nodes_block(load) != block)
1666 /* Store should be attached to the load */
1667 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1669 /* store should have the same pointer as the load */
1670 if(get_Load_ptr(load) != ptr)
1673 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1674 if(other != NULL && get_nodes_block(other) == block
1675 && heights_reachable_in_block(heights, other, load))
1678 assert(get_Load_mode(load) == mode);
1683 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1684 ir_node *mem, ir_node *ptr, ir_mode *mode,
1685 construct_binop_dest_func *func,
1686 construct_binop_dest_func *func8bit,
1689 ir_node *src_block = get_nodes_block(node);
1691 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1692 ir_graph *irg = current_ir_graph;
1696 ia32_address_mode_t am;
1697 ia32_address_t *addr = &am.addr;
1698 memset(&am, 0, sizeof(am));
1700 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1701 build_address(&am, op1);
1702 new_op = create_immediate_or_transform(op2, 0);
1703 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1704 build_address(&am, op2);
1705 new_op = create_immediate_or_transform(op1, 0);
1710 if(addr->base == NULL)
1711 addr->base = noreg_gp;
1712 if(addr->index == NULL)
1713 addr->index = noreg_gp;
1714 if(addr->mem == NULL)
1715 addr->mem = new_NoMem();
1717 dbgi = get_irn_dbg_info(node);
1718 block = be_transform_node(src_block);
1719 if(get_mode_size_bits(mode) == 8) {
1720 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1723 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1726 set_address(new_node, addr);
1727 set_ia32_op_type(new_node, ia32_AddrModeD);
1728 set_ia32_ls_mode(new_node, mode);
1729 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1734 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1735 ir_node *ptr, ir_mode *mode,
1736 construct_unop_dest_func *func)
1738 ir_node *src_block = get_nodes_block(node);
1740 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1741 ir_graph *irg = current_ir_graph;
1744 ia32_address_mode_t am;
1745 ia32_address_t *addr = &am.addr;
1746 memset(&am, 0, sizeof(am));
1748 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1751 build_address(&am, op);
1753 if(addr->base == NULL)
1754 addr->base = noreg_gp;
1755 if(addr->index == NULL)
1756 addr->index = noreg_gp;
1757 if(addr->mem == NULL)
1758 addr->mem = new_NoMem();
1760 dbgi = get_irn_dbg_info(node);
1761 block = be_transform_node(src_block);
1762 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1763 set_address(new_node, addr);
1764 set_ia32_op_type(new_node, ia32_AddrModeD);
1765 set_ia32_ls_mode(new_node, mode);
1766 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1771 static ir_node *try_create_dest_am(ir_node *node) {
1772 ir_node *val = get_Store_value(node);
1773 ir_node *mem = get_Store_mem(node);
1774 ir_node *ptr = get_Store_ptr(node);
1775 ir_mode *mode = get_irn_mode(val);
1780 /* handle only GP modes for now... */
1781 if(!mode_needs_gp_reg(mode))
1784 /* store must be the only user of the val node */
1785 if(get_irn_n_edges(val) > 1)
1788 switch(get_irn_opcode(val)) {
1790 op1 = get_Add_left(val);
1791 op2 = get_Add_right(val);
1792 if(is_Const_1(op2)) {
1793 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1794 new_rd_ia32_IncMem);
1796 } else if(is_Const_Minus_1(op2)) {
1797 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1798 new_rd_ia32_DecMem);
1801 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1802 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, 1);
1805 op1 = get_Sub_left(val);
1806 op2 = get_Sub_right(val);
1808 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
1811 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1812 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, 0);
1815 op1 = get_And_left(val);
1816 op2 = get_And_right(val);
1817 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1818 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, 1);
1821 op1 = get_Or_left(val);
1822 op2 = get_Or_right(val);
1823 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1824 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, 1);
1827 op1 = get_Eor_left(val);
1828 op2 = get_Eor_right(val);
1829 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1830 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, 1);
1833 op1 = get_Shl_left(val);
1834 op2 = get_Shl_right(val);
1835 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1836 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, 0);
1839 op1 = get_Shr_left(val);
1840 op2 = get_Shr_right(val);
1841 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1842 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, 0);
1845 op1 = get_Shrs_left(val);
1846 op2 = get_Shrs_right(val);
1847 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1848 new_rd_ia32_SarMem, new_rd_ia32_SarMem, 0);
1851 op1 = get_Rot_left(val);
1852 op2 = get_Rot_right(val);
1853 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1854 new_rd_ia32_RolMem, new_rd_ia32_RolMem, 0);
1856 /* TODO: match ROR patterns... */
1858 op1 = get_Minus_op(val);
1859 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1862 /* should be lowered already */
1863 assert(mode != mode_b);
1864 op1 = get_Not_op(val);
1865 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1875 * Transforms a Store.
1877 * @return the created ia32 Store node
1879 static ir_node *gen_Store(ir_node *node) {
1880 ir_node *block = be_transform_node(get_nodes_block(node));
1881 ir_node *ptr = get_Store_ptr(node);
1884 ir_node *val = get_Store_value(node);
1886 ir_node *mem = get_Store_mem(node);
1887 ir_node *new_mem = be_transform_node(mem);
1888 ir_graph *irg = current_ir_graph;
1889 dbg_info *dbgi = get_irn_dbg_info(node);
1890 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1891 ir_mode *mode = get_irn_mode(val);
1893 ia32_address_t addr;
1895 /* check for destination address mode */
1896 new_op = try_create_dest_am(node);
1900 /* construct store address */
1901 memset(&addr, 0, sizeof(addr));
1902 ia32_create_address_mode(&addr, ptr, 0);
1909 base = be_transform_node(base);
1915 index = be_transform_node(index);
1918 if (mode_is_float(mode)) {
1919 new_val = be_transform_node(val);
1920 if (USE_SSE2(env_cg)) {
1921 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
1924 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
1928 new_val = create_immediate_or_transform(val, 0);
1932 if (get_mode_size_bits(mode) == 8) {
1933 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
1936 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
1941 set_irn_pinned(new_op, get_irn_pinned(node));
1942 set_ia32_op_type(new_op, ia32_AddrModeD);
1943 set_ia32_ls_mode(new_op, mode);
1945 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1946 set_address(new_op, &addr);
1947 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1952 static ir_node *create_Switch(ir_node *node)
1954 ir_graph *irg = current_ir_graph;
1955 dbg_info *dbgi = get_irn_dbg_info(node);
1956 ir_node *block = be_transform_node(get_nodes_block(node));
1957 ir_node *sel = get_Cond_selector(node);
1958 ir_node *new_sel = be_transform_node(sel);
1960 int switch_min = INT_MAX;
1961 const ir_edge_t *edge;
1963 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1965 /* determine the smallest switch case value */
1966 foreach_out_edge(node, edge) {
1967 ir_node *proj = get_edge_src_irn(edge);
1968 int pn = get_Proj_proj(proj);
1973 if (switch_min != 0) {
1974 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1976 /* if smallest switch case is not 0 we need an additional sub */
1977 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1978 add_ia32_am_offs_int(new_sel, -switch_min);
1979 set_ia32_op_type(new_sel, ia32_AddrModeS);
1981 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1984 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1985 set_ia32_pncode(res, get_Cond_defaultProj(node));
1987 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1992 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
1994 ir_graph *irg = current_ir_graph;
2002 /* we have a Cmp as input */
2004 ir_node *pred = get_Proj_pred(node);
2006 flags = be_transform_node(pred);
2007 *pnc_out = get_Proj_proj(node);
2012 /* a mode_b value, we have to compare it against 0 */
2013 dbgi = get_irn_dbg_info(node);
2014 new_block = be_transform_node(get_nodes_block(node));
2015 new_op = be_transform_node(node);
2016 noreg = ia32_new_NoReg_gp(env_cg);
2017 nomem = new_NoMem();
2018 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
2019 new_op, new_op, 0, 0);
2020 *pnc_out = pn_Cmp_Lg;
2024 static ir_node *gen_Cond(ir_node *node) {
2025 ir_node *block = get_nodes_block(node);
2026 ir_node *new_block = be_transform_node(block);
2027 ir_graph *irg = current_ir_graph;
2028 dbg_info *dbgi = get_irn_dbg_info(node);
2029 ir_node *sel = get_Cond_selector(node);
2030 ir_mode *sel_mode = get_irn_mode(sel);
2032 ir_node *flags = NULL;
2035 if (sel_mode != mode_b) {
2036 return create_Switch(node);
2039 /* we get flags from a cmp */
2040 flags = get_flags_node(sel, &pnc);
2042 res = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2043 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2051 * Transforms a CopyB node.
2053 * @return The transformed node.
2055 static ir_node *gen_CopyB(ir_node *node) {
2056 ir_node *block = be_transform_node(get_nodes_block(node));
2057 ir_node *src = get_CopyB_src(node);
2058 ir_node *new_src = be_transform_node(src);
2059 ir_node *dst = get_CopyB_dst(node);
2060 ir_node *new_dst = be_transform_node(dst);
2061 ir_node *mem = get_CopyB_mem(node);
2062 ir_node *new_mem = be_transform_node(mem);
2063 ir_node *res = NULL;
2064 ir_graph *irg = current_ir_graph;
2065 dbg_info *dbgi = get_irn_dbg_info(node);
2066 int size = get_type_size_bytes(get_CopyB_type(node));
2069 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2070 /* then we need the size explicitly in ECX. */
2071 if (size >= 32 * 4) {
2072 rem = size & 0x3; /* size % 4 */
2075 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2077 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2079 set_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);
2081 add_irn_dep(res, get_irg_frame(irg));
2083 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2084 /* we misuse the pncode field for the copyb size */
2085 set_ia32_pncode(res, rem);
2087 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2088 set_ia32_pncode(res, size);
2091 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2096 static ir_node *gen_be_Copy(ir_node *node)
2098 ir_node *result = be_duplicate_node(node);
2099 ir_mode *mode = get_irn_mode(result);
2101 if (mode_needs_gp_reg(mode)) {
2102 set_irn_mode(result, mode_Iu);
2109 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2110 * to fold an and into a test node
2112 static int can_fold_test_and(ir_node *node)
2114 const ir_edge_t *edge;
2116 /** we can only have eq and lg projs */
2117 foreach_out_edge(node, edge) {
2118 ir_node *proj = get_edge_src_irn(edge);
2119 pn_Cmp pnc = get_Proj_proj(proj);
2120 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2127 static ir_node *try_create_Test(ir_node *node)
2129 ir_graph *irg = current_ir_graph;
2130 dbg_info *dbgi = get_irn_dbg_info(node);
2131 ir_node *block = get_nodes_block(node);
2132 ir_node *new_block = be_transform_node(block);
2133 ir_node *cmp_left = get_Cmp_left(node);
2134 ir_node *cmp_right = get_Cmp_right(node);
2139 ia32_address_mode_t am;
2140 ia32_address_t *addr = &am.addr;
2143 /* can we use a test instruction? */
2144 if(!is_Const_0(cmp_right))
2147 if(is_And(cmp_left) && can_fold_test_and(node)) {
2148 ir_node *and_left = get_And_left(cmp_left);
2149 ir_node *and_right = get_And_right(cmp_left);
2151 mode = get_irn_mode(and_left);
2155 mode = get_irn_mode(cmp_left);
2160 assert(get_mode_size_bits(mode) <= 32);
2162 match_arguments(&am, block, left, right, match_commutative |
2163 match_8_16_bit_am | match_am_and_immediates);
2165 cmp_unsigned = !mode_is_signed(mode);
2166 if(get_mode_size_bits(mode) == 8) {
2167 res = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2168 addr->index, addr->mem, am.new_op1,
2169 am.new_op2, am.flipped, cmp_unsigned);
2171 res = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, addr->index,
2172 addr->mem, am.new_op1, am.new_op2, am.flipped,
2175 set_am_attributes(res, &am);
2176 assert(mode != NULL);
2177 set_ia32_ls_mode(res, mode);
2179 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2181 res = fix_mem_proj(res, &am);
2185 static ir_node *create_Fucom(ir_node *node)
2187 ir_graph *irg = current_ir_graph;
2188 dbg_info *dbgi = get_irn_dbg_info(node);
2189 ir_node *block = get_nodes_block(node);
2190 ir_node *new_block = be_transform_node(block);
2191 ir_node *left = get_Cmp_left(node);
2192 ir_node *new_left = be_transform_node(left);
2193 ir_node *right = get_Cmp_right(node);
2194 ir_node *new_right = be_transform_node(right);
2197 res = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left, new_right,
2199 set_ia32_commutative(res);
2201 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2203 res = new_rd_ia32_Sahf(dbgi, irg, new_block, res);
2204 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2209 static ir_node *create_Ucomi(ir_node *node)
2211 ir_graph *irg = current_ir_graph;
2212 dbg_info *dbgi = get_irn_dbg_info(node);
2213 ir_node *block = get_nodes_block(node);
2214 ir_node *new_block = be_transform_node(block);
2215 ir_node *left = get_Cmp_left(node);
2216 ir_node *new_left = be_transform_node(left);
2217 ir_node *right = get_Cmp_right(node);
2218 ir_node *new_right = be_transform_node(right);
2219 ir_mode *mode = get_irn_mode(left);
2220 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2221 ir_node *nomem = new_NoMem();
2224 res = new_rd_ia32_Ucomi(dbgi, irg, new_block, noreg, noreg, nomem, new_left,
2226 set_ia32_commutative(res);
2227 set_ia32_ls_mode(res, mode);
2229 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2234 static ir_node *gen_Cmp(ir_node *node)
2236 ir_graph *irg = current_ir_graph;
2237 dbg_info *dbgi = get_irn_dbg_info(node);
2238 ir_node *block = get_nodes_block(node);
2239 ir_node *new_block = be_transform_node(block);
2240 ir_node *left = get_Cmp_left(node);
2241 ir_node *right = get_Cmp_right(node);
2242 ir_mode *cmp_mode = get_irn_mode(left);
2244 ia32_address_mode_t am;
2245 ia32_address_t *addr = &am.addr;
2248 if(mode_is_float(cmp_mode)) {
2249 if (USE_SSE2(env_cg)) {
2250 return create_Ucomi(node);
2252 return create_Fucom(node);
2256 assert(mode_needs_gp_reg(cmp_mode));
2258 /* we prefer the Test instruction where possible except cases where
2259 * we can use SourceAM */
2260 if(!use_source_address_mode(block, left, right) &&
2261 !use_source_address_mode(block, right, left)) {
2262 res = try_create_Test(node);
2267 match_arguments(&am, block, left, right,
2268 match_commutative | match_8_16_bit_am |
2269 match_am_and_immediates);
2271 cmp_unsigned = !mode_is_signed(get_irn_mode(left));
2272 if(get_mode_size_bits(cmp_mode) == 8) {
2273 res = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, addr->index,
2274 addr->mem, am.new_op1, am.new_op2,
2275 am.flipped, cmp_unsigned);
2277 res = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, addr->index,
2278 addr->mem, am.new_op1, am.new_op2, am.flipped,
2281 set_am_attributes(res, &am);
2282 assert(cmp_mode != NULL);
2283 set_ia32_ls_mode(res, cmp_mode);
2285 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2287 res = fix_mem_proj(res, &am);
2292 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2294 ir_graph *irg = current_ir_graph;
2295 dbg_info *dbgi = get_irn_dbg_info(node);
2296 ir_node *block = get_nodes_block(node);
2297 ir_node *new_block = be_transform_node(block);
2298 ir_node *val_true = get_Psi_val(node, 0);
2299 ir_node *new_val_true = be_transform_node(val_true);
2300 ir_node *val_false = get_Psi_default(node);
2301 ir_node *new_val_false = be_transform_node(val_false);
2302 ir_mode *mode = get_irn_mode(node);
2303 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2304 ir_node *nomem = new_NoMem();
2307 assert(mode_needs_gp_reg(mode));
2309 res = new_rd_ia32_CMov(dbgi, irg, new_block, noreg, noreg, nomem,
2310 new_val_false, new_val_true, new_flags, pnc);
2311 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2318 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2319 ir_node *flags, pn_Cmp pnc, ir_node *orig_node)
2321 ir_graph *irg = current_ir_graph;
2322 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2323 ir_node *nomem = new_NoMem();
2326 res = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc);
2327 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2328 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2329 nomem, res, mode_Bu);
2330 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2336 * Transforms a Psi node into CMov.
2338 * @return The transformed node.
2340 static ir_node *gen_Psi(ir_node *node)
2342 dbg_info *dbgi = get_irn_dbg_info(node);
2343 ir_node *block = get_nodes_block(node);
2344 ir_node *new_block = be_transform_node(block);
2345 ir_node *psi_true = get_Psi_val(node, 0);
2346 ir_node *psi_default = get_Psi_default(node);
2347 ir_node *cond = get_Psi_cond(node, 0);
2348 ir_node *flags = NULL;
2353 assert(get_Psi_n_conds(node) == 1);
2354 assert(get_irn_mode(cond) == mode_b);
2355 assert(mode_needs_gp_reg(get_irn_mode(node)));
2357 flags = get_flags_node(cond, &pnc);
2359 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2360 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2361 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2362 pnc = get_negated_pnc(pnc, cmp_mode);
2363 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2365 res = create_CMov(node, flags, pnc);
2372 * Create a conversion from x87 state register to general purpose.
2374 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2375 ir_node *block = be_transform_node(get_nodes_block(node));
2376 ir_node *op = get_Conv_op(node);
2377 ir_node *new_op = be_transform_node(op);
2378 ia32_code_gen_t *cg = env_cg;
2379 ir_graph *irg = current_ir_graph;
2380 dbg_info *dbgi = get_irn_dbg_info(node);
2381 ir_node *noreg = ia32_new_NoReg_gp(cg);
2382 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2383 ir_mode *mode = get_irn_mode(node);
2384 ir_node *fist, *load;
2387 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2388 new_NoMem(), new_op, trunc_mode);
2390 set_irn_pinned(fist, op_pin_state_floats);
2391 set_ia32_use_frame(fist);
2392 set_ia32_op_type(fist, ia32_AddrModeD);
2394 assert(get_mode_size_bits(mode) <= 32);
2395 /* exception we can only store signed 32 bit integers, so for unsigned
2396 we store a 64bit (signed) integer and load the lower bits */
2397 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2398 set_ia32_ls_mode(fist, mode_Ls);
2400 set_ia32_ls_mode(fist, mode_Is);
2402 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2405 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2407 set_irn_pinned(load, op_pin_state_floats);
2408 set_ia32_use_frame(load);
2409 set_ia32_op_type(load, ia32_AddrModeS);
2410 set_ia32_ls_mode(load, mode_Is);
2411 if(get_ia32_ls_mode(fist) == mode_Ls) {
2412 ia32_attr_t *attr = get_ia32_attr(load);
2413 attr->data.need_64bit_stackent = 1;
2415 ia32_attr_t *attr = get_ia32_attr(load);
2416 attr->data.need_32bit_stackent = 1;
2418 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2420 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2424 * Creates a x87 strict Conv by placing a Sore and a Load
2426 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2428 ir_node *block = get_nodes_block(node);
2429 ir_graph *irg = current_ir_graph;
2430 dbg_info *dbgi = get_irn_dbg_info(node);
2431 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2432 ir_node *nomem = new_NoMem();
2433 ir_node *frame = get_irg_frame(irg);
2434 ir_node *store, *load;
2437 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2439 set_ia32_use_frame(store);
2440 set_ia32_op_type(store, ia32_AddrModeD);
2441 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2443 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2445 set_ia32_use_frame(load);
2446 set_ia32_op_type(load, ia32_AddrModeS);
2447 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2449 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2454 * Create a conversion from general purpose to x87 register
2456 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2457 ir_node *block = be_transform_node(get_nodes_block(node));
2458 ir_node *op = get_Conv_op(node);
2459 ir_node *new_op = be_transform_node(op);
2460 ir_graph *irg = current_ir_graph;
2461 dbg_info *dbgi = get_irn_dbg_info(node);
2462 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2463 ir_node *nomem = new_NoMem();
2464 ir_mode *mode = get_irn_mode(op);
2465 ir_mode *store_mode;
2466 ir_node *fild, *store;
2470 /* first convert to 32 bit signed if necessary */
2471 src_bits = get_mode_size_bits(src_mode);
2472 if (src_bits == 8) {
2473 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2475 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2477 } else if (src_bits < 32) {
2478 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2480 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2484 assert(get_mode_size_bits(mode) == 32);
2487 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2490 set_ia32_use_frame(store);
2491 set_ia32_op_type(store, ia32_AddrModeD);
2492 set_ia32_ls_mode(store, mode_Iu);
2494 /* exception for 32bit unsigned, do a 64bit spill+load */
2495 if(!mode_is_signed(mode)) {
2498 ir_node *zero_const = create_Immediate_from_int(0);
2500 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2501 get_irg_frame(irg), noreg, nomem,
2504 set_ia32_use_frame(zero_store);
2505 set_ia32_op_type(zero_store, ia32_AddrModeD);
2506 add_ia32_am_offs_int(zero_store, 4);
2507 set_ia32_ls_mode(zero_store, mode_Iu);
2512 store = new_rd_Sync(dbgi, irg, block, 2, in);
2513 store_mode = mode_Ls;
2515 store_mode = mode_Is;
2519 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2521 set_ia32_use_frame(fild);
2522 set_ia32_op_type(fild, ia32_AddrModeS);
2523 set_ia32_ls_mode(fild, store_mode);
2525 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2531 * Crete a conversion from one integer mode into another one
2533 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2534 dbg_info *dbgi, ir_node *block, ir_node *op,
2537 ir_graph *irg = current_ir_graph;
2538 int src_bits = get_mode_size_bits(src_mode);
2539 int tgt_bits = get_mode_size_bits(tgt_mode);
2540 ir_node *new_block = be_transform_node(block);
2541 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2544 ir_mode *smaller_mode;
2546 ia32_address_mode_t am;
2547 ia32_address_t *addr = &am.addr;
2549 if (src_bits < tgt_bits) {
2550 smaller_mode = src_mode;
2551 smaller_bits = src_bits;
2553 smaller_mode = tgt_mode;
2554 smaller_bits = tgt_bits;
2557 memset(&am, 0, sizeof(am));
2558 if(use_source_address_mode(block, op, NULL)) {
2559 build_address(&am, op);
2561 am.op_type = ia32_AddrModeS;
2563 new_op = be_transform_node(op);
2564 am.op_type = ia32_Normal;
2566 if(addr->base == NULL)
2568 if(addr->index == NULL)
2569 addr->index = noreg;
2570 if(addr->mem == NULL)
2571 addr->mem = new_NoMem();
2573 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2574 if (smaller_bits == 8) {
2575 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2576 addr->index, addr->mem, new_op,
2579 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2580 addr->index, addr->mem, new_op,
2584 set_am_attributes(res, &am);
2585 set_ia32_ls_mode(res, smaller_mode);
2586 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2587 res = fix_mem_proj(res, &am);
2593 * Transforms a Conv node.
2595 * @return The created ia32 Conv node
2597 static ir_node *gen_Conv(ir_node *node) {
2598 ir_node *block = get_nodes_block(node);
2599 ir_node *new_block = be_transform_node(block);
2600 ir_node *op = get_Conv_op(node);
2601 ir_node *new_op = NULL;
2602 ir_graph *irg = current_ir_graph;
2603 dbg_info *dbgi = get_irn_dbg_info(node);
2604 ir_mode *src_mode = get_irn_mode(op);
2605 ir_mode *tgt_mode = get_irn_mode(node);
2606 int src_bits = get_mode_size_bits(src_mode);
2607 int tgt_bits = get_mode_size_bits(tgt_mode);
2608 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2609 ir_node *nomem = new_rd_NoMem(irg);
2610 ir_node *res = NULL;
2612 if (src_mode == mode_b) {
2613 assert(mode_is_int(tgt_mode));
2614 /* nothing to do, we already model bools as 0/1 ints */
2615 return be_transform_node(op);
2618 if (src_mode == tgt_mode) {
2619 if (get_Conv_strict(node)) {
2620 if (USE_SSE2(env_cg)) {
2621 /* when we are in SSE mode, we can kill all strict no-op conversion */
2622 return be_transform_node(op);
2625 /* this should be optimized already, but who knows... */
2626 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2627 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2628 return be_transform_node(op);
2632 if (mode_is_float(src_mode)) {
2633 new_op = be_transform_node(op);
2634 /* we convert from float ... */
2635 if (mode_is_float(tgt_mode)) {
2636 if(src_mode == mode_E && tgt_mode == mode_D
2637 && !get_Conv_strict(node)) {
2638 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2643 if (USE_SSE2(env_cg)) {
2644 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2645 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2647 set_ia32_ls_mode(res, tgt_mode);
2649 if(get_Conv_strict(node)) {
2650 res = gen_x87_strict_conv(tgt_mode, new_op);
2651 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2654 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2659 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2660 if (USE_SSE2(env_cg)) {
2661 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2663 set_ia32_ls_mode(res, src_mode);
2665 return gen_x87_fp_to_gp(node);
2669 /* we convert from int ... */
2670 if (mode_is_float(tgt_mode)) {
2672 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2673 if (USE_SSE2(env_cg)) {
2674 new_op = be_transform_node(op);
2675 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2677 set_ia32_ls_mode(res, tgt_mode);
2679 res = gen_x87_gp_to_fp(node, src_mode);
2680 if(get_Conv_strict(node)) {
2681 res = gen_x87_strict_conv(tgt_mode, res);
2682 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2683 ia32_get_old_node_name(env_cg, node));
2687 } else if(tgt_mode == mode_b) {
2688 /* mode_b lowering already took care that we only have 0/1 values */
2689 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2690 src_mode, tgt_mode));
2691 return be_transform_node(op);
2694 if (src_bits == tgt_bits) {
2695 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2696 src_mode, tgt_mode));
2697 return be_transform_node(op);
2700 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2708 static int check_immediate_constraint(long val, char immediate_constraint_type)
2710 switch (immediate_constraint_type) {
2714 return val >= 0 && val <= 32;
2716 return val >= 0 && val <= 63;
2718 return val >= -128 && val <= 127;
2720 return val == 0xff || val == 0xffff;
2722 return val >= 0 && val <= 3;
2724 return val >= 0 && val <= 255;
2726 return val >= 0 && val <= 127;
2730 panic("Invalid immediate constraint found");
2734 static ir_node *try_create_Immediate(ir_node *node,
2735 char immediate_constraint_type)
2738 tarval *offset = NULL;
2739 int offset_sign = 0;
2741 ir_entity *symconst_ent = NULL;
2742 int symconst_sign = 0;
2744 ir_node *cnst = NULL;
2745 ir_node *symconst = NULL;
2751 mode = get_irn_mode(node);
2752 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2756 if(is_Minus(node)) {
2758 node = get_Minus_op(node);
2761 if(is_Const(node)) {
2764 offset_sign = minus;
2765 } else if(is_SymConst(node)) {
2768 symconst_sign = minus;
2769 } else if(is_Add(node)) {
2770 ir_node *left = get_Add_left(node);
2771 ir_node *right = get_Add_right(node);
2772 if(is_Const(left) && is_SymConst(right)) {
2775 symconst_sign = minus;
2776 offset_sign = minus;
2777 } else if(is_SymConst(left) && is_Const(right)) {
2780 symconst_sign = minus;
2781 offset_sign = minus;
2783 } else if(is_Sub(node)) {
2784 ir_node *left = get_Sub_left(node);
2785 ir_node *right = get_Sub_right(node);
2786 if(is_Const(left) && is_SymConst(right)) {
2789 symconst_sign = !minus;
2790 offset_sign = minus;
2791 } else if(is_SymConst(left) && is_Const(right)) {
2794 symconst_sign = minus;
2795 offset_sign = !minus;
2802 offset = get_Const_tarval(cnst);
2803 if(tarval_is_long(offset)) {
2804 val = get_tarval_long(offset);
2806 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2811 if(!check_immediate_constraint(val, immediate_constraint_type))
2814 if(symconst != NULL) {
2815 if(immediate_constraint_type != 0) {
2816 /* we need full 32bits for symconsts */
2820 /* unfortunately the assembler/linker doesn't support -symconst */
2824 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2826 symconst_ent = get_SymConst_entity(symconst);
2828 if(cnst == NULL && symconst == NULL)
2831 if(offset_sign && offset != NULL) {
2832 offset = tarval_neg(offset);
2835 irg = current_ir_graph;
2836 dbgi = get_irn_dbg_info(node);
2837 block = get_irg_start_block(irg);
2838 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2839 symconst_sign, val);
2840 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2845 static ir_node *create_immediate_or_transform(ir_node *node,
2846 char immediate_constraint_type)
2848 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2849 if (new_node == NULL) {
2850 new_node = be_transform_node(node);
2855 typedef struct constraint_t constraint_t;
2856 struct constraint_t {
2859 const arch_register_req_t **out_reqs;
2861 const arch_register_req_t *req;
2862 unsigned immediate_possible;
2863 char immediate_type;
2866 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2868 int immediate_possible = 0;
2869 char immediate_type = 0;
2870 unsigned limited = 0;
2871 const arch_register_class_t *cls = NULL;
2872 ir_graph *irg = current_ir_graph;
2873 struct obstack *obst = get_irg_obstack(irg);
2874 arch_register_req_t *req;
2875 unsigned *limited_ptr;
2879 /* TODO: replace all the asserts with nice error messages */
2881 printf("Constraint: %s\n", c);
2891 assert(cls == NULL ||
2892 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2893 cls = &ia32_reg_classes[CLASS_ia32_gp];
2894 limited |= 1 << REG_EAX;
2897 assert(cls == NULL ||
2898 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2899 cls = &ia32_reg_classes[CLASS_ia32_gp];
2900 limited |= 1 << REG_EBX;
2903 assert(cls == NULL ||
2904 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2905 cls = &ia32_reg_classes[CLASS_ia32_gp];
2906 limited |= 1 << REG_ECX;
2909 assert(cls == NULL ||
2910 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2911 cls = &ia32_reg_classes[CLASS_ia32_gp];
2912 limited |= 1 << REG_EDX;
2915 assert(cls == NULL ||
2916 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2917 cls = &ia32_reg_classes[CLASS_ia32_gp];
2918 limited |= 1 << REG_EDI;
2921 assert(cls == NULL ||
2922 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2923 cls = &ia32_reg_classes[CLASS_ia32_gp];
2924 limited |= 1 << REG_ESI;
2927 case 'q': /* q means lower part of the regs only, this makes no
2928 * difference to Q for us (we only assigne whole registers) */
2929 assert(cls == NULL ||
2930 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2931 cls = &ia32_reg_classes[CLASS_ia32_gp];
2932 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2936 assert(cls == NULL ||
2937 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2938 cls = &ia32_reg_classes[CLASS_ia32_gp];
2939 limited |= 1 << REG_EAX | 1 << REG_EDX;
2942 assert(cls == NULL ||
2943 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2944 cls = &ia32_reg_classes[CLASS_ia32_gp];
2945 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2946 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2953 assert(cls == NULL);
2954 cls = &ia32_reg_classes[CLASS_ia32_gp];
2960 /* TODO: mark values so the x87 simulator knows about t and u */
2961 assert(cls == NULL);
2962 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2967 assert(cls == NULL);
2968 /* TODO: check that sse2 is supported */
2969 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2979 assert(!immediate_possible);
2980 immediate_possible = 1;
2981 immediate_type = *c;
2985 assert(!immediate_possible);
2986 immediate_possible = 1;
2990 assert(!immediate_possible && cls == NULL);
2991 immediate_possible = 1;
2992 cls = &ia32_reg_classes[CLASS_ia32_gp];
3005 assert(constraint->is_in && "can only specify same constraint "
3008 sscanf(c, "%d%n", &same_as, &p);
3015 case 'E': /* no float consts yet */
3016 case 'F': /* no float consts yet */
3017 case 's': /* makes no sense on x86 */
3018 case 'X': /* we can't support that in firm */
3022 case '<': /* no autodecrement on x86 */
3023 case '>': /* no autoincrement on x86 */
3024 case 'C': /* sse constant not supported yet */
3025 case 'G': /* 80387 constant not supported yet */
3026 case 'y': /* we don't support mmx registers yet */
3027 case 'Z': /* not available in 32 bit mode */
3028 case 'e': /* not available in 32 bit mode */
3029 assert(0 && "asm constraint not supported");
3032 assert(0 && "unknown asm constraint found");
3039 const arch_register_req_t *other_constr;
3041 assert(cls == NULL && "same as and register constraint not supported");
3042 assert(!immediate_possible && "same as and immediate constraint not "
3044 assert(same_as < constraint->n_outs && "wrong constraint number in "
3045 "same_as constraint");
3047 other_constr = constraint->out_reqs[same_as];
3049 req = obstack_alloc(obst, sizeof(req[0]));
3050 req->cls = other_constr->cls;
3051 req->type = arch_register_req_type_should_be_same;
3052 req->limited = NULL;
3053 req->other_same = pos;
3054 req->other_different = -1;
3056 /* switch constraints. This is because in firm we have same_as
3057 * constraints on the output constraints while in the gcc asm syntax
3058 * they are specified on the input constraints */
3059 constraint->req = other_constr;
3060 constraint->out_reqs[same_as] = req;
3061 constraint->immediate_possible = 0;
3065 if(immediate_possible && cls == NULL) {
3066 cls = &ia32_reg_classes[CLASS_ia32_gp];
3068 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3069 assert(cls != NULL);
3071 if(immediate_possible) {
3072 assert(constraint->is_in
3073 && "imeediates make no sense for output constraints");
3075 /* todo: check types (no float input on 'r' constrained in and such... */
3078 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3079 limited_ptr = (unsigned*) (req+1);
3081 req = obstack_alloc(obst, sizeof(req[0]));
3083 memset(req, 0, sizeof(req[0]));
3086 req->type = arch_register_req_type_limited;
3087 *limited_ptr = limited;
3088 req->limited = limited_ptr;
3090 req->type = arch_register_req_type_normal;
3094 constraint->req = req;
3095 constraint->immediate_possible = immediate_possible;
3096 constraint->immediate_type = immediate_type;
3099 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3106 panic("Clobbers not supported yet");
3110 * generates code for a ASM node
3112 static ir_node *gen_ASM(ir_node *node)
3115 ir_graph *irg = current_ir_graph;
3116 ir_node *block = be_transform_node(get_nodes_block(node));
3117 dbg_info *dbgi = get_irn_dbg_info(node);
3124 ia32_asm_attr_t *attr;
3125 const arch_register_req_t **out_reqs;
3126 const arch_register_req_t **in_reqs;
3127 struct obstack *obst;
3128 constraint_t parsed_constraint;
3130 /* transform inputs */
3131 arity = get_irn_arity(node);
3132 in = alloca(arity * sizeof(in[0]));
3133 memset(in, 0, arity * sizeof(in[0]));
3135 n_outs = get_ASM_n_output_constraints(node);
3136 n_clobbers = get_ASM_n_clobbers(node);
3137 out_arity = n_outs + n_clobbers;
3139 /* construct register constraints */
3140 obst = get_irg_obstack(irg);
3141 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
3142 parsed_constraint.out_reqs = out_reqs;
3143 parsed_constraint.n_outs = n_outs;
3144 parsed_constraint.is_in = 0;
3145 for(i = 0; i < out_arity; ++i) {
3149 const ir_asm_constraint *constraint;
3150 constraint = & get_ASM_output_constraints(node) [i];
3151 c = get_id_str(constraint->constraint);
3152 parse_asm_constraint(i, &parsed_constraint, c);
3154 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
3155 c = get_id_str(glob_id);
3156 parse_clobber(node, i, &parsed_constraint, c);
3158 out_reqs[i] = parsed_constraint.req;
3161 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
3162 parsed_constraint.is_in = 1;
3163 for(i = 0; i < arity; ++i) {
3164 const ir_asm_constraint *constraint;
3168 constraint = & get_ASM_input_constraints(node) [i];
3169 constr_id = constraint->constraint;
3170 c = get_id_str(constr_id);
3171 parse_asm_constraint(i, &parsed_constraint, c);
3172 in_reqs[i] = parsed_constraint.req;
3174 if(parsed_constraint.immediate_possible) {
3175 ir_node *pred = get_irn_n(node, i);
3176 char imm_type = parsed_constraint.immediate_type;
3177 ir_node *immediate = try_create_Immediate(pred, imm_type);
3179 if(immediate != NULL) {
3185 /* transform inputs */
3186 for(i = 0; i < arity; ++i) {
3188 ir_node *transformed;
3193 pred = get_irn_n(node, i);
3194 transformed = be_transform_node(pred);
3195 in[i] = transformed;
3198 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
3200 generic_attr = get_irn_generic_attr(res);
3201 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
3202 attr->asm_text = get_ASM_text(node);
3203 set_ia32_out_req_all(res, out_reqs);
3204 set_ia32_in_req_all(res, in_reqs);
3206 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3211 /********************************************
3214 * | |__ ___ _ __ ___ __| | ___ ___
3215 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3216 * | |_) | __/ | | | (_) | (_| | __/\__ \
3217 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3219 ********************************************/
3222 * Transforms a FrameAddr into an ia32 Add.
3224 static ir_node *gen_be_FrameAddr(ir_node *node) {
3225 ir_node *block = be_transform_node(get_nodes_block(node));
3226 ir_node *op = be_get_FrameAddr_frame(node);
3227 ir_node *new_op = be_transform_node(op);
3228 ir_graph *irg = current_ir_graph;
3229 dbg_info *dbgi = get_irn_dbg_info(node);
3230 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3233 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3234 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3235 set_ia32_use_frame(res);
3237 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3243 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3245 static ir_node *gen_be_Return(ir_node *node) {
3246 ir_graph *irg = current_ir_graph;
3247 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3248 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3249 ir_entity *ent = get_irg_entity(irg);
3250 ir_type *tp = get_entity_type(ent);
3255 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3256 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3259 int pn_ret_val, pn_ret_mem, arity, i;
3261 assert(ret_val != NULL);
3262 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3263 return be_duplicate_node(node);
3266 res_type = get_method_res_type(tp, 0);
3268 if (! is_Primitive_type(res_type)) {
3269 return be_duplicate_node(node);
3272 mode = get_type_mode(res_type);
3273 if (! mode_is_float(mode)) {
3274 return be_duplicate_node(node);
3277 assert(get_method_n_ress(tp) == 1);
3279 pn_ret_val = get_Proj_proj(ret_val);
3280 pn_ret_mem = get_Proj_proj(ret_mem);
3282 /* get the Barrier */
3283 barrier = get_Proj_pred(ret_val);
3285 /* get result input of the Barrier */
3286 ret_val = get_irn_n(barrier, pn_ret_val);
3287 new_ret_val = be_transform_node(ret_val);
3289 /* get memory input of the Barrier */
3290 ret_mem = get_irn_n(barrier, pn_ret_mem);
3291 new_ret_mem = be_transform_node(ret_mem);
3293 frame = get_irg_frame(irg);
3295 dbgi = get_irn_dbg_info(barrier);
3296 block = be_transform_node(get_nodes_block(barrier));
3298 noreg = ia32_new_NoReg_gp(env_cg);
3300 /* store xmm0 onto stack */
3301 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3302 new_ret_mem, new_ret_val);
3303 set_ia32_ls_mode(sse_store, mode);
3304 set_ia32_op_type(sse_store, ia32_AddrModeD);
3305 set_ia32_use_frame(sse_store);
3307 /* load into x87 register */
3308 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3309 set_ia32_op_type(fld, ia32_AddrModeS);
3310 set_ia32_use_frame(fld);
3312 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3313 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3315 /* create a new barrier */
3316 arity = get_irn_arity(barrier);
3317 in = alloca(arity * sizeof(in[0]));
3318 for (i = 0; i < arity; ++i) {
3321 if (i == pn_ret_val) {
3323 } else if (i == pn_ret_mem) {
3326 ir_node *in = get_irn_n(barrier, i);
3327 new_in = be_transform_node(in);
3332 new_barrier = new_ir_node(dbgi, irg, block,
3333 get_irn_op(barrier), get_irn_mode(barrier),
3335 copy_node_attr(barrier, new_barrier);
3336 be_duplicate_deps(barrier, new_barrier);
3337 be_set_transformed_node(barrier, new_barrier);
3338 mark_irn_visited(barrier);
3340 /* transform normally */
3341 return be_duplicate_node(node);
3345 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3347 static ir_node *gen_be_AddSP(ir_node *node) {
3348 ir_node *block = be_transform_node(get_nodes_block(node));
3349 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3351 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3352 ir_node *new_sp = be_transform_node(sp);
3353 ir_graph *irg = current_ir_graph;
3354 dbg_info *dbgi = get_irn_dbg_info(node);
3355 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3356 ir_node *nomem = new_NoMem();
3359 new_sz = create_immediate_or_transform(sz, 0);
3361 /* ia32 stack grows in reverse direction, make a SubSP */
3362 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
3364 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3370 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3372 static ir_node *gen_be_SubSP(ir_node *node) {
3373 ir_node *block = be_transform_node(get_nodes_block(node));
3374 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3376 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3377 ir_node *new_sp = be_transform_node(sp);
3378 ir_graph *irg = current_ir_graph;
3379 dbg_info *dbgi = get_irn_dbg_info(node);
3380 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3381 ir_node *nomem = new_NoMem();
3384 new_sz = create_immediate_or_transform(sz, 0);
3386 /* ia32 stack grows in reverse direction, make an AddSP */
3387 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
3389 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3395 * This function just sets the register for the Unknown node
3396 * as this is not done during register allocation because Unknown
3397 * is an "ignore" node.
3399 static ir_node *gen_Unknown(ir_node *node) {
3400 ir_mode *mode = get_irn_mode(node);
3402 if (mode_is_float(mode)) {
3403 if (USE_SSE2(env_cg)) {
3404 return ia32_new_Unknown_xmm(env_cg);
3406 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3407 ir_graph *irg = current_ir_graph;
3408 dbg_info *dbgi = get_irn_dbg_info(node);
3409 ir_node *block = get_irg_start_block(irg);
3410 return new_rd_ia32_vfldz(dbgi, irg, block);
3412 } else if (mode_needs_gp_reg(mode)) {
3413 return ia32_new_Unknown_gp(env_cg);
3415 assert(0 && "unsupported Unknown-Mode");
3422 * Change some phi modes
3424 static ir_node *gen_Phi(ir_node *node) {
3425 ir_node *block = be_transform_node(get_nodes_block(node));
3426 ir_graph *irg = current_ir_graph;
3427 dbg_info *dbgi = get_irn_dbg_info(node);
3428 ir_mode *mode = get_irn_mode(node);
3431 if(mode_needs_gp_reg(mode)) {
3432 /* we shouldn't have any 64bit stuff around anymore */
3433 assert(get_mode_size_bits(mode) <= 32);
3434 /* all integer operations are on 32bit registers now */
3436 } else if(mode_is_float(mode)) {
3437 if (USE_SSE2(env_cg)) {
3444 /* phi nodes allow loops, so we use the old arguments for now
3445 * and fix this later */
3446 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3447 get_irn_in(node) + 1);
3448 copy_node_attr(node, phi);
3449 be_duplicate_deps(node, phi);
3451 be_set_transformed_node(node, phi);
3452 be_enqueue_preds(node);
3460 static ir_node *gen_IJmp(ir_node *node) {
3461 /* TODO: support AM */
3462 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3466 /**********************************************************************
3469 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3470 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3471 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3472 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3474 **********************************************************************/
3476 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3478 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3481 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3482 ir_node *val, ir_node *mem);
3485 * Transforms a lowered Load into a "real" one.
3487 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3489 ir_node *block = be_transform_node(get_nodes_block(node));
3490 ir_node *ptr = get_irn_n(node, 0);
3491 ir_node *new_ptr = be_transform_node(ptr);
3492 ir_node *mem = get_irn_n(node, 1);
3493 ir_node *new_mem = be_transform_node(mem);
3494 ir_graph *irg = current_ir_graph;
3495 dbg_info *dbgi = get_irn_dbg_info(node);
3496 ir_mode *mode = get_ia32_ls_mode(node);
3497 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3500 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3502 set_ia32_op_type(new_op, ia32_AddrModeS);
3503 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3504 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3505 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3506 if (is_ia32_am_sc_sign(node))
3507 set_ia32_am_sc_sign(new_op);
3508 set_ia32_ls_mode(new_op, mode);
3509 if (is_ia32_use_frame(node)) {
3510 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3511 set_ia32_use_frame(new_op);
3514 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3520 * Transforms a lowered Store into a "real" one.
3522 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3524 ir_node *block = be_transform_node(get_nodes_block(node));
3525 ir_node *ptr = get_irn_n(node, 0);
3526 ir_node *new_ptr = be_transform_node(ptr);
3527 ir_node *val = get_irn_n(node, 1);
3528 ir_node *new_val = be_transform_node(val);
3529 ir_node *mem = get_irn_n(node, 2);
3530 ir_node *new_mem = be_transform_node(mem);
3531 ir_graph *irg = current_ir_graph;
3532 dbg_info *dbgi = get_irn_dbg_info(node);
3533 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3534 ir_mode *mode = get_ia32_ls_mode(node);
3538 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3540 am_offs = get_ia32_am_offs_int(node);
3541 add_ia32_am_offs_int(new_op, am_offs);
3543 set_ia32_op_type(new_op, ia32_AddrModeD);
3544 set_ia32_ls_mode(new_op, mode);
3545 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3546 set_ia32_use_frame(new_op);
3548 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3555 * Transforms an ia32_l_XXX into a "real" XXX node
3557 * @param node The node to transform
3558 * @return the created ia32 XXX node
3560 #define GEN_LOWERED_OP(op) \
3561 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3562 return gen_binop(node, get_binop_left(node), \
3563 get_binop_right(node), new_rd_ia32_##op,0); \
3566 #define GEN_LOWERED_x87_OP(op) \
3567 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3569 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3570 get_binop_right(node), new_rd_ia32_##op); \
3574 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3575 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3576 return gen_shift_binop(node, get_irn_n(node, 0), \
3577 get_irn_n(node, 1), new_rd_ia32_##op); \
3580 GEN_LOWERED_x87_OP(vfprem)
3581 GEN_LOWERED_x87_OP(vfmul)
3582 GEN_LOWERED_x87_OP(vfsub)
3583 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3584 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3585 GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
3586 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3588 static ir_node *gen_ia32_l_Add(ir_node *node) {
3589 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3590 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3591 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, 1);
3593 if(is_Proj(lowered)) {
3594 lowered = get_Proj_pred(lowered);
3596 assert(is_ia32_Add(lowered));
3597 set_irn_mode(lowered, mode_T);
3603 static ir_node *gen_ia32_l_Adc(ir_node *node) {
3604 ir_node *src_block = get_nodes_block(node);
3605 ir_node *block = be_transform_node(src_block);
3606 ir_node *op1 = get_irn_n(node, n_ia32_l_Adc_left);
3607 ir_node *op2 = get_irn_n(node, n_ia32_l_Adc_right);
3608 ir_node *flags = get_irn_n(node, n_ia32_l_Adc_eflags);
3609 ir_node *new_flags = be_transform_node(flags);
3610 ir_graph *irg = current_ir_graph;
3611 dbg_info *dbgi = get_irn_dbg_info(node);
3613 ia32_address_mode_t am;
3614 ia32_address_t *addr = &am.addr;
3616 match_arguments(&am, src_block, op1, op2, match_commutative);
3618 new_node = new_rd_ia32_Adc(dbgi, irg, block, addr->base, addr->index,
3619 addr->mem, am.new_op1, am.new_op2, new_flags);
3620 set_am_attributes(new_node, &am);
3621 /* we can't use source address mode anymore when using immediates */
3622 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3623 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3624 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3626 new_node = fix_mem_proj(new_node, &am);
3632 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3634 * @param node The node to transform
3635 * @return the created ia32 Neg node
3637 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3638 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3642 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3644 * @param node The node to transform
3645 * @return the created ia32 vfild node
3647 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3648 return gen_lowered_Load(node, new_rd_ia32_vfild);
3652 * Transforms an ia32_l_Load into a "real" ia32_Load node
3654 * @param node The node to transform
3655 * @return the created ia32 Load node
3657 static ir_node *gen_ia32_l_Load(ir_node *node) {
3658 return gen_lowered_Load(node, new_rd_ia32_Load);
3662 * Transforms an ia32_l_Store into a "real" ia32_Store node
3664 * @param node The node to transform
3665 * @return the created ia32 Store node
3667 static ir_node *gen_ia32_l_Store(ir_node *node) {
3668 return gen_lowered_Store(node, new_rd_ia32_Store);
3672 * Transforms a l_vfist into a "real" vfist node.
3674 * @param node The node to transform
3675 * @return the created ia32 vfist node
3677 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3678 ir_node *block = be_transform_node(get_nodes_block(node));
3679 ir_node *ptr = get_irn_n(node, 0);
3680 ir_node *new_ptr = be_transform_node(ptr);
3681 ir_node *val = get_irn_n(node, 1);
3682 ir_node *new_val = be_transform_node(val);
3683 ir_node *mem = get_irn_n(node, 2);
3684 ir_node *new_mem = be_transform_node(mem);
3685 ir_graph *irg = current_ir_graph;
3686 dbg_info *dbgi = get_irn_dbg_info(node);
3687 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3688 ir_mode *mode = get_ia32_ls_mode(node);
3689 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3693 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3694 new_val, trunc_mode);
3696 am_offs = get_ia32_am_offs_int(node);
3697 add_ia32_am_offs_int(new_op, am_offs);
3699 set_ia32_op_type(new_op, ia32_AddrModeD);
3700 set_ia32_ls_mode(new_op, mode);
3701 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3702 set_ia32_use_frame(new_op);
3704 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3710 * Transforms a l_vfdiv into a "real" vfdiv node.
3712 * @param env The transformation environment
3713 * @return the created ia32 vfdiv node
3715 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3716 ir_node *block = be_transform_node(get_nodes_block(node));
3717 ir_node *left = get_binop_left(node);
3718 ir_node *new_left = be_transform_node(left);
3719 ir_node *right = get_binop_right(node);
3720 ir_node *new_right = be_transform_node(right);
3721 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3722 ir_graph *irg = current_ir_graph;
3723 dbg_info *dbgi = get_irn_dbg_info(node);
3724 ir_node *fpcw = get_fpcw();
3727 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_NoMem(),
3728 new_left, new_right, fpcw);
3729 clear_ia32_commutative(vfdiv);
3731 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3737 * Transforms a l_MulS into a "real" MulS node.
3739 * @param env The transformation environment
3740 * @return the created ia32 Mul node
3742 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3743 ir_node *block = be_transform_node(get_nodes_block(node));
3744 ir_node *left = get_binop_left(node);
3745 ir_node *new_left = be_transform_node(left);
3746 ir_node *right = get_binop_right(node);
3747 ir_node *new_right = be_transform_node(right);
3748 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3749 ir_graph *irg = current_ir_graph;
3750 dbg_info *dbgi = get_irn_dbg_info(node);
3752 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3753 /* and then skip the result Proj, because all needed Projs are already there. */
3754 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(),
3755 new_left, new_right);
3756 clear_ia32_commutative(muls);
3758 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3764 * Transforms a l_IMulS into a "real" IMul1OPS node.
3766 * @param env The transformation environment
3767 * @return the created ia32 IMul1OP node
3769 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3770 ir_node *block = be_transform_node(get_nodes_block(node));
3771 ir_node *left = get_binop_left(node);
3772 ir_node *new_left = be_transform_node(left);
3773 ir_node *right = get_binop_right(node);
3774 ir_node *new_right = be_transform_node(right);
3775 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3776 ir_graph *irg = current_ir_graph;
3777 dbg_info *dbgi = get_irn_dbg_info(node);
3779 /* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */
3780 /* and then skip the result Proj, because all needed Projs are already there. */
3781 ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg,
3782 new_NoMem(), new_left, new_right);
3783 clear_ia32_commutative(muls);
3785 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3790 static ir_node *gen_ia32_Add64Bit(ir_node *node)
3792 ir_node *a_l = be_transform_node(get_irn_n(node, 0));
3793 ir_node *a_h = be_transform_node(get_irn_n(node, 1));
3794 ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0);
3795 ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0);
3796 ir_node *block = be_transform_node(get_nodes_block(node));
3797 dbg_info *dbgi = get_irn_dbg_info(node);
3798 ir_graph *irg = current_ir_graph;
3799 ir_node *new_op = new_rd_ia32_Add64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h);
3800 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3804 static ir_node *gen_ia32_Sub64Bit(ir_node *node)
3806 ir_node *a_l = be_transform_node(get_irn_n(node, 0));
3807 ir_node *a_h = be_transform_node(get_irn_n(node, 1));
3808 ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0);
3809 ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0);
3810 ir_node *block = be_transform_node(get_nodes_block(node));
3811 dbg_info *dbgi = get_irn_dbg_info(node);
3812 ir_graph *irg = current_ir_graph;
3813 ir_node *new_op = new_rd_ia32_Sub64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h);
3814 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3819 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3820 * op1 - target to be shifted
3821 * op2 - contains bits to be shifted into target
3823 * Only op3 can be an immediate.
3825 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3826 ir_node *op2, ir_node *count)
3828 ir_node *block = be_transform_node(get_nodes_block(node));
3829 ir_node *new_op = NULL;
3830 ir_graph *irg = current_ir_graph;
3831 dbg_info *dbgi = get_irn_dbg_info(node);
3832 ir_node *new_op1 = be_transform_node(op1);
3833 ir_node *new_op2 = be_transform_node(op2);
3834 ir_node *new_count = create_immediate_or_transform(count, 'I');
3836 /* TODO proper AM support */
3838 if (is_ia32_l_ShlD(node))
3839 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3841 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3843 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3848 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3849 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3850 get_irn_n(node, 1), get_irn_n(node, 2));
3853 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3854 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3855 get_irn_n(node, 1), get_irn_n(node, 2));
3859 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3861 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3862 ir_node *block = be_transform_node(get_nodes_block(node));
3863 ir_node *val = get_irn_n(node, 1);
3864 ir_node *new_val = be_transform_node(val);
3865 ia32_code_gen_t *cg = env_cg;
3866 ir_node *res = NULL;
3867 ir_graph *irg = current_ir_graph;
3869 ir_node *noreg, *new_ptr, *new_mem;
3876 mem = get_irn_n(node, 2);
3877 new_mem = be_transform_node(mem);
3878 ptr = get_irn_n(node, 0);
3879 new_ptr = be_transform_node(ptr);
3880 noreg = ia32_new_NoReg_gp(cg);
3881 dbgi = get_irn_dbg_info(node);
3883 /* Store x87 -> MEM */
3884 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
3885 get_ia32_ls_mode(node));
3886 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3887 set_ia32_use_frame(res);
3888 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3889 set_ia32_op_type(res, ia32_AddrModeD);
3891 /* Load MEM -> SSE */
3892 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
3893 get_ia32_ls_mode(node));
3894 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3895 set_ia32_use_frame(res);
3896 set_ia32_op_type(res, ia32_AddrModeS);
3897 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3903 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3905 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3906 ir_node *block = be_transform_node(get_nodes_block(node));
3907 ir_node *val = get_irn_n(node, 1);
3908 ir_node *new_val = be_transform_node(val);
3909 ia32_code_gen_t *cg = env_cg;
3910 ir_graph *irg = current_ir_graph;
3911 ir_node *res = NULL;
3912 ir_entity *fent = get_ia32_frame_ent(node);
3913 ir_mode *lsmode = get_ia32_ls_mode(node);
3915 ir_node *noreg, *new_ptr, *new_mem;
3919 if (! USE_SSE2(cg)) {
3920 /* SSE unit is not used -> skip this node. */
3924 ptr = get_irn_n(node, 0);
3925 new_ptr = be_transform_node(ptr);
3926 mem = get_irn_n(node, 2);
3927 new_mem = be_transform_node(mem);
3928 noreg = ia32_new_NoReg_gp(cg);
3929 dbgi = get_irn_dbg_info(node);
3931 /* Store SSE -> MEM */
3932 if (is_ia32_xLoad(skip_Proj(new_val))) {
3933 ir_node *ld = skip_Proj(new_val);
3935 /* we can vfld the value directly into the fpu */
3936 fent = get_ia32_frame_ent(ld);
3937 ptr = get_irn_n(ld, 0);
3938 offs = get_ia32_am_offs_int(ld);
3940 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
3942 set_ia32_frame_ent(res, fent);
3943 set_ia32_use_frame(res);
3944 set_ia32_ls_mode(res, lsmode);
3945 set_ia32_op_type(res, ia32_AddrModeD);
3949 /* Load MEM -> x87 */
3950 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3951 set_ia32_frame_ent(res, fent);
3952 set_ia32_use_frame(res);
3953 add_ia32_am_offs_int(res, offs);
3954 set_ia32_op_type(res, ia32_AddrModeS);
3955 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3960 /*********************************************************
3963 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3964 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3965 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3966 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3968 *********************************************************/
3971 * the BAD transformer.
3973 static ir_node *bad_transform(ir_node *node) {
3974 panic("No transform function for %+F available.\n", node);
3979 * Transform the Projs of an AddSP.
3981 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3982 ir_node *block = be_transform_node(get_nodes_block(node));
3983 ir_node *pred = get_Proj_pred(node);
3984 ir_node *new_pred = be_transform_node(pred);
3985 ir_graph *irg = current_ir_graph;
3986 dbg_info *dbgi = get_irn_dbg_info(node);
3987 long proj = get_Proj_proj(node);
3989 if (proj == pn_be_AddSP_sp) {
3990 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3991 pn_ia32_SubSP_stack);
3992 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3994 } else if(proj == pn_be_AddSP_res) {
3995 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3996 pn_ia32_SubSP_addr);
3997 } else if (proj == pn_be_AddSP_M) {
3998 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4002 return new_rd_Unknown(irg, get_irn_mode(node));
4006 * Transform the Projs of a SubSP.
4008 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4009 ir_node *block = be_transform_node(get_nodes_block(node));
4010 ir_node *pred = get_Proj_pred(node);
4011 ir_node *new_pred = be_transform_node(pred);
4012 ir_graph *irg = current_ir_graph;
4013 dbg_info *dbgi = get_irn_dbg_info(node);
4014 long proj = get_Proj_proj(node);
4016 if (proj == pn_be_SubSP_sp) {
4017 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4018 pn_ia32_AddSP_stack);
4019 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4021 } else if (proj == pn_be_SubSP_M) {
4022 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4026 return new_rd_Unknown(irg, get_irn_mode(node));
4030 * Transform and renumber the Projs from a Load.
4032 static ir_node *gen_Proj_Load(ir_node *node) {
4034 ir_node *block = be_transform_node(get_nodes_block(node));
4035 ir_node *pred = get_Proj_pred(node);
4036 ir_graph *irg = current_ir_graph;
4037 dbg_info *dbgi = get_irn_dbg_info(node);
4038 long proj = get_Proj_proj(node);
4041 /* loads might be part of source address mode matches, so we don't
4042 transform the ProjMs yet (with the exception of loads whose result is
4045 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4048 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4050 /* this is needed, because sometimes we have loops that are only
4051 reachable through the ProjM */
4052 be_enqueue_preds(node);
4053 /* do it in 2 steps, to silence firm verifier */
4054 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4055 set_Proj_proj(res, pn_ia32_Load_M);
4059 /* renumber the proj */
4060 new_pred = be_transform_node(pred);
4061 if (is_ia32_Load(new_pred)) {
4062 if (proj == pn_Load_res) {
4063 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4065 } else if (proj == pn_Load_M) {
4066 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4069 } else if(is_ia32_Conv_I2I(new_pred)) {
4070 set_irn_mode(new_pred, mode_T);
4071 if (proj == pn_Load_res) {
4072 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4073 } else if (proj == pn_Load_M) {
4074 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4076 } else if (is_ia32_xLoad(new_pred)) {
4077 if (proj == pn_Load_res) {
4078 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4080 } else if (proj == pn_Load_M) {
4081 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4084 } else if (is_ia32_vfld(new_pred)) {
4085 if (proj == pn_Load_res) {
4086 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4088 } else if (proj == pn_Load_M) {
4089 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4093 /* can happen for ProJMs when source address mode happened for the
4096 /* however it should not be the result proj, as that would mean the
4097 load had multiple users and should not have been used for
4099 if(proj != pn_Load_M) {
4100 panic("internal error: transformed node not a Load");
4102 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4106 return new_rd_Unknown(irg, get_irn_mode(node));
4110 * Transform and renumber the Projs from a DivMod like instruction.
4112 static ir_node *gen_Proj_DivMod(ir_node *node) {
4113 ir_node *block = be_transform_node(get_nodes_block(node));
4114 ir_node *pred = get_Proj_pred(node);
4115 ir_node *new_pred = be_transform_node(pred);
4116 ir_graph *irg = current_ir_graph;
4117 dbg_info *dbgi = get_irn_dbg_info(node);
4118 ir_mode *mode = get_irn_mode(node);
4119 long proj = get_Proj_proj(node);
4121 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4123 switch (get_irn_opcode(pred)) {
4127 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4129 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4137 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4139 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4147 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4148 case pn_DivMod_res_div:
4149 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4150 case pn_DivMod_res_mod:
4151 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4161 return new_rd_Unknown(irg, mode);
4165 * Transform and renumber the Projs from a CopyB.
4167 static ir_node *gen_Proj_CopyB(ir_node *node) {
4168 ir_node *block = be_transform_node(get_nodes_block(node));
4169 ir_node *pred = get_Proj_pred(node);
4170 ir_node *new_pred = be_transform_node(pred);
4171 ir_graph *irg = current_ir_graph;
4172 dbg_info *dbgi = get_irn_dbg_info(node);
4173 ir_mode *mode = get_irn_mode(node);
4174 long proj = get_Proj_proj(node);
4177 case pn_CopyB_M_regular:
4178 if (is_ia32_CopyB_i(new_pred)) {
4179 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4180 } else if (is_ia32_CopyB(new_pred)) {
4181 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4189 return new_rd_Unknown(irg, mode);
4193 * Transform and renumber the Projs from a vfdiv.
4195 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
4196 ir_node *block = be_transform_node(get_nodes_block(node));
4197 ir_node *pred = get_Proj_pred(node);
4198 ir_node *new_pred = be_transform_node(pred);
4199 ir_graph *irg = current_ir_graph;
4200 dbg_info *dbgi = get_irn_dbg_info(node);
4201 ir_mode *mode = get_irn_mode(node);
4202 long proj = get_Proj_proj(node);
4205 case pn_ia32_l_vfdiv_M:
4206 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4207 case pn_ia32_l_vfdiv_res:
4208 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4213 return new_rd_Unknown(irg, mode);
4217 * Transform and renumber the Projs from a Quot.
4219 static ir_node *gen_Proj_Quot(ir_node *node) {
4220 ir_node *block = be_transform_node(get_nodes_block(node));
4221 ir_node *pred = get_Proj_pred(node);
4222 ir_node *new_pred = be_transform_node(pred);
4223 ir_graph *irg = current_ir_graph;
4224 dbg_info *dbgi = get_irn_dbg_info(node);
4225 ir_mode *mode = get_irn_mode(node);
4226 long proj = get_Proj_proj(node);
4230 if (is_ia32_xDiv(new_pred)) {
4231 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4232 } else if (is_ia32_vfdiv(new_pred)) {
4233 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4237 if (is_ia32_xDiv(new_pred)) {
4238 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4239 } else if (is_ia32_vfdiv(new_pred)) {
4240 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4248 return new_rd_Unknown(irg, mode);
4252 * Transform the Thread Local Storage Proj.
4254 static ir_node *gen_Proj_tls(ir_node *node) {
4255 ir_node *block = be_transform_node(get_nodes_block(node));
4256 ir_graph *irg = current_ir_graph;
4257 dbg_info *dbgi = NULL;
4258 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4263 static ir_node *gen_be_Call(ir_node *node) {
4264 ir_node *res = be_duplicate_node(node);
4265 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4270 static ir_node *gen_be_IncSP(ir_node *node) {
4271 ir_node *res = be_duplicate_node(node);
4272 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4278 * Transform the Projs from a be_Call.
4280 static ir_node *gen_Proj_be_Call(ir_node *node) {
4281 ir_node *block = be_transform_node(get_nodes_block(node));
4282 ir_node *call = get_Proj_pred(node);
4283 ir_node *new_call = be_transform_node(call);
4284 ir_graph *irg = current_ir_graph;
4285 dbg_info *dbgi = get_irn_dbg_info(node);
4286 ir_type *method_type = be_Call_get_type(call);
4287 int n_res = get_method_n_ress(method_type);
4288 long proj = get_Proj_proj(node);
4289 ir_mode *mode = get_irn_mode(node);
4291 const arch_register_class_t *cls;
4293 /* The following is kinda tricky: If we're using SSE, then we have to
4294 * move the result value of the call in floating point registers to an
4295 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4296 * after the call, we have to make sure to correctly make the
4297 * MemProj and the result Proj use these 2 nodes
4299 if (proj == pn_be_Call_M_regular) {
4300 // get new node for result, are we doing the sse load/store hack?
4301 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4302 ir_node *call_res_new;
4303 ir_node *call_res_pred = NULL;
4305 if (call_res != NULL) {
4306 call_res_new = be_transform_node(call_res);
4307 call_res_pred = get_Proj_pred(call_res_new);
4310 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4311 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4312 pn_be_Call_M_regular);
4314 assert(is_ia32_xLoad(call_res_pred));
4315 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4319 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4320 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4321 && USE_SSE2(env_cg)) {
4323 ir_node *frame = get_irg_frame(irg);
4324 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4326 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4329 /* in case there is no memory output: create one to serialize the copy
4331 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4332 pn_be_Call_M_regular);
4333 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4334 pn_be_Call_first_res);
4336 /* store st(0) onto stack */
4337 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4339 set_ia32_op_type(fstp, ia32_AddrModeD);
4340 set_ia32_use_frame(fstp);
4342 /* load into SSE register */
4343 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4345 set_ia32_op_type(sse_load, ia32_AddrModeS);
4346 set_ia32_use_frame(sse_load);
4348 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4354 /* transform call modes */
4355 if (mode_is_data(mode)) {
4356 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4360 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4364 * Transform the Projs from a Cmp.
4366 static ir_node *gen_Proj_Cmp(ir_node *node)
4368 /* normally Cmps are processed when looking at Cond nodes, but this case
4369 * can happen in complicated Psi conditions */
4370 dbg_info *dbgi = get_irn_dbg_info(node);
4371 ir_node *block = get_nodes_block(node);
4372 ir_node *new_block = be_transform_node(block);
4373 ir_node *cmp = get_Proj_pred(node);
4374 ir_node *new_cmp = be_transform_node(cmp);
4375 long pnc = get_Proj_proj(node);
4378 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node);
4384 * Transform and potentially renumber Proj nodes.
4386 static ir_node *gen_Proj(ir_node *node) {
4387 ir_graph *irg = current_ir_graph;
4388 dbg_info *dbgi = get_irn_dbg_info(node);
4389 ir_node *pred = get_Proj_pred(node);
4390 long proj = get_Proj_proj(node);
4392 if (is_Store(pred)) {
4393 if (proj == pn_Store_M) {
4394 return be_transform_node(pred);
4397 return new_r_Bad(irg);
4399 } else if (is_Load(pred)) {
4400 return gen_Proj_Load(node);
4401 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4402 return gen_Proj_DivMod(node);
4403 } else if (is_CopyB(pred)) {
4404 return gen_Proj_CopyB(node);
4405 } else if (is_Quot(pred)) {
4406 return gen_Proj_Quot(node);
4407 } else if (is_ia32_l_vfdiv(pred)) {
4408 return gen_Proj_l_vfdiv(node);
4409 } else if (be_is_SubSP(pred)) {
4410 return gen_Proj_be_SubSP(node);
4411 } else if (be_is_AddSP(pred)) {
4412 return gen_Proj_be_AddSP(node);
4413 } else if (be_is_Call(pred)) {
4414 return gen_Proj_be_Call(node);
4415 } else if (is_Cmp(pred)) {
4416 return gen_Proj_Cmp(node);
4417 } else if (get_irn_op(pred) == op_Start) {
4418 if (proj == pn_Start_X_initial_exec) {
4419 ir_node *block = get_nodes_block(pred);
4422 /* we exchange the ProjX with a jump */
4423 block = be_transform_node(block);
4424 jump = new_rd_Jmp(dbgi, irg, block);
4427 if (node == be_get_old_anchor(anchor_tls)) {
4428 return gen_Proj_tls(node);
4431 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4435 ir_node *new_pred = be_transform_node(pred);
4436 ir_node *block = be_transform_node(get_nodes_block(node));
4437 ir_mode *mode = get_irn_mode(node);
4438 if (mode_needs_gp_reg(mode)) {
4439 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4440 get_Proj_proj(node));
4441 #ifdef DEBUG_libfirm
4442 new_proj->node_nr = node->node_nr;
4448 return be_duplicate_node(node);
4452 * Enters all transform functions into the generic pointer
4454 static void register_transformers(void)
4458 /* first clear the generic function pointer for all ops */
4459 clear_irp_opcodes_generic_func();
4461 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4462 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4500 /* transform ops from intrinsic lowering */
4522 GEN(ia32_l_X87toSSE);
4523 GEN(ia32_l_SSEtoX87);
4529 /* we should never see these nodes */
4544 /* handle generic backend nodes */
4553 op_Mulh = get_op_Mulh();
4562 * Pre-transform all unknown and noreg nodes.
4564 static void ia32_pretransform_node(void *arch_cg) {
4565 ia32_code_gen_t *cg = arch_cg;
4567 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4568 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4569 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4570 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4571 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4572 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4577 * Walker, checks if all ia32 nodes producing more than one result have
4578 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4580 static void add_missing_keep_walker(ir_node *node, void *data)
4583 unsigned found_projs = 0;
4584 const ir_edge_t *edge;
4585 ir_mode *mode = get_irn_mode(node);
4590 if(!is_ia32_irn(node))
4593 n_outs = get_ia32_n_res(node);
4596 if(is_ia32_SwitchJmp(node))
4599 assert(n_outs < (int) sizeof(unsigned) * 8);
4600 foreach_out_edge(node, edge) {
4601 ir_node *proj = get_edge_src_irn(edge);
4602 int pn = get_Proj_proj(proj);
4604 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4605 found_projs |= 1 << pn;
4609 /* are keeps missing? */
4611 for(i = 0; i < n_outs; ++i) {
4614 const arch_register_req_t *req;
4615 const arch_register_class_t *class;
4617 if(found_projs & (1 << i)) {
4621 req = get_ia32_out_req(node, i);
4626 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4630 block = get_nodes_block(node);
4631 in[0] = new_r_Proj(current_ir_graph, block, node,
4632 arch_register_class_mode(class), i);
4633 if(last_keep != NULL) {
4634 be_Keep_add_node(last_keep, class, in[0]);
4636 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4637 if(sched_is_scheduled(node)) {
4638 sched_add_after(node, last_keep);
4645 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4648 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4650 ir_graph *irg = be_get_birg_irg(cg->birg);
4651 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4654 /* do the transformation */
4655 void ia32_transform_graph(ia32_code_gen_t *cg) {
4656 ir_graph *irg = cg->irg;
4658 register_transformers();
4660 initial_fpcw = NULL;
4662 heights = heights_new(irg);
4663 calculate_non_address_mode_nodes(irg);
4665 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4667 free_non_address_mode_nodes();
4668 heights_free(heights);
4672 void ia32_init_transform(void)
4674 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");