2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
98 static transform_config_t transform_config;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
108 ir_node *op1, ir_node *op2, ir_node *flags);
110 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *op1, ir_node *op2);
113 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
118 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
120 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
122 ir_node *op1, ir_node *op2, ir_node *fpcw);
124 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
125 ir_node *block, ir_node *op);
127 /****************************************************************************************************
129 * | | | | / _| | | (_)
130 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
131 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
132 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
133 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
135 ****************************************************************************************************/
137 static ir_node *try_create_Immediate(ir_node *node,
138 char immediate_constraint_type);
140 static ir_node *create_immediate_or_transform(ir_node *node,
141 char immediate_constraint_type);
143 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
144 dbg_info *dbgi, ir_node *block,
145 ir_node *op, ir_node *orig_node);
148 * Return true if a mode can be stored in the GP register set
150 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
151 if(mode == mode_fpcw)
153 if(get_mode_size_bits(mode) > 32)
155 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
159 * creates a unique ident by adding a number to a tag
161 * @param tag the tag string, must contain a %d if a number
164 static ident *unique_id(const char *tag)
166 static unsigned id = 0;
169 snprintf(str, sizeof(str), tag, ++id);
170 return new_id_from_str(str);
174 * Get a primitive type for a mode.
176 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
178 pmap_entry *e = pmap_find(types, mode);
183 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
184 res = new_type_primitive(new_id_from_str(buf), mode);
185 set_type_alignment_bytes(res, 16);
186 pmap_insert(types, mode, res);
194 * Get an atomic entity that is initialized with a tarval
196 static ir_entity *create_float_const_entity(ir_node *cnst)
198 ia32_isa_t *isa = env_cg->isa;
199 tarval *tv = get_Const_tarval(cnst);
200 pmap_entry *e = pmap_find(isa->tv_ent, tv);
205 ir_mode *mode = get_irn_mode(cnst);
206 ir_type *tp = get_Const_type(cnst);
207 if (tp == firm_unknown_type)
208 tp = get_prim_type(isa->types, mode);
210 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
212 set_entity_ld_ident(res, get_entity_ident(res));
213 set_entity_visibility(res, visibility_local);
214 set_entity_variability(res, variability_constant);
215 set_entity_allocation(res, allocation_static);
217 /* we create a new entity here: It's initialization must resist on the
219 rem = current_ir_graph;
220 current_ir_graph = get_const_code_irg();
221 set_atomic_ent_value(res, new_Const_type(tv, tp));
222 current_ir_graph = rem;
224 pmap_insert(isa->tv_ent, tv, res);
232 static int is_Const_0(ir_node *node) {
233 return is_Const(node) && is_Const_null(node);
236 static int is_Const_1(ir_node *node) {
237 return is_Const(node) && is_Const_one(node);
240 static int is_Const_Minus_1(ir_node *node) {
241 return is_Const(node) && is_Const_all_one(node);
245 * returns true if constant can be created with a simple float command
247 static int is_simple_x87_Const(ir_node *node)
249 tarval *tv = get_Const_tarval(node);
251 if(tarval_is_null(tv) || tarval_is_one(tv))
254 /* TODO: match all the other float constants */
259 * Transforms a Const.
261 static ir_node *gen_Const(ir_node *node) {
262 ir_graph *irg = current_ir_graph;
263 ir_node *old_block = get_nodes_block(node);
264 ir_node *block = be_transform_node(old_block);
265 dbg_info *dbgi = get_irn_dbg_info(node);
266 ir_mode *mode = get_irn_mode(node);
268 if (mode_is_float(mode)) {
270 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
271 ir_node *nomem = new_NoMem();
275 if (USE_SSE2(env_cg)) {
276 if (is_Const_null(node)) {
277 load = new_rd_ia32_xZero(dbgi, irg, block);
278 set_ia32_ls_mode(load, mode);
281 floatent = create_float_const_entity(node);
283 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
285 set_ia32_op_type(load, ia32_AddrModeS);
286 set_ia32_am_sc(load, floatent);
287 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
288 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
291 if (is_Const_null(node)) {
292 load = new_rd_ia32_vfldz(dbgi, irg, block);
294 } else if (is_Const_one(node)) {
295 load = new_rd_ia32_vfld1(dbgi, irg, block);
298 floatent = create_float_const_entity(node);
300 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
301 set_ia32_op_type(load, ia32_AddrModeS);
302 set_ia32_am_sc(load, floatent);
303 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
304 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
306 set_ia32_ls_mode(load, mode);
309 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
311 /* Const Nodes before the initial IncSP are a bad idea, because
312 * they could be spilled and we have no SP ready at that point yet.
313 * So add a dependency to the initial frame pointer calculation to
314 * avoid that situation.
316 if (get_irg_start_block(irg) == block) {
317 add_irn_dep(load, get_irg_frame(irg));
320 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
324 tarval *tv = get_Const_tarval(node);
327 tv = tarval_convert_to(tv, mode_Iu);
329 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
331 panic("couldn't convert constant tarval (%+F)", node);
333 val = get_tarval_long(tv);
335 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
339 if (get_irg_start_block(irg) == block) {
340 add_irn_dep(cnst, get_irg_frame(irg));
348 * Transforms a SymConst.
350 static ir_node *gen_SymConst(ir_node *node) {
351 ir_graph *irg = current_ir_graph;
352 ir_node *old_block = get_nodes_block(node);
353 ir_node *block = be_transform_node(old_block);
354 dbg_info *dbgi = get_irn_dbg_info(node);
355 ir_mode *mode = get_irn_mode(node);
358 if (mode_is_float(mode)) {
359 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
360 ir_node *nomem = new_NoMem();
362 if (USE_SSE2(env_cg))
363 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
365 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
366 set_ia32_am_sc(cnst, get_SymConst_entity(node));
367 set_ia32_use_frame(cnst);
371 if(get_SymConst_kind(node) != symconst_addr_ent) {
372 panic("backend only support symconst_addr_ent (at %+F)", node);
374 entity = get_SymConst_entity(node);
375 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
378 /* Const Nodes before the initial IncSP are a bad idea, because
379 * they could be spilled and we have no SP ready at that point yet
381 if (get_irg_start_block(irg) == block) {
382 add_irn_dep(cnst, get_irg_frame(irg));
385 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
390 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
391 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
392 static const struct {
394 const char *ent_name;
395 const char *cnst_str;
398 } names [ia32_known_const_max] = {
399 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
400 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
401 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
402 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
403 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
405 static ir_entity *ent_cache[ia32_known_const_max];
407 const char *tp_name, *ent_name, *cnst_str;
415 ent_name = names[kct].ent_name;
416 if (! ent_cache[kct]) {
417 tp_name = names[kct].tp_name;
418 cnst_str = names[kct].cnst_str;
420 switch (names[kct].mode) {
421 case 0: mode = mode_Iu; break;
422 case 1: mode = mode_Lu; break;
423 default: mode = mode_F; break;
425 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
426 tp = new_type_primitive(new_id_from_str(tp_name), mode);
427 /* set the specified alignment */
428 set_type_alignment_bytes(tp, names[kct].align);
430 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
432 set_entity_ld_ident(ent, get_entity_ident(ent));
433 set_entity_visibility(ent, visibility_local);
434 set_entity_variability(ent, variability_constant);
435 set_entity_allocation(ent, allocation_static);
437 /* we create a new entity here: It's initialization must resist on the
439 rem = current_ir_graph;
440 current_ir_graph = get_const_code_irg();
441 cnst = new_Const(mode, tv);
442 current_ir_graph = rem;
444 set_atomic_ent_value(ent, cnst);
446 /* cache the entry */
447 ent_cache[kct] = ent;
450 return ent_cache[kct];
455 * Prints the old node name on cg obst and returns a pointer to it.
457 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
458 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
460 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
461 obstack_1grow(isa->name_obst, 0);
462 return obstack_finish(isa->name_obst);
466 int ia32_use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
468 ir_mode *mode = get_irn_mode(node);
472 /* float constants are always available */
473 if(is_Const(node) && mode_is_float(mode)) {
474 if(!is_simple_x87_Const(node))
476 if(get_irn_n_edges(node) > 1)
483 load = get_Proj_pred(node);
484 pn = get_Proj_proj(node);
485 if(!is_Load(load) || pn != pn_Load_res)
487 if(get_nodes_block(load) != block)
489 /* we only use address mode if we're the only user of the load */
490 if(get_irn_n_edges(node) > 1)
492 /* in some edge cases with address mode we might reach the load normally
493 * and through some AM sequence, if it is already materialized then we
494 * can't create an AM node from it */
495 if(be_is_transformed(node))
498 /* don't do AM if other node inputs depend on the load (via mem-proj) */
499 if(other != NULL && get_nodes_block(other) == block
500 && heights_reachable_in_block(heights, other, load))
506 typedef struct ia32_address_mode_t ia32_address_mode_t;
507 struct ia32_address_mode_t {
511 ia32_op_type_t op_type;
515 unsigned commutative:1;
516 unsigned ins_permuted:1;
519 static void build_address(ia32_address_mode_t *am, ir_node *node)
521 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
522 ia32_address_t *addr = &am->addr;
531 ir_entity *entity = create_float_const_entity(node);
532 addr->base = noreg_gp;
533 addr->index = noreg_gp;
534 addr->mem = new_NoMem();
535 addr->symconst_ent = entity;
537 am->ls_mode = get_irn_mode(node);
538 am->pinned = op_pin_state_floats;
542 load = get_Proj_pred(node);
543 ptr = get_Load_ptr(load);
544 mem = get_Load_mem(load);
545 new_mem = be_transform_node(mem);
546 am->pinned = get_irn_pinned(load);
547 am->ls_mode = get_Load_mode(load);
548 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
550 /* construct load address */
551 ia32_create_address_mode(addr, ptr, /*force=*/0);
558 base = be_transform_node(base);
564 index = be_transform_node(index);
572 static void set_address(ir_node *node, const ia32_address_t *addr)
574 set_ia32_am_scale(node, addr->scale);
575 set_ia32_am_sc(node, addr->symconst_ent);
576 set_ia32_am_offs_int(node, addr->offset);
577 if(addr->symconst_sign)
578 set_ia32_am_sc_sign(node);
580 set_ia32_use_frame(node);
581 set_ia32_frame_ent(node, addr->frame_entity);
584 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
586 set_address(node, &am->addr);
588 set_ia32_op_type(node, am->op_type);
589 set_ia32_ls_mode(node, am->ls_mode);
590 if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) {
591 set_irn_pinned(node, am->pinned);
594 set_ia32_commutative(node);
598 * Check, if a given node is a Down-Conv, ie. a integer Conv
599 * from a mode with a mode with more bits to a mode with lesser bits.
600 * Moreover, we return only true if the node has not more than 1 user.
602 * @param node the node
603 * @return non-zero if node is a Down-Conv
605 static int is_downconv(const ir_node *node)
613 /* we only want to skip the conv when we're the only user
614 * (not optimal but for now...)
616 if(get_irn_n_edges(node) > 1)
619 src_mode = get_irn_mode(get_Conv_op(node));
620 dest_mode = get_irn_mode(node);
621 return mode_needs_gp_reg(src_mode)
622 && mode_needs_gp_reg(dest_mode)
623 && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode);
626 /* Skip all Down-Conv's on a given node and return the resulting node. */
627 ir_node *ia32_skip_downconv(ir_node *node) {
628 while (is_downconv(node))
629 node = get_Conv_op(node);
635 static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
637 ir_mode *mode = get_irn_mode(node);
642 if(mode_is_signed(mode)) {
647 block = get_nodes_block(node);
648 dbgi = get_irn_dbg_info(node);
650 return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
654 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
655 ir_node *op1, ir_node *op2, match_flags_t flags)
657 ia32_address_t *addr = &am->addr;
658 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
661 ir_mode *mode = get_irn_mode(op2);
663 unsigned commutative;
664 int use_am_and_immediates;
666 int mode_bits = get_mode_size_bits(mode);
668 memset(am, 0, sizeof(am[0]));
670 commutative = (flags & match_commutative) != 0;
671 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
672 use_am = (flags & match_am) != 0;
673 use_immediate = (flags & match_immediate) != 0;
674 assert(!use_am_and_immediates || use_immediate);
677 assert(!commutative || op1 != NULL);
680 if (! (flags & match_8bit_am))
682 assert((flags & match_mode_neutral) || (flags & match_8bit));
683 } else if(mode_bits == 16) {
684 if(! (flags & match_16bit_am))
686 assert((flags & match_mode_neutral) || (flags & match_16bit));
689 /* we can simply skip downconvs for mode neutral nodes: the upper bits
690 * can be random for these operations */
691 if(flags & match_mode_neutral) {
692 op2 = ia32_skip_downconv(op2);
694 op1 = ia32_skip_downconv(op1);
698 if(! (flags & match_try_am) && use_immediate)
699 new_op2 = try_create_Immediate(op2, 0);
703 if(new_op2 == NULL && use_am && ia32_use_source_address_mode(block, op2, op1)) {
704 build_address(am, op2);
705 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
706 if(mode_is_float(mode)) {
707 new_op2 = ia32_new_NoReg_vfp(env_cg);
711 am->op_type = ia32_AddrModeS;
712 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
713 use_am && ia32_use_source_address_mode(block, op1, op2)) {
715 build_address(am, op1);
717 if(mode_is_float(mode)) {
718 noreg = ia32_new_NoReg_vfp(env_cg);
723 if(new_op2 != NULL) {
726 new_op1 = be_transform_node(op2);
728 am->ins_permuted = 1;
730 am->op_type = ia32_AddrModeS;
732 if(flags & match_try_am) {
735 am->op_type = ia32_Normal;
739 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
741 new_op2 = be_transform_node(op2);
742 am->op_type = ia32_Normal;
743 am->ls_mode = get_irn_mode(op2);
744 if(flags & match_mode_neutral)
745 am->ls_mode = mode_Iu;
747 if(addr->base == NULL)
748 addr->base = noreg_gp;
749 if(addr->index == NULL)
750 addr->index = noreg_gp;
751 if(addr->mem == NULL)
752 addr->mem = new_NoMem();
754 am->new_op1 = new_op1;
755 am->new_op2 = new_op2;
756 am->commutative = commutative;
759 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
761 ir_graph *irg = current_ir_graph;
765 if(am->mem_proj == NULL)
768 /* we have to create a mode_T so the old MemProj can attach to us */
769 mode = get_irn_mode(node);
770 load = get_Proj_pred(am->mem_proj);
772 mark_irn_visited(load);
773 be_set_transformed_node(load, node);
776 set_irn_mode(node, mode_T);
777 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
784 * Construct a standard binary operation, set AM and immediate if required.
786 * @param op1 The first operand
787 * @param op2 The second operand
788 * @param func The node constructor function
789 * @return The constructed ia32 node.
791 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
792 construct_binop_func *func, match_flags_t flags)
794 ir_node *block = get_nodes_block(node);
795 ir_node *new_block = be_transform_node(block);
796 ir_graph *irg = current_ir_graph;
797 dbg_info *dbgi = get_irn_dbg_info(node);
799 ia32_address_mode_t am;
800 ia32_address_t *addr = &am.addr;
802 match_arguments(&am, block, op1, op2, flags);
804 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
805 am.new_op1, am.new_op2);
806 set_am_attributes(new_node, &am);
807 /* we can't use source address mode anymore when using immediates */
808 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
809 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
810 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
812 new_node = fix_mem_proj(new_node, &am);
819 n_ia32_l_binop_right,
820 n_ia32_l_binop_eflags
822 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
823 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
824 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
825 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left)
826 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right)
827 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
830 * Construct a binary operation which also consumes the eflags.
832 * @param node The node to transform
833 * @param func The node constructor function
834 * @param flags The match flags
835 * @return The constructor ia32 node
837 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
840 ir_node *src_block = get_nodes_block(node);
841 ir_node *block = be_transform_node(src_block);
842 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
843 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
844 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
845 ir_node *new_eflags = be_transform_node(eflags);
846 ir_graph *irg = current_ir_graph;
847 dbg_info *dbgi = get_irn_dbg_info(node);
849 ia32_address_mode_t am;
850 ia32_address_t *addr = &am.addr;
852 match_arguments(&am, src_block, op1, op2, flags);
854 new_node = func(dbgi, irg, block, addr->base, addr->index,
855 addr->mem, am.new_op1, am.new_op2, new_eflags);
856 set_am_attributes(new_node, &am);
857 /* we can't use source address mode anymore when using immediates */
858 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
859 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
860 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
862 new_node = fix_mem_proj(new_node, &am);
867 static ir_node *get_fpcw(void)
870 if(initial_fpcw != NULL)
873 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
874 &ia32_fp_cw_regs[REG_FPCW]);
875 initial_fpcw = be_transform_node(fpcw);
881 * Construct a standard binary operation, set AM and immediate if required.
883 * @param op1 The first operand
884 * @param op2 The second operand
885 * @param func The node constructor function
886 * @return The constructed ia32 node.
888 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
889 construct_binop_float_func *func,
892 ir_graph *irg = current_ir_graph;
893 dbg_info *dbgi = get_irn_dbg_info(node);
894 ir_node *block = get_nodes_block(node);
895 ir_node *new_block = be_transform_node(block);
897 ia32_address_mode_t am;
898 ia32_address_t *addr = &am.addr;
900 match_arguments(&am, block, op1, op2, flags);
902 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
903 am.new_op1, am.new_op2, get_fpcw());
904 set_am_attributes(new_node, &am);
906 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
908 new_node = fix_mem_proj(new_node, &am);
914 * Construct a shift/rotate binary operation, sets AM and immediate if required.
916 * @param op1 The first operand
917 * @param op2 The second operand
918 * @param func The node constructor function
919 * @return The constructed ia32 node.
921 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
922 construct_shift_func *func,
925 dbg_info *dbgi = get_irn_dbg_info(node);
926 ir_graph *irg = current_ir_graph;
927 ir_node *block = get_nodes_block(node);
928 ir_node *new_block = be_transform_node(block);
929 ir_mode *mode = get_irn_mode(node);
934 assert(! mode_is_float(mode));
935 assert(flags & match_immediate);
936 assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
938 if(flags & match_mode_neutral) {
939 op1 = ia32_skip_downconv(op1);
941 new_op1 = be_transform_node(op1);
943 /* the shift amount can be any mode that is bigger than 5 bits, since all
944 * other bits are ignored anyway */
945 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
946 op2 = get_Conv_op(op2);
947 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
949 new_op2 = create_immediate_or_transform(op2, 0);
951 new_node = func(dbgi, irg, new_block, new_op1, new_op2);
952 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
954 /* lowered shift instruction may have a dependency operand, handle it here */
955 if (get_irn_arity(node) == 3) {
956 /* we have a dependency */
957 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
958 add_irn_dep(new_node, new_dep);
966 * Construct a standard unary operation, set AM and immediate if required.
968 * @param op The operand
969 * @param func The node constructor function
970 * @return The constructed ia32 node.
972 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
975 ir_graph *irg = current_ir_graph;
976 dbg_info *dbgi = get_irn_dbg_info(node);
977 ir_node *block = get_nodes_block(node);
978 ir_node *new_block = be_transform_node(block);
982 assert(flags == 0 || flags == match_mode_neutral);
983 if(flags & match_mode_neutral) {
984 op = ia32_skip_downconv(op);
987 new_op = be_transform_node(op);
988 new_node = func(dbgi, irg, new_block, new_op);
990 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
995 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
996 ia32_address_t *addr)
998 ir_graph *irg = current_ir_graph;
999 ir_node *base = addr->base;
1000 ir_node *index = addr->index;
1004 base = ia32_new_NoReg_gp(env_cg);
1006 base = be_transform_node(base);
1010 index = ia32_new_NoReg_gp(env_cg);
1012 index = be_transform_node(index);
1015 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1016 set_address(res, addr);
1021 static int am_has_immediates(const ia32_address_t *addr)
1023 return addr->offset != 0 || addr->symconst_ent != NULL
1024 || addr->frame_entity || addr->use_frame;
1028 * Creates an ia32 Add.
1030 * @return the created ia32 Add node
1032 static ir_node *gen_Add(ir_node *node) {
1033 ir_graph *irg = current_ir_graph;
1034 dbg_info *dbgi = get_irn_dbg_info(node);
1035 ir_node *block = get_nodes_block(node);
1036 ir_node *new_block = be_transform_node(block);
1037 ir_node *op1 = get_Add_left(node);
1038 ir_node *op2 = get_Add_right(node);
1039 ir_mode *mode = get_irn_mode(node);
1041 ir_node *add_immediate_op;
1042 ia32_address_t addr;
1043 ia32_address_mode_t am;
1045 if (mode_is_float(mode)) {
1046 if (USE_SSE2(env_cg))
1047 return gen_binop(node, op1, op2, new_rd_ia32_xAdd,
1048 match_commutative | match_am);
1050 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd,
1051 match_commutative | match_am);
1054 ia32_mark_non_am(node);
1056 op2 = ia32_skip_downconv(op2);
1057 op1 = ia32_skip_downconv(op1);
1061 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1062 * 1. Add with immediate -> Lea
1063 * 2. Add with possible source address mode -> Add
1064 * 3. Otherwise -> Lea
1066 memset(&addr, 0, sizeof(addr));
1067 ia32_create_address_mode(&addr, node, /*force=*/1);
1068 add_immediate_op = NULL;
1070 if(addr.base == NULL && addr.index == NULL) {
1071 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
1072 addr.symconst_sign, addr.offset);
1073 add_irn_dep(new_node, get_irg_frame(irg));
1074 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1077 /* add with immediate? */
1078 if(addr.index == NULL) {
1079 add_immediate_op = addr.base;
1080 } else if(addr.base == NULL && addr.scale == 0) {
1081 add_immediate_op = addr.index;
1084 if(add_immediate_op != NULL) {
1085 if(!am_has_immediates(&addr)) {
1086 #ifdef DEBUG_libfirm
1087 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1090 return be_transform_node(add_immediate_op);
1093 new_node = create_lea_from_address(dbgi, new_block, &addr);
1094 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1098 /* test if we can use source address mode */
1099 match_arguments(&am, block, op1, op2, match_commutative
1100 | match_mode_neutral | match_am | match_immediate | match_try_am);
1102 /* construct an Add with source address mode */
1103 if (am.op_type == ia32_AddrModeS) {
1104 ia32_address_t *am_addr = &am.addr;
1105 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
1106 am_addr->index, am_addr->mem, am.new_op1,
1108 set_am_attributes(new_node, &am);
1109 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1111 new_node = fix_mem_proj(new_node, &am);
1116 /* otherwise construct a lea */
1117 new_node = create_lea_from_address(dbgi, new_block, &addr);
1118 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1123 * Creates an ia32 Mul.
1125 * @return the created ia32 Mul node
1127 static ir_node *gen_Mul(ir_node *node) {
1128 ir_node *op1 = get_Mul_left(node);
1129 ir_node *op2 = get_Mul_right(node);
1130 ir_mode *mode = get_irn_mode(node);
1132 if (mode_is_float(mode)) {
1133 if (USE_SSE2(env_cg))
1134 return gen_binop(node, op1, op2, new_rd_ia32_xMul,
1135 match_commutative | match_am);
1137 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul,
1138 match_commutative | match_am);
1142 for the lower 32bit of the result it doesn't matter whether we use
1143 signed or unsigned multiplication so we use IMul as it has fewer
1146 return gen_binop(node, op1, op2, new_rd_ia32_IMul,
1147 match_commutative | match_am | match_mode_neutral);
1151 * Creates an ia32 Mulh.
1152 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1153 * this result while Mul returns the lower 32 bit.
1155 * @return the created ia32 Mulh node
1157 static ir_node *gen_Mulh(ir_node *node)
1159 ir_node *block = get_nodes_block(node);
1160 ir_node *new_block = be_transform_node(block);
1161 ir_graph *irg = current_ir_graph;
1162 dbg_info *dbgi = get_irn_dbg_info(node);
1163 ir_mode *mode = get_irn_mode(node);
1164 ir_node *op1 = get_Mulh_left(node);
1165 ir_node *op2 = get_Mulh_right(node);
1168 match_flags_t flags;
1169 ia32_address_mode_t am;
1170 ia32_address_t *addr = &am.addr;
1172 flags = match_commutative | match_am;
1174 assert(!mode_is_float(mode) && "Mulh with float not supported");
1175 assert(get_mode_size_bits(mode) == 32);
1177 match_arguments(&am, block, op1, op2, flags);
1179 if (mode_is_signed(mode)) {
1180 new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base,
1181 addr->index, addr->mem, am.new_op1,
1184 new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base,
1185 addr->index, addr->mem, am.new_op1,
1189 set_am_attributes(new_node, &am);
1190 /* we can't use source address mode anymore when using immediates */
1191 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
1192 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
1193 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1195 assert(get_irn_mode(new_node) == mode_T);
1197 fix_mem_proj(new_node, &am);
1199 assert(pn_ia32_IMul1OP_EDX == pn_ia32_Mul_EDX);
1200 proj_EDX = new_rd_Proj(dbgi, irg, block, new_node,
1201 mode_Iu, pn_ia32_IMul1OP_EDX);
1209 * Creates an ia32 And.
1211 * @return The created ia32 And node
1213 static ir_node *gen_And(ir_node *node) {
1214 ir_node *op1 = get_And_left(node);
1215 ir_node *op2 = get_And_right(node);
1216 assert(! mode_is_float(get_irn_mode(node)));
1218 /* is it a zero extension? */
1219 if (is_Const(op2)) {
1220 tarval *tv = get_Const_tarval(op2);
1221 long v = get_tarval_long(tv);
1223 if (v == 0xFF || v == 0xFFFF) {
1224 dbg_info *dbgi = get_irn_dbg_info(node);
1225 ir_node *block = get_nodes_block(node);
1232 assert(v == 0xFFFF);
1235 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1241 return gen_binop(node, op1, op2, new_rd_ia32_And,
1242 match_commutative | match_mode_neutral | match_am
1249 * Creates an ia32 Or.
1251 * @return The created ia32 Or node
1253 static ir_node *gen_Or(ir_node *node) {
1254 ir_node *op1 = get_Or_left(node);
1255 ir_node *op2 = get_Or_right(node);
1257 assert (! mode_is_float(get_irn_mode(node)));
1258 return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative
1259 | match_mode_neutral | match_am | match_immediate);
1265 * Creates an ia32 Eor.
1267 * @return The created ia32 Eor node
1269 static ir_node *gen_Eor(ir_node *node) {
1270 ir_node *op1 = get_Eor_left(node);
1271 ir_node *op2 = get_Eor_right(node);
1273 assert(! mode_is_float(get_irn_mode(node)));
1274 return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative
1275 | match_mode_neutral | match_am | match_immediate);
1280 * Creates an ia32 Sub.
1282 * @return The created ia32 Sub node
1284 static ir_node *gen_Sub(ir_node *node) {
1285 ir_node *op1 = get_Sub_left(node);
1286 ir_node *op2 = get_Sub_right(node);
1287 ir_mode *mode = get_irn_mode(node);
1289 if (mode_is_float(mode)) {
1290 if (USE_SSE2(env_cg))
1291 return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am);
1293 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub,
1298 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1302 return gen_binop(node, op1, op2, new_rd_ia32_Sub, match_mode_neutral
1303 | match_am | match_immediate);
1307 * Generates an ia32 DivMod with additional infrastructure for the
1308 * register allocator if needed.
1310 static ir_node *create_Div(ir_node *node)
1312 ir_graph *irg = current_ir_graph;
1313 dbg_info *dbgi = get_irn_dbg_info(node);
1314 ir_node *block = get_nodes_block(node);
1315 ir_node *new_block = be_transform_node(block);
1322 ir_node *sign_extension;
1324 ia32_address_mode_t am;
1325 ia32_address_t *addr = &am.addr;
1327 /* the upper bits have random contents for smaller modes */
1329 switch (get_irn_opcode(node)) {
1331 op1 = get_Div_left(node);
1332 op2 = get_Div_right(node);
1333 mem = get_Div_mem(node);
1334 mode = get_Div_resmode(node);
1335 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1338 op1 = get_Mod_left(node);
1339 op2 = get_Mod_right(node);
1340 mem = get_Mod_mem(node);
1341 mode = get_Mod_resmode(node);
1342 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1345 op1 = get_DivMod_left(node);
1346 op2 = get_DivMod_right(node);
1347 mem = get_DivMod_mem(node);
1348 mode = get_DivMod_resmode(node);
1349 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1352 panic("invalid divmod node %+F", node);
1355 match_arguments(&am, block, op1, op2, match_am);
1357 if(!is_NoMem(mem)) {
1358 new_mem = be_transform_node(mem);
1359 if(!is_NoMem(addr->mem)) {
1363 new_mem = new_rd_Sync(dbgi, irg, new_block, 2, in);
1366 new_mem = addr->mem;
1369 if (mode_is_signed(mode)) {
1370 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1371 add_irn_dep(produceval, get_irg_frame(irg));
1372 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1,
1375 new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base,
1376 addr->index, new_mem, am.new_op1,
1377 sign_extension, am.new_op2);
1379 sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0);
1380 add_irn_dep(sign_extension, get_irg_frame(irg));
1382 new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base,
1383 addr->index, new_mem, am.new_op1,
1384 sign_extension, am.new_op2);
1387 set_ia32_exc_label(new_node, has_exc);
1388 set_irn_pinned(new_node, get_irn_pinned(node));
1390 set_am_attributes(new_node, &am);
1391 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1393 new_node = fix_mem_proj(new_node, &am);
1399 static ir_node *gen_Mod(ir_node *node) {
1400 return create_Div(node);
1403 static ir_node *gen_Div(ir_node *node) {
1404 return create_Div(node);
1407 static ir_node *gen_DivMod(ir_node *node) {
1408 return create_Div(node);
1414 * Creates an ia32 floating Div.
1416 * @return The created ia32 xDiv node
1418 static ir_node *gen_Quot(ir_node *node)
1420 ir_node *op1 = get_Quot_left(node);
1421 ir_node *op2 = get_Quot_right(node);
1423 if (USE_SSE2(env_cg)) {
1424 return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am);
1426 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, match_am);
1432 * Creates an ia32 Shl.
1434 * @return The created ia32 Shl node
1436 static ir_node *gen_Shl(ir_node *node) {
1437 ir_node *left = get_Shl_left(node);
1438 ir_node *right = get_Shl_right(node);
1440 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
1441 match_mode_neutral | match_immediate);
1445 * Creates an ia32 Shr.
1447 * @return The created ia32 Shr node
1449 static ir_node *gen_Shr(ir_node *node) {
1450 ir_node *left = get_Shr_left(node);
1451 ir_node *right = get_Shr_right(node);
1453 return gen_shift_binop(node, left, right, new_rd_ia32_Shr, match_immediate);
1459 * Creates an ia32 Sar.
1461 * @return The created ia32 Shrs node
1463 static ir_node *gen_Shrs(ir_node *node) {
1464 ir_node *left = get_Shrs_left(node);
1465 ir_node *right = get_Shrs_right(node);
1466 ir_mode *mode = get_irn_mode(node);
1468 if(is_Const(right) && mode == mode_Is) {
1469 tarval *tv = get_Const_tarval(right);
1470 long val = get_tarval_long(tv);
1472 /* this is a sign extension */
1473 ir_graph *irg = current_ir_graph;
1474 dbg_info *dbgi = get_irn_dbg_info(node);
1475 ir_node *block = be_transform_node(get_nodes_block(node));
1477 ir_node *new_op = be_transform_node(op);
1478 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1479 add_irn_dep(pval, get_irg_frame(irg));
1481 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1485 /* 8 or 16 bit sign extension? */
1486 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1487 ir_node *shl_left = get_Shl_left(left);
1488 ir_node *shl_right = get_Shl_right(left);
1489 if(is_Const(shl_right)) {
1490 tarval *tv1 = get_Const_tarval(right);
1491 tarval *tv2 = get_Const_tarval(shl_right);
1492 if(tv1 == tv2 && tarval_is_long(tv1)) {
1493 long val = get_tarval_long(tv1);
1494 if(val == 16 || val == 24) {
1495 dbg_info *dbgi = get_irn_dbg_info(node);
1496 ir_node *block = get_nodes_block(node);
1506 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1515 return gen_shift_binop(node, left, right, new_rd_ia32_Sar, match_immediate);
1521 * Creates an ia32 RotL.
1523 * @param op1 The first operator
1524 * @param op2 The second operator
1525 * @return The created ia32 RotL node
1527 static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) {
1528 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate);
1534 * Creates an ia32 RotR.
1535 * NOTE: There is no RotR with immediate because this would always be a RotL
1536 * "imm-mode_size_bits" which can be pre-calculated.
1538 * @param op1 The first operator
1539 * @param op2 The second operator
1540 * @return The created ia32 RotR node
1542 static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) {
1543 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate);
1549 * Creates an ia32 RotR or RotL (depending on the found pattern).
1551 * @return The created ia32 RotL or RotR node
1553 static ir_node *gen_Rot(ir_node *node) {
1554 ir_node *rotate = NULL;
1555 ir_node *op1 = get_Rot_left(node);
1556 ir_node *op2 = get_Rot_right(node);
1558 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1559 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1560 that means we can create a RotR instead of an Add and a RotL */
1562 if (get_irn_op(op2) == op_Add) {
1564 ir_node *left = get_Add_left(add);
1565 ir_node *right = get_Add_right(add);
1566 if (is_Const(right)) {
1567 tarval *tv = get_Const_tarval(right);
1568 ir_mode *mode = get_irn_mode(node);
1569 long bits = get_mode_size_bits(mode);
1571 if (get_irn_op(left) == op_Minus &&
1572 tarval_is_long(tv) &&
1573 get_tarval_long(tv) == bits &&
1576 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1577 rotate = gen_RotR(node, op1, get_Minus_op(left));
1582 if (rotate == NULL) {
1583 rotate = gen_RotL(node, op1, op2);
1592 * Transforms a Minus node.
1594 * @return The created ia32 Minus node
1596 static ir_node *gen_Minus(ir_node *node)
1598 ir_node *op = get_Minus_op(node);
1599 ir_node *block = be_transform_node(get_nodes_block(node));
1600 ir_graph *irg = current_ir_graph;
1601 dbg_info *dbgi = get_irn_dbg_info(node);
1602 ir_mode *mode = get_irn_mode(node);
1607 if (mode_is_float(mode)) {
1608 ir_node *new_op = be_transform_node(op);
1609 if (USE_SSE2(env_cg)) {
1610 /* TODO: non-optimal... if we have many xXors, then we should
1611 * rather create a load for the const and use that instead of
1612 * several AM nodes... */
1613 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1614 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1615 ir_node *nomem = new_rd_NoMem(irg);
1617 new_node = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp,
1618 nomem, new_op, noreg_xmm);
1620 size = get_mode_size_bits(mode);
1621 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1623 set_ia32_am_sc(new_node, ent);
1624 set_ia32_op_type(new_node, ia32_AddrModeS);
1625 set_ia32_ls_mode(new_node, mode);
1627 new_node = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1630 new_node = gen_unop(node, op, new_rd_ia32_Neg, match_mode_neutral);
1633 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1639 * Transforms a Not node.
1641 * @return The created ia32 Not node
1643 static ir_node *gen_Not(ir_node *node) {
1644 ir_node *op = get_Not_op(node);
1646 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1647 assert (! mode_is_float(get_irn_mode(node)));
1649 return gen_unop(node, op, new_rd_ia32_Not, match_mode_neutral);
1655 * Transforms an Abs node.
1657 * @return The created ia32 Abs node
1659 static ir_node *gen_Abs(ir_node *node)
1661 ir_node *block = be_transform_node(get_nodes_block(node));
1662 ir_node *op = get_Abs_op(node);
1663 ir_node *new_op = be_transform_node(op);
1664 ir_graph *irg = current_ir_graph;
1665 dbg_info *dbgi = get_irn_dbg_info(node);
1666 ir_mode *mode = get_irn_mode(node);
1667 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1668 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1669 ir_node *nomem = new_NoMem();
1674 if (mode_is_float(mode)) {
1675 if (USE_SSE2(env_cg)) {
1676 new_node = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp,
1677 nomem, new_op, noreg_fp);
1679 size = get_mode_size_bits(mode);
1680 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1682 set_ia32_am_sc(new_node, ent);
1684 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1686 set_ia32_op_type(new_node, ia32_AddrModeS);
1687 set_ia32_ls_mode(new_node, mode);
1689 new_node = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1690 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1694 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1695 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1698 assert(get_mode_size_bits(mode) == 32);
1700 add_irn_dep(pval, get_irg_frame(irg));
1701 SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node));
1703 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1704 new_op, sign_extension);
1705 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1707 new_node = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1708 xor, sign_extension);
1709 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1716 * Transforms a Load.
1718 * @return the created ia32 Load node
1720 static ir_node *gen_Load(ir_node *node) {
1721 ir_node *old_block = get_nodes_block(node);
1722 ir_node *block = be_transform_node(old_block);
1723 ir_node *ptr = get_Load_ptr(node);
1724 ir_node *mem = get_Load_mem(node);
1725 ir_node *new_mem = be_transform_node(mem);
1728 ir_graph *irg = current_ir_graph;
1729 dbg_info *dbgi = get_irn_dbg_info(node);
1730 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1731 ir_mode *mode = get_Load_mode(node);
1734 ia32_address_t addr;
1736 /* construct load address */
1737 memset(&addr, 0, sizeof(addr));
1738 ia32_create_address_mode(&addr, ptr, /*force=*/0);
1745 base = be_transform_node(base);
1751 index = be_transform_node(index);
1754 if (mode_is_float(mode)) {
1755 if (USE_SSE2(env_cg)) {
1756 new_node = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1758 res_mode = mode_xmm;
1760 new_node = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1762 res_mode = mode_vfp;
1765 assert(mode != mode_b);
1767 /* create a conv node with address mode for smaller modes */
1768 if(get_mode_size_bits(mode) < 32) {
1769 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1770 new_mem, noreg, mode);
1772 new_node = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1777 set_irn_pinned(new_node, get_irn_pinned(node));
1778 set_ia32_op_type(new_node, ia32_AddrModeS);
1779 set_ia32_ls_mode(new_node, mode);
1780 set_address(new_node, &addr);
1782 /* make sure we are scheduled behind the initial IncSP/Barrier
1783 * to avoid spills being placed before it
1785 if (block == get_irg_start_block(irg)) {
1786 add_irn_dep(new_node, get_irg_frame(irg));
1789 set_ia32_exc_label(new_node,
1790 be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1791 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1796 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1797 ir_node *ptr, ir_node *other)
1804 /* we only use address mode if we're the only user of the load */
1805 if(get_irn_n_edges(node) > 1)
1808 load = get_Proj_pred(node);
1811 if(get_nodes_block(load) != block)
1814 /* Store should be attached to the load */
1815 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1817 /* store should have the same pointer as the load */
1818 if(get_Load_ptr(load) != ptr)
1821 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1822 if(other != NULL && get_nodes_block(other) == block
1823 && heights_reachable_in_block(heights, other, load))
1829 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1830 ir_node *mem, ir_node *ptr, ir_mode *mode,
1831 construct_binop_dest_func *func,
1832 construct_binop_dest_func *func8bit,
1833 match_flags_t flags)
1835 ir_node *src_block = get_nodes_block(node);
1837 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1838 ir_graph *irg = current_ir_graph;
1843 ia32_address_mode_t am;
1844 ia32_address_t *addr = &am.addr;
1845 memset(&am, 0, sizeof(am));
1847 assert(flags & match_dest_am);
1848 assert(flags & match_immediate); /* there is no destam node without... */
1849 commutative = (flags & match_commutative) != 0;
1851 if(use_dest_am(src_block, op1, mem, ptr, op2)) {
1852 build_address(&am, op1);
1853 new_op = create_immediate_or_transform(op2, 0);
1854 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
1855 build_address(&am, op2);
1856 new_op = create_immediate_or_transform(op1, 0);
1861 if(addr->base == NULL)
1862 addr->base = noreg_gp;
1863 if(addr->index == NULL)
1864 addr->index = noreg_gp;
1865 if(addr->mem == NULL)
1866 addr->mem = new_NoMem();
1868 dbgi = get_irn_dbg_info(node);
1869 block = be_transform_node(src_block);
1870 if(get_mode_size_bits(mode) == 8) {
1871 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1874 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1877 set_address(new_node, addr);
1878 set_ia32_op_type(new_node, ia32_AddrModeD);
1879 set_ia32_ls_mode(new_node, mode);
1880 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1885 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1886 ir_node *ptr, ir_mode *mode,
1887 construct_unop_dest_func *func)
1889 ir_node *src_block = get_nodes_block(node);
1891 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1892 ir_graph *irg = current_ir_graph;
1895 ia32_address_mode_t am;
1896 ia32_address_t *addr = &am.addr;
1897 memset(&am, 0, sizeof(am));
1899 if(!use_dest_am(src_block, op, mem, ptr, NULL))
1902 build_address(&am, op);
1904 if(addr->base == NULL)
1905 addr->base = noreg_gp;
1906 if(addr->index == NULL)
1907 addr->index = noreg_gp;
1908 if(addr->mem == NULL)
1909 addr->mem = new_NoMem();
1911 dbgi = get_irn_dbg_info(node);
1912 block = be_transform_node(src_block);
1913 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1914 set_address(new_node, addr);
1915 set_ia32_op_type(new_node, ia32_AddrModeD);
1916 set_ia32_ls_mode(new_node, mode);
1917 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1922 static ir_node *try_create_dest_am(ir_node *node) {
1923 ir_node *val = get_Store_value(node);
1924 ir_node *mem = get_Store_mem(node);
1925 ir_node *ptr = get_Store_ptr(node);
1926 ir_mode *mode = get_irn_mode(val);
1931 /* handle only GP modes for now... */
1932 if(!mode_needs_gp_reg(mode))
1935 /* store must be the only user of the val node */
1936 if(get_irn_n_edges(val) > 1)
1939 switch(get_irn_opcode(val)) {
1941 op1 = get_Add_left(val);
1942 op2 = get_Add_right(val);
1943 if(is_Const_1(op2)) {
1944 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1945 new_rd_ia32_IncMem);
1947 } else if(is_Const_Minus_1(op2)) {
1948 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1949 new_rd_ia32_DecMem);
1952 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1953 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit,
1954 match_dest_am | match_commutative |
1958 op1 = get_Sub_left(val);
1959 op2 = get_Sub_right(val);
1961 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
1964 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1965 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit,
1966 match_dest_am | match_immediate |
1970 op1 = get_And_left(val);
1971 op2 = get_And_right(val);
1972 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1973 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit,
1974 match_dest_am | match_commutative |
1978 op1 = get_Or_left(val);
1979 op2 = get_Or_right(val);
1980 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1981 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit,
1982 match_dest_am | match_commutative |
1986 op1 = get_Eor_left(val);
1987 op2 = get_Eor_right(val);
1988 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1989 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit,
1990 match_dest_am | match_commutative |
1994 op1 = get_Shl_left(val);
1995 op2 = get_Shl_right(val);
1996 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1997 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem,
1998 match_dest_am | match_immediate);
2001 op1 = get_Shr_left(val);
2002 op2 = get_Shr_right(val);
2003 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2004 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem,
2005 match_dest_am | match_immediate);
2008 op1 = get_Shrs_left(val);
2009 op2 = get_Shrs_right(val);
2010 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2011 new_rd_ia32_SarMem, new_rd_ia32_SarMem,
2012 match_dest_am | match_immediate);
2015 op1 = get_Rot_left(val);
2016 op2 = get_Rot_right(val);
2017 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2018 new_rd_ia32_RolMem, new_rd_ia32_RolMem,
2019 match_dest_am | match_immediate);
2021 /* TODO: match ROR patterns... */
2023 op1 = get_Minus_op(val);
2024 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
2027 /* should be lowered already */
2028 assert(mode != mode_b);
2029 op1 = get_Not_op(val);
2030 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
2040 * Transforms a Store.
2042 * @return the created ia32 Store node
2044 static ir_node *gen_Store(ir_node *node) {
2045 ir_node *block = be_transform_node(get_nodes_block(node));
2046 ir_node *ptr = get_Store_ptr(node);
2049 ir_node *val = get_Store_value(node);
2051 ir_node *mem = get_Store_mem(node);
2052 ir_node *new_mem = be_transform_node(mem);
2053 ir_graph *irg = current_ir_graph;
2054 dbg_info *dbgi = get_irn_dbg_info(node);
2055 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2056 ir_mode *mode = get_irn_mode(val);
2058 ia32_address_t addr;
2060 /* check for destination address mode */
2061 new_node = try_create_dest_am(node);
2062 if(new_node != NULL)
2065 /* construct store address */
2066 memset(&addr, 0, sizeof(addr));
2067 ia32_create_address_mode(&addr, ptr, /*force=*/0);
2074 base = be_transform_node(base);
2080 index = be_transform_node(index);
2083 if (mode_is_float(mode)) {
2084 /* convs (and strict-convs) before stores are unnecessary if the mode
2086 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2087 val = get_Conv_op(val);
2089 new_val = be_transform_node(val);
2090 if (USE_SSE2(env_cg)) {
2091 new_node = new_rd_ia32_xStore(dbgi, irg, block, base, index,
2094 new_node = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem,
2098 new_val = create_immediate_or_transform(val, 0);
2102 if (get_mode_size_bits(mode) == 8) {
2103 new_node = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index,
2106 new_node = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
2111 set_irn_pinned(new_node, get_irn_pinned(node));
2112 set_ia32_op_type(new_node, ia32_AddrModeD);
2113 set_ia32_ls_mode(new_node, mode);
2115 set_ia32_exc_label(new_node,
2116 be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
2117 set_address(new_node, &addr);
2118 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2123 static ir_node *create_Switch(ir_node *node)
2125 ir_graph *irg = current_ir_graph;
2126 dbg_info *dbgi = get_irn_dbg_info(node);
2127 ir_node *block = be_transform_node(get_nodes_block(node));
2128 ir_node *sel = get_Cond_selector(node);
2129 ir_node *new_sel = be_transform_node(sel);
2130 int switch_min = INT_MAX;
2132 const ir_edge_t *edge;
2134 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2136 /* determine the smallest switch case value */
2137 foreach_out_edge(node, edge) {
2138 ir_node *proj = get_edge_src_irn(edge);
2139 int pn = get_Proj_proj(proj);
2144 if (switch_min != 0) {
2145 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2147 /* if smallest switch case is not 0 we need an additional sub */
2148 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2149 add_ia32_am_offs_int(new_sel, -switch_min);
2150 set_ia32_op_type(new_sel, ia32_AddrModeS);
2152 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2155 new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel,
2156 get_Cond_defaultProj(node));
2157 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2162 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
2164 ir_graph *irg = current_ir_graph;
2172 /* we have a Cmp as input */
2174 ir_node *pred = get_Proj_pred(node);
2176 flags = be_transform_node(pred);
2177 *pnc_out = get_Proj_proj(node);
2182 /* a mode_b value, we have to compare it against 0 */
2183 dbgi = get_irn_dbg_info(node);
2184 new_block = be_transform_node(get_nodes_block(node));
2185 new_op = be_transform_node(node);
2186 noreg = ia32_new_NoReg_gp(env_cg);
2187 nomem = new_NoMem();
2188 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
2189 new_op, new_op, 0, 0);
2190 *pnc_out = pn_Cmp_Lg;
2194 static ir_node *gen_Cond(ir_node *node) {
2195 ir_node *block = get_nodes_block(node);
2196 ir_node *new_block = be_transform_node(block);
2197 ir_graph *irg = current_ir_graph;
2198 dbg_info *dbgi = get_irn_dbg_info(node);
2199 ir_node *sel = get_Cond_selector(node);
2200 ir_mode *sel_mode = get_irn_mode(sel);
2201 ir_node *flags = NULL;
2205 if (sel_mode != mode_b) {
2206 return create_Switch(node);
2209 /* we get flags from a cmp */
2210 flags = get_flags_node(sel, &pnc);
2212 new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2213 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2221 * Transforms a CopyB node.
2223 * @return The transformed node.
2225 static ir_node *gen_CopyB(ir_node *node) {
2226 ir_node *block = be_transform_node(get_nodes_block(node));
2227 ir_node *src = get_CopyB_src(node);
2228 ir_node *new_src = be_transform_node(src);
2229 ir_node *dst = get_CopyB_dst(node);
2230 ir_node *new_dst = be_transform_node(dst);
2231 ir_node *mem = get_CopyB_mem(node);
2232 ir_node *new_mem = be_transform_node(mem);
2233 ir_node *res = NULL;
2234 ir_graph *irg = current_ir_graph;
2235 dbg_info *dbgi = get_irn_dbg_info(node);
2236 int size = get_type_size_bytes(get_CopyB_type(node));
2239 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2240 /* then we need the size explicitly in ECX. */
2241 if (size >= 32 * 4) {
2242 rem = size & 0x3; /* size % 4 */
2245 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2246 add_irn_dep(res, get_irg_frame(irg));
2248 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
2251 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2254 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
2257 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2262 static ir_node *gen_be_Copy(ir_node *node)
2264 ir_node *new_node = be_duplicate_node(node);
2265 ir_mode *mode = get_irn_mode(new_node);
2267 if (mode_needs_gp_reg(mode)) {
2268 set_irn_mode(new_node, mode_Iu);
2275 * helper function: checks whether all Cmp projs are Lg or Eq which is needed
2276 * to fold an And into a test node
2278 static int can_fold_test_and(ir_node *node)
2280 const ir_edge_t *edge;
2282 /* we can only have Eq and Lg Projs */
2283 foreach_out_edge(node, edge) {
2284 ir_node *proj = get_edge_src_irn(edge);
2285 pn_Cmp pnc = get_Proj_proj(proj);
2286 if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2293 static ir_node *try_create_Test(ir_node *node)
2295 ir_graph *irg = current_ir_graph;
2296 dbg_info *dbgi = get_irn_dbg_info(node);
2297 ir_node *block = get_nodes_block(node);
2298 ir_node *new_block = be_transform_node(block);
2299 ir_node *cmp_left = get_Cmp_left(node);
2300 ir_node *cmp_right = get_Cmp_right(node);
2305 ia32_address_mode_t am;
2306 ia32_address_t *addr = &am.addr;
2309 /* can we use a test instruction? */
2310 if(!is_Const_0(cmp_right))
2313 if(is_And(cmp_left) && get_irn_n_edges(cmp_left) == 1 &&
2314 can_fold_test_and(node)) {
2315 ir_node *and_left = get_And_left(cmp_left);
2316 ir_node *and_right = get_And_right(cmp_left);
2318 mode = get_irn_mode(and_left);
2322 mode = get_irn_mode(cmp_left);
2327 assert(get_mode_size_bits(mode) <= 32);
2329 match_arguments(&am, block, left, right, match_commutative |
2330 match_am | match_8bit_am | match_16bit_am |
2331 match_am_and_immediates | match_immediate |
2332 match_8bit | match_16bit);
2334 cmp_unsigned = !mode_is_signed(mode);
2335 if(get_mode_size_bits(mode) == 8) {
2336 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2337 addr->index, addr->mem, am.new_op1,
2338 am.new_op2, am.ins_permuted,
2341 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2342 addr->index, addr->mem, am.new_op1,
2343 am.new_op2, am.ins_permuted, cmp_unsigned);
2345 set_am_attributes(new_node, &am);
2346 assert(mode != NULL);
2347 set_ia32_ls_mode(new_node, mode);
2349 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2351 new_node = fix_mem_proj(new_node, &am);
2355 static ir_node *create_Fucom(ir_node *node)
2357 ir_graph *irg = current_ir_graph;
2358 dbg_info *dbgi = get_irn_dbg_info(node);
2359 ir_node *block = get_nodes_block(node);
2360 ir_node *new_block = be_transform_node(block);
2361 ir_node *left = get_Cmp_left(node);
2362 ir_node *new_left = be_transform_node(left);
2363 ir_node *right = get_Cmp_right(node);
2367 if(transform_config.use_fucomi) {
2368 new_right = be_transform_node(right);
2369 new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left,
2371 set_ia32_commutative(new_node);
2372 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2374 if(transform_config.use_ftst && is_Const_null(right)) {
2375 new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left,
2378 new_right = be_transform_node(right);
2379 new_node = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2383 set_ia32_commutative(new_node);
2385 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2387 new_node = new_rd_ia32_Sahf(dbgi, irg, new_block, new_node);
2388 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2394 static ir_node *create_Ucomi(ir_node *node)
2396 ir_graph *irg = current_ir_graph;
2397 dbg_info *dbgi = get_irn_dbg_info(node);
2398 ir_node *src_block = get_nodes_block(node);
2399 ir_node *new_block = be_transform_node(src_block);
2400 ir_node *left = get_Cmp_left(node);
2401 ir_node *right = get_Cmp_right(node);
2403 ia32_address_mode_t am;
2404 ia32_address_t *addr = &am.addr;
2406 match_arguments(&am, src_block, left, right, match_commutative | match_am);
2408 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2409 addr->mem, am.new_op1, am.new_op2,
2411 set_am_attributes(new_node, &am);
2413 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2415 new_node = fix_mem_proj(new_node, &am);
2420 static ir_node *gen_Cmp(ir_node *node)
2422 ir_graph *irg = current_ir_graph;
2423 dbg_info *dbgi = get_irn_dbg_info(node);
2424 ir_node *block = get_nodes_block(node);
2425 ir_node *new_block = be_transform_node(block);
2426 ir_node *left = get_Cmp_left(node);
2427 ir_node *right = get_Cmp_right(node);
2428 ir_mode *cmp_mode = get_irn_mode(left);
2430 ia32_address_mode_t am;
2431 ia32_address_t *addr = &am.addr;
2434 if(mode_is_float(cmp_mode)) {
2435 if (USE_SSE2(env_cg)) {
2436 return create_Ucomi(node);
2438 return create_Fucom(node);
2442 assert(mode_needs_gp_reg(cmp_mode));
2444 /* we prefer the Test instruction where possible except cases where
2445 * we can use SourceAM */
2446 if(!ia32_use_source_address_mode(block, left, right) &&
2447 !ia32_use_source_address_mode(block, right, left)) {
2448 new_node = try_create_Test(node);
2449 if(new_node != NULL)
2453 match_arguments(&am, block, left, right, match_commutative |
2454 match_am | match_8bit_am | match_16bit_am |
2455 match_immediate | match_am_and_immediates |
2456 match_8bit | match_16bit);
2458 cmp_unsigned = !mode_is_signed(get_irn_mode(left));
2459 if(get_mode_size_bits(cmp_mode) == 8) {
2460 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2461 addr->index, addr->mem, am.new_op1,
2462 am.new_op2, am.ins_permuted,
2465 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2466 addr->index, addr->mem, am.new_op1,
2467 am.new_op2, am.ins_permuted, cmp_unsigned);
2469 set_am_attributes(new_node, &am);
2470 assert(cmp_mode != NULL);
2471 set_ia32_ls_mode(new_node, cmp_mode);
2473 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2475 new_node = fix_mem_proj(new_node, &am);
2480 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2482 ir_graph *irg = current_ir_graph;
2483 dbg_info *dbgi = get_irn_dbg_info(node);
2484 ir_node *block = get_nodes_block(node);
2485 ir_node *new_block = be_transform_node(block);
2486 ir_node *val_true = get_Psi_val(node, 0);
2487 ir_node *val_false = get_Psi_default(node);
2489 match_flags_t match_flags;
2490 ia32_address_mode_t am;
2491 ia32_address_t *addr;
2493 assert(transform_config.use_cmov);
2494 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2498 match_flags = match_commutative | match_am | match_16bit_am |
2501 match_arguments(&am, block, val_false, val_true, match_flags);
2503 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2504 addr->mem, am.new_op1, am.new_op2, new_flags,
2505 am.ins_permuted, pnc);
2506 set_am_attributes(new_node, &am);
2508 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2510 new_node = fix_mem_proj(new_node, &am);
2517 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2518 ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
2521 ir_graph *irg = current_ir_graph;
2522 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2523 ir_node *nomem = new_NoMem();
2526 new_node = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
2527 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2528 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2529 nomem, new_node, mode_Bu);
2530 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2537 * Transforms a Psi node into CMov.
2539 * @return The transformed node.
2541 static ir_node *gen_Psi(ir_node *node)
2543 dbg_info *dbgi = get_irn_dbg_info(node);
2544 ir_node *block = get_nodes_block(node);
2545 ir_node *new_block = be_transform_node(block);
2546 ir_node *psi_true = get_Psi_val(node, 0);
2547 ir_node *psi_default = get_Psi_default(node);
2548 ir_node *cond = get_Psi_cond(node, 0);
2549 ir_node *flags = NULL;
2553 assert(get_Psi_n_conds(node) == 1);
2554 assert(get_irn_mode(cond) == mode_b);
2555 assert(mode_needs_gp_reg(get_irn_mode(node)));
2557 flags = get_flags_node(cond, &pnc);
2559 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2560 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
2561 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2562 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
2564 new_node = create_CMov(node, flags, pnc);
2571 * Create a conversion from x87 state register to general purpose.
2573 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2574 ir_node *block = be_transform_node(get_nodes_block(node));
2575 ir_node *op = get_Conv_op(node);
2576 ir_node *new_op = be_transform_node(op);
2577 ia32_code_gen_t *cg = env_cg;
2578 ir_graph *irg = current_ir_graph;
2579 dbg_info *dbgi = get_irn_dbg_info(node);
2580 ir_node *noreg = ia32_new_NoReg_gp(cg);
2581 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2582 ir_mode *mode = get_irn_mode(node);
2583 ir_node *fist, *load;
2586 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2587 new_NoMem(), new_op, trunc_mode);
2589 set_irn_pinned(fist, op_pin_state_floats);
2590 set_ia32_use_frame(fist);
2591 set_ia32_op_type(fist, ia32_AddrModeD);
2593 assert(get_mode_size_bits(mode) <= 32);
2594 /* exception we can only store signed 32 bit integers, so for unsigned
2595 we store a 64bit (signed) integer and load the lower bits */
2596 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2597 set_ia32_ls_mode(fist, mode_Ls);
2599 set_ia32_ls_mode(fist, mode_Is);
2601 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2604 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2606 set_irn_pinned(load, op_pin_state_floats);
2607 set_ia32_use_frame(load);
2608 set_ia32_op_type(load, ia32_AddrModeS);
2609 set_ia32_ls_mode(load, mode_Is);
2610 if(get_ia32_ls_mode(fist) == mode_Ls) {
2611 ia32_attr_t *attr = get_ia32_attr(load);
2612 attr->data.need_64bit_stackent = 1;
2614 ia32_attr_t *attr = get_ia32_attr(load);
2615 attr->data.need_32bit_stackent = 1;
2617 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2619 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2623 * Creates a x87 strict Conv by placing a Sore and a Load
2625 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2627 ir_node *block = get_nodes_block(node);
2628 ir_graph *irg = current_ir_graph;
2629 dbg_info *dbgi = get_irn_dbg_info(node);
2630 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2631 ir_node *nomem = new_NoMem();
2632 ir_node *frame = get_irg_frame(irg);
2633 ir_node *store, *load;
2636 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2638 set_ia32_use_frame(store);
2639 set_ia32_op_type(store, ia32_AddrModeD);
2640 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2642 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2644 set_ia32_use_frame(load);
2645 set_ia32_op_type(load, ia32_AddrModeS);
2646 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2648 new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2652 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2654 ir_graph *irg = current_ir_graph;
2655 ir_node *start_block = get_irg_start_block(irg);
2656 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2657 symconst, symconst_sign, val);
2658 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2664 * Create a conversion from general purpose to x87 register
2666 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2667 ir_node *src_block = get_nodes_block(node);
2668 ir_node *block = be_transform_node(src_block);
2669 ir_graph *irg = current_ir_graph;
2670 dbg_info *dbgi = get_irn_dbg_info(node);
2671 ir_node *op = get_Conv_op(node);
2672 ir_node *new_op = NULL;
2676 ir_mode *store_mode;
2682 /* fild can use source AM if the operand is a signed 32bit integer */
2683 if (src_mode == mode_Is) {
2684 ia32_address_mode_t am;
2686 match_arguments(&am, src_block, NULL, op, match_am | match_try_am);
2687 if (am.op_type == ia32_AddrModeS) {
2688 ia32_address_t *addr = &am.addr;
2690 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base,
2691 addr->index, addr->mem);
2692 new_node = new_r_Proj(irg, block, fild, mode_vfp,
2695 set_am_attributes(fild, &am);
2696 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2698 fix_mem_proj(fild, &am);
2703 if(new_op == NULL) {
2704 new_op = be_transform_node(op);
2707 noreg = ia32_new_NoReg_gp(env_cg);
2708 nomem = new_NoMem();
2709 mode = get_irn_mode(op);
2711 /* first convert to 32 bit signed if necessary */
2712 src_bits = get_mode_size_bits(src_mode);
2713 if (src_bits == 8) {
2714 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2716 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2718 } else if (src_bits < 32) {
2719 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2721 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2725 assert(get_mode_size_bits(mode) == 32);
2728 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2731 set_ia32_use_frame(store);
2732 set_ia32_op_type(store, ia32_AddrModeD);
2733 set_ia32_ls_mode(store, mode_Iu);
2735 /* exception for 32bit unsigned, do a 64bit spill+load */
2736 if(!mode_is_signed(mode)) {
2739 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2741 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2742 get_irg_frame(irg), noreg, nomem,
2745 set_ia32_use_frame(zero_store);
2746 set_ia32_op_type(zero_store, ia32_AddrModeD);
2747 add_ia32_am_offs_int(zero_store, 4);
2748 set_ia32_ls_mode(zero_store, mode_Iu);
2753 store = new_rd_Sync(dbgi, irg, block, 2, in);
2754 store_mode = mode_Ls;
2756 store_mode = mode_Is;
2760 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2762 set_ia32_use_frame(fild);
2763 set_ia32_op_type(fild, ia32_AddrModeS);
2764 set_ia32_ls_mode(fild, store_mode);
2766 new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2772 * Create a conversion from one integer mode into another one
2774 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2775 dbg_info *dbgi, ir_node *block, ir_node *op,
2778 ir_graph *irg = current_ir_graph;
2779 int src_bits = get_mode_size_bits(src_mode);
2780 int tgt_bits = get_mode_size_bits(tgt_mode);
2781 ir_node *new_block = be_transform_node(block);
2783 ir_mode *smaller_mode;
2785 ia32_address_mode_t am;
2786 ia32_address_t *addr = &am.addr;
2788 if (src_bits < tgt_bits) {
2789 smaller_mode = src_mode;
2790 smaller_bits = src_bits;
2792 smaller_mode = tgt_mode;
2793 smaller_bits = tgt_bits;
2796 #ifdef DEBUG_libfirm
2798 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
2803 match_arguments(&am, block, NULL, op,
2804 match_8bit | match_16bit | match_8bit_am | match_16bit_am);
2805 if (smaller_bits == 8) {
2806 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2807 addr->index, addr->mem, am.new_op2,
2810 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2811 addr->index, addr->mem, am.new_op2,
2814 set_am_attributes(new_node, &am);
2815 /* match_arguments assume that out-mode = in-mode, this isn't true here
2817 set_ia32_ls_mode(new_node, smaller_mode);
2818 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2819 new_node = fix_mem_proj(new_node, &am);
2824 * Transforms a Conv node.
2826 * @return The created ia32 Conv node
2828 static ir_node *gen_Conv(ir_node *node) {
2829 ir_node *block = get_nodes_block(node);
2830 ir_node *new_block = be_transform_node(block);
2831 ir_node *op = get_Conv_op(node);
2832 ir_node *new_op = NULL;
2833 ir_graph *irg = current_ir_graph;
2834 dbg_info *dbgi = get_irn_dbg_info(node);
2835 ir_mode *src_mode = get_irn_mode(op);
2836 ir_mode *tgt_mode = get_irn_mode(node);
2837 int src_bits = get_mode_size_bits(src_mode);
2838 int tgt_bits = get_mode_size_bits(tgt_mode);
2839 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2840 ir_node *nomem = new_rd_NoMem(irg);
2841 ir_node *res = NULL;
2843 if (src_mode == mode_b) {
2844 assert(mode_is_int(tgt_mode));
2845 /* nothing to do, we already model bools as 0/1 ints */
2846 return be_transform_node(op);
2849 if (src_mode == tgt_mode) {
2850 if (get_Conv_strict(node)) {
2851 if (USE_SSE2(env_cg)) {
2852 /* when we are in SSE mode, we can kill all strict no-op conversion */
2853 return be_transform_node(op);
2856 /* this should be optimized already, but who knows... */
2857 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2858 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2859 return be_transform_node(op);
2863 if (mode_is_float(src_mode)) {
2864 new_op = be_transform_node(op);
2865 /* we convert from float ... */
2866 if (mode_is_float(tgt_mode)) {
2867 if(src_mode == mode_E && tgt_mode == mode_D
2868 && !get_Conv_strict(node)) {
2869 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2874 if (USE_SSE2(env_cg)) {
2875 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2876 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2878 set_ia32_ls_mode(res, tgt_mode);
2880 if(get_Conv_strict(node)) {
2881 res = gen_x87_strict_conv(tgt_mode, new_op);
2882 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2885 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2890 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2891 if (USE_SSE2(env_cg)) {
2892 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2894 set_ia32_ls_mode(res, src_mode);
2896 return gen_x87_fp_to_gp(node);
2900 /* we convert from int ... */
2901 if (mode_is_float(tgt_mode)) {
2903 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2904 if (USE_SSE2(env_cg)) {
2905 new_op = be_transform_node(op);
2906 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2908 set_ia32_ls_mode(res, tgt_mode);
2910 res = gen_x87_gp_to_fp(node, src_mode);
2911 if(get_Conv_strict(node)) {
2912 res = gen_x87_strict_conv(tgt_mode, res);
2913 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2914 ia32_get_old_node_name(env_cg, node));
2918 } else if(tgt_mode == mode_b) {
2919 /* mode_b lowering already took care that we only have 0/1 values */
2920 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2921 src_mode, tgt_mode));
2922 return be_transform_node(op);
2925 if (src_bits == tgt_bits) {
2926 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2927 src_mode, tgt_mode));
2928 return be_transform_node(op);
2931 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2939 static int check_immediate_constraint(long val, char immediate_constraint_type)
2941 switch (immediate_constraint_type) {
2945 return val >= 0 && val <= 32;
2947 return val >= 0 && val <= 63;
2949 return val >= -128 && val <= 127;
2951 return val == 0xff || val == 0xffff;
2953 return val >= 0 && val <= 3;
2955 return val >= 0 && val <= 255;
2957 return val >= 0 && val <= 127;
2961 panic("Invalid immediate constraint found");
2965 static ir_node *try_create_Immediate(ir_node *node,
2966 char immediate_constraint_type)
2969 tarval *offset = NULL;
2970 int offset_sign = 0;
2972 ir_entity *symconst_ent = NULL;
2973 int symconst_sign = 0;
2975 ir_node *cnst = NULL;
2976 ir_node *symconst = NULL;
2979 mode = get_irn_mode(node);
2980 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2984 if(is_Minus(node)) {
2986 node = get_Minus_op(node);
2989 if(is_Const(node)) {
2992 offset_sign = minus;
2993 } else if(is_SymConst(node)) {
2996 symconst_sign = minus;
2997 } else if(is_Add(node)) {
2998 ir_node *left = get_Add_left(node);
2999 ir_node *right = get_Add_right(node);
3000 if(is_Const(left) && is_SymConst(right)) {
3003 symconst_sign = minus;
3004 offset_sign = minus;
3005 } else if(is_SymConst(left) && is_Const(right)) {
3008 symconst_sign = minus;
3009 offset_sign = minus;
3011 } else if(is_Sub(node)) {
3012 ir_node *left = get_Sub_left(node);
3013 ir_node *right = get_Sub_right(node);
3014 if(is_Const(left) && is_SymConst(right)) {
3017 symconst_sign = !minus;
3018 offset_sign = minus;
3019 } else if(is_SymConst(left) && is_Const(right)) {
3022 symconst_sign = minus;
3023 offset_sign = !minus;
3030 offset = get_Const_tarval(cnst);
3031 if(tarval_is_long(offset)) {
3032 val = get_tarval_long(offset);
3034 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
3039 if(!check_immediate_constraint(val, immediate_constraint_type))
3042 if(symconst != NULL) {
3043 if(immediate_constraint_type != 0) {
3044 /* we need full 32bits for symconsts */
3048 /* unfortunately the assembler/linker doesn't support -symconst */
3052 if(get_SymConst_kind(symconst) != symconst_addr_ent)
3054 symconst_ent = get_SymConst_entity(symconst);
3056 if(cnst == NULL && symconst == NULL)
3059 if(offset_sign && offset != NULL) {
3060 offset = tarval_neg(offset);
3063 new_node = create_Immediate(symconst_ent, symconst_sign, val);
3068 static ir_node *create_immediate_or_transform(ir_node *node,
3069 char immediate_constraint_type)
3071 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
3072 if (new_node == NULL) {
3073 new_node = be_transform_node(node);
3078 static const arch_register_req_t no_register_req = {
3079 arch_register_req_type_none,
3080 NULL, /* regclass */
3081 NULL, /* limit bitset */
3082 { -1, -1 }, /* same pos */
3083 -1 /* different pos */
3087 * An assembler constraint.
3089 typedef struct constraint_t constraint_t;
3090 struct constraint_t {
3093 const arch_register_req_t **out_reqs;
3095 const arch_register_req_t *req;
3096 unsigned immediate_possible;
3097 char immediate_type;
3100 static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
3102 int immediate_possible = 0;
3103 char immediate_type = 0;
3104 unsigned limited = 0;
3105 const arch_register_class_t *cls = NULL;
3106 ir_graph *irg = current_ir_graph;
3107 struct obstack *obst = get_irg_obstack(irg);
3108 arch_register_req_t *req;
3109 unsigned *limited_ptr;
3113 /* TODO: replace all the asserts with nice error messages */
3116 /* a memory constraint: no need to do anything in backend about it
3117 * (the dependencies are already respected by the memory edge of
3119 constraint->req = &no_register_req;
3131 assert(cls == NULL ||
3132 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3133 cls = &ia32_reg_classes[CLASS_ia32_gp];
3134 limited |= 1 << REG_EAX;
3137 assert(cls == NULL ||
3138 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3139 cls = &ia32_reg_classes[CLASS_ia32_gp];
3140 limited |= 1 << REG_EBX;
3143 assert(cls == NULL ||
3144 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3145 cls = &ia32_reg_classes[CLASS_ia32_gp];
3146 limited |= 1 << REG_ECX;
3149 assert(cls == NULL ||
3150 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3151 cls = &ia32_reg_classes[CLASS_ia32_gp];
3152 limited |= 1 << REG_EDX;
3155 assert(cls == NULL ||
3156 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3157 cls = &ia32_reg_classes[CLASS_ia32_gp];
3158 limited |= 1 << REG_EDI;
3161 assert(cls == NULL ||
3162 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3163 cls = &ia32_reg_classes[CLASS_ia32_gp];
3164 limited |= 1 << REG_ESI;
3167 case 'q': /* q means lower part of the regs only, this makes no
3168 * difference to Q for us (we only assigne whole registers) */
3169 assert(cls == NULL ||
3170 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3171 cls = &ia32_reg_classes[CLASS_ia32_gp];
3172 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3176 assert(cls == NULL ||
3177 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3178 cls = &ia32_reg_classes[CLASS_ia32_gp];
3179 limited |= 1 << REG_EAX | 1 << REG_EDX;
3182 assert(cls == NULL ||
3183 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3184 cls = &ia32_reg_classes[CLASS_ia32_gp];
3185 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3186 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3193 assert(cls == NULL);
3194 cls = &ia32_reg_classes[CLASS_ia32_gp];
3200 /* TODO: mark values so the x87 simulator knows about t and u */
3201 assert(cls == NULL);
3202 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3207 assert(cls == NULL);
3208 /* TODO: check that sse2 is supported */
3209 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3219 assert(!immediate_possible);
3220 immediate_possible = 1;
3221 immediate_type = *c;
3225 assert(!immediate_possible);
3226 immediate_possible = 1;
3230 assert(!immediate_possible && cls == NULL);
3231 immediate_possible = 1;
3232 cls = &ia32_reg_classes[CLASS_ia32_gp];
3245 assert(constraint->is_in && "can only specify same constraint "
3248 sscanf(c, "%d%n", &same_as, &p);
3256 /* memory constraint no need to do anything in backend about it
3257 * (the dependencies are already respected by the memory edge of
3259 constraint->req = &no_register_req;
3262 case 'E': /* no float consts yet */
3263 case 'F': /* no float consts yet */
3264 case 's': /* makes no sense on x86 */
3265 case 'X': /* we can't support that in firm */
3268 case '<': /* no autodecrement on x86 */
3269 case '>': /* no autoincrement on x86 */
3270 case 'C': /* sse constant not supported yet */
3271 case 'G': /* 80387 constant not supported yet */
3272 case 'y': /* we don't support mmx registers yet */
3273 case 'Z': /* not available in 32 bit mode */
3274 case 'e': /* not available in 32 bit mode */
3275 panic("unsupported asm constraint '%c' found in (%+F)",
3276 *c, current_ir_graph);
3279 panic("unknown asm constraint '%c' found in (%+F)", *c,
3287 const arch_register_req_t *other_constr;
3289 assert(cls == NULL && "same as and register constraint not supported");
3290 assert(!immediate_possible && "same as and immediate constraint not "
3292 assert(same_as < constraint->n_outs && "wrong constraint number in "
3293 "same_as constraint");
3295 other_constr = constraint->out_reqs[same_as];
3297 req = obstack_alloc(obst, sizeof(req[0]));
3298 req->cls = other_constr->cls;
3299 req->type = arch_register_req_type_should_be_same;
3300 req->limited = NULL;
3301 req->other_same[0] = pos;
3302 req->other_same[1] = -1;
3303 req->other_different = -1;
3305 /* switch constraints. This is because in firm we have same_as
3306 * constraints on the output constraints while in the gcc asm syntax
3307 * they are specified on the input constraints */
3308 constraint->req = other_constr;
3309 constraint->out_reqs[same_as] = req;
3310 constraint->immediate_possible = 0;
3314 if(immediate_possible && cls == NULL) {
3315 cls = &ia32_reg_classes[CLASS_ia32_gp];
3317 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3318 assert(cls != NULL);
3320 if(immediate_possible) {
3321 assert(constraint->is_in
3322 && "immediate make no sense for output constraints");
3324 /* todo: check types (no float input on 'r' constrained in and such... */
3327 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3328 limited_ptr = (unsigned*) (req+1);
3330 req = obstack_alloc(obst, sizeof(req[0]));
3332 memset(req, 0, sizeof(req[0]));
3335 req->type = arch_register_req_type_limited;
3336 *limited_ptr = limited;
3337 req->limited = limited_ptr;
3339 req->type = arch_register_req_type_normal;
3343 constraint->req = req;
3344 constraint->immediate_possible = immediate_possible;
3345 constraint->immediate_type = immediate_type;
3348 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3355 panic("Clobbers not supported yet");
3358 static int is_memory_op(const ir_asm_constraint *constraint)
3360 ident *id = constraint->constraint;
3361 const char *str = get_id_str(id);
3364 for(c = str; *c != '\0'; ++c) {
3373 * generates code for a ASM node
3375 static ir_node *gen_ASM(ir_node *node)
3378 ir_graph *irg = current_ir_graph;
3379 ir_node *block = get_nodes_block(node);
3380 ir_node *new_block = be_transform_node(block);
3381 dbg_info *dbgi = get_irn_dbg_info(node);
3385 int n_out_constraints;
3387 const arch_register_req_t **out_reg_reqs;
3388 const arch_register_req_t **in_reg_reqs;
3389 ia32_asm_reg_t *register_map;
3390 unsigned reg_map_size = 0;
3391 struct obstack *obst;
3392 const ir_asm_constraint *in_constraints;
3393 const ir_asm_constraint *out_constraints;
3395 constraint_t parsed_constraint;
3397 arity = get_irn_arity(node);
3398 in = alloca(arity * sizeof(in[0]));
3399 memset(in, 0, arity * sizeof(in[0]));
3401 n_out_constraints = get_ASM_n_output_constraints(node);
3402 n_clobbers = get_ASM_n_clobbers(node);
3403 out_arity = n_out_constraints + n_clobbers;
3405 in_constraints = get_ASM_input_constraints(node);
3406 out_constraints = get_ASM_output_constraints(node);
3407 clobbers = get_ASM_clobbers(node);
3409 /* construct output constraints */
3410 obst = get_irg_obstack(irg);
3411 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
3412 parsed_constraint.out_reqs = out_reg_reqs;
3413 parsed_constraint.n_outs = n_out_constraints;
3414 parsed_constraint.is_in = 0;
3416 for(i = 0; i < out_arity; ++i) {
3419 if(i < n_out_constraints) {
3420 const ir_asm_constraint *constraint = &out_constraints[i];
3421 c = get_id_str(constraint->constraint);
3422 parse_asm_constraint(i, &parsed_constraint, c);
3424 if(constraint->pos > reg_map_size)
3425 reg_map_size = constraint->pos;
3427 ident *glob_id = clobbers [i - n_out_constraints];
3428 c = get_id_str(glob_id);
3429 parse_clobber(node, i, &parsed_constraint, c);
3432 out_reg_reqs[i] = parsed_constraint.req;
3435 /* construct input constraints */
3436 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
3437 parsed_constraint.is_in = 1;
3438 for(i = 0; i < arity; ++i) {
3439 const ir_asm_constraint *constraint = &in_constraints[i];
3440 ident *constr_id = constraint->constraint;
3441 const char *c = get_id_str(constr_id);
3443 parse_asm_constraint(i, &parsed_constraint, c);
3444 in_reg_reqs[i] = parsed_constraint.req;
3446 if(constraint->pos > reg_map_size)
3447 reg_map_size = constraint->pos;
3449 if(parsed_constraint.immediate_possible) {
3450 ir_node *pred = get_irn_n(node, i);
3451 char imm_type = parsed_constraint.immediate_type;
3452 ir_node *immediate = try_create_Immediate(pred, imm_type);
3454 if(immediate != NULL) {
3461 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
3462 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
3464 for(i = 0; i < n_out_constraints; ++i) {
3465 const ir_asm_constraint *constraint = &out_constraints[i];
3466 unsigned pos = constraint->pos;
3468 assert(pos < reg_map_size);
3469 register_map[pos].use_input = 0;
3470 register_map[pos].valid = 1;
3471 register_map[pos].memory = is_memory_op(constraint);
3472 register_map[pos].inout_pos = i;
3473 register_map[pos].mode = constraint->mode;
3476 /* transform inputs */
3477 for(i = 0; i < arity; ++i) {
3478 const ir_asm_constraint *constraint = &in_constraints[i];
3479 unsigned pos = constraint->pos;
3480 ir_node *pred = get_irn_n(node, i);
3481 ir_node *transformed;
3483 assert(pos < reg_map_size);
3484 register_map[pos].use_input = 1;
3485 register_map[pos].valid = 1;
3486 register_map[pos].memory = is_memory_op(constraint);
3487 register_map[pos].inout_pos = i;
3488 register_map[pos].mode = constraint->mode;
3493 transformed = be_transform_node(pred);
3494 in[i] = transformed;
3497 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
3498 get_ASM_text(node), register_map);
3500 set_ia32_out_req_all(new_node, out_reg_reqs);
3501 set_ia32_in_req_all(new_node, in_reg_reqs);
3503 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3508 /********************************************
3511 * | |__ ___ _ __ ___ __| | ___ ___
3512 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3513 * | |_) | __/ | | | (_) | (_| | __/\__ \
3514 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3516 ********************************************/
3519 * Transforms a FrameAddr into an ia32 Add.
3521 static ir_node *gen_be_FrameAddr(ir_node *node) {
3522 ir_node *block = be_transform_node(get_nodes_block(node));
3523 ir_node *op = be_get_FrameAddr_frame(node);
3524 ir_node *new_op = be_transform_node(op);
3525 ir_graph *irg = current_ir_graph;
3526 dbg_info *dbgi = get_irn_dbg_info(node);
3527 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3530 new_node = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3531 set_ia32_frame_ent(new_node, arch_get_frame_entity(env_cg->arch_env, node));
3532 set_ia32_use_frame(new_node);
3534 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3540 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3542 static ir_node *gen_be_Return(ir_node *node) {
3543 ir_graph *irg = current_ir_graph;
3544 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3545 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3546 ir_entity *ent = get_irg_entity(irg);
3547 ir_type *tp = get_entity_type(ent);
3552 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3553 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3556 int pn_ret_val, pn_ret_mem, arity, i;
3558 assert(ret_val != NULL);
3559 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3560 return be_duplicate_node(node);
3563 res_type = get_method_res_type(tp, 0);
3565 if (! is_Primitive_type(res_type)) {
3566 return be_duplicate_node(node);
3569 mode = get_type_mode(res_type);
3570 if (! mode_is_float(mode)) {
3571 return be_duplicate_node(node);
3574 assert(get_method_n_ress(tp) == 1);
3576 pn_ret_val = get_Proj_proj(ret_val);
3577 pn_ret_mem = get_Proj_proj(ret_mem);
3579 /* get the Barrier */
3580 barrier = get_Proj_pred(ret_val);
3582 /* get result input of the Barrier */
3583 ret_val = get_irn_n(barrier, pn_ret_val);
3584 new_ret_val = be_transform_node(ret_val);
3586 /* get memory input of the Barrier */
3587 ret_mem = get_irn_n(barrier, pn_ret_mem);
3588 new_ret_mem = be_transform_node(ret_mem);
3590 frame = get_irg_frame(irg);
3592 dbgi = get_irn_dbg_info(barrier);
3593 block = be_transform_node(get_nodes_block(barrier));
3595 noreg = ia32_new_NoReg_gp(env_cg);
3597 /* store xmm0 onto stack */
3598 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3599 new_ret_mem, new_ret_val);
3600 set_ia32_ls_mode(sse_store, mode);
3601 set_ia32_op_type(sse_store, ia32_AddrModeD);
3602 set_ia32_use_frame(sse_store);
3604 /* load into x87 register */
3605 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3606 set_ia32_op_type(fld, ia32_AddrModeS);
3607 set_ia32_use_frame(fld);
3609 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3610 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3612 /* create a new barrier */
3613 arity = get_irn_arity(barrier);
3614 in = alloca(arity * sizeof(in[0]));
3615 for (i = 0; i < arity; ++i) {
3618 if (i == pn_ret_val) {
3620 } else if (i == pn_ret_mem) {
3623 ir_node *in = get_irn_n(barrier, i);
3624 new_in = be_transform_node(in);
3629 new_barrier = new_ir_node(dbgi, irg, block,
3630 get_irn_op(barrier), get_irn_mode(barrier),
3632 copy_node_attr(barrier, new_barrier);
3633 be_duplicate_deps(barrier, new_barrier);
3634 be_set_transformed_node(barrier, new_barrier);
3635 mark_irn_visited(barrier);
3637 /* transform normally */
3638 return be_duplicate_node(node);
3642 * Transform a be_AddSP into an ia32_SubSP.
3644 static ir_node *gen_be_AddSP(ir_node *node)
3646 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3647 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3649 return gen_binop(node, sp, sz, new_rd_ia32_SubSP, match_am);
3653 * Transform a be_SubSP into an ia32_AddSP
3655 static ir_node *gen_be_SubSP(ir_node *node)
3657 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3658 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3660 return gen_binop(node, sp, sz, new_rd_ia32_AddSP, match_am);
3664 * This function just sets the register for the Unknown node
3665 * as this is not done during register allocation because Unknown
3666 * is an "ignore" node.
3668 static ir_node *gen_Unknown(ir_node *node) {
3669 ir_mode *mode = get_irn_mode(node);
3671 if (mode_is_float(mode)) {
3672 if (USE_SSE2(env_cg)) {
3673 return ia32_new_Unknown_xmm(env_cg);
3675 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3676 ir_graph *irg = current_ir_graph;
3677 dbg_info *dbgi = get_irn_dbg_info(node);
3678 ir_node *block = get_irg_start_block(irg);
3679 return new_rd_ia32_vfldz(dbgi, irg, block);
3681 } else if (mode_needs_gp_reg(mode)) {
3682 return ia32_new_Unknown_gp(env_cg);
3684 panic("unsupported Unknown-Mode");
3690 * Change some phi modes
3692 static ir_node *gen_Phi(ir_node *node) {
3693 ir_node *block = be_transform_node(get_nodes_block(node));
3694 ir_graph *irg = current_ir_graph;
3695 dbg_info *dbgi = get_irn_dbg_info(node);
3696 ir_mode *mode = get_irn_mode(node);
3699 if(mode_needs_gp_reg(mode)) {
3700 /* we shouldn't have any 64bit stuff around anymore */
3701 assert(get_mode_size_bits(mode) <= 32);
3702 /* all integer operations are on 32bit registers now */
3704 } else if(mode_is_float(mode)) {
3705 if (USE_SSE2(env_cg)) {
3712 /* phi nodes allow loops, so we use the old arguments for now
3713 * and fix this later */
3714 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3715 get_irn_in(node) + 1);
3716 copy_node_attr(node, phi);
3717 be_duplicate_deps(node, phi);
3719 be_set_transformed_node(node, phi);
3720 be_enqueue_preds(node);
3728 static ir_node *gen_IJmp(ir_node *node)
3730 ir_node *block = get_nodes_block(node);
3731 ir_node *new_block = be_transform_node(block);
3732 ir_graph *irg = current_ir_graph;
3733 dbg_info *dbgi = get_irn_dbg_info(node);
3734 ir_node *op = get_IJmp_target(node);
3736 ia32_address_mode_t am;
3737 ia32_address_t *addr = &am.addr;
3739 assert(get_irn_mode(op) == mode_P);
3741 match_arguments(&am, block, NULL, op,
3742 match_am | match_8bit_am | match_16bit_am |
3743 match_immediate | match_8bit | match_16bit);
3745 new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index,
3746 addr->mem, am.new_op2);
3747 set_am_attributes(new_node, &am);
3748 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3750 new_node = fix_mem_proj(new_node, &am);
3756 /**********************************************************************
3759 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3760 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3761 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3762 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3764 **********************************************************************/
3766 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3768 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3771 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3772 ir_node *val, ir_node *mem);
3775 * Transforms a lowered Load into a "real" one.
3777 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3779 ir_node *block = be_transform_node(get_nodes_block(node));
3780 ir_node *ptr = get_irn_n(node, 0);
3781 ir_node *new_ptr = be_transform_node(ptr);
3782 ir_node *mem = get_irn_n(node, 1);
3783 ir_node *new_mem = be_transform_node(mem);
3784 ir_graph *irg = current_ir_graph;
3785 dbg_info *dbgi = get_irn_dbg_info(node);
3786 ir_mode *mode = get_ia32_ls_mode(node);
3787 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3790 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3792 set_ia32_op_type(new_op, ia32_AddrModeS);
3793 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3794 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3795 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3796 if (is_ia32_am_sc_sign(node))
3797 set_ia32_am_sc_sign(new_op);
3798 set_ia32_ls_mode(new_op, mode);
3799 if (is_ia32_use_frame(node)) {
3800 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3801 set_ia32_use_frame(new_op);
3804 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3810 * Transforms a lowered Store into a "real" one.
3812 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3814 ir_node *block = be_transform_node(get_nodes_block(node));
3815 ir_node *ptr = get_irn_n(node, 0);
3816 ir_node *new_ptr = be_transform_node(ptr);
3817 ir_node *val = get_irn_n(node, 1);
3818 ir_node *new_val = be_transform_node(val);
3819 ir_node *mem = get_irn_n(node, 2);
3820 ir_node *new_mem = be_transform_node(mem);
3821 ir_graph *irg = current_ir_graph;
3822 dbg_info *dbgi = get_irn_dbg_info(node);
3823 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3824 ir_mode *mode = get_ia32_ls_mode(node);
3828 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3830 am_offs = get_ia32_am_offs_int(node);
3831 add_ia32_am_offs_int(new_op, am_offs);
3833 set_ia32_op_type(new_op, ia32_AddrModeD);
3834 set_ia32_ls_mode(new_op, mode);
3835 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3836 set_ia32_use_frame(new_op);
3838 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3843 static ir_node *gen_ia32_l_ShlDep(ir_node *node)
3845 ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_left);
3846 ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_right);
3848 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
3849 match_immediate | match_mode_neutral);
3852 static ir_node *gen_ia32_l_ShrDep(ir_node *node)
3854 ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_left);
3855 ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_right);
3856 return gen_shift_binop(node, left, right, new_rd_ia32_Shr,
3860 static ir_node *gen_ia32_l_SarDep(ir_node *node)
3862 ir_node *left = get_irn_n(node, n_ia32_l_SarDep_left);
3863 ir_node *right = get_irn_n(node, n_ia32_l_SarDep_right);
3864 return gen_shift_binop(node, left, right, new_rd_ia32_Sar,
3868 static ir_node *gen_ia32_l_Add(ir_node *node) {
3869 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3870 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3871 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add,
3872 match_commutative | match_am | match_immediate |
3873 match_mode_neutral);
3875 if(is_Proj(lowered)) {
3876 lowered = get_Proj_pred(lowered);
3878 assert(is_ia32_Add(lowered));
3879 set_irn_mode(lowered, mode_T);
3885 static ir_node *gen_ia32_l_Adc(ir_node *node)
3887 return gen_binop_flags(node, new_rd_ia32_Adc,
3888 match_commutative | match_am | match_immediate |
3889 match_mode_neutral);
3893 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3895 * @param node The node to transform
3896 * @return the created ia32 vfild node
3898 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3899 return gen_lowered_Load(node, new_rd_ia32_vfild);
3903 * Transforms an ia32_l_Load into a "real" ia32_Load node
3905 * @param node The node to transform
3906 * @return the created ia32 Load node
3908 static ir_node *gen_ia32_l_Load(ir_node *node) {
3909 return gen_lowered_Load(node, new_rd_ia32_Load);
3913 * Transforms an ia32_l_Store into a "real" ia32_Store node
3915 * @param node The node to transform
3916 * @return the created ia32 Store node
3918 static ir_node *gen_ia32_l_Store(ir_node *node) {
3919 return gen_lowered_Store(node, new_rd_ia32_Store);
3923 * Transforms a l_vfist into a "real" vfist node.
3925 * @param node The node to transform
3926 * @return the created ia32 vfist node
3928 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3929 ir_node *block = be_transform_node(get_nodes_block(node));
3930 ir_node *ptr = get_irn_n(node, 0);
3931 ir_node *new_ptr = be_transform_node(ptr);
3932 ir_node *val = get_irn_n(node, 1);
3933 ir_node *new_val = be_transform_node(val);
3934 ir_node *mem = get_irn_n(node, 2);
3935 ir_node *new_mem = be_transform_node(mem);
3936 ir_graph *irg = current_ir_graph;
3937 dbg_info *dbgi = get_irn_dbg_info(node);
3938 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3939 ir_mode *mode = get_ia32_ls_mode(node);
3940 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3944 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3945 new_val, trunc_mode);
3947 am_offs = get_ia32_am_offs_int(node);
3948 add_ia32_am_offs_int(new_op, am_offs);
3950 set_ia32_op_type(new_op, ia32_AddrModeD);
3951 set_ia32_ls_mode(new_op, mode);
3952 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3953 set_ia32_use_frame(new_op);
3955 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3961 * Transforms a l_MulS into a "real" MulS node.
3963 * @return the created ia32 Mul node
3965 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3966 ir_node *left = get_binop_left(node);
3967 ir_node *right = get_binop_right(node);
3969 return gen_binop(node, left, right, new_rd_ia32_Mul,
3970 match_commutative | match_am | match_mode_neutral);
3974 * Transforms a l_IMulS into a "real" IMul1OPS node.
3976 * @return the created ia32 IMul1OP node
3978 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3979 ir_node *left = get_binop_left(node);
3980 ir_node *right = get_binop_right(node);
3982 return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
3983 match_commutative | match_am | match_mode_neutral);
3986 static ir_node *gen_ia32_l_Sub(ir_node *node) {
3987 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
3988 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
3989 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub,
3990 match_am | match_immediate | match_mode_neutral);
3992 if(is_Proj(lowered)) {
3993 lowered = get_Proj_pred(lowered);
3995 assert(is_ia32_Sub(lowered));
3996 set_irn_mode(lowered, mode_T);
4002 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
4003 return gen_binop_flags(node, new_rd_ia32_Sbb,
4004 match_am | match_immediate | match_mode_neutral);
4008 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
4009 * op1 - target to be shifted
4010 * op2 - contains bits to be shifted into target
4012 * Only op3 can be an immediate.
4014 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
4015 ir_node *low, ir_node *count)
4017 ir_node *block = get_nodes_block(node);
4018 ir_node *new_block = be_transform_node(block);
4019 ir_graph *irg = current_ir_graph;
4020 dbg_info *dbgi = get_irn_dbg_info(node);
4021 ir_node *new_high = be_transform_node(high);
4022 ir_node *new_low = be_transform_node(low);
4026 /* the shift amount can be any mode that is bigger than 5 bits, since all
4027 * other bits are ignored anyway */
4028 while (is_Conv(count) && get_irn_n_edges(count) == 1) {
4029 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
4030 count = get_Conv_op(count);
4032 new_count = create_immediate_or_transform(count, 0);
4034 if (is_ia32_l_ShlD(node)) {
4035 new_node = new_rd_ia32_ShlD(dbgi, irg, new_block, new_high, new_low,
4038 new_node = new_rd_ia32_ShrD(dbgi, irg, new_block, new_high, new_low,
4041 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
4046 static ir_node *gen_ia32_l_ShlD(ir_node *node)
4048 ir_node *high = get_irn_n(node, n_ia32_l_ShlD_high);
4049 ir_node *low = get_irn_n(node, n_ia32_l_ShlD_low);
4050 ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
4051 return gen_lowered_64bit_shifts(node, high, low, count);
4054 static ir_node *gen_ia32_l_ShrD(ir_node *node)
4056 ir_node *high = get_irn_n(node, n_ia32_l_ShrD_high);
4057 ir_node *low = get_irn_n(node, n_ia32_l_ShrD_low);
4058 ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
4059 return gen_lowered_64bit_shifts(node, high, low, count);
4063 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
4065 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
4066 ir_node *block = be_transform_node(get_nodes_block(node));
4067 ir_node *val = get_irn_n(node, 1);
4068 ir_node *new_val = be_transform_node(val);
4069 ia32_code_gen_t *cg = env_cg;
4070 ir_node *res = NULL;
4071 ir_graph *irg = current_ir_graph;
4073 ir_node *noreg, *new_ptr, *new_mem;
4080 mem = get_irn_n(node, 2);
4081 new_mem = be_transform_node(mem);
4082 ptr = get_irn_n(node, 0);
4083 new_ptr = be_transform_node(ptr);
4084 noreg = ia32_new_NoReg_gp(cg);
4085 dbgi = get_irn_dbg_info(node);
4087 /* Store x87 -> MEM */
4088 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
4089 get_ia32_ls_mode(node));
4090 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4091 set_ia32_use_frame(res);
4092 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
4093 set_ia32_op_type(res, ia32_AddrModeD);
4095 /* Load MEM -> SSE */
4096 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
4097 get_ia32_ls_mode(node));
4098 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4099 set_ia32_use_frame(res);
4100 set_ia32_op_type(res, ia32_AddrModeS);
4101 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
4107 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
4109 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
4110 ir_node *block = be_transform_node(get_nodes_block(node));
4111 ir_node *val = get_irn_n(node, 1);
4112 ir_node *new_val = be_transform_node(val);
4113 ia32_code_gen_t *cg = env_cg;
4114 ir_graph *irg = current_ir_graph;
4115 ir_node *res = NULL;
4116 ir_entity *fent = get_ia32_frame_ent(node);
4117 ir_mode *lsmode = get_ia32_ls_mode(node);
4119 ir_node *noreg, *new_ptr, *new_mem;
4123 if (! USE_SSE2(cg)) {
4124 /* SSE unit is not used -> skip this node. */
4128 ptr = get_irn_n(node, 0);
4129 new_ptr = be_transform_node(ptr);
4130 mem = get_irn_n(node, 2);
4131 new_mem = be_transform_node(mem);
4132 noreg = ia32_new_NoReg_gp(cg);
4133 dbgi = get_irn_dbg_info(node);
4135 /* Store SSE -> MEM */
4136 if (is_ia32_xLoad(skip_Proj(new_val))) {
4137 ir_node *ld = skip_Proj(new_val);
4139 /* we can vfld the value directly into the fpu */
4140 fent = get_ia32_frame_ent(ld);
4141 ptr = get_irn_n(ld, 0);
4142 offs = get_ia32_am_offs_int(ld);
4144 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
4146 set_ia32_frame_ent(res, fent);
4147 set_ia32_use_frame(res);
4148 set_ia32_ls_mode(res, lsmode);
4149 set_ia32_op_type(res, ia32_AddrModeD);
4153 /* Load MEM -> x87 */
4154 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4155 set_ia32_frame_ent(res, fent);
4156 set_ia32_use_frame(res);
4157 add_ia32_am_offs_int(res, offs);
4158 set_ia32_op_type(res, ia32_AddrModeS);
4159 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4164 /*********************************************************
4167 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
4168 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
4169 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4170 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4172 *********************************************************/
4175 * the BAD transformer.
4177 static ir_node *bad_transform(ir_node *node) {
4178 panic("No transform function for %+F available.\n", node);
4183 * Transform the Projs of an AddSP.
4185 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4186 ir_node *block = be_transform_node(get_nodes_block(node));
4187 ir_node *pred = get_Proj_pred(node);
4188 ir_node *new_pred = be_transform_node(pred);
4189 ir_graph *irg = current_ir_graph;
4190 dbg_info *dbgi = get_irn_dbg_info(node);
4191 long proj = get_Proj_proj(node);
4193 if (proj == pn_be_AddSP_sp) {
4194 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4195 pn_ia32_SubSP_stack);
4196 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4198 } else if(proj == pn_be_AddSP_res) {
4199 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4200 pn_ia32_SubSP_addr);
4201 } else if (proj == pn_be_AddSP_M) {
4202 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4206 return new_rd_Unknown(irg, get_irn_mode(node));
4210 * Transform the Projs of a SubSP.
4212 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4213 ir_node *block = be_transform_node(get_nodes_block(node));
4214 ir_node *pred = get_Proj_pred(node);
4215 ir_node *new_pred = be_transform_node(pred);
4216 ir_graph *irg = current_ir_graph;
4217 dbg_info *dbgi = get_irn_dbg_info(node);
4218 long proj = get_Proj_proj(node);
4220 if (proj == pn_be_SubSP_sp) {
4221 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4222 pn_ia32_AddSP_stack);
4223 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4225 } else if (proj == pn_be_SubSP_M) {
4226 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4230 return new_rd_Unknown(irg, get_irn_mode(node));
4234 * Transform and renumber the Projs from a Load.
4236 static ir_node *gen_Proj_Load(ir_node *node) {
4238 ir_node *block = be_transform_node(get_nodes_block(node));
4239 ir_node *pred = get_Proj_pred(node);
4240 ir_graph *irg = current_ir_graph;
4241 dbg_info *dbgi = get_irn_dbg_info(node);
4242 long proj = get_Proj_proj(node);
4245 /* loads might be part of source address mode matches, so we don't
4246 transform the ProjMs yet (with the exception of loads whose result is
4249 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4252 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4254 /* this is needed, because sometimes we have loops that are only
4255 reachable through the ProjM */
4256 be_enqueue_preds(node);
4257 /* do it in 2 steps, to silence firm verifier */
4258 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4259 set_Proj_proj(res, pn_ia32_Load_M);
4263 /* renumber the proj */
4264 new_pred = be_transform_node(pred);
4265 if (is_ia32_Load(new_pred)) {
4266 if (proj == pn_Load_res) {
4267 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4269 } else if (proj == pn_Load_M) {
4270 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4273 } else if(is_ia32_Conv_I2I(new_pred)
4274 || is_ia32_Conv_I2I8Bit(new_pred)) {
4275 set_irn_mode(new_pred, mode_T);
4276 if (proj == pn_Load_res) {
4277 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4278 } else if (proj == pn_Load_M) {
4279 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4281 } else if (is_ia32_xLoad(new_pred)) {
4282 if (proj == pn_Load_res) {
4283 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4285 } else if (proj == pn_Load_M) {
4286 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4289 } else if (is_ia32_vfld(new_pred)) {
4290 if (proj == pn_Load_res) {
4291 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4293 } else if (proj == pn_Load_M) {
4294 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4298 /* can happen for ProJMs when source address mode happened for the
4301 /* however it should not be the result proj, as that would mean the
4302 load had multiple users and should not have been used for
4304 if(proj != pn_Load_M) {
4305 panic("internal error: transformed node not a Load");
4307 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4311 return new_rd_Unknown(irg, get_irn_mode(node));
4315 * Transform and renumber the Projs from a DivMod like instruction.
4317 static ir_node *gen_Proj_DivMod(ir_node *node) {
4318 ir_node *block = be_transform_node(get_nodes_block(node));
4319 ir_node *pred = get_Proj_pred(node);
4320 ir_node *new_pred = be_transform_node(pred);
4321 ir_graph *irg = current_ir_graph;
4322 dbg_info *dbgi = get_irn_dbg_info(node);
4323 ir_mode *mode = get_irn_mode(node);
4324 long proj = get_Proj_proj(node);
4326 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4328 switch (get_irn_opcode(pred)) {
4332 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4334 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4342 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4344 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4352 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4353 case pn_DivMod_res_div:
4354 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4355 case pn_DivMod_res_mod:
4356 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4366 return new_rd_Unknown(irg, mode);
4370 * Transform and renumber the Projs from a CopyB.
4372 static ir_node *gen_Proj_CopyB(ir_node *node) {
4373 ir_node *block = be_transform_node(get_nodes_block(node));
4374 ir_node *pred = get_Proj_pred(node);
4375 ir_node *new_pred = be_transform_node(pred);
4376 ir_graph *irg = current_ir_graph;
4377 dbg_info *dbgi = get_irn_dbg_info(node);
4378 ir_mode *mode = get_irn_mode(node);
4379 long proj = get_Proj_proj(node);
4382 case pn_CopyB_M_regular:
4383 if (is_ia32_CopyB_i(new_pred)) {
4384 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4385 } else if (is_ia32_CopyB(new_pred)) {
4386 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4394 return new_rd_Unknown(irg, mode);
4398 * Transform and renumber the Projs from a Quot.
4400 static ir_node *gen_Proj_Quot(ir_node *node) {
4401 ir_node *block = be_transform_node(get_nodes_block(node));
4402 ir_node *pred = get_Proj_pred(node);
4403 ir_node *new_pred = be_transform_node(pred);
4404 ir_graph *irg = current_ir_graph;
4405 dbg_info *dbgi = get_irn_dbg_info(node);
4406 ir_mode *mode = get_irn_mode(node);
4407 long proj = get_Proj_proj(node);
4411 if (is_ia32_xDiv(new_pred)) {
4412 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4413 } else if (is_ia32_vfdiv(new_pred)) {
4414 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4418 if (is_ia32_xDiv(new_pred)) {
4419 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4420 } else if (is_ia32_vfdiv(new_pred)) {
4421 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4429 return new_rd_Unknown(irg, mode);
4433 * Transform the Thread Local Storage Proj.
4435 static ir_node *gen_Proj_tls(ir_node *node) {
4436 ir_node *block = be_transform_node(get_nodes_block(node));
4437 ir_graph *irg = current_ir_graph;
4438 dbg_info *dbgi = NULL;
4439 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4444 static ir_node *gen_be_Call(ir_node *node) {
4445 ir_node *res = be_duplicate_node(node);
4446 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4451 static ir_node *gen_be_IncSP(ir_node *node) {
4452 ir_node *res = be_duplicate_node(node);
4453 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4459 * Transform the Projs from a be_Call.
4461 static ir_node *gen_Proj_be_Call(ir_node *node) {
4462 ir_node *block = be_transform_node(get_nodes_block(node));
4463 ir_node *call = get_Proj_pred(node);
4464 ir_node *new_call = be_transform_node(call);
4465 ir_graph *irg = current_ir_graph;
4466 dbg_info *dbgi = get_irn_dbg_info(node);
4467 ir_type *method_type = be_Call_get_type(call);
4468 int n_res = get_method_n_ress(method_type);
4469 long proj = get_Proj_proj(node);
4470 ir_mode *mode = get_irn_mode(node);
4472 const arch_register_class_t *cls;
4474 /* The following is kinda tricky: If we're using SSE, then we have to
4475 * move the result value of the call in floating point registers to an
4476 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4477 * after the call, we have to make sure to correctly make the
4478 * MemProj and the result Proj use these 2 nodes
4480 if (proj == pn_be_Call_M_regular) {
4481 // get new node for result, are we doing the sse load/store hack?
4482 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4483 ir_node *call_res_new;
4484 ir_node *call_res_pred = NULL;
4486 if (call_res != NULL) {
4487 call_res_new = be_transform_node(call_res);
4488 call_res_pred = get_Proj_pred(call_res_new);
4491 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4492 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4493 pn_be_Call_M_regular);
4495 assert(is_ia32_xLoad(call_res_pred));
4496 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4500 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4501 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4502 && USE_SSE2(env_cg)) {
4504 ir_node *frame = get_irg_frame(irg);
4505 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4507 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4510 /* in case there is no memory output: create one to serialize the copy
4512 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4513 pn_be_Call_M_regular);
4514 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4515 pn_be_Call_first_res);
4517 /* store st(0) onto stack */
4518 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4520 set_ia32_op_type(fstp, ia32_AddrModeD);
4521 set_ia32_use_frame(fstp);
4523 /* load into SSE register */
4524 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4526 set_ia32_op_type(sse_load, ia32_AddrModeS);
4527 set_ia32_use_frame(sse_load);
4529 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4535 /* transform call modes */
4536 if (mode_is_data(mode)) {
4537 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4541 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4545 * Transform the Projs from a Cmp.
4547 static ir_node *gen_Proj_Cmp(ir_node *node)
4549 /* normally Cmps are processed when looking at Cond nodes, but this case
4550 * can happen in complicated Psi conditions */
4551 dbg_info *dbgi = get_irn_dbg_info(node);
4552 ir_node *block = get_nodes_block(node);
4553 ir_node *new_block = be_transform_node(block);
4554 ir_node *cmp = get_Proj_pred(node);
4555 ir_node *new_cmp = be_transform_node(cmp);
4556 long pnc = get_Proj_proj(node);
4559 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node, 0);
4565 * Transform and potentially renumber Proj nodes.
4567 static ir_node *gen_Proj(ir_node *node) {
4568 ir_graph *irg = current_ir_graph;
4569 dbg_info *dbgi = get_irn_dbg_info(node);
4570 ir_node *pred = get_Proj_pred(node);
4571 long proj = get_Proj_proj(node);
4573 if (is_Store(pred)) {
4574 if (proj == pn_Store_M) {
4575 return be_transform_node(pred);
4578 return new_r_Bad(irg);
4580 } else if (is_Load(pred)) {
4581 return gen_Proj_Load(node);
4582 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4583 return gen_Proj_DivMod(node);
4584 } else if (is_CopyB(pred)) {
4585 return gen_Proj_CopyB(node);
4586 } else if (is_Quot(pred)) {
4587 return gen_Proj_Quot(node);
4588 } else if (be_is_SubSP(pred)) {
4589 return gen_Proj_be_SubSP(node);
4590 } else if (be_is_AddSP(pred)) {
4591 return gen_Proj_be_AddSP(node);
4592 } else if (be_is_Call(pred)) {
4593 return gen_Proj_be_Call(node);
4594 } else if (is_Cmp(pred)) {
4595 return gen_Proj_Cmp(node);
4596 } else if (get_irn_op(pred) == op_Start) {
4597 if (proj == pn_Start_X_initial_exec) {
4598 ir_node *block = get_nodes_block(pred);
4601 /* we exchange the ProjX with a jump */
4602 block = be_transform_node(block);
4603 jump = new_rd_Jmp(dbgi, irg, block);
4606 if (node == be_get_old_anchor(anchor_tls)) {
4607 return gen_Proj_tls(node);
4610 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4614 ir_node *new_pred = be_transform_node(pred);
4615 ir_node *block = be_transform_node(get_nodes_block(node));
4616 ir_mode *mode = get_irn_mode(node);
4617 if (mode_needs_gp_reg(mode)) {
4618 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4619 get_Proj_proj(node));
4620 #ifdef DEBUG_libfirm
4621 new_proj->node_nr = node->node_nr;
4627 return be_duplicate_node(node);
4631 * Enters all transform functions into the generic pointer
4633 static void register_transformers(void)
4637 /* first clear the generic function pointer for all ops */
4638 clear_irp_opcodes_generic_func();
4640 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4641 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4679 /* transform ops from intrinsic lowering */
4695 GEN(ia32_l_X87toSSE);
4696 GEN(ia32_l_SSEtoX87);
4702 /* we should never see these nodes */
4717 /* handle generic backend nodes */
4726 op_Mulh = get_op_Mulh();
4735 * Pre-transform all unknown and noreg nodes.
4737 static void ia32_pretransform_node(void *arch_cg) {
4738 ia32_code_gen_t *cg = arch_cg;
4740 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4741 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4742 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4743 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4744 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4745 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4750 * Walker, checks if all ia32 nodes producing more than one result have
4751 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4753 static void add_missing_keep_walker(ir_node *node, void *data)
4756 unsigned found_projs = 0;
4757 const ir_edge_t *edge;
4758 ir_mode *mode = get_irn_mode(node);
4763 if(!is_ia32_irn(node))
4766 n_outs = get_ia32_n_res(node);
4769 if(is_ia32_SwitchJmp(node))
4772 assert(n_outs < (int) sizeof(unsigned) * 8);
4773 foreach_out_edge(node, edge) {
4774 ir_node *proj = get_edge_src_irn(edge);
4775 int pn = get_Proj_proj(proj);
4777 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4778 found_projs |= 1 << pn;
4782 /* are keeps missing? */
4784 for(i = 0; i < n_outs; ++i) {
4787 const arch_register_req_t *req;
4788 const arch_register_class_t *class;
4790 if(found_projs & (1 << i)) {
4794 req = get_ia32_out_req(node, i);
4799 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4803 block = get_nodes_block(node);
4804 in[0] = new_r_Proj(current_ir_graph, block, node,
4805 arch_register_class_mode(class), i);
4806 if(last_keep != NULL) {
4807 be_Keep_add_node(last_keep, class, in[0]);
4809 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4810 if(sched_is_scheduled(node)) {
4811 sched_add_after(node, last_keep);
4818 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4821 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4823 ir_graph *irg = be_get_birg_irg(cg->birg);
4824 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4827 /* do the transformation */
4828 void ia32_transform_graph(ia32_code_gen_t *cg) {
4830 ir_graph *irg = cg->irg;
4831 int opt_arch = cg->isa->opt_arch;
4832 int arch = cg->isa->arch;
4834 /* TODO: look at cpu and fill transform config in with that... */
4835 transform_config.use_incdec = 1;
4836 transform_config.use_sse2 = 0;
4837 transform_config.use_ffreep = ARCH_ATHLON(opt_arch);
4838 transform_config.use_ftst = 0;
4839 transform_config.use_femms = ARCH_ATHLON(opt_arch) && ARCH_MMX(arch) && ARCH_AMD(arch);
4840 transform_config.use_fucomi = 1;
4841 transform_config.use_cmov = IS_P6_ARCH(arch);
4843 register_transformers();
4845 initial_fpcw = NULL;
4847 heights = heights_new(irg);
4848 ia32_calculate_non_address_mode_nodes(irg);
4850 /* the transform phase is not safe for CSE (yet) because several nodes get
4851 * attributes set after their creation */
4852 cse_last = get_opt_cse();
4855 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4857 set_opt_cse(cse_last);
4859 ia32_free_non_address_mode_nodes();
4860 heights_free(heights);
4864 void ia32_init_transform(void)
4866 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");