2 * This file implements the IR transformation from firm into
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
26 #include "../benode_t.h"
27 #include "../besched.h"
29 #include "bearch_ia32_t.h"
31 #include "ia32_nodes_attr.h"
32 #include "../arch/archop.h" /* we need this for Min and Max nodes */
33 #include "ia32_transform.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
37 #include "gen_ia32_regalloc_if.h"
39 #define SFP_SIGN "0x80000000"
40 #define DFP_SIGN "0x8000000000000000"
41 #define SFP_ABS "0x7FFFFFFF"
42 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
44 #define TP_SFP_SIGN "ia32_sfp_sign"
45 #define TP_DFP_SIGN "ia32_dfp_sign"
46 #define TP_SFP_ABS "ia32_sfp_abs"
47 #define TP_DFP_ABS "ia32_dfp_abs"
49 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
50 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
51 #define ENT_SFP_ABS "IA32_SFP_ABS"
52 #define ENT_DFP_ABS "IA32_DFP_ABS"
54 extern ir_op *get_op_Mulh(void);
56 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
57 ir_node *op1, ir_node *op2, ir_node *mem, ir_mode *mode);
59 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
60 ir_node *op, ir_node *mem, ir_mode *mode);
63 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS
66 /****************************************************************************************************
68 * | | | | / _| | | (_)
69 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
70 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
71 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
72 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
74 ****************************************************************************************************/
81 /* Compares two (entity, tarval) combinations */
82 static int cmp_tv_ent(const void *a, const void *b, size_t len) {
83 const struct tv_ent *e1 = a;
84 const struct tv_ent *e2 = b;
86 return !(e1->tv == e2->tv);
89 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
90 static char *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
91 static set *const_set = NULL;
103 const_set = new_set(cmp_tv_ent, 10);
108 tp_name = TP_SFP_SIGN;
109 ent_name = ENT_SFP_SIGN;
113 tp_name = TP_DFP_SIGN;
114 ent_name = ENT_DFP_SIGN;
118 tp_name = TP_SFP_ABS;
119 ent_name = ENT_SFP_ABS;
123 tp_name = TP_DFP_ABS;
124 ent_name = ENT_DFP_ABS;
130 key.tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
133 entry = set_insert(const_set, &key, sizeof(key), HASH_PTR(key.tv));
136 tp = new_type_primitive(new_id_from_str(tp_name), mode);
137 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
139 set_entity_ld_ident(ent, get_entity_ident(ent));
140 set_entity_visibility(ent, visibility_local);
141 set_entity_variability(ent, variability_constant);
142 set_entity_allocation(ent, allocation_static);
144 /* we create a new entity here: It's initialization must resist on the
146 rem = current_ir_graph;
147 current_ir_graph = get_const_code_irg();
148 cnst = new_Const(mode, key.tv);
149 current_ir_graph = rem;
151 set_atomic_ent_value(ent, cnst);
153 /* set the entry for hashmap */
162 * Prints the old node name on cg obst and returns a pointer to it.
164 const char *get_old_node_name(ia32_transform_env_t *env) {
165 static int name_cnt = 0;
166 ia32_isa_t *isa = (ia32_isa_t *)env->cg->arch_env->isa;
168 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", env->irn);
169 obstack_1grow(isa->name_obst, 0);
170 isa->name_obst_size += obstack_object_size(isa->name_obst);
172 if (name_cnt % 1024 == 0) {
173 printf("name obst size reached %d bytes after %d nodes\n", isa->name_obst_size, name_cnt);
175 return obstack_finish(isa->name_obst);
179 /* determine if one operator is an Imm */
180 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
182 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
183 else return is_ia32_Cnst(op2) ? op2 : NULL;
186 /* determine if one operator is not an Imm */
187 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
188 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
193 * Construct a standard binary operation, set AM and immediate if required.
195 * @param env The transformation environment
196 * @param op1 The first operand
197 * @param op2 The second operand
198 * @param func The node constructor function
199 * @return The constructed ia32 node.
201 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
202 ir_node *new_op = NULL;
203 ir_mode *mode = env->mode;
204 dbg_info *dbg = env->dbg;
205 ir_graph *irg = env->irg;
206 ir_node *block = env->block;
207 firm_dbg_module_t *mod = env->mod;
208 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
209 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
210 ir_node *nomem = new_NoMem();
211 ir_node *expr_op, *imm_op;
213 /* Check if immediate optimization is on and */
214 /* if it's an operation with immediate. */
215 if (! env->cg->opt.immops) {
219 else if (is_op_commutative(get_irn_op(env->irn))) {
220 imm_op = get_immediate_op(op1, op2);
221 expr_op = get_expr_op(op1, op2);
224 imm_op = get_immediate_op(NULL, op2);
225 expr_op = get_expr_op(op1, op2);
228 assert((expr_op || imm_op) && "invalid operands");
231 /* We have two consts here: not yet supported */
235 if (mode_is_float(mode)) {
236 /* floating point operations */
238 DB((mod, LEVEL_1, "FP with immediate ..."));
239 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem, mode_T);
240 set_ia32_Immop_attr(new_op, imm_op);
241 set_ia32_am_support(new_op, ia32_am_None);
244 DB((mod, LEVEL_1, "FP binop ..."));
245 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
246 set_ia32_am_support(new_op, ia32_am_Source);
250 /* integer operations */
252 /* This is expr + const */
253 DB((mod, LEVEL_1, "INT with immediate ..."));
254 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem, mode_T);
255 set_ia32_Immop_attr(new_op, imm_op);
258 set_ia32_am_support(new_op, ia32_am_Dest);
261 DB((mod, LEVEL_1, "INT binop ..."));
262 /* This is a normal operation */
263 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
266 set_ia32_am_support(new_op, ia32_am_Full);
271 set_ia32_orig_node(new_op, get_old_node_name(env));
274 set_ia32_res_mode(new_op, mode);
276 if (is_op_commutative(get_irn_op(env->irn))) {
277 set_ia32_commutative(new_op);
280 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
286 * Construct a shift/rotate binary operation, sets AM and immediate if required.
288 * @param env The transformation environment
289 * @param op1 The first operand
290 * @param op2 The second operand
291 * @param func The node constructor function
292 * @return The constructed ia32 node.
294 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
295 ir_node *new_op = NULL;
296 ir_mode *mode = env->mode;
297 dbg_info *dbg = env->dbg;
298 ir_graph *irg = env->irg;
299 ir_node *block = env->block;
300 firm_dbg_module_t *mod = env->mod;
301 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
302 ir_node *nomem = new_NoMem();
303 ir_node *expr_op, *imm_op;
306 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
308 /* Check if immediate optimization is on and */
309 /* if it's an operation with immediate. */
310 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
311 expr_op = get_expr_op(op1, op2);
313 assert((expr_op || imm_op) && "invalid operands");
316 /* We have two consts here: not yet supported */
320 /* Limit imm_op within range imm8 */
322 tv = get_ia32_Immop_tarval(imm_op);
325 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
332 /* integer operations */
334 /* This is shift/rot with const */
335 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
337 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
338 set_ia32_Immop_attr(new_op, imm_op);
341 /* This is a normal shift/rot */
342 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
343 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
347 set_ia32_am_support(new_op, ia32_am_Dest);
350 set_ia32_orig_node(new_op, get_old_node_name(env));
353 set_ia32_res_mode(new_op, mode);
355 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
360 * Construct a standard unary operation, set AM and immediate if required.
362 * @param env The transformation environment
363 * @param op The operand
364 * @param func The node constructor function
365 * @return The constructed ia32 node.
367 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
368 ir_node *new_op = NULL;
369 ir_mode *mode = env->mode;
370 dbg_info *dbg = env->dbg;
371 firm_dbg_module_t *mod = env->mod;
372 ir_graph *irg = env->irg;
373 ir_node *block = env->block;
374 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
375 ir_node *nomem = new_NoMem();
377 new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
379 if (mode_is_float(mode)) {
380 DB((mod, LEVEL_1, "FP unop ..."));
381 /* floating point operations don't support implicit store */
382 set_ia32_am_support(new_op, ia32_am_None);
385 DB((mod, LEVEL_1, "INT unop ..."));
386 set_ia32_am_support(new_op, ia32_am_Dest);
390 set_ia32_orig_node(new_op, get_old_node_name(env));
393 set_ia32_res_mode(new_op, mode);
395 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
401 * Creates an ia32 Add with immediate.
403 * @param env The transformation environment
404 * @param expr_op The expression operator
405 * @param const_op The constant
406 * @return the created ia32 Add node
408 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
409 ir_node *new_op = NULL;
410 tarval *tv = get_ia32_Immop_tarval(const_op);
411 firm_dbg_module_t *mod = env->mod;
412 dbg_info *dbg = env->dbg;
413 ir_graph *irg = env->irg;
414 ir_node *block = env->block;
415 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
416 ir_node *nomem = new_NoMem();
418 tarval_classification_t class_tv, class_negtv;
420 /* try to optimize to inc/dec */
421 if (env->cg->opt.incdec && tv) {
422 /* optimize tarvals */
423 class_tv = classify_tarval(tv);
424 class_negtv = classify_tarval(tarval_neg(tv));
426 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
427 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
428 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
431 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
432 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
433 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
439 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
440 set_ia32_Immop_attr(new_op, const_op);
447 * Creates an ia32 Add.
449 * @param dbg firm node dbg
450 * @param block the block the new node should belong to
451 * @param op1 first operator
452 * @param op2 second operator
453 * @param mode node mode
454 * @return the created ia32 Add node
456 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
457 ir_node *new_op = NULL;
458 dbg_info *dbg = env->dbg;
459 ir_mode *mode = env->mode;
460 ir_graph *irg = env->irg;
461 ir_node *block = env->block;
462 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
463 ir_node *nomem = new_NoMem();
464 ir_node *expr_op, *imm_op;
466 /* Check if immediate optimization is on and */
467 /* if it's an operation with immediate. */
468 imm_op = env->cg->opt.immops ? get_immediate_op(op1, op2) : NULL;
469 expr_op = get_expr_op(op1, op2);
471 assert((expr_op || imm_op) && "invalid operands");
473 if (mode_is_float(mode)) {
474 return gen_binop(env, op1, op2, new_rd_ia32_fAdd);
479 /* No expr_op means, that we have two const - one symconst and */
480 /* one tarval or another symconst - because this case is not */
481 /* covered by constant folding */
483 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
484 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
485 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
488 set_ia32_am_support(new_op, ia32_am_Source);
489 set_ia32_op_type(new_op, ia32_AddrModeS);
490 set_ia32_am_flavour(new_op, ia32_am_O);
492 /* Lea doesn't need a Proj */
496 /* This is expr + const */
497 new_op = gen_imm_Add(env, expr_op, imm_op);
500 set_ia32_am_support(new_op, ia32_am_Dest);
503 /* This is a normal add */
504 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
507 set_ia32_am_support(new_op, ia32_am_Full);
512 set_ia32_orig_node(new_op, get_old_node_name(env));
515 set_ia32_res_mode(new_op, mode);
517 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
523 * Creates an ia32 Mul.
525 * @param dbg firm node dbg
526 * @param block the block the new node should belong to
527 * @param op1 first operator
528 * @param op2 second operator
529 * @param mode node mode
530 * @return the created ia32 Mul node
532 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
535 if (mode_is_float(env->mode)) {
536 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul);
539 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
548 * Creates an ia32 Mulh.
549 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
550 * this result while Mul returns the lower 32 bit.
552 * @param env The transformation environment
553 * @param op1 The first operator
554 * @param op2 The second operator
555 * @return the created ia32 Mulh node
557 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
558 ir_node *proj_EAX, *proj_EDX, *mulh;
561 assert(mode_is_float(env->mode) && "Mulh with float not supported");
562 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
563 mulh = get_Proj_pred(proj_EAX);
564 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
566 /* to be on the save side */
567 set_Proj_proj(proj_EAX, pn_EAX);
569 if (get_ia32_cnst(mulh)) {
570 /* Mulh with const cannot have AM */
571 set_ia32_am_support(mulh, ia32_am_None);
574 /* Mulh cannot have AM for destination */
575 set_ia32_am_support(mulh, ia32_am_Source);
581 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
589 * Creates an ia32 And.
591 * @param env The transformation environment
592 * @param op1 The first operator
593 * @param op2 The second operator
594 * @return The created ia32 And node
596 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
597 if (mode_is_float(env->mode)) {
598 return gen_binop(env, op1, op2, new_rd_ia32_fAnd);
601 return gen_binop(env, op1, op2, new_rd_ia32_And);
608 * Creates an ia32 Or.
610 * @param env The transformation environment
611 * @param op1 The first operator
612 * @param op2 The second operator
613 * @return The created ia32 Or node
615 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
616 if (mode_is_float(env->mode)) {
617 return gen_binop(env, op1, op2, new_rd_ia32_fOr);
620 return gen_binop(env, op1, op2, new_rd_ia32_Or);
627 * Creates an ia32 Eor.
629 * @param env The transformation environment
630 * @param op1 The first operator
631 * @param op2 The second operator
632 * @return The created ia32 Eor node
634 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
635 if (mode_is_float(env->mode)) {
636 return gen_binop(env, op1, op2, new_rd_ia32_fEor);
639 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
646 * Creates an ia32 Max.
648 * @param env The transformation environment
649 * @param op1 The first operator
650 * @param op2 The second operator
651 * @return the created ia32 Max node
653 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
656 if (mode_is_float(env->mode)) {
657 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
660 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
661 set_ia32_am_support(new_op, ia32_am_None);
663 set_ia32_orig_node(new_op, get_old_node_name(env));
673 * Creates an ia32 Min.
675 * @param env The transformation environment
676 * @param op1 The first operator
677 * @param op2 The second operator
678 * @return the created ia32 Min node
680 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
683 if (mode_is_float(env->mode)) {
684 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
687 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
688 set_ia32_am_support(new_op, ia32_am_None);
690 set_ia32_orig_node(new_op, get_old_node_name(env));
700 * Creates an ia32 Sub with immediate.
702 * @param env The transformation environment
703 * @param op1 The first operator
704 * @param op2 The second operator
705 * @return The created ia32 Sub node
707 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
708 ir_node *new_op = NULL;
709 tarval *tv = get_ia32_Immop_tarval(const_op);
710 firm_dbg_module_t *mod = env->mod;
711 dbg_info *dbg = env->dbg;
712 ir_graph *irg = env->irg;
713 ir_node *block = env->block;
714 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
715 ir_node *nomem = new_NoMem();
717 tarval_classification_t class_tv, class_negtv;
719 /* try to optimize to inc/dec */
720 if (env->cg->opt.incdec && tv) {
721 /* optimize tarvals */
722 class_tv = classify_tarval(tv);
723 class_negtv = classify_tarval(tarval_neg(tv));
725 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
726 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
727 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
730 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
731 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
732 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
738 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
739 set_ia32_Immop_attr(new_op, const_op);
746 * Creates an ia32 Sub.
748 * @param env The transformation environment
749 * @param op1 The first operator
750 * @param op2 The second operator
751 * @return The created ia32 Sub node
753 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
754 ir_node *new_op = NULL;
755 dbg_info *dbg = env->dbg;
756 ir_mode *mode = env->mode;
757 ir_graph *irg = env->irg;
758 ir_node *block = env->block;
759 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
760 ir_node *nomem = new_NoMem();
761 ir_node *expr_op, *imm_op;
763 /* Check if immediate optimization is on and */
764 /* if it's an operation with immediate. */
765 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
766 expr_op = get_expr_op(op1, op2);
768 assert((expr_op || imm_op) && "invalid operands");
770 if (mode_is_float(mode)) {
771 return gen_binop(env, op1, op2, new_rd_ia32_fSub);
776 /* No expr_op means, that we have two const - one symconst and */
777 /* one tarval or another symconst - because this case is not */
778 /* covered by constant folding */
780 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
781 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
782 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
785 set_ia32_am_support(new_op, ia32_am_Source);
786 set_ia32_op_type(new_op, ia32_AddrModeS);
787 set_ia32_am_flavour(new_op, ia32_am_O);
789 /* Lea doesn't need a Proj */
793 /* This is expr - const */
794 new_op = gen_imm_Sub(env, expr_op, imm_op);
797 set_ia32_am_support(new_op, ia32_am_Dest);
800 /* This is a normal sub */
801 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
804 set_ia32_am_support(new_op, ia32_am_Full);
809 set_ia32_orig_node(new_op, get_old_node_name(env));
812 set_ia32_res_mode(new_op, mode);
814 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
820 * Generates an ia32 DivMod with additional infrastructure for the
821 * register allocator if needed.
823 * @param env The transformation environment
824 * @param dividend -no comment- :)
825 * @param divisor -no comment- :)
826 * @param dm_flav flavour_Div/Mod/DivMod
827 * @return The created ia32 DivMod node
829 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
831 ir_node *edx_node, *cltd;
833 dbg_info *dbg = env->dbg;
834 ir_graph *irg = env->irg;
835 ir_node *block = env->block;
836 ir_mode *mode = env->mode;
837 ir_node *irn = env->irn;
842 mem = get_Div_mem(irn);
845 mem = get_Mod_mem(irn);
848 mem = get_DivMod_mem(irn);
854 if (mode_is_signed(mode)) {
855 /* in signed mode, we need to sign extend the dividend */
856 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend, mode_T);
857 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EAX);
858 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EDX);
861 edx_node = new_rd_ia32_Const(dbg, irg, block, mode_Iu);
862 set_ia32_Const_type(edx_node, ia32_Const);
863 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
866 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode_T);
868 set_ia32_flavour(res, dm_flav);
869 set_ia32_n_res(res, 2);
871 /* Only one proj is used -> We must add a second proj and */
872 /* connect this one to a Keep node to eat up the second */
873 /* destroyed register. */
874 if (get_irn_n_edges(irn) == 1) {
875 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
876 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
878 if (get_Proj_proj(proj) == pn_DivMod_res_div) {
879 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
882 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
885 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
889 set_ia32_orig_node(res, get_old_node_name(env));
892 set_ia32_res_mode(res, mode_Is);
899 * Wrapper for generate_DivMod. Sets flavour_Mod.
901 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
902 return generate_DivMod(env, op1, op2, flavour_Mod);
908 * Wrapper for generate_DivMod. Sets flavour_Div.
910 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
911 return generate_DivMod(env, op1, op2, flavour_Div);
917 * Wrapper for generate_DivMod. Sets flavour_DivMod.
919 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
920 return generate_DivMod(env, op1, op2, flavour_DivMod);
926 * Creates an ia32 floating Div.
928 * @param env The transformation environment
929 * @param op1 The first operator
930 * @param op2 The second operator
931 * @return The created ia32 fDiv node
933 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
934 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
935 ir_node *nomem = new_rd_NoMem(env->irg);
938 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, env->mode);
939 set_ia32_am_support(new_op, ia32_am_Source);
942 set_ia32_orig_node(new_op, get_old_node_name(env));
951 * Creates an ia32 Shl.
953 * @param env The transformation environment
954 * @param op1 The first operator
955 * @param op2 The second operator
956 * @return The created ia32 Shl node
958 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
959 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shl);
965 * Creates an ia32 Shr.
967 * @param env The transformation environment
968 * @param op1 The first operator
969 * @param op2 The second operator
970 * @return The created ia32 Shr node
972 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
973 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shr);
979 * Creates an ia32 Shrs.
981 * @param env The transformation environment
982 * @param op1 The first operator
983 * @param op2 The second operator
984 * @return The created ia32 Shrs node
986 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
987 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shrs);
993 * Creates an ia32 RotL.
995 * @param env The transformation environment
996 * @param op1 The first operator
997 * @param op2 The second operator
998 * @return The created ia32 RotL node
1000 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1001 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1007 * Creates an ia32 RotR.
1008 * NOTE: There is no RotR with immediate because this would always be a RotL
1009 * "imm-mode_size_bits" which can be pre-calculated.
1011 * @param env The transformation environment
1012 * @param op1 The first operator
1013 * @param op2 The second operator
1014 * @return The created ia32 RotR node
1016 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1017 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1023 * Creates an ia32 RotR or RotL (depending on the found pattern).
1025 * @param env The transformation environment
1026 * @param op1 The first operator
1027 * @param op2 The second operator
1028 * @return The created ia32 RotL or RotR node
1030 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1031 ir_node *rotate = NULL;
1033 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1034 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1035 that means we can create a RotR instead of an Add and a RotL */
1038 ir_node *pred = get_Proj_pred(op2);
1040 if (is_ia32_Add(pred)) {
1041 ir_node *pred_pred = get_irn_n(pred, 2);
1042 tarval *tv = get_ia32_Immop_tarval(pred);
1043 long bits = get_mode_size_bits(env->mode);
1045 if (is_Proj(pred_pred)) {
1046 pred_pred = get_Proj_pred(pred_pred);
1049 if (is_ia32_Minus(pred_pred) &&
1050 tarval_is_long(tv) &&
1051 get_tarval_long(tv) == bits)
1053 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1054 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1061 rotate = gen_RotL(env, op1, op2);
1070 * Transforms a Minus node.
1072 * @param env The transformation environment
1073 * @param op The operator
1074 * @return The created ia32 Minus node
1076 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
1079 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1080 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1081 ir_node *nomem = new_rd_NoMem(env->irg);
1084 if (mode_is_float(env->mode)) {
1085 new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1087 size = get_mode_size_bits(env->mode);
1088 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1090 set_ia32_sc(new_op, name);
1093 set_ia32_orig_node(new_op, get_old_node_name(env));
1096 set_ia32_res_mode(new_op, env->mode);
1098 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1101 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1110 * Transforms a Not node.
1112 * @param env The transformation environment
1113 * @param op The operator
1114 * @return The created ia32 Not node
1116 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) {
1119 if (mode_is_float(env->mode)) {
1123 new_op = gen_unop(env, op, new_rd_ia32_Not);
1132 * Transforms an Abs node.
1134 * @param env The transformation environment
1135 * @param op The operator
1136 * @return The created ia32 Abs node
1138 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
1139 ir_node *res, *p_eax, *p_edx;
1140 dbg_info *dbg = env->dbg;
1141 ir_mode *mode = env->mode;
1142 ir_graph *irg = env->irg;
1143 ir_node *block = env->block;
1144 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1145 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1146 ir_node *nomem = new_NoMem();
1150 if (mode_is_float(mode)) {
1151 res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1153 size = get_mode_size_bits(mode);
1154 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1156 set_ia32_sc(res, name);
1159 set_ia32_orig_node(res, get_old_node_name(env));
1162 set_ia32_res_mode(res, mode);
1164 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1167 res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T);
1169 set_ia32_orig_node(res, get_old_node_name(env));
1171 set_ia32_res_mode(res, mode);
1173 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
1174 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
1176 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T);
1178 set_ia32_orig_node(res, get_old_node_name(env));
1180 set_ia32_res_mode(res, mode);
1182 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1184 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T);
1186 set_ia32_orig_node(res, get_old_node_name(env));
1188 set_ia32_res_mode(res, mode);
1190 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1199 * Transforms a Load.
1201 * @param mod the debug module
1202 * @param block the block the new node should belong to
1203 * @param node the ir Load node
1204 * @param mode node mode
1205 * @return the created ia32 Load node
1207 static ir_node *gen_Load(ia32_transform_env_t *env) {
1208 ir_node *node = env->irn;
1209 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1212 if (mode_is_float(env->mode)) {
1213 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1216 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1219 set_ia32_am_support(new_op, ia32_am_Source);
1220 set_ia32_op_type(new_op, ia32_AddrModeS);
1221 set_ia32_am_flavour(new_op, ia32_B);
1222 set_ia32_ls_mode(new_op, get_Load_mode(node));
1225 set_ia32_orig_node(new_op, get_old_node_name(env));
1234 * Transforms a Store.
1236 * @param mod the debug module
1237 * @param block the block the new node should belong to
1238 * @param node the ir Store node
1239 * @param mode node mode
1240 * @return the created ia32 Store node
1242 static ir_node *gen_Store(ia32_transform_env_t *env) {
1243 ir_node *node = env->irn;
1244 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1245 ir_node *val = get_Store_value(node);
1246 ir_node *ptr = get_Store_ptr(node);
1247 ir_node *mem = get_Store_mem(node);
1248 ir_node *sval = val;
1251 /* in case of storing a const -> make it an attribute */
1252 if (is_ia32_Cnst(val)) {
1256 if (mode_is_float(env->mode)) {
1257 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode);
1260 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode);
1263 /* stored const is an attribute (saves a register) */
1264 if (is_ia32_Cnst(val)) {
1265 set_ia32_Immop_attr(new_op, val);
1268 set_ia32_am_support(new_op, ia32_am_Dest);
1269 set_ia32_op_type(new_op, ia32_AddrModeD);
1270 set_ia32_am_flavour(new_op, ia32_B);
1271 set_ia32_ls_mode(new_op, get_irn_mode(val));
1274 set_ia32_orig_node(new_op, get_old_node_name(env));
1283 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp or CondJmp_i
1285 * @param env The transformation environment
1286 * @return The transformed node.
1288 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1289 dbg_info *dbg = env->dbg;
1290 ir_graph *irg = env->irg;
1291 ir_node *block = env->block;
1292 ir_node *node = env->irn;
1293 ir_node *sel = get_Cond_selector(node);
1294 ir_mode *sel_mode = get_irn_mode(sel);
1295 ir_node *res = NULL;
1296 ir_node *pred = NULL;
1297 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1298 ir_node *nomem = new_NoMem();
1299 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1301 if (is_Proj(sel) && sel_mode == mode_b) {
1302 pred = get_Proj_pred(sel);
1304 /* get both compare operators */
1305 cmp_a = get_Cmp_left(pred);
1306 cmp_b = get_Cmp_right(pred);
1308 /* check if we can use a CondJmp with immediate */
1309 cnst = env->cg->opt.immops ? get_immediate_op(cmp_a, cmp_b) : NULL;
1310 expr = get_expr_op(cmp_a, cmp_b);
1313 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1314 set_ia32_Immop_attr(res, cnst);
1317 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1320 set_ia32_pncode(res, get_Proj_proj(sel));
1321 set_ia32_am_support(res, ia32_am_Source);
1324 res = new_rd_ia32_SwitchJmp(dbg, irg, block, sel, mode_T);
1325 set_ia32_pncode(res, get_Cond_defaultProj(node));
1329 set_ia32_orig_node(res, get_old_node_name(env));
1338 * Transforms a CopyB node.
1340 * @param env The transformation environment
1341 * @return The transformed node.
1343 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1344 ir_node *res = NULL;
1345 dbg_info *dbg = env->dbg;
1346 ir_graph *irg = env->irg;
1347 ir_mode *mode = env->mode;
1348 ir_node *block = env->block;
1349 ir_node *node = env->irn;
1350 ir_node *src = get_CopyB_src(node);
1351 ir_node *dst = get_CopyB_dst(node);
1352 ir_node *mem = get_CopyB_mem(node);
1353 int size = get_type_size_bytes(get_CopyB_type(node));
1356 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1357 /* then we need the size explicitly in ECX. */
1358 if (size >= 16 * 4) {
1359 rem = size & 0x3; /* size % 4 */
1362 res = new_rd_ia32_Const(dbg, irg, block, mode_Is);
1363 set_ia32_op_type(res, ia32_Const);
1364 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1366 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1367 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1370 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1371 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1375 set_ia32_orig_node(res, get_old_node_name(env));
1384 * Transforms a Mux node into CMov.
1386 * @param env The transformation environment
1387 * @return The transformed node.
1389 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1390 ir_node *node = env->irn;
1391 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1392 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1395 set_ia32_orig_node(new_op, get_old_node_name(env));
1403 * Following conversion rules apply:
1407 * 1) n bit -> m bit n < m (upscale)
1409 * 2) n bit -> m bit n == m (sign change)
1411 * 3) n bit -> m bit n > m (downscale)
1412 * a) Un -> Um = AND Un, (1 << m) - 1
1413 * b) Sn -> Um same as a)
1414 * c) Un -> Sm same as a)
1415 * d) Sn -> Sm = ASHL Sn, (n - m); ASHR Sn, (n - m)
1419 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1423 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1424 * if target mode < 32bit: additional INT -> INT conversion (see above)
1428 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1431 static ir_node *gen_int_downscale_conv(ia32_transform_env_t *env, ir_node *op,
1432 ir_mode *src_mode, ir_mode *tgt_mode)
1434 int n = get_mode_size_bits(src_mode);
1435 int m = get_mode_size_bits(tgt_mode);
1436 dbg_info *dbg = env->dbg;
1437 ir_graph *irg = env->irg;
1438 ir_node *block = env->block;
1439 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1440 ir_node *nomem = new_rd_NoMem(irg);
1441 ir_node *new_op, *proj;
1443 assert(n > m && "downscale expected");
1445 if (mode_is_signed(src_mode) && mode_is_signed(tgt_mode)) {
1446 /* ASHL Sn, n - m */
1447 new_op = new_rd_ia32_Shl(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
1448 proj = new_rd_Proj(dbg, irg, block, new_op, src_mode, 0);
1449 set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
1450 set_ia32_am_support(new_op, ia32_am_Source);
1452 set_ia32_orig_node(new_op, get_old_node_name(env));
1455 /* ASHR Sn, n - m */
1456 new_op = new_rd_ia32_Shrs(dbg, irg, block, noreg, noreg, proj, noreg, nomem, mode_T);
1457 set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
1460 new_op = new_rd_ia32_And(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
1461 set_ia32_Immop_tarval(new_op, new_tarval_from_long((1 << m) - 1, mode_Is));
1468 * Transforms a Conv node.
1470 * @param env The transformation environment
1471 * @param op The operator
1472 * @return The created ia32 Conv node
1474 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
1475 dbg_info *dbg = env->dbg;
1476 ir_graph *irg = env->irg;
1477 ir_mode *src_mode = get_irn_mode(op);
1478 ir_mode *tgt_mode = env->mode;
1479 ir_node *block = env->block;
1480 ir_node *new_op = NULL;
1481 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1482 ir_node *nomem = new_rd_NoMem(irg);
1483 firm_dbg_module_t *mod = env->mod;
1486 if (src_mode == tgt_mode) {
1487 /* this can happen when changing mode_P to mode_Is */
1488 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1489 edges_reroute(env->irn, op, irg);
1491 else if (mode_is_float(src_mode)) {
1492 /* we convert from float ... */
1493 if (mode_is_float(tgt_mode)) {
1495 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1496 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1500 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1501 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1502 /* if target mode is not int: add an additional downscale convert */
1503 if (get_mode_size_bits(tgt_mode) < 32) {
1505 set_ia32_orig_node(new_op, get_old_node_name(env));
1507 set_ia32_res_mode(new_op, tgt_mode);
1508 set_ia32_am_support(new_op, ia32_am_Source);
1510 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
1511 new_op = gen_int_downscale_conv(env, proj, src_mode, tgt_mode);
1516 /* we convert from int ... */
1517 if (mode_is_float(tgt_mode)) {
1519 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1520 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1524 if (get_mode_size_bits(src_mode) <= get_mode_size_bits(tgt_mode)) {
1525 DB((mod, LEVEL_1, "omitting upscale Conv(%+F, %+F) ...", src_mode, tgt_mode));
1526 edges_reroute(env->irn, op, irg);
1529 DB((mod, LEVEL_1, "create downscale Conv(%+F, %+F) ...", src_mode, tgt_mode));
1530 new_op = gen_int_downscale_conv(env, op, src_mode, tgt_mode);
1537 set_ia32_orig_node(new_op, get_old_node_name(env));
1539 set_ia32_res_mode(new_op, tgt_mode);
1541 set_ia32_am_support(new_op, ia32_am_Source);
1543 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
1551 /********************************************
1554 * | |__ ___ _ __ ___ __| | ___ ___
1555 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1556 * | |_) | __/ | | | (_) | (_| | __/\__ \
1557 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1559 ********************************************/
1561 static ir_node *gen_StackParam(ia32_transform_env_t *env) {
1562 ir_node *new_op = NULL;
1563 ir_node *node = env->irn;
1564 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1565 ir_node *mem = new_rd_NoMem(env->irg);
1566 ir_node *ptr = get_irn_n(node, 0);
1567 entity *ent = be_get_frame_entity(node);
1568 ir_mode *mode = env->mode;
1570 if (mode_is_float(mode)) {
1571 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1574 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1577 set_ia32_frame_ent(new_op, ent);
1578 set_ia32_use_frame(new_op);
1580 set_ia32_am_support(new_op, ia32_am_Source);
1581 set_ia32_op_type(new_op, ia32_AddrModeS);
1582 set_ia32_am_flavour(new_op, ia32_B);
1583 set_ia32_ls_mode(new_op, mode);
1586 set_ia32_orig_node(new_op, get_old_node_name(env));
1589 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
1593 * Transforms a FrameAddr into an ia32 Add.
1595 static ir_node *gen_FrameAddr(ia32_transform_env_t *env) {
1596 ir_node *new_op = NULL;
1597 ir_node *node = env->irn;
1598 ir_node *op = get_irn_n(node, 0);
1599 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1600 ir_node *nomem = new_rd_NoMem(env->irg);
1602 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem, mode_T);
1603 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1604 set_ia32_am_support(new_op, ia32_am_Full);
1605 set_ia32_use_frame(new_op);
1608 set_ia32_orig_node(new_op, get_old_node_name(env));
1611 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1615 * Transforms a FrameLoad into an ia32 Load.
1617 static ir_node *gen_FrameLoad(ia32_transform_env_t *env) {
1618 ir_node *new_op = NULL;
1619 ir_node *node = env->irn;
1620 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1621 ir_node *mem = get_irn_n(node, 0);
1622 ir_node *ptr = get_irn_n(node, 1);
1623 entity *ent = be_get_frame_entity(node);
1624 ir_mode *mode = get_type_mode(get_entity_type(ent));
1626 if (mode_is_float(mode)) {
1627 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1630 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1633 set_ia32_frame_ent(new_op, ent);
1634 set_ia32_use_frame(new_op);
1636 set_ia32_am_support(new_op, ia32_am_Source);
1637 set_ia32_op_type(new_op, ia32_AddrModeS);
1638 set_ia32_am_flavour(new_op, ia32_B);
1639 set_ia32_ls_mode(new_op, mode);
1642 set_ia32_orig_node(new_op, get_old_node_name(env));
1650 * Transforms a FrameStore into an ia32 Store.
1652 static ir_node *gen_FrameStore(ia32_transform_env_t *env) {
1653 ir_node *new_op = NULL;
1654 ir_node *node = env->irn;
1655 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1656 ir_node *mem = get_irn_n(node, 0);
1657 ir_node *ptr = get_irn_n(node, 1);
1658 ir_node *val = get_irn_n(node, 2);
1659 entity *ent = be_get_frame_entity(node);
1660 ir_mode *mode = get_irn_mode(val);
1662 if (mode_is_float(mode)) {
1663 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1666 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1669 set_ia32_frame_ent(new_op, ent);
1670 set_ia32_use_frame(new_op);
1672 set_ia32_am_support(new_op, ia32_am_Dest);
1673 set_ia32_op_type(new_op, ia32_AddrModeD);
1674 set_ia32_am_flavour(new_op, ia32_B);
1675 set_ia32_ls_mode(new_op, mode);
1678 set_ia32_orig_node(new_op, get_old_node_name(env));
1686 /*********************************************************
1689 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1690 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1691 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1692 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1694 *********************************************************/
1697 * Transforms a Sub or fSub into Neg--Add iff OUT_REG == SRC2_REG.
1698 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
1700 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
1701 ia32_transform_env_t tenv;
1702 ir_node *in1, *in2, *noreg, *nomem, *res;
1703 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
1705 /* Return if AM node or not a Sub or fSub */
1706 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_fSub(irn)))
1709 noreg = ia32_new_NoReg_gp(cg);
1710 nomem = new_rd_NoMem(cg->irg);
1711 in1 = get_irn_n(irn, 2);
1712 in2 = get_irn_n(irn, 3);
1713 in1_reg = arch_get_irn_register(cg->arch_env, in1);
1714 in2_reg = arch_get_irn_register(cg->arch_env, in2);
1715 out_reg = get_ia32_out_reg(irn, 0);
1717 tenv.block = get_nodes_block(irn);
1718 tenv.dbg = get_irn_dbg_info(irn);
1722 tenv.mode = get_ia32_res_mode(irn);
1725 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
1726 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
1727 /* generate the neg src2 */
1728 res = gen_Minus(&tenv, in2);
1729 arch_set_irn_register(cg->arch_env, res, in2_reg);
1731 /* add to schedule */
1732 sched_add_before(irn, res);
1734 /* generate the add */
1735 if (mode_is_float(tenv.mode)) {
1736 res = new_rd_ia32_fAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
1739 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
1743 set_ia32_orig_node(res, get_old_node_name(&tenv));
1746 slots = get_ia32_slots(res);
1749 /* add to schedule */
1750 sched_add_before(irn, res);
1752 /* remove the old sub */
1755 /* exchange the add and the sub */
1761 * Transforms the given firm node (and maybe some other related nodes)
1762 * into one or more assembler nodes.
1764 * @param node the firm node
1765 * @param env the debug module
1767 void ia32_transform_node(ir_node *node, void *env) {
1768 ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env;
1769 opcode code = get_irn_opcode(node);
1770 ir_node *asm_node = NULL;
1771 ia32_transform_env_t tenv;
1776 tenv.block = get_nodes_block(node);
1777 tenv.dbg = get_irn_dbg_info(node);
1778 tenv.irg = current_ir_graph;
1780 tenv.mod = cgenv->mod;
1781 tenv.mode = get_irn_mode(node);
1784 #define UNOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_op(node)); break
1785 #define BINOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_left(node), get_##a##_right(node)); break
1786 #define GEN(a) case iro_##a: asm_node = gen_##a(&tenv); break
1787 #define IGN(a) case iro_##a: break
1788 #define BAD(a) case iro_##a: goto bad
1789 #define OTHER_BIN(a) \
1790 if (get_irn_op(node) == get_op_##a()) { \
1791 asm_node = gen_##a(&tenv, get_irn_n(node, 0), get_irn_n(node, 1)); \
1795 if (be_is_##a(node)) { \
1796 asm_node = gen_##a(&tenv); \
1800 DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
1847 /* constant transformation happens earlier */
1877 fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
1881 /* exchange nodes if a new one was generated */
1883 exchange(node, asm_node);
1884 DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
1887 DB((tenv.mod, LEVEL_1, "ignored\n"));