2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
50 #include "../benode_t.h"
51 #include "../besched.h"
53 #include "../beutil.h"
54 #include "../beirg_t.h"
55 #include "../betranshlp.h"
57 #include "bearch_ia32_t.h"
58 #include "ia32_nodes_attr.h"
59 #include "ia32_transform.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_dbg_stat.h"
63 #include "ia32_optimize.h"
64 #include "ia32_util.h"
66 #include "gen_ia32_regalloc_if.h"
68 #define SFP_SIGN "0x80000000"
69 #define DFP_SIGN "0x8000000000000000"
70 #define SFP_ABS "0x7FFFFFFF"
71 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
73 #define TP_SFP_SIGN "ia32_sfp_sign"
74 #define TP_DFP_SIGN "ia32_dfp_sign"
75 #define TP_SFP_ABS "ia32_sfp_abs"
76 #define TP_DFP_ABS "ia32_dfp_abs"
78 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
79 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
80 #define ENT_SFP_ABS "IA32_SFP_ABS"
81 #define ENT_DFP_ABS "IA32_DFP_ABS"
83 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
84 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
86 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
88 /** hold the current code generator during transformation */
89 static ia32_code_gen_t *env_cg = NULL;
90 static ir_node *initial_fpcw = NULL;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
119 static ir_node *create_immediate_or_transform(ir_node *node,
120 char immediate_constraint_type);
122 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
123 dbg_info *dbgi, ir_node *new_block,
127 * Return true if a mode can be stored in the GP register set
129 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
130 if(mode == mode_fpcw)
132 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
136 * Returns 1 if irn is a Const representing 0, 0 otherwise
138 static INLINE int is_ia32_Const_0(ir_node *irn) {
139 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
140 && tarval_is_null(get_ia32_Immop_tarval(irn));
144 * Returns 1 if irn is a Const representing 1, 0 otherwise
146 static INLINE int is_ia32_Const_1(ir_node *irn) {
147 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
148 && tarval_is_one(get_ia32_Immop_tarval(irn));
152 * Collects all Projs of a node into the node array. Index is the projnum.
153 * BEWARE: The caller has to assure the appropriate array size!
155 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
156 const ir_edge_t *edge;
157 assert(get_irn_mode(irn) == mode_T && "need mode_T");
159 memset(projs, 0, size * sizeof(projs[0]));
161 foreach_out_edge(irn, edge) {
162 ir_node *proj = get_edge_src_irn(edge);
163 int proj_proj = get_Proj_proj(proj);
164 assert(proj_proj < size);
165 projs[proj_proj] = proj;
170 * Renumbers the proj having pn_old in the array tp pn_new
171 * and removes the proj from the array.
173 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
174 fprintf(stderr, "Warning: renumber_Proj used!\n");
176 set_Proj_proj(projs[pn_old], pn_new);
177 projs[pn_old] = NULL;
182 * creates a unique ident by adding a number to a tag
184 * @param tag the tag string, must contain a %d if a number
187 static ident *unique_id(const char *tag)
189 static unsigned id = 0;
192 snprintf(str, sizeof(str), tag, ++id);
193 return new_id_from_str(str);
197 * Get a primitive type for a mode.
199 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
201 pmap_entry *e = pmap_find(types, mode);
206 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
207 res = new_type_primitive(new_id_from_str(buf), mode);
208 set_type_alignment_bytes(res, 16);
209 pmap_insert(types, mode, res);
217 * Get an entity that is initialized with a tarval
219 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
221 tarval *tv = get_Const_tarval(cnst);
222 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
227 ir_mode *mode = get_irn_mode(cnst);
228 ir_type *tp = get_Const_type(cnst);
229 if (tp == firm_unknown_type)
230 tp = get_prim_type(cg->isa->types, mode);
232 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
234 set_entity_ld_ident(res, get_entity_ident(res));
235 set_entity_visibility(res, visibility_local);
236 set_entity_variability(res, variability_constant);
237 set_entity_allocation(res, allocation_static);
239 /* we create a new entity here: It's initialization must resist on the
241 rem = current_ir_graph;
242 current_ir_graph = get_const_code_irg();
243 set_atomic_ent_value(res, new_Const_type(tv, tp));
244 current_ir_graph = rem;
246 pmap_insert(cg->isa->tv_ent, tv, res);
254 static int is_Const_0(ir_node *node) {
258 return classify_Const(node) == CNST_NULL;
261 static int is_Const_1(ir_node *node) {
265 return classify_Const(node) == CNST_ONE;
269 * Transforms a Const.
271 static ir_node *gen_Const(ir_node *node) {
272 ir_graph *irg = current_ir_graph;
273 ir_node *old_block = get_nodes_block(node);
274 ir_node *block = be_transform_node(old_block);
275 dbg_info *dbgi = get_irn_dbg_info(node);
276 ir_mode *mode = get_irn_mode(node);
278 if (mode_is_float(mode)) {
280 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
281 ir_node *nomem = new_NoMem();
285 if (! USE_SSE2(env_cg)) {
286 cnst_classify_t clss = classify_Const(node);
288 if (clss == CNST_NULL) {
289 load = new_rd_ia32_vfldz(dbgi, irg, block);
291 } else if (clss == CNST_ONE) {
292 load = new_rd_ia32_vfld1(dbgi, irg, block);
295 floatent = get_entity_for_tv(env_cg, node);
297 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
298 set_ia32_op_type(load, ia32_AddrModeS);
299 set_ia32_am_flavour(load, ia32_am_N);
300 set_ia32_am_sc(load, floatent);
301 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
302 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
304 set_ia32_ls_mode(load, mode);
306 floatent = get_entity_for_tv(env_cg, node);
308 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
309 set_ia32_op_type(load, ia32_AddrModeS);
310 set_ia32_am_flavour(load, ia32_am_N);
311 set_ia32_am_sc(load, floatent);
312 set_ia32_ls_mode(load, mode);
313 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
315 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
318 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
320 /* Const Nodes before the initial IncSP are a bad idea, because
321 * they could be spilled and we have no SP ready at that point yet.
322 * So add a dependency to the initial frame pointer calculation to
323 * avoid that situation.
325 if (get_irg_start_block(irg) == block) {
326 add_irn_dep(load, get_irg_frame(irg));
329 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
332 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
335 if (get_irg_start_block(irg) == block) {
336 add_irn_dep(cnst, get_irg_frame(irg));
339 set_ia32_Const_attr(cnst, node);
340 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
345 return new_r_Bad(irg);
349 * Transforms a SymConst.
351 static ir_node *gen_SymConst(ir_node *node) {
352 ir_graph *irg = current_ir_graph;
353 ir_node *old_block = get_nodes_block(node);
354 ir_node *block = be_transform_node(old_block);
355 dbg_info *dbgi = get_irn_dbg_info(node);
356 ir_mode *mode = get_irn_mode(node);
359 if (mode_is_float(mode)) {
360 if (USE_SSE2(env_cg))
361 cnst = new_rd_ia32_xConst(dbgi, irg, block);
363 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
364 //set_ia32_ls_mode(cnst, mode);
365 set_ia32_ls_mode(cnst, mode_E);
367 cnst = new_rd_ia32_Const(dbgi, irg, block);
370 /* Const Nodes before the initial IncSP are a bad idea, because
371 * they could be spilled and we have no SP ready at that point yet
373 if (get_irg_start_block(irg) == block) {
374 add_irn_dep(cnst, get_irg_frame(irg));
377 set_ia32_Const_attr(cnst, node);
378 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
383 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
384 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
385 static const struct {
387 const char *ent_name;
388 const char *cnst_str;
389 } names [ia32_known_const_max] = {
390 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
391 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
392 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
393 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
395 static ir_entity *ent_cache[ia32_known_const_max];
397 const char *tp_name, *ent_name, *cnst_str;
405 ent_name = names[kct].ent_name;
406 if (! ent_cache[kct]) {
407 tp_name = names[kct].tp_name;
408 cnst_str = names[kct].cnst_str;
410 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
412 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
413 tp = new_type_primitive(new_id_from_str(tp_name), mode);
414 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
416 set_entity_ld_ident(ent, get_entity_ident(ent));
417 set_entity_visibility(ent, visibility_local);
418 set_entity_variability(ent, variability_constant);
419 set_entity_allocation(ent, allocation_static);
421 /* we create a new entity here: It's initialization must resist on the
423 rem = current_ir_graph;
424 current_ir_graph = get_const_code_irg();
425 cnst = new_Const(mode, tv);
426 current_ir_graph = rem;
428 set_atomic_ent_value(ent, cnst);
430 /* cache the entry */
431 ent_cache[kct] = ent;
434 return ent_cache[kct];
439 * Prints the old node name on cg obst and returns a pointer to it.
441 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
442 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
444 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
445 obstack_1grow(isa->name_obst, 0);
446 return obstack_finish(isa->name_obst);
450 /* determine if one operator is an Imm */
451 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
453 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
455 return is_ia32_Cnst(op2) ? op2 : NULL;
459 /* determine if one operator is not an Imm */
460 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
461 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
464 static void fold_immediate(ir_node *node, int in1, int in2) {
468 if (!(env_cg->opt & IA32_OPT_IMMOPS))
471 left = get_irn_n(node, in1);
472 right = get_irn_n(node, in2);
473 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
474 /* we can only set right operand to immediate */
475 if(!is_ia32_commutative(node))
477 /* exchange left/right */
478 set_irn_n(node, in1, right);
479 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
480 copy_ia32_Immop_attr(node, left);
481 } else if(is_ia32_Cnst(right)) {
482 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
483 copy_ia32_Immop_attr(node, right);
488 clear_ia32_commutative(node);
489 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
490 get_ia32_am_arity(node));
494 * Construct a standard binary operation, set AM and immediate if required.
496 * @param op1 The first operand
497 * @param op2 The second operand
498 * @param func The node constructor function
499 * @return The constructed ia32 node.
501 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
502 construct_binop_func *func, int commutative)
504 ir_node *block = be_transform_node(get_nodes_block(node));
505 ir_graph *irg = current_ir_graph;
506 dbg_info *dbgi = get_irn_dbg_info(node);
507 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
508 ir_node *nomem = new_NoMem();
511 ir_node *new_op1 = be_transform_node(op1);
512 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
513 if (is_ia32_Immediate(new_op2)) {
517 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
518 if (func == new_rd_ia32_IMul) {
519 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
521 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
524 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
526 set_ia32_commutative(new_node);
533 * Construct a standard binary operation, set AM and immediate if required.
535 * @param op1 The first operand
536 * @param op2 The second operand
537 * @param func The node constructor function
538 * @return The constructed ia32 node.
540 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
541 construct_binop_func *func)
543 ir_node *block = be_transform_node(get_nodes_block(node));
544 ir_node *new_op1 = be_transform_node(op1);
545 ir_node *new_op2 = be_transform_node(op2);
546 ir_node *new_node = NULL;
547 dbg_info *dbgi = get_irn_dbg_info(node);
548 ir_graph *irg = current_ir_graph;
549 ir_mode *mode = get_irn_mode(node);
550 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
551 ir_node *nomem = new_NoMem();
553 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
555 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
556 if (is_op_commutative(get_irn_op(node))) {
557 set_ia32_commutative(new_node);
559 set_ia32_ls_mode(new_node, mode);
561 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
566 static ir_node *get_fpcw(void)
569 if(initial_fpcw != NULL)
572 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
573 &ia32_fp_cw_regs[REG_FPCW]);
574 initial_fpcw = be_transform_node(fpcw);
580 * Construct a standard binary operation, set AM and immediate if required.
582 * @param op1 The first operand
583 * @param op2 The second operand
584 * @param func The node constructor function
585 * @return The constructed ia32 node.
587 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
588 construct_binop_float_func *func)
590 ir_node *block = be_transform_node(get_nodes_block(node));
591 ir_node *new_op1 = be_transform_node(op1);
592 ir_node *new_op2 = be_transform_node(op2);
593 ir_node *new_node = NULL;
594 dbg_info *dbgi = get_irn_dbg_info(node);
595 ir_graph *irg = current_ir_graph;
596 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
597 ir_node *nomem = new_NoMem();
599 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
601 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
602 if (is_op_commutative(get_irn_op(node))) {
603 set_ia32_commutative(new_node);
606 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
612 * Construct a shift/rotate binary operation, sets AM and immediate if required.
614 * @param op1 The first operand
615 * @param op2 The second operand
616 * @param func The node constructor function
617 * @return The constructed ia32 node.
619 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
620 construct_binop_func *func)
622 ir_node *block = be_transform_node(get_nodes_block(node));
623 ir_node *new_op1 = be_transform_node(op1);
625 ir_node *new_op = NULL;
626 dbg_info *dbgi = get_irn_dbg_info(node);
627 ir_graph *irg = current_ir_graph;
628 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
629 ir_node *nomem = new_NoMem();
631 assert(! mode_is_float(get_irn_mode(node))
632 && "Shift/Rotate with float not supported");
634 new_op2 = create_immediate_or_transform(op2, 'N');
636 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
639 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
641 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
643 set_ia32_emit_cl(new_op);
650 * Construct a standard unary operation, set AM and immediate if required.
652 * @param op The operand
653 * @param func The node constructor function
654 * @return The constructed ia32 node.
656 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
658 ir_node *block = be_transform_node(get_nodes_block(node));
659 ir_node *new_op = be_transform_node(op);
660 ir_node *new_node = NULL;
661 ir_graph *irg = current_ir_graph;
662 dbg_info *dbgi = get_irn_dbg_info(node);
663 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
664 ir_node *nomem = new_NoMem();
666 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
667 DB((dbg, LEVEL_1, "INT unop ..."));
668 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
670 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
676 * Creates an ia32 Add.
678 * @return the created ia32 Add node
680 static ir_node *gen_Add(ir_node *node) {
681 ir_node *block = be_transform_node(get_nodes_block(node));
682 ir_node *op1 = get_Add_left(node);
683 ir_node *new_op1 = be_transform_node(op1);
684 ir_node *op2 = get_Add_right(node);
685 ir_node *new_op2 = be_transform_node(op2);
686 ir_node *new_op = NULL;
687 ir_graph *irg = current_ir_graph;
688 dbg_info *dbgi = get_irn_dbg_info(node);
689 ir_mode *mode = get_irn_mode(node);
690 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
691 ir_node *nomem = new_NoMem();
692 ir_node *expr_op, *imm_op;
694 /* Check if immediate optimization is on and */
695 /* if it's an operation with immediate. */
696 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
697 expr_op = get_expr_op(new_op1, new_op2);
699 assert((expr_op || imm_op) && "invalid operands");
701 if (mode_is_float(mode)) {
702 if (USE_SSE2(env_cg))
703 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
705 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
710 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
711 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
713 /* No expr_op means, that we have two const - one symconst and */
714 /* one tarval or another symconst - because this case is not */
715 /* covered by constant folding */
716 /* We need to check for: */
717 /* 1) symconst + const -> becomes a LEA */
718 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
719 /* linker doesn't support two symconsts */
721 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
722 /* this is the 2nd case */
723 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
724 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
725 set_ia32_am_flavour(new_op, ia32_am_B);
726 set_ia32_op_type(new_op, ia32_AddrModeS);
728 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
729 } else if (tp1 == ia32_ImmSymConst) {
730 tarval *tv = get_ia32_Immop_tarval(new_op2);
731 long offs = get_tarval_long(tv);
733 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
734 add_irn_dep(new_op, get_irg_frame(irg));
735 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
737 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
738 add_ia32_am_offs_int(new_op, offs);
739 set_ia32_am_flavour(new_op, ia32_am_OB);
740 set_ia32_op_type(new_op, ia32_AddrModeS);
741 } else if (tp2 == ia32_ImmSymConst) {
742 tarval *tv = get_ia32_Immop_tarval(new_op1);
743 long offs = get_tarval_long(tv);
745 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
746 add_irn_dep(new_op, get_irg_frame(irg));
747 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
749 add_ia32_am_offs_int(new_op, offs);
750 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
751 set_ia32_am_flavour(new_op, ia32_am_OB);
752 set_ia32_op_type(new_op, ia32_AddrModeS);
754 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
755 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
756 tarval *restv = tarval_add(tv1, tv2);
758 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
760 new_op = new_rd_ia32_Const(dbgi, irg, block);
761 set_ia32_Const_tarval(new_op, restv);
762 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
765 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
768 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
769 tarval_classification_t class_tv, class_negtv;
770 tarval *tv = get_ia32_Immop_tarval(imm_op);
772 /* optimize tarvals */
773 class_tv = classify_tarval(tv);
774 class_negtv = classify_tarval(tarval_neg(tv));
776 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
777 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
778 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
779 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
781 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
782 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
783 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
784 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
790 /* This is a normal add */
791 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
794 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
795 set_ia32_commutative(new_op);
797 fold_immediate(new_op, 2, 3);
799 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
805 * Creates an ia32 Mul.
807 * @return the created ia32 Mul node
809 static ir_node *gen_Mul(ir_node *node) {
810 ir_node *op1 = get_Mul_left(node);
811 ir_node *op2 = get_Mul_right(node);
812 ir_mode *mode = get_irn_mode(node);
814 if (mode_is_float(mode)) {
815 if (USE_SSE2(env_cg))
816 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
818 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
822 for the lower 32bit of the result it doesn't matter whether we use
823 signed or unsigned multiplication so we use IMul as it has fewer
826 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
830 * Creates an ia32 Mulh.
831 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
832 * this result while Mul returns the lower 32 bit.
834 * @return the created ia32 Mulh node
836 static ir_node *gen_Mulh(ir_node *node) {
837 ir_node *block = be_transform_node(get_nodes_block(node));
838 ir_node *op1 = get_irn_n(node, 0);
839 ir_node *new_op1 = be_transform_node(op1);
840 ir_node *op2 = get_irn_n(node, 1);
841 ir_node *new_op2 = be_transform_node(op2);
842 ir_graph *irg = current_ir_graph;
843 dbg_info *dbgi = get_irn_dbg_info(node);
844 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
845 ir_mode *mode = get_irn_mode(node);
846 ir_node *proj_EDX, *res;
848 assert(!mode_is_float(mode) && "Mulh with float not supported");
849 if (mode_is_signed(mode)) {
850 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
851 new_op2, new_NoMem());
853 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
857 set_ia32_commutative(res);
858 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
860 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
868 * Creates an ia32 And.
870 * @return The created ia32 And node
872 static ir_node *gen_And(ir_node *node) {
873 ir_node *op1 = get_And_left(node);
874 ir_node *op2 = get_And_right(node);
876 assert (! mode_is_float(get_irn_mode(node)));
877 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
883 * Creates an ia32 Or.
885 * @return The created ia32 Or node
887 static ir_node *gen_Or(ir_node *node) {
888 ir_node *op1 = get_Or_left(node);
889 ir_node *op2 = get_Or_right(node);
891 assert (! mode_is_float(get_irn_mode(node)));
892 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
898 * Creates an ia32 Eor.
900 * @return The created ia32 Eor node
902 static ir_node *gen_Eor(ir_node *node) {
903 ir_node *op1 = get_Eor_left(node);
904 ir_node *op2 = get_Eor_right(node);
906 assert(! mode_is_float(get_irn_mode(node)));
907 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
912 * Creates an ia32 Sub.
914 * @return The created ia32 Sub node
916 static ir_node *gen_Sub(ir_node *node) {
917 ir_node *block = be_transform_node(get_nodes_block(node));
918 ir_node *op1 = get_Sub_left(node);
919 ir_node *new_op1 = be_transform_node(op1);
920 ir_node *op2 = get_Sub_right(node);
921 ir_node *new_op2 = be_transform_node(op2);
922 ir_node *new_op = NULL;
923 ir_graph *irg = current_ir_graph;
924 dbg_info *dbgi = get_irn_dbg_info(node);
925 ir_mode *mode = get_irn_mode(node);
926 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
927 ir_node *nomem = new_NoMem();
928 ir_node *expr_op, *imm_op;
930 /* Check if immediate optimization is on and */
931 /* if it's an operation with immediate. */
932 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
933 expr_op = get_expr_op(new_op1, new_op2);
935 assert((expr_op || imm_op) && "invalid operands");
937 if (mode_is_float(mode)) {
938 if (USE_SSE2(env_cg))
939 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
941 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
946 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
947 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
949 /* No expr_op means, that we have two const - one symconst and */
950 /* one tarval or another symconst - because this case is not */
951 /* covered by constant folding */
952 /* We need to check for: */
953 /* 1) symconst - const -> becomes a LEA */
954 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
955 /* linker doesn't support two symconsts */
956 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
957 /* this is the 2nd case */
958 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
959 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
960 set_ia32_am_sc_sign(new_op);
961 set_ia32_am_flavour(new_op, ia32_am_B);
963 DBG_OPT_LEA3(op1, op2, node, new_op);
964 } else if (tp1 == ia32_ImmSymConst) {
965 tarval *tv = get_ia32_Immop_tarval(new_op2);
966 long offs = get_tarval_long(tv);
968 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
969 add_irn_dep(new_op, get_irg_frame(irg));
970 DBG_OPT_LEA3(op1, op2, node, new_op);
972 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
973 add_ia32_am_offs_int(new_op, -offs);
974 set_ia32_am_flavour(new_op, ia32_am_OB);
975 set_ia32_op_type(new_op, ia32_AddrModeS);
976 } else if (tp2 == ia32_ImmSymConst) {
977 tarval *tv = get_ia32_Immop_tarval(new_op1);
978 long offs = get_tarval_long(tv);
980 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
981 add_irn_dep(new_op, get_irg_frame(irg));
982 DBG_OPT_LEA3(op1, op2, node, new_op);
984 add_ia32_am_offs_int(new_op, offs);
985 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
986 set_ia32_am_sc_sign(new_op);
987 set_ia32_am_flavour(new_op, ia32_am_OB);
988 set_ia32_op_type(new_op, ia32_AddrModeS);
990 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
991 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
992 tarval *restv = tarval_sub(tv1, tv2);
994 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
996 new_op = new_rd_ia32_Const(dbgi, irg, block);
997 set_ia32_Const_tarval(new_op, restv);
998 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1001 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1003 } else if (imm_op) {
1004 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1005 tarval_classification_t class_tv, class_negtv;
1006 tarval *tv = get_ia32_Immop_tarval(imm_op);
1008 /* optimize tarvals */
1009 class_tv = classify_tarval(tv);
1010 class_negtv = classify_tarval(tarval_neg(tv));
1012 if (class_tv == TV_CLASSIFY_ONE) {
1013 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1014 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1015 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1017 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1018 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1019 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1020 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1026 /* This is a normal sub */
1027 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1029 /* set AM support */
1030 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1032 fold_immediate(new_op, 2, 3);
1034 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1042 * Generates an ia32 DivMod with additional infrastructure for the
1043 * register allocator if needed.
1045 * @param dividend -no comment- :)
1046 * @param divisor -no comment- :)
1047 * @param dm_flav flavour_Div/Mod/DivMod
1048 * @return The created ia32 DivMod node
1050 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1051 ir_node *divisor, ia32_op_flavour_t dm_flav)
1053 ir_node *block = be_transform_node(get_nodes_block(node));
1054 ir_node *new_dividend = be_transform_node(dividend);
1055 ir_node *new_divisor = be_transform_node(divisor);
1056 ir_graph *irg = current_ir_graph;
1057 dbg_info *dbgi = get_irn_dbg_info(node);
1058 ir_mode *mode = get_irn_mode(node);
1059 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1060 ir_node *res, *proj_div, *proj_mod;
1061 ir_node *sign_extension;
1062 ir_node *mem, *new_mem;
1063 ir_node *projs[pn_DivMod_max];
1066 ia32_collect_Projs(node, projs, pn_DivMod_max);
1068 proj_div = proj_mod = NULL;
1072 mem = get_Div_mem(node);
1073 mode = get_Div_resmode(node);
1074 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1075 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1078 mem = get_Mod_mem(node);
1079 mode = get_Mod_resmode(node);
1080 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1081 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1083 case flavour_DivMod:
1084 mem = get_DivMod_mem(node);
1085 mode = get_DivMod_resmode(node);
1086 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1087 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1088 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1091 panic("invalid divmod flavour!");
1093 new_mem = be_transform_node(mem);
1095 if (mode_is_signed(mode)) {
1096 /* in signed mode, we need to sign extend the dividend */
1097 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1098 add_irn_dep(produceval, get_irg_frame(irg));
1099 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1102 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1103 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1105 add_irn_dep(sign_extension, get_irg_frame(irg));
1108 if (mode_is_signed(mode)) {
1109 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1110 sign_extension, new_divisor, new_mem, dm_flav);
1112 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1113 sign_extension, new_divisor, new_mem, dm_flav);
1116 set_ia32_exc_label(res, has_exc);
1117 set_irn_pinned(res, get_irn_pinned(node));
1118 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1120 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1127 * Wrapper for generate_DivMod. Sets flavour_Mod.
1130 static ir_node *gen_Mod(ir_node *node) {
1131 return generate_DivMod(node, get_Mod_left(node),
1132 get_Mod_right(node), flavour_Mod);
1136 * Wrapper for generate_DivMod. Sets flavour_Div.
1139 static ir_node *gen_Div(ir_node *node) {
1140 return generate_DivMod(node, get_Div_left(node),
1141 get_Div_right(node), flavour_Div);
1145 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1147 static ir_node *gen_DivMod(ir_node *node) {
1148 return generate_DivMod(node, get_DivMod_left(node),
1149 get_DivMod_right(node), flavour_DivMod);
1155 * Creates an ia32 floating Div.
1157 * @return The created ia32 xDiv node
1159 static ir_node *gen_Quot(ir_node *node) {
1160 ir_node *block = be_transform_node(get_nodes_block(node));
1161 ir_node *op1 = get_Quot_left(node);
1162 ir_node *new_op1 = be_transform_node(op1);
1163 ir_node *op2 = get_Quot_right(node);
1164 ir_node *new_op2 = be_transform_node(op2);
1165 ir_graph *irg = current_ir_graph;
1166 dbg_info *dbgi = get_irn_dbg_info(node);
1167 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1168 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1171 if (USE_SSE2(env_cg)) {
1172 ir_mode *mode = get_irn_mode(op1);
1173 if (is_ia32_xConst(new_op2)) {
1174 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1175 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1176 copy_ia32_Immop_attr(new_op, new_op2);
1178 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1179 // Matze: disabled for now, spillslot coalescer fails
1180 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1182 set_ia32_ls_mode(new_op, mode);
1184 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1185 new_op2, nomem, get_fpcw());
1186 // Matze: disabled for now (spillslot coalescer fails)
1187 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1189 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1195 * Creates an ia32 Shl.
1197 * @return The created ia32 Shl node
1199 static ir_node *gen_Shl(ir_node *node) {
1200 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1207 * Creates an ia32 Shr.
1209 * @return The created ia32 Shr node
1211 static ir_node *gen_Shr(ir_node *node) {
1212 return gen_shift_binop(node, get_Shr_left(node),
1213 get_Shr_right(node), new_rd_ia32_Shr);
1219 * Creates an ia32 Sar.
1221 * @return The created ia32 Shrs node
1223 static ir_node *gen_Shrs(ir_node *node) {
1224 ir_node *left = get_Shrs_left(node);
1225 ir_node *right = get_Shrs_right(node);
1226 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1227 tarval *tv = get_Const_tarval(right);
1228 long val = get_tarval_long(tv);
1230 /* this is a sign extension */
1231 ir_graph *irg = current_ir_graph;
1232 dbg_info *dbgi = get_irn_dbg_info(node);
1233 ir_node *block = be_transform_node(get_nodes_block(node));
1235 ir_node *new_op = be_transform_node(op);
1236 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1237 add_irn_dep(pval, get_irg_frame(irg));
1239 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1243 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1249 * Creates an ia32 RotL.
1251 * @param op1 The first operator
1252 * @param op2 The second operator
1253 * @return The created ia32 RotL node
1255 static ir_node *gen_RotL(ir_node *node,
1256 ir_node *op1, ir_node *op2) {
1257 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1263 * Creates an ia32 RotR.
1264 * NOTE: There is no RotR with immediate because this would always be a RotL
1265 * "imm-mode_size_bits" which can be pre-calculated.
1267 * @param op1 The first operator
1268 * @param op2 The second operator
1269 * @return The created ia32 RotR node
1271 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1273 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1279 * Creates an ia32 RotR or RotL (depending on the found pattern).
1281 * @return The created ia32 RotL or RotR node
1283 static ir_node *gen_Rot(ir_node *node) {
1284 ir_node *rotate = NULL;
1285 ir_node *op1 = get_Rot_left(node);
1286 ir_node *op2 = get_Rot_right(node);
1288 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1289 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1290 that means we can create a RotR instead of an Add and a RotL */
1292 if (get_irn_op(op2) == op_Add) {
1294 ir_node *left = get_Add_left(add);
1295 ir_node *right = get_Add_right(add);
1296 if (is_Const(right)) {
1297 tarval *tv = get_Const_tarval(right);
1298 ir_mode *mode = get_irn_mode(node);
1299 long bits = get_mode_size_bits(mode);
1301 if (get_irn_op(left) == op_Minus &&
1302 tarval_is_long(tv) &&
1303 get_tarval_long(tv) == bits)
1305 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1306 rotate = gen_RotR(node, op1, get_Minus_op(left));
1311 if (rotate == NULL) {
1312 rotate = gen_RotL(node, op1, op2);
1321 * Transforms a Minus node.
1323 * @param op The Minus operand
1324 * @return The created ia32 Minus node
1326 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1327 ir_node *block = be_transform_node(get_nodes_block(node));
1328 ir_graph *irg = current_ir_graph;
1329 dbg_info *dbgi = get_irn_dbg_info(node);
1330 ir_mode *mode = get_irn_mode(node);
1335 if (mode_is_float(mode)) {
1336 ir_node *new_op = be_transform_node(op);
1337 if (USE_SSE2(env_cg)) {
1338 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1339 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1340 ir_node *nomem = new_rd_NoMem(irg);
1342 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1344 size = get_mode_size_bits(mode);
1345 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1347 set_ia32_am_sc(res, ent);
1348 set_ia32_op_type(res, ia32_AddrModeS);
1349 set_ia32_ls_mode(res, mode);
1351 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1354 res = gen_unop(node, op, new_rd_ia32_Neg);
1357 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1363 * Transforms a Minus node.
1365 * @return The created ia32 Minus node
1367 static ir_node *gen_Minus(ir_node *node) {
1368 return gen_Minus_ex(node, get_Minus_op(node));
1371 static ir_node *gen_bin_Not(ir_node *node)
1373 ir_graph *irg = current_ir_graph;
1374 dbg_info *dbgi = get_irn_dbg_info(node);
1375 ir_node *block = be_transform_node(get_nodes_block(node));
1376 ir_node *op = get_Not_op(node);
1377 ir_node *new_op = be_transform_node(op);
1378 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1379 ir_node *nomem = new_NoMem();
1380 ir_node *one = new_rd_ia32_Immediate(dbgi, irg, block, NULL, 0, 1);
1381 arch_set_irn_register(env_cg->arch_env, one, &ia32_gp_regs[REG_GP_NOREG]);
1383 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1387 * Transforms a Not node.
1389 * @return The created ia32 Not node
1391 static ir_node *gen_Not(ir_node *node) {
1392 ir_node *op = get_Not_op(node);
1393 ir_mode *mode = get_irn_mode(node);
1395 if(mode == mode_b) {
1396 return gen_bin_Not(node);
1399 assert (! mode_is_float(get_irn_mode(node)));
1400 return gen_unop(node, op, new_rd_ia32_Not);
1406 * Transforms an Abs node.
1408 * @return The created ia32 Abs node
1410 static ir_node *gen_Abs(ir_node *node) {
1411 ir_node *block = be_transform_node(get_nodes_block(node));
1412 ir_node *op = get_Abs_op(node);
1413 ir_node *new_op = be_transform_node(op);
1414 ir_graph *irg = current_ir_graph;
1415 dbg_info *dbgi = get_irn_dbg_info(node);
1416 ir_mode *mode = get_irn_mode(node);
1417 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1418 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1419 ir_node *nomem = new_NoMem();
1424 if (mode_is_float(mode)) {
1425 if (USE_SSE2(env_cg)) {
1426 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1428 size = get_mode_size_bits(mode);
1429 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1431 set_ia32_am_sc(res, ent);
1433 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1435 set_ia32_op_type(res, ia32_AddrModeS);
1436 set_ia32_ls_mode(res, mode);
1439 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1440 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1444 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1445 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1448 add_irn_dep(pval, get_irg_frame(irg));
1449 SET_IA32_ORIG_NODE(sign_extension,
1450 ia32_get_old_node_name(env_cg, node));
1452 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1453 sign_extension, nomem);
1454 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1456 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1457 sign_extension, nomem);
1458 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1467 * Transforms a Load.
1469 * @return the created ia32 Load node
1471 static ir_node *gen_Load(ir_node *node) {
1472 ir_node *old_block = get_nodes_block(node);
1473 ir_node *block = be_transform_node(old_block);
1474 ir_node *ptr = get_Load_ptr(node);
1475 ir_node *new_ptr = be_transform_node(ptr);
1476 ir_node *mem = get_Load_mem(node);
1477 ir_node *new_mem = be_transform_node(mem);
1478 ir_graph *irg = current_ir_graph;
1479 dbg_info *dbgi = get_irn_dbg_info(node);
1480 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1481 ir_mode *mode = get_Load_mode(node);
1483 ir_node *lptr = new_ptr;
1486 ia32_am_flavour_t am_flav = ia32_am_B;
1488 /* address might be a constant (symconst or absolute address) */
1489 if (is_ia32_Const(new_ptr)) {
1494 if (mode_is_float(mode)) {
1495 if (USE_SSE2(env_cg)) {
1496 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1497 res_mode = mode_xmm;
1499 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1500 res_mode = mode_vfp;
1506 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1510 /* base is a constant address */
1512 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1513 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1514 am_flav = ia32_am_N;
1516 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1517 long offs = get_tarval_long(tv);
1519 add_ia32_am_offs_int(new_op, offs);
1520 am_flav = ia32_am_O;
1524 set_irn_pinned(new_op, get_irn_pinned(node));
1525 set_ia32_op_type(new_op, ia32_AddrModeS);
1526 set_ia32_am_flavour(new_op, am_flav);
1527 set_ia32_ls_mode(new_op, mode);
1529 /* make sure we are scheduled behind the initial IncSP/Barrier
1530 * to avoid spills being placed before it
1532 if (block == get_irg_start_block(irg)) {
1533 add_irn_dep(new_op, get_irg_frame(irg));
1536 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1537 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1545 * Transforms a Store.
1547 * @return the created ia32 Store node
1549 static ir_node *gen_Store(ir_node *node) {
1550 ir_node *block = be_transform_node(get_nodes_block(node));
1551 ir_node *ptr = get_Store_ptr(node);
1552 ir_node *new_ptr = be_transform_node(ptr);
1553 ir_node *val = get_Store_value(node);
1555 ir_node *mem = get_Store_mem(node);
1556 ir_node *new_mem = be_transform_node(mem);
1557 ir_graph *irg = current_ir_graph;
1558 dbg_info *dbgi = get_irn_dbg_info(node);
1559 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1560 ir_node *sptr = new_ptr;
1561 ir_mode *mode = get_irn_mode(val);
1564 ia32_am_flavour_t am_flav = ia32_am_B;
1566 /* address might be a constant (symconst or absolute address) */
1567 if (is_ia32_Const(new_ptr)) {
1572 if (mode_is_float(mode)) {
1573 new_val = be_transform_node(val);
1574 if (USE_SSE2(env_cg)) {
1575 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1578 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1582 new_val = create_immediate_or_transform(val, 0);
1586 if (get_mode_size_bits(mode) == 8) {
1587 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1590 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1595 /* base is an constant address */
1597 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1598 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1599 am_flav = ia32_am_N;
1601 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1602 long offs = get_tarval_long(tv);
1604 add_ia32_am_offs_int(new_op, offs);
1605 am_flav = ia32_am_O;
1609 set_irn_pinned(new_op, get_irn_pinned(node));
1610 set_ia32_op_type(new_op, ia32_AddrModeD);
1611 set_ia32_am_flavour(new_op, am_flav);
1612 set_ia32_ls_mode(new_op, mode);
1614 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1615 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1620 static ir_node *maybe_scale_up(ir_node *new_op, ir_mode *mode, dbg_info *dbgi)
1625 if(get_mode_size_bits(mode) == 32)
1629 if(is_ia32_Immediate(new_op))
1632 if(mode_is_signed(mode))
1637 block = get_nodes_block(new_op);
1638 return create_I2I_Conv(mode, tgt_mode, dbgi, block, new_op);
1641 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1642 ir_node *cmp_left, ir_node *cmp_right)
1644 ir_node *new_cmp_left;
1645 ir_node *new_cmp_right;
1652 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1654 if(cmp_right != NULL && !is_Const_0(cmp_right))
1657 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1658 and_left = get_And_left(cmp_left);
1659 and_right = get_And_right(cmp_left);
1661 mode = get_irn_mode(and_left);
1662 new_cmp_left = be_transform_node(and_left);
1663 new_cmp_right = create_immediate_or_transform(and_right, 0);
1665 mode = get_irn_mode(cmp_left);
1666 new_cmp_left = be_transform_node(cmp_left);
1667 new_cmp_right = be_transform_node(cmp_left);
1670 assert(get_mode_size_bits(mode) <= 32);
1671 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1672 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1673 noreg = ia32_new_NoReg_gp(env_cg);
1674 nomem = new_NoMem();
1676 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1677 new_cmp_left, new_cmp_right, nomem, pnc);
1678 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1683 static ir_node *create_Switch(ir_node *node)
1685 ir_graph *irg = current_ir_graph;
1686 dbg_info *dbgi = get_irn_dbg_info(node);
1687 ir_node *block = be_transform_node(get_nodes_block(node));
1688 ir_node *sel = get_Cond_selector(node);
1689 ir_node *new_sel = be_transform_node(sel);
1691 int switch_min = INT_MAX;
1692 const ir_edge_t *edge;
1694 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1696 /* determine the smallest switch case value */
1697 foreach_out_edge(node, edge) {
1698 ir_node *proj = get_edge_src_irn(edge);
1699 int pn = get_Proj_proj(proj);
1704 if (switch_min != 0) {
1705 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1707 /* if smallest switch case is not 0 we need an additional sub */
1708 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1709 add_ia32_am_offs_int(new_sel, -switch_min);
1710 set_ia32_am_flavour(new_sel, ia32_am_OB);
1711 set_ia32_op_type(new_sel, ia32_AddrModeS);
1713 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1716 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1717 set_ia32_pncode(res, get_Cond_defaultProj(node));
1719 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1725 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1727 * @return The transformed node.
1729 static ir_node *gen_Cond(ir_node *node) {
1730 ir_node *block = be_transform_node(get_nodes_block(node));
1731 ir_graph *irg = current_ir_graph;
1732 dbg_info *dbgi = get_irn_dbg_info(node);
1733 ir_node *sel = get_Cond_selector(node);
1734 ir_mode *sel_mode = get_irn_mode(sel);
1735 ir_node *res = NULL;
1736 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1743 ir_node *nomem = new_NoMem();
1746 if (sel_mode != mode_b) {
1747 return create_Switch(node);
1750 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
1751 /* it's some mode_b value but not a direct comparison -> create a
1753 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
1754 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1758 cmp = get_Proj_pred(sel);
1759 cmp_a = get_Cmp_left(cmp);
1760 cmp_b = get_Cmp_right(cmp);
1761 cmp_mode = get_irn_mode(cmp_a);
1762 pnc = get_Proj_proj(sel);
1763 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1764 pnc |= ia32_pn_Cmp_Unsigned;
1767 if(mode_needs_gp_reg(cmp_mode)) {
1768 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b);
1770 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1775 new_cmp_a = be_transform_node(cmp_a);
1776 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1778 if (mode_is_float(cmp_mode)) {
1779 if (USE_SSE2(env_cg)) {
1780 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1782 set_ia32_commutative(res);
1783 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1784 set_ia32_ls_mode(res, cmp_mode);
1786 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1787 set_ia32_commutative(res);
1790 /** workaround smaller compare modes with converts...
1791 * We could easily support 16bit compares, for 8 bit we have to set
1792 * additional register constraints, which we don't do yet
1794 new_cmp_a = maybe_scale_up(new_cmp_a, cmp_mode, dbgi);
1795 new_cmp_b = maybe_scale_up(new_cmp_b, cmp_mode, dbgi);
1797 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1798 new_cmp_a, new_cmp_b, nomem, pnc);
1799 set_ia32_commutative(res);
1800 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1803 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1811 * Transforms a CopyB node.
1813 * @return The transformed node.
1815 static ir_node *gen_CopyB(ir_node *node) {
1816 ir_node *block = be_transform_node(get_nodes_block(node));
1817 ir_node *src = get_CopyB_src(node);
1818 ir_node *new_src = be_transform_node(src);
1819 ir_node *dst = get_CopyB_dst(node);
1820 ir_node *new_dst = be_transform_node(dst);
1821 ir_node *mem = get_CopyB_mem(node);
1822 ir_node *new_mem = be_transform_node(mem);
1823 ir_node *res = NULL;
1824 ir_graph *irg = current_ir_graph;
1825 dbg_info *dbgi = get_irn_dbg_info(node);
1826 int size = get_type_size_bytes(get_CopyB_type(node));
1829 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1830 /* then we need the size explicitly in ECX. */
1831 if (size >= 32 * 4) {
1832 rem = size & 0x3; /* size % 4 */
1835 res = new_rd_ia32_Const(dbgi, irg, block);
1836 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1837 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1839 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1840 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1842 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1843 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1846 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1852 ir_node *gen_be_Copy(ir_node *node)
1854 ir_node *result = be_duplicate_node(node);
1855 ir_mode *mode = get_irn_mode(result);
1857 if (mode_needs_gp_reg(mode)) {
1858 set_irn_mode(result, mode_Iu);
1865 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1866 dbg_info *dbgi, ir_node *block)
1868 ir_graph *irg = current_ir_graph;
1869 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1870 ir_node *nomem = new_rd_NoMem(irg);
1872 ir_node *new_cmp_left;
1873 ir_node *new_cmp_right;
1876 /* can we use a test instruction? */
1877 if(cmp_right == NULL || is_Const_0(cmp_right)) {
1878 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1879 if(is_And(cmp_left) &&
1880 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1881 ir_node *and_left = get_And_left(cmp_left);
1882 ir_node *and_right = get_And_right(cmp_left);
1884 mode = get_irn_mode(and_left);
1885 new_cmp_left = be_transform_node(and_left);
1886 new_cmp_right = create_immediate_or_transform(and_right, 0);
1888 mode = get_irn_mode(cmp_left);
1889 new_cmp_left = be_transform_node(cmp_left);
1890 new_cmp_right = be_transform_node(cmp_left);
1893 assert(get_mode_size_bits(mode) <= 32);
1894 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1895 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1897 res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
1898 new_cmp_left, new_cmp_right, nomem, pnc);
1899 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1904 mode = get_irn_mode(cmp_left);
1906 new_cmp_left = be_transform_node(cmp_left);
1907 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1909 assert(get_mode_size_bits(mode) <= 32);
1910 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1911 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1913 res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
1914 new_cmp_left, new_cmp_right, nomem, pnc);
1919 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1920 ir_node *val_true, ir_node *val_false,
1921 dbg_info *dbgi, ir_node *block)
1923 ir_graph *irg = current_ir_graph;
1924 ir_node *new_val_true = be_transform_node(val_true);
1925 ir_node *new_val_false = be_transform_node(val_false);
1926 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1927 ir_node *nomem = new_NoMem();
1928 ir_node *new_cmp_left;
1929 ir_node *new_cmp_right;
1932 /* cmovs with unknowns are pointless... */
1933 if(is_Unknown(val_true)) {
1934 #ifdef DEBUG_libfirm
1935 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1937 return new_val_false;
1939 if(is_Unknown(val_false)) {
1940 #ifdef DEBUG_libfirm
1941 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1943 return new_val_true;
1946 /* can we use a test instruction? */
1947 if(is_Const_0(cmp_right)) {
1948 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1949 if(is_And(cmp_left) &&
1950 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1951 ir_node *and_left = get_And_left(cmp_left);
1952 ir_node *and_right = get_And_right(cmp_left);
1954 new_cmp_left = be_transform_node(and_left);
1955 new_cmp_right = create_immediate_or_transform(and_right, 0);
1957 new_cmp_left = be_transform_node(cmp_left);
1958 new_cmp_right = be_transform_node(cmp_left);
1961 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, block, noreg, noreg,
1962 new_cmp_left, new_cmp_right, nomem,
1963 new_val_true, new_val_false, pnc);
1964 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1969 new_cmp_left = be_transform_node(cmp_left);
1970 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1972 res = new_rd_ia32_CmpCMov(dbgi, irg, block, noreg, noreg, new_cmp_left,
1973 new_cmp_right, nomem, new_val_true, new_val_false,
1975 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1982 * Transforms a Psi node into CMov.
1984 * @return The transformed node.
1986 static ir_node *gen_Psi(ir_node *node) {
1987 ir_node *psi_true = get_Psi_val(node, 0);
1988 ir_node *psi_default = get_Psi_default(node);
1989 ia32_code_gen_t *cg = env_cg;
1990 ir_node *cond = get_Psi_cond(node, 0);
1991 ir_node *block = be_transform_node(get_nodes_block(node));
1992 dbg_info *dbgi = get_irn_dbg_info(node);
1999 assert(get_Psi_n_conds(node) == 1);
2000 assert(get_irn_mode(cond) == mode_b);
2002 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
2003 /* a mode_b value, we have to compare it against 0 */
2005 cmp_right = new_Const_long(mode_Iu, 0);
2009 ir_node *cmp = get_Proj_pred(cond);
2011 cmp_left = get_Cmp_left(cmp);
2012 cmp_right = get_Cmp_right(cmp);
2013 cmp_mode = get_irn_mode(cmp_left);
2014 pnc = get_Proj_proj(cond);
2016 assert(!mode_is_float(cmp_mode));
2018 if (!mode_is_signed(cmp_mode)) {
2019 pnc |= ia32_pn_Cmp_Unsigned;
2023 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2024 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2025 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2026 pnc = get_negated_pnc(pnc, cmp_mode);
2027 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2029 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
2032 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2038 * Following conversion rules apply:
2042 * 1) n bit -> m bit n > m (downscale)
2044 * 2) n bit -> m bit n == m (sign change)
2046 * 3) n bit -> m bit n < m (upscale)
2047 * a) source is signed: movsx
2048 * b) source is unsigned: and with lower bits sets
2052 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2056 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2060 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2061 * x87 is mode_E internally, conversions happen only at load and store
2062 * in non-strict semantic
2066 * Create a conversion from x87 state register to general purpose.
2068 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2069 ir_node *block = be_transform_node(get_nodes_block(node));
2070 ir_node *op = get_Conv_op(node);
2071 ir_node *new_op = be_transform_node(op);
2072 ia32_code_gen_t *cg = env_cg;
2073 ir_graph *irg = current_ir_graph;
2074 dbg_info *dbgi = get_irn_dbg_info(node);
2075 ir_node *noreg = ia32_new_NoReg_gp(cg);
2076 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2077 ir_node *fist, *load;
2080 fist = new_rd_ia32_vfist(dbgi, irg, block,
2081 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2083 set_irn_pinned(fist, op_pin_state_floats);
2084 set_ia32_use_frame(fist);
2085 set_ia32_op_type(fist, ia32_AddrModeD);
2086 set_ia32_am_flavour(fist, ia32_am_B);
2087 set_ia32_ls_mode(fist, mode_Iu);
2088 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2091 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2093 set_irn_pinned(load, op_pin_state_floats);
2094 set_ia32_use_frame(load);
2095 set_ia32_op_type(load, ia32_AddrModeS);
2096 set_ia32_am_flavour(load, ia32_am_B);
2097 set_ia32_ls_mode(load, mode_Iu);
2098 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2100 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2103 static ir_node *create_strict_conv(ir_mode *tgt_mode, ir_node *node)
2105 ir_node *block = get_nodes_block(node);
2106 ir_graph *irg = current_ir_graph;
2107 dbg_info *dbgi = get_irn_dbg_info(node);
2108 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2109 ir_node *nomem = new_NoMem();
2110 ir_node *frame = get_irg_frame(irg);
2111 ir_node *store, *load;
2114 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2116 set_ia32_use_frame(store);
2117 set_ia32_op_type(store, ia32_AddrModeD);
2118 set_ia32_am_flavour(store, ia32_am_OB);
2119 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2121 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2123 set_ia32_use_frame(load);
2124 set_ia32_op_type(load, ia32_AddrModeS);
2125 set_ia32_am_flavour(load, ia32_am_OB);
2126 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2128 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2133 * Create a conversion from general purpose to x87 register
2135 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2136 ir_node *block = be_transform_node(get_nodes_block(node));
2137 ir_node *op = get_Conv_op(node);
2138 ir_node *new_op = be_transform_node(op);
2139 ir_graph *irg = current_ir_graph;
2140 dbg_info *dbgi = get_irn_dbg_info(node);
2141 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2142 ir_node *nomem = new_NoMem();
2143 ir_node *fild, *store;
2147 /* first convert to 32 bit if necessary */
2148 src_bits = get_mode_size_bits(src_mode);
2149 if (src_bits == 8) {
2150 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2151 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2152 set_ia32_ls_mode(new_op, src_mode);
2153 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2154 } else if (src_bits < 32) {
2155 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2156 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2157 set_ia32_ls_mode(new_op, src_mode);
2158 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2162 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2164 set_ia32_use_frame(store);
2165 set_ia32_op_type(store, ia32_AddrModeD);
2166 set_ia32_am_flavour(store, ia32_am_OB);
2167 set_ia32_ls_mode(store, mode_Iu);
2170 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2172 set_ia32_use_frame(fild);
2173 set_ia32_op_type(fild, ia32_AddrModeS);
2174 set_ia32_am_flavour(fild, ia32_am_OB);
2175 set_ia32_ls_mode(fild, mode_Iu);
2177 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2182 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2183 dbg_info *dbgi, ir_node *new_block,
2186 ir_graph *irg = current_ir_graph;
2187 int src_bits = get_mode_size_bits(src_mode);
2188 int tgt_bits = get_mode_size_bits(tgt_mode);
2189 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2190 ir_node *nomem = new_rd_NoMem(irg);
2192 ir_mode *smaller_mode;
2195 if (src_bits < tgt_bits) {
2196 smaller_mode = src_mode;
2197 smaller_bits = src_bits;
2199 smaller_mode = tgt_mode;
2200 smaller_bits = tgt_bits;
2203 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2204 if (smaller_bits == 8) {
2205 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2207 set_ia32_ls_mode(res, smaller_mode);
2209 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, noreg, noreg, new_op,
2211 set_ia32_ls_mode(res, smaller_mode);
2213 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2219 * Transforms a Conv node.
2221 * @return The created ia32 Conv node
2223 static ir_node *gen_Conv(ir_node *node) {
2224 ir_node *block = be_transform_node(get_nodes_block(node));
2225 ir_node *op = get_Conv_op(node);
2226 ir_node *new_op = be_transform_node(op);
2227 ir_graph *irg = current_ir_graph;
2228 dbg_info *dbgi = get_irn_dbg_info(node);
2229 ir_mode *src_mode = get_irn_mode(op);
2230 ir_mode *tgt_mode = get_irn_mode(node);
2231 int src_bits = get_mode_size_bits(src_mode);
2232 int tgt_bits = get_mode_size_bits(tgt_mode);
2233 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2234 ir_node *nomem = new_rd_NoMem(irg);
2237 if (src_mode == mode_b) {
2238 assert(mode_is_int(tgt_mode));
2239 /* nothing to do, we already model bools as 0/1 ints */
2243 if (src_mode == tgt_mode) {
2244 if (get_Conv_strict(node)) {
2245 if (USE_SSE2(env_cg)) {
2246 /* when we are in SSE mode, we can kill all strict no-op conversion */
2250 /* this should be optimized already, but who knows... */
2251 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2252 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2257 if (mode_is_float(src_mode)) {
2258 /* we convert from float ... */
2259 if (mode_is_float(tgt_mode)) {
2260 if(src_mode == mode_E && tgt_mode == mode_D
2261 && !get_Conv_strict(node)) {
2262 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2267 if (USE_SSE2(env_cg)) {
2268 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2269 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2270 set_ia32_ls_mode(res, tgt_mode);
2272 if(get_Conv_strict(node)) {
2273 res = create_strict_conv(tgt_mode, new_op);
2274 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2277 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2282 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2283 if (USE_SSE2(env_cg)) {
2284 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2285 set_ia32_ls_mode(res, src_mode);
2287 return gen_x87_fp_to_gp(node);
2291 /* we convert from int ... */
2292 if (mode_is_float(tgt_mode)) {
2294 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2295 if (USE_SSE2(env_cg)) {
2296 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2297 set_ia32_ls_mode(res, tgt_mode);
2298 if(src_bits == 32) {
2299 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2302 res = gen_x87_gp_to_fp(node, src_mode);
2303 if(get_Conv_strict(node)) {
2304 res = create_strict_conv(tgt_mode, res);
2305 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2306 ia32_get_old_node_name(env_cg, node));
2310 } else if(tgt_mode == mode_b) {
2311 /* mode_b lowering already took care that we only have 0/1 values */
2312 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2313 src_mode, tgt_mode));
2317 if (src_bits == tgt_bits) {
2318 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2319 src_mode, tgt_mode));
2323 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, new_op);
2327 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2333 int check_immediate_constraint(long val, char immediate_constraint_type)
2335 switch (immediate_constraint_type) {
2339 return val >= 0 && val <= 32;
2341 return val >= 0 && val <= 63;
2343 return val >= -128 && val <= 127;
2345 return val == 0xff || val == 0xffff;
2347 return val >= 0 && val <= 3;
2349 return val >= 0 && val <= 255;
2351 return val >= 0 && val <= 127;
2355 panic("Invalid immediate constraint found");
2360 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2363 tarval *offset = NULL;
2364 int offset_sign = 0;
2366 ir_entity *symconst_ent = NULL;
2367 int symconst_sign = 0;
2369 ir_node *cnst = NULL;
2370 ir_node *symconst = NULL;
2376 mode = get_irn_mode(node);
2377 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2381 if(is_Minus(node)) {
2383 node = get_Minus_op(node);
2386 if(is_Const(node)) {
2389 offset_sign = minus;
2390 } else if(is_SymConst(node)) {
2393 symconst_sign = minus;
2394 } else if(is_Add(node)) {
2395 ir_node *left = get_Add_left(node);
2396 ir_node *right = get_Add_right(node);
2397 if(is_Const(left) && is_SymConst(right)) {
2400 symconst_sign = minus;
2401 offset_sign = minus;
2402 } else if(is_SymConst(left) && is_Const(right)) {
2405 symconst_sign = minus;
2406 offset_sign = minus;
2408 } else if(is_Sub(node)) {
2409 ir_node *left = get_Sub_left(node);
2410 ir_node *right = get_Sub_right(node);
2411 if(is_Const(left) && is_SymConst(right)) {
2414 symconst_sign = !minus;
2415 offset_sign = minus;
2416 } else if(is_SymConst(left) && is_Const(right)) {
2419 symconst_sign = minus;
2420 offset_sign = !minus;
2427 offset = get_Const_tarval(cnst);
2428 if(tarval_is_long(offset)) {
2429 val = get_tarval_long(offset);
2430 } else if(tarval_is_null(offset)) {
2433 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2438 if(!check_immediate_constraint(val, immediate_constraint_type))
2441 if(symconst != NULL) {
2442 if(immediate_constraint_type != 0) {
2443 /* we need full 32bits for symconsts */
2447 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2449 symconst_ent = get_SymConst_entity(symconst);
2451 if(cnst == NULL && symconst == NULL)
2454 if(offset_sign && offset != NULL) {
2455 offset = tarval_neg(offset);
2458 irg = current_ir_graph;
2459 dbgi = get_irn_dbg_info(node);
2460 block = get_irg_start_block(irg);
2461 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2462 symconst_sign, val);
2463 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2469 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2471 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2472 if (new_node == NULL) {
2473 new_node = be_transform_node(node);
2478 typedef struct constraint_t constraint_t;
2479 struct constraint_t {
2482 const arch_register_req_t **out_reqs;
2484 const arch_register_req_t *req;
2485 unsigned immediate_possible;
2486 char immediate_type;
2489 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2491 int immediate_possible = 0;
2492 char immediate_type = 0;
2493 unsigned limited = 0;
2494 const arch_register_class_t *cls = NULL;
2496 struct obstack *obst;
2497 arch_register_req_t *req;
2498 unsigned *limited_ptr;
2502 /* TODO: replace all the asserts with nice error messages */
2504 printf("Constraint: %s\n", c);
2514 assert(cls == NULL ||
2515 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2516 cls = &ia32_reg_classes[CLASS_ia32_gp];
2517 limited |= 1 << REG_EAX;
2520 assert(cls == NULL ||
2521 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2522 cls = &ia32_reg_classes[CLASS_ia32_gp];
2523 limited |= 1 << REG_EBX;
2526 assert(cls == NULL ||
2527 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2528 cls = &ia32_reg_classes[CLASS_ia32_gp];
2529 limited |= 1 << REG_ECX;
2532 assert(cls == NULL ||
2533 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2534 cls = &ia32_reg_classes[CLASS_ia32_gp];
2535 limited |= 1 << REG_EDX;
2538 assert(cls == NULL ||
2539 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2540 cls = &ia32_reg_classes[CLASS_ia32_gp];
2541 limited |= 1 << REG_EDI;
2544 assert(cls == NULL ||
2545 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2546 cls = &ia32_reg_classes[CLASS_ia32_gp];
2547 limited |= 1 << REG_ESI;
2550 case 'q': /* q means lower part of the regs only, this makes no
2551 * difference to Q for us (we only assigne whole registers) */
2552 assert(cls == NULL ||
2553 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2554 cls = &ia32_reg_classes[CLASS_ia32_gp];
2555 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2559 assert(cls == NULL ||
2560 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2561 cls = &ia32_reg_classes[CLASS_ia32_gp];
2562 limited |= 1 << REG_EAX | 1 << REG_EDX;
2565 assert(cls == NULL ||
2566 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2567 cls = &ia32_reg_classes[CLASS_ia32_gp];
2568 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2569 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2576 assert(cls == NULL);
2577 cls = &ia32_reg_classes[CLASS_ia32_gp];
2583 /* TODO: mark values so the x87 simulator knows about t and u */
2584 assert(cls == NULL);
2585 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2590 assert(cls == NULL);
2591 /* TODO: check that sse2 is supported */
2592 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2602 assert(!immediate_possible);
2603 immediate_possible = 1;
2604 immediate_type = *c;
2608 assert(!immediate_possible);
2609 immediate_possible = 1;
2613 assert(!immediate_possible && cls == NULL);
2614 immediate_possible = 1;
2615 cls = &ia32_reg_classes[CLASS_ia32_gp];
2628 assert(constraint->is_in && "can only specify same constraint "
2631 sscanf(c, "%d%n", &same_as, &p);
2638 case 'E': /* no float consts yet */
2639 case 'F': /* no float consts yet */
2640 case 's': /* makes no sense on x86 */
2641 case 'X': /* we can't support that in firm */
2645 case '<': /* no autodecrement on x86 */
2646 case '>': /* no autoincrement on x86 */
2647 case 'C': /* sse constant not supported yet */
2648 case 'G': /* 80387 constant not supported yet */
2649 case 'y': /* we don't support mmx registers yet */
2650 case 'Z': /* not available in 32 bit mode */
2651 case 'e': /* not available in 32 bit mode */
2652 assert(0 && "asm constraint not supported");
2655 assert(0 && "unknown asm constraint found");
2662 const arch_register_req_t *other_constr;
2664 assert(cls == NULL && "same as and register constraint not supported");
2665 assert(!immediate_possible && "same as and immediate constraint not "
2667 assert(same_as < constraint->n_outs && "wrong constraint number in "
2668 "same_as constraint");
2670 other_constr = constraint->out_reqs[same_as];
2672 req = obstack_alloc(obst, sizeof(req[0]));
2673 req->cls = other_constr->cls;
2674 req->type = arch_register_req_type_should_be_same;
2675 req->limited = NULL;
2676 req->other_same = pos;
2677 req->other_different = -1;
2679 /* switch constraints. This is because in firm we have same_as
2680 * constraints on the output constraints while in the gcc asm syntax
2681 * they are specified on the input constraints */
2682 constraint->req = other_constr;
2683 constraint->out_reqs[same_as] = req;
2684 constraint->immediate_possible = 0;
2688 if(immediate_possible && cls == NULL) {
2689 cls = &ia32_reg_classes[CLASS_ia32_gp];
2691 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2692 assert(cls != NULL);
2694 if(immediate_possible) {
2695 assert(constraint->is_in
2696 && "imeediates make no sense for output constraints");
2698 /* todo: check types (no float input on 'r' constrainted in and such... */
2700 irg = current_ir_graph;
2701 obst = get_irg_obstack(irg);
2704 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2705 limited_ptr = (unsigned*) (req+1);
2707 req = obstack_alloc(obst, sizeof(req[0]));
2709 memset(req, 0, sizeof(req[0]));
2712 req->type = arch_register_req_type_limited;
2713 *limited_ptr = limited;
2714 req->limited = limited_ptr;
2716 req->type = arch_register_req_type_normal;
2720 constraint->req = req;
2721 constraint->immediate_possible = immediate_possible;
2722 constraint->immediate_type = immediate_type;
2726 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2733 panic("Clobbers not supported yet");
2736 ir_node *gen_ASM(ir_node *node)
2739 ir_graph *irg = current_ir_graph;
2740 ir_node *block = be_transform_node(get_nodes_block(node));
2741 dbg_info *dbgi = get_irn_dbg_info(node);
2748 ia32_asm_attr_t *attr;
2749 const arch_register_req_t **out_reqs;
2750 const arch_register_req_t **in_reqs;
2751 struct obstack *obst;
2752 constraint_t parsed_constraint;
2754 /* transform inputs */
2755 arity = get_irn_arity(node);
2756 in = alloca(arity * sizeof(in[0]));
2757 memset(in, 0, arity * sizeof(in[0]));
2759 n_outs = get_ASM_n_output_constraints(node);
2760 n_clobbers = get_ASM_n_clobbers(node);
2761 out_arity = n_outs + n_clobbers;
2763 /* construct register constraints */
2764 obst = get_irg_obstack(irg);
2765 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2766 parsed_constraint.out_reqs = out_reqs;
2767 parsed_constraint.n_outs = n_outs;
2768 parsed_constraint.is_in = 0;
2769 for(i = 0; i < out_arity; ++i) {
2773 const ir_asm_constraint *constraint;
2774 constraint = & get_ASM_output_constraints(node) [i];
2775 c = get_id_str(constraint->constraint);
2776 parse_asm_constraint(i, &parsed_constraint, c);
2778 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2779 c = get_id_str(glob_id);
2780 parse_clobber(node, i, &parsed_constraint, c);
2782 out_reqs[i] = parsed_constraint.req;
2785 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2786 parsed_constraint.is_in = 1;
2787 for(i = 0; i < arity; ++i) {
2788 const ir_asm_constraint *constraint;
2792 constraint = & get_ASM_input_constraints(node) [i];
2793 constr_id = constraint->constraint;
2794 c = get_id_str(constr_id);
2795 parse_asm_constraint(i, &parsed_constraint, c);
2796 in_reqs[i] = parsed_constraint.req;
2798 if(parsed_constraint.immediate_possible) {
2799 ir_node *pred = get_irn_n(node, i);
2800 char imm_type = parsed_constraint.immediate_type;
2801 ir_node *immediate = try_create_Immediate(pred, imm_type);
2803 if(immediate != NULL) {
2809 /* transform inputs */
2810 for(i = 0; i < arity; ++i) {
2812 ir_node *transformed;
2817 pred = get_irn_n(node, i);
2818 transformed = be_transform_node(pred);
2819 in[i] = transformed;
2822 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2824 generic_attr = get_irn_generic_attr(res);
2825 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2826 attr->asm_text = get_ASM_text(node);
2827 set_ia32_out_req_all(res, out_reqs);
2828 set_ia32_in_req_all(res, in_reqs);
2830 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2835 /********************************************
2838 * | |__ ___ _ __ ___ __| | ___ ___
2839 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2840 * | |_) | __/ | | | (_) | (_| | __/\__ \
2841 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2843 ********************************************/
2845 static ir_node *gen_be_StackParam(ir_node *node) {
2846 ir_node *block = be_transform_node(get_nodes_block(node));
2847 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2848 ir_node *new_ptr = be_transform_node(ptr);
2849 ir_node *new_op = NULL;
2850 ir_graph *irg = current_ir_graph;
2851 dbg_info *dbgi = get_irn_dbg_info(node);
2852 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2853 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2854 ir_mode *load_mode = get_irn_mode(node);
2855 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2859 if (mode_is_float(load_mode)) {
2860 if (USE_SSE2(env_cg)) {
2861 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2862 pn_res = pn_ia32_xLoad_res;
2863 proj_mode = mode_xmm;
2865 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2866 pn_res = pn_ia32_vfld_res;
2867 proj_mode = mode_vfp;
2870 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2871 proj_mode = mode_Iu;
2872 pn_res = pn_ia32_Load_res;
2875 set_irn_pinned(new_op, op_pin_state_floats);
2876 set_ia32_frame_ent(new_op, ent);
2877 set_ia32_use_frame(new_op);
2879 set_ia32_op_type(new_op, ia32_AddrModeS);
2880 set_ia32_am_flavour(new_op, ia32_am_B);
2881 set_ia32_ls_mode(new_op, load_mode);
2882 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2884 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2886 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2890 * Transforms a FrameAddr into an ia32 Add.
2892 static ir_node *gen_be_FrameAddr(ir_node *node) {
2893 ir_node *block = be_transform_node(get_nodes_block(node));
2894 ir_node *op = be_get_FrameAddr_frame(node);
2895 ir_node *new_op = be_transform_node(op);
2896 ir_graph *irg = current_ir_graph;
2897 dbg_info *dbgi = get_irn_dbg_info(node);
2898 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2901 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2902 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2903 set_ia32_use_frame(res);
2904 set_ia32_am_flavour(res, ia32_am_OB);
2906 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2912 * Transforms a FrameLoad into an ia32 Load.
2914 static ir_node *gen_be_FrameLoad(ir_node *node) {
2915 ir_node *block = be_transform_node(get_nodes_block(node));
2916 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2917 ir_node *new_mem = be_transform_node(mem);
2918 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2919 ir_node *new_ptr = be_transform_node(ptr);
2920 ir_node *new_op = NULL;
2921 ir_graph *irg = current_ir_graph;
2922 dbg_info *dbgi = get_irn_dbg_info(node);
2923 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2924 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2925 ir_mode *mode = get_type_mode(get_entity_type(ent));
2926 ir_node *projs[pn_Load_max];
2928 ia32_collect_Projs(node, projs, pn_Load_max);
2930 if (mode_is_float(mode)) {
2931 if (USE_SSE2(env_cg)) {
2932 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2935 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2939 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2942 set_irn_pinned(new_op, op_pin_state_floats);
2943 set_ia32_frame_ent(new_op, ent);
2944 set_ia32_use_frame(new_op);
2946 set_ia32_op_type(new_op, ia32_AddrModeS);
2947 set_ia32_am_flavour(new_op, ia32_am_B);
2948 set_ia32_ls_mode(new_op, mode);
2949 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2951 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2958 * Transforms a FrameStore into an ia32 Store.
2960 static ir_node *gen_be_FrameStore(ir_node *node) {
2961 ir_node *block = be_transform_node(get_nodes_block(node));
2962 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2963 ir_node *new_mem = be_transform_node(mem);
2964 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2965 ir_node *new_ptr = be_transform_node(ptr);
2966 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2967 ir_node *new_val = be_transform_node(val);
2968 ir_node *new_op = NULL;
2969 ir_graph *irg = current_ir_graph;
2970 dbg_info *dbgi = get_irn_dbg_info(node);
2971 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2972 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2973 ir_mode *mode = get_irn_mode(val);
2975 if (mode_is_float(mode)) {
2976 if (USE_SSE2(env_cg)) {
2977 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2979 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2981 } else if (get_mode_size_bits(mode) == 8) {
2982 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2984 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2987 set_ia32_frame_ent(new_op, ent);
2988 set_ia32_use_frame(new_op);
2990 set_ia32_op_type(new_op, ia32_AddrModeD);
2991 set_ia32_am_flavour(new_op, ia32_am_B);
2992 set_ia32_ls_mode(new_op, mode);
2994 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3000 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3002 static ir_node *gen_be_Return(ir_node *node) {
3003 ir_graph *irg = current_ir_graph;
3004 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3005 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3006 ir_entity *ent = get_irg_entity(irg);
3007 ir_type *tp = get_entity_type(ent);
3012 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3013 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3016 int pn_ret_val, pn_ret_mem, arity, i;
3018 assert(ret_val != NULL);
3019 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3020 return be_duplicate_node(node);
3023 res_type = get_method_res_type(tp, 0);
3025 if (! is_Primitive_type(res_type)) {
3026 return be_duplicate_node(node);
3029 mode = get_type_mode(res_type);
3030 if (! mode_is_float(mode)) {
3031 return be_duplicate_node(node);
3034 assert(get_method_n_ress(tp) == 1);
3036 pn_ret_val = get_Proj_proj(ret_val);
3037 pn_ret_mem = get_Proj_proj(ret_mem);
3039 /* get the Barrier */
3040 barrier = get_Proj_pred(ret_val);
3042 /* get result input of the Barrier */
3043 ret_val = get_irn_n(barrier, pn_ret_val);
3044 new_ret_val = be_transform_node(ret_val);
3046 /* get memory input of the Barrier */
3047 ret_mem = get_irn_n(barrier, pn_ret_mem);
3048 new_ret_mem = be_transform_node(ret_mem);
3050 frame = get_irg_frame(irg);
3052 dbgi = get_irn_dbg_info(barrier);
3053 block = be_transform_node(get_nodes_block(barrier));
3055 noreg = ia32_new_NoReg_gp(env_cg);
3057 /* store xmm0 onto stack */
3058 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3059 new_ret_val, new_ret_mem);
3060 set_ia32_ls_mode(sse_store, mode);
3061 set_ia32_op_type(sse_store, ia32_AddrModeD);
3062 set_ia32_use_frame(sse_store);
3063 set_ia32_am_flavour(sse_store, ia32_am_B);
3065 /* load into x87 register */
3066 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3067 set_ia32_op_type(fld, ia32_AddrModeS);
3068 set_ia32_use_frame(fld);
3069 set_ia32_am_flavour(fld, ia32_am_B);
3071 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3072 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3074 /* create a new barrier */
3075 arity = get_irn_arity(barrier);
3076 in = alloca(arity * sizeof(in[0]));
3077 for (i = 0; i < arity; ++i) {
3080 if (i == pn_ret_val) {
3082 } else if (i == pn_ret_mem) {
3085 ir_node *in = get_irn_n(barrier, i);
3086 new_in = be_transform_node(in);
3091 new_barrier = new_ir_node(dbgi, irg, block,
3092 get_irn_op(barrier), get_irn_mode(barrier),
3094 copy_node_attr(barrier, new_barrier);
3095 be_duplicate_deps(barrier, new_barrier);
3096 be_set_transformed_node(barrier, new_barrier);
3097 mark_irn_visited(barrier);
3099 /* transform normally */
3100 return be_duplicate_node(node);
3104 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3106 static ir_node *gen_be_AddSP(ir_node *node) {
3107 ir_node *block = be_transform_node(get_nodes_block(node));
3108 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3110 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3111 ir_node *new_sp = be_transform_node(sp);
3112 ir_graph *irg = current_ir_graph;
3113 dbg_info *dbgi = get_irn_dbg_info(node);
3114 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3115 ir_node *nomem = new_NoMem();
3118 new_sz = create_immediate_or_transform(sz, 0);
3120 /* ia32 stack grows in reverse direction, make a SubSP */
3121 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3123 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3124 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3130 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3132 static ir_node *gen_be_SubSP(ir_node *node) {
3133 ir_node *block = be_transform_node(get_nodes_block(node));
3134 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3136 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3137 ir_node *new_sp = be_transform_node(sp);
3138 ir_graph *irg = current_ir_graph;
3139 dbg_info *dbgi = get_irn_dbg_info(node);
3140 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3141 ir_node *nomem = new_NoMem();
3144 new_sz = create_immediate_or_transform(sz, 0);
3146 /* ia32 stack grows in reverse direction, make an AddSP */
3147 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3148 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3149 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3155 * This function just sets the register for the Unknown node
3156 * as this is not done during register allocation because Unknown
3157 * is an "ignore" node.
3159 static ir_node *gen_Unknown(ir_node *node) {
3160 ir_mode *mode = get_irn_mode(node);
3162 if (mode_is_float(mode)) {
3164 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3165 if (USE_SSE2(env_cg))
3166 return ia32_new_Unknown_xmm(env_cg);
3168 return ia32_new_Unknown_vfp(env_cg);
3170 ir_graph *irg = current_ir_graph;
3171 dbg_info *dbgi = get_irn_dbg_info(node);
3172 ir_node *block = get_irg_start_block(irg);
3173 return new_rd_ia32_vfldz(dbgi, irg, block);
3175 } else if (mode_needs_gp_reg(mode)) {
3176 return ia32_new_Unknown_gp(env_cg);
3178 assert(0 && "unsupported Unknown-Mode");
3185 * Change some phi modes
3187 static ir_node *gen_Phi(ir_node *node) {
3188 ir_node *block = be_transform_node(get_nodes_block(node));
3189 ir_graph *irg = current_ir_graph;
3190 dbg_info *dbgi = get_irn_dbg_info(node);
3191 ir_mode *mode = get_irn_mode(node);
3194 if(mode_needs_gp_reg(mode)) {
3195 /* we shouldn't have any 64bit stuff around anymore */
3196 assert(get_mode_size_bits(mode) <= 32);
3197 /* all integer operations are on 32bit registers now */
3199 } else if(mode_is_float(mode)) {
3200 if (USE_SSE2(env_cg)) {
3207 /* phi nodes allow loops, so we use the old arguments for now
3208 * and fix this later */
3209 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3210 copy_node_attr(node, phi);
3211 be_duplicate_deps(node, phi);
3213 be_set_transformed_node(node, phi);
3214 be_enqueue_preds(node);
3219 /**********************************************************************
3222 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3223 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3224 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3225 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3227 **********************************************************************/
3229 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3231 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3234 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3235 ir_node *val, ir_node *mem);
3238 * Transforms a lowered Load into a "real" one.
3240 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3242 ir_node *block = be_transform_node(get_nodes_block(node));
3243 ir_node *ptr = get_irn_n(node, 0);
3244 ir_node *new_ptr = be_transform_node(ptr);
3245 ir_node *mem = get_irn_n(node, 1);
3246 ir_node *new_mem = be_transform_node(mem);
3247 ir_graph *irg = current_ir_graph;
3248 dbg_info *dbgi = get_irn_dbg_info(node);
3249 ir_mode *mode = get_ia32_ls_mode(node);
3250 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3253 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3255 set_ia32_op_type(new_op, ia32_AddrModeS);
3256 set_ia32_am_flavour(new_op, ia32_am_OB);
3257 set_ia32_am_offs_int(new_op, 0);
3258 set_ia32_am_scale(new_op, 1);
3259 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3260 if (is_ia32_am_sc_sign(node))
3261 set_ia32_am_sc_sign(new_op);
3262 set_ia32_ls_mode(new_op, mode);
3263 if (is_ia32_use_frame(node)) {
3264 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3265 set_ia32_use_frame(new_op);
3268 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3274 * Transforms a lowered Store into a "real" one.
3276 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3278 ir_node *block = be_transform_node(get_nodes_block(node));
3279 ir_node *ptr = get_irn_n(node, 0);
3280 ir_node *new_ptr = be_transform_node(ptr);
3281 ir_node *val = get_irn_n(node, 1);
3282 ir_node *new_val = be_transform_node(val);
3283 ir_node *mem = get_irn_n(node, 2);
3284 ir_node *new_mem = be_transform_node(mem);
3285 ir_graph *irg = current_ir_graph;
3286 dbg_info *dbgi = get_irn_dbg_info(node);
3287 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3288 ir_mode *mode = get_ia32_ls_mode(node);
3291 ia32_am_flavour_t am_flav = ia32_B;
3293 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3295 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3297 add_ia32_am_offs_int(new_op, am_offs);
3300 set_ia32_op_type(new_op, ia32_AddrModeD);
3301 set_ia32_am_flavour(new_op, am_flav);
3302 set_ia32_ls_mode(new_op, mode);
3303 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3304 set_ia32_use_frame(new_op);
3306 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3313 * Transforms an ia32_l_XXX into a "real" XXX node
3315 * @param env The transformation environment
3316 * @return the created ia32 XXX node
3318 #define GEN_LOWERED_OP(op) \
3319 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3320 return gen_binop(node, get_binop_left(node), \
3321 get_binop_right(node), new_rd_ia32_##op,0); \
3324 #define GEN_LOWERED_x87_OP(op) \
3325 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3327 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3328 get_binop_right(node), new_rd_ia32_##op); \
3332 #define GEN_LOWERED_UNOP(op) \
3333 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3334 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3337 #define GEN_LOWERED_SHIFT_OP(op) \
3338 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3339 return gen_shift_binop(node, get_binop_left(node), \
3340 get_binop_right(node), new_rd_ia32_##op); \
3343 #define GEN_LOWERED_LOAD(op) \
3344 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3345 return gen_lowered_Load(node, new_rd_ia32_##op); \
3348 #define GEN_LOWERED_STORE(op) \
3349 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3350 return gen_lowered_Store(node, new_rd_ia32_##op); \
3357 GEN_LOWERED_OP(IMul)
3359 GEN_LOWERED_x87_OP(vfprem)
3360 GEN_LOWERED_x87_OP(vfmul)
3361 GEN_LOWERED_x87_OP(vfsub)
3363 GEN_LOWERED_UNOP(Neg)
3365 GEN_LOWERED_LOAD(vfild)
3366 GEN_LOWERED_LOAD(Load)
3367 // GEN_LOWERED_STORE(vfist) TODO
3368 GEN_LOWERED_STORE(Store)
3370 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3371 ir_node *block = be_transform_node(get_nodes_block(node));
3372 ir_node *left = get_binop_left(node);
3373 ir_node *new_left = be_transform_node(left);
3374 ir_node *right = get_binop_right(node);
3375 ir_node *new_right = be_transform_node(right);
3376 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3377 ir_graph *irg = current_ir_graph;
3378 dbg_info *dbgi = get_irn_dbg_info(node);
3379 ir_node *fpcw = get_fpcw();
3382 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3383 new_right, new_NoMem(), fpcw);
3384 clear_ia32_commutative(vfdiv);
3385 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3387 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3393 * Transforms a l_MulS into a "real" MulS node.
3395 * @param env The transformation environment
3396 * @return the created ia32 Mul node
3398 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3399 ir_node *block = be_transform_node(get_nodes_block(node));
3400 ir_node *left = get_binop_left(node);
3401 ir_node *new_left = be_transform_node(left);
3402 ir_node *right = get_binop_right(node);
3403 ir_node *new_right = be_transform_node(right);
3404 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3405 ir_graph *irg = current_ir_graph;
3406 dbg_info *dbgi = get_irn_dbg_info(node);
3408 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3409 /* and then skip the result Proj, because all needed Projs are already there. */
3410 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3411 new_right, new_NoMem());
3412 clear_ia32_commutative(muls);
3413 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3415 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3420 GEN_LOWERED_SHIFT_OP(Shl)
3421 GEN_LOWERED_SHIFT_OP(Shr)
3422 GEN_LOWERED_SHIFT_OP(Sar)
3425 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3426 * op1 - target to be shifted
3427 * op2 - contains bits to be shifted into target
3429 * Only op3 can be an immediate.
3431 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3432 ir_node *op2, ir_node *count)
3434 ir_node *block = be_transform_node(get_nodes_block(node));
3435 ir_node *new_op1 = be_transform_node(op1);
3436 ir_node *new_op2 = be_transform_node(op2);
3437 ir_node *new_count = be_transform_node(count);
3438 ir_node *new_op = NULL;
3439 ir_graph *irg = current_ir_graph;
3440 dbg_info *dbgi = get_irn_dbg_info(node);
3441 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3442 ir_node *nomem = new_NoMem();
3446 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3448 /* Check if immediate optimization is on and */
3449 /* if it's an operation with immediate. */
3450 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3452 /* Limit imm_op within range imm8 */
3454 tv = get_ia32_Immop_tarval(imm_op);
3457 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3458 set_ia32_Immop_tarval(imm_op, tv);
3465 /* integer operations */
3467 /* This is ShiftD with const */
3468 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3470 if (is_ia32_l_ShlD(node))
3471 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3472 new_op1, new_op2, noreg, nomem);
3474 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3475 new_op1, new_op2, noreg, nomem);
3476 copy_ia32_Immop_attr(new_op, imm_op);
3479 /* This is a normal ShiftD */
3480 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3481 if (is_ia32_l_ShlD(node))
3482 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3483 new_op1, new_op2, new_count, nomem);
3485 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3486 new_op1, new_op2, new_count, nomem);
3489 /* set AM support */
3490 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3492 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3494 set_ia32_emit_cl(new_op);
3499 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3500 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3501 get_irn_n(node, 1), get_irn_n(node, 2));
3504 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3505 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3506 get_irn_n(node, 1), get_irn_n(node, 2));
3510 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3512 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3513 ir_node *block = be_transform_node(get_nodes_block(node));
3514 ir_node *val = get_irn_n(node, 1);
3515 ir_node *new_val = be_transform_node(val);
3516 ia32_code_gen_t *cg = env_cg;
3517 ir_node *res = NULL;
3518 ir_graph *irg = current_ir_graph;
3520 ir_node *noreg, *new_ptr, *new_mem;
3527 mem = get_irn_n(node, 2);
3528 new_mem = be_transform_node(mem);
3529 ptr = get_irn_n(node, 0);
3530 new_ptr = be_transform_node(ptr);
3531 noreg = ia32_new_NoReg_gp(cg);
3532 dbgi = get_irn_dbg_info(node);
3534 /* Store x87 -> MEM */
3535 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3536 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3537 set_ia32_use_frame(res);
3538 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3539 set_ia32_am_flavour(res, ia32_B);
3540 set_ia32_op_type(res, ia32_AddrModeD);
3542 /* Load MEM -> SSE */
3543 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3544 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3545 set_ia32_use_frame(res);
3546 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3547 set_ia32_am_flavour(res, ia32_B);
3548 set_ia32_op_type(res, ia32_AddrModeS);
3549 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3555 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3557 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3558 ir_node *block = be_transform_node(get_nodes_block(node));
3559 ir_node *val = get_irn_n(node, 1);
3560 ir_node *new_val = be_transform_node(val);
3561 ia32_code_gen_t *cg = env_cg;
3562 ir_graph *irg = current_ir_graph;
3563 ir_node *res = NULL;
3564 ir_entity *fent = get_ia32_frame_ent(node);
3565 ir_mode *lsmode = get_ia32_ls_mode(node);
3567 ir_node *noreg, *new_ptr, *new_mem;
3571 if (! USE_SSE2(cg)) {
3572 /* SSE unit is not used -> skip this node. */
3576 ptr = get_irn_n(node, 0);
3577 new_ptr = be_transform_node(ptr);
3578 mem = get_irn_n(node, 2);
3579 new_mem = be_transform_node(mem);
3580 noreg = ia32_new_NoReg_gp(cg);
3581 dbgi = get_irn_dbg_info(node);
3583 /* Store SSE -> MEM */
3584 if (is_ia32_xLoad(skip_Proj(new_val))) {
3585 ir_node *ld = skip_Proj(new_val);
3587 /* we can vfld the value directly into the fpu */
3588 fent = get_ia32_frame_ent(ld);
3589 ptr = get_irn_n(ld, 0);
3590 offs = get_ia32_am_offs_int(ld);
3592 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3593 set_ia32_frame_ent(res, fent);
3594 set_ia32_use_frame(res);
3595 set_ia32_ls_mode(res, lsmode);
3596 set_ia32_am_flavour(res, ia32_B);
3597 set_ia32_op_type(res, ia32_AddrModeD);
3601 /* Load MEM -> x87 */
3602 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3603 set_ia32_frame_ent(res, fent);
3604 set_ia32_use_frame(res);
3605 add_ia32_am_offs_int(res, offs);
3606 set_ia32_am_flavour(res, ia32_B);
3607 set_ia32_op_type(res, ia32_AddrModeS);
3608 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3613 /*********************************************************
3616 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3617 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3618 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3619 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3621 *********************************************************/
3624 * the BAD transformer.
3626 static ir_node *bad_transform(ir_node *node) {
3627 panic("No transform function for %+F available.\n", node);
3632 * Transform the Projs of an AddSP.
3634 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3635 ir_node *block = be_transform_node(get_nodes_block(node));
3636 ir_node *pred = get_Proj_pred(node);
3637 ir_node *new_pred = be_transform_node(pred);
3638 ir_graph *irg = current_ir_graph;
3639 dbg_info *dbgi = get_irn_dbg_info(node);
3640 long proj = get_Proj_proj(node);
3642 if (proj == pn_be_AddSP_sp) {
3643 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3644 pn_ia32_SubSP_stack);
3645 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3647 } else if(proj == pn_be_AddSP_res) {
3648 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3649 pn_ia32_SubSP_addr);
3650 } else if (proj == pn_be_AddSP_M) {
3651 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3655 return new_rd_Unknown(irg, get_irn_mode(node));
3659 * Transform the Projs of a SubSP.
3661 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3662 ir_node *block = be_transform_node(get_nodes_block(node));
3663 ir_node *pred = get_Proj_pred(node);
3664 ir_node *new_pred = be_transform_node(pred);
3665 ir_graph *irg = current_ir_graph;
3666 dbg_info *dbgi = get_irn_dbg_info(node);
3667 long proj = get_Proj_proj(node);
3669 if (proj == pn_be_SubSP_sp) {
3670 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3671 pn_ia32_AddSP_stack);
3672 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3674 } else if (proj == pn_be_SubSP_M) {
3675 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3679 return new_rd_Unknown(irg, get_irn_mode(node));
3683 * Transform and renumber the Projs from a Load.
3685 static ir_node *gen_Proj_Load(ir_node *node) {
3686 ir_node *block = be_transform_node(get_nodes_block(node));
3687 ir_node *pred = get_Proj_pred(node);
3688 ir_node *new_pred = be_transform_node(pred);
3689 ir_graph *irg = current_ir_graph;
3690 dbg_info *dbgi = get_irn_dbg_info(node);
3691 long proj = get_Proj_proj(node);
3693 /* renumber the proj */
3694 if (is_ia32_Load(new_pred)) {
3695 if (proj == pn_Load_res) {
3696 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3697 } else if (proj == pn_Load_M) {
3698 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3700 } else if (is_ia32_xLoad(new_pred)) {
3701 if (proj == pn_Load_res) {
3702 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3703 } else if (proj == pn_Load_M) {
3704 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3706 } else if (is_ia32_vfld(new_pred)) {
3707 if (proj == pn_Load_res) {
3708 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3709 } else if (proj == pn_Load_M) {
3710 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3715 return new_rd_Unknown(irg, get_irn_mode(node));
3719 * Transform and renumber the Projs from a DivMod like instruction.
3721 static ir_node *gen_Proj_DivMod(ir_node *node) {
3722 ir_node *block = be_transform_node(get_nodes_block(node));
3723 ir_node *pred = get_Proj_pred(node);
3724 ir_node *new_pred = be_transform_node(pred);
3725 ir_graph *irg = current_ir_graph;
3726 dbg_info *dbgi = get_irn_dbg_info(node);
3727 ir_mode *mode = get_irn_mode(node);
3728 long proj = get_Proj_proj(node);
3730 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3732 switch (get_irn_opcode(pred)) {
3736 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3738 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3746 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3748 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3756 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3757 case pn_DivMod_res_div:
3758 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3759 case pn_DivMod_res_mod:
3760 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3770 return new_rd_Unknown(irg, mode);
3774 * Transform and renumber the Projs from a CopyB.
3776 static ir_node *gen_Proj_CopyB(ir_node *node) {
3777 ir_node *block = be_transform_node(get_nodes_block(node));
3778 ir_node *pred = get_Proj_pred(node);
3779 ir_node *new_pred = be_transform_node(pred);
3780 ir_graph *irg = current_ir_graph;
3781 dbg_info *dbgi = get_irn_dbg_info(node);
3782 ir_mode *mode = get_irn_mode(node);
3783 long proj = get_Proj_proj(node);
3786 case pn_CopyB_M_regular:
3787 if (is_ia32_CopyB_i(new_pred)) {
3788 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3789 } else if (is_ia32_CopyB(new_pred)) {
3790 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3798 return new_rd_Unknown(irg, mode);
3802 * Transform and renumber the Projs from a vfdiv.
3804 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3805 ir_node *block = be_transform_node(get_nodes_block(node));
3806 ir_node *pred = get_Proj_pred(node);
3807 ir_node *new_pred = be_transform_node(pred);
3808 ir_graph *irg = current_ir_graph;
3809 dbg_info *dbgi = get_irn_dbg_info(node);
3810 ir_mode *mode = get_irn_mode(node);
3811 long proj = get_Proj_proj(node);
3814 case pn_ia32_l_vfdiv_M:
3815 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3816 case pn_ia32_l_vfdiv_res:
3817 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3822 return new_rd_Unknown(irg, mode);
3826 * Transform and renumber the Projs from a Quot.
3828 static ir_node *gen_Proj_Quot(ir_node *node) {
3829 ir_node *block = be_transform_node(get_nodes_block(node));
3830 ir_node *pred = get_Proj_pred(node);
3831 ir_node *new_pred = be_transform_node(pred);
3832 ir_graph *irg = current_ir_graph;
3833 dbg_info *dbgi = get_irn_dbg_info(node);
3834 ir_mode *mode = get_irn_mode(node);
3835 long proj = get_Proj_proj(node);
3839 if (is_ia32_xDiv(new_pred)) {
3840 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3841 } else if (is_ia32_vfdiv(new_pred)) {
3842 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3846 if (is_ia32_xDiv(new_pred)) {
3847 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3848 } else if (is_ia32_vfdiv(new_pred)) {
3849 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3857 return new_rd_Unknown(irg, mode);
3861 * Transform the Thread Local Storage Proj.
3863 static ir_node *gen_Proj_tls(ir_node *node) {
3864 ir_node *block = be_transform_node(get_nodes_block(node));
3865 ir_graph *irg = current_ir_graph;
3866 dbg_info *dbgi = NULL;
3867 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3873 * Transform the Projs from a be_Call.
3875 static ir_node *gen_Proj_be_Call(ir_node *node) {
3876 ir_node *block = be_transform_node(get_nodes_block(node));
3877 ir_node *call = get_Proj_pred(node);
3878 ir_node *new_call = be_transform_node(call);
3879 ir_graph *irg = current_ir_graph;
3880 dbg_info *dbgi = get_irn_dbg_info(node);
3881 long proj = get_Proj_proj(node);
3882 ir_mode *mode = get_irn_mode(node);
3884 const arch_register_class_t *cls;
3886 /* The following is kinda tricky: If we're using SSE, then we have to
3887 * move the result value of the call in floating point registers to an
3888 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3889 * after the call, we have to make sure to correctly make the
3890 * MemProj and the result Proj use these 2 nodes
3892 if (proj == pn_be_Call_M_regular) {
3893 // get new node for result, are we doing the sse load/store hack?
3894 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3895 ir_node *call_res_new;
3896 ir_node *call_res_pred = NULL;
3898 if (call_res != NULL) {
3899 call_res_new = be_transform_node(call_res);
3900 call_res_pred = get_Proj_pred(call_res_new);
3903 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3904 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
3905 pn_be_Call_M_regular);
3907 assert(is_ia32_xLoad(call_res_pred));
3908 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
3912 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3914 ir_node *frame = get_irg_frame(irg);
3915 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3917 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3920 /* in case there is no memory output: create one to serialize the copy
3922 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
3923 pn_be_Call_M_regular);
3924 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
3925 pn_be_Call_first_res);
3927 /* store st(0) onto stack */
3928 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
3930 set_ia32_op_type(fstp, ia32_AddrModeD);
3931 set_ia32_use_frame(fstp);
3932 set_ia32_am_flavour(fstp, ia32_am_B);
3934 /* load into SSE register */
3935 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3936 set_ia32_ls_mode(sse_load, mode);
3937 set_ia32_op_type(sse_load, ia32_AddrModeS);
3938 set_ia32_use_frame(sse_load);
3939 set_ia32_am_flavour(sse_load, ia32_am_B);
3941 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
3945 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3947 /* get a Proj representing a caller save register */
3948 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3949 assert(is_Proj(p) && "Proj expected.");
3951 /* user of the the proj is the Keep */
3952 p = get_edge_src_irn(get_irn_out_edge_first(p));
3953 assert(be_is_Keep(p) && "Keep expected.");
3959 /* transform call modes */
3960 if (mode_is_data(mode)) {
3961 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
3965 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3969 * Transform the Projs from a Cmp.
3971 static ir_node *gen_Proj_Cmp(ir_node *node)
3973 /* normally Cmps are processed when looking at Cond nodes, but this case
3974 * can happen in complicated Psi conditions */
3976 ir_node *cmp = get_Proj_pred(node);
3977 long pnc = get_Proj_proj(node);
3978 ir_node *cmp_left = get_Cmp_left(cmp);
3979 ir_node *cmp_right = get_Cmp_right(cmp);
3980 ir_mode *cmp_mode = get_irn_mode(cmp_left);
3981 dbg_info *dbgi = get_irn_dbg_info(cmp);
3982 ir_node *block = be_transform_node(get_nodes_block(node));
3985 assert(!mode_is_float(cmp_mode));
3987 if(!mode_is_signed(cmp_mode)) {
3988 pnc |= ia32_pn_Cmp_Unsigned;
3991 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
3992 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
3998 * Transform and potentially renumber Proj nodes.
4000 static ir_node *gen_Proj(ir_node *node) {
4001 ir_graph *irg = current_ir_graph;
4002 dbg_info *dbgi = get_irn_dbg_info(node);
4003 ir_node *pred = get_Proj_pred(node);
4004 long proj = get_Proj_proj(node);
4006 if (is_Store(pred) || be_is_FrameStore(pred)) {
4007 if (proj == pn_Store_M) {
4008 return be_transform_node(pred);
4011 return new_r_Bad(irg);
4013 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4014 return gen_Proj_Load(node);
4015 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4016 return gen_Proj_DivMod(node);
4017 } else if (is_CopyB(pred)) {
4018 return gen_Proj_CopyB(node);
4019 } else if (is_Quot(pred)) {
4020 return gen_Proj_Quot(node);
4021 } else if (is_ia32_l_vfdiv(pred)) {
4022 return gen_Proj_l_vfdiv(node);
4023 } else if (be_is_SubSP(pred)) {
4024 return gen_Proj_be_SubSP(node);
4025 } else if (be_is_AddSP(pred)) {
4026 return gen_Proj_be_AddSP(node);
4027 } else if (be_is_Call(pred)) {
4028 return gen_Proj_be_Call(node);
4029 } else if (is_Cmp(pred)) {
4030 return gen_Proj_Cmp(node);
4031 } else if (get_irn_op(pred) == op_Start) {
4032 if (proj == pn_Start_X_initial_exec) {
4033 ir_node *block = get_nodes_block(pred);
4036 /* we exchange the ProjX with a jump */
4037 block = be_transform_node(block);
4038 jump = new_rd_Jmp(dbgi, irg, block);
4041 if (node == be_get_old_anchor(anchor_tls)) {
4042 return gen_Proj_tls(node);
4045 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4049 ir_node *new_pred = be_transform_node(pred);
4050 ir_node *block = be_transform_node(get_nodes_block(node));
4051 ir_mode *mode = get_irn_mode(node);
4052 if (mode_needs_gp_reg(mode)) {
4053 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4054 get_Proj_proj(node));
4055 #ifdef DEBUG_libfirm
4056 new_proj->node_nr = node->node_nr;
4062 return be_duplicate_node(node);
4066 * Enters all transform functions into the generic pointer
4068 static void register_transformers(void)
4072 /* first clear the generic function pointer for all ops */
4073 clear_irp_opcodes_generic_func();
4075 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4076 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4112 /* transform ops from intrinsic lowering */
4132 /* GEN(ia32_l_vfist); TODO */
4134 GEN(ia32_l_X87toSSE);
4135 GEN(ia32_l_SSEtoX87);
4140 /* we should never see these nodes */
4155 /* handle generic backend nodes */
4166 /* set the register for all Unknown nodes */
4169 op_Mulh = get_op_Mulh();
4178 * Pre-transform all unknown and noreg nodes.
4180 static void ia32_pretransform_node(void *arch_cg) {
4181 ia32_code_gen_t *cg = arch_cg;
4183 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4184 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4185 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4186 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4187 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4188 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4193 void add_missing_keep_walker(ir_node *node, void *data)
4196 unsigned found_projs = 0;
4197 const ir_edge_t *edge;
4198 ir_mode *mode = get_irn_mode(node);
4203 if(!is_ia32_irn(node))
4206 n_outs = get_ia32_n_res(node);
4209 if(is_ia32_SwitchJmp(node))
4212 assert(n_outs < (int) sizeof(unsigned) * 8);
4213 foreach_out_edge(node, edge) {
4214 ir_node *proj = get_edge_src_irn(edge);
4215 int pn = get_Proj_proj(proj);
4217 assert(pn < n_outs);
4218 found_projs |= 1 << pn;
4222 /* are keeps missing? */
4224 for(i = 0; i < n_outs; ++i) {
4227 const arch_register_req_t *req;
4228 const arch_register_class_t *class;
4230 if(found_projs & (1 << i)) {
4234 req = get_ia32_out_req(node, i);
4240 block = get_nodes_block(node);
4241 in[0] = new_r_Proj(current_ir_graph, block, node,
4242 arch_register_class_mode(class), i);
4243 if(last_keep != NULL) {
4244 be_Keep_add_node(last_keep, class, in[0]);
4246 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4252 * Adds missing keeps to nodes
4255 void add_missing_keeps(ia32_code_gen_t *cg)
4257 ir_graph *irg = be_get_birg_irg(cg->birg);
4258 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4261 /* do the transformation */
4262 void ia32_transform_graph(ia32_code_gen_t *cg) {
4263 register_transformers();
4265 initial_fpcw = NULL;
4266 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4267 edges_verify(cg->irg);
4268 add_missing_keeps(cg);
4269 edges_verify(cg->irg);
4272 void ia32_init_transform(void)
4274 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");