2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_map_regs.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
67 #include "gen_ia32_regalloc_if.h"
69 #define SFP_SIGN "0x80000000"
70 #define DFP_SIGN "0x8000000000000000"
71 #define SFP_ABS "0x7FFFFFFF"
72 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
74 #define TP_SFP_SIGN "ia32_sfp_sign"
75 #define TP_DFP_SIGN "ia32_dfp_sign"
76 #define TP_SFP_ABS "ia32_sfp_abs"
77 #define TP_DFP_ABS "ia32_dfp_abs"
79 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
80 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
81 #define ENT_SFP_ABS "IA32_SFP_ABS"
82 #define ENT_DFP_ABS "IA32_DFP_ABS"
84 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
85 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
87 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 /** hold the current code generator during transformation */
90 static ia32_code_gen_t *env_cg = NULL;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
119 static ir_node *create_immediate_or_transform(ir_node *node,
120 char immediate_constraint_type);
123 * Return true if a mode can be stored in the GP register set
125 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
126 if(mode == mode_fpcw)
128 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
132 * Returns 1 if irn is a Const representing 0, 0 otherwise
134 static INLINE int is_ia32_Const_0(ir_node *irn) {
135 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
136 && tarval_is_null(get_ia32_Immop_tarval(irn));
140 * Returns 1 if irn is a Const representing 1, 0 otherwise
142 static INLINE int is_ia32_Const_1(ir_node *irn) {
143 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
144 && tarval_is_one(get_ia32_Immop_tarval(irn));
148 * Collects all Projs of a node into the node array. Index is the projnum.
149 * BEWARE: The caller has to assure the appropriate array size!
151 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
152 const ir_edge_t *edge;
153 assert(get_irn_mode(irn) == mode_T && "need mode_T");
155 memset(projs, 0, size * sizeof(projs[0]));
157 foreach_out_edge(irn, edge) {
158 ir_node *proj = get_edge_src_irn(edge);
159 int proj_proj = get_Proj_proj(proj);
160 assert(proj_proj < size);
161 projs[proj_proj] = proj;
166 * Renumbers the proj having pn_old in the array tp pn_new
167 * and removes the proj from the array.
169 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
170 fprintf(stderr, "Warning: renumber_Proj used!\n");
172 set_Proj_proj(projs[pn_old], pn_new);
173 projs[pn_old] = NULL;
178 * creates a unique ident by adding a number to a tag
180 * @param tag the tag string, must contain a %d if a number
183 static ident *unique_id(const char *tag)
185 static unsigned id = 0;
188 snprintf(str, sizeof(str), tag, ++id);
189 return new_id_from_str(str);
193 * Get a primitive type for a mode.
195 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
197 pmap_entry *e = pmap_find(types, mode);
202 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
203 res = new_type_primitive(new_id_from_str(buf), mode);
204 set_type_alignment_bytes(res, 16);
205 pmap_insert(types, mode, res);
213 * Get an entity that is initialized with a tarval
215 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
217 tarval *tv = get_Const_tarval(cnst);
218 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
223 ir_mode *mode = get_irn_mode(cnst);
224 ir_type *tp = get_Const_type(cnst);
225 if (tp == firm_unknown_type)
226 tp = get_prim_type(cg->isa->types, mode);
228 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
230 set_entity_ld_ident(res, get_entity_ident(res));
231 set_entity_visibility(res, visibility_local);
232 set_entity_variability(res, variability_constant);
233 set_entity_allocation(res, allocation_static);
235 /* we create a new entity here: It's initialization must resist on the
237 rem = current_ir_graph;
238 current_ir_graph = get_const_code_irg();
239 set_atomic_ent_value(res, new_Const_type(tv, tp));
240 current_ir_graph = rem;
242 pmap_insert(cg->isa->tv_ent, tv, res);
250 static int is_Const_0(ir_node *node) {
254 return classify_Const(node) == CNST_NULL;
257 static int is_Const_1(ir_node *node) {
261 return classify_Const(node) == CNST_ONE;
265 * Transforms a Const.
267 static ir_node *gen_Const(ir_node *node) {
268 ir_graph *irg = current_ir_graph;
269 ir_node *block = be_transform_node(get_nodes_block(node));
270 dbg_info *dbgi = get_irn_dbg_info(node);
271 ir_mode *mode = get_irn_mode(node);
273 if (mode_is_float(mode)) {
275 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
276 ir_node *nomem = new_NoMem();
281 if (! USE_SSE2(env_cg)) {
282 cnst_classify_t clss = classify_Const(node);
284 if (clss == CNST_NULL) {
285 load = new_rd_ia32_vfldz(dbgi, irg, block);
287 } else if (clss == CNST_ONE) {
288 load = new_rd_ia32_vfld1(dbgi, irg, block);
291 floatent = get_entity_for_tv(env_cg, node);
293 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
294 set_ia32_op_type(load, ia32_AddrModeS);
295 set_ia32_am_flavour(load, ia32_am_N);
296 set_ia32_am_sc(load, floatent);
297 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
298 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
300 set_ia32_ls_mode(load, mode);
302 floatent = get_entity_for_tv(env_cg, node);
304 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
305 set_ia32_op_type(load, ia32_AddrModeS);
306 set_ia32_am_flavour(load, ia32_am_N);
307 set_ia32_am_sc(load, floatent);
308 set_ia32_ls_mode(load, mode);
309 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
311 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
314 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
316 /* Const Nodes before the initial IncSP are a bad idea, because
317 * they could be spilled and we have no SP ready at that point yet.
318 * So add a dependency to the initial frame pointer calculation to
319 * avoid that situation.
321 if (get_irg_start_block(irg) == block) {
322 add_irn_dep(load, get_irg_frame(irg));
325 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
328 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
331 if (get_irg_start_block(irg) == block) {
332 add_irn_dep(cnst, get_irg_frame(irg));
335 set_ia32_Const_attr(cnst, node);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
341 return new_r_Bad(irg);
345 * Transforms a SymConst.
347 static ir_node *gen_SymConst(ir_node *node) {
348 ir_graph *irg = current_ir_graph;
349 ir_node *block = be_transform_node(get_nodes_block(node));
350 dbg_info *dbgi = get_irn_dbg_info(node);
351 ir_mode *mode = get_irn_mode(node);
354 if (mode_is_float(mode)) {
356 if (USE_SSE2(env_cg))
357 cnst = new_rd_ia32_xConst(dbgi, irg, block);
359 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
360 //set_ia32_ls_mode(cnst, mode);
361 set_ia32_ls_mode(cnst, mode_E);
363 cnst = new_rd_ia32_Const(dbgi, irg, block);
366 /* Const Nodes before the initial IncSP are a bad idea, because
367 * they could be spilled and we have no SP ready at that point yet
369 if (get_irg_start_block(irg) == block) {
370 add_irn_dep(cnst, get_irg_frame(irg));
373 set_ia32_Const_attr(cnst, node);
374 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
379 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
380 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
381 static const struct {
383 const char *ent_name;
384 const char *cnst_str;
385 } names [ia32_known_const_max] = {
386 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
387 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
388 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
389 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
391 static ir_entity *ent_cache[ia32_known_const_max];
393 const char *tp_name, *ent_name, *cnst_str;
401 ent_name = names[kct].ent_name;
402 if (! ent_cache[kct]) {
403 tp_name = names[kct].tp_name;
404 cnst_str = names[kct].cnst_str;
406 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
408 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
409 tp = new_type_primitive(new_id_from_str(tp_name), mode);
410 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
412 set_entity_ld_ident(ent, get_entity_ident(ent));
413 set_entity_visibility(ent, visibility_local);
414 set_entity_variability(ent, variability_constant);
415 set_entity_allocation(ent, allocation_static);
417 /* we create a new entity here: It's initialization must resist on the
419 rem = current_ir_graph;
420 current_ir_graph = get_const_code_irg();
421 cnst = new_Const(mode, tv);
422 current_ir_graph = rem;
424 set_atomic_ent_value(ent, cnst);
426 /* cache the entry */
427 ent_cache[kct] = ent;
430 return ent_cache[kct];
435 * Prints the old node name on cg obst and returns a pointer to it.
437 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
438 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
440 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
441 obstack_1grow(isa->name_obst, 0);
442 return obstack_finish(isa->name_obst);
446 /* determine if one operator is an Imm */
447 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
449 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
451 return is_ia32_Cnst(op2) ? op2 : NULL;
455 /* determine if one operator is not an Imm */
456 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
457 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
460 static void fold_immediate(ir_node *node, int in1, int in2) {
464 if (!(env_cg->opt & IA32_OPT_IMMOPS))
467 left = get_irn_n(node, in1);
468 right = get_irn_n(node, in2);
469 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
470 /* we can only set right operand to immediate */
471 if(!is_ia32_commutative(node))
473 /* exchange left/right */
474 set_irn_n(node, in1, right);
475 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
476 copy_ia32_Immop_attr(node, left);
477 } else if(is_ia32_Cnst(right)) {
478 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
479 copy_ia32_Immop_attr(node, right);
484 clear_ia32_commutative(node);
485 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
486 get_ia32_am_arity(node));
490 * Construct a standard binary operation, set AM and immediate if required.
492 * @param op1 The first operand
493 * @param op2 The second operand
494 * @param func The node constructor function
495 * @return The constructed ia32 node.
497 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
498 construct_binop_func *func, int commutative)
500 ir_node *block = be_transform_node(get_nodes_block(node));
501 ir_graph *irg = current_ir_graph;
502 dbg_info *dbgi = get_irn_dbg_info(node);
503 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
504 ir_node *nomem = new_NoMem();
507 ir_node *new_op1 = be_transform_node(op1);
508 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
509 if (is_ia32_Immediate(new_op2)) {
513 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
514 if (func == new_rd_ia32_IMul) {
515 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
517 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
520 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
522 set_ia32_commutative(new_node);
529 * Construct a standard binary operation, set AM and immediate if required.
531 * @param op1 The first operand
532 * @param op2 The second operand
533 * @param func The node constructor function
534 * @return The constructed ia32 node.
536 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
537 construct_binop_func *func)
539 ir_node *block = be_transform_node(get_nodes_block(node));
540 ir_node *new_op1 = be_transform_node(op1);
541 ir_node *new_op2 = be_transform_node(op2);
542 ir_node *new_node = NULL;
543 dbg_info *dbgi = get_irn_dbg_info(node);
544 ir_graph *irg = current_ir_graph;
545 ir_mode *mode = get_irn_mode(node);
546 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
547 ir_node *nomem = new_NoMem();
549 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
551 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
552 if (is_op_commutative(get_irn_op(node))) {
553 set_ia32_commutative(new_node);
555 set_ia32_ls_mode(new_node, mode);
557 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
563 * Construct a standard binary operation, set AM and immediate if required.
565 * @param op1 The first operand
566 * @param op2 The second operand
567 * @param func The node constructor function
568 * @return The constructed ia32 node.
570 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
571 construct_binop_float_func *func)
573 ir_node *block = be_transform_node(get_nodes_block(node));
574 ir_node *new_op1 = be_transform_node(op1);
575 ir_node *new_op2 = be_transform_node(op2);
576 ir_node *new_node = NULL;
577 dbg_info *dbgi = get_irn_dbg_info(node);
578 ir_graph *irg = current_ir_graph;
579 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
580 ir_node *nomem = new_NoMem();
581 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
582 &ia32_fp_cw_regs[REG_FPCW]);
584 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
586 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
587 if (is_op_commutative(get_irn_op(node))) {
588 set_ia32_commutative(new_node);
591 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
597 * Construct a shift/rotate binary operation, sets AM and immediate if required.
599 * @param op1 The first operand
600 * @param op2 The second operand
601 * @param func The node constructor function
602 * @return The constructed ia32 node.
604 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
605 construct_binop_func *func)
607 ir_node *block = be_transform_node(get_nodes_block(node));
608 ir_node *new_op1 = be_transform_node(op1);
610 ir_node *new_op = NULL;
611 dbg_info *dbgi = get_irn_dbg_info(node);
612 ir_graph *irg = current_ir_graph;
613 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
614 ir_node *nomem = new_NoMem();
616 assert(! mode_is_float(get_irn_mode(node))
617 && "Shift/Rotate with float not supported");
619 new_op2 = create_immediate_or_transform(op2, 'N');
621 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
624 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
626 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
628 set_ia32_emit_cl(new_op);
635 * Construct a standard unary operation, set AM and immediate if required.
637 * @param op The operand
638 * @param func The node constructor function
639 * @return The constructed ia32 node.
641 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
643 ir_node *block = be_transform_node(get_nodes_block(node));
644 ir_node *new_op = be_transform_node(op);
645 ir_node *new_node = NULL;
646 ir_graph *irg = current_ir_graph;
647 dbg_info *dbgi = get_irn_dbg_info(node);
648 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
649 ir_node *nomem = new_NoMem();
651 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
652 DB((dbg, LEVEL_1, "INT unop ..."));
653 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
655 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
661 * Creates an ia32 Add.
663 * @return the created ia32 Add node
665 static ir_node *gen_Add(ir_node *node) {
666 ir_node *block = be_transform_node(get_nodes_block(node));
667 ir_node *op1 = get_Add_left(node);
668 ir_node *new_op1 = be_transform_node(op1);
669 ir_node *op2 = get_Add_right(node);
670 ir_node *new_op2 = be_transform_node(op2);
671 ir_node *new_op = NULL;
672 ir_graph *irg = current_ir_graph;
673 dbg_info *dbgi = get_irn_dbg_info(node);
674 ir_mode *mode = get_irn_mode(node);
675 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
676 ir_node *nomem = new_NoMem();
677 ir_node *expr_op, *imm_op;
679 /* Check if immediate optimization is on and */
680 /* if it's an operation with immediate. */
681 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
682 expr_op = get_expr_op(new_op1, new_op2);
684 assert((expr_op || imm_op) && "invalid operands");
686 if (mode_is_float(mode)) {
688 if (USE_SSE2(env_cg))
689 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
691 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
696 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
697 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
699 /* No expr_op means, that we have two const - one symconst and */
700 /* one tarval or another symconst - because this case is not */
701 /* covered by constant folding */
702 /* We need to check for: */
703 /* 1) symconst + const -> becomes a LEA */
704 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
705 /* linker doesn't support two symconsts */
707 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
708 /* this is the 2nd case */
709 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
710 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
711 set_ia32_am_flavour(new_op, ia32_am_B);
712 set_ia32_op_type(new_op, ia32_AddrModeS);
714 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
715 } else if (tp1 == ia32_ImmSymConst) {
716 tarval *tv = get_ia32_Immop_tarval(new_op2);
717 long offs = get_tarval_long(tv);
719 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
720 add_irn_dep(new_op, get_irg_frame(irg));
721 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
723 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
724 add_ia32_am_offs_int(new_op, offs);
725 set_ia32_am_flavour(new_op, ia32_am_OB);
726 set_ia32_op_type(new_op, ia32_AddrModeS);
727 } else if (tp2 == ia32_ImmSymConst) {
728 tarval *tv = get_ia32_Immop_tarval(new_op1);
729 long offs = get_tarval_long(tv);
731 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
732 add_irn_dep(new_op, get_irg_frame(irg));
733 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
735 add_ia32_am_offs_int(new_op, offs);
736 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
737 set_ia32_am_flavour(new_op, ia32_am_OB);
738 set_ia32_op_type(new_op, ia32_AddrModeS);
740 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
741 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
742 tarval *restv = tarval_add(tv1, tv2);
744 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
746 new_op = new_rd_ia32_Const(dbgi, irg, block);
747 set_ia32_Const_tarval(new_op, restv);
748 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
751 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
754 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
755 tarval_classification_t class_tv, class_negtv;
756 tarval *tv = get_ia32_Immop_tarval(imm_op);
758 /* optimize tarvals */
759 class_tv = classify_tarval(tv);
760 class_negtv = classify_tarval(tarval_neg(tv));
762 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
763 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
764 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
765 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
767 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
768 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
769 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
770 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
776 /* This is a normal add */
777 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
780 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
781 set_ia32_commutative(new_op);
783 fold_immediate(new_op, 2, 3);
785 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
791 * Creates an ia32 Mul.
793 * @return the created ia32 Mul node
795 static ir_node *gen_Mul(ir_node *node) {
796 ir_node *op1 = get_Mul_left(node);
797 ir_node *op2 = get_Mul_right(node);
798 ir_mode *mode = get_irn_mode(node);
800 if (mode_is_float(mode)) {
802 if (USE_SSE2(env_cg))
803 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
805 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
809 for the lower 32bit of the result it doesn't matter whether we use
810 signed or unsigned multiplication so we use IMul as it has fewer
813 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
817 * Creates an ia32 Mulh.
818 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
819 * this result while Mul returns the lower 32 bit.
821 * @return the created ia32 Mulh node
823 static ir_node *gen_Mulh(ir_node *node) {
824 ir_node *block = be_transform_node(get_nodes_block(node));
825 ir_node *op1 = get_irn_n(node, 0);
826 ir_node *new_op1 = be_transform_node(op1);
827 ir_node *op2 = get_irn_n(node, 1);
828 ir_node *new_op2 = be_transform_node(op2);
829 ir_graph *irg = current_ir_graph;
830 dbg_info *dbgi = get_irn_dbg_info(node);
831 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
832 ir_mode *mode = get_irn_mode(node);
833 ir_node *proj_EAX, *proj_EDX, *res;
836 assert(!mode_is_float(mode) && "Mulh with float not supported");
837 if (mode_is_signed(mode)) {
838 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
840 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
843 set_ia32_commutative(res);
844 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
846 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
847 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
851 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
859 * Creates an ia32 And.
861 * @return The created ia32 And node
863 static ir_node *gen_And(ir_node *node) {
864 ir_node *op1 = get_And_left(node);
865 ir_node *op2 = get_And_right(node);
867 assert (! mode_is_float(get_irn_mode(node)));
868 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
874 * Creates an ia32 Or.
876 * @return The created ia32 Or node
878 static ir_node *gen_Or(ir_node *node) {
879 ir_node *op1 = get_Or_left(node);
880 ir_node *op2 = get_Or_right(node);
882 assert (! mode_is_float(get_irn_mode(node)));
883 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
889 * Creates an ia32 Eor.
891 * @return The created ia32 Eor node
893 static ir_node *gen_Eor(ir_node *node) {
894 ir_node *op1 = get_Eor_left(node);
895 ir_node *op2 = get_Eor_right(node);
897 assert(! mode_is_float(get_irn_mode(node)));
898 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
903 * Creates an ia32 Sub.
905 * @return The created ia32 Sub node
907 static ir_node *gen_Sub(ir_node *node) {
908 ir_node *block = be_transform_node(get_nodes_block(node));
909 ir_node *op1 = get_Sub_left(node);
910 ir_node *new_op1 = be_transform_node(op1);
911 ir_node *op2 = get_Sub_right(node);
912 ir_node *new_op2 = be_transform_node(op2);
913 ir_node *new_op = NULL;
914 ir_graph *irg = current_ir_graph;
915 dbg_info *dbgi = get_irn_dbg_info(node);
916 ir_mode *mode = get_irn_mode(node);
917 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
918 ir_node *nomem = new_NoMem();
919 ir_node *expr_op, *imm_op;
921 /* Check if immediate optimization is on and */
922 /* if it's an operation with immediate. */
923 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
924 expr_op = get_expr_op(new_op1, new_op2);
926 assert((expr_op || imm_op) && "invalid operands");
928 if (mode_is_float(mode)) {
930 if (USE_SSE2(env_cg))
931 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
933 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
938 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
939 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
941 /* No expr_op means, that we have two const - one symconst and */
942 /* one tarval or another symconst - because this case is not */
943 /* covered by constant folding */
944 /* We need to check for: */
945 /* 1) symconst - const -> becomes a LEA */
946 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
947 /* linker doesn't support two symconsts */
948 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
949 /* this is the 2nd case */
950 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
951 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
952 set_ia32_am_sc_sign(new_op);
953 set_ia32_am_flavour(new_op, ia32_am_B);
955 DBG_OPT_LEA3(op1, op2, node, new_op);
956 } else if (tp1 == ia32_ImmSymConst) {
957 tarval *tv = get_ia32_Immop_tarval(new_op2);
958 long offs = get_tarval_long(tv);
960 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
961 add_irn_dep(new_op, get_irg_frame(irg));
962 DBG_OPT_LEA3(op1, op2, node, new_op);
964 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
965 add_ia32_am_offs_int(new_op, -offs);
966 set_ia32_am_flavour(new_op, ia32_am_OB);
967 set_ia32_op_type(new_op, ia32_AddrModeS);
968 } else if (tp2 == ia32_ImmSymConst) {
969 tarval *tv = get_ia32_Immop_tarval(new_op1);
970 long offs = get_tarval_long(tv);
972 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
973 add_irn_dep(new_op, get_irg_frame(irg));
974 DBG_OPT_LEA3(op1, op2, node, new_op);
976 add_ia32_am_offs_int(new_op, offs);
977 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
978 set_ia32_am_sc_sign(new_op);
979 set_ia32_am_flavour(new_op, ia32_am_OB);
980 set_ia32_op_type(new_op, ia32_AddrModeS);
982 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
983 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
984 tarval *restv = tarval_sub(tv1, tv2);
986 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
988 new_op = new_rd_ia32_Const(dbgi, irg, block);
989 set_ia32_Const_tarval(new_op, restv);
990 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
993 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
996 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
997 tarval_classification_t class_tv, class_negtv;
998 tarval *tv = get_ia32_Immop_tarval(imm_op);
1000 /* optimize tarvals */
1001 class_tv = classify_tarval(tv);
1002 class_negtv = classify_tarval(tarval_neg(tv));
1004 if (class_tv == TV_CLASSIFY_ONE) {
1005 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1006 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1007 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1009 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1010 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1011 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1012 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1018 /* This is a normal sub */
1019 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1021 /* set AM support */
1022 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1024 fold_immediate(new_op, 2, 3);
1026 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1034 * Generates an ia32 DivMod with additional infrastructure for the
1035 * register allocator if needed.
1037 * @param dividend -no comment- :)
1038 * @param divisor -no comment- :)
1039 * @param dm_flav flavour_Div/Mod/DivMod
1040 * @return The created ia32 DivMod node
1042 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1043 ir_node *divisor, ia32_op_flavour_t dm_flav)
1045 ir_node *block = be_transform_node(get_nodes_block(node));
1046 ir_node *new_dividend = be_transform_node(dividend);
1047 ir_node *new_divisor = be_transform_node(divisor);
1048 ir_graph *irg = current_ir_graph;
1049 dbg_info *dbgi = get_irn_dbg_info(node);
1050 ir_mode *mode = get_irn_mode(node);
1051 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1052 ir_node *res, *proj_div, *proj_mod;
1053 ir_node *sign_extension;
1054 ir_node *in_keep[2];
1055 ir_node *mem, *new_mem;
1056 ir_node *projs[pn_DivMod_max];
1059 ia32_collect_Projs(node, projs, pn_DivMod_max);
1061 proj_div = proj_mod = NULL;
1065 mem = get_Div_mem(node);
1066 mode = get_Div_resmode(node);
1067 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1068 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1071 mem = get_Mod_mem(node);
1072 mode = get_Mod_resmode(node);
1073 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1074 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1076 case flavour_DivMod:
1077 mem = get_DivMod_mem(node);
1078 mode = get_DivMod_resmode(node);
1079 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1080 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1081 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1084 panic("invalid divmod flavour!");
1086 new_mem = be_transform_node(mem);
1088 if (mode_is_signed(mode)) {
1089 /* in signed mode, we need to sign extend the dividend */
1090 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1092 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1093 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1095 add_irn_dep(sign_extension, get_irg_frame(irg));
1098 if (mode_is_signed(mode)) {
1099 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1100 sign_extension, new_divisor, new_mem, dm_flav);
1102 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1103 sign_extension, new_divisor, new_mem, dm_flav);
1106 set_ia32_exc_label(res, has_exc);
1107 set_irn_pinned(res, get_irn_pinned(node));
1109 /* set AM support */
1110 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1112 /* check, which Proj-Keep, we need to add */
1114 if (proj_div == NULL) {
1115 /* We have only mod result: add div res Proj-Keep */
1116 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1119 if (proj_mod == NULL) {
1120 /* We have only div result: add mod res Proj-Keep */
1121 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1125 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1127 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1134 * Wrapper for generate_DivMod. Sets flavour_Mod.
1137 static ir_node *gen_Mod(ir_node *node) {
1138 return generate_DivMod(node, get_Mod_left(node),
1139 get_Mod_right(node), flavour_Mod);
1143 * Wrapper for generate_DivMod. Sets flavour_Div.
1146 static ir_node *gen_Div(ir_node *node) {
1147 return generate_DivMod(node, get_Div_left(node),
1148 get_Div_right(node), flavour_Div);
1152 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1154 static ir_node *gen_DivMod(ir_node *node) {
1155 return generate_DivMod(node, get_DivMod_left(node),
1156 get_DivMod_right(node), flavour_DivMod);
1162 * Creates an ia32 floating Div.
1164 * @return The created ia32 xDiv node
1166 static ir_node *gen_Quot(ir_node *node) {
1167 ir_node *block = be_transform_node(get_nodes_block(node));
1168 ir_node *op1 = get_Quot_left(node);
1169 ir_node *new_op1 = be_transform_node(op1);
1170 ir_node *op2 = get_Quot_right(node);
1171 ir_node *new_op2 = be_transform_node(op2);
1172 ir_graph *irg = current_ir_graph;
1173 dbg_info *dbgi = get_irn_dbg_info(node);
1174 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1175 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1179 if (USE_SSE2(env_cg)) {
1180 ir_mode *mode = get_irn_mode(op1);
1181 if (is_ia32_xConst(new_op2)) {
1182 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1183 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1184 copy_ia32_Immop_attr(new_op, new_op2);
1186 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1187 // Matze: disabled for now, spillslot coalescer fails
1188 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1190 set_ia32_ls_mode(new_op, mode);
1192 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1193 &ia32_fp_cw_regs[REG_FPCW]);
1194 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1195 new_op2, nomem, fpcw);
1196 // Matze: disabled for now (spillslot coalescer fails)
1197 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1199 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1205 * Creates an ia32 Shl.
1207 * @return The created ia32 Shl node
1209 static ir_node *gen_Shl(ir_node *node) {
1210 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1217 * Creates an ia32 Shr.
1219 * @return The created ia32 Shr node
1221 static ir_node *gen_Shr(ir_node *node) {
1222 return gen_shift_binop(node, get_Shr_left(node),
1223 get_Shr_right(node), new_rd_ia32_Shr);
1229 * Creates an ia32 Sar.
1231 * @return The created ia32 Shrs node
1233 static ir_node *gen_Shrs(ir_node *node) {
1234 ir_node *left = get_Shrs_left(node);
1235 ir_node *right = get_Shrs_right(node);
1236 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1237 tarval *tv = get_Const_tarval(right);
1238 long val = get_tarval_long(tv);
1240 /* this is a sign extension */
1241 ir_graph *irg = current_ir_graph;
1242 dbg_info *dbgi = get_irn_dbg_info(node);
1243 ir_node *block = be_transform_node(get_nodes_block(node));
1245 ir_node *new_op = be_transform_node(op);
1247 return new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1251 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1257 * Creates an ia32 RotL.
1259 * @param op1 The first operator
1260 * @param op2 The second operator
1261 * @return The created ia32 RotL node
1263 static ir_node *gen_RotL(ir_node *node,
1264 ir_node *op1, ir_node *op2) {
1265 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1271 * Creates an ia32 RotR.
1272 * NOTE: There is no RotR with immediate because this would always be a RotL
1273 * "imm-mode_size_bits" which can be pre-calculated.
1275 * @param op1 The first operator
1276 * @param op2 The second operator
1277 * @return The created ia32 RotR node
1279 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1281 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1287 * Creates an ia32 RotR or RotL (depending on the found pattern).
1289 * @return The created ia32 RotL or RotR node
1291 static ir_node *gen_Rot(ir_node *node) {
1292 ir_node *rotate = NULL;
1293 ir_node *op1 = get_Rot_left(node);
1294 ir_node *op2 = get_Rot_right(node);
1296 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1297 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1298 that means we can create a RotR instead of an Add and a RotL */
1300 if (get_irn_op(op2) == op_Add) {
1302 ir_node *left = get_Add_left(add);
1303 ir_node *right = get_Add_right(add);
1304 if (is_Const(right)) {
1305 tarval *tv = get_Const_tarval(right);
1306 ir_mode *mode = get_irn_mode(node);
1307 long bits = get_mode_size_bits(mode);
1309 if (get_irn_op(left) == op_Minus &&
1310 tarval_is_long(tv) &&
1311 get_tarval_long(tv) == bits)
1313 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1314 rotate = gen_RotR(node, op1, get_Minus_op(left));
1319 if (rotate == NULL) {
1320 rotate = gen_RotL(node, op1, op2);
1329 * Transforms a Minus node.
1331 * @param op The Minus operand
1332 * @return The created ia32 Minus node
1334 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1335 ir_node *block = be_transform_node(get_nodes_block(node));
1336 ir_graph *irg = current_ir_graph;
1337 dbg_info *dbgi = get_irn_dbg_info(node);
1338 ir_mode *mode = get_irn_mode(node);
1343 if (mode_is_float(mode)) {
1344 ir_node *new_op = be_transform_node(op);
1346 if (USE_SSE2(env_cg)) {
1347 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1348 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1349 ir_node *nomem = new_rd_NoMem(irg);
1351 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1353 size = get_mode_size_bits(mode);
1354 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1356 set_ia32_am_sc(res, ent);
1357 set_ia32_op_type(res, ia32_AddrModeS);
1358 set_ia32_ls_mode(res, mode);
1360 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1363 res = gen_unop(node, op, new_rd_ia32_Neg);
1366 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1372 * Transforms a Minus node.
1374 * @return The created ia32 Minus node
1376 static ir_node *gen_Minus(ir_node *node) {
1377 return gen_Minus_ex(node, get_Minus_op(node));
1382 * Transforms a Not node.
1384 * @return The created ia32 Not node
1386 static ir_node *gen_Not(ir_node *node) {
1387 ir_node *op = get_Not_op(node);
1389 assert (! mode_is_float(get_irn_mode(node)));
1390 return gen_unop(node, op, new_rd_ia32_Not);
1396 * Transforms an Abs node.
1398 * @return The created ia32 Abs node
1400 static ir_node *gen_Abs(ir_node *node) {
1401 ir_node *block = be_transform_node(get_nodes_block(node));
1402 ir_node *op = get_Abs_op(node);
1403 ir_node *new_op = be_transform_node(op);
1404 ir_graph *irg = current_ir_graph;
1405 dbg_info *dbgi = get_irn_dbg_info(node);
1406 ir_mode *mode = get_irn_mode(node);
1407 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1408 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1409 ir_node *nomem = new_NoMem();
1414 if (mode_is_float(mode)) {
1416 if (USE_SSE2(env_cg)) {
1417 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1419 size = get_mode_size_bits(mode);
1420 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1422 set_ia32_am_sc(res, ent);
1424 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1426 set_ia32_op_type(res, ia32_AddrModeS);
1427 set_ia32_ls_mode(res, mode);
1430 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1431 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1435 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1436 SET_IA32_ORIG_NODE(sign_extension,
1437 ia32_get_old_node_name(env_cg, node));
1439 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1440 sign_extension, nomem);
1441 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1443 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1444 sign_extension, nomem);
1445 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1454 * Transforms a Load.
1456 * @return the created ia32 Load node
1458 static ir_node *gen_Load(ir_node *node) {
1459 ir_node *block = be_transform_node(get_nodes_block(node));
1460 ir_node *ptr = get_Load_ptr(node);
1461 ir_node *new_ptr = be_transform_node(ptr);
1462 ir_node *mem = get_Load_mem(node);
1463 ir_node *new_mem = be_transform_node(mem);
1464 ir_graph *irg = current_ir_graph;
1465 dbg_info *dbgi = get_irn_dbg_info(node);
1466 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1467 ir_mode *mode = get_Load_mode(node);
1469 ir_node *lptr = new_ptr;
1472 ir_node *projs[pn_Load_max];
1473 ia32_am_flavour_t am_flav = ia32_am_B;
1475 ia32_collect_Projs(node, projs, pn_Load_max);
1477 /* address might be a constant (symconst or absolute address) */
1478 if (is_ia32_Const(new_ptr)) {
1483 if (mode_is_float(mode)) {
1485 if (USE_SSE2(env_cg)) {
1486 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1487 res_mode = mode_xmm;
1489 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1490 res_mode = mode_vfp;
1493 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1498 check for special case: the loaded value might not be used
1500 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
1501 /* add a result proj and a Keep to produce a pseudo use */
1502 ir_node *proj = new_r_Proj(irg, block, new_op, mode_Iu,
1504 be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
1507 /* base is a constant address */
1509 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1510 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1511 am_flav = ia32_am_N;
1513 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1514 long offs = get_tarval_long(tv);
1516 add_ia32_am_offs_int(new_op, offs);
1517 am_flav = ia32_am_O;
1521 set_irn_pinned(new_op, get_irn_pinned(node));
1522 set_ia32_op_type(new_op, ia32_AddrModeS);
1523 set_ia32_am_flavour(new_op, am_flav);
1524 set_ia32_ls_mode(new_op, mode);
1526 /* make sure we are scheduled behind the initial IncSP/Barrier
1527 * to avoid spills being placed before it
1529 if (block == get_irg_start_block(irg)) {
1530 add_irn_dep(new_op, get_irg_frame(irg));
1533 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1534 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1542 * Transforms a Store.
1544 * @return the created ia32 Store node
1546 static ir_node *gen_Store(ir_node *node) {
1547 ir_node *block = be_transform_node(get_nodes_block(node));
1548 ir_node *ptr = get_Store_ptr(node);
1549 ir_node *new_ptr = be_transform_node(ptr);
1550 ir_node *val = get_Store_value(node);
1552 ir_node *mem = get_Store_mem(node);
1553 ir_node *new_mem = be_transform_node(mem);
1554 ir_graph *irg = current_ir_graph;
1555 dbg_info *dbgi = get_irn_dbg_info(node);
1556 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1557 ir_node *sptr = new_ptr;
1558 ir_mode *mode = get_irn_mode(val);
1561 ia32_am_flavour_t am_flav = ia32_am_B;
1563 /* address might be a constant (symconst or absolute address) */
1564 if (is_ia32_Const(new_ptr)) {
1569 if (mode_is_float(mode)) {
1572 new_val = be_transform_node(val);
1573 if (USE_SSE2(env_cg)) {
1574 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1577 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1581 new_val = create_immediate_or_transform(val, 0);
1583 if (get_mode_size_bits(mode) == 8) {
1584 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1587 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1592 /* base is an constant address */
1594 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1595 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1596 am_flav = ia32_am_N;
1598 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1599 long offs = get_tarval_long(tv);
1601 add_ia32_am_offs_int(new_op, offs);
1602 am_flav = ia32_am_O;
1606 set_irn_pinned(new_op, get_irn_pinned(node));
1607 set_ia32_op_type(new_op, ia32_AddrModeD);
1608 set_ia32_am_flavour(new_op, am_flav);
1609 set_ia32_ls_mode(new_op, mode);
1611 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1612 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1617 static ir_node *try_create_TestJmp(ir_node *block, ir_node *node, long pnc)
1619 ir_node *cmp_left = get_Cmp_left(node);
1620 ir_node *new_cmp_left;
1621 ir_node *cmp_right = get_Cmp_right(node);
1622 ir_node *new_cmp_right;
1629 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1631 if(!is_Const_0(cmp_right))
1634 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1635 and_left = get_And_left(cmp_left);
1636 and_right = get_And_right(cmp_left);
1638 new_cmp_left = be_transform_node(and_left);
1639 new_cmp_right = create_immediate_or_transform(and_right, 0);
1641 new_cmp_left = be_transform_node(cmp_left);
1642 new_cmp_right = be_transform_node(cmp_left);
1645 dbgi = get_irn_dbg_info(node);
1646 noreg = ia32_new_NoReg_gp(env_cg);
1647 nomem = new_NoMem();
1649 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1650 new_cmp_left, new_cmp_right, nomem, pnc);
1651 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1652 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1657 static ir_node *create_Switch(ir_node *node)
1659 ir_graph *irg = current_ir_graph;
1660 dbg_info *dbgi = get_irn_dbg_info(node);
1661 ir_node *block = be_transform_node(get_nodes_block(node));
1662 ir_node *sel = get_Cond_selector(node);
1663 ir_node *new_sel = be_transform_node(sel);
1665 int switch_min = INT_MAX;
1666 const ir_edge_t *edge;
1668 /* determine the smallest switch case value */
1669 foreach_out_edge(node, edge) {
1670 ir_node *proj = get_edge_src_irn(edge);
1671 int pn = get_Proj_proj(proj);
1676 if (switch_min != 0) {
1677 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1679 /* if smallest switch case is not 0 we need an additional sub */
1680 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1681 add_ia32_am_offs_int(new_sel, -switch_min);
1682 set_ia32_am_flavour(new_sel, ia32_am_OB);
1683 set_ia32_op_type(new_sel, ia32_AddrModeS);
1685 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1688 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1689 set_ia32_pncode(res, get_Cond_defaultProj(node));
1691 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1697 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1699 * @return The transformed node.
1701 static ir_node *gen_Cond(ir_node *node) {
1702 ir_node *block = be_transform_node(get_nodes_block(node));
1703 ir_graph *irg = current_ir_graph;
1704 dbg_info *dbgi = get_irn_dbg_info(node);
1705 ir_node *sel = get_Cond_selector(node);
1706 ir_mode *sel_mode = get_irn_mode(sel);
1707 ir_node *res = NULL;
1708 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1715 ir_node *nomem = new_NoMem();
1718 if (sel_mode != mode_b) {
1719 return create_Switch(node);
1722 cmp = get_Proj_pred(sel);
1723 cmp_a = get_Cmp_left(cmp);
1724 cmp_b = get_Cmp_right(cmp);
1725 cmp_mode = get_irn_mode(cmp_a);
1726 pnc = get_Proj_proj(sel);
1727 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1728 pnc |= ia32_pn_Cmp_Unsigned;
1731 if(mode_needs_gp_reg(cmp_mode)) {
1732 res = try_create_TestJmp(block, cmp, pnc);
1737 new_cmp_a = be_transform_node(cmp_a);
1738 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1740 if (mode_is_float(cmp_mode)) {
1742 if (USE_SSE2(env_cg)) {
1743 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1745 set_ia32_commutative(res);
1746 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1747 set_ia32_ls_mode(res, cmp_mode);
1750 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1751 set_ia32_commutative(res);
1752 proj_eax = new_r_Proj(irg, block, res, mode_Iu,
1753 pn_ia32_vfCondJmp_temp_reg_eax);
1754 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1,
1758 assert(get_mode_size_bits(cmp_mode) == 32);
1759 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1760 new_cmp_a, new_cmp_b, nomem, pnc);
1761 set_ia32_commutative(res);
1762 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1765 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1773 * Transforms a CopyB node.
1775 * @return The transformed node.
1777 static ir_node *gen_CopyB(ir_node *node) {
1778 ir_node *block = be_transform_node(get_nodes_block(node));
1779 ir_node *src = get_CopyB_src(node);
1780 ir_node *new_src = be_transform_node(src);
1781 ir_node *dst = get_CopyB_dst(node);
1782 ir_node *new_dst = be_transform_node(dst);
1783 ir_node *mem = get_CopyB_mem(node);
1784 ir_node *new_mem = be_transform_node(mem);
1785 ir_node *res = NULL;
1786 ir_graph *irg = current_ir_graph;
1787 dbg_info *dbgi = get_irn_dbg_info(node);
1788 int size = get_type_size_bytes(get_CopyB_type(node));
1789 ir_mode *dst_mode = get_irn_mode(dst);
1790 ir_mode *src_mode = get_irn_mode(src);
1794 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1795 /* then we need the size explicitly in ECX. */
1796 if (size >= 32 * 4) {
1797 rem = size & 0x3; /* size % 4 */
1800 res = new_rd_ia32_Const(dbgi, irg, block);
1801 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1802 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1804 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1805 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1807 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1808 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1809 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1810 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1811 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1814 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1815 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1817 /* ok: now attach Proj's because movsd will destroy esi and edi */
1818 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1819 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1820 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1823 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1829 ir_node *gen_be_Copy(ir_node *node)
1831 ir_node *result = be_duplicate_node(node);
1832 ir_mode *mode = get_irn_mode(result);
1834 if (mode_needs_gp_reg(mode)) {
1835 set_irn_mode(result, mode_Iu);
1842 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1843 dbg_info *dbgi, ir_node *block)
1845 ir_graph *irg = current_ir_graph;
1846 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1847 ir_node *nomem = new_rd_NoMem(irg);
1848 ir_node *new_cmp_left;
1849 ir_node *new_cmp_right;
1852 /* can we use a test instruction? */
1853 if(is_Const_0(cmp_right)) {
1854 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1855 if(is_And(cmp_left) &&
1856 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1857 ir_node *and_left = get_And_left(cmp_left);
1858 ir_node *and_right = get_And_right(cmp_left);
1860 new_cmp_left = be_transform_node(and_left);
1861 new_cmp_right = create_immediate_or_transform(and_right, 0);
1863 new_cmp_left = be_transform_node(cmp_left);
1864 new_cmp_right = be_transform_node(cmp_left);
1867 res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
1868 new_cmp_left, new_cmp_right, nomem, pnc);
1869 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1874 new_cmp_left = be_transform_node(cmp_left);
1875 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1876 res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
1877 new_cmp_left, new_cmp_right, nomem, pnc);
1882 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1883 ir_node *val_true, ir_node *val_false,
1884 dbg_info *dbgi, ir_node *block)
1886 ir_graph *irg = current_ir_graph;
1887 ir_node *new_val_true = be_transform_node(val_true);
1888 ir_node *new_val_false = be_transform_node(val_false);
1889 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1890 ir_node *nomem = new_NoMem();
1891 ir_node *new_cmp_left;
1892 ir_node *new_cmp_right;
1895 /* cmovs with unknowns are pointless... */
1896 if(is_Unknown(val_true)) {
1897 #ifdef DEBUG_libfirm
1898 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1900 return new_val_false;
1902 if(is_Unknown(val_false)) {
1903 #ifdef DEBUG_libfirm
1904 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1906 return new_val_true;
1909 /* can we use a test instruction? */
1910 if(is_Const_0(cmp_right)) {
1911 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1912 if(is_And(cmp_left) &&
1913 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1914 ir_node *and_left = get_And_left(cmp_left);
1915 ir_node *and_right = get_And_right(cmp_left);
1917 new_cmp_left = be_transform_node(and_left);
1918 new_cmp_right = create_immediate_or_transform(and_right, 0);
1920 new_cmp_left = be_transform_node(cmp_left);
1921 new_cmp_right = be_transform_node(cmp_left);
1924 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, block, noreg, noreg,
1925 new_cmp_left, new_cmp_right, nomem,
1926 new_val_true, new_val_false, pnc);
1927 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1932 new_cmp_left = be_transform_node(cmp_left);
1933 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1935 res = new_rd_ia32_CmpCMov(dbgi, irg, block, noreg, noreg, new_cmp_left,
1936 new_cmp_right, nomem, new_val_true, new_val_false,
1938 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1945 * Transforms a Psi node into CMov.
1947 * @return The transformed node.
1949 static ir_node *gen_Psi(ir_node *node) {
1950 ir_node *psi_true = get_Psi_val(node, 0);
1951 ir_node *psi_default = get_Psi_default(node);
1952 ia32_code_gen_t *cg = env_cg;
1953 ir_node *cond = get_Psi_cond(node, 0);
1954 ir_node *block = be_transform_node(get_nodes_block(node));
1955 dbg_info *dbgi = get_irn_dbg_info(node);
1962 assert(get_Psi_n_conds(node) == 1);
1963 assert(get_irn_mode(cond) == mode_b);
1965 if(is_And(cond) || is_Or(cond)) {
1966 /* this is a psi with a complicated condition, we have to compare it
1969 cmp_right = new_Const_long(mode_Iu, 0);
1973 ir_node *cmp = get_Proj_pred(cond);
1975 cmp_left = get_Cmp_left(cmp);
1976 cmp_right = get_Cmp_right(cmp);
1977 cmp_mode = get_irn_mode(cmp_left);
1978 pnc = get_Proj_proj(cond);
1980 assert(!mode_is_float(cmp_mode));
1982 if (!mode_is_signed(cmp_mode)) {
1983 pnc |= ia32_pn_Cmp_Unsigned;
1987 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
1988 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
1989 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
1990 pnc = get_negated_pnc(pnc, cmp_mode);
1991 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
1993 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
1996 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2002 * Following conversion rules apply:
2006 * 1) n bit -> m bit n > m (downscale)
2008 * 2) n bit -> m bit n == m (sign change)
2010 * 3) n bit -> m bit n < m (upscale)
2011 * a) source is signed: movsx
2012 * b) source is unsigned: and with lower bits sets
2016 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2020 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2024 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2025 * x87 is mode_E internally, conversions happen only at load and store
2026 * in non-strict semantic
2030 * Create a conversion from x87 state register to general purpose.
2032 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2033 ir_node *block = be_transform_node(get_nodes_block(node));
2034 ir_node *op = get_Conv_op(node);
2035 ir_node *new_op = be_transform_node(op);
2036 ia32_code_gen_t *cg = env_cg;
2037 ir_graph *irg = current_ir_graph;
2038 dbg_info *dbgi = get_irn_dbg_info(node);
2039 ir_node *noreg = ia32_new_NoReg_gp(cg);
2040 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2041 ir_node *fist, *load;
2044 fist = new_rd_ia32_vfist(dbgi, irg, block,
2045 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2047 set_irn_pinned(fist, op_pin_state_floats);
2048 set_ia32_use_frame(fist);
2049 set_ia32_op_type(fist, ia32_AddrModeD);
2050 set_ia32_am_flavour(fist, ia32_am_B);
2051 set_ia32_ls_mode(fist, mode_Iu);
2052 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2055 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2057 set_irn_pinned(load, op_pin_state_floats);
2058 set_ia32_use_frame(load);
2059 set_ia32_op_type(load, ia32_AddrModeS);
2060 set_ia32_am_flavour(load, ia32_am_B);
2061 set_ia32_ls_mode(load, mode_Iu);
2062 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2064 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2068 * Create a conversion from general purpose to x87 register
2070 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2071 ir_node *block = be_transform_node(get_nodes_block(node));
2072 ir_node *op = get_Conv_op(node);
2073 ir_node *new_op = be_transform_node(op);
2074 ir_graph *irg = current_ir_graph;
2075 dbg_info *dbgi = get_irn_dbg_info(node);
2076 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2077 ir_node *nomem = new_NoMem();
2078 ir_node *fild, *store;
2081 /* first convert to 32 bit if necessary */
2082 src_bits = get_mode_size_bits(src_mode);
2083 if (src_bits == 8) {
2084 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2085 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2086 set_ia32_ls_mode(new_op, src_mode);
2087 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2088 } else if (src_bits < 32) {
2089 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2090 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2091 set_ia32_ls_mode(new_op, src_mode);
2092 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2096 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2098 set_ia32_use_frame(store);
2099 set_ia32_op_type(store, ia32_AddrModeD);
2100 set_ia32_am_flavour(store, ia32_am_OB);
2101 set_ia32_ls_mode(store, mode_Iu);
2104 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2106 set_ia32_use_frame(fild);
2107 set_ia32_op_type(fild, ia32_AddrModeS);
2108 set_ia32_am_flavour(fild, ia32_am_OB);
2109 set_ia32_ls_mode(fild, mode_Iu);
2111 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2114 static ir_node *create_Strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
2117 ir_node *block = get_nodes_block(node);
2118 ir_graph *irg = current_ir_graph;
2119 dbg_info *dbgi = get_irn_dbg_info(node);
2120 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2121 ir_node *nomem = new_NoMem();
2122 int src_bits = get_mode_size_bits(src_mode);
2123 int tgt_bits = get_mode_size_bits(tgt_mode);
2124 ir_node *frame = get_irg_frame(irg);
2125 ir_mode *smaller_mode;
2126 ir_node *store, *load;
2129 if(src_bits <= tgt_bits)
2130 smaller_mode = src_mode;
2132 smaller_mode = tgt_mode;
2134 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2136 set_ia32_use_frame(store);
2137 set_ia32_op_type(store, ia32_AddrModeD);
2138 set_ia32_am_flavour(store, ia32_am_OB);
2140 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2142 set_ia32_use_frame(load);
2143 set_ia32_op_type(load, ia32_AddrModeS);
2144 set_ia32_am_flavour(load, ia32_am_OB);
2146 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2151 * Transforms a Conv node.
2153 * @return The created ia32 Conv node
2155 static ir_node *gen_Conv(ir_node *node) {
2156 ir_node *block = be_transform_node(get_nodes_block(node));
2157 ir_node *op = get_Conv_op(node);
2158 ir_node *new_op = be_transform_node(op);
2159 ir_graph *irg = current_ir_graph;
2160 dbg_info *dbgi = get_irn_dbg_info(node);
2161 ir_mode *src_mode = get_irn_mode(op);
2162 ir_mode *tgt_mode = get_irn_mode(node);
2163 int src_bits = get_mode_size_bits(src_mode);
2164 int tgt_bits = get_mode_size_bits(tgt_mode);
2165 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2166 ir_node *nomem = new_rd_NoMem(irg);
2169 if (src_mode == tgt_mode) {
2170 if (get_Conv_strict(node)) {
2171 if (USE_SSE2(env_cg)) {
2172 /* when we are in SSE mode, we can kill all strict no-op conversion */
2176 /* this should be optimized already, but who knows... */
2177 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2178 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2183 if (mode_is_float(src_mode)) {
2184 /* we convert from float ... */
2185 if (mode_is_float(tgt_mode)) {
2186 if(src_mode == mode_E && tgt_mode == mode_D
2187 && !get_Conv_strict(node)) {
2188 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2193 if (USE_SSE2(env_cg)) {
2194 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2195 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2196 set_ia32_ls_mode(res, tgt_mode);
2198 // Matze: TODO what about strict convs?
2199 if(get_Conv_strict(node)) {
2200 res = create_Strict_conv(src_mode, tgt_mode, new_op);
2201 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2204 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2209 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2210 if (USE_SSE2(env_cg)) {
2211 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2212 set_ia32_ls_mode(res, src_mode);
2214 return gen_x87_fp_to_gp(node);
2218 /* we convert from int ... */
2219 if (mode_is_float(tgt_mode)) {
2222 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2223 if (USE_SSE2(env_cg)) {
2224 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2225 set_ia32_ls_mode(res, tgt_mode);
2226 if(src_bits == 32) {
2227 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2230 return gen_x87_gp_to_fp(node, src_mode);
2234 ir_mode *smaller_mode;
2237 if (src_bits == tgt_bits) {
2238 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2242 if (src_bits < tgt_bits) {
2243 smaller_mode = src_mode;
2244 smaller_bits = src_bits;
2246 smaller_mode = tgt_mode;
2247 smaller_bits = tgt_bits;
2250 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2251 if (smaller_bits == 8) {
2252 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2253 set_ia32_ls_mode(res, smaller_mode);
2255 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2256 set_ia32_ls_mode(res, smaller_mode);
2258 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2262 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2268 int check_immediate_constraint(long val, char immediate_constraint_type)
2270 switch (immediate_constraint_type) {
2274 return val >= 0 && val <= 32;
2276 return val >= 0 && val <= 63;
2278 return val >= -128 && val <= 127;
2280 return val == 0xff || val == 0xffff;
2282 return val >= 0 && val <= 3;
2284 return val >= 0 && val <= 255;
2286 return val >= 0 && val <= 127;
2290 panic("Invalid immediate constraint found");
2295 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2298 tarval *offset = NULL;
2299 int offset_sign = 0;
2301 ir_entity *symconst_ent = NULL;
2302 int symconst_sign = 0;
2304 ir_node *cnst = NULL;
2305 ir_node *symconst = NULL;
2311 mode = get_irn_mode(node);
2312 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2313 !mode_is_reference(mode)) {
2317 if(is_Minus(node)) {
2319 node = get_Minus_op(node);
2322 if(is_Const(node)) {
2325 offset_sign = minus;
2326 } else if(is_SymConst(node)) {
2329 symconst_sign = minus;
2330 } else if(is_Add(node)) {
2331 ir_node *left = get_Add_left(node);
2332 ir_node *right = get_Add_right(node);
2333 if(is_Const(left) && is_SymConst(right)) {
2336 symconst_sign = minus;
2337 offset_sign = minus;
2338 } else if(is_SymConst(left) && is_Const(right)) {
2341 symconst_sign = minus;
2342 offset_sign = minus;
2344 } else if(is_Sub(node)) {
2345 ir_node *left = get_Sub_left(node);
2346 ir_node *right = get_Sub_right(node);
2347 if(is_Const(left) && is_SymConst(right)) {
2350 symconst_sign = !minus;
2351 offset_sign = minus;
2352 } else if(is_SymConst(left) && is_Const(right)) {
2355 symconst_sign = minus;
2356 offset_sign = !minus;
2363 offset = get_Const_tarval(cnst);
2364 if(tarval_is_long(offset)) {
2365 val = get_tarval_long(offset);
2366 } else if(tarval_is_null(offset)) {
2369 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2374 if(!check_immediate_constraint(val, immediate_constraint_type))
2377 if(symconst != NULL) {
2378 if(immediate_constraint_type != 0) {
2379 /* we need full 32bits for symconsts */
2383 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2385 symconst_ent = get_SymConst_entity(symconst);
2387 if(cnst == NULL && symconst == NULL)
2390 if(offset_sign && offset != NULL) {
2391 offset = tarval_neg(offset);
2394 irg = current_ir_graph;
2395 dbgi = get_irn_dbg_info(node);
2396 block = get_irg_start_block(irg);
2397 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2399 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2401 /* make sure we don't schedule stuff before the barrier */
2402 add_irn_dep(res, get_irg_frame(irg));
2408 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2410 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2411 if (new_node == NULL) {
2412 new_node = be_transform_node(node);
2417 typedef struct constraint_t constraint_t;
2418 struct constraint_t {
2421 const arch_register_req_t **out_reqs;
2423 const arch_register_req_t *req;
2424 unsigned immediate_possible;
2425 char immediate_type;
2428 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2430 int immediate_possible = 0;
2431 char immediate_type = 0;
2432 unsigned limited = 0;
2433 const arch_register_class_t *cls = NULL;
2435 struct obstack *obst;
2436 arch_register_req_t *req;
2437 unsigned *limited_ptr;
2441 /* TODO: replace all the asserts with nice error messages */
2443 printf("Constraint: %s\n", c);
2453 assert(cls == NULL ||
2454 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2455 cls = &ia32_reg_classes[CLASS_ia32_gp];
2456 limited |= 1 << REG_EAX;
2459 assert(cls == NULL ||
2460 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2461 cls = &ia32_reg_classes[CLASS_ia32_gp];
2462 limited |= 1 << REG_EBX;
2465 assert(cls == NULL ||
2466 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2467 cls = &ia32_reg_classes[CLASS_ia32_gp];
2468 limited |= 1 << REG_ECX;
2471 assert(cls == NULL ||
2472 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2473 cls = &ia32_reg_classes[CLASS_ia32_gp];
2474 limited |= 1 << REG_EDX;
2477 assert(cls == NULL ||
2478 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2479 cls = &ia32_reg_classes[CLASS_ia32_gp];
2480 limited |= 1 << REG_EDI;
2483 assert(cls == NULL ||
2484 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2485 cls = &ia32_reg_classes[CLASS_ia32_gp];
2486 limited |= 1 << REG_ESI;
2489 case 'q': /* q means lower part of the regs only, this makes no
2490 * difference to Q for us (we only assigne whole registers) */
2491 assert(cls == NULL ||
2492 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2493 cls = &ia32_reg_classes[CLASS_ia32_gp];
2494 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2498 assert(cls == NULL ||
2499 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2500 cls = &ia32_reg_classes[CLASS_ia32_gp];
2501 limited |= 1 << REG_EAX | 1 << REG_EDX;
2504 assert(cls == NULL ||
2505 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2506 cls = &ia32_reg_classes[CLASS_ia32_gp];
2507 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2508 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2515 assert(cls == NULL);
2516 cls = &ia32_reg_classes[CLASS_ia32_gp];
2522 /* TODO: mark values so the x87 simulator knows about t and u */
2523 assert(cls == NULL);
2524 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2529 assert(cls == NULL);
2530 /* TODO: check that sse2 is supported */
2531 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2541 assert(!immediate_possible);
2542 immediate_possible = 1;
2543 immediate_type = *c;
2547 assert(!immediate_possible);
2548 immediate_possible = 1;
2552 assert(!immediate_possible && cls == NULL);
2553 immediate_possible = 1;
2554 cls = &ia32_reg_classes[CLASS_ia32_gp];
2567 assert(constraint->is_in && "can only specify same constraint "
2570 sscanf(c, "%d%n", &same_as, &p);
2577 case 'E': /* no float consts yet */
2578 case 'F': /* no float consts yet */
2579 case 's': /* makes no sense on x86 */
2580 case 'X': /* we can't support that in firm */
2584 case '<': /* no autodecrement on x86 */
2585 case '>': /* no autoincrement on x86 */
2586 case 'C': /* sse constant not supported yet */
2587 case 'G': /* 80387 constant not supported yet */
2588 case 'y': /* we don't support mmx registers yet */
2589 case 'Z': /* not available in 32 bit mode */
2590 case 'e': /* not available in 32 bit mode */
2591 assert(0 && "asm constraint not supported");
2594 assert(0 && "unknown asm constraint found");
2601 const arch_register_req_t *other_constr;
2603 assert(cls == NULL && "same as and register constraint not supported");
2604 assert(!immediate_possible && "same as and immediate constraint not "
2606 assert(same_as < constraint->n_outs && "wrong constraint number in "
2607 "same_as constraint");
2609 other_constr = constraint->out_reqs[same_as];
2611 req = obstack_alloc(obst, sizeof(req[0]));
2612 req->cls = other_constr->cls;
2613 req->type = arch_register_req_type_should_be_same;
2614 req->limited = NULL;
2615 req->other_same = pos;
2616 req->other_different = -1;
2618 /* switch constraints. This is because in firm we have same_as
2619 * constraints on the output constraints while in the gcc asm syntax
2620 * they are specified on the input constraints */
2621 constraint->req = other_constr;
2622 constraint->out_reqs[same_as] = req;
2623 constraint->immediate_possible = 0;
2627 if(immediate_possible && cls == NULL) {
2628 cls = &ia32_reg_classes[CLASS_ia32_gp];
2630 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2631 assert(cls != NULL);
2633 if(immediate_possible) {
2634 assert(constraint->is_in
2635 && "imeediates make no sense for output constraints");
2637 /* todo: check types (no float input on 'r' constrainted in and such... */
2639 irg = current_ir_graph;
2640 obst = get_irg_obstack(irg);
2643 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2644 limited_ptr = (unsigned*) (req+1);
2646 req = obstack_alloc(obst, sizeof(req[0]));
2648 memset(req, 0, sizeof(req[0]));
2651 req->type = arch_register_req_type_limited;
2652 *limited_ptr = limited;
2653 req->limited = limited_ptr;
2655 req->type = arch_register_req_type_normal;
2659 constraint->req = req;
2660 constraint->immediate_possible = immediate_possible;
2661 constraint->immediate_type = immediate_type;
2665 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2672 panic("Clobbers not supported yet");
2675 ir_node *gen_ASM(ir_node *node)
2678 ir_graph *irg = current_ir_graph;
2679 ir_node *block = be_transform_node(get_nodes_block(node));
2680 dbg_info *dbgi = get_irn_dbg_info(node);
2687 ia32_asm_attr_t *attr;
2688 const arch_register_req_t **out_reqs;
2689 const arch_register_req_t **in_reqs;
2690 struct obstack *obst;
2691 constraint_t parsed_constraint;
2693 /* assembler could contain float statements */
2696 /* transform inputs */
2697 arity = get_irn_arity(node);
2698 in = alloca(arity * sizeof(in[0]));
2699 memset(in, 0, arity * sizeof(in[0]));
2701 n_outs = get_ASM_n_output_constraints(node);
2702 n_clobbers = get_ASM_n_clobbers(node);
2703 out_arity = n_outs + n_clobbers;
2705 /* construct register constraints */
2706 obst = get_irg_obstack(irg);
2707 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2708 parsed_constraint.out_reqs = out_reqs;
2709 parsed_constraint.n_outs = n_outs;
2710 parsed_constraint.is_in = 0;
2711 for(i = 0; i < out_arity; ++i) {
2715 const ir_asm_constraint *constraint;
2716 constraint = & get_ASM_output_constraints(node) [i];
2717 c = get_id_str(constraint->constraint);
2718 parse_asm_constraint(i, &parsed_constraint, c);
2720 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2721 c = get_id_str(glob_id);
2722 parse_clobber(node, i, &parsed_constraint, c);
2724 out_reqs[i] = parsed_constraint.req;
2727 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2728 parsed_constraint.is_in = 1;
2729 for(i = 0; i < arity; ++i) {
2730 const ir_asm_constraint *constraint;
2734 constraint = & get_ASM_input_constraints(node) [i];
2735 constr_id = constraint->constraint;
2736 c = get_id_str(constr_id);
2737 parse_asm_constraint(i, &parsed_constraint, c);
2738 in_reqs[i] = parsed_constraint.req;
2740 if(parsed_constraint.immediate_possible) {
2741 ir_node *pred = get_irn_n(node, i);
2742 char imm_type = parsed_constraint.immediate_type;
2743 ir_node *immediate = try_create_Immediate(pred, imm_type);
2745 if(immediate != NULL) {
2751 /* transform inputs */
2752 for(i = 0; i < arity; ++i) {
2754 ir_node *transformed;
2759 pred = get_irn_n(node, i);
2760 transformed = be_transform_node(pred);
2761 in[i] = transformed;
2764 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2766 generic_attr = get_irn_generic_attr(res);
2767 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2768 attr->asm_text = get_ASM_text(node);
2769 set_ia32_out_req_all(res, out_reqs);
2770 set_ia32_in_req_all(res, in_reqs);
2772 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2777 /********************************************
2780 * | |__ ___ _ __ ___ __| | ___ ___
2781 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2782 * | |_) | __/ | | | (_) | (_| | __/\__ \
2783 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2785 ********************************************/
2787 static ir_node *gen_be_StackParam(ir_node *node) {
2788 ir_node *block = be_transform_node(get_nodes_block(node));
2789 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2790 ir_node *new_ptr = be_transform_node(ptr);
2791 ir_node *new_op = NULL;
2792 ir_graph *irg = current_ir_graph;
2793 dbg_info *dbgi = get_irn_dbg_info(node);
2794 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2795 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2796 ir_mode *load_mode = get_irn_mode(node);
2797 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2801 if (mode_is_float(load_mode)) {
2803 if (USE_SSE2(env_cg)) {
2804 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2805 pn_res = pn_ia32_xLoad_res;
2806 proj_mode = mode_xmm;
2808 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2809 pn_res = pn_ia32_vfld_res;
2810 proj_mode = mode_vfp;
2813 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2814 proj_mode = mode_Iu;
2815 pn_res = pn_ia32_Load_res;
2818 set_irn_pinned(new_op, op_pin_state_floats);
2819 set_ia32_frame_ent(new_op, ent);
2820 set_ia32_use_frame(new_op);
2822 set_ia32_op_type(new_op, ia32_AddrModeS);
2823 set_ia32_am_flavour(new_op, ia32_am_B);
2824 set_ia32_ls_mode(new_op, load_mode);
2825 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2827 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2829 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2833 * Transforms a FrameAddr into an ia32 Add.
2835 static ir_node *gen_be_FrameAddr(ir_node *node) {
2836 ir_node *block = be_transform_node(get_nodes_block(node));
2837 ir_node *op = be_get_FrameAddr_frame(node);
2838 ir_node *new_op = be_transform_node(op);
2839 ir_graph *irg = current_ir_graph;
2840 dbg_info *dbgi = get_irn_dbg_info(node);
2841 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2844 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2845 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2846 set_ia32_use_frame(res);
2847 set_ia32_am_flavour(res, ia32_am_OB);
2849 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2855 * Transforms a FrameLoad into an ia32 Load.
2857 static ir_node *gen_be_FrameLoad(ir_node *node) {
2858 ir_node *block = be_transform_node(get_nodes_block(node));
2859 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2860 ir_node *new_mem = be_transform_node(mem);
2861 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2862 ir_node *new_ptr = be_transform_node(ptr);
2863 ir_node *new_op = NULL;
2864 ir_graph *irg = current_ir_graph;
2865 dbg_info *dbgi = get_irn_dbg_info(node);
2866 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2867 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2868 ir_mode *mode = get_type_mode(get_entity_type(ent));
2869 ir_node *projs[pn_Load_max];
2871 ia32_collect_Projs(node, projs, pn_Load_max);
2873 if (mode_is_float(mode)) {
2875 if (USE_SSE2(env_cg)) {
2876 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2879 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2883 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2886 set_irn_pinned(new_op, op_pin_state_floats);
2887 set_ia32_frame_ent(new_op, ent);
2888 set_ia32_use_frame(new_op);
2890 set_ia32_op_type(new_op, ia32_AddrModeS);
2891 set_ia32_am_flavour(new_op, ia32_am_B);
2892 set_ia32_ls_mode(new_op, mode);
2893 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2895 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2902 * Transforms a FrameStore into an ia32 Store.
2904 static ir_node *gen_be_FrameStore(ir_node *node) {
2905 ir_node *block = be_transform_node(get_nodes_block(node));
2906 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2907 ir_node *new_mem = be_transform_node(mem);
2908 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2909 ir_node *new_ptr = be_transform_node(ptr);
2910 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2911 ir_node *new_val = be_transform_node(val);
2912 ir_node *new_op = NULL;
2913 ir_graph *irg = current_ir_graph;
2914 dbg_info *dbgi = get_irn_dbg_info(node);
2915 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2916 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2917 ir_mode *mode = get_irn_mode(val);
2919 if (mode_is_float(mode)) {
2921 if (USE_SSE2(env_cg)) {
2922 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2924 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2926 } else if (get_mode_size_bits(mode) == 8) {
2927 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2929 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2932 set_ia32_frame_ent(new_op, ent);
2933 set_ia32_use_frame(new_op);
2935 set_ia32_op_type(new_op, ia32_AddrModeD);
2936 set_ia32_am_flavour(new_op, ia32_am_B);
2937 set_ia32_ls_mode(new_op, mode);
2939 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2945 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2947 static ir_node *gen_be_Return(ir_node *node) {
2948 ir_graph *irg = current_ir_graph;
2949 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2950 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2951 ir_entity *ent = get_irg_entity(irg);
2952 ir_type *tp = get_entity_type(ent);
2957 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2958 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2961 int pn_ret_val, pn_ret_mem, arity, i;
2963 assert(ret_val != NULL);
2964 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
2965 return be_duplicate_node(node);
2968 res_type = get_method_res_type(tp, 0);
2970 if (! is_Primitive_type(res_type)) {
2971 return be_duplicate_node(node);
2974 mode = get_type_mode(res_type);
2975 if (! mode_is_float(mode)) {
2976 return be_duplicate_node(node);
2979 assert(get_method_n_ress(tp) == 1);
2981 pn_ret_val = get_Proj_proj(ret_val);
2982 pn_ret_mem = get_Proj_proj(ret_mem);
2984 /* get the Barrier */
2985 barrier = get_Proj_pred(ret_val);
2987 /* get result input of the Barrier */
2988 ret_val = get_irn_n(barrier, pn_ret_val);
2989 new_ret_val = be_transform_node(ret_val);
2991 /* get memory input of the Barrier */
2992 ret_mem = get_irn_n(barrier, pn_ret_mem);
2993 new_ret_mem = be_transform_node(ret_mem);
2995 frame = get_irg_frame(irg);
2997 dbgi = get_irn_dbg_info(barrier);
2998 block = be_transform_node(get_nodes_block(barrier));
3000 noreg = ia32_new_NoReg_gp(env_cg);
3002 /* store xmm0 onto stack */
3003 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
3004 set_ia32_ls_mode(sse_store, mode);
3005 set_ia32_op_type(sse_store, ia32_AddrModeD);
3006 set_ia32_use_frame(sse_store);
3007 set_ia32_am_flavour(sse_store, ia32_am_B);
3010 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
3011 set_ia32_ls_mode(fld, mode);
3012 set_ia32_op_type(fld, ia32_AddrModeS);
3013 set_ia32_use_frame(fld);
3014 set_ia32_am_flavour(fld, ia32_am_B);
3016 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3017 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3018 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3020 /* create a new barrier */
3021 arity = get_irn_arity(barrier);
3022 in = alloca(arity * sizeof(in[0]));
3023 for (i = 0; i < arity; ++i) {
3026 if (i == pn_ret_val) {
3028 } else if (i == pn_ret_mem) {
3031 ir_node *in = get_irn_n(barrier, i);
3032 new_in = be_transform_node(in);
3037 new_barrier = new_ir_node(dbgi, irg, block,
3038 get_irn_op(barrier), get_irn_mode(barrier),
3040 copy_node_attr(barrier, new_barrier);
3041 be_duplicate_deps(barrier, new_barrier);
3042 be_set_transformed_node(barrier, new_barrier);
3043 mark_irn_visited(barrier);
3045 /* transform normally */
3046 return be_duplicate_node(node);
3050 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3052 static ir_node *gen_be_AddSP(ir_node *node) {
3053 ir_node *block = be_transform_node(get_nodes_block(node));
3054 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3056 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3057 ir_node *new_sp = be_transform_node(sp);
3058 ir_graph *irg = current_ir_graph;
3059 dbg_info *dbgi = get_irn_dbg_info(node);
3060 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3061 ir_node *nomem = new_NoMem();
3064 new_sz = create_immediate_or_transform(sz, 0);
3066 /* ia32 stack grows in reverse direction, make a SubSP */
3067 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3069 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3070 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3076 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3078 static ir_node *gen_be_SubSP(ir_node *node) {
3079 ir_node *block = be_transform_node(get_nodes_block(node));
3080 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3082 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3083 ir_node *new_sp = be_transform_node(sp);
3084 ir_graph *irg = current_ir_graph;
3085 dbg_info *dbgi = get_irn_dbg_info(node);
3086 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3087 ir_node *nomem = new_NoMem();
3090 new_sz = create_immediate_or_transform(sz, 0);
3092 /* ia32 stack grows in reverse direction, make an AddSP */
3093 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3094 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3095 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3101 * This function just sets the register for the Unknown node
3102 * as this is not done during register allocation because Unknown
3103 * is an "ignore" node.
3105 static ir_node *gen_Unknown(ir_node *node) {
3106 ir_mode *mode = get_irn_mode(node);
3108 if (mode_is_float(mode)) {
3110 if (USE_SSE2(env_cg))
3111 return ia32_new_Unknown_xmm(env_cg);
3113 return ia32_new_Unknown_vfp(env_cg);
3114 } else if (mode_needs_gp_reg(mode)) {
3115 return ia32_new_Unknown_gp(env_cg);
3117 assert(0 && "unsupported Unknown-Mode");
3124 * Change some phi modes
3126 static ir_node *gen_Phi(ir_node *node) {
3127 ir_node *block = be_transform_node(get_nodes_block(node));
3128 ir_graph *irg = current_ir_graph;
3129 dbg_info *dbgi = get_irn_dbg_info(node);
3130 ir_mode *mode = get_irn_mode(node);
3133 if(mode_needs_gp_reg(mode)) {
3134 /* we shouldn't have any 64bit stuff around anymore */
3135 assert(get_mode_size_bits(mode) <= 32);
3136 /* all integer operations are on 32bit registers now */
3138 } else if(mode_is_float(mode)) {
3139 if (USE_SSE2(env_cg)) {
3146 /* phi nodes allow loops, so we use the old arguments for now
3147 * and fix this later */
3148 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3149 copy_node_attr(node, phi);
3150 be_duplicate_deps(node, phi);
3152 be_set_transformed_node(node, phi);
3153 be_enqueue_preds(node);
3158 /**********************************************************************
3161 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3162 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3163 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3164 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3166 **********************************************************************/
3168 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3170 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3173 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3174 ir_node *val, ir_node *mem);
3177 * Transforms a lowered Load into a "real" one.
3179 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3180 ir_node *block = be_transform_node(get_nodes_block(node));
3181 ir_node *ptr = get_irn_n(node, 0);
3182 ir_node *new_ptr = be_transform_node(ptr);
3183 ir_node *mem = get_irn_n(node, 1);
3184 ir_node *new_mem = be_transform_node(mem);
3185 ir_graph *irg = current_ir_graph;
3186 dbg_info *dbgi = get_irn_dbg_info(node);
3187 ir_mode *mode = get_ia32_ls_mode(node);
3188 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3192 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3193 lowering we have x87 nodes, so we need to enforce simulation.
3195 if (mode_is_float(mode)) {
3197 if (fp_unit == fp_x87)
3201 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3203 set_ia32_op_type(new_op, ia32_AddrModeS);
3204 set_ia32_am_flavour(new_op, ia32_am_OB);
3205 set_ia32_am_offs_int(new_op, 0);
3206 set_ia32_am_scale(new_op, 1);
3207 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3208 if (is_ia32_am_sc_sign(node))
3209 set_ia32_am_sc_sign(new_op);
3210 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3211 if (is_ia32_use_frame(node)) {
3212 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3213 set_ia32_use_frame(new_op);
3216 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3222 * Transforms a lowered Store into a "real" one.
3224 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3225 ir_node *block = be_transform_node(get_nodes_block(node));
3226 ir_node *ptr = get_irn_n(node, 0);
3227 ir_node *new_ptr = be_transform_node(ptr);
3228 ir_node *val = get_irn_n(node, 1);
3229 ir_node *new_val = be_transform_node(val);
3230 ir_node *mem = get_irn_n(node, 2);
3231 ir_node *new_mem = be_transform_node(mem);
3232 ir_graph *irg = current_ir_graph;
3233 dbg_info *dbgi = get_irn_dbg_info(node);
3234 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3235 ir_mode *mode = get_ia32_ls_mode(node);
3238 ia32_am_flavour_t am_flav = ia32_B;
3241 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3242 lowering we have x87 nodes, so we need to enforce simulation.
3244 if (mode_is_float(mode)) {
3246 if (fp_unit == fp_x87)
3250 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3252 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3254 add_ia32_am_offs_int(new_op, am_offs);
3257 set_ia32_op_type(new_op, ia32_AddrModeD);
3258 set_ia32_am_flavour(new_op, am_flav);
3259 set_ia32_ls_mode(new_op, mode);
3260 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3261 set_ia32_use_frame(new_op);
3263 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3270 * Transforms an ia32_l_XXX into a "real" XXX node
3272 * @param env The transformation environment
3273 * @return the created ia32 XXX node
3275 #define GEN_LOWERED_OP(op) \
3276 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3277 ir_mode *mode = get_irn_mode(node); \
3278 if (mode_is_float(mode)) \
3280 return gen_binop(node, get_binop_left(node), \
3281 get_binop_right(node), new_rd_ia32_##op,0); \
3284 #define GEN_LOWERED_x87_OP(op) \
3285 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3287 FORCE_x87(env_cg); \
3288 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3289 get_binop_right(node), new_rd_ia32_##op); \
3293 #define GEN_LOWERED_UNOP(op) \
3294 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3295 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3298 #define GEN_LOWERED_SHIFT_OP(op) \
3299 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3300 return gen_shift_binop(node, get_binop_left(node), \
3301 get_binop_right(node), new_rd_ia32_##op); \
3304 #define GEN_LOWERED_LOAD(op, fp_unit) \
3305 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3306 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3309 #define GEN_LOWERED_STORE(op, fp_unit) \
3310 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3311 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3318 GEN_LOWERED_OP(IMul)
3320 GEN_LOWERED_x87_OP(vfprem)
3321 GEN_LOWERED_x87_OP(vfmul)
3322 GEN_LOWERED_x87_OP(vfsub)
3324 GEN_LOWERED_UNOP(Neg)
3326 GEN_LOWERED_LOAD(vfild, fp_x87)
3327 GEN_LOWERED_LOAD(Load, fp_none)
3328 /*GEN_LOWERED_STORE(vfist, fp_x87)
3331 GEN_LOWERED_STORE(Store, fp_none)
3333 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3334 ir_node *block = be_transform_node(get_nodes_block(node));
3335 ir_node *left = get_binop_left(node);
3336 ir_node *new_left = be_transform_node(left);
3337 ir_node *right = get_binop_right(node);
3338 ir_node *new_right = be_transform_node(right);
3339 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3340 ir_graph *irg = current_ir_graph;
3341 dbg_info *dbgi = get_irn_dbg_info(node);
3342 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
3343 &ia32_fp_cw_regs[REG_FPCW]);
3346 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3347 new_right, new_NoMem(), fpcw);
3348 clear_ia32_commutative(vfdiv);
3349 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3351 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3359 * Transforms a l_MulS into a "real" MulS node.
3361 * @param env The transformation environment
3362 * @return the created ia32 Mul node
3364 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3365 ir_node *block = be_transform_node(get_nodes_block(node));
3366 ir_node *left = get_binop_left(node);
3367 ir_node *new_left = be_transform_node(left);
3368 ir_node *right = get_binop_right(node);
3369 ir_node *new_right = be_transform_node(right);
3370 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3371 ir_graph *irg = current_ir_graph;
3372 dbg_info *dbgi = get_irn_dbg_info(node);
3375 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3376 /* and then skip the result Proj, because all needed Projs are already there. */
3377 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3378 new_right, new_NoMem());
3379 clear_ia32_commutative(muls);
3380 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3382 /* check if EAX and EDX proj exist, add missing one */
3383 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3384 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3385 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3387 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3392 GEN_LOWERED_SHIFT_OP(Shl)
3393 GEN_LOWERED_SHIFT_OP(Shr)
3394 GEN_LOWERED_SHIFT_OP(Sar)
3397 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3398 * op1 - target to be shifted
3399 * op2 - contains bits to be shifted into target
3401 * Only op3 can be an immediate.
3403 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3404 ir_node *op2, ir_node *count)
3406 ir_node *block = be_transform_node(get_nodes_block(node));
3407 ir_node *new_op1 = be_transform_node(op1);
3408 ir_node *new_op2 = be_transform_node(op2);
3409 ir_node *new_count = be_transform_node(count);
3410 ir_node *new_op = NULL;
3411 ir_graph *irg = current_ir_graph;
3412 dbg_info *dbgi = get_irn_dbg_info(node);
3413 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3414 ir_node *nomem = new_NoMem();
3418 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3420 /* Check if immediate optimization is on and */
3421 /* if it's an operation with immediate. */
3422 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3424 /* Limit imm_op within range imm8 */
3426 tv = get_ia32_Immop_tarval(imm_op);
3429 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3430 set_ia32_Immop_tarval(imm_op, tv);
3437 /* integer operations */
3439 /* This is ShiftD with const */
3440 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3442 if (is_ia32_l_ShlD(node))
3443 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3444 new_op1, new_op2, noreg, nomem);
3446 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3447 new_op1, new_op2, noreg, nomem);
3448 copy_ia32_Immop_attr(new_op, imm_op);
3451 /* This is a normal ShiftD */
3452 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3453 if (is_ia32_l_ShlD(node))
3454 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3455 new_op1, new_op2, new_count, nomem);
3457 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3458 new_op1, new_op2, new_count, nomem);
3461 /* set AM support */
3462 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3464 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3466 set_ia32_emit_cl(new_op);
3471 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3472 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3473 get_irn_n(node, 1), get_irn_n(node, 2));
3476 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3477 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3478 get_irn_n(node, 1), get_irn_n(node, 2));
3482 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3484 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3485 ir_node *block = be_transform_node(get_nodes_block(node));
3486 ir_node *val = get_irn_n(node, 1);
3487 ir_node *new_val = be_transform_node(val);
3488 ia32_code_gen_t *cg = env_cg;
3489 ir_node *res = NULL;
3490 ir_graph *irg = current_ir_graph;
3492 ir_node *noreg, *new_ptr, *new_mem;
3499 mem = get_irn_n(node, 2);
3500 new_mem = be_transform_node(mem);
3501 ptr = get_irn_n(node, 0);
3502 new_ptr = be_transform_node(ptr);
3503 noreg = ia32_new_NoReg_gp(cg);
3504 dbgi = get_irn_dbg_info(node);
3506 /* Store x87 -> MEM */
3507 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3508 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3509 set_ia32_use_frame(res);
3510 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3511 set_ia32_am_flavour(res, ia32_B);
3512 set_ia32_op_type(res, ia32_AddrModeD);
3514 /* Load MEM -> SSE */
3515 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3516 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3517 set_ia32_use_frame(res);
3518 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3519 set_ia32_am_flavour(res, ia32_B);
3520 set_ia32_op_type(res, ia32_AddrModeS);
3521 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3527 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3529 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3530 ir_node *block = be_transform_node(get_nodes_block(node));
3531 ir_node *val = get_irn_n(node, 1);
3532 ir_node *new_val = be_transform_node(val);
3533 ia32_code_gen_t *cg = env_cg;
3534 ir_graph *irg = current_ir_graph;
3535 ir_node *res = NULL;
3536 ir_entity *fent = get_ia32_frame_ent(node);
3537 ir_mode *lsmode = get_ia32_ls_mode(node);
3539 ir_node *noreg, *new_ptr, *new_mem;
3543 if (! USE_SSE2(cg)) {
3544 /* SSE unit is not used -> skip this node. */
3548 ptr = get_irn_n(node, 0);
3549 new_ptr = be_transform_node(ptr);
3550 mem = get_irn_n(node, 2);
3551 new_mem = be_transform_node(mem);
3552 noreg = ia32_new_NoReg_gp(cg);
3553 dbgi = get_irn_dbg_info(node);
3555 /* Store SSE -> MEM */
3556 if (is_ia32_xLoad(skip_Proj(new_val))) {
3557 ir_node *ld = skip_Proj(new_val);
3559 /* we can vfld the value directly into the fpu */
3560 fent = get_ia32_frame_ent(ld);
3561 ptr = get_irn_n(ld, 0);
3562 offs = get_ia32_am_offs_int(ld);
3564 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3565 set_ia32_frame_ent(res, fent);
3566 set_ia32_use_frame(res);
3567 set_ia32_ls_mode(res, lsmode);
3568 set_ia32_am_flavour(res, ia32_B);
3569 set_ia32_op_type(res, ia32_AddrModeD);
3573 /* Load MEM -> x87 */
3574 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3575 set_ia32_frame_ent(res, fent);
3576 set_ia32_use_frame(res);
3577 add_ia32_am_offs_int(res, offs);
3578 set_ia32_am_flavour(res, ia32_B);
3579 set_ia32_op_type(res, ia32_AddrModeS);
3580 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3585 /*********************************************************
3588 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3589 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3590 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3591 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3593 *********************************************************/
3596 * the BAD transformer.
3598 static ir_node *bad_transform(ir_node *node) {
3599 panic("No transform function for %+F available.\n", node);
3604 * Transform the Projs of an AddSP.
3606 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3607 ir_node *block = be_transform_node(get_nodes_block(node));
3608 ir_node *pred = get_Proj_pred(node);
3609 ir_node *new_pred = be_transform_node(pred);
3610 ir_graph *irg = current_ir_graph;
3611 dbg_info *dbgi = get_irn_dbg_info(node);
3612 long proj = get_Proj_proj(node);
3614 if (proj == pn_be_AddSP_res) {
3615 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3616 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3618 } else if (proj == pn_be_AddSP_M) {
3619 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3623 return new_rd_Unknown(irg, get_irn_mode(node));
3627 * Transform the Projs of a SubSP.
3629 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3630 ir_node *block = be_transform_node(get_nodes_block(node));
3631 ir_node *pred = get_Proj_pred(node);
3632 ir_node *new_pred = be_transform_node(pred);
3633 ir_graph *irg = current_ir_graph;
3634 dbg_info *dbgi = get_irn_dbg_info(node);
3635 long proj = get_Proj_proj(node);
3637 if (proj == pn_be_SubSP_res) {
3638 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3639 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3641 } else if (proj == pn_be_SubSP_M) {
3642 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3646 return new_rd_Unknown(irg, get_irn_mode(node));
3650 * Transform and renumber the Projs from a Load.
3652 static ir_node *gen_Proj_Load(ir_node *node) {
3653 ir_node *block = be_transform_node(get_nodes_block(node));
3654 ir_node *pred = get_Proj_pred(node);
3655 ir_node *new_pred = be_transform_node(pred);
3656 ir_graph *irg = current_ir_graph;
3657 dbg_info *dbgi = get_irn_dbg_info(node);
3658 long proj = get_Proj_proj(node);
3660 /* renumber the proj */
3661 if (is_ia32_Load(new_pred)) {
3662 if (proj == pn_Load_res) {
3663 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3664 } else if (proj == pn_Load_M) {
3665 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3667 } else if (is_ia32_xLoad(new_pred)) {
3668 if (proj == pn_Load_res) {
3669 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3670 } else if (proj == pn_Load_M) {
3671 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3673 } else if (is_ia32_vfld(new_pred)) {
3674 if (proj == pn_Load_res) {
3675 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3676 } else if (proj == pn_Load_M) {
3677 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3682 return new_rd_Unknown(irg, get_irn_mode(node));
3686 * Transform and renumber the Projs from a DivMod like instruction.
3688 static ir_node *gen_Proj_DivMod(ir_node *node) {
3689 ir_node *block = be_transform_node(get_nodes_block(node));
3690 ir_node *pred = get_Proj_pred(node);
3691 ir_node *new_pred = be_transform_node(pred);
3692 ir_graph *irg = current_ir_graph;
3693 dbg_info *dbgi = get_irn_dbg_info(node);
3694 ir_mode *mode = get_irn_mode(node);
3695 long proj = get_Proj_proj(node);
3697 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3699 switch (get_irn_opcode(pred)) {
3703 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3705 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3713 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3715 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3723 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3724 case pn_DivMod_res_div:
3725 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3726 case pn_DivMod_res_mod:
3727 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3737 return new_rd_Unknown(irg, mode);
3741 * Transform and renumber the Projs from a CopyB.
3743 static ir_node *gen_Proj_CopyB(ir_node *node) {
3744 ir_node *block = be_transform_node(get_nodes_block(node));
3745 ir_node *pred = get_Proj_pred(node);
3746 ir_node *new_pred = be_transform_node(pred);
3747 ir_graph *irg = current_ir_graph;
3748 dbg_info *dbgi = get_irn_dbg_info(node);
3749 ir_mode *mode = get_irn_mode(node);
3750 long proj = get_Proj_proj(node);
3753 case pn_CopyB_M_regular:
3754 if (is_ia32_CopyB_i(new_pred)) {
3755 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3756 } else if (is_ia32_CopyB(new_pred)) {
3757 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3765 return new_rd_Unknown(irg, mode);
3769 * Transform and renumber the Projs from a vfdiv.
3771 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3772 ir_node *block = be_transform_node(get_nodes_block(node));
3773 ir_node *pred = get_Proj_pred(node);
3774 ir_node *new_pred = be_transform_node(pred);
3775 ir_graph *irg = current_ir_graph;
3776 dbg_info *dbgi = get_irn_dbg_info(node);
3777 ir_mode *mode = get_irn_mode(node);
3778 long proj = get_Proj_proj(node);
3781 case pn_ia32_l_vfdiv_M:
3782 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3783 case pn_ia32_l_vfdiv_res:
3784 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3789 return new_rd_Unknown(irg, mode);
3793 * Transform and renumber the Projs from a Quot.
3795 static ir_node *gen_Proj_Quot(ir_node *node) {
3796 ir_node *block = be_transform_node(get_nodes_block(node));
3797 ir_node *pred = get_Proj_pred(node);
3798 ir_node *new_pred = be_transform_node(pred);
3799 ir_graph *irg = current_ir_graph;
3800 dbg_info *dbgi = get_irn_dbg_info(node);
3801 ir_mode *mode = get_irn_mode(node);
3802 long proj = get_Proj_proj(node);
3806 if (is_ia32_xDiv(new_pred)) {
3807 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3808 } else if (is_ia32_vfdiv(new_pred)) {
3809 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3813 if (is_ia32_xDiv(new_pred)) {
3814 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3815 } else if (is_ia32_vfdiv(new_pred)) {
3816 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3824 return new_rd_Unknown(irg, mode);
3828 * Transform the Thread Local Storage Proj.
3830 static ir_node *gen_Proj_tls(ir_node *node) {
3831 ir_node *block = be_transform_node(get_nodes_block(node));
3832 ir_graph *irg = current_ir_graph;
3833 dbg_info *dbgi = NULL;
3834 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3840 * Transform the Projs from a be_Call.
3842 static ir_node *gen_Proj_be_Call(ir_node *node) {
3843 ir_node *block = be_transform_node(get_nodes_block(node));
3844 ir_node *call = get_Proj_pred(node);
3845 ir_node *new_call = be_transform_node(call);
3846 ir_graph *irg = current_ir_graph;
3847 dbg_info *dbgi = get_irn_dbg_info(node);
3848 long proj = get_Proj_proj(node);
3849 ir_mode *mode = get_irn_mode(node);
3851 const arch_register_class_t *cls;
3853 /* The following is kinda tricky: If we're using SSE, then we have to
3854 * move the result value of the call in floating point registers to an
3855 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3856 * after the call, we have to make sure to correctly make the
3857 * MemProj and the result Proj use these 2 nodes
3859 if (proj == pn_be_Call_M_regular) {
3860 // get new node for result, are we doing the sse load/store hack?
3861 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3862 ir_node *call_res_new;
3863 ir_node *call_res_pred = NULL;
3865 if (call_res != NULL) {
3866 call_res_new = be_transform_node(call_res);
3867 call_res_pred = get_Proj_pred(call_res_new);
3870 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3871 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3873 assert(is_ia32_xLoad(call_res_pred));
3874 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3877 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3879 ir_node *frame = get_irg_frame(irg);
3880 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3882 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3884 const arch_register_class_t *cls;
3886 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3887 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3889 /* store st(0) onto stack */
3890 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3892 set_ia32_ls_mode(fstp, mode);
3893 set_ia32_op_type(fstp, ia32_AddrModeD);
3894 set_ia32_use_frame(fstp);
3895 set_ia32_am_flavour(fstp, ia32_am_B);
3897 /* load into SSE register */
3898 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3899 set_ia32_ls_mode(sse_load, mode);
3900 set_ia32_op_type(sse_load, ia32_AddrModeS);
3901 set_ia32_use_frame(sse_load);
3902 set_ia32_am_flavour(sse_load, ia32_am_B);
3904 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3906 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3908 /* get a Proj representing a caller save register */
3909 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3910 assert(is_Proj(p) && "Proj expected.");
3912 /* user of the the proj is the Keep */
3913 p = get_edge_src_irn(get_irn_out_edge_first(p));
3914 assert(be_is_Keep(p) && "Keep expected.");
3916 /* keep the result */
3917 cls = arch_get_irn_reg_class(env_cg->arch_env, sse_load, -1);
3918 keepin[0] = sse_load;
3919 be_new_Keep(cls, irg, block, 1, keepin);
3924 /* transform call modes */
3925 if (mode_is_data(mode)) {
3926 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
3930 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3934 * Transform the Projs from a Cmp.
3936 static ir_node *gen_Proj_Cmp(ir_node *node)
3938 /* normally Cmps are processed when looking at Cond nodes, but this case
3939 * can happen in complicated Psi conditions */
3941 ir_node *cmp = get_Proj_pred(node);
3942 long pnc = get_Proj_proj(node);
3943 ir_node *cmp_left = get_Cmp_left(cmp);
3944 ir_node *cmp_right = get_Cmp_right(cmp);
3945 ir_mode *cmp_mode = get_irn_mode(cmp_left);
3946 dbg_info *dbgi = get_irn_dbg_info(cmp);
3947 ir_node *block = be_transform_node(get_nodes_block(node));
3950 assert(!mode_is_float(cmp_mode));
3952 if(!mode_is_signed(cmp_mode)) {
3953 pnc |= ia32_pn_Cmp_Unsigned;
3956 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
3957 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
3963 * Transform and potentially renumber Proj nodes.
3965 static ir_node *gen_Proj(ir_node *node) {
3966 ir_graph *irg = current_ir_graph;
3967 dbg_info *dbgi = get_irn_dbg_info(node);
3968 ir_node *pred = get_Proj_pred(node);
3969 long proj = get_Proj_proj(node);
3971 if (is_Store(pred) || be_is_FrameStore(pred)) {
3972 if (proj == pn_Store_M) {
3973 return be_transform_node(pred);
3976 return new_r_Bad(irg);
3978 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
3979 return gen_Proj_Load(node);
3980 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3981 return gen_Proj_DivMod(node);
3982 } else if (is_CopyB(pred)) {
3983 return gen_Proj_CopyB(node);
3984 } else if (is_Quot(pred)) {
3985 return gen_Proj_Quot(node);
3986 } else if (is_ia32_l_vfdiv(pred)) {
3987 return gen_Proj_l_vfdiv(node);
3988 } else if (be_is_SubSP(pred)) {
3989 return gen_Proj_be_SubSP(node);
3990 } else if (be_is_AddSP(pred)) {
3991 return gen_Proj_be_AddSP(node);
3992 } else if (be_is_Call(pred)) {
3993 return gen_Proj_be_Call(node);
3994 } else if (is_Cmp(pred)) {
3995 return gen_Proj_Cmp(node);
3996 } else if (get_irn_op(pred) == op_Start) {
3997 if (proj == pn_Start_X_initial_exec) {
3998 ir_node *block = get_nodes_block(pred);
4001 /* we exchange the ProjX with a jump */
4002 block = be_transform_node(block);
4003 jump = new_rd_Jmp(dbgi, irg, block);
4006 if (node == be_get_old_anchor(anchor_tls)) {
4007 return gen_Proj_tls(node);
4010 ir_node *new_pred = be_transform_node(pred);
4011 ir_node *block = be_transform_node(get_nodes_block(node));
4012 ir_mode *mode = get_irn_mode(node);
4013 if (mode_needs_gp_reg(mode)) {
4014 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4015 get_Proj_proj(node));
4016 #ifdef DEBUG_libfirm
4017 new_proj->node_nr = node->node_nr;
4023 return be_duplicate_node(node);
4027 * Enters all transform functions into the generic pointer
4029 static void register_transformers(void)
4033 /* first clear the generic function pointer for all ops */
4034 clear_irp_opcodes_generic_func();
4036 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4037 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4073 /* transform ops from intrinsic lowering */
4093 /* GEN(ia32_l_vfist); TODO */
4095 GEN(ia32_l_X87toSSE);
4096 GEN(ia32_l_SSEtoX87);
4101 /* we should never see these nodes */
4116 /* handle generic backend nodes */
4127 /* set the register for all Unknown nodes */
4130 op_Mulh = get_op_Mulh();
4139 * Pre-transform all unknown and noreg nodes.
4141 static void ia32_pretransform_node(void *arch_cg) {
4142 ia32_code_gen_t *cg = arch_cg;
4144 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4145 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4146 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4147 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4148 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4149 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4152 /* do the transformation */
4153 void ia32_transform_graph(ia32_code_gen_t *cg) {
4154 register_transformers();
4156 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4159 void ia32_init_transform(void)
4161 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");