2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
76 #define TP_SFP_SIGN "ia32_sfp_sign"
77 #define TP_DFP_SIGN "ia32_dfp_sign"
78 #define TP_SFP_ABS "ia32_sfp_abs"
79 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
82 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
83 #define ENT_SFP_ABS "IA32_SFP_ABS"
84 #define ENT_DFP_ABS "IA32_DFP_ABS"
86 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
87 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
89 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
91 /** hold the current code generator during transformation */
92 static ia32_code_gen_t *env_cg = NULL;
93 static ir_node *initial_fpcw = NULL;
94 static heights_t *heights = NULL;
96 extern ir_op *get_op_Mulh(void);
98 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem);
102 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *op1, ir_node *op2);
105 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
106 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
109 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
110 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
112 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
113 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
114 ir_node *op2, ir_node *mem, ir_node *fpcw);
116 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
117 ir_node *block, ir_node *op);
119 /****************************************************************************************************
121 * | | | | / _| | | (_)
122 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
123 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
124 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
125 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
127 ****************************************************************************************************/
129 static ir_node *try_create_Immediate(ir_node *node,
130 char immediate_constraint_type);
132 static ir_node *create_immediate_or_transform(ir_node *node,
133 char immediate_constraint_type);
135 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
136 dbg_info *dbgi, ir_node *new_block,
140 * Return true if a mode can be stored in the GP register set
142 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
143 if(mode == mode_fpcw)
145 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
149 * creates a unique ident by adding a number to a tag
151 * @param tag the tag string, must contain a %d if a number
154 static ident *unique_id(const char *tag)
156 static unsigned id = 0;
159 snprintf(str, sizeof(str), tag, ++id);
160 return new_id_from_str(str);
164 * Get a primitive type for a mode.
166 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
168 pmap_entry *e = pmap_find(types, mode);
173 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
174 res = new_type_primitive(new_id_from_str(buf), mode);
175 set_type_alignment_bytes(res, 16);
176 pmap_insert(types, mode, res);
184 * Get an atomic entity that is initialized with a tarval
186 static ir_entity *ia32_get_entity_for_tv(ia32_isa_t *isa, ir_node *cnst)
188 tarval *tv = get_Const_tarval(cnst);
189 pmap_entry *e = pmap_find(isa->tv_ent, tv);
194 ir_mode *mode = get_irn_mode(cnst);
195 ir_type *tp = get_Const_type(cnst);
196 if (tp == firm_unknown_type)
197 tp = get_prim_type(isa->types, mode);
199 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
201 set_entity_ld_ident(res, get_entity_ident(res));
202 set_entity_visibility(res, visibility_local);
203 set_entity_variability(res, variability_constant);
204 set_entity_allocation(res, allocation_static);
206 /* we create a new entity here: It's initialization must resist on the
208 rem = current_ir_graph;
209 current_ir_graph = get_const_code_irg();
210 set_atomic_ent_value(res, new_Const_type(tv, tp));
211 current_ir_graph = rem;
213 pmap_insert(isa->tv_ent, tv, res);
221 static int is_Const_0(ir_node *node) {
225 return classify_Const(node) == CNST_NULL;
228 static int is_Const_1(ir_node *node) {
232 return classify_Const(node) == CNST_ONE;
235 static int is_Const_Minus_1(ir_node *node) {
241 mode = get_irn_mode(node);
242 if(!mode_is_signed(mode))
245 tv = get_Const_tarval(node);
248 return classify_tarval(tv) == CNST_ONE;
252 * Transforms a Const.
254 static ir_node *gen_Const(ir_node *node) {
255 ir_graph *irg = current_ir_graph;
256 ir_node *old_block = get_nodes_block(node);
257 ir_node *block = be_transform_node(old_block);
258 dbg_info *dbgi = get_irn_dbg_info(node);
259 ir_mode *mode = get_irn_mode(node);
261 if (mode_is_float(mode)) {
263 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
264 ir_node *nomem = new_NoMem();
267 cnst_classify_t clss = classify_Const(node);
269 if (USE_SSE2(env_cg)) {
270 if (clss == CNST_NULL) {
271 load = new_rd_ia32_xZero(dbgi, irg, block);
272 set_ia32_ls_mode(load, mode);
275 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
277 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
279 set_ia32_op_type(load, ia32_AddrModeS);
280 set_ia32_am_sc(load, floatent);
281 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
282 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
285 if (clss == CNST_NULL) {
286 load = new_rd_ia32_vfldz(dbgi, irg, block);
288 } else if (clss == CNST_ONE) {
289 load = new_rd_ia32_vfld1(dbgi, irg, block);
292 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
294 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
295 set_ia32_op_type(load, ia32_AddrModeS);
296 set_ia32_am_sc(load, floatent);
297 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
298 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
300 set_ia32_ls_mode(load, mode);
303 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
305 /* Const Nodes before the initial IncSP are a bad idea, because
306 * they could be spilled and we have no SP ready at that point yet.
307 * So add a dependency to the initial frame pointer calculation to
308 * avoid that situation.
310 if (get_irg_start_block(irg) == block) {
311 add_irn_dep(load, get_irg_frame(irg));
314 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
318 tarval *tv = get_Const_tarval(node);
321 tv = tarval_convert_to(tv, mode_Iu);
323 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
325 panic("couldn't convert constant tarval (%+F)", node);
327 val = get_tarval_long(tv);
329 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
330 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
333 if (get_irg_start_block(irg) == block) {
334 add_irn_dep(cnst, get_irg_frame(irg));
342 * Transforms a SymConst.
344 static ir_node *gen_SymConst(ir_node *node) {
345 ir_graph *irg = current_ir_graph;
346 ir_node *old_block = get_nodes_block(node);
347 ir_node *block = be_transform_node(old_block);
348 dbg_info *dbgi = get_irn_dbg_info(node);
349 ir_mode *mode = get_irn_mode(node);
352 if (mode_is_float(mode)) {
353 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
354 ir_node *nomem = new_NoMem();
356 if (USE_SSE2(env_cg))
357 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
359 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
360 set_ia32_am_sc(cnst, get_SymConst_entity(node));
364 if(get_SymConst_kind(node) != symconst_addr_ent) {
365 panic("backend only support symconst_addr_ent (at %+F)", node);
367 entity = get_SymConst_entity(node);
368 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
371 /* Const Nodes before the initial IncSP are a bad idea, because
372 * they could be spilled and we have no SP ready at that point yet
374 if (get_irg_start_block(irg) == block) {
375 add_irn_dep(cnst, get_irg_frame(irg));
378 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
383 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
384 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
385 static const struct {
387 const char *ent_name;
388 const char *cnst_str;
389 } names [ia32_known_const_max] = {
390 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
391 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
392 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
393 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
395 static ir_entity *ent_cache[ia32_known_const_max];
397 const char *tp_name, *ent_name, *cnst_str;
405 ent_name = names[kct].ent_name;
406 if (! ent_cache[kct]) {
407 tp_name = names[kct].tp_name;
408 cnst_str = names[kct].cnst_str;
410 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
412 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
413 tp = new_type_primitive(new_id_from_str(tp_name), mode);
414 /* these constants are loaded as part of an instruction, so they must be aligned
416 set_type_alignment_bytes(tp, 16);
417 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
419 set_entity_ld_ident(ent, get_entity_ident(ent));
420 set_entity_visibility(ent, visibility_local);
421 set_entity_variability(ent, variability_constant);
422 set_entity_allocation(ent, allocation_static);
424 /* we create a new entity here: It's initialization must resist on the
426 rem = current_ir_graph;
427 current_ir_graph = get_const_code_irg();
428 cnst = new_Const(mode, tv);
429 current_ir_graph = rem;
431 set_atomic_ent_value(ent, cnst);
433 /* cache the entry */
434 ent_cache[kct] = ent;
437 return ent_cache[kct];
442 * Prints the old node name on cg obst and returns a pointer to it.
444 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
445 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
447 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
448 obstack_1grow(isa->name_obst, 0);
449 return obstack_finish(isa->name_obst);
453 static int use_source_address_mode(ir_node *block, ir_node *node,
462 load = get_Proj_pred(node);
463 pn = get_Proj_proj(node);
464 if(!is_Load(load) || pn != pn_Load_res)
466 if(get_nodes_block(load) != block)
468 /* we only use address mode if we're the only user of the load */
469 if(get_irn_n_edges(node) > 1)
472 mode = get_irn_mode(node);
473 if(!mode_needs_gp_reg(mode))
475 if(get_mode_size_bits(mode) != 32)
478 /* don't do AM if other node inputs depend on the load (via mem-proj) */
479 if(other != NULL && get_nodes_block(other) == block
480 && heights_reachable_in_block(heights, other, load))
486 typedef struct ia32_address_mode_t ia32_address_mode_t;
487 struct ia32_address_mode_t {
491 ia32_op_type_t op_type;
498 static void build_address(ia32_address_mode_t *am, ir_node *node)
500 ia32_address_t *addr = &am->addr;
501 ir_node *load = get_Proj_pred(node);
502 ir_node *ptr = get_Load_ptr(load);
503 ir_node *mem = get_Load_mem(load);
504 ir_node *new_mem = be_transform_node(mem);
508 am->ls_mode = get_Load_mode(load);
509 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
511 /* construct load address */
512 ia32_create_address_mode(addr, ptr, 0);
517 base = ia32_new_NoReg_gp(env_cg);
519 base = be_transform_node(base);
523 index = ia32_new_NoReg_gp(env_cg);
525 index = be_transform_node(index);
533 static void set_address(ir_node *node, ia32_address_t *addr)
535 set_ia32_am_scale(node, addr->scale);
536 set_ia32_am_sc(node, addr->symconst_ent);
537 set_ia32_am_offs_int(node, addr->offset);
538 if(addr->symconst_sign)
539 set_ia32_am_sc_sign(node);
541 set_ia32_use_frame(node);
542 set_ia32_frame_ent(node, addr->frame_entity);
545 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
547 set_address(node, &am->addr);
549 set_ia32_op_type(node, am->op_type);
550 set_ia32_ls_mode(node, am->ls_mode);
552 set_ia32_commutative(node);
555 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
556 ir_node *op1, ir_node *op2, int commutative,
557 int use_am_and_immediates, int use_am)
559 ia32_address_t *addr = &am->addr;
560 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
564 memset(am, 0, sizeof(am[0]));
566 new_op2 = try_create_Immediate(op2, 0);
567 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
568 build_address(am, op2);
569 new_op1 = be_transform_node(op1);
571 am->op_type = ia32_AddrModeS;
572 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
573 use_am && use_source_address_mode(block, op1, op2)) {
574 build_address(am, op1);
575 if(new_op2 != NULL) {
578 new_op1 = be_transform_node(op2);
582 am->op_type = ia32_AddrModeS;
584 new_op1 = be_transform_node(op1);
586 new_op2 = be_transform_node(op2);
587 am->op_type = ia32_Normal;
589 if(addr->base == NULL)
590 addr->base = noreg_gp;
591 if(addr->index == NULL)
592 addr->index = noreg_gp;
593 if(addr->mem == NULL)
594 addr->mem = new_NoMem();
596 am->new_op1 = new_op1;
597 am->new_op2 = new_op2;
598 am->commutative = commutative;
601 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
603 ir_graph *irg = current_ir_graph;
607 if(am->mem_proj == NULL)
610 /* we have to create a mode_T so the old MemProj can attach to us */
611 mode = get_irn_mode(node);
612 load = get_Proj_pred(am->mem_proj);
614 mark_irn_visited(load);
615 be_set_transformed_node(load, node);
618 set_irn_mode(node, mode_T);
619 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, 0);
626 * Construct a standard binary operation, set AM and immediate if required.
628 * @param op1 The first operand
629 * @param op2 The second operand
630 * @param func The node constructor function
631 * @return The constructed ia32 node.
633 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
634 construct_binop_func *func, int commutative)
636 ir_node *src_block = get_nodes_block(node);
637 ir_node *block = be_transform_node(src_block);
638 ir_graph *irg = current_ir_graph;
639 dbg_info *dbgi = get_irn_dbg_info(node);
641 ia32_address_mode_t am;
642 ia32_address_t *addr = &am.addr;
644 match_arguments(&am, src_block, op1, op2, commutative, 0, 1);
646 new_node = func(dbgi, irg, block, addr->base, addr->index, am.new_op1,
647 am.new_op2, addr->mem);
648 set_am_attributes(new_node, &am);
649 /* we can't use source address mode anymore when using immediates */
650 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
651 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
652 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
654 new_node = fix_mem_proj(new_node, &am);
660 * Construct a standard binary operation, set AM and immediate if required.
662 * @param op1 The first operand
663 * @param op2 The second operand
664 * @param func The node constructor function
665 * @return The constructed ia32 node.
667 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
668 construct_binop_func *func)
670 ir_node *block = be_transform_node(get_nodes_block(node));
671 ir_node *new_op1 = be_transform_node(op1);
672 ir_node *new_op2 = be_transform_node(op2);
673 ir_node *new_node = NULL;
674 dbg_info *dbgi = get_irn_dbg_info(node);
675 ir_graph *irg = current_ir_graph;
676 ir_mode *mode = get_irn_mode(node);
677 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
678 ir_node *nomem = new_NoMem();
680 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
682 if (is_op_commutative(get_irn_op(node))) {
683 set_ia32_commutative(new_node);
685 set_ia32_ls_mode(new_node, mode);
687 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
692 static ir_node *get_fpcw(void)
695 if(initial_fpcw != NULL)
698 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
699 &ia32_fp_cw_regs[REG_FPCW]);
700 initial_fpcw = be_transform_node(fpcw);
706 * Construct a standard binary operation, set AM and immediate if required.
708 * @param op1 The first operand
709 * @param op2 The second operand
710 * @param func The node constructor function
711 * @return The constructed ia32 node.
713 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
714 construct_binop_float_func *func)
716 ir_node *block = be_transform_node(get_nodes_block(node));
717 ir_node *new_op1 = be_transform_node(op1);
718 ir_node *new_op2 = be_transform_node(op2);
719 ir_node *new_node = NULL;
720 dbg_info *dbgi = get_irn_dbg_info(node);
721 ir_graph *irg = current_ir_graph;
722 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
723 ir_node *nomem = new_NoMem();
725 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
727 if (is_op_commutative(get_irn_op(node))) {
728 set_ia32_commutative(new_node);
731 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
737 * Construct a shift/rotate binary operation, sets AM and immediate if required.
739 * @param op1 The first operand
740 * @param op2 The second operand
741 * @param func The node constructor function
742 * @return The constructed ia32 node.
744 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
745 construct_shift_func *func)
747 dbg_info *dbgi = get_irn_dbg_info(node);
748 ir_graph *irg = current_ir_graph;
749 ir_node *block = get_nodes_block(node);
750 ir_node *new_block = be_transform_node(block);
751 ir_node *new_op1 = be_transform_node(op1);
752 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
755 assert(! mode_is_float(get_irn_mode(node))
756 && "Shift/Rotate with float not supported");
758 res = func(dbgi, irg, new_block, new_op1, new_op2);
759 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
761 /* lowered shift instruction may have a dependency operand, handle it here */
762 if (get_irn_arity(node) == 3) {
763 /* we have a dependency */
764 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
765 add_irn_dep(res, new_dep);
773 * Construct a standard unary operation, set AM and immediate if required.
775 * @param op The operand
776 * @param func The node constructor function
777 * @return The constructed ia32 node.
779 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
781 ir_node *block = be_transform_node(get_nodes_block(node));
782 ir_node *new_op = be_transform_node(op);
783 ir_node *new_node = NULL;
784 ir_graph *irg = current_ir_graph;
785 dbg_info *dbgi = get_irn_dbg_info(node);
787 new_node = func(dbgi, irg, block, new_op);
789 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
794 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
795 ia32_address_t *addr)
797 ir_graph *irg = current_ir_graph;
798 ir_node *base = addr->base;
799 ir_node *index = addr->index;
803 base = ia32_new_NoReg_gp(env_cg);
805 base = be_transform_node(base);
809 index = ia32_new_NoReg_gp(env_cg);
811 index = be_transform_node(index);
814 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
815 set_address(res, addr);
820 static int am_has_immediates(const ia32_address_t *addr)
822 return addr->offset != 0 || addr->symconst_ent != NULL
823 || addr->frame_entity || addr->use_frame;
827 * Creates an ia32 Add.
829 * @return the created ia32 Add node
831 static ir_node *gen_Add(ir_node *node) {
832 ir_node *block = be_transform_node(get_nodes_block(node));
833 ir_node *op1 = get_Add_left(node);
834 ir_node *op2 = get_Add_right(node);
837 ir_graph *irg = current_ir_graph;
838 dbg_info *dbgi = get_irn_dbg_info(node);
839 ir_mode *mode = get_irn_mode(node);
840 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
841 ir_node *src_block = get_nodes_block(node);
842 ir_node *add_immediate_op;
844 ia32_address_mode_t am;
846 if (mode_is_float(mode)) {
847 if (USE_SSE2(env_cg))
848 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
850 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
855 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
856 * 1. Add with immediate -> Lea
857 * 2. Add with possible source address mode -> Add
858 * 3. Otherwise -> Lea
860 memset(&addr, 0, sizeof(addr));
861 ia32_create_address_mode(&addr, node, 1);
862 add_immediate_op = NULL;
864 if(addr.base == NULL && addr.index == NULL) {
865 new_op = new_rd_ia32_Const(dbgi, irg, block, addr.symconst_ent,
866 addr.symconst_sign, addr.offset);
867 add_irn_dep(new_op, get_irg_frame(irg));
868 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
871 /* add with immediate? */
872 if(addr.index == NULL) {
873 add_immediate_op = addr.base;
874 } else if(addr.base == NULL && addr.scale == 0) {
875 add_immediate_op = addr.index;
878 if(add_immediate_op != NULL) {
879 if(!am_has_immediates(&addr)) {
881 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
884 return be_transform_node(add_immediate_op);
887 new_op = create_lea_from_address(dbgi, block, &addr);
888 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
892 /* test if we can use source address mode */
893 memset(&am, 0, sizeof(am));
895 if(use_source_address_mode(src_block, op2, op1)) {
896 build_address(&am, op2);
897 new_op1 = be_transform_node(op1);
898 } else if(use_source_address_mode(src_block, op1, op2)) {
899 build_address(&am, op1);
900 new_op1 = be_transform_node(op2);
902 /* construct an Add with source address mode */
903 if(new_op1 != NULL) {
904 ia32_address_t *am_addr = &am.addr;
905 new_op = new_rd_ia32_Add(dbgi, irg, block, am_addr->base,
906 am_addr->index, new_op1, noreg, am_addr->mem);
907 set_address(new_op, am_addr);
908 set_ia32_op_type(new_op, ia32_AddrModeS);
909 set_ia32_ls_mode(new_op, am.ls_mode);
910 set_ia32_commutative(new_op);
911 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
913 new_op = fix_mem_proj(new_op, &am);
918 /* otherwise construct a lea */
919 new_op = create_lea_from_address(dbgi, block, &addr);
920 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
925 * Creates an ia32 Mul.
927 * @return the created ia32 Mul node
929 static ir_node *gen_Mul(ir_node *node) {
930 ir_node *op1 = get_Mul_left(node);
931 ir_node *op2 = get_Mul_right(node);
932 ir_mode *mode = get_irn_mode(node);
934 if (mode_is_float(mode)) {
935 if (USE_SSE2(env_cg))
936 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
938 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
942 for the lower 32bit of the result it doesn't matter whether we use
943 signed or unsigned multiplication so we use IMul as it has fewer
946 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
950 * Creates an ia32 Mulh.
951 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
952 * this result while Mul returns the lower 32 bit.
954 * @return the created ia32 Mulh node
956 static ir_node *gen_Mulh(ir_node *node) {
957 ir_node *block = be_transform_node(get_nodes_block(node));
958 ir_node *op1 = get_irn_n(node, 0);
959 ir_node *new_op1 = be_transform_node(op1);
960 ir_node *op2 = get_irn_n(node, 1);
961 ir_node *new_op2 = be_transform_node(op2);
962 ir_graph *irg = current_ir_graph;
963 dbg_info *dbgi = get_irn_dbg_info(node);
964 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
965 ir_mode *mode = get_irn_mode(node);
966 ir_node *proj_EDX, *res;
968 assert(!mode_is_float(mode) && "Mulh with float not supported");
969 if (mode_is_signed(mode)) {
970 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
971 new_op2, new_NoMem());
973 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
977 set_ia32_commutative(res);
979 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
987 * Creates an ia32 And.
989 * @return The created ia32 And node
991 static ir_node *gen_And(ir_node *node) {
992 ir_node *op1 = get_And_left(node);
993 ir_node *op2 = get_And_right(node);
994 assert(! mode_is_float(get_irn_mode(node)));
996 /* is it a zero extension? */
998 tarval *tv = get_Const_tarval(op2);
999 long v = get_tarval_long(tv);
1001 if (v == 0xFF || v == 0xFFFF) {
1002 dbg_info *dbgi = get_irn_dbg_info(node);
1003 ir_node *block = be_transform_node(get_nodes_block(node));
1004 ir_node *new_op = be_transform_node(op1);
1011 assert(v == 0xFFFF);
1014 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, new_op);
1015 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1021 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
1027 * Creates an ia32 Or.
1029 * @return The created ia32 Or node
1031 static ir_node *gen_Or(ir_node *node) {
1032 ir_node *op1 = get_Or_left(node);
1033 ir_node *op2 = get_Or_right(node);
1035 assert (! mode_is_float(get_irn_mode(node)));
1036 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
1042 * Creates an ia32 Eor.
1044 * @return The created ia32 Eor node
1046 static ir_node *gen_Eor(ir_node *node) {
1047 ir_node *op1 = get_Eor_left(node);
1048 ir_node *op2 = get_Eor_right(node);
1050 assert(! mode_is_float(get_irn_mode(node)));
1051 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
1056 * Creates an ia32 Sub.
1058 * @return The created ia32 Sub node
1060 static ir_node *gen_Sub(ir_node *node) {
1061 ir_node *op1 = get_Sub_left(node);
1062 ir_node *op2 = get_Sub_right(node);
1063 ir_mode *mode = get_irn_mode(node);
1065 if (mode_is_float(mode)) {
1066 if (USE_SSE2(env_cg))
1067 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1069 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1073 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1077 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1083 * Generates an ia32 DivMod with additional infrastructure for the
1084 * register allocator if needed.
1086 * @param dividend -no comment- :)
1087 * @param divisor -no comment- :)
1088 * @param dm_flav flavour_Div/Mod/DivMod
1089 * @return The created ia32 DivMod node
1091 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1092 ir_node *divisor, ia32_op_flavour_t dm_flav)
1094 ir_node *block = be_transform_node(get_nodes_block(node));
1095 ir_node *new_dividend = be_transform_node(dividend);
1096 ir_node *new_divisor = be_transform_node(divisor);
1097 ir_graph *irg = current_ir_graph;
1098 dbg_info *dbgi = get_irn_dbg_info(node);
1099 ir_mode *mode = get_irn_mode(node);
1100 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1101 ir_node *res, *proj_div, *proj_mod;
1102 ir_node *sign_extension;
1103 ir_node *mem, *new_mem;
1106 proj_div = proj_mod = NULL;
1110 mem = get_Div_mem(node);
1111 mode = get_Div_resmode(node);
1112 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1113 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1116 mem = get_Mod_mem(node);
1117 mode = get_Mod_resmode(node);
1118 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1119 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1121 case flavour_DivMod:
1122 mem = get_DivMod_mem(node);
1123 mode = get_DivMod_resmode(node);
1124 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1125 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1126 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1129 panic("invalid divmod flavour!");
1131 new_mem = be_transform_node(mem);
1133 if (mode_is_signed(mode)) {
1134 /* in signed mode, we need to sign extend the dividend */
1135 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1136 add_irn_dep(produceval, get_irg_frame(irg));
1137 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1140 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1141 add_irn_dep(sign_extension, get_irg_frame(irg));
1144 if (mode_is_signed(mode)) {
1145 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1146 sign_extension, new_divisor, new_mem, dm_flav);
1148 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1149 sign_extension, new_divisor, new_mem, dm_flav);
1152 set_ia32_exc_label(res, has_exc);
1153 set_irn_pinned(res, get_irn_pinned(node));
1155 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1162 * Wrapper for generate_DivMod. Sets flavour_Mod.
1165 static ir_node *gen_Mod(ir_node *node) {
1166 return generate_DivMod(node, get_Mod_left(node),
1167 get_Mod_right(node), flavour_Mod);
1171 * Wrapper for generate_DivMod. Sets flavour_Div.
1174 static ir_node *gen_Div(ir_node *node) {
1175 return generate_DivMod(node, get_Div_left(node),
1176 get_Div_right(node), flavour_Div);
1180 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1182 static ir_node *gen_DivMod(ir_node *node) {
1183 return generate_DivMod(node, get_DivMod_left(node),
1184 get_DivMod_right(node), flavour_DivMod);
1190 * Creates an ia32 floating Div.
1192 * @return The created ia32 xDiv node
1194 static ir_node *gen_Quot(ir_node *node) {
1195 ir_node *block = be_transform_node(get_nodes_block(node));
1196 ir_node *op1 = get_Quot_left(node);
1197 ir_node *new_op1 = be_transform_node(op1);
1198 ir_node *op2 = get_Quot_right(node);
1199 ir_node *new_op2 = be_transform_node(op2);
1200 ir_graph *irg = current_ir_graph;
1201 dbg_info *dbgi = get_irn_dbg_info(node);
1202 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1203 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1206 if (USE_SSE2(env_cg)) {
1207 ir_mode *mode = get_irn_mode(op1);
1208 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1,
1210 set_ia32_ls_mode(new_op, mode);
1212 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1213 new_op2, nomem, get_fpcw());
1215 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1221 * Creates an ia32 Shl.
1223 * @return The created ia32 Shl node
1225 static ir_node *gen_Shl(ir_node *node) {
1226 ir_node *right = get_Shl_right(node);
1228 /* test whether we can build a lea */
1229 if(is_Const(right)) {
1230 tarval *tv = get_Const_tarval(right);
1231 if(tarval_is_long(tv)) {
1232 long val = get_tarval_long(tv);
1233 if(val >= 0 && val <= 3) {
1234 ir_graph *irg = current_ir_graph;
1235 dbg_info *dbgi = get_irn_dbg_info(node);
1236 ir_node *block = be_transform_node(get_nodes_block(node));
1237 ir_node *base = ia32_new_NoReg_gp(env_cg);
1238 ir_node *index = be_transform_node(get_Shl_left(node));
1241 = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1242 set_ia32_am_scale(res, val);
1243 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1249 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1256 * Creates an ia32 Shr.
1258 * @return The created ia32 Shr node
1260 static ir_node *gen_Shr(ir_node *node) {
1261 return gen_shift_binop(node, get_Shr_left(node),
1262 get_Shr_right(node), new_rd_ia32_Shr);
1268 * Creates an ia32 Sar.
1270 * @return The created ia32 Shrs node
1272 static ir_node *gen_Shrs(ir_node *node) {
1273 ir_node *left = get_Shrs_left(node);
1274 ir_node *right = get_Shrs_right(node);
1275 ir_mode *mode = get_irn_mode(node);
1276 if(is_Const(right) && mode == mode_Is) {
1277 tarval *tv = get_Const_tarval(right);
1278 long val = get_tarval_long(tv);
1280 /* this is a sign extension */
1281 ir_graph *irg = current_ir_graph;
1282 dbg_info *dbgi = get_irn_dbg_info(node);
1283 ir_node *block = be_transform_node(get_nodes_block(node));
1285 ir_node *new_op = be_transform_node(op);
1286 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1287 add_irn_dep(pval, get_irg_frame(irg));
1289 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1293 /* 8 or 16 bit sign extension? */
1294 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1295 ir_node *shl_left = get_Shl_left(left);
1296 ir_node *shl_right = get_Shl_right(left);
1297 if(is_Const(shl_right)) {
1298 tarval *tv1 = get_Const_tarval(right);
1299 tarval *tv2 = get_Const_tarval(shl_right);
1300 if(tv1 == tv2 && tarval_is_long(tv1)) {
1301 long val = get_tarval_long(tv1);
1302 if(val == 16 || val == 24) {
1303 dbg_info *dbgi = get_irn_dbg_info(node);
1304 ir_node *block = be_transform_node(get_nodes_block(node));
1305 ir_node *new_op = be_transform_node(shl_left);
1315 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1317 SET_IA32_ORIG_NODE(res,
1318 ia32_get_old_node_name(env_cg, node));
1326 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1332 * Creates an ia32 RotL.
1334 * @param op1 The first operator
1335 * @param op2 The second operator
1336 * @return The created ia32 RotL node
1338 static ir_node *gen_RotL(ir_node *node,
1339 ir_node *op1, ir_node *op2) {
1340 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1346 * Creates an ia32 RotR.
1347 * NOTE: There is no RotR with immediate because this would always be a RotL
1348 * "imm-mode_size_bits" which can be pre-calculated.
1350 * @param op1 The first operator
1351 * @param op2 The second operator
1352 * @return The created ia32 RotR node
1354 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1356 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1362 * Creates an ia32 RotR or RotL (depending on the found pattern).
1364 * @return The created ia32 RotL or RotR node
1366 static ir_node *gen_Rot(ir_node *node) {
1367 ir_node *rotate = NULL;
1368 ir_node *op1 = get_Rot_left(node);
1369 ir_node *op2 = get_Rot_right(node);
1371 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1372 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1373 that means we can create a RotR instead of an Add and a RotL */
1375 if (get_irn_op(op2) == op_Add) {
1377 ir_node *left = get_Add_left(add);
1378 ir_node *right = get_Add_right(add);
1379 if (is_Const(right)) {
1380 tarval *tv = get_Const_tarval(right);
1381 ir_mode *mode = get_irn_mode(node);
1382 long bits = get_mode_size_bits(mode);
1384 if (get_irn_op(left) == op_Minus &&
1385 tarval_is_long(tv) &&
1386 get_tarval_long(tv) == bits)
1388 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1389 rotate = gen_RotR(node, op1, get_Minus_op(left));
1394 if (rotate == NULL) {
1395 rotate = gen_RotL(node, op1, op2);
1404 * Transforms a Minus node.
1406 * @param op The Minus operand
1407 * @return The created ia32 Minus node
1409 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1410 ir_node *block = be_transform_node(get_nodes_block(node));
1411 ir_graph *irg = current_ir_graph;
1412 dbg_info *dbgi = get_irn_dbg_info(node);
1413 ir_mode *mode = get_irn_mode(node);
1418 if (mode_is_float(mode)) {
1419 ir_node *new_op = be_transform_node(op);
1420 if (USE_SSE2(env_cg)) {
1421 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1422 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1423 ir_node *nomem = new_rd_NoMem(irg);
1425 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1427 size = get_mode_size_bits(mode);
1428 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1430 set_ia32_am_sc(res, ent);
1431 set_ia32_op_type(res, ia32_AddrModeS);
1432 set_ia32_ls_mode(res, mode);
1434 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1437 res = gen_unop(node, op, new_rd_ia32_Neg);
1440 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1446 * Transforms a Minus node.
1448 * @return The created ia32 Minus node
1450 static ir_node *gen_Minus(ir_node *node) {
1451 return gen_Minus_ex(node, get_Minus_op(node));
1454 static ir_node *create_Immediate_from_int(int val)
1456 ir_graph *irg = current_ir_graph;
1457 ir_node *start_block = get_irg_start_block(irg);
1458 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, 0, val);
1459 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
1464 static ir_node *gen_bin_Not(ir_node *node)
1466 ir_graph *irg = current_ir_graph;
1467 dbg_info *dbgi = get_irn_dbg_info(node);
1468 ir_node *block = be_transform_node(get_nodes_block(node));
1469 ir_node *op = get_Not_op(node);
1470 ir_node *new_op = be_transform_node(op);
1471 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1472 ir_node *nomem = new_NoMem();
1473 ir_node *one = create_Immediate_from_int(1);
1475 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1479 * Transforms a Not node.
1481 * @return The created ia32 Not node
1483 static ir_node *gen_Not(ir_node *node) {
1484 ir_node *op = get_Not_op(node);
1485 ir_mode *mode = get_irn_mode(node);
1487 if(mode == mode_b) {
1488 return gen_bin_Not(node);
1491 assert (! mode_is_float(get_irn_mode(node)));
1492 return gen_unop(node, op, new_rd_ia32_Not);
1498 * Transforms an Abs node.
1500 * @return The created ia32 Abs node
1502 static ir_node *gen_Abs(ir_node *node) {
1503 ir_node *block = be_transform_node(get_nodes_block(node));
1504 ir_node *op = get_Abs_op(node);
1505 ir_node *new_op = be_transform_node(op);
1506 ir_graph *irg = current_ir_graph;
1507 dbg_info *dbgi = get_irn_dbg_info(node);
1508 ir_mode *mode = get_irn_mode(node);
1509 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1510 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1511 ir_node *nomem = new_NoMem();
1516 if (mode_is_float(mode)) {
1517 if (USE_SSE2(env_cg)) {
1518 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1520 size = get_mode_size_bits(mode);
1521 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1523 set_ia32_am_sc(res, ent);
1525 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1527 set_ia32_op_type(res, ia32_AddrModeS);
1528 set_ia32_ls_mode(res, mode);
1531 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1532 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1536 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1537 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1540 add_irn_dep(pval, get_irg_frame(irg));
1541 SET_IA32_ORIG_NODE(sign_extension,
1542 ia32_get_old_node_name(env_cg, node));
1544 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1545 sign_extension, nomem);
1546 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1548 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1549 sign_extension, nomem);
1550 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1557 * Transforms a Load.
1559 * @return the created ia32 Load node
1561 static ir_node *gen_Load(ir_node *node) {
1562 ir_node *old_block = get_nodes_block(node);
1563 ir_node *block = be_transform_node(old_block);
1564 ir_node *ptr = get_Load_ptr(node);
1565 ir_node *mem = get_Load_mem(node);
1566 ir_node *new_mem = be_transform_node(mem);
1569 ir_graph *irg = current_ir_graph;
1570 dbg_info *dbgi = get_irn_dbg_info(node);
1571 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1572 ir_mode *mode = get_Load_mode(node);
1575 ia32_address_t addr;
1577 /* construct load address */
1578 memset(&addr, 0, sizeof(addr));
1579 ia32_create_address_mode(&addr, ptr, 0);
1586 base = be_transform_node(base);
1592 index = be_transform_node(index);
1595 if (mode_is_float(mode)) {
1596 if (USE_SSE2(env_cg)) {
1597 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1599 res_mode = mode_xmm;
1601 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1603 res_mode = mode_vfp;
1609 /* create a conv node with address mode for smaller modes */
1610 if(get_mode_size_bits(mode) < 32) {
1611 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index, noreg,
1614 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1619 set_irn_pinned(new_op, get_irn_pinned(node));
1620 set_ia32_op_type(new_op, ia32_AddrModeS);
1621 set_ia32_ls_mode(new_op, mode);
1622 set_address(new_op, &addr);
1624 /* make sure we are scheduled behind the initial IncSP/Barrier
1625 * to avoid spills being placed before it
1627 if (block == get_irg_start_block(irg)) {
1628 add_irn_dep(new_op, get_irg_frame(irg));
1631 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1632 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1637 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1638 ir_node *ptr, ir_mode *mode, ir_node *other)
1645 /* we only use address mode if we're the only user of the load */
1646 if(get_irn_n_edges(node) > 1)
1649 load = get_Proj_pred(node);
1652 if(get_nodes_block(load) != block)
1655 /* Store should be attached to the load */
1656 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1658 /* store should have the same pointer as the load */
1659 if(get_Load_ptr(load) != ptr)
1662 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1663 if(other != NULL && get_nodes_block(other) == block
1664 && heights_reachable_in_block(heights, other, load))
1667 assert(get_Load_mode(load) == mode);
1672 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1673 ir_node *mem, ir_node *ptr, ir_mode *mode,
1674 construct_binop_dest_func *func, int commutative)
1676 ir_node *src_block = get_nodes_block(node);
1678 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1679 ir_graph *irg = current_ir_graph;
1683 ia32_address_mode_t am;
1684 ia32_address_t *addr = &am.addr;
1685 memset(&am, 0, sizeof(am));
1687 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1688 build_address(&am, op1);
1689 new_op = create_immediate_or_transform(op2, 0);
1690 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1691 build_address(&am, op2);
1692 new_op = create_immediate_or_transform(op1, 0);
1697 if(addr->base == NULL)
1698 addr->base = noreg_gp;
1699 if(addr->index == NULL)
1700 addr->index = noreg_gp;
1701 if(addr->mem == NULL)
1702 addr->mem = new_NoMem();
1704 dbgi = get_irn_dbg_info(node);
1705 block = be_transform_node(src_block);
1706 new_node = func(dbgi, irg, block, addr->base, addr->index, new_op,
1708 set_address(new_node, addr);
1709 set_ia32_op_type(new_node, ia32_AddrModeD);
1710 set_ia32_ls_mode(new_node, mode);
1711 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1716 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1717 ir_node *ptr, ir_mode *mode,
1718 construct_unop_dest_func *func)
1720 ir_node *src_block = get_nodes_block(node);
1722 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1723 ir_graph *irg = current_ir_graph;
1726 ia32_address_mode_t am;
1727 ia32_address_t *addr = &am.addr;
1728 memset(&am, 0, sizeof(am));
1730 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1733 build_address(&am, op);
1735 if(addr->base == NULL)
1736 addr->base = noreg_gp;
1737 if(addr->index == NULL)
1738 addr->index = noreg_gp;
1739 if(addr->mem == NULL)
1740 addr->mem = new_NoMem();
1742 dbgi = get_irn_dbg_info(node);
1743 block = be_transform_node(src_block);
1744 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1745 set_address(new_node, addr);
1746 set_ia32_op_type(new_node, ia32_AddrModeD);
1747 set_ia32_ls_mode(new_node, mode);
1748 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1753 static ir_node *try_create_dest_am(ir_node *node) {
1754 ir_node *val = get_Store_value(node);
1755 ir_node *mem = get_Store_mem(node);
1756 ir_node *ptr = get_Store_ptr(node);
1757 ir_mode *mode = get_irn_mode(val);
1762 /* handle only GP modes for now... */
1763 if(!mode_needs_gp_reg(mode))
1765 if(get_mode_size_bits(mode) != 32)
1768 /* store must be the only user of the val node */
1769 if(get_irn_n_edges(val) > 1)
1772 switch(get_irn_opcode(val)) {
1774 op1 = get_Add_left(val);
1775 op2 = get_Add_right(val);
1776 if(is_Const_1(op2)) {
1777 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1778 new_rd_ia32_IncMem);
1780 } else if(is_Const_Minus_1(op2)) {
1781 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1782 new_rd_ia32_DecMem);
1785 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1786 new_rd_ia32_AddMem, 1);
1789 op1 = get_Sub_left(val);
1790 op2 = get_Sub_right(val);
1791 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1792 new_rd_ia32_SubMem, 0);
1795 op1 = get_And_left(val);
1796 op2 = get_And_right(val);
1797 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1798 new_rd_ia32_AndMem, 1);
1801 op1 = get_Or_left(val);
1802 op2 = get_Or_right(val);
1803 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1804 new_rd_ia32_OrMem, 1);
1807 op1 = get_Eor_left(val);
1808 op2 = get_Eor_right(val);
1809 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1810 new_rd_ia32_XorMem, 1);
1813 op1 = get_Shl_left(val);
1814 op2 = get_Shl_right(val);
1815 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1816 new_rd_ia32_ShlMem, 0);
1819 op1 = get_Shr_left(val);
1820 op2 = get_Shr_right(val);
1821 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1822 new_rd_ia32_ShrMem, 0);
1825 op1 = get_Shrs_left(val);
1826 op2 = get_Shrs_right(val);
1827 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1828 new_rd_ia32_SarMem, 0);
1831 op1 = get_Rot_left(val);
1832 op2 = get_Rot_right(val);
1833 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1834 new_rd_ia32_RolMem, 0);
1836 /* TODO: match ROR patterns... */
1838 op1 = get_Minus_op(val);
1839 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1842 /* TODO this would be ^ 1 with DestAM */
1845 op1 = get_Not_op(val);
1846 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1856 * Transforms a Store.
1858 * @return the created ia32 Store node
1860 static ir_node *gen_Store(ir_node *node) {
1861 ir_node *block = be_transform_node(get_nodes_block(node));
1862 ir_node *ptr = get_Store_ptr(node);
1865 ir_node *val = get_Store_value(node);
1867 ir_node *mem = get_Store_mem(node);
1868 ir_node *new_mem = be_transform_node(mem);
1869 ir_graph *irg = current_ir_graph;
1870 dbg_info *dbgi = get_irn_dbg_info(node);
1871 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1872 ir_mode *mode = get_irn_mode(val);
1874 ia32_address_t addr;
1876 /* check for destination address mode */
1877 new_op = try_create_dest_am(node);
1881 /* construct store address */
1882 memset(&addr, 0, sizeof(addr));
1883 ia32_create_address_mode(&addr, ptr, 0);
1890 base = be_transform_node(base);
1896 index = be_transform_node(index);
1899 if (mode_is_float(mode)) {
1900 new_val = be_transform_node(val);
1901 if (USE_SSE2(env_cg)) {
1902 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_val,
1905 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_val,
1909 new_val = create_immediate_or_transform(val, 0);
1913 if (get_mode_size_bits(mode) == 8) {
1914 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index,
1917 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_val,
1922 set_irn_pinned(new_op, get_irn_pinned(node));
1923 set_ia32_op_type(new_op, ia32_AddrModeD);
1924 set_ia32_ls_mode(new_op, mode);
1926 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1927 set_address(new_op, &addr);
1928 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1933 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1934 ir_node *cmp_left, ir_node *cmp_right,
1941 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1942 ia32_address_mode_t am;
1943 ia32_address_t *addr = &am.addr;
1945 if(cmp_right != NULL && !is_Const_0(cmp_right))
1948 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1949 mode = get_irn_mode(cmp_left);
1950 arg_left = get_And_left(cmp_left);
1951 arg_right = get_And_right(cmp_left);
1953 mode = get_irn_mode(cmp_left);
1954 arg_left = cmp_left;
1955 arg_right = cmp_left;
1961 assert(get_mode_size_bits(mode) <= 32);
1962 match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am);
1964 pnc = get_inversed_pnc(pnc);
1966 if(get_mode_size_bits(mode) == 8) {
1967 res = new_rd_ia32_TestJmp8Bit(dbgi, current_ir_graph, block, addr->base,
1968 addr->index, am.new_op1, am.new_op2,
1971 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, addr->base,
1972 addr->index, am.new_op1, am.new_op2,
1975 set_am_attributes(res, &am);
1976 set_ia32_ls_mode(res, mode);
1978 res = fix_mem_proj(res, &am);
1983 static ir_node *create_Switch(ir_node *node)
1985 ir_graph *irg = current_ir_graph;
1986 dbg_info *dbgi = get_irn_dbg_info(node);
1987 ir_node *block = be_transform_node(get_nodes_block(node));
1988 ir_node *sel = get_Cond_selector(node);
1989 ir_node *new_sel = be_transform_node(sel);
1991 int switch_min = INT_MAX;
1992 const ir_edge_t *edge;
1994 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1996 /* determine the smallest switch case value */
1997 foreach_out_edge(node, edge) {
1998 ir_node *proj = get_edge_src_irn(edge);
1999 int pn = get_Proj_proj(proj);
2004 if (switch_min != 0) {
2005 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2007 /* if smallest switch case is not 0 we need an additional sub */
2008 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2009 add_ia32_am_offs_int(new_sel, -switch_min);
2010 set_ia32_op_type(new_sel, ia32_AddrModeS);
2012 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2015 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
2016 set_ia32_pncode(res, get_Cond_defaultProj(node));
2018 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2024 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
2026 * @return The transformed node.
2028 static ir_node *gen_Cond(ir_node *node) {
2029 ir_node *src_block = get_nodes_block(node);
2030 ir_node *block = be_transform_node(src_block);
2031 ir_graph *irg = current_ir_graph;
2032 dbg_info *dbgi = get_irn_dbg_info(node);
2033 ir_node *sel = get_Cond_selector(node);
2034 ir_mode *sel_mode = get_irn_mode(sel);
2035 ir_node *res = NULL;
2036 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2037 ir_node *nomem = new_NoMem();
2047 if (sel_mode != mode_b) {
2048 return create_Switch(node);
2051 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
2052 /* it's some mode_b value but not a direct comparison -> create a
2054 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL, 1);
2055 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2059 /* address mode makes only sense when we're the only user of the cmp */
2060 use_am = get_irn_n_edges(node) <= 1;
2062 cmp = get_Proj_pred(sel);
2063 cmp_a = get_Cmp_left(cmp);
2064 cmp_b = get_Cmp_right(cmp);
2065 cmp_mode = get_irn_mode(cmp_a);
2066 pnc = get_Proj_proj(sel);
2067 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2068 pnc |= ia32_pn_Cmp_Unsigned;
2071 if(mode_needs_gp_reg(cmp_mode)) {
2072 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b, use_am);
2074 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2079 if (mode_is_float(cmp_mode)) {
2080 new_cmp_a = be_transform_node(cmp_a);
2081 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
2082 if (USE_SSE2(env_cg)) {
2083 res = new_rd_ia32_xCmpJmp(dbgi, irg, block, noreg, noreg, cmp_a,
2085 set_ia32_commutative(res);
2086 set_ia32_ls_mode(res, cmp_mode);
2088 res = new_rd_ia32_vfCmpJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
2089 set_ia32_commutative(res);
2092 ia32_address_mode_t am;
2093 ia32_address_t *addr = &am.addr;
2094 match_arguments(&am, src_block, cmp_a, cmp_b, 1, 1, use_am);
2096 pnc = get_inversed_pnc(pnc);
2098 if(get_mode_size_bits(cmp_mode) == 8) {
2099 res = new_rd_ia32_CmpJmp8Bit(dbgi, irg, block, addr->base,
2100 addr->index, am.new_op1, am.new_op2,
2103 res = new_rd_ia32_CmpJmp(dbgi, irg, block, addr->base, addr->index,
2104 am.new_op1, am.new_op2, addr->mem, pnc);
2106 set_am_attributes(res, &am);
2107 assert(cmp_mode != NULL);
2108 set_ia32_ls_mode(res, cmp_mode);
2110 res = fix_mem_proj(res, &am);
2113 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2121 * Transforms a CopyB node.
2123 * @return The transformed node.
2125 static ir_node *gen_CopyB(ir_node *node) {
2126 ir_node *block = be_transform_node(get_nodes_block(node));
2127 ir_node *src = get_CopyB_src(node);
2128 ir_node *new_src = be_transform_node(src);
2129 ir_node *dst = get_CopyB_dst(node);
2130 ir_node *new_dst = be_transform_node(dst);
2131 ir_node *mem = get_CopyB_mem(node);
2132 ir_node *new_mem = be_transform_node(mem);
2133 ir_node *res = NULL;
2134 ir_graph *irg = current_ir_graph;
2135 dbg_info *dbgi = get_irn_dbg_info(node);
2136 int size = get_type_size_bytes(get_CopyB_type(node));
2139 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2140 /* then we need the size explicitly in ECX. */
2141 if (size >= 32 * 4) {
2142 rem = size & 0x3; /* size % 4 */
2145 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2146 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
2148 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2149 /* we misuse the pncode field for the copyb size */
2150 set_ia32_pncode(res, rem);
2152 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2153 set_ia32_pncode(res, size);
2156 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2162 ir_node *gen_be_Copy(ir_node *node)
2164 ir_node *result = be_duplicate_node(node);
2165 ir_mode *mode = get_irn_mode(result);
2167 if (mode_needs_gp_reg(mode)) {
2168 set_irn_mode(result, mode_Iu);
2175 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
2176 dbg_info *dbgi, ir_node *block, int use_am)
2178 ir_graph *irg = current_ir_graph;
2179 ir_node *new_block = be_transform_node(block);
2180 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2181 ir_node *nomem = new_rd_NoMem(irg);
2186 ia32_address_mode_t am;
2187 ia32_address_t *addr = &am.addr;
2189 /* can we use a test instruction? */
2190 if(cmp_right == NULL || is_Const_0(cmp_right)) {
2191 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2192 if(is_And(cmp_left) &&
2193 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2194 ir_node *and_left = get_And_left(cmp_left);
2195 ir_node *and_right = get_And_right(cmp_left);
2197 mode = get_irn_mode(and_left);
2198 arg_left = and_left;
2199 arg_right = and_right;
2201 mode = get_irn_mode(cmp_left);
2202 arg_left = cmp_left;
2203 arg_right = cmp_left;
2206 assert(get_mode_size_bits(mode) <= 32);
2208 match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am);
2210 pnc = get_inversed_pnc(pnc);
2212 if(get_mode_size_bits(mode) == 8) {
2213 res = new_rd_ia32_TestSet8Bit(dbgi, irg, new_block, addr->base,
2214 addr->index, am.new_op1, am.new_op2,
2217 res = new_rd_ia32_TestSet(dbgi, irg, new_block, addr->base,
2218 addr->index, am.new_op1, am.new_op2,
2221 set_am_attributes(res, &am);
2222 set_ia32_ls_mode(res, mode);
2224 res = fix_mem_proj(res, &am);
2226 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, res,
2232 mode = get_irn_mode(cmp_left);
2233 assert(get_mode_size_bits(mode) <= 32);
2235 match_arguments(&am, block, cmp_left, cmp_right, 1, 1, use_am);
2237 pnc = get_inversed_pnc(pnc);
2239 if(get_mode_size_bits(mode) == 8) {
2240 res = new_rd_ia32_CmpSet8Bit(dbgi, irg, new_block, addr->base,
2241 addr->index, am.new_op1, am.new_op2,
2244 res = new_rd_ia32_CmpSet(dbgi, irg, new_block, addr->base, addr->index,
2245 am.new_op1, am.new_op2, addr->mem, pnc);
2247 set_am_attributes(res, &am);
2248 set_ia32_ls_mode(res, mode);
2250 res = fix_mem_proj(res, &am);
2252 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, res,
2258 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
2259 ir_node *val_true, ir_node *val_false,
2260 dbg_info *dbgi, ir_node *block)
2262 ir_graph *irg = current_ir_graph;
2263 ir_node *new_block = be_transform_node(block);
2264 ir_node *new_val_true = be_transform_node(val_true);
2265 ir_node *new_val_false = be_transform_node(val_false);
2266 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2267 ir_node *nomem = new_NoMem();
2268 ir_node *new_cmp_left;
2269 ir_node *new_cmp_right;
2273 /* cmovs with unknowns are pointless... */
2274 if(is_Unknown(val_true)) {
2275 #ifdef DEBUG_libfirm
2276 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2278 return new_val_false;
2280 if(is_Unknown(val_false)) {
2281 #ifdef DEBUG_libfirm
2282 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2284 return new_val_true;
2287 /* can we use a test instruction? */
2288 if(is_Const_0(cmp_right)) {
2289 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2290 if(is_And(cmp_left) &&
2291 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2292 ir_node *and_left = get_And_left(cmp_left);
2293 ir_node *and_right = get_And_right(cmp_left);
2295 mode = get_irn_mode(and_left);
2296 new_cmp_left = be_transform_node(and_left);
2297 new_cmp_right = create_immediate_or_transform(and_right, 0);
2299 mode = get_irn_mode(cmp_left);
2300 new_cmp_left = be_transform_node(cmp_left);
2301 new_cmp_right = be_transform_node(cmp_left);
2304 assert(get_mode_size_bits(mode) <= 32);
2306 if(get_mode_size_bits(mode) == 8) {
2307 res = new_rd_ia32_TestCMov8Bit(dbgi, current_ir_graph, new_block,
2308 noreg, noreg, new_cmp_left,
2309 new_cmp_right, nomem, new_val_true,
2310 new_val_false, pnc);
2312 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, new_block, noreg,
2313 noreg, new_cmp_left, new_cmp_right,
2314 nomem, new_val_true, new_val_false, pnc);
2316 set_ia32_ls_mode(res, mode);
2321 mode = get_irn_mode(cmp_left);
2322 new_cmp_left = be_transform_node(cmp_left);
2323 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
2325 /* no support for 8,16 bit modes yet */
2326 assert(get_mode_size_bits(mode) <= 32);
2328 if(get_mode_size_bits(mode) == 8) {
2329 res = new_rd_ia32_CmpCMov8Bit(dbgi, irg, new_block, noreg, noreg,
2330 new_cmp_left, new_cmp_right, nomem,
2331 new_val_true, new_val_false, pnc);
2333 res = new_rd_ia32_CmpCMov(dbgi, irg, new_block, noreg, noreg,
2334 new_cmp_left, new_cmp_right, nomem,
2335 new_val_true, new_val_false, pnc);
2337 set_ia32_ls_mode(res, mode);
2344 * Transforms a Psi node into CMov.
2346 * @return The transformed node.
2348 static ir_node *gen_Psi(ir_node *node) {
2349 ir_node *psi_true = get_Psi_val(node, 0);
2350 ir_node *psi_default = get_Psi_default(node);
2351 ia32_code_gen_t *cg = env_cg;
2352 ir_node *cond = get_Psi_cond(node, 0);
2353 ir_node *block = get_nodes_block(node);
2354 dbg_info *dbgi = get_irn_dbg_info(node);
2361 assert(get_Psi_n_conds(node) == 1);
2362 assert(get_irn_mode(cond) == mode_b);
2363 assert(mode_needs_gp_reg(get_irn_mode(node)));
2365 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
2366 /* a mode_b value, we have to compare it against 0 */
2368 cmp_right = new_Const_long(mode_Iu, 0);
2372 ir_node *cmp = get_Proj_pred(cond);
2374 cmp_left = get_Cmp_left(cmp);
2375 cmp_right = get_Cmp_right(cmp);
2376 cmp_mode = get_irn_mode(cmp_left);
2377 pnc = get_Proj_proj(cond);
2379 assert(!mode_is_float(cmp_mode));
2381 if (!mode_is_signed(cmp_mode)) {
2382 pnc |= ia32_pn_Cmp_Unsigned;
2386 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2387 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block, 1);
2388 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2389 pnc = get_negated_pnc(pnc, cmp_mode);
2390 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block, 1);
2392 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
2395 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2401 * Create a conversion from x87 state register to general purpose.
2403 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2404 ir_node *block = be_transform_node(get_nodes_block(node));
2405 ir_node *op = get_Conv_op(node);
2406 ir_node *new_op = be_transform_node(op);
2407 ia32_code_gen_t *cg = env_cg;
2408 ir_graph *irg = current_ir_graph;
2409 dbg_info *dbgi = get_irn_dbg_info(node);
2410 ir_node *noreg = ia32_new_NoReg_gp(cg);
2411 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2412 ir_mode *mode = get_irn_mode(node);
2413 ir_node *fist, *load;
2416 fist = new_rd_ia32_vfist(dbgi, irg, block,
2417 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2419 set_irn_pinned(fist, op_pin_state_floats);
2420 set_ia32_use_frame(fist);
2421 set_ia32_op_type(fist, ia32_AddrModeD);
2423 assert(get_mode_size_bits(mode) <= 32);
2424 /* exception we can only store signed 32 bit integers, so for unsigned
2425 we store a 64bit (signed) integer and load the lower bits */
2426 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2427 set_ia32_ls_mode(fist, mode_Ls);
2429 set_ia32_ls_mode(fist, mode_Is);
2431 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2434 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2436 set_irn_pinned(load, op_pin_state_floats);
2437 set_ia32_use_frame(load);
2438 set_ia32_op_type(load, ia32_AddrModeS);
2439 set_ia32_ls_mode(load, mode_Is);
2440 if(get_ia32_ls_mode(fist) == mode_Ls) {
2441 ia32_attr_t *attr = get_ia32_attr(load);
2442 attr->data.need_64bit_stackent = 1;
2444 ia32_attr_t *attr = get_ia32_attr(load);
2445 attr->data.need_32bit_stackent = 1;
2447 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2449 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2453 * Creates a x87 strict Conv by placing a Sore and a Load
2455 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2457 ir_node *block = get_nodes_block(node);
2458 ir_graph *irg = current_ir_graph;
2459 dbg_info *dbgi = get_irn_dbg_info(node);
2460 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2461 ir_node *nomem = new_NoMem();
2462 ir_node *frame = get_irg_frame(irg);
2463 ir_node *store, *load;
2466 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2468 set_ia32_use_frame(store);
2469 set_ia32_op_type(store, ia32_AddrModeD);
2470 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2472 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2474 set_ia32_use_frame(load);
2475 set_ia32_op_type(load, ia32_AddrModeS);
2476 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2478 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2483 * Create a conversion from general purpose to x87 register
2485 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2486 ir_node *block = be_transform_node(get_nodes_block(node));
2487 ir_node *op = get_Conv_op(node);
2488 ir_node *new_op = be_transform_node(op);
2489 ir_graph *irg = current_ir_graph;
2490 dbg_info *dbgi = get_irn_dbg_info(node);
2491 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2492 ir_node *nomem = new_NoMem();
2493 ir_mode *mode = get_irn_mode(op);
2494 ir_mode *store_mode;
2495 ir_node *fild, *store;
2499 /* first convert to 32 bit signed if necessary */
2500 src_bits = get_mode_size_bits(src_mode);
2501 if (src_bits == 8) {
2502 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem,
2504 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2506 } else if (src_bits < 32) {
2507 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem, src_mode);
2508 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2512 assert(get_mode_size_bits(mode) == 32);
2515 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2517 set_ia32_use_frame(store);
2518 set_ia32_op_type(store, ia32_AddrModeD);
2519 set_ia32_ls_mode(store, mode_Iu);
2521 /* exception for 32bit unsigned, do a 64bit spill+load */
2522 if(!mode_is_signed(mode)) {
2525 ir_node *zero_const = create_Immediate_from_int(0);
2527 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg,
2530 set_ia32_use_frame(zero_store);
2531 set_ia32_op_type(zero_store, ia32_AddrModeD);
2532 add_ia32_am_offs_int(zero_store, 4);
2533 set_ia32_ls_mode(zero_store, mode_Iu);
2538 store = new_rd_Sync(dbgi, irg, block, 2, in);
2539 store_mode = mode_Ls;
2541 store_mode = mode_Is;
2545 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2547 set_ia32_use_frame(fild);
2548 set_ia32_op_type(fild, ia32_AddrModeS);
2549 set_ia32_ls_mode(fild, store_mode);
2551 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2557 * Crete a conversion from one integer mode into another one
2559 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2560 dbg_info *dbgi, ir_node *new_block,
2563 ir_graph *irg = current_ir_graph;
2564 int src_bits = get_mode_size_bits(src_mode);
2565 int tgt_bits = get_mode_size_bits(tgt_mode);
2566 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2567 ir_node *nomem = new_rd_NoMem(irg);
2569 ir_mode *smaller_mode;
2572 if (src_bits < tgt_bits) {
2573 smaller_mode = src_mode;
2574 smaller_bits = src_bits;
2576 smaller_mode = tgt_mode;
2577 smaller_bits = tgt_bits;
2580 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2581 if (smaller_bits == 8) {
2582 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2583 new_op, nomem, smaller_mode);
2585 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, noreg, noreg, new_op,
2586 nomem, smaller_mode);
2593 * Transforms a Conv node.
2595 * @return The created ia32 Conv node
2597 static ir_node *gen_Conv(ir_node *node) {
2598 ir_node *block = be_transform_node(get_nodes_block(node));
2599 ir_node *op = get_Conv_op(node);
2600 ir_node *new_op = be_transform_node(op);
2601 ir_graph *irg = current_ir_graph;
2602 dbg_info *dbgi = get_irn_dbg_info(node);
2603 ir_mode *src_mode = get_irn_mode(op);
2604 ir_mode *tgt_mode = get_irn_mode(node);
2605 int src_bits = get_mode_size_bits(src_mode);
2606 int tgt_bits = get_mode_size_bits(tgt_mode);
2607 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2608 ir_node *nomem = new_rd_NoMem(irg);
2611 if (src_mode == mode_b) {
2612 assert(mode_is_int(tgt_mode));
2613 /* nothing to do, we already model bools as 0/1 ints */
2617 if (src_mode == tgt_mode) {
2618 if (get_Conv_strict(node)) {
2619 if (USE_SSE2(env_cg)) {
2620 /* when we are in SSE mode, we can kill all strict no-op conversion */
2624 /* this should be optimized already, but who knows... */
2625 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2626 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2631 if (mode_is_float(src_mode)) {
2632 /* we convert from float ... */
2633 if (mode_is_float(tgt_mode)) {
2634 if(src_mode == mode_E && tgt_mode == mode_D
2635 && !get_Conv_strict(node)) {
2636 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2641 if (USE_SSE2(env_cg)) {
2642 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2643 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2644 set_ia32_ls_mode(res, tgt_mode);
2646 if(get_Conv_strict(node)) {
2647 res = gen_x87_strict_conv(tgt_mode, new_op);
2648 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2651 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2656 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2657 if (USE_SSE2(env_cg)) {
2658 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2659 set_ia32_ls_mode(res, src_mode);
2661 return gen_x87_fp_to_gp(node);
2665 /* we convert from int ... */
2666 if (mode_is_float(tgt_mode)) {
2668 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2669 if (USE_SSE2(env_cg)) {
2670 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2671 set_ia32_ls_mode(res, tgt_mode);
2673 res = gen_x87_gp_to_fp(node, src_mode);
2674 if(get_Conv_strict(node)) {
2675 res = gen_x87_strict_conv(tgt_mode, res);
2676 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2677 ia32_get_old_node_name(env_cg, node));
2681 } else if(tgt_mode == mode_b) {
2682 /* mode_b lowering already took care that we only have 0/1 values */
2683 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2684 src_mode, tgt_mode));
2688 if (src_bits == tgt_bits) {
2689 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2690 src_mode, tgt_mode));
2694 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, new_op);
2698 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2704 int check_immediate_constraint(long val, char immediate_constraint_type)
2706 switch (immediate_constraint_type) {
2710 return val >= 0 && val <= 32;
2712 return val >= 0 && val <= 63;
2714 return val >= -128 && val <= 127;
2716 return val == 0xff || val == 0xffff;
2718 return val >= 0 && val <= 3;
2720 return val >= 0 && val <= 255;
2722 return val >= 0 && val <= 127;
2726 panic("Invalid immediate constraint found");
2731 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2734 tarval *offset = NULL;
2735 int offset_sign = 0;
2737 ir_entity *symconst_ent = NULL;
2738 int symconst_sign = 0;
2740 ir_node *cnst = NULL;
2741 ir_node *symconst = NULL;
2747 mode = get_irn_mode(node);
2748 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2752 if(is_Minus(node)) {
2754 node = get_Minus_op(node);
2757 if(is_Const(node)) {
2760 offset_sign = minus;
2761 } else if(is_SymConst(node)) {
2764 symconst_sign = minus;
2765 } else if(is_Add(node)) {
2766 ir_node *left = get_Add_left(node);
2767 ir_node *right = get_Add_right(node);
2768 if(is_Const(left) && is_SymConst(right)) {
2771 symconst_sign = minus;
2772 offset_sign = minus;
2773 } else if(is_SymConst(left) && is_Const(right)) {
2776 symconst_sign = minus;
2777 offset_sign = minus;
2779 } else if(is_Sub(node)) {
2780 ir_node *left = get_Sub_left(node);
2781 ir_node *right = get_Sub_right(node);
2782 if(is_Const(left) && is_SymConst(right)) {
2785 symconst_sign = !minus;
2786 offset_sign = minus;
2787 } else if(is_SymConst(left) && is_Const(right)) {
2790 symconst_sign = minus;
2791 offset_sign = !minus;
2798 offset = get_Const_tarval(cnst);
2799 if(tarval_is_long(offset)) {
2800 val = get_tarval_long(offset);
2801 } else if(tarval_is_null(offset)) {
2804 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2809 if(!check_immediate_constraint(val, immediate_constraint_type))
2812 if(symconst != NULL) {
2813 if(immediate_constraint_type != 0) {
2814 /* we need full 32bits for symconsts */
2818 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2820 symconst_ent = get_SymConst_entity(symconst);
2822 if(cnst == NULL && symconst == NULL)
2825 if(offset_sign && offset != NULL) {
2826 offset = tarval_neg(offset);
2829 irg = current_ir_graph;
2830 dbgi = get_irn_dbg_info(node);
2831 block = get_irg_start_block(irg);
2832 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2833 symconst_sign, val);
2834 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2840 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2842 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2843 if (new_node == NULL) {
2844 new_node = be_transform_node(node);
2849 typedef struct constraint_t constraint_t;
2850 struct constraint_t {
2853 const arch_register_req_t **out_reqs;
2855 const arch_register_req_t *req;
2856 unsigned immediate_possible;
2857 char immediate_type;
2860 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2862 int immediate_possible = 0;
2863 char immediate_type = 0;
2864 unsigned limited = 0;
2865 const arch_register_class_t *cls = NULL;
2866 ir_graph *irg = current_ir_graph;
2867 struct obstack *obst = get_irg_obstack(irg);
2868 arch_register_req_t *req;
2869 unsigned *limited_ptr;
2873 /* TODO: replace all the asserts with nice error messages */
2875 printf("Constraint: %s\n", c);
2885 assert(cls == NULL ||
2886 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2887 cls = &ia32_reg_classes[CLASS_ia32_gp];
2888 limited |= 1 << REG_EAX;
2891 assert(cls == NULL ||
2892 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2893 cls = &ia32_reg_classes[CLASS_ia32_gp];
2894 limited |= 1 << REG_EBX;
2897 assert(cls == NULL ||
2898 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2899 cls = &ia32_reg_classes[CLASS_ia32_gp];
2900 limited |= 1 << REG_ECX;
2903 assert(cls == NULL ||
2904 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2905 cls = &ia32_reg_classes[CLASS_ia32_gp];
2906 limited |= 1 << REG_EDX;
2909 assert(cls == NULL ||
2910 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2911 cls = &ia32_reg_classes[CLASS_ia32_gp];
2912 limited |= 1 << REG_EDI;
2915 assert(cls == NULL ||
2916 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2917 cls = &ia32_reg_classes[CLASS_ia32_gp];
2918 limited |= 1 << REG_ESI;
2921 case 'q': /* q means lower part of the regs only, this makes no
2922 * difference to Q for us (we only assigne whole registers) */
2923 assert(cls == NULL ||
2924 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2925 cls = &ia32_reg_classes[CLASS_ia32_gp];
2926 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2930 assert(cls == NULL ||
2931 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2932 cls = &ia32_reg_classes[CLASS_ia32_gp];
2933 limited |= 1 << REG_EAX | 1 << REG_EDX;
2936 assert(cls == NULL ||
2937 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2938 cls = &ia32_reg_classes[CLASS_ia32_gp];
2939 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2940 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2947 assert(cls == NULL);
2948 cls = &ia32_reg_classes[CLASS_ia32_gp];
2954 /* TODO: mark values so the x87 simulator knows about t and u */
2955 assert(cls == NULL);
2956 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2961 assert(cls == NULL);
2962 /* TODO: check that sse2 is supported */
2963 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2973 assert(!immediate_possible);
2974 immediate_possible = 1;
2975 immediate_type = *c;
2979 assert(!immediate_possible);
2980 immediate_possible = 1;
2984 assert(!immediate_possible && cls == NULL);
2985 immediate_possible = 1;
2986 cls = &ia32_reg_classes[CLASS_ia32_gp];
2999 assert(constraint->is_in && "can only specify same constraint "
3002 sscanf(c, "%d%n", &same_as, &p);
3009 case 'E': /* no float consts yet */
3010 case 'F': /* no float consts yet */
3011 case 's': /* makes no sense on x86 */
3012 case 'X': /* we can't support that in firm */
3016 case '<': /* no autodecrement on x86 */
3017 case '>': /* no autoincrement on x86 */
3018 case 'C': /* sse constant not supported yet */
3019 case 'G': /* 80387 constant not supported yet */
3020 case 'y': /* we don't support mmx registers yet */
3021 case 'Z': /* not available in 32 bit mode */
3022 case 'e': /* not available in 32 bit mode */
3023 assert(0 && "asm constraint not supported");
3026 assert(0 && "unknown asm constraint found");
3033 const arch_register_req_t *other_constr;
3035 assert(cls == NULL && "same as and register constraint not supported");
3036 assert(!immediate_possible && "same as and immediate constraint not "
3038 assert(same_as < constraint->n_outs && "wrong constraint number in "
3039 "same_as constraint");
3041 other_constr = constraint->out_reqs[same_as];
3043 req = obstack_alloc(obst, sizeof(req[0]));
3044 req->cls = other_constr->cls;
3045 req->type = arch_register_req_type_should_be_same;
3046 req->limited = NULL;
3047 req->other_same = pos;
3048 req->other_different = -1;
3050 /* switch constraints. This is because in firm we have same_as
3051 * constraints on the output constraints while in the gcc asm syntax
3052 * they are specified on the input constraints */
3053 constraint->req = other_constr;
3054 constraint->out_reqs[same_as] = req;
3055 constraint->immediate_possible = 0;
3059 if(immediate_possible && cls == NULL) {
3060 cls = &ia32_reg_classes[CLASS_ia32_gp];
3062 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3063 assert(cls != NULL);
3065 if(immediate_possible) {
3066 assert(constraint->is_in
3067 && "imeediates make no sense for output constraints");
3069 /* todo: check types (no float input on 'r' constrained in and such... */
3072 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3073 limited_ptr = (unsigned*) (req+1);
3075 req = obstack_alloc(obst, sizeof(req[0]));
3077 memset(req, 0, sizeof(req[0]));
3080 req->type = arch_register_req_type_limited;
3081 *limited_ptr = limited;
3082 req->limited = limited_ptr;
3084 req->type = arch_register_req_type_normal;
3088 constraint->req = req;
3089 constraint->immediate_possible = immediate_possible;
3090 constraint->immediate_type = immediate_type;
3094 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3101 panic("Clobbers not supported yet");
3105 * generates code for a ASM node
3107 static ir_node *gen_ASM(ir_node *node)
3110 ir_graph *irg = current_ir_graph;
3111 ir_node *block = be_transform_node(get_nodes_block(node));
3112 dbg_info *dbgi = get_irn_dbg_info(node);
3119 ia32_asm_attr_t *attr;
3120 const arch_register_req_t **out_reqs;
3121 const arch_register_req_t **in_reqs;
3122 struct obstack *obst;
3123 constraint_t parsed_constraint;
3125 /* transform inputs */
3126 arity = get_irn_arity(node);
3127 in = alloca(arity * sizeof(in[0]));
3128 memset(in, 0, arity * sizeof(in[0]));
3130 n_outs = get_ASM_n_output_constraints(node);
3131 n_clobbers = get_ASM_n_clobbers(node);
3132 out_arity = n_outs + n_clobbers;
3134 /* construct register constraints */
3135 obst = get_irg_obstack(irg);
3136 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
3137 parsed_constraint.out_reqs = out_reqs;
3138 parsed_constraint.n_outs = n_outs;
3139 parsed_constraint.is_in = 0;
3140 for(i = 0; i < out_arity; ++i) {
3144 const ir_asm_constraint *constraint;
3145 constraint = & get_ASM_output_constraints(node) [i];
3146 c = get_id_str(constraint->constraint);
3147 parse_asm_constraint(i, &parsed_constraint, c);
3149 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
3150 c = get_id_str(glob_id);
3151 parse_clobber(node, i, &parsed_constraint, c);
3153 out_reqs[i] = parsed_constraint.req;
3156 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
3157 parsed_constraint.is_in = 1;
3158 for(i = 0; i < arity; ++i) {
3159 const ir_asm_constraint *constraint;
3163 constraint = & get_ASM_input_constraints(node) [i];
3164 constr_id = constraint->constraint;
3165 c = get_id_str(constr_id);
3166 parse_asm_constraint(i, &parsed_constraint, c);
3167 in_reqs[i] = parsed_constraint.req;
3169 if(parsed_constraint.immediate_possible) {
3170 ir_node *pred = get_irn_n(node, i);
3171 char imm_type = parsed_constraint.immediate_type;
3172 ir_node *immediate = try_create_Immediate(pred, imm_type);
3174 if(immediate != NULL) {
3180 /* transform inputs */
3181 for(i = 0; i < arity; ++i) {
3183 ir_node *transformed;
3188 pred = get_irn_n(node, i);
3189 transformed = be_transform_node(pred);
3190 in[i] = transformed;
3193 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
3195 generic_attr = get_irn_generic_attr(res);
3196 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
3197 attr->asm_text = get_ASM_text(node);
3198 set_ia32_out_req_all(res, out_reqs);
3199 set_ia32_in_req_all(res, in_reqs);
3201 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3206 /********************************************
3209 * | |__ ___ _ __ ___ __| | ___ ___
3210 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3211 * | |_) | __/ | | | (_) | (_| | __/\__ \
3212 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3214 ********************************************/
3217 * Transforms a FrameAddr into an ia32 Add.
3219 static ir_node *gen_be_FrameAddr(ir_node *node) {
3220 ir_node *block = be_transform_node(get_nodes_block(node));
3221 ir_node *op = be_get_FrameAddr_frame(node);
3222 ir_node *new_op = be_transform_node(op);
3223 ir_graph *irg = current_ir_graph;
3224 dbg_info *dbgi = get_irn_dbg_info(node);
3225 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3228 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3229 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3230 set_ia32_use_frame(res);
3232 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3238 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3240 static ir_node *gen_be_Return(ir_node *node) {
3241 ir_graph *irg = current_ir_graph;
3242 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3243 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3244 ir_entity *ent = get_irg_entity(irg);
3245 ir_type *tp = get_entity_type(ent);
3250 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3251 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3254 int pn_ret_val, pn_ret_mem, arity, i;
3256 assert(ret_val != NULL);
3257 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3258 return be_duplicate_node(node);
3261 res_type = get_method_res_type(tp, 0);
3263 if (! is_Primitive_type(res_type)) {
3264 return be_duplicate_node(node);
3267 mode = get_type_mode(res_type);
3268 if (! mode_is_float(mode)) {
3269 return be_duplicate_node(node);
3272 assert(get_method_n_ress(tp) == 1);
3274 pn_ret_val = get_Proj_proj(ret_val);
3275 pn_ret_mem = get_Proj_proj(ret_mem);
3277 /* get the Barrier */
3278 barrier = get_Proj_pred(ret_val);
3280 /* get result input of the Barrier */
3281 ret_val = get_irn_n(barrier, pn_ret_val);
3282 new_ret_val = be_transform_node(ret_val);
3284 /* get memory input of the Barrier */
3285 ret_mem = get_irn_n(barrier, pn_ret_mem);
3286 new_ret_mem = be_transform_node(ret_mem);
3288 frame = get_irg_frame(irg);
3290 dbgi = get_irn_dbg_info(barrier);
3291 block = be_transform_node(get_nodes_block(barrier));
3293 noreg = ia32_new_NoReg_gp(env_cg);
3295 /* store xmm0 onto stack */
3296 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3297 new_ret_val, new_ret_mem);
3298 set_ia32_ls_mode(sse_store, mode);
3299 set_ia32_op_type(sse_store, ia32_AddrModeD);
3300 set_ia32_use_frame(sse_store);
3302 /* load into x87 register */
3303 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3304 set_ia32_op_type(fld, ia32_AddrModeS);
3305 set_ia32_use_frame(fld);
3307 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3308 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3310 /* create a new barrier */
3311 arity = get_irn_arity(barrier);
3312 in = alloca(arity * sizeof(in[0]));
3313 for (i = 0; i < arity; ++i) {
3316 if (i == pn_ret_val) {
3318 } else if (i == pn_ret_mem) {
3321 ir_node *in = get_irn_n(barrier, i);
3322 new_in = be_transform_node(in);
3327 new_barrier = new_ir_node(dbgi, irg, block,
3328 get_irn_op(barrier), get_irn_mode(barrier),
3330 copy_node_attr(barrier, new_barrier);
3331 be_duplicate_deps(barrier, new_barrier);
3332 be_set_transformed_node(barrier, new_barrier);
3333 mark_irn_visited(barrier);
3335 /* transform normally */
3336 return be_duplicate_node(node);
3340 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3342 static ir_node *gen_be_AddSP(ir_node *node) {
3343 ir_node *block = be_transform_node(get_nodes_block(node));
3344 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3346 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3347 ir_node *new_sp = be_transform_node(sp);
3348 ir_graph *irg = current_ir_graph;
3349 dbg_info *dbgi = get_irn_dbg_info(node);
3350 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3351 ir_node *nomem = new_NoMem();
3354 new_sz = create_immediate_or_transform(sz, 0);
3356 /* ia32 stack grows in reverse direction, make a SubSP */
3357 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3359 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3365 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3367 static ir_node *gen_be_SubSP(ir_node *node) {
3368 ir_node *block = be_transform_node(get_nodes_block(node));
3369 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3371 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3372 ir_node *new_sp = be_transform_node(sp);
3373 ir_graph *irg = current_ir_graph;
3374 dbg_info *dbgi = get_irn_dbg_info(node);
3375 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3376 ir_node *nomem = new_NoMem();
3379 new_sz = create_immediate_or_transform(sz, 0);
3381 /* ia32 stack grows in reverse direction, make an AddSP */
3382 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3383 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3389 * This function just sets the register for the Unknown node
3390 * as this is not done during register allocation because Unknown
3391 * is an "ignore" node.
3393 static ir_node *gen_Unknown(ir_node *node) {
3394 ir_mode *mode = get_irn_mode(node);
3396 if (mode_is_float(mode)) {
3397 if (USE_SSE2(env_cg)) {
3398 return ia32_new_Unknown_xmm(env_cg);
3400 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3401 ir_graph *irg = current_ir_graph;
3402 dbg_info *dbgi = get_irn_dbg_info(node);
3403 ir_node *block = get_irg_start_block(irg);
3404 return new_rd_ia32_vfldz(dbgi, irg, block);
3406 } else if (mode_needs_gp_reg(mode)) {
3407 return ia32_new_Unknown_gp(env_cg);
3409 assert(0 && "unsupported Unknown-Mode");
3416 * Change some phi modes
3418 static ir_node *gen_Phi(ir_node *node) {
3419 ir_node *block = be_transform_node(get_nodes_block(node));
3420 ir_graph *irg = current_ir_graph;
3421 dbg_info *dbgi = get_irn_dbg_info(node);
3422 ir_mode *mode = get_irn_mode(node);
3425 if(mode_needs_gp_reg(mode)) {
3426 /* we shouldn't have any 64bit stuff around anymore */
3427 assert(get_mode_size_bits(mode) <= 32);
3428 /* all integer operations are on 32bit registers now */
3430 } else if(mode_is_float(mode)) {
3431 if (USE_SSE2(env_cg)) {
3438 /* phi nodes allow loops, so we use the old arguments for now
3439 * and fix this later */
3440 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3441 get_irn_in(node) + 1);
3442 copy_node_attr(node, phi);
3443 be_duplicate_deps(node, phi);
3445 be_set_transformed_node(node, phi);
3446 be_enqueue_preds(node);
3454 static ir_node *gen_IJmp(ir_node *node) {
3455 /* TODO: support AM */
3456 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3460 /**********************************************************************
3463 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3464 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3465 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3466 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3468 **********************************************************************/
3470 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3472 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3475 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3476 ir_node *val, ir_node *mem);
3479 * Transforms a lowered Load into a "real" one.
3481 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3483 ir_node *block = be_transform_node(get_nodes_block(node));
3484 ir_node *ptr = get_irn_n(node, 0);
3485 ir_node *new_ptr = be_transform_node(ptr);
3486 ir_node *mem = get_irn_n(node, 1);
3487 ir_node *new_mem = be_transform_node(mem);
3488 ir_graph *irg = current_ir_graph;
3489 dbg_info *dbgi = get_irn_dbg_info(node);
3490 ir_mode *mode = get_ia32_ls_mode(node);
3491 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3494 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3496 set_ia32_op_type(new_op, ia32_AddrModeS);
3497 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3498 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3499 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3500 if (is_ia32_am_sc_sign(node))
3501 set_ia32_am_sc_sign(new_op);
3502 set_ia32_ls_mode(new_op, mode);
3503 if (is_ia32_use_frame(node)) {
3504 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3505 set_ia32_use_frame(new_op);
3508 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3514 * Transforms a lowered Store into a "real" one.
3516 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3518 ir_node *block = be_transform_node(get_nodes_block(node));
3519 ir_node *ptr = get_irn_n(node, 0);
3520 ir_node *new_ptr = be_transform_node(ptr);
3521 ir_node *val = get_irn_n(node, 1);
3522 ir_node *new_val = be_transform_node(val);
3523 ir_node *mem = get_irn_n(node, 2);
3524 ir_node *new_mem = be_transform_node(mem);
3525 ir_graph *irg = current_ir_graph;
3526 dbg_info *dbgi = get_irn_dbg_info(node);
3527 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3528 ir_mode *mode = get_ia32_ls_mode(node);
3532 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3534 am_offs = get_ia32_am_offs_int(node);
3535 add_ia32_am_offs_int(new_op, am_offs);
3537 set_ia32_op_type(new_op, ia32_AddrModeD);
3538 set_ia32_ls_mode(new_op, mode);
3539 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3540 set_ia32_use_frame(new_op);
3542 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3549 * Transforms an ia32_l_XXX into a "real" XXX node
3551 * @param node The node to transform
3552 * @return the created ia32 XXX node
3554 #define GEN_LOWERED_OP(op) \
3555 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3556 return gen_binop(node, get_binop_left(node), \
3557 get_binop_right(node), new_rd_ia32_##op,0); \
3560 #define GEN_LOWERED_x87_OP(op) \
3561 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3563 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3564 get_binop_right(node), new_rd_ia32_##op); \
3568 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3569 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3570 return gen_shift_binop(node, get_irn_n(node, 0), \
3571 get_irn_n(node, 1), new_rd_ia32_##op); \
3579 GEN_LOWERED_x87_OP(vfprem)
3580 GEN_LOWERED_x87_OP(vfmul)
3581 GEN_LOWERED_x87_OP(vfsub)
3582 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3583 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3584 GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
3585 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3589 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3591 * @param node The node to transform
3592 * @return the created ia32 Neg node
3594 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3595 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3599 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3601 * @param node The node to transform
3602 * @return the created ia32 vfild node
3604 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3605 return gen_lowered_Load(node, new_rd_ia32_vfild);
3609 * Transforms an ia32_l_Load into a "real" ia32_Load node
3611 * @param node The node to transform
3612 * @return the created ia32 Load node
3614 static ir_node *gen_ia32_l_Load(ir_node *node) {
3615 return gen_lowered_Load(node, new_rd_ia32_Load);
3619 * Transforms an ia32_l_Store into a "real" ia32_Store node
3621 * @param node The node to transform
3622 * @return the created ia32 Store node
3624 static ir_node *gen_ia32_l_Store(ir_node *node) {
3625 return gen_lowered_Store(node, new_rd_ia32_Store);
3629 * Transforms a l_vfist into a "real" vfist node.
3631 * @param node The node to transform
3632 * @return the created ia32 vfist node
3634 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3635 ir_node *block = be_transform_node(get_nodes_block(node));
3636 ir_node *ptr = get_irn_n(node, 0);
3637 ir_node *new_ptr = be_transform_node(ptr);
3638 ir_node *val = get_irn_n(node, 1);
3639 ir_node *new_val = be_transform_node(val);
3640 ir_node *mem = get_irn_n(node, 2);
3641 ir_node *new_mem = be_transform_node(mem);
3642 ir_graph *irg = current_ir_graph;
3643 dbg_info *dbgi = get_irn_dbg_info(node);
3644 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3645 ir_mode *mode = get_ia32_ls_mode(node);
3646 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3650 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_val,
3651 trunc_mode, new_mem);
3653 am_offs = get_ia32_am_offs_int(node);
3654 add_ia32_am_offs_int(new_op, am_offs);
3656 set_ia32_op_type(new_op, ia32_AddrModeD);
3657 set_ia32_ls_mode(new_op, mode);
3658 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3659 set_ia32_use_frame(new_op);
3661 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3667 * Transforms a l_vfdiv into a "real" vfdiv node.
3669 * @param env The transformation environment
3670 * @return the created ia32 vfdiv node
3672 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3673 ir_node *block = be_transform_node(get_nodes_block(node));
3674 ir_node *left = get_binop_left(node);
3675 ir_node *new_left = be_transform_node(left);
3676 ir_node *right = get_binop_right(node);
3677 ir_node *new_right = be_transform_node(right);
3678 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3679 ir_graph *irg = current_ir_graph;
3680 dbg_info *dbgi = get_irn_dbg_info(node);
3681 ir_node *fpcw = get_fpcw();
3684 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3685 new_right, new_NoMem(), fpcw);
3686 clear_ia32_commutative(vfdiv);
3688 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3694 * Transforms a l_MulS into a "real" MulS node.
3696 * @param env The transformation environment
3697 * @return the created ia32 Mul node
3699 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3700 ir_node *block = be_transform_node(get_nodes_block(node));
3701 ir_node *left = get_binop_left(node);
3702 ir_node *new_left = be_transform_node(left);
3703 ir_node *right = get_binop_right(node);
3704 ir_node *new_right = be_transform_node(right);
3705 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3706 ir_graph *irg = current_ir_graph;
3707 dbg_info *dbgi = get_irn_dbg_info(node);
3709 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3710 /* and then skip the result Proj, because all needed Projs are already there. */
3711 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3712 new_right, new_NoMem());
3713 clear_ia32_commutative(muls);
3715 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3721 * Transforms a l_IMulS into a "real" IMul1OPS node.
3723 * @param env The transformation environment
3724 * @return the created ia32 IMul1OP node
3726 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3727 ir_node *block = be_transform_node(get_nodes_block(node));
3728 ir_node *left = get_binop_left(node);
3729 ir_node *new_left = be_transform_node(left);
3730 ir_node *right = get_binop_right(node);
3731 ir_node *new_right = be_transform_node(right);
3732 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3733 ir_graph *irg = current_ir_graph;
3734 dbg_info *dbgi = get_irn_dbg_info(node);
3736 /* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */
3737 /* and then skip the result Proj, because all needed Projs are already there. */
3738 ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_left,
3739 new_right, new_NoMem());
3740 clear_ia32_commutative(muls);
3742 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3747 static ir_node *gen_ia32_Add64Bit(ir_node *node)
3749 ir_node *a_l = be_transform_node(get_irn_n(node, 0));
3750 ir_node *a_h = be_transform_node(get_irn_n(node, 1));
3751 ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0);
3752 ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0);
3753 ir_node *block = be_transform_node(get_nodes_block(node));
3754 dbg_info *dbgi = get_irn_dbg_info(node);
3755 ir_graph *irg = current_ir_graph;
3756 ir_node *new_op = new_rd_ia32_Add64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h);
3757 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3762 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3763 * op1 - target to be shifted
3764 * op2 - contains bits to be shifted into target
3766 * Only op3 can be an immediate.
3768 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3769 ir_node *op2, ir_node *count)
3771 ir_node *block = be_transform_node(get_nodes_block(node));
3772 ir_node *new_op = NULL;
3773 ir_graph *irg = current_ir_graph;
3774 dbg_info *dbgi = get_irn_dbg_info(node);
3775 ir_node *new_op1 = be_transform_node(op1);
3776 ir_node *new_op2 = be_transform_node(op2);
3777 ir_node *new_count = create_immediate_or_transform(count, 'I');
3779 /* TODO proper AM support */
3781 if (is_ia32_l_ShlD(node))
3782 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3784 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3786 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3791 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3792 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3793 get_irn_n(node, 1), get_irn_n(node, 2));
3796 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3797 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3798 get_irn_n(node, 1), get_irn_n(node, 2));
3802 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3804 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3805 ir_node *block = be_transform_node(get_nodes_block(node));
3806 ir_node *val = get_irn_n(node, 1);
3807 ir_node *new_val = be_transform_node(val);
3808 ia32_code_gen_t *cg = env_cg;
3809 ir_node *res = NULL;
3810 ir_graph *irg = current_ir_graph;
3812 ir_node *noreg, *new_ptr, *new_mem;
3819 mem = get_irn_n(node, 2);
3820 new_mem = be_transform_node(mem);
3821 ptr = get_irn_n(node, 0);
3822 new_ptr = be_transform_node(ptr);
3823 noreg = ia32_new_NoReg_gp(cg);
3824 dbgi = get_irn_dbg_info(node);
3826 /* Store x87 -> MEM */
3827 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3828 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3829 set_ia32_use_frame(res);
3830 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3831 set_ia32_op_type(res, ia32_AddrModeD);
3833 /* Load MEM -> SSE */
3834 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
3835 get_ia32_ls_mode(node));
3836 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3837 set_ia32_use_frame(res);
3838 set_ia32_op_type(res, ia32_AddrModeS);
3839 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3845 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3847 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3848 ir_node *block = be_transform_node(get_nodes_block(node));
3849 ir_node *val = get_irn_n(node, 1);
3850 ir_node *new_val = be_transform_node(val);
3851 ia32_code_gen_t *cg = env_cg;
3852 ir_graph *irg = current_ir_graph;
3853 ir_node *res = NULL;
3854 ir_entity *fent = get_ia32_frame_ent(node);
3855 ir_mode *lsmode = get_ia32_ls_mode(node);
3857 ir_node *noreg, *new_ptr, *new_mem;
3861 if (! USE_SSE2(cg)) {
3862 /* SSE unit is not used -> skip this node. */
3866 ptr = get_irn_n(node, 0);
3867 new_ptr = be_transform_node(ptr);
3868 mem = get_irn_n(node, 2);
3869 new_mem = be_transform_node(mem);
3870 noreg = ia32_new_NoReg_gp(cg);
3871 dbgi = get_irn_dbg_info(node);
3873 /* Store SSE -> MEM */
3874 if (is_ia32_xLoad(skip_Proj(new_val))) {
3875 ir_node *ld = skip_Proj(new_val);
3877 /* we can vfld the value directly into the fpu */
3878 fent = get_ia32_frame_ent(ld);
3879 ptr = get_irn_n(ld, 0);
3880 offs = get_ia32_am_offs_int(ld);
3882 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3883 set_ia32_frame_ent(res, fent);
3884 set_ia32_use_frame(res);
3885 set_ia32_ls_mode(res, lsmode);
3886 set_ia32_op_type(res, ia32_AddrModeD);
3890 /* Load MEM -> x87 */
3891 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3892 set_ia32_frame_ent(res, fent);
3893 set_ia32_use_frame(res);
3894 add_ia32_am_offs_int(res, offs);
3895 set_ia32_op_type(res, ia32_AddrModeS);
3896 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3901 /*********************************************************
3904 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3905 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3906 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3907 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3909 *********************************************************/
3912 * the BAD transformer.
3914 static ir_node *bad_transform(ir_node *node) {
3915 panic("No transform function for %+F available.\n", node);
3920 * Transform the Projs of an AddSP.
3922 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3923 ir_node *block = be_transform_node(get_nodes_block(node));
3924 ir_node *pred = get_Proj_pred(node);
3925 ir_node *new_pred = be_transform_node(pred);
3926 ir_graph *irg = current_ir_graph;
3927 dbg_info *dbgi = get_irn_dbg_info(node);
3928 long proj = get_Proj_proj(node);
3930 if (proj == pn_be_AddSP_sp) {
3931 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3932 pn_ia32_SubSP_stack);
3933 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3935 } else if(proj == pn_be_AddSP_res) {
3936 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3937 pn_ia32_SubSP_addr);
3938 } else if (proj == pn_be_AddSP_M) {
3939 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3943 return new_rd_Unknown(irg, get_irn_mode(node));
3947 * Transform the Projs of a SubSP.
3949 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3950 ir_node *block = be_transform_node(get_nodes_block(node));
3951 ir_node *pred = get_Proj_pred(node);
3952 ir_node *new_pred = be_transform_node(pred);
3953 ir_graph *irg = current_ir_graph;
3954 dbg_info *dbgi = get_irn_dbg_info(node);
3955 long proj = get_Proj_proj(node);
3957 if (proj == pn_be_SubSP_sp) {
3958 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3959 pn_ia32_AddSP_stack);
3960 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3962 } else if (proj == pn_be_SubSP_M) {
3963 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3967 return new_rd_Unknown(irg, get_irn_mode(node));
3971 * Transform and renumber the Projs from a Load.
3973 static ir_node *gen_Proj_Load(ir_node *node) {
3975 ir_node *block = be_transform_node(get_nodes_block(node));
3976 ir_node *pred = get_Proj_pred(node);
3977 ir_graph *irg = current_ir_graph;
3978 dbg_info *dbgi = get_irn_dbg_info(node);
3979 long proj = get_Proj_proj(node);
3982 /* loads might be part of source address mode matches, so we don't
3983 transform the ProjMs yet (with the exception of loads whose result is
3986 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
3989 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
3991 /* this is needed, because sometimes we have loops that are only
3992 reachable through the ProjM */
3993 be_enqueue_preds(node);
3994 /* do it in 2 steps, to silence firm verifier */
3995 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
3996 set_Proj_proj(res, pn_ia32_Load_M);
4000 /* renumber the proj */
4001 new_pred = be_transform_node(pred);
4002 if (is_ia32_Load(new_pred)) {
4003 if (proj == pn_Load_res) {
4004 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4006 } else if (proj == pn_Load_M) {
4007 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4010 } else if(is_ia32_Conv_I2I(new_pred)) {
4011 set_irn_mode(new_pred, mode_T);
4012 if (proj == pn_Load_res) {
4013 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, 0);
4014 } else if (proj == pn_Load_M) {
4015 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4017 } else if (is_ia32_xLoad(new_pred)) {
4018 if (proj == pn_Load_res) {
4019 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4021 } else if (proj == pn_Load_M) {
4022 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4025 } else if (is_ia32_vfld(new_pred)) {
4026 if (proj == pn_Load_res) {
4027 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4029 } else if (proj == pn_Load_M) {
4030 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4034 /* can happen for ProJMs when source address mode happened for the
4037 /* however it should not be the result proj, as that would mean the
4038 load had multiple users and should not have been used for
4040 if(proj != pn_Load_M) {
4041 panic("internal error: transformed node not a Load");
4043 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4047 return new_rd_Unknown(irg, get_irn_mode(node));
4051 * Transform and renumber the Projs from a DivMod like instruction.
4053 static ir_node *gen_Proj_DivMod(ir_node *node) {
4054 ir_node *block = be_transform_node(get_nodes_block(node));
4055 ir_node *pred = get_Proj_pred(node);
4056 ir_node *new_pred = be_transform_node(pred);
4057 ir_graph *irg = current_ir_graph;
4058 dbg_info *dbgi = get_irn_dbg_info(node);
4059 ir_mode *mode = get_irn_mode(node);
4060 long proj = get_Proj_proj(node);
4062 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4064 switch (get_irn_opcode(pred)) {
4068 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4070 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4078 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4080 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4088 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4089 case pn_DivMod_res_div:
4090 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4091 case pn_DivMod_res_mod:
4092 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4102 return new_rd_Unknown(irg, mode);
4106 * Transform and renumber the Projs from a CopyB.
4108 static ir_node *gen_Proj_CopyB(ir_node *node) {
4109 ir_node *block = be_transform_node(get_nodes_block(node));
4110 ir_node *pred = get_Proj_pred(node);
4111 ir_node *new_pred = be_transform_node(pred);
4112 ir_graph *irg = current_ir_graph;
4113 dbg_info *dbgi = get_irn_dbg_info(node);
4114 ir_mode *mode = get_irn_mode(node);
4115 long proj = get_Proj_proj(node);
4118 case pn_CopyB_M_regular:
4119 if (is_ia32_CopyB_i(new_pred)) {
4120 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4121 } else if (is_ia32_CopyB(new_pred)) {
4122 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4130 return new_rd_Unknown(irg, mode);
4134 * Transform and renumber the Projs from a vfdiv.
4136 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
4137 ir_node *block = be_transform_node(get_nodes_block(node));
4138 ir_node *pred = get_Proj_pred(node);
4139 ir_node *new_pred = be_transform_node(pred);
4140 ir_graph *irg = current_ir_graph;
4141 dbg_info *dbgi = get_irn_dbg_info(node);
4142 ir_mode *mode = get_irn_mode(node);
4143 long proj = get_Proj_proj(node);
4146 case pn_ia32_l_vfdiv_M:
4147 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4148 case pn_ia32_l_vfdiv_res:
4149 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4154 return new_rd_Unknown(irg, mode);
4158 * Transform and renumber the Projs from a Quot.
4160 static ir_node *gen_Proj_Quot(ir_node *node) {
4161 ir_node *block = be_transform_node(get_nodes_block(node));
4162 ir_node *pred = get_Proj_pred(node);
4163 ir_node *new_pred = be_transform_node(pred);
4164 ir_graph *irg = current_ir_graph;
4165 dbg_info *dbgi = get_irn_dbg_info(node);
4166 ir_mode *mode = get_irn_mode(node);
4167 long proj = get_Proj_proj(node);
4171 if (is_ia32_xDiv(new_pred)) {
4172 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4173 } else if (is_ia32_vfdiv(new_pred)) {
4174 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4178 if (is_ia32_xDiv(new_pred)) {
4179 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4180 } else if (is_ia32_vfdiv(new_pred)) {
4181 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4189 return new_rd_Unknown(irg, mode);
4193 * Transform the Thread Local Storage Proj.
4195 static ir_node *gen_Proj_tls(ir_node *node) {
4196 ir_node *block = be_transform_node(get_nodes_block(node));
4197 ir_graph *irg = current_ir_graph;
4198 dbg_info *dbgi = NULL;
4199 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4205 * Transform the Projs from a be_Call.
4207 static ir_node *gen_Proj_be_Call(ir_node *node) {
4208 ir_node *block = be_transform_node(get_nodes_block(node));
4209 ir_node *call = get_Proj_pred(node);
4210 ir_node *new_call = be_transform_node(call);
4211 ir_graph *irg = current_ir_graph;
4212 dbg_info *dbgi = get_irn_dbg_info(node);
4213 ir_type *method_type = be_Call_get_type(call);
4214 int n_res = get_method_n_ress(method_type);
4215 long proj = get_Proj_proj(node);
4216 ir_mode *mode = get_irn_mode(node);
4218 const arch_register_class_t *cls;
4220 /* The following is kinda tricky: If we're using SSE, then we have to
4221 * move the result value of the call in floating point registers to an
4222 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4223 * after the call, we have to make sure to correctly make the
4224 * MemProj and the result Proj use these 2 nodes
4226 if (proj == pn_be_Call_M_regular) {
4227 // get new node for result, are we doing the sse load/store hack?
4228 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4229 ir_node *call_res_new;
4230 ir_node *call_res_pred = NULL;
4232 if (call_res != NULL) {
4233 call_res_new = be_transform_node(call_res);
4234 call_res_pred = get_Proj_pred(call_res_new);
4237 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4238 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4239 pn_be_Call_M_regular);
4241 assert(is_ia32_xLoad(call_res_pred));
4242 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4246 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4247 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4248 && USE_SSE2(env_cg)) {
4250 ir_node *frame = get_irg_frame(irg);
4251 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4253 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4256 /* in case there is no memory output: create one to serialize the copy
4258 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4259 pn_be_Call_M_regular);
4260 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4261 pn_be_Call_first_res);
4263 /* store st(0) onto stack */
4264 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_res,
4266 set_ia32_op_type(fstp, ia32_AddrModeD);
4267 set_ia32_use_frame(fstp);
4269 /* load into SSE register */
4270 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4272 set_ia32_op_type(sse_load, ia32_AddrModeS);
4273 set_ia32_use_frame(sse_load);
4275 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4281 /* transform call modes */
4282 if (mode_is_data(mode)) {
4283 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4287 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4291 * Transform the Projs from a Cmp.
4293 static ir_node *gen_Proj_Cmp(ir_node *node)
4295 /* normally Cmps are processed when looking at Cond nodes, but this case
4296 * can happen in complicated Psi conditions */
4298 ir_node *cmp = get_Proj_pred(node);
4299 long pnc = get_Proj_proj(node);
4300 ir_node *cmp_left = get_Cmp_left(cmp);
4301 ir_node *cmp_right = get_Cmp_right(cmp);
4302 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4303 dbg_info *dbgi = get_irn_dbg_info(cmp);
4304 ir_node *block = get_nodes_block(node);
4308 assert(!mode_is_float(cmp_mode));
4310 if(!mode_is_signed(cmp_mode)) {
4311 pnc |= ia32_pn_Cmp_Unsigned;
4315 * address mode makes only sense when we'll be the only node using the cmp
4317 use_am = get_irn_n_edges(cmp) <= 1;
4319 res = create_set(pnc, cmp_left, cmp_right, dbgi, block, use_am);
4320 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
4326 * Transform and potentially renumber Proj nodes.
4328 static ir_node *gen_Proj(ir_node *node) {
4329 ir_graph *irg = current_ir_graph;
4330 dbg_info *dbgi = get_irn_dbg_info(node);
4331 ir_node *pred = get_Proj_pred(node);
4332 long proj = get_Proj_proj(node);
4334 if (is_Store(pred)) {
4335 if (proj == pn_Store_M) {
4336 return be_transform_node(pred);
4339 return new_r_Bad(irg);
4341 } else if (is_Load(pred)) {
4342 return gen_Proj_Load(node);
4343 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4344 return gen_Proj_DivMod(node);
4345 } else if (is_CopyB(pred)) {
4346 return gen_Proj_CopyB(node);
4347 } else if (is_Quot(pred)) {
4348 return gen_Proj_Quot(node);
4349 } else if (is_ia32_l_vfdiv(pred)) {
4350 return gen_Proj_l_vfdiv(node);
4351 } else if (be_is_SubSP(pred)) {
4352 return gen_Proj_be_SubSP(node);
4353 } else if (be_is_AddSP(pred)) {
4354 return gen_Proj_be_AddSP(node);
4355 } else if (be_is_Call(pred)) {
4356 return gen_Proj_be_Call(node);
4357 } else if (is_Cmp(pred)) {
4358 return gen_Proj_Cmp(node);
4359 } else if (get_irn_op(pred) == op_Start) {
4360 if (proj == pn_Start_X_initial_exec) {
4361 ir_node *block = get_nodes_block(pred);
4364 /* we exchange the ProjX with a jump */
4365 block = be_transform_node(block);
4366 jump = new_rd_Jmp(dbgi, irg, block);
4369 if (node == be_get_old_anchor(anchor_tls)) {
4370 return gen_Proj_tls(node);
4373 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4377 ir_node *new_pred = be_transform_node(pred);
4378 ir_node *block = be_transform_node(get_nodes_block(node));
4379 ir_mode *mode = get_irn_mode(node);
4380 if (mode_needs_gp_reg(mode)) {
4381 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4382 get_Proj_proj(node));
4383 #ifdef DEBUG_libfirm
4384 new_proj->node_nr = node->node_nr;
4390 return be_duplicate_node(node);
4394 * Enters all transform functions into the generic pointer
4396 static void register_transformers(void)
4400 /* first clear the generic function pointer for all ops */
4401 clear_irp_opcodes_generic_func();
4403 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4404 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4441 /* transform ops from intrinsic lowering */
4465 GEN(ia32_l_X87toSSE);
4466 GEN(ia32_l_SSEtoX87);
4472 /* we should never see these nodes */
4487 /* handle generic backend nodes */
4495 op_Mulh = get_op_Mulh();
4504 * Pre-transform all unknown and noreg nodes.
4506 static void ia32_pretransform_node(void *arch_cg) {
4507 ia32_code_gen_t *cg = arch_cg;
4509 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4510 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4511 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4512 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4513 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4514 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4519 * Walker, checks if all ia32 nodes producing more than one result have
4520 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4523 void add_missing_keep_walker(ir_node *node, void *data)
4526 unsigned found_projs = 0;
4527 const ir_edge_t *edge;
4528 ir_mode *mode = get_irn_mode(node);
4533 if(!is_ia32_irn(node))
4536 n_outs = get_ia32_n_res(node);
4539 if(is_ia32_SwitchJmp(node))
4542 assert(n_outs < (int) sizeof(unsigned) * 8);
4543 foreach_out_edge(node, edge) {
4544 ir_node *proj = get_edge_src_irn(edge);
4545 int pn = get_Proj_proj(proj);
4547 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4548 found_projs |= 1 << pn;
4552 /* are keeps missing? */
4554 for(i = 0; i < n_outs; ++i) {
4557 const arch_register_req_t *req;
4558 const arch_register_class_t *class;
4560 if(found_projs & (1 << i)) {
4564 req = get_ia32_out_req(node, i);
4570 block = get_nodes_block(node);
4571 in[0] = new_r_Proj(current_ir_graph, block, node,
4572 arch_register_class_mode(class), i);
4573 if(last_keep != NULL) {
4574 be_Keep_add_node(last_keep, class, in[0]);
4576 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4582 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4586 void add_missing_keeps(ia32_code_gen_t *cg)
4588 ir_graph *irg = be_get_birg_irg(cg->birg);
4589 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4592 /* do the transformation */
4593 void ia32_transform_graph(ia32_code_gen_t *cg) {
4594 register_transformers();
4596 initial_fpcw = NULL;
4598 heights = heights_new(cg->irg);
4600 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4602 heights_free(heights);
4604 add_missing_keeps(cg);
4607 void ia32_init_transform(void)
4609 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");