2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
30 #include "archop.h" /* we need this for Min and Max nodes */
37 #include "../benode_t.h"
38 #include "../besched.h"
40 #include "../beutil.h"
41 #include "../beirg_t.h"
43 #include "bearch_ia32_t.h"
44 #include "ia32_nodes_attr.h"
45 #include "ia32_transform.h"
46 #include "ia32_new_nodes.h"
47 #include "ia32_map_regs.h"
48 #include "ia32_dbg_stat.h"
49 #include "ia32_optimize.h"
50 #include "ia32_util.h"
52 #include "gen_ia32_regalloc_if.h"
54 #define SFP_SIGN "0x80000000"
55 #define DFP_SIGN "0x8000000000000000"
56 #define SFP_ABS "0x7FFFFFFF"
57 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
59 #define TP_SFP_SIGN "ia32_sfp_sign"
60 #define TP_DFP_SIGN "ia32_dfp_sign"
61 #define TP_SFP_ABS "ia32_sfp_abs"
62 #define TP_DFP_ABS "ia32_dfp_abs"
64 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
65 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
66 #define ENT_SFP_ABS "IA32_SFP_ABS"
67 #define ENT_DFP_ABS "IA32_DFP_ABS"
69 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
70 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
72 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
74 typedef struct ia32_transform_env_t {
75 ir_graph *irg; /**< The irg, the node should be created in */
76 ia32_code_gen_t *cg; /**< The code generator */
77 int visited; /**< visited count that indicates whether a
78 node is already transformed */
79 pdeq *worklist; /**< worklist of nodes that still need to be
81 ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/
82 } ia32_transform_env_t;
84 extern ir_op *get_op_Mulh(void);
86 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
87 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
88 ir_node *op2, ir_node *mem);
90 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
91 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
94 typedef ir_node *(transform_func)(ia32_transform_env_t *env, ir_node *node);
96 /****************************************************************************************************
98 * | | | | / _| | | (_)
99 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
100 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
101 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
102 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
104 ****************************************************************************************************/
106 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node);
107 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node);
108 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
111 static INLINE int mode_needs_gp_reg(ir_mode *mode)
113 if(mode == mode_fpcw)
116 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
119 static INLINE void set_new_node(ir_node *old_node, ir_node *new_node)
121 set_irn_link(old_node, new_node);
124 static INLINE ir_node *get_new_node(ir_node *old_node)
126 assert(irn_visited(old_node));
127 return (ir_node*) get_irn_link(old_node);
131 * Returns 1 if irn is a Const representing 0, 0 otherwise
133 static INLINE int is_ia32_Const_0(ir_node *irn) {
134 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
135 && tarval_is_null(get_ia32_Immop_tarval(irn));
139 * Returns 1 if irn is a Const representing 1, 0 otherwise
141 static INLINE int is_ia32_Const_1(ir_node *irn) {
142 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
143 && tarval_is_one(get_ia32_Immop_tarval(irn));
147 * Collects all Projs of a node into the node array. Index is the projnum.
148 * BEWARE: The caller has to assure the appropriate array size!
150 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
151 const ir_edge_t *edge;
152 assert(get_irn_mode(irn) == mode_T && "need mode_T");
154 memset(projs, 0, size * sizeof(projs[0]));
156 foreach_out_edge(irn, edge) {
157 ir_node *proj = get_edge_src_irn(edge);
158 int proj_proj = get_Proj_proj(proj);
159 assert(proj_proj < size);
160 projs[proj_proj] = proj;
165 * Renumbers the proj having pn_old in the array tp pn_new
166 * and removes the proj from the array.
168 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
169 fprintf(stderr, "Warning: renumber_Proj used!\n");
171 set_Proj_proj(projs[pn_old], pn_new);
172 projs[pn_old] = NULL;
177 * creates a unique ident by adding a number to a tag
179 * @param tag the tag string, must contain a %d if a number
182 static ident *unique_id(const char *tag)
184 static unsigned id = 0;
187 snprintf(str, sizeof(str), tag, ++id);
188 return new_id_from_str(str);
192 * Get a primitive type for a mode.
194 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
196 pmap_entry *e = pmap_find(types, mode);
201 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
202 res = new_type_primitive(new_id_from_str(buf), mode);
203 pmap_insert(types, mode, res);
211 * Get an entity that is initialized with a tarval
213 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
215 tarval *tv = get_Const_tarval(cnst);
216 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
221 ir_mode *mode = get_irn_mode(cnst);
222 ir_type *tp = get_Const_type(cnst);
223 if (tp == firm_unknown_type)
224 tp = get_prim_type(cg->isa->types, mode);
226 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
228 set_entity_ld_ident(res, get_entity_ident(res));
229 set_entity_visibility(res, visibility_local);
230 set_entity_variability(res, variability_constant);
231 set_entity_allocation(res, allocation_static);
233 /* we create a new entity here: It's initialization must resist on the
235 rem = current_ir_graph;
236 current_ir_graph = get_const_code_irg();
237 set_atomic_ent_value(res, new_Const_type(tv, tp));
238 current_ir_graph = rem;
240 pmap_insert(cg->isa->tv_ent, tv, res);
249 * Transforms a Const.
251 static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) {
252 ir_graph *irg = env->irg;
253 dbg_info *dbgi = get_irn_dbg_info(node);
254 ir_mode *mode = get_irn_mode(node);
255 ir_node *block = transform_node(env, get_nodes_block(node));
257 if (mode_is_float(mode)) {
260 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
261 ir_node *nomem = new_NoMem();
265 if (! USE_SSE2(env->cg)) {
266 cnst_classify_t clss = classify_Const(node);
268 if (clss == CNST_NULL) {
269 load = new_rd_ia32_vfldz(dbgi, irg, block);
271 } else if (clss == CNST_ONE) {
272 load = new_rd_ia32_vfld1(dbgi, irg, block);
275 floatent = get_entity_for_tv(env->cg, node);
277 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem);
278 set_ia32_am_support(load, ia32_am_Source);
279 set_ia32_op_type(load, ia32_AddrModeS);
280 set_ia32_am_flavour(load, ia32_am_N);
281 set_ia32_am_sc(load, floatent);
282 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
284 set_ia32_ls_mode(load, mode);
286 floatent = get_entity_for_tv(env->cg, node);
288 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
289 set_ia32_am_support(load, ia32_am_Source);
290 set_ia32_op_type(load, ia32_AddrModeS);
291 set_ia32_am_flavour(load, ia32_am_N);
292 set_ia32_am_sc(load, floatent);
293 set_ia32_ls_mode(load, mode);
295 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
298 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
300 /* Const Nodes before the initial IncSP are a bad idea, because
301 * they could be spilled and we have no SP ready at that point yet
303 if (get_irg_start_block(irg) == block) {
304 add_irn_dep(load, get_irg_frame(irg));
307 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
310 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
313 if (get_irg_start_block(irg) == block) {
314 add_irn_dep(cnst, get_irg_frame(irg));
317 set_ia32_Const_attr(cnst, node);
318 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
323 return new_r_Bad(irg);
327 * Transforms a SymConst.
329 static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) {
330 ir_graph *irg = env->irg;
331 dbg_info *dbgi = get_irn_dbg_info(node);
332 ir_mode *mode = get_irn_mode(node);
333 ir_node *block = transform_node(env, get_nodes_block(node));
336 if (mode_is_float(mode)) {
338 if (USE_SSE2(env->cg))
339 cnst = new_rd_ia32_xConst(dbgi, irg, block);
341 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
342 set_ia32_ls_mode(cnst, mode);
344 cnst = new_rd_ia32_Const(dbgi, irg, block);
347 /* Const Nodes before the initial IncSP are a bad idea, because
348 * they could be spilled and we have no SP ready at that point yet
350 if (get_irg_start_block(irg) == block) {
351 add_irn_dep(cnst, get_irg_frame(irg));
354 set_ia32_Const_attr(cnst, node);
355 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
361 * SSE convert of an integer node into a floating point node.
363 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbgi,
364 ir_graph *irg, ir_node *block,
365 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
367 ir_node *noreg = ia32_new_NoReg_gp(cg);
368 ir_node *nomem = new_rd_NoMem(irg);
369 ir_node *old_pred = get_Cmp_left(old_node);
370 ir_mode *in_mode = get_irn_mode(old_pred);
371 int in_bits = get_mode_size_bits(in_mode);
373 ir_node *conv = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, in, nomem);
374 set_ia32_ls_mode(conv, tgt_mode);
376 set_ia32_am_support(conv, ia32_am_Source);
378 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
384 * SSE convert of an float node into a double node.
386 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbgi,
387 ir_graph *irg, ir_node *block,
388 ir_node *in, ir_node *old_node)
390 ir_node *noreg = ia32_new_NoReg_gp(cg);
391 ir_node *nomem = new_rd_NoMem(irg);
393 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, in, nomem);
394 set_ia32_am_support(conv, ia32_am_Source);
395 set_ia32_ls_mode(conv, mode_xmm);
396 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
401 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
402 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
403 static const struct {
405 const char *ent_name;
406 const char *cnst_str;
407 } names [ia32_known_const_max] = {
408 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
409 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
410 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
411 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
413 static ir_entity *ent_cache[ia32_known_const_max];
415 const char *tp_name, *ent_name, *cnst_str;
423 ent_name = names[kct].ent_name;
424 if (! ent_cache[kct]) {
425 tp_name = names[kct].tp_name;
426 cnst_str = names[kct].cnst_str;
428 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
430 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
431 tp = new_type_primitive(new_id_from_str(tp_name), mode);
432 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
434 set_entity_ld_ident(ent, get_entity_ident(ent));
435 set_entity_visibility(ent, visibility_local);
436 set_entity_variability(ent, variability_constant);
437 set_entity_allocation(ent, allocation_static);
439 /* we create a new entity here: It's initialization must resist on the
441 rem = current_ir_graph;
442 current_ir_graph = get_const_code_irg();
443 cnst = new_Const(mode, tv);
444 current_ir_graph = rem;
446 set_atomic_ent_value(ent, cnst);
448 /* cache the entry */
449 ent_cache[kct] = ent;
452 return ent_cache[kct];
457 * Prints the old node name on cg obst and returns a pointer to it.
459 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
460 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
462 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
463 obstack_1grow(isa->name_obst, 0);
464 return obstack_finish(isa->name_obst);
468 /* determine if one operator is an Imm */
469 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
471 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
473 return is_ia32_Cnst(op2) ? op2 : NULL;
477 /* determine if one operator is not an Imm */
478 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
479 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
482 static void fold_immediate(ia32_transform_env_t *env, ir_node *node, int in1, int in2) {
486 if(! (env->cg->opt & IA32_OPT_IMMOPS))
489 left = get_irn_n(node, in1);
490 right = get_irn_n(node, in2);
491 if(!is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
492 /* we can only set right operand to immediate */
493 if(!is_ia32_commutative(node))
495 /* exchange left/right */
496 set_irn_n(node, in1, right);
497 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
498 copy_ia32_Immop_attr(node, left);
499 } else if(is_ia32_Cnst(right)) {
500 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
501 copy_ia32_Immop_attr(node, right);
506 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
510 * Construct a standard binary operation, set AM and immediate if required.
512 * @param env The transformation environment
513 * @param op1 The first operand
514 * @param op2 The second operand
515 * @param func The node constructor function
516 * @return The constructed ia32 node.
518 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *node,
519 ir_node *op1, ir_node *op2,
520 construct_binop_func *func) {
521 ir_node *new_node = NULL;
522 ir_graph *irg = env->irg;
523 dbg_info *dbgi = get_irn_dbg_info(node);
524 ir_node *block = transform_node(env, get_nodes_block(node));
525 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
526 ir_node *nomem = new_NoMem();
527 ir_node *new_op1 = transform_node(env, op1);
528 ir_node *new_op2 = transform_node(env, op2);
530 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
531 if(func == new_rd_ia32_IMul) {
532 set_ia32_am_support(new_node, ia32_am_Source);
534 set_ia32_am_support(new_node, ia32_am_Full);
537 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
538 if (is_op_commutative(get_irn_op(node))) {
539 set_ia32_commutative(new_node);
541 fold_immediate(env, new_node, 2, 3);
547 * Construct a standard binary operation, set AM and immediate if required.
549 * @param env The transformation environment
550 * @param op1 The first operand
551 * @param op2 The second operand
552 * @param func The node constructor function
553 * @return The constructed ia32 node.
555 static ir_node *gen_binop_float(ia32_transform_env_t *env, ir_node *node,
556 ir_node *op1, ir_node *op2,
557 construct_binop_func *func)
559 ir_node *new_node = NULL;
560 dbg_info *dbgi = get_irn_dbg_info(node);
561 ir_graph *irg = env->irg;
562 ir_mode *mode = get_irn_mode(node);
563 ir_node *block = transform_node(env, get_nodes_block(node));
564 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
565 ir_node *nomem = new_NoMem();
566 ir_node *new_op1 = transform_node(env, op1);
567 ir_node *new_op2 = transform_node(env, op2);
569 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
570 set_ia32_am_support(new_node, ia32_am_Source);
571 if (is_op_commutative(get_irn_op(node))) {
572 set_ia32_commutative(new_node);
574 if (USE_SSE2(env->cg)) {
575 set_ia32_ls_mode(new_node, mode);
578 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
585 * Construct a shift/rotate binary operation, sets AM and immediate if required.
587 * @param env The transformation environment
588 * @param op1 The first operand
589 * @param op2 The second operand
590 * @param func The node constructor function
591 * @return The constructed ia32 node.
593 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node,
594 ir_node *op1, ir_node *op2,
595 construct_binop_func *func) {
596 ir_node *new_op = NULL;
597 dbg_info *dbgi = get_irn_dbg_info(node);
598 ir_graph *irg = env->irg;
599 ir_node *block = transform_node(env, get_nodes_block(node));
600 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
601 ir_node *nomem = new_NoMem();
604 ir_node *new_op1 = transform_node(env, op1);
605 ir_node *new_op2 = transform_node(env, op2);
608 assert(! mode_is_float(get_irn_mode(node))
609 && "Shift/Rotate with float not supported");
611 /* Check if immediate optimization is on and */
612 /* if it's an operation with immediate. */
613 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
614 expr_op = get_expr_op(new_op1, new_op2);
616 assert((expr_op || imm_op) && "invalid operands");
619 /* We have two consts here: not yet supported */
623 /* Limit imm_op within range imm8 */
625 tv = get_ia32_Immop_tarval(imm_op);
628 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
629 set_ia32_Immop_tarval(imm_op, tv);
636 /* integer operations */
638 /* This is shift/rot with const */
639 DB((dbg, LEVEL_1, "Shift/Rot with immediate ..."));
641 new_op = func(dbgi, irg, block, noreg, noreg, expr_op, noreg, nomem);
642 copy_ia32_Immop_attr(new_op, imm_op);
644 /* This is a normal shift/rot */
645 DB((dbg, LEVEL_1, "Shift/Rot binop ..."));
646 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
650 set_ia32_am_support(new_op, ia32_am_Dest);
652 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
654 set_ia32_emit_cl(new_op);
661 * Construct a standard unary operation, set AM and immediate if required.
663 * @param env The transformation environment
664 * @param op The operand
665 * @param func The node constructor function
666 * @return The constructed ia32 node.
668 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *node, ir_node *op,
669 construct_unop_func *func) {
670 ir_node *new_node = NULL;
671 ir_graph *irg = env->irg;
672 dbg_info *dbgi = get_irn_dbg_info(node);
673 ir_node *block = transform_node(env, get_nodes_block(node));
674 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
675 ir_node *nomem = new_NoMem();
676 ir_node *new_op = transform_node(env, op);
678 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
679 DB((dbg, LEVEL_1, "INT unop ..."));
680 set_ia32_am_support(new_node, ia32_am_Dest);
682 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
689 * Creates an ia32 Add.
691 * @param env The transformation environment
692 * @return the created ia32 Add node
694 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) {
695 ir_node *new_op = NULL;
696 ir_graph *irg = env->irg;
697 dbg_info *dbgi = get_irn_dbg_info(node);
698 ir_mode *mode = get_irn_mode(node);
699 ir_node *block = transform_node(env, get_nodes_block(node));
700 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
701 ir_node *nomem = new_NoMem();
702 ir_node *expr_op, *imm_op;
703 ir_node *op1 = get_Add_left(node);
704 ir_node *op2 = get_Add_right(node);
705 ir_node *new_op1 = transform_node(env, op1);
706 ir_node *new_op2 = transform_node(env, op2);
708 /* Check if immediate optimization is on and */
709 /* if it's an operation with immediate. */
710 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
711 expr_op = get_expr_op(new_op1, new_op2);
713 assert((expr_op || imm_op) && "invalid operands");
715 if (mode_is_float(mode)) {
717 if (USE_SSE2(env->cg))
718 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xAdd);
720 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfadd);
725 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
726 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
728 /* No expr_op means, that we have two const - one symconst and */
729 /* one tarval or another symconst - because this case is not */
730 /* covered by constant folding */
731 /* We need to check for: */
732 /* 1) symconst + const -> becomes a LEA */
733 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
734 /* linker doesn't support two symconsts */
736 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
737 /* this is the 2nd case */
738 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
739 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
740 set_ia32_am_flavour(new_op, ia32_am_OB);
741 set_ia32_am_support(new_op, ia32_am_Source);
742 set_ia32_op_type(new_op, ia32_AddrModeS);
744 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
745 } else if (tp1 == ia32_ImmSymConst) {
746 tarval *tv = get_ia32_Immop_tarval(new_op2);
747 long offs = get_tarval_long(tv);
749 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
750 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
752 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
753 add_ia32_am_offs_int(new_op, offs);
754 set_ia32_am_flavour(new_op, ia32_am_O);
755 set_ia32_am_support(new_op, ia32_am_Source);
756 set_ia32_op_type(new_op, ia32_AddrModeS);
757 } else if (tp2 == ia32_ImmSymConst) {
758 tarval *tv = get_ia32_Immop_tarval(new_op1);
759 long offs = get_tarval_long(tv);
761 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
762 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
764 add_ia32_am_offs_int(new_op, offs);
765 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
766 set_ia32_am_flavour(new_op, ia32_am_O);
767 set_ia32_am_support(new_op, ia32_am_Source);
768 set_ia32_op_type(new_op, ia32_AddrModeS);
770 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
771 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
772 tarval *restv = tarval_add(tv1, tv2);
774 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
776 new_op = new_rd_ia32_Const(dbgi, irg, block);
777 set_ia32_Const_tarval(new_op, restv);
778 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
781 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
784 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
785 tarval_classification_t class_tv, class_negtv;
786 tarval *tv = get_ia32_Immop_tarval(imm_op);
788 /* optimize tarvals */
789 class_tv = classify_tarval(tv);
790 class_negtv = classify_tarval(tarval_neg(tv));
792 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
793 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
794 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
795 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
797 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
798 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
799 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
800 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
806 /* This is a normal add */
807 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
810 set_ia32_am_support(new_op, ia32_am_Full);
811 set_ia32_commutative(new_op);
813 fold_immediate(env, new_op, 2, 3);
815 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
821 static ir_node *create_ia32_Mul(ia32_transform_env_t *env, ir_node *node) {
822 ir_graph *irg = env->irg;
823 dbg_info *dbgi = get_irn_dbg_info(node);
824 ir_node *block = transform_node(env, get_nodes_block(node));
825 ir_node *op1 = get_Mul_left(node);
826 ir_node *op2 = get_Mul_right(node);
827 ir_node *new_op1 = transform_node(env, op1);
828 ir_node *new_op2 = transform_node(env, op2);
829 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
830 ir_node *proj_EAX, *proj_EDX, *res;
833 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
834 set_ia32_commutative(res);
835 set_ia32_am_support(res, ia32_am_Source);
837 /* imediates are not supported, so no fold_immediate */
838 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
839 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
843 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
851 * Creates an ia32 Mul.
853 * @param env The transformation environment
854 * @return the created ia32 Mul node
856 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) {
857 ir_node *op1 = get_Mul_left(node);
858 ir_node *op2 = get_Mul_right(node);
859 ir_mode *mode = get_irn_mode(node);
861 if (mode_is_float(mode)) {
863 if (USE_SSE2(env->cg))
864 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul);
866 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul);
869 // for the lower 32bit of the result it doesn't matter whether we use
870 // signed or unsigned multiplication so we use IMul as it has fewer
872 return gen_binop(env, node, op1, op2, new_rd_ia32_IMul);
876 * Creates an ia32 Mulh.
877 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
878 * this result while Mul returns the lower 32 bit.
880 * @param env The transformation environment
881 * @return the created ia32 Mulh node
883 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) {
884 ir_graph *irg = env->irg;
885 dbg_info *dbgi = get_irn_dbg_info(node);
886 ir_node *block = transform_node(env, get_nodes_block(node));
887 ir_node *op1 = get_irn_n(node, 0);
888 ir_node *op2 = get_irn_n(node, 1);
889 ir_node *new_op1 = transform_node(env, op1);
890 ir_node *new_op2 = transform_node(env, op2);
891 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
892 ir_node *proj_EAX, *proj_EDX, *res;
893 ir_mode *mode = get_irn_mode(node);
896 assert(!mode_is_float(mode) && "Mulh with float not supported");
897 if(mode_is_signed(mode)) {
898 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
900 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
903 set_ia32_commutative(res);
904 set_ia32_am_support(res, ia32_am_Source);
906 set_ia32_am_support(res, ia32_am_Source);
908 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
909 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
913 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
921 * Creates an ia32 And.
923 * @param env The transformation environment
924 * @return The created ia32 And node
926 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *node) {
927 ir_node *op1 = get_And_left(node);
928 ir_node *op2 = get_And_right(node);
930 assert (! mode_is_float(get_irn_mode(node)));
931 return gen_binop(env, node, op1, op2, new_rd_ia32_And);
937 * Creates an ia32 Or.
939 * @param env The transformation environment
940 * @return The created ia32 Or node
942 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *node) {
943 ir_node *op1 = get_Or_left(node);
944 ir_node *op2 = get_Or_right(node);
946 assert (! mode_is_float(get_irn_mode(node)));
947 return gen_binop(env, node, op1, op2, new_rd_ia32_Or);
953 * Creates an ia32 Eor.
955 * @param env The transformation environment
956 * @return The created ia32 Eor node
958 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *node) {
959 ir_node *op1 = get_Eor_left(node);
960 ir_node *op2 = get_Eor_right(node);
962 assert(! mode_is_float(get_irn_mode(node)));
963 return gen_binop(env, node, op1, op2, new_rd_ia32_Xor);
969 * Creates an ia32 Max.
971 * @param env The transformation environment
972 * @return the created ia32 Max node
974 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *node) {
975 ir_graph *irg = env->irg;
977 ir_mode *mode = get_irn_mode(node);
978 dbg_info *dbgi = get_irn_dbg_info(node);
979 ir_node *block = transform_node(env, get_nodes_block(node));
980 ir_node *op1 = get_irn_n(node, 0);
981 ir_node *op2 = get_irn_n(node, 1);
982 ir_node *new_op1 = transform_node(env, op1);
983 ir_node *new_op2 = transform_node(env, op2);
984 ir_mode *op_mode = get_irn_mode(op1);
986 assert(get_mode_size_bits(mode) == 32);
988 if (mode_is_float(mode)) {
990 if (USE_SSE2(env->cg)) {
991 new_op = gen_binop_float(env, node, new_op1, new_op2, new_rd_ia32_xMax);
993 panic("Can't create Max node");
996 long pnc = pn_Cmp_Gt;
997 if(!mode_is_signed(op_mode)) {
998 pnc |= ia32_pn_Cmp_Unsigned;
1000 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1001 set_ia32_pncode(new_op, pnc);
1002 set_ia32_am_support(new_op, ia32_am_None);
1004 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1010 * Creates an ia32 Min.
1012 * @param env The transformation environment
1013 * @return the created ia32 Min node
1015 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *node) {
1016 ir_graph *irg = env->irg;
1018 ir_mode *mode = get_irn_mode(node);
1019 dbg_info *dbgi = get_irn_dbg_info(node);
1020 ir_node *block = transform_node(env, get_nodes_block(node));
1021 ir_node *op1 = get_irn_n(node, 0);
1022 ir_node *op2 = get_irn_n(node, 1);
1023 ir_node *new_op1 = transform_node(env, op1);
1024 ir_node *new_op2 = transform_node(env, op2);
1025 ir_mode *op_mode = get_irn_mode(op1);
1027 assert(get_mode_size_bits(mode) == 32);
1029 if (mode_is_float(mode)) {
1031 if (USE_SSE2(env->cg)) {
1032 new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMin);
1034 panic("can't create Min node");
1037 long pnc = pn_Cmp_Lt;
1038 if(!mode_is_signed(op_mode)) {
1039 pnc |= ia32_pn_Cmp_Unsigned;
1041 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1042 set_ia32_pncode(new_op, pnc);
1043 set_ia32_am_support(new_op, ia32_am_None);
1045 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1052 * Creates an ia32 Sub.
1054 * @param env The transformation environment
1055 * @return The created ia32 Sub node
1057 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) {
1058 ir_node *new_op = NULL;
1059 ir_graph *irg = env->irg;
1060 dbg_info *dbgi = get_irn_dbg_info(node);
1061 ir_mode *mode = get_irn_mode(node);
1062 ir_node *block = transform_node(env, get_nodes_block(node));
1063 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1064 ir_node *nomem = new_NoMem();
1065 ir_node *op1 = get_Sub_left(node);
1066 ir_node *op2 = get_Sub_right(node);
1067 ir_node *new_op1 = transform_node(env, op1);
1068 ir_node *new_op2 = transform_node(env, op2);
1069 ir_node *expr_op, *imm_op;
1071 /* Check if immediate optimization is on and */
1072 /* if it's an operation with immediate. */
1073 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1074 expr_op = get_expr_op(new_op1, new_op2);
1076 assert((expr_op || imm_op) && "invalid operands");
1078 if (mode_is_float(mode)) {
1080 if (USE_SSE2(env->cg))
1081 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xSub);
1083 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfsub);
1088 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1089 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1091 /* No expr_op means, that we have two const - one symconst and */
1092 /* one tarval or another symconst - because this case is not */
1093 /* covered by constant folding */
1094 /* We need to check for: */
1095 /* 1) symconst - const -> becomes a LEA */
1096 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1097 /* linker doesn't support two symconsts */
1098 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1099 /* this is the 2nd case */
1100 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1101 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1102 set_ia32_am_sc_sign(new_op);
1103 set_ia32_am_flavour(new_op, ia32_am_OB);
1105 DBG_OPT_LEA3(op1, op2, node, new_op);
1106 } else if (tp1 == ia32_ImmSymConst) {
1107 tarval *tv = get_ia32_Immop_tarval(new_op2);
1108 long offs = get_tarval_long(tv);
1110 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1111 DBG_OPT_LEA3(op1, op2, node, new_op);
1113 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1114 add_ia32_am_offs_int(new_op, -offs);
1115 set_ia32_am_flavour(new_op, ia32_am_O);
1116 set_ia32_am_support(new_op, ia32_am_Source);
1117 set_ia32_op_type(new_op, ia32_AddrModeS);
1118 } else if (tp2 == ia32_ImmSymConst) {
1119 tarval *tv = get_ia32_Immop_tarval(new_op1);
1120 long offs = get_tarval_long(tv);
1122 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1123 DBG_OPT_LEA3(op1, op2, node, new_op);
1125 add_ia32_am_offs_int(new_op, offs);
1126 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1127 set_ia32_am_sc_sign(new_op);
1128 set_ia32_am_flavour(new_op, ia32_am_O);
1129 set_ia32_am_support(new_op, ia32_am_Source);
1130 set_ia32_op_type(new_op, ia32_AddrModeS);
1132 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1133 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1134 tarval *restv = tarval_sub(tv1, tv2);
1136 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1138 new_op = new_rd_ia32_Const(dbgi, irg, block);
1139 set_ia32_Const_tarval(new_op, restv);
1140 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1143 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1145 } else if (imm_op) {
1146 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1147 tarval_classification_t class_tv, class_negtv;
1148 tarval *tv = get_ia32_Immop_tarval(imm_op);
1150 /* optimize tarvals */
1151 class_tv = classify_tarval(tv);
1152 class_negtv = classify_tarval(tarval_neg(tv));
1154 if (class_tv == TV_CLASSIFY_ONE) {
1155 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1156 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1157 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1159 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1160 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1161 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1162 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1168 /* This is a normal sub */
1169 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1171 /* set AM support */
1172 set_ia32_am_support(new_op, ia32_am_Full);
1174 fold_immediate(env, new_op, 2, 3);
1176 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1184 * Generates an ia32 DivMod with additional infrastructure for the
1185 * register allocator if needed.
1187 * @param env The transformation environment
1188 * @param dividend -no comment- :)
1189 * @param divisor -no comment- :)
1190 * @param dm_flav flavour_Div/Mod/DivMod
1191 * @return The created ia32 DivMod node
1193 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *node,
1194 ir_node *dividend, ir_node *divisor,
1195 ia32_op_flavour_t dm_flav) {
1196 ir_graph *irg = env->irg;
1197 dbg_info *dbgi = get_irn_dbg_info(node);
1198 ir_mode *mode = get_irn_mode(node);
1199 ir_node *block = transform_node(env, get_nodes_block(node));
1200 ir_node *res, *proj_div, *proj_mod;
1201 ir_node *edx_node, *cltd;
1202 ir_node *in_keep[1];
1203 ir_node *mem, *new_mem;
1204 ir_node *projs[pn_DivMod_max];
1205 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1206 ir_node *new_dividend = transform_node(env, dividend);
1207 ir_node *new_divisor = transform_node(env, divisor);
1209 ia32_collect_Projs(node, projs, pn_DivMod_max);
1213 mem = get_Div_mem(node);
1214 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Div_res));
1217 mem = get_Mod_mem(node);
1218 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Mod_res));
1220 case flavour_DivMod:
1221 mem = get_DivMod_mem(node);
1222 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1223 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1224 mode = proj_div ? get_irn_mode(proj_div) : get_irn_mode(proj_mod);
1227 panic("invalid divmod flavour!");
1229 new_mem = transform_node(env, mem);
1231 if (mode_is_signed(mode)) {
1232 /* in signed mode, we need to sign extend the dividend */
1233 cltd = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1234 new_dividend = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1235 edx_node = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1237 edx_node = new_rd_ia32_Const(dbgi, irg, block);
1238 add_irn_dep(edx_node, be_abi_get_start_barrier(env->cg->birg->abi));
1239 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1242 if(mode_is_signed(mode)) {
1243 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1245 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1248 /* Matze: code can't handle this at the moment... */
1250 /* set AM support */
1251 set_ia32_am_support(res, ia32_am_Source);
1254 set_ia32_n_res(res, 2);
1256 /* Only one proj is used -> We must add a second proj and */
1257 /* connect this one to a Keep node to eat up the second */
1258 /* destroyed register. */
1259 /* We also renumber the Firm projs into ia32 projs. */
1261 switch (get_irn_opcode(node)) {
1263 /* add Proj-Keep for mod res */
1264 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1265 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1268 /* add Proj-Keep for div res */
1269 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1270 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1273 /* check, which Proj-Keep, we need to add */
1274 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1275 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1277 if (proj_div && proj_mod) {
1278 /* nothing to be done */
1280 else if (! proj_div && ! proj_mod) {
1281 assert(0 && "Missing DivMod result proj");
1283 else if (! proj_div) {
1284 /* We have only mod result: add div res Proj-Keep */
1285 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1286 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1289 /* We have only div result: add mod res Proj-Keep */
1290 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1291 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1295 assert(0 && "Div, Mod, or DivMod expected.");
1299 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1306 * Wrapper for generate_DivMod. Sets flavour_Mod.
1308 * @param env The transformation environment
1310 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *node) {
1311 return generate_DivMod(env, node, get_Mod_left(node),
1312 get_Mod_right(node), flavour_Mod);
1316 * Wrapper for generate_DivMod. Sets flavour_Div.
1318 * @param env The transformation environment
1320 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *node) {
1321 return generate_DivMod(env, node, get_Div_left(node),
1322 get_Div_right(node), flavour_Div);
1326 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1328 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *node) {
1329 return generate_DivMod(env, node, get_DivMod_left(node),
1330 get_DivMod_right(node), flavour_DivMod);
1336 * Creates an ia32 floating Div.
1338 * @param env The transformation environment
1339 * @return The created ia32 xDiv node
1341 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *node) {
1342 ir_graph *irg = env->irg;
1343 dbg_info *dbgi = get_irn_dbg_info(node);
1344 ir_node *block = transform_node(env, get_nodes_block(node));
1345 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1347 ir_node *nomem = new_rd_NoMem(env->irg);
1348 ir_node *op1 = get_Quot_left(node);
1349 ir_node *op2 = get_Quot_right(node);
1350 ir_node *new_op1 = transform_node(env, op1);
1351 ir_node *new_op2 = transform_node(env, op2);
1354 if (USE_SSE2(env->cg)) {
1355 ir_mode *mode = get_irn_mode(op1);
1356 if (is_ia32_xConst(new_op2)) {
1357 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1358 set_ia32_am_support(new_op, ia32_am_None);
1359 copy_ia32_Immop_attr(new_op, new_op2);
1361 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1362 // Matze: disabled for now, spillslot coalescer fails
1363 //set_ia32_am_support(new_op, ia32_am_Source);
1365 set_ia32_ls_mode(new_op, mode);
1367 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1368 // Matze: disabled for now (spillslot coalescer fails)
1369 //set_ia32_am_support(new_op, ia32_am_Source);
1371 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1377 * Creates an ia32 Shl.
1379 * @param env The transformation environment
1380 * @return The created ia32 Shl node
1382 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *node) {
1383 return gen_shift_binop(env, node, get_Shl_left(node), get_Shl_right(node),
1390 * Creates an ia32 Shr.
1392 * @param env The transformation environment
1393 * @return The created ia32 Shr node
1395 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *node) {
1396 return gen_shift_binop(env, node, get_Shr_left(node),
1397 get_Shr_right(node), new_rd_ia32_Shr);
1403 * Creates an ia32 Sar.
1405 * @param env The transformation environment
1406 * @return The created ia32 Shrs node
1408 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) {
1409 return gen_shift_binop(env, node, get_Shrs_left(node),
1410 get_Shrs_right(node), new_rd_ia32_Sar);
1416 * Creates an ia32 RotL.
1418 * @param env The transformation environment
1419 * @param op1 The first operator
1420 * @param op2 The second operator
1421 * @return The created ia32 RotL node
1423 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node,
1424 ir_node *op1, ir_node *op2) {
1425 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Rol);
1431 * Creates an ia32 RotR.
1432 * NOTE: There is no RotR with immediate because this would always be a RotL
1433 * "imm-mode_size_bits" which can be pre-calculated.
1435 * @param env The transformation environment
1436 * @param op1 The first operator
1437 * @param op2 The second operator
1438 * @return The created ia32 RotR node
1440 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1,
1442 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Ror);
1448 * Creates an ia32 RotR or RotL (depending on the found pattern).
1450 * @param env The transformation environment
1451 * @return The created ia32 RotL or RotR node
1453 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) {
1454 ir_node *rotate = NULL;
1455 ir_node *op1 = get_Rot_left(node);
1456 ir_node *op2 = get_Rot_right(node);
1458 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1459 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1460 that means we can create a RotR instead of an Add and a RotL */
1462 if (get_irn_op(op2) == op_Add) {
1464 ir_node *left = get_Add_left(add);
1465 ir_node *right = get_Add_right(add);
1466 if (is_Const(right)) {
1467 tarval *tv = get_Const_tarval(right);
1468 ir_mode *mode = get_irn_mode(node);
1469 long bits = get_mode_size_bits(mode);
1471 if (get_irn_op(left) == op_Minus &&
1472 tarval_is_long(tv) &&
1473 get_tarval_long(tv) == bits)
1475 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1476 rotate = gen_RotR(env, node, op1, get_Minus_op(left));
1481 if (rotate == NULL) {
1482 rotate = gen_RotL(env, node, op1, op2);
1491 * Transforms a Minus node.
1493 * @param env The transformation environment
1494 * @param op The Minus operand
1495 * @return The created ia32 Minus node
1497 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *node, ir_node *op) {
1500 ir_graph *irg = env->irg;
1501 dbg_info *dbgi = get_irn_dbg_info(node);
1502 ir_node *block = transform_node(env, get_nodes_block(node));
1503 ir_mode *mode = get_irn_mode(node);
1506 if (mode_is_float(mode)) {
1507 ir_node *new_op = transform_node(env, op);
1509 if (USE_SSE2(env->cg)) {
1510 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1511 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1512 ir_node *nomem = new_rd_NoMem(irg);
1514 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1516 size = get_mode_size_bits(mode);
1517 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1519 set_ia32_am_sc(res, ent);
1520 set_ia32_op_type(res, ia32_AddrModeS);
1521 set_ia32_ls_mode(res, mode);
1523 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1526 res = gen_unop(env, node, op, new_rd_ia32_Neg);
1529 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1535 * Transforms a Minus node.
1537 * @param env The transformation environment
1538 * @return The created ia32 Minus node
1540 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *node) {
1541 return gen_Minus_ex(env, node, get_Minus_op(node));
1546 * Transforms a Not node.
1548 * @param env The transformation environment
1549 * @return The created ia32 Not node
1551 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *node) {
1552 ir_node *op = get_Not_op(node);
1554 assert (! mode_is_float(get_irn_mode(node)));
1555 return gen_unop(env, node, op, new_rd_ia32_Not);
1561 * Transforms an Abs node.
1563 * @param env The transformation environment
1564 * @return The created ia32 Abs node
1566 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *node) {
1567 ir_node *res, *p_eax, *p_edx;
1568 ir_graph *irg = env->irg;
1569 dbg_info *dbgi = get_irn_dbg_info(node);
1570 ir_node *block = transform_node(env, get_nodes_block(node));
1571 ir_mode *mode = get_irn_mode(node);
1572 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1573 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1574 ir_node *nomem = new_NoMem();
1575 ir_node *op = get_Abs_op(node);
1576 ir_node *new_op = transform_node(env, op);
1580 if (mode_is_float(mode)) {
1582 if (USE_SSE2(env->cg)) {
1583 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1585 size = get_mode_size_bits(mode);
1586 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1588 set_ia32_am_sc(res, ent);
1590 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1592 set_ia32_op_type(res, ia32_AddrModeS);
1593 set_ia32_ls_mode(res, mode);
1596 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1597 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1601 res = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1602 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1604 p_eax = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
1605 p_edx = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1607 res = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1608 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1610 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1611 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1620 * Transforms a Load.
1622 * @param env The transformation environment
1623 * @return the created ia32 Load node
1625 static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) {
1626 ir_graph *irg = env->irg;
1627 dbg_info *dbgi = get_irn_dbg_info(node);
1628 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1629 ir_mode *mode = get_Load_mode(node);
1630 ir_node *block = transform_node(env, get_nodes_block(node));
1631 ir_node *ptr = get_Load_ptr(node);
1632 ir_node *new_ptr = transform_node(env, ptr);
1633 ir_node *lptr = new_ptr;
1634 ir_node *mem = get_Load_mem(node);
1635 ir_node *new_mem = transform_node(env, mem);
1638 ia32_am_flavour_t am_flav = ia32_am_B;
1639 ir_node *projs[pn_Load_max];
1641 ia32_collect_Projs(node, projs, pn_Load_max);
1644 check for special case: the loaded value might not be used (optimized, volatile, ...)
1645 we add a Proj + Keep for volatile loads and ignore all other cases
1647 if (! be_get_Proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1648 /* add a result proj and a Keep to produce a pseudo use */
1649 ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res);
1650 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), irg, block, 1, &proj);
1653 /* address might be a constant (symconst or absolute address) */
1654 if (is_ia32_Const(new_ptr)) {
1659 if (mode_is_float(mode)) {
1661 if (USE_SSE2(env->cg)) {
1662 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1664 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem);
1667 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1670 /* base is a constant address */
1672 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1673 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1674 am_flav = ia32_am_N;
1676 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1677 long offs = get_tarval_long(tv);
1679 add_ia32_am_offs_int(new_op, offs);
1680 am_flav = ia32_am_O;
1684 set_ia32_am_support(new_op, ia32_am_Source);
1685 set_ia32_op_type(new_op, ia32_AddrModeS);
1686 set_ia32_am_flavour(new_op, am_flav);
1687 set_ia32_ls_mode(new_op, mode);
1689 /* make sure we are scheduled behind the intial IncSP/Barrier
1690 * to avoid spills being placed before it
1692 if(block == get_irg_start_block(irg)) {
1693 add_irn_dep(new_op, get_irg_frame(irg));
1696 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1704 * Transforms a Store.
1706 * @param env The transformation environment
1707 * @return the created ia32 Store node
1709 static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) {
1710 ir_graph *irg = env->irg;
1711 dbg_info *dbgi = get_irn_dbg_info(node);
1712 ir_node *block = transform_node(env, get_nodes_block(node));
1713 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1714 ir_node *ptr = get_Store_ptr(node);
1715 ir_node *new_ptr = transform_node(env, ptr);
1716 ir_node *sptr = new_ptr;
1717 ir_node *val = get_Store_value(node);
1718 ir_node *new_val = transform_node(env, val);
1719 ir_node *mem = get_Store_mem(node);
1720 ir_node *new_mem = transform_node(env, mem);
1721 ir_mode *mode = get_irn_mode(val);
1722 ir_node *sval = new_val;
1725 ia32_am_flavour_t am_flav = ia32_am_B;
1727 if (is_ia32_Const(new_val)) {
1728 assert(!mode_is_float(mode));
1732 /* address might be a constant (symconst or absolute address) */
1733 if (is_ia32_Const(new_ptr)) {
1738 if (mode_is_float(mode)) {
1740 if (USE_SSE2(env->cg)) {
1741 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, sval, new_mem);
1743 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, sval, new_mem);
1745 } else if (get_mode_size_bits(mode) == 8) {
1746 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg, sval, new_mem);
1748 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, sval, new_mem);
1751 /* stored const is an immediate value */
1752 if (is_ia32_Const(new_val)) {
1753 assert(!mode_is_float(mode));
1754 copy_ia32_Immop_attr(new_op, new_val);
1757 /* base is an constant address */
1759 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1760 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1761 am_flav = ia32_am_N;
1763 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1764 long offs = get_tarval_long(tv);
1766 add_ia32_am_offs_int(new_op, offs);
1767 am_flav = ia32_am_O;
1771 set_ia32_am_support(new_op, ia32_am_Dest);
1772 set_ia32_op_type(new_op, ia32_AddrModeD);
1773 set_ia32_am_flavour(new_op, am_flav);
1774 set_ia32_ls_mode(new_op, mode);
1776 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1784 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1786 * @param env The transformation environment
1787 * @return The transformed node.
1789 static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) {
1790 ir_graph *irg = env->irg;
1791 dbg_info *dbgi = get_irn_dbg_info(node);
1792 ir_node *block = transform_node(env, get_nodes_block(node));
1793 ir_node *sel = get_Cond_selector(node);
1794 ir_mode *sel_mode = get_irn_mode(sel);
1795 ir_node *res = NULL;
1796 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1797 ir_node *cnst, *expr;
1799 if (is_Proj(sel) && sel_mode == mode_b) {
1800 ir_node *nomem = new_NoMem();
1801 ir_node *pred = get_Proj_pred(sel);
1802 ir_node *cmp_a = get_Cmp_left(pred);
1803 ir_node *new_cmp_a = transform_node(env, cmp_a);
1804 ir_node *cmp_b = get_Cmp_right(pred);
1805 ir_node *new_cmp_b = transform_node(env, cmp_b);
1806 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1808 int pnc = get_Proj_proj(sel);
1809 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1810 pnc |= ia32_pn_Cmp_Unsigned;
1813 /* check if we can use a CondJmp with immediate */
1814 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1815 expr = get_expr_op(new_cmp_a, new_cmp_b);
1817 if (cnst != NULL && expr != NULL) {
1818 /* immop has to be the right operand, we might need to flip pnc */
1819 if(cnst != new_cmp_b) {
1820 pnc = get_inversed_pnc(pnc);
1823 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_needs_gp_reg(get_irn_mode(expr))) {
1824 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1825 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1827 /* a Cmp A =/!= 0 */
1828 ir_node *op1 = expr;
1829 ir_node *op2 = expr;
1832 /* check, if expr is an only once used And operation */
1833 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1834 op1 = get_irn_n(expr, 2);
1835 op2 = get_irn_n(expr, 3);
1837 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1839 res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2);
1840 set_ia32_pncode(res, pnc);
1843 copy_ia32_Immop_attr(res, expr);
1846 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1851 if (mode_is_float(cmp_mode)) {
1853 if (USE_SSE2(env->cg)) {
1854 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1855 set_ia32_ls_mode(res, cmp_mode);
1861 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1863 copy_ia32_Immop_attr(res, cnst);
1866 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1868 if (mode_is_float(cmp_mode)) {
1870 if (USE_SSE2(env->cg)) {
1871 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1872 set_ia32_ls_mode(res, cmp_mode);
1875 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1876 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1877 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1881 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1882 set_ia32_commutative(res);
1886 set_ia32_pncode(res, pnc);
1887 // Matze: disabled for now, because the default collect_spills_walker
1888 // is not able to detect the mode of the spilled value
1889 // moreover, the lea optimize phase freely exchanges left/right
1890 // without updating the pnc
1891 //set_ia32_am_support(res, ia32_am_Source);
1894 /* determine the smallest switch case value */
1895 int switch_min = INT_MAX;
1896 const ir_edge_t *edge;
1897 ir_node *new_sel = transform_node(env, sel);
1899 foreach_out_edge(node, edge) {
1900 int pn = get_Proj_proj(get_edge_src_irn(edge));
1901 switch_min = pn < switch_min ? pn : switch_min;
1905 /* if smallest switch case is not 0 we need an additional sub */
1906 res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1907 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1908 add_ia32_am_offs_int(res, -switch_min);
1909 set_ia32_am_flavour(res, ia32_am_OB);
1910 set_ia32_am_support(res, ia32_am_Source);
1911 set_ia32_op_type(res, ia32_AddrModeS);
1914 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T);
1915 set_ia32_pncode(res, get_Cond_defaultProj(node));
1918 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1925 * Transforms a CopyB node.
1927 * @param env The transformation environment
1928 * @return The transformed node.
1930 static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) {
1931 ir_node *res = NULL;
1932 ir_graph *irg = env->irg;
1933 dbg_info *dbgi = get_irn_dbg_info(node);
1934 ir_node *block = transform_node(env, get_nodes_block(node));
1935 ir_node *src = get_CopyB_src(node);
1936 ir_node *new_src = transform_node(env, src);
1937 ir_node *dst = get_CopyB_dst(node);
1938 ir_node *new_dst = transform_node(env, dst);
1939 ir_node *mem = get_CopyB_mem(node);
1940 ir_node *new_mem = transform_node(env, mem);
1941 int size = get_type_size_bytes(get_CopyB_type(node));
1942 ir_mode *dst_mode = get_irn_mode(dst);
1943 ir_mode *src_mode = get_irn_mode(src);
1947 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1948 /* then we need the size explicitly in ECX. */
1949 if (size >= 32 * 4) {
1950 rem = size & 0x3; /* size % 4 */
1953 res = new_rd_ia32_Const(dbgi, irg, block);
1954 add_irn_dep(res, be_abi_get_start_barrier(env->cg->birg->abi));
1955 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1957 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1958 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1960 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1961 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1962 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1963 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1964 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1967 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1968 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1970 /* ok: now attach Proj's because movsd will destroy esi and edi */
1971 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1972 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1973 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1976 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1984 * Transforms a Mux node into CMov.
1986 * @param env The transformation environment
1987 * @return The transformed node.
1989 static ir_node *gen_Mux(ia32_transform_env_t *env, ir_node *node) {
1990 ir_node *new_op = new_rd_ia32_CMov(env->dbgi, env->irg, env->block, \
1991 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1993 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1999 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
2000 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
2001 ir_node *psi_default);
2004 * Transforms a Psi node into CMov.
2006 * @param env The transformation environment
2007 * @return The transformed node.
2009 static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) {
2010 ia32_code_gen_t *cg = env->cg;
2011 ir_graph *irg = env->irg;
2012 dbg_info *dbgi = get_irn_dbg_info(node);
2013 ir_mode *mode = get_irn_mode(node);
2014 ir_node *block = transform_node(env, get_nodes_block(node));
2015 ir_node *cmp_proj = get_Mux_sel(node);
2016 ir_node *psi_true = get_Psi_val(node, 0);
2017 ir_node *psi_default = get_Psi_default(node);
2018 ir_node *new_psi_true = transform_node(env, psi_true);
2019 ir_node *new_psi_default = transform_node(env, psi_default);
2020 ir_node *noreg = ia32_new_NoReg_gp(cg);
2021 ir_node *nomem = new_rd_NoMem(irg);
2022 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
2023 ir_node *new_cmp_a, *new_cmp_b;
2027 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
2029 cmp = get_Proj_pred(cmp_proj);
2030 cmp_a = get_Cmp_left(cmp);
2031 cmp_b = get_Cmp_right(cmp);
2032 cmp_mode = get_irn_mode(cmp_a);
2033 new_cmp_a = transform_node(env, cmp_a);
2034 new_cmp_b = transform_node(env, cmp_b);
2036 pnc = get_Proj_proj(cmp_proj);
2037 if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2038 pnc |= ia32_pn_Cmp_Unsigned;
2041 if (mode_is_float(mode)) {
2042 /* floating point psi */
2045 /* 1st case: compare operands are float too */
2047 /* psi(cmp(a, b), t, f) can be done as: */
2048 /* tmp = cmp a, b */
2049 /* tmp2 = t and tmp */
2050 /* tmp3 = f and not tmp */
2051 /* res = tmp2 or tmp3 */
2053 /* in case the compare operands are int, we move them into xmm register */
2054 if (! mode_is_float(get_irn_mode(cmp_a))) {
2055 new_cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_a, node, mode_xmm);
2056 new_cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_b, node, mode_xmm);
2058 pnc |= 8; /* transform integer compare to fp compare */
2061 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2062 set_ia32_pncode(new_op, pnc);
2063 set_ia32_am_support(new_op, ia32_am_Source);
2064 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2066 and1 = new_rd_ia32_xAnd(dbgi, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2067 set_ia32_am_support(and1, ia32_am_None);
2068 set_ia32_commutative(and1);
2069 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2071 and2 = new_rd_ia32_xAndNot(dbgi, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2072 set_ia32_am_support(and2, ia32_am_None);
2073 set_ia32_commutative(and2);
2074 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2076 new_op = new_rd_ia32_xOr(dbgi, irg, block, noreg, noreg, and1, and2, nomem);
2077 set_ia32_am_support(new_op, ia32_am_None);
2078 set_ia32_commutative(new_op);
2079 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2083 new_op = new_rd_ia32_vfCMov(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2084 set_ia32_pncode(new_op, pnc);
2085 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2090 construct_binop_func *set_func = NULL;
2091 cmov_func_t *cmov_func = NULL;
2093 if (mode_is_float(get_irn_mode(cmp_a))) {
2094 /* 1st case: compare operands are floats */
2099 set_func = new_rd_ia32_xCmpSet;
2100 cmov_func = new_rd_ia32_xCmpCMov;
2104 set_func = new_rd_ia32_vfCmpSet;
2105 cmov_func = new_rd_ia32_vfCmpCMov;
2108 pnc &= ~0x8; /* fp compare -> int compare */
2111 /* 2nd case: compare operand are integer too */
2112 set_func = new_rd_ia32_CmpSet;
2113 cmov_func = new_rd_ia32_CmpCMov;
2116 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2117 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2118 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2119 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2120 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2121 set_ia32_pncode(new_op, pnc);
2123 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2124 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2125 /* we invert condition and set default to 0 */
2126 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2127 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2130 /* otherwise: use CMOVcc */
2131 new_op = new_rd_ia32_PsiCondCMov(dbgi, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2132 set_ia32_pncode(new_op, pnc);
2135 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2138 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2139 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2140 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2141 set_ia32_pncode(new_op, pnc);
2142 set_ia32_am_support(new_op, ia32_am_Source);
2144 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2145 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2146 /* we invert condition and set default to 0 */
2147 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2148 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2149 set_ia32_am_support(new_op, ia32_am_Source);
2152 /* otherwise: use CMOVcc */
2153 new_op = cmov_func(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2154 set_ia32_pncode(new_op, pnc);
2155 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2165 * Following conversion rules apply:
2169 * 1) n bit -> m bit n > m (downscale)
2171 * 2) n bit -> m bit n == m (sign change)
2173 * 3) n bit -> m bit n < m (upscale)
2174 * a) source is signed: movsx
2175 * b) source is unsigned: and with lower bits sets
2179 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2183 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2187 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2188 * x87 is mode_E internally, conversions happen only at load and store
2189 * in non-strict semantic
2193 * Create a conversion from x87 state register to general purpose.
2195 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) {
2196 ia32_code_gen_t *cg = env->cg;
2197 ir_graph *irg = env->irg;
2198 dbg_info *dbgi = get_irn_dbg_info(node);
2199 ir_node *block = transform_node(env, get_nodes_block(node));
2200 ir_node *noreg = ia32_new_NoReg_gp(cg);
2201 ir_node *op = get_Conv_op(node);
2202 ir_node *new_op = transform_node(env, op);
2203 ir_node *fist, *load;
2204 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2207 fist = new_rd_ia32_vfist(dbgi, irg, block,
2208 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2210 set_ia32_use_frame(fist);
2211 set_ia32_am_support(fist, ia32_am_Dest);
2212 set_ia32_op_type(fist, ia32_AddrModeD);
2213 set_ia32_am_flavour(fist, ia32_am_B);
2214 set_ia32_ls_mode(fist, mode_Iu);
2215 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2218 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2220 set_ia32_use_frame(load);
2221 set_ia32_am_support(load, ia32_am_Source);
2222 set_ia32_op_type(load, ia32_AddrModeS);
2223 set_ia32_am_flavour(load, ia32_am_B);
2224 set_ia32_ls_mode(load, mode_Iu);
2225 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2227 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2231 * Create a conversion from general purpose to x87 register
2233 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mode *src_mode) {
2235 ia32_code_gen_t *cg = env->cg;
2237 ir_graph *irg = env->irg;
2238 dbg_info *dbgi = get_irn_dbg_info(node);
2239 ir_node *block = transform_node(env, get_nodes_block(node));
2240 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2241 ir_node *nomem = new_NoMem();
2242 ir_node *op = get_Conv_op(node);
2243 ir_node *new_op = transform_node(env, op);
2244 ir_node *fild, *store;
2247 /* first convert to 32 bit if necessary */
2248 src_bits = get_mode_size_bits(src_mode);
2249 if (src_bits == 8) {
2250 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2251 set_ia32_am_support(new_op, ia32_am_Source);
2252 set_ia32_ls_mode(new_op, src_mode);
2253 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2254 } else if (src_bits < 32) {
2255 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2256 set_ia32_am_support(new_op, ia32_am_Source);
2257 set_ia32_ls_mode(new_op, src_mode);
2258 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2262 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2264 set_ia32_use_frame(store);
2265 set_ia32_am_support(store, ia32_am_Dest);
2266 set_ia32_op_type(store, ia32_AddrModeD);
2267 set_ia32_am_flavour(store, ia32_am_OB);
2268 set_ia32_ls_mode(store, mode_Iu);
2271 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2273 set_ia32_use_frame(fild);
2274 set_ia32_am_support(fild, ia32_am_Source);
2275 set_ia32_op_type(fild, ia32_AddrModeS);
2276 set_ia32_am_flavour(fild, ia32_am_OB);
2277 set_ia32_ls_mode(fild, mode_Iu);
2279 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2283 * Transforms a Conv node.
2285 * @param env The transformation environment
2286 * @return The created ia32 Conv node
2288 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) {
2289 ir_graph *irg = env->irg;
2290 dbg_info *dbgi = get_irn_dbg_info(node);
2291 ir_node *op = get_Conv_op(node);
2292 ir_mode *src_mode = get_irn_mode(op);
2293 ir_mode *tgt_mode = get_irn_mode(node);
2294 int src_bits = get_mode_size_bits(src_mode);
2295 int tgt_bits = get_mode_size_bits(tgt_mode);
2296 ir_node *block = transform_node(env, get_nodes_block(node));
2298 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2299 ir_node *nomem = new_rd_NoMem(irg);
2300 ir_node *new_op = transform_node(env, op);
2302 if (src_mode == tgt_mode) {
2303 if (get_Conv_strict(node)) {
2304 if (USE_SSE2(env->cg)) {
2305 /* when we are in SSE mode, we can kill all strict no-op conversion */
2309 /* this should be optimized already, but who knows... */
2310 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2311 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2316 if (mode_is_float(src_mode)) {
2317 /* we convert from float ... */
2318 if (mode_is_float(tgt_mode)) {
2320 if (USE_SSE2(env->cg)) {
2321 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2322 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2323 set_ia32_ls_mode(res, tgt_mode);
2325 // Matze: TODO what about strict convs?
2326 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: strict conv %+F ignored yet\n", node));
2327 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2332 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2333 if (USE_SSE2(env->cg)) {
2334 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2335 set_ia32_ls_mode(res, src_mode);
2337 return gen_x87_fp_to_gp(env, node);
2341 /* we convert from int ... */
2342 if (mode_is_float(tgt_mode)) {
2345 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2346 if (USE_SSE2(env->cg)) {
2347 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2348 set_ia32_ls_mode(res, tgt_mode);
2349 if(src_bits == 32) {
2350 set_ia32_am_support(res, ia32_am_Source);
2353 return gen_x87_gp_to_fp(env, node, src_mode);
2357 ir_mode *smaller_mode;
2360 if (src_bits == tgt_bits) {
2361 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2365 if(src_bits < tgt_bits) {
2366 smaller_mode = src_mode;
2367 smaller_bits = src_bits;
2369 smaller_mode = tgt_mode;
2370 smaller_bits = tgt_bits;
2373 // The following is not correct, we can't change the mode,
2374 // maybe others are using the load too
2375 // better move this to a separate phase!
2378 if(is_Proj(new_op)) {
2379 /* load operations do already sign/zero extend, so we have
2380 * nothing left to do */
2381 ir_node *pred = get_Proj_pred(new_op);
2382 if(is_ia32_Load(pred)) {
2383 set_ia32_ls_mode(pred, smaller_mode);
2389 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2390 if (smaller_bits == 8) {
2391 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2392 set_ia32_ls_mode(res, smaller_mode);
2394 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2395 set_ia32_ls_mode(res, smaller_mode);
2397 set_ia32_am_support(res, ia32_am_Source);
2401 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2408 /********************************************
2411 * | |__ ___ _ __ ___ __| | ___ ___
2412 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2413 * | |_) | __/ | | | (_) | (_| | __/\__ \
2414 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2416 ********************************************/
2418 static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) {
2419 ir_node *new_op = NULL;
2420 ir_graph *irg = env->irg;
2421 dbg_info *dbgi = get_irn_dbg_info(node);
2422 ir_node *block = transform_node(env, get_nodes_block(node));
2423 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2424 ir_node *nomem = new_rd_NoMem(env->irg);
2425 ir_node *ptr = get_irn_n(node, 0);
2426 ir_node *new_ptr = transform_node(env, ptr);
2427 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2428 ir_mode *load_mode = get_irn_mode(node);
2432 if (mode_is_float(load_mode)) {
2434 if (USE_SSE2(env->cg)) {
2435 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2436 pn_res = pn_ia32_xLoad_res;
2437 proj_mode = mode_xmm;
2439 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem);
2440 pn_res = pn_ia32_vfld_res;
2441 proj_mode = mode_vfp;
2444 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2445 proj_mode = mode_Iu;
2446 pn_res = pn_ia32_Load_res;
2449 set_ia32_frame_ent(new_op, ent);
2450 set_ia32_use_frame(new_op);
2452 set_ia32_am_support(new_op, ia32_am_Source);
2453 set_ia32_op_type(new_op, ia32_AddrModeS);
2454 set_ia32_am_flavour(new_op, ia32_am_B);
2455 set_ia32_ls_mode(new_op, load_mode);
2456 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2458 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2460 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2464 * Transforms a FrameAddr into an ia32 Add.
2466 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) {
2467 ir_graph *irg = env->irg;
2468 dbg_info *dbgi = get_irn_dbg_info(node);
2469 ir_node *block = transform_node(env, get_nodes_block(node));
2470 ir_node *op = get_irn_n(node, 0);
2471 ir_node *new_op = transform_node(env, op);
2473 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2475 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2476 set_ia32_frame_ent(res, arch_get_frame_entity(env->cg->arch_env, node));
2477 set_ia32_am_support(res, ia32_am_Full);
2478 set_ia32_use_frame(res);
2479 set_ia32_am_flavour(res, ia32_am_OB);
2481 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2487 * Transforms a FrameLoad into an ia32 Load.
2489 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) {
2490 ir_node *new_op = NULL;
2491 ir_graph *irg = env->irg;
2492 dbg_info *dbgi = get_irn_dbg_info(node);
2493 ir_node *block = transform_node(env, get_nodes_block(node));
2494 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2495 ir_node *mem = get_irn_n(node, 0);
2496 ir_node *ptr = get_irn_n(node, 1);
2497 ir_node *new_mem = transform_node(env, mem);
2498 ir_node *new_ptr = transform_node(env, ptr);
2499 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2500 ir_mode *mode = get_type_mode(get_entity_type(ent));
2501 ir_node *projs[pn_Load_max];
2503 ia32_collect_Projs(node, projs, pn_Load_max);
2505 if (mode_is_float(mode)) {
2507 if (USE_SSE2(env->cg)) {
2508 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2511 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
2515 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2518 set_ia32_frame_ent(new_op, ent);
2519 set_ia32_use_frame(new_op);
2521 set_ia32_am_support(new_op, ia32_am_Source);
2522 set_ia32_op_type(new_op, ia32_AddrModeS);
2523 set_ia32_am_flavour(new_op, ia32_am_B);
2524 set_ia32_ls_mode(new_op, mode);
2526 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2533 * Transforms a FrameStore into an ia32 Store.
2535 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) {
2536 ir_node *new_op = NULL;
2537 ir_graph *irg = env->irg;
2538 dbg_info *dbgi = get_irn_dbg_info(node);
2539 ir_node *block = transform_node(env, get_nodes_block(node));
2540 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2541 ir_node *mem = get_irn_n(node, 0);
2542 ir_node *ptr = get_irn_n(node, 1);
2543 ir_node *val = get_irn_n(node, 2);
2544 ir_node *new_mem = transform_node(env, mem);
2545 ir_node *new_ptr = transform_node(env, ptr);
2546 ir_node *new_val = transform_node(env, val);
2547 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2548 ir_mode *mode = get_irn_mode(val);
2550 if (mode_is_float(mode)) {
2552 if (USE_SSE2(env->cg)) {
2553 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2555 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2557 } else if (get_mode_size_bits(mode) == 8) {
2558 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2560 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2563 set_ia32_frame_ent(new_op, ent);
2564 set_ia32_use_frame(new_op);
2566 set_ia32_am_support(new_op, ia32_am_Dest);
2567 set_ia32_op_type(new_op, ia32_AddrModeD);
2568 set_ia32_am_flavour(new_op, ia32_am_B);
2569 set_ia32_ls_mode(new_op, mode);
2571 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2577 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2579 static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
2580 ir_graph *irg = env->irg;
2583 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2584 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2585 ir_entity *ent = get_irg_entity(irg);
2586 ir_type *tp = get_entity_type(ent);
2589 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2590 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2592 int pn_ret_val, pn_ret_mem, arity, i;
2594 assert(ret_val != NULL);
2595 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env->cg)) {
2596 return duplicate_node(env, node);
2599 res_type = get_method_res_type(tp, 0);
2601 if (!is_Primitive_type(res_type)) {
2602 return duplicate_node(env, node);
2605 mode = get_type_mode(res_type);
2606 if (!mode_is_float(mode)) {
2607 return duplicate_node(env, node);
2610 assert(get_method_n_ress(tp) == 1);
2612 pn_ret_val = get_Proj_proj(ret_val);
2613 pn_ret_mem = get_Proj_proj(ret_mem);
2615 /* get the Barrier */
2616 barrier = get_Proj_pred(ret_val);
2618 /* get result input of the Barrier */
2619 ret_val = get_irn_n(barrier, pn_ret_val);
2620 new_ret_val = transform_node(env, ret_val);
2622 /* get memory input of the Barrier */
2623 ret_mem = get_irn_n(barrier, pn_ret_mem);
2624 new_ret_mem = transform_node(env, ret_mem);
2626 frame = get_irg_frame(irg);
2628 dbgi = get_irn_dbg_info(barrier);
2629 block = transform_node(env, get_nodes_block(barrier));
2631 /* store xmm0 onto stack */
2632 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, new_ret_val, new_ret_mem);
2633 set_ia32_ls_mode(sse_store, mode);
2634 set_ia32_op_type(sse_store, ia32_AddrModeD);
2635 set_ia32_use_frame(sse_store);
2636 set_ia32_am_flavour(sse_store, ia32_am_B);
2637 set_ia32_am_support(sse_store, ia32_am_Dest);
2640 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, sse_store);
2641 set_ia32_ls_mode(fld, mode);
2642 set_ia32_op_type(fld, ia32_AddrModeS);
2643 set_ia32_use_frame(fld);
2644 set_ia32_am_flavour(fld, ia32_am_B);
2645 set_ia32_am_support(fld, ia32_am_Source);
2647 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
2648 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
2649 arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2651 /* create a new barrier */
2652 arity = get_irn_arity(barrier);
2653 in = alloca(arity * sizeof(in[0]));
2654 for(i = 0; i < arity; ++i) {
2656 if(i == pn_ret_val) {
2658 } else if(i == pn_ret_mem) {
2661 ir_node *in = get_irn_n(barrier, i);
2662 new_in = transform_node(env, in);
2667 new_barrier = new_ir_node(dbgi, irg, block,
2668 get_irn_op(barrier), get_irn_mode(barrier),
2670 copy_node_attr(barrier, new_barrier);
2671 duplicate_deps(env, barrier, new_barrier);
2672 set_new_node(barrier, new_barrier);
2673 mark_irn_visited(barrier);
2675 /* transform normally */
2676 return duplicate_node(env, node);
2680 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2682 static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
2684 ir_graph *irg = env->irg;
2685 dbg_info *dbgi = get_irn_dbg_info(node);
2686 ir_node *block = transform_node(env, get_nodes_block(node));
2687 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
2688 ir_node *new_sz = transform_node(env, sz);
2689 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
2690 ir_node *new_sp = transform_node(env, sp);
2691 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2692 ir_node *nomem = new_NoMem();
2694 /* ia32 stack grows in reverse direction, make a SubSP */
2695 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2696 set_ia32_am_support(new_op, ia32_am_Source);
2697 fold_immediate(env, new_op, 2, 3);
2699 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2705 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
2707 static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
2709 ir_graph *irg = env->irg;
2710 dbg_info *dbgi = get_irn_dbg_info(node);
2711 ir_node *block = transform_node(env, get_nodes_block(node));
2712 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
2713 ir_node *new_sz = transform_node(env, sz);
2714 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
2715 ir_node *new_sp = transform_node(env, sp);
2716 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2717 ir_node *nomem = new_NoMem();
2719 /* ia32 stack grows in reverse direction, make an AddSP */
2720 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2721 set_ia32_am_support(new_op, ia32_am_Source);
2722 fold_immediate(env, new_op, 2, 3);
2724 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2730 * This function just sets the register for the Unknown node
2731 * as this is not done during register allocation because Unknown
2732 * is an "ignore" node.
2734 static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) {
2735 ir_mode *mode = get_irn_mode(node);
2737 if (mode_is_float(mode)) {
2738 if (USE_SSE2(env->cg))
2739 return ia32_new_Unknown_xmm(env->cg);
2741 return ia32_new_Unknown_vfp(env->cg);
2742 } else if (mode_needs_gp_reg(mode)) {
2743 return ia32_new_Unknown_gp(env->cg);
2745 assert(0 && "unsupported Unknown-Mode");
2752 * Change some phi modes
2754 static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
2755 ir_graph *irg = env->irg;
2756 dbg_info *dbgi = get_irn_dbg_info(node);
2757 ir_mode *mode = get_irn_mode(node);
2758 ir_node *block = transform_node(env, get_nodes_block(node));
2762 if(mode_needs_gp_reg(mode)) {
2763 // we shouldn't have any 64bit stuff around anymore
2764 assert(get_mode_size_bits(mode) <= 32);
2765 // all integer operations are on 32bit registers now
2767 } else if(mode_is_float(mode)) {
2768 assert(mode == mode_D || mode == mode_F);
2769 if (USE_SSE2(env->cg)) {
2776 /* phi nodes allow loops, so we use the old arguments for now
2777 * and fix this later */
2778 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
2779 get_irn_in(node) + 1);
2780 copy_node_attr(node, phi);
2781 duplicate_deps(env, node, phi);
2783 set_new_node(node, phi);
2785 /* put the preds in the worklist */
2786 arity = get_irn_arity(node);
2787 for(i = 0; i < arity; ++i) {
2788 ir_node *pred = get_irn_n(node, i);
2789 pdeq_putr(env->worklist, pred);
2795 /**********************************************************************
2798 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2799 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2800 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2801 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2803 **********************************************************************/
2805 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2807 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2810 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2811 ir_node *val, ir_node *mem);
2814 * Transforms a lowered Load into a "real" one.
2816 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) {
2817 ir_graph *irg = env->irg;
2818 dbg_info *dbgi = get_irn_dbg_info(node);
2819 ir_node *block = transform_node(env, get_nodes_block(node));
2820 ir_mode *mode = get_ia32_ls_mode(node);
2822 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2823 ir_node *ptr = get_irn_n(node, 0);
2824 ir_node *mem = get_irn_n(node, 1);
2825 ir_node *new_ptr = transform_node(env, ptr);
2826 ir_node *new_mem = transform_node(env, mem);
2829 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2830 lowering we have x87 nodes, so we need to enforce simulation.
2832 if (mode_is_float(mode)) {
2834 if (fp_unit == fp_x87)
2838 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
2840 set_ia32_am_support(new_op, ia32_am_Source);
2841 set_ia32_op_type(new_op, ia32_AddrModeS);
2842 set_ia32_am_flavour(new_op, ia32_am_OB);
2843 set_ia32_am_offs_int(new_op, 0);
2844 set_ia32_am_scale(new_op, 1);
2845 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
2846 if(is_ia32_am_sc_sign(node))
2847 set_ia32_am_sc_sign(new_op);
2848 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
2849 if(is_ia32_use_frame(node)) {
2850 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2851 set_ia32_use_frame(new_op);
2854 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2860 * Transforms a lowered Store into a "real" one.
2862 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) {
2863 ir_graph *irg = env->irg;
2864 dbg_info *dbgi = get_irn_dbg_info(node);
2865 ir_node *block = transform_node(env, get_nodes_block(node));
2866 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2867 ir_mode *mode = get_ia32_ls_mode(node);
2870 ia32_am_flavour_t am_flav = ia32_B;
2871 ir_node *ptr = get_irn_n(node, 0);
2872 ir_node *val = get_irn_n(node, 1);
2873 ir_node *mem = get_irn_n(node, 2);
2874 ir_node *new_ptr = transform_node(env, ptr);
2875 ir_node *new_val = transform_node(env, val);
2876 ir_node *new_mem = transform_node(env, mem);
2879 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2880 lowering we have x87 nodes, so we need to enforce simulation.
2882 if (mode_is_float(mode)) {
2884 if (fp_unit == fp_x87)
2888 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2890 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
2892 add_ia32_am_offs_int(new_op, am_offs);
2895 set_ia32_am_support(new_op, ia32_am_Dest);
2896 set_ia32_op_type(new_op, ia32_AddrModeD);
2897 set_ia32_am_flavour(new_op, am_flav);
2898 set_ia32_ls_mode(new_op, mode);
2899 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2900 set_ia32_use_frame(new_op);
2902 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2909 * Transforms an ia32_l_XXX into a "real" XXX node
2911 * @param env The transformation environment
2912 * @return the created ia32 XXX node
2914 #define GEN_LOWERED_OP(op) \
2915 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2916 ir_mode *mode = get_irn_mode(node); \
2917 if (mode_is_float(mode)) \
2919 return gen_binop(env, node, get_binop_left(node), \
2920 get_binop_right(node), new_rd_ia32_##op); \
2923 #define GEN_LOWERED_x87_OP(op) \
2924 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2926 FORCE_x87(env->cg); \
2927 new_op = gen_binop_float(env, node, get_binop_left(node), \
2928 get_binop_right(node), new_rd_ia32_##op); \
2932 #define GEN_LOWERED_UNOP(op) \
2933 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2934 return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \
2937 #define GEN_LOWERED_SHIFT_OP(op) \
2938 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2939 return gen_shift_binop(env, node, get_binop_left(node), \
2940 get_binop_right(node), new_rd_ia32_##op); \
2943 #define GEN_LOWERED_LOAD(op, fp_unit) \
2944 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2945 return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \
2948 #define GEN_LOWERED_STORE(op, fp_unit) \
2949 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2950 return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \
2957 GEN_LOWERED_OP(IMul)
2959 GEN_LOWERED_x87_OP(vfprem)
2960 GEN_LOWERED_x87_OP(vfmul)
2961 GEN_LOWERED_x87_OP(vfsub)
2963 GEN_LOWERED_UNOP(Neg)
2965 GEN_LOWERED_LOAD(vfild, fp_x87)
2966 GEN_LOWERED_LOAD(Load, fp_none)
2967 /*GEN_LOWERED_STORE(vfist, fp_x87)
2970 GEN_LOWERED_STORE(Store, fp_none)
2972 static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
2973 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2974 ir_graph *irg = env->irg;
2975 dbg_info *dbgi = get_irn_dbg_info(node);
2976 ir_node *block = transform_node(env, get_nodes_block(node));
2977 ir_node *left = get_binop_left(node);
2978 ir_node *right = get_binop_right(node);
2979 ir_node *new_left = transform_node(env, left);
2980 ir_node *new_right = transform_node(env, right);
2983 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
2984 clear_ia32_commutative(vfdiv);
2985 set_ia32_am_support(vfdiv, ia32_am_Source);
2986 fold_immediate(env, vfdiv, 2, 3);
2988 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env->cg, node));
2996 * Transforms a l_MulS into a "real" MulS node.
2998 * @param env The transformation environment
2999 * @return the created ia32 Mul node
3001 static ir_node *gen_ia32_l_Mul(ia32_transform_env_t *env, ir_node *node) {
3002 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3003 ir_graph *irg = env->irg;
3004 dbg_info *dbgi = get_irn_dbg_info(node);
3005 ir_node *block = transform_node(env, get_nodes_block(node));
3006 ir_node *left = get_binop_left(node);
3007 ir_node *right = get_binop_right(node);
3008 ir_node *new_left = transform_node(env, left);
3009 ir_node *new_right = transform_node(env, right);
3012 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3013 /* and then skip the result Proj, because all needed Projs are already there. */
3014 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3015 clear_ia32_commutative(muls);
3016 set_ia32_am_support(muls, ia32_am_Source);
3017 fold_immediate(env, muls, 2, 3);
3019 /* check if EAX and EDX proj exist, add missing one */
3020 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3021 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3022 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3024 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env->cg, node));
3029 GEN_LOWERED_SHIFT_OP(Shl)
3030 GEN_LOWERED_SHIFT_OP(Shr)
3031 GEN_LOWERED_SHIFT_OP(Sar)
3034 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3035 * op1 - target to be shifted
3036 * op2 - contains bits to be shifted into target
3038 * Only op3 can be an immediate.
3040 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *node,
3041 ir_node *op1, ir_node *op2,
3043 ir_node *new_op = NULL;
3044 ir_graph *irg = env->irg;
3045 dbg_info *dbgi = get_irn_dbg_info(node);
3046 ir_node *block = transform_node(env, get_nodes_block(node));
3047 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3048 ir_node *nomem = new_NoMem();
3050 ir_node *new_op1 = transform_node(env, op1);
3051 ir_node *new_op2 = transform_node(env, op2);
3052 ir_node *new_count = transform_node(env, count);
3055 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3057 /* Check if immediate optimization is on and */
3058 /* if it's an operation with immediate. */
3059 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3061 /* Limit imm_op within range imm8 */
3063 tv = get_ia32_Immop_tarval(imm_op);
3066 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3067 set_ia32_Immop_tarval(imm_op, tv);
3074 /* integer operations */
3076 /* This is ShiftD with const */
3077 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3079 if (is_ia32_l_ShlD(node))
3080 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3081 new_op1, new_op2, noreg, nomem);
3083 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3084 new_op1, new_op2, noreg, nomem);
3085 copy_ia32_Immop_attr(new_op, imm_op);
3088 /* This is a normal ShiftD */
3089 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3090 if (is_ia32_l_ShlD(node))
3091 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3092 new_op1, new_op2, new_count, nomem);
3094 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3095 new_op1, new_op2, new_count, nomem);
3098 /* set AM support */
3099 // Matze: node has unsupported format (6inputs)
3100 //set_ia32_am_support(new_op, ia32_am_Dest);
3102 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3104 set_ia32_emit_cl(new_op);
3109 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env, ir_node *node) {
3110 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3111 get_irn_n(node, 1), get_irn_n(node, 2));
3114 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env, ir_node *node) {
3115 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3116 get_irn_n(node, 1), get_irn_n(node, 2));
3120 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3122 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) {
3123 ia32_code_gen_t *cg = env->cg;
3124 ir_node *res = NULL;
3125 ir_graph *irg = env->irg;
3126 dbg_info *dbgi = get_irn_dbg_info(node);
3127 ir_node *block = transform_node(env, get_nodes_block(node));
3128 ir_node *ptr = get_irn_n(node, 0);
3129 ir_node *val = get_irn_n(node, 1);
3130 ir_node *new_val = transform_node(env, val);
3131 ir_node *mem = get_irn_n(node, 2);
3132 ir_node *noreg, *new_ptr, *new_mem;
3138 noreg = ia32_new_NoReg_gp(cg);
3139 new_mem = transform_node(env, mem);
3140 new_ptr = transform_node(env, ptr);
3142 /* Store x87 -> MEM */
3143 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3144 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3145 set_ia32_use_frame(res);
3146 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3147 set_ia32_am_support(res, ia32_am_Dest);
3148 set_ia32_am_flavour(res, ia32_B);
3149 set_ia32_op_type(res, ia32_AddrModeD);
3151 /* Load MEM -> SSE */
3152 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3153 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3154 set_ia32_use_frame(res);
3155 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3156 set_ia32_am_support(res, ia32_am_Source);
3157 set_ia32_am_flavour(res, ia32_B);
3158 set_ia32_op_type(res, ia32_AddrModeS);
3159 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3165 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3167 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) {
3168 ia32_code_gen_t *cg = env->cg;
3169 ir_graph *irg = env->irg;
3170 dbg_info *dbgi = get_irn_dbg_info(node);
3171 ir_node *block = transform_node(env, get_nodes_block(node));
3172 ir_node *res = NULL;
3173 ir_node *ptr = get_irn_n(node, 0);
3174 ir_node *val = get_irn_n(node, 1);
3175 ir_node *mem = get_irn_n(node, 2);
3176 ir_entity *fent = get_ia32_frame_ent(node);
3177 ir_mode *lsmode = get_ia32_ls_mode(node);
3178 ir_node *new_val = transform_node(env, val);
3179 ir_node *noreg, *new_ptr, *new_mem;
3182 if (!USE_SSE2(cg)) {
3183 /* SSE unit is not used -> skip this node. */
3187 noreg = ia32_new_NoReg_gp(cg);
3188 new_val = transform_node(env, val);
3189 new_ptr = transform_node(env, ptr);
3190 new_mem = transform_node(env, mem);
3192 /* Store SSE -> MEM */
3193 if (is_ia32_xLoad(skip_Proj(new_val))) {
3194 ir_node *ld = skip_Proj(new_val);
3196 /* we can vfld the value directly into the fpu */
3197 fent = get_ia32_frame_ent(ld);
3198 ptr = get_irn_n(ld, 0);
3199 offs = get_ia32_am_offs_int(ld);
3201 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3202 set_ia32_frame_ent(res, fent);
3203 set_ia32_use_frame(res);
3204 set_ia32_ls_mode(res, lsmode);
3205 set_ia32_am_support(res, ia32_am_Dest);
3206 set_ia32_am_flavour(res, ia32_B);
3207 set_ia32_op_type(res, ia32_AddrModeD);
3211 /* Load MEM -> x87 */
3212 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
3213 set_ia32_frame_ent(res, fent);
3214 set_ia32_use_frame(res);
3215 set_ia32_ls_mode(res, lsmode);
3216 add_ia32_am_offs_int(res, offs);
3217 set_ia32_am_support(res, ia32_am_Source);
3218 set_ia32_am_flavour(res, ia32_B);
3219 set_ia32_op_type(res, ia32_AddrModeS);
3220 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3225 /*********************************************************
3228 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3229 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3230 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3231 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3233 *********************************************************/
3236 * the BAD transformer.
3238 static ir_node *bad_transform(ia32_transform_env_t *env, ir_node *node) {
3239 panic("No transform function for %+F available.\n", node);
3243 static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) {
3244 /* end has to be duplicated manually because we need a dynamic in array */
3245 ir_graph *irg = env->irg;
3246 dbg_info *dbgi = get_irn_dbg_info(node);
3247 ir_node *block = transform_node(env, get_nodes_block(node));
3251 new_end = new_ir_node(dbgi, irg, block, op_End, mode_X, -1, NULL);
3252 copy_node_attr(node, new_end);
3253 duplicate_deps(env, node, new_end);
3255 set_irg_end(irg, new_end);
3256 set_new_node(new_end, new_end);
3258 /* transform preds */
3259 arity = get_irn_arity(node);
3260 for(i = 0; i < arity; ++i) {
3261 ir_node *in = get_irn_n(node, i);
3262 ir_node *new_in = transform_node(env, in);
3264 add_End_keepalive(new_end, new_in);
3270 static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) {
3271 ir_graph *irg = env->irg;
3272 dbg_info *dbgi = get_irn_dbg_info(node);
3273 ir_node *start_block = env->old_anchors[anchor_start_block];
3278 * We replace the ProjX from the start node with a jump,
3279 * so the startblock has no preds anymore now
3281 if(node == start_block) {
3282 return new_rd_Block(dbgi, irg, 0, NULL);
3285 /* we use the old blocks for now, because jumps allow cycles in the graph
3286 * we have to fix this later */
3287 block = new_ir_node(dbgi, irg, NULL, get_irn_op(node), get_irn_mode(node),
3288 get_irn_arity(node), get_irn_in(node) + 1);
3289 copy_node_attr(node, block);
3291 #ifdef DEBUG_libfirm
3292 block->node_nr = node->node_nr;
3294 set_new_node(node, block);
3296 /* put the preds in the worklist */
3297 arity = get_irn_arity(node);
3298 for(i = 0; i < arity; ++i) {
3299 ir_node *in = get_irn_n(node, i);
3300 pdeq_putr(env->worklist, in);
3306 static ir_node *gen_Proj_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
3307 ir_graph *irg = env->irg;
3308 ir_node *block = transform_node(env, get_nodes_block(node));
3309 dbg_info *dbgi = get_irn_dbg_info(node);
3310 ir_node *pred = get_Proj_pred(node);
3311 ir_node *new_pred = transform_node(env, pred);
3312 long proj = get_Proj_proj(node);
3314 if(proj == pn_be_AddSP_res) {
3315 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3316 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3318 } else if(proj == pn_be_AddSP_M) {
3319 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3323 return new_rd_Unknown(irg, get_irn_mode(node));
3326 static ir_node *gen_Proj_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
3327 ir_graph *irg = env->irg;
3328 ir_node *block = transform_node(env, get_nodes_block(node));
3329 dbg_info *dbgi = get_irn_dbg_info(node);
3330 ir_node *pred = get_Proj_pred(node);
3331 ir_node *new_pred = transform_node(env, pred);
3332 long proj = get_Proj_proj(node);
3334 if(proj == pn_be_SubSP_res) {
3335 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3336 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3338 } else if(proj == pn_be_SubSP_M) {
3339 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3343 return new_rd_Unknown(irg, get_irn_mode(node));
3346 static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) {
3347 ir_graph *irg = env->irg;
3348 ir_node *block = transform_node(env, get_nodes_block(node));
3349 dbg_info *dbgi = get_irn_dbg_info(node);
3350 ir_node *pred = get_Proj_pred(node);
3351 ir_node *new_pred = transform_node(env, pred);
3352 long proj = get_Proj_proj(node);
3354 /* renumber the proj */
3355 if(is_ia32_Load(new_pred)) {
3356 if(proj == pn_Load_res) {
3357 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3358 } else if(proj == pn_Load_M) {
3359 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3361 } else if(is_ia32_xLoad(new_pred)) {
3362 if(proj == pn_Load_res) {
3363 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3364 } else if(proj == pn_Load_M) {
3365 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3367 } else if(is_ia32_vfld(new_pred)) {
3368 if(proj == pn_Load_res) {
3369 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3370 } else if(proj == pn_Load_M) {
3371 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3376 return new_rd_Unknown(irg, get_irn_mode(node));
3379 static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) {
3380 ir_graph *irg = env->irg;
3381 dbg_info *dbgi = get_irn_dbg_info(node);
3382 ir_node *block = transform_node(env, get_nodes_block(node));
3383 ir_mode *mode = get_irn_mode(node);
3385 ir_node *pred = get_Proj_pred(node);
3386 ir_node *new_pred = transform_node(env, pred);
3387 long proj = get_Proj_proj(node);
3389 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3391 switch(get_irn_opcode(pred)) {
3395 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3397 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3405 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3407 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3415 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3416 case pn_DivMod_res_div:
3417 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3418 case pn_DivMod_res_mod:
3419 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3429 return new_rd_Unknown(irg, mode);
3432 static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node)
3434 ir_graph *irg = env->irg;
3435 dbg_info *dbgi = get_irn_dbg_info(node);
3436 ir_node *block = transform_node(env, get_nodes_block(node));
3437 ir_mode *mode = get_irn_mode(node);
3439 ir_node *pred = get_Proj_pred(node);
3440 ir_node *new_pred = transform_node(env, pred);
3441 long proj = get_Proj_proj(node);
3444 case pn_CopyB_M_regular:
3445 if(is_ia32_CopyB_i(new_pred)) {
3446 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3448 } else if(is_ia32_CopyB(new_pred)) {
3449 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3458 return new_rd_Unknown(irg, mode);
3461 static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node)
3463 ir_graph *irg = env->irg;
3464 dbg_info *dbgi = get_irn_dbg_info(node);
3465 ir_node *block = transform_node(env, get_nodes_block(node));
3466 ir_mode *mode = get_irn_mode(node);
3468 ir_node *pred = get_Proj_pred(node);
3469 ir_node *new_pred = transform_node(env, pred);
3470 long proj = get_Proj_proj(node);
3473 case pn_ia32_l_vfdiv_M:
3474 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3475 case pn_ia32_l_vfdiv_res:
3476 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3481 return new_rd_Unknown(irg, mode);
3484 static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node)
3486 ir_graph *irg = env->irg;
3487 dbg_info *dbgi = get_irn_dbg_info(node);
3488 ir_node *block = transform_node(env, get_nodes_block(node));
3489 ir_mode *mode = get_irn_mode(node);
3491 ir_node *pred = get_Proj_pred(node);
3492 ir_node *new_pred = transform_node(env, pred);
3493 long proj = get_Proj_proj(node);
3497 if(is_ia32_xDiv(new_pred)) {
3498 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3500 } else if(is_ia32_vfdiv(new_pred)) {
3501 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3506 if(is_ia32_xDiv(new_pred)) {
3507 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
3509 } else if(is_ia32_vfdiv(new_pred)) {
3510 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
3519 return new_rd_Unknown(irg, mode);
3522 static ir_node *gen_Proj_tls(ia32_transform_env_t *env, ir_node *node) {
3523 ir_graph *irg = env->irg;
3524 //dbg_info *dbgi = get_irn_dbg_info(node);
3525 dbg_info *dbgi = NULL;
3526 ir_node *block = transform_node(env, get_nodes_block(node));
3528 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3533 static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) {
3534 ir_graph *irg = env->irg;
3535 dbg_info *dbgi = get_irn_dbg_info(node);
3536 long proj = get_Proj_proj(node);
3537 ir_mode *mode = get_irn_mode(node);
3538 ir_node *block = transform_node(env, get_nodes_block(node));
3540 ir_node *call = get_Proj_pred(node);
3541 ir_node *new_call = transform_node(env, call);
3542 const arch_register_class_t *cls;
3544 /* The following is kinda tricky: If we're using SSE, then we have to
3545 * move the result value of the call in floating point registers to an
3546 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3547 * after the call, we have to make sure to correctly make the
3548 * MemProj and the result Proj use these 2 nodes
3550 if(proj == pn_be_Call_M_regular) {
3551 // get new node for result, are we doing the sse load/store hack?
3552 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3553 ir_node *call_res_new;
3554 ir_node *call_res_pred = NULL;
3556 if(call_res != NULL) {
3557 call_res_new = transform_node(env, call_res);
3558 call_res_pred = get_Proj_pred(call_res_new);
3561 if(call_res_pred == NULL || be_is_Call(call_res_pred)) {
3562 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3564 assert(is_ia32_xLoad(call_res_pred));
3565 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3568 if(proj == pn_be_Call_first_res && mode_is_float(mode)
3569 && USE_SSE2(env->cg)) {
3571 ir_node *frame = get_irg_frame(irg);
3572 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3574 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3576 const arch_register_class_t *cls;
3578 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3579 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3581 /* store st(0) onto stack */
3582 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3584 set_ia32_ls_mode(fstp, mode);
3585 set_ia32_op_type(fstp, ia32_AddrModeD);
3586 set_ia32_use_frame(fstp);
3587 set_ia32_am_flavour(fstp, ia32_am_B);
3588 set_ia32_am_support(fstp, ia32_am_Dest);
3590 /* load into SSE register */
3591 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3592 set_ia32_ls_mode(sse_load, mode);
3593 set_ia32_op_type(sse_load, ia32_AddrModeS);
3594 set_ia32_use_frame(sse_load);
3595 set_ia32_am_flavour(sse_load, ia32_am_B);
3596 set_ia32_am_support(sse_load, ia32_am_Source);
3598 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3600 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3602 /* get a Proj representing a caller save register */
3603 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3604 assert(is_Proj(p) && "Proj expected.");
3606 /* user of the the proj is the Keep */
3607 p = get_edge_src_irn(get_irn_out_edge_first(p));
3608 assert(be_is_Keep(p) && "Keep expected.");
3610 /* keep the result */
3611 cls = arch_get_irn_reg_class(env->cg->arch_env, sse_load, -1);
3612 keepin[0] = sse_load;
3613 be_new_Keep(cls, irg, block, 1, keepin);
3618 /* transform call modes */
3619 if (mode_is_data(mode)) {
3620 cls = arch_get_irn_reg_class(env->cg->arch_env, node, -1);
3624 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3627 static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) {
3628 ir_graph *irg = env->irg;
3629 dbg_info *dbgi = get_irn_dbg_info(node);
3630 ir_node *pred = get_Proj_pred(node);
3631 long proj = get_Proj_proj(node);
3633 if(is_Store(pred) || be_is_FrameStore(pred)) {
3634 if(proj == pn_Store_M) {
3635 return transform_node(env, pred);
3638 return new_r_Bad(irg);
3640 } else if(is_Load(pred) || be_is_FrameLoad(pred)) {
3641 return gen_Proj_Load(env, node);
3642 } else if(is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3643 return gen_Proj_DivMod(env, node);
3644 } else if(is_CopyB(pred)) {
3645 return gen_Proj_CopyB(env, node);
3646 } else if(is_Quot(pred)) {
3647 return gen_Proj_Quot(env, node);
3648 } else if(is_ia32_l_vfdiv(pred)) {
3649 return gen_Proj_l_vfdiv(env, node);
3650 } else if(be_is_SubSP(pred)) {
3651 return gen_Proj_be_SubSP(env, node);
3652 } else if(be_is_AddSP(pred)) {
3653 return gen_Proj_be_AddSP(env, node);
3654 } else if(be_is_Call(pred)) {
3655 return gen_Proj_be_Call(env, node);
3656 } else if(get_irn_op(pred) == op_Start) {
3657 if(proj == pn_Start_X_initial_exec) {
3658 ir_node *block = get_nodes_block(pred);
3661 block = transform_node(env, block);
3662 // we exchange the ProjX with a jump
3663 jump = new_rd_Jmp(dbgi, irg, block);
3664 ir_fprintf(stderr, "created jump: %+F\n", jump);
3667 if(node == env->old_anchors[anchor_tls]) {
3668 return gen_Proj_tls(env, node);
3671 ir_node *new_pred = transform_node(env, pred);
3672 ir_node *block = transform_node(env, get_nodes_block(node));
3673 ir_mode *mode = get_irn_mode(node);
3674 if (mode_needs_gp_reg(mode)) {
3675 return new_r_Proj(irg, block, new_pred, mode_Iu, get_Proj_proj(node));
3679 return duplicate_node(env, node);
3683 * Enters all transform functions into the generic pointer
3685 static void register_transformers(void) {
3686 ir_op *op_Max, *op_Min, *op_Mulh;
3688 /* first clear the generic function pointer for all ops */
3689 clear_irp_opcodes_generic_func();
3691 #define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3692 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
3731 /* transform ops from intrinsic lowering */
3751 /* GEN(ia32_l_vfist); TODO */
3753 GEN(ia32_l_X87toSSE);
3754 GEN(ia32_l_SSEtoX87);
3759 /* we should never see these nodes */
3774 /* handle generic backend nodes */
3784 /* set the register for all Unknown nodes */
3787 op_Max = get_op_Max();
3790 op_Min = get_op_Min();
3793 op_Mulh = get_op_Mulh();
3801 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
3805 int deps = get_irn_deps(old_node);
3807 for(i = 0; i < deps; ++i) {
3808 ir_node *dep = get_irn_dep(old_node, i);
3809 ir_node *new_dep = transform_node(env, dep);
3811 add_irn_dep(new_node, new_dep);
3815 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node)
3817 ir_graph *irg = env->irg;
3818 dbg_info *dbgi = get_irn_dbg_info(node);
3819 ir_mode *mode = get_irn_mode(node);
3820 ir_op *op = get_irn_op(node);
3825 block = transform_node(env, get_nodes_block(node));
3827 arity = get_irn_arity(node);
3828 if(op->opar == oparity_dynamic) {
3829 new_node = new_ir_node(dbgi, irg, block, op, mode, -1, NULL);
3830 for(i = 0; i < arity; ++i) {
3831 ir_node *in = get_irn_n(node, i);
3832 in = transform_node(env, in);
3833 add_irn_n(new_node, in);
3836 ir_node **ins = alloca(arity * sizeof(ins[0]));
3837 for(i = 0; i < arity; ++i) {
3838 ir_node *in = get_irn_n(node, i);
3839 ins[i] = transform_node(env, in);
3842 new_node = new_ir_node(dbgi, irg, block, op, mode, arity, ins);
3845 copy_node_attr(node, new_node);
3846 duplicate_deps(env, node, new_node);
3851 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node)
3854 ir_op *op = get_irn_op(node);
3856 if(irn_visited(node)) {
3857 assert(get_new_node(node) != NULL);
3858 return get_new_node(node);
3861 mark_irn_visited(node);
3862 DEBUG_ONLY(set_new_node(node, NULL));
3864 if (op->ops.generic) {
3865 transform_func *transform = (transform_func *)op->ops.generic;
3867 new_node = (*transform)(env, node);
3868 assert(new_node != NULL);
3870 new_node = duplicate_node(env, node);
3872 //ir_fprintf(stderr, "%+F -> %+F\n", node, new_node);
3874 set_new_node(node, new_node);
3875 mark_irn_visited(new_node);
3876 hook_dead_node_elim_subst(current_ir_graph, node, new_node);
3880 static void fix_loops(ia32_transform_env_t *env, ir_node *node)
3884 if(irn_visited(node))
3886 mark_irn_visited(node);
3888 assert(node_is_in_irgs_storage(env->irg, node));
3890 if(!is_Block(node)) {
3891 ir_node *block = get_nodes_block(node);
3892 ir_node *new_block = (ir_node*) get_irn_link(block);
3894 if(new_block != NULL) {
3895 set_nodes_block(node, new_block);
3899 fix_loops(env, block);
3902 arity = get_irn_arity(node);
3903 for(i = 0; i < arity; ++i) {
3904 ir_node *in = get_irn_n(node, i);
3905 ir_node *new = (ir_node*) get_irn_link(in);
3907 if(new != NULL && new != in) {
3908 set_irn_n(node, i, new);
3915 arity = get_irn_deps(node);
3916 for(i = 0; i < arity; ++i) {
3917 ir_node *in = get_irn_dep(node, i);
3918 ir_node *new = (ir_node*) get_irn_link(in);
3920 if(new != NULL && new != in) {
3921 set_irn_dep(node, i, new);
3929 static void pre_transform_node(ir_node **place, ia32_transform_env_t *env)
3934 *place = transform_node(env, *place);
3937 static void transform_nodes(ia32_code_gen_t *cg)
3940 ir_graph *irg = cg->irg;
3942 ia32_transform_env_t env;
3944 hook_dead_node_elim(irg, 1);
3946 inc_irg_visited(irg);
3950 env.visited = get_irg_visited(irg);
3951 env.worklist = new_pdeq();
3952 env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
3954 old_end = get_irg_end(irg);
3956 /* put all anchor nodes in the worklist */
3957 for(i = 0; i < anchor_max; ++i) {
3958 ir_node *anchor = irg->anchors[i];
3961 pdeq_putr(env.worklist, anchor);
3964 env.old_anchors[i] = anchor;
3965 // and set it to NULL to make sure we don't accidently use it
3966 irg->anchors[i] = NULL;
3969 // pre transform some anchors (so they are available in the other transform
3971 set_irg_bad(irg, transform_node(&env, env.old_anchors[anchor_bad]));
3972 set_irg_no_mem(irg, transform_node(&env, env.old_anchors[anchor_no_mem]));
3973 set_irg_start_block(irg, transform_node(&env, env.old_anchors[anchor_start_block]));
3974 set_irg_start(irg, transform_node(&env, env.old_anchors[anchor_start]));
3975 set_irg_frame(irg, transform_node(&env, env.old_anchors[anchor_frame]));
3977 pre_transform_node(&cg->unknown_gp, &env);
3978 pre_transform_node(&cg->unknown_vfp, &env);
3979 pre_transform_node(&cg->unknown_xmm, &env);
3980 pre_transform_node(&cg->noreg_gp, &env);
3981 pre_transform_node(&cg->noreg_vfp, &env);
3982 pre_transform_node(&cg->noreg_xmm, &env);
3984 /* process worklist (this should transform all nodes in the graph) */
3985 while(!pdeq_empty(env.worklist)) {
3986 ir_node *node = pdeq_getl(env.worklist);
3987 transform_node(&env, node);
3990 /* fix loops and set new anchors*/
3991 inc_irg_visited(irg);
3992 for(i = 0; i < anchor_max; ++i) {
3993 ir_node *anchor = env.old_anchors[i];
3997 anchor = get_irn_link(anchor);
3998 fix_loops(&env, anchor);
3999 assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
4000 irg->anchors[i] = anchor;
4003 del_pdeq(env.worklist);
4005 hook_dead_node_elim(irg, 0);
4008 void ia32_transform_graph(ia32_code_gen_t *cg)
4010 ir_graph *irg = cg->irg;
4011 be_irg_t *birg = cg->birg;
4012 ir_graph *old_current_ir_graph = current_ir_graph;
4013 int old_interprocedural_view = get_interprocedural_view();
4014 struct obstack *old_obst = NULL;
4015 struct obstack *new_obst = NULL;
4017 current_ir_graph = irg;
4018 set_interprocedural_view(0);
4019 register_transformers();
4021 /* most analysis info is wrong after transformation */
4022 free_callee_info(irg);
4024 irg->outs_state = outs_none;
4026 free_loop_information(irg);
4027 set_irg_doms_inconsistent(irg);
4028 be_invalidate_liveness(birg);
4029 be_invalidate_dom_front(birg);
4031 /* create a new obstack */
4032 old_obst = irg->obst;
4033 new_obst = xmalloc(sizeof(*new_obst));
4034 obstack_init(new_obst);
4035 irg->obst = new_obst;
4036 irg->last_node_idx = 0;
4038 /* create new value table for CSE */
4039 del_identities(irg->value_table);
4040 irg->value_table = new_identities();
4042 /* do the main transformation */
4043 transform_nodes(cg);
4045 /* we don't want the globals anchor anymore */
4046 set_irg_globals(irg, new_r_Bad(irg));
4048 /* free the old obstack */
4049 obstack_free(old_obst, 0);
4053 current_ir_graph = old_current_ir_graph;
4054 set_interprocedural_view(old_interprocedural_view);
4056 /* recalculate edges */
4057 edges_deactivate(irg);
4058 edges_activate(irg);
4062 * Transforms a psi condition.
4064 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
4067 /* if the mode is target mode, we have already seen this part of the tree */
4068 if (get_irn_mode(cond) == mode)
4071 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
4073 set_irn_mode(cond, mode);
4075 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
4076 ir_node *in = get_irn_n(cond, i);
4078 /* if in is a compare: transform into Set/xCmp */
4080 ir_node *new_op = NULL;
4081 ir_node *cmp = get_Proj_pred(in);
4082 ir_node *cmp_a = get_Cmp_left(cmp);
4083 ir_node *cmp_b = get_Cmp_right(cmp);
4084 dbg_info *dbgi = get_irn_dbg_info(cmp);
4085 ir_graph *irg = get_irn_irg(cmp);
4086 ir_node *block = get_nodes_block(cmp);
4087 ir_node *noreg = ia32_new_NoReg_gp(cg);
4088 ir_node *nomem = new_rd_NoMem(irg);
4089 int pnc = get_Proj_proj(in);
4091 /* this is a compare */
4092 if (mode_is_float(mode)) {
4093 /* Psi is float, we need a floating point compare */
4096 ir_mode *m = get_irn_mode(cmp_a);
4098 if (! mode_is_float(m)) {
4099 cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_a, cmp_a, mode);
4100 cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_b, cmp_b, mode);
4101 } else if (m == mode_F) {
4102 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
4103 cmp_a = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_a, cmp_a);
4104 cmp_b = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_b, cmp_b);
4107 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4108 set_ia32_pncode(new_op, pnc);
4109 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
4116 construct_binop_func *set_func = NULL;
4118 if (mode_is_float(get_irn_mode(cmp_a))) {
4119 /* 1st case: compare operands are floats */
4124 set_func = new_rd_ia32_xCmpSet;
4127 set_func = new_rd_ia32_vfCmpSet;
4130 pnc &= 7; /* fp compare -> int compare */
4132 /* 2nd case: compare operand are integer too */
4133 set_func = new_rd_ia32_CmpSet;
4136 new_op = set_func(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4137 if(!mode_is_signed(mode))
4138 pnc |= ia32_pn_Cmp_Unsigned;
4140 set_ia32_pncode(new_op, pnc);
4141 set_ia32_am_support(new_op, ia32_am_Source);
4144 /* the the new compare as in */
4145 set_irn_n(cond, i, new_op);
4147 /* another complex condition */
4148 transform_psi_cond(in, mode, cg);
4154 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
4155 * We create a Set node, respectively a xCmp in case the Psi is a float, for
4156 * each compare, which causes the compare result to be stored in a register. The
4157 * "And"s and "Or"s are transformed later, we just have to set their mode right.
4159 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
4160 ia32_code_gen_t *cg = env;
4161 ir_node *psi_sel, *new_cmp, *block;
4166 if (get_irn_opcode(node) != iro_Psi)
4169 psi_sel = get_Psi_cond(node, 0);
4171 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
4172 if (is_Proj(psi_sel)) {
4173 assert(is_Cmp(get_Proj_pred(psi_sel)));
4177 //mode = get_irn_mode(node);
4178 // TODO probably wrong...
4181 transform_psi_cond(psi_sel, mode, cg);
4183 irg = get_irn_irg(node);
4184 block = get_nodes_block(node);
4186 /* we need to compare the evaluated condition tree with 0 */
4187 mode = get_irn_mode(node);
4188 if (mode_is_float(mode)) {
4189 /* BEWARE: new_r_Const_long works for floating point as well */
4190 ir_node *zero = new_r_Const_long(irg, block, mode, 0);
4192 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
4193 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4194 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
4196 ir_node *zero = new_r_Const_long(irg, block, mode_Iu, 0);
4197 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4198 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
4201 set_Psi_cond(node, 0, new_cmp);
4204 void ia32_init_transform(void)
4206 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");