2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode.h"
52 #include "../besched.h"
54 #include "../beutil.h"
56 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_common_transform.h"
61 #include "ia32_nodes_attr.h"
62 #include "ia32_transform.h"
63 #include "ia32_new_nodes.h"
64 #include "ia32_map_regs.h"
65 #include "ia32_dbg_stat.h"
66 #include "ia32_optimize.h"
67 #include "ia32_util.h"
68 #include "ia32_address_mode.h"
69 #include "ia32_architecture.h"
71 #include "gen_ia32_regalloc_if.h"
73 /* define this to construct SSE constants instead of load them */
74 #undef CONSTRUCT_SSE_CONST
77 #define SFP_SIGN "0x80000000"
78 #define DFP_SIGN "0x8000000000000000"
79 #define SFP_ABS "0x7FFFFFFF"
80 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
81 #define DFP_INTMAX "9223372036854775807"
82 #define ULL_BIAS "18446744073709551616"
84 #define ENT_SFP_SIGN ".LC_ia32_sfp_sign"
85 #define ENT_DFP_SIGN ".LC_ia32_dfp_sign"
86 #define ENT_SFP_ABS ".LC_ia32_sfp_abs"
87 #define ENT_DFP_ABS ".LC_ia32_dfp_abs"
88 #define ENT_ULL_BIAS ".LC_ia32_ull_bias"
90 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
91 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
93 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
95 static ir_node *initial_fpcw = NULL;
98 typedef ir_node *construct_binop_func(dbg_info *db, ir_node *block,
99 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1,
102 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_node *block,
103 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2,
106 typedef ir_node *construct_shift_func(dbg_info *db, ir_node *block,
107 ir_node *op1, ir_node *op2);
109 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_node *block,
110 ir_node *base, ir_node *index, ir_node *mem, ir_node *op);
112 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_node *block,
113 ir_node *base, ir_node *index, ir_node *mem);
115 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_node *block,
116 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2,
119 typedef ir_node *construct_unop_func(dbg_info *db, ir_node *block, ir_node *op);
121 static ir_node *create_immediate_or_transform(ir_node *node,
122 char immediate_constraint_type);
124 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
125 dbg_info *dbgi, ir_node *block,
126 ir_node *op, ir_node *orig_node);
128 /* its enough to have those once */
129 static ir_node *nomem, *noreg_GP;
131 /** a list to postprocess all calls */
132 static ir_node **call_list;
133 static ir_type **call_types;
135 /** Return non-zero is a node represents the 0 constant. */
136 static bool is_Const_0(ir_node *node)
138 return is_Const(node) && is_Const_null(node);
141 /** Return non-zero is a node represents the 1 constant. */
142 static bool is_Const_1(ir_node *node)
144 return is_Const(node) && is_Const_one(node);
147 /** Return non-zero is a node represents the -1 constant. */
148 static bool is_Const_Minus_1(ir_node *node)
150 return is_Const(node) && is_Const_all_one(node);
154 * returns true if constant can be created with a simple float command
156 static bool is_simple_x87_Const(ir_node *node)
158 tarval *tv = get_Const_tarval(node);
159 if (tarval_is_null(tv) || tarval_is_one(tv))
162 /* TODO: match all the other float constants */
167 * returns true if constant can be created with a simple float command
169 static bool is_simple_sse_Const(ir_node *node)
171 tarval *tv = get_Const_tarval(node);
172 ir_mode *mode = get_tarval_mode(tv);
177 if (tarval_is_null(tv)
178 #ifdef CONSTRUCT_SSE_CONST
183 #ifdef CONSTRUCT_SSE_CONST
184 if (mode == mode_D) {
185 unsigned val = get_tarval_sub_bits(tv, 0) |
186 (get_tarval_sub_bits(tv, 1) << 8) |
187 (get_tarval_sub_bits(tv, 2) << 16) |
188 (get_tarval_sub_bits(tv, 3) << 24);
190 /* lower 32bit are zero, really a 32bit constant */
193 #endif /* CONSTRUCT_SSE_CONST */
194 /* TODO: match all the other float constants */
199 * return NoREG or pic_base in case of PIC.
200 * This is necessary as base address for newly created symbols
202 static ir_node *get_symconst_base(void)
204 if (env_cg->birg->main_env->options->pic) {
205 return arch_code_generator_get_pic_base(env_cg);
212 * Transforms a Const.
214 static ir_node *gen_Const(ir_node *node)
216 ir_node *old_block = get_nodes_block(node);
217 ir_node *block = be_transform_node(old_block);
218 dbg_info *dbgi = get_irn_dbg_info(node);
219 ir_mode *mode = get_irn_mode(node);
221 assert(is_Const(node));
223 if (mode_is_float(mode)) {
229 if (ia32_cg_config.use_sse2) {
230 tarval *tv = get_Const_tarval(node);
231 if (tarval_is_null(tv)) {
232 load = new_bd_ia32_xZero(dbgi, block);
233 set_ia32_ls_mode(load, mode);
235 #ifdef CONSTRUCT_SSE_CONST
236 } else if (tarval_is_one(tv)) {
237 int cnst = mode == mode_F ? 26 : 55;
238 ir_node *imm1 = ia32_create_Immediate(NULL, 0, cnst);
239 ir_node *imm2 = ia32_create_Immediate(NULL, 0, 2);
240 ir_node *pslld, *psrld;
242 load = new_bd_ia32_xAllOnes(dbgi, block);
243 set_ia32_ls_mode(load, mode);
244 pslld = new_bd_ia32_xPslld(dbgi, block, load, imm1);
245 set_ia32_ls_mode(pslld, mode);
246 psrld = new_bd_ia32_xPsrld(dbgi, block, pslld, imm2);
247 set_ia32_ls_mode(psrld, mode);
249 #endif /* CONSTRUCT_SSE_CONST */
250 } else if (mode == mode_F) {
251 /* we can place any 32bit constant by using a movd gp, sse */
252 unsigned val = get_tarval_sub_bits(tv, 0) |
253 (get_tarval_sub_bits(tv, 1) << 8) |
254 (get_tarval_sub_bits(tv, 2) << 16) |
255 (get_tarval_sub_bits(tv, 3) << 24);
256 ir_node *cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
257 load = new_bd_ia32_xMovd(dbgi, block, cnst);
258 set_ia32_ls_mode(load, mode);
261 #ifdef CONSTRUCT_SSE_CONST
262 if (mode == mode_D) {
263 unsigned val = get_tarval_sub_bits(tv, 0) |
264 (get_tarval_sub_bits(tv, 1) << 8) |
265 (get_tarval_sub_bits(tv, 2) << 16) |
266 (get_tarval_sub_bits(tv, 3) << 24);
268 ir_node *imm32 = ia32_create_Immediate(NULL, 0, 32);
269 ir_node *cnst, *psllq;
271 /* fine, lower 32bit are zero, produce 32bit value */
272 val = get_tarval_sub_bits(tv, 4) |
273 (get_tarval_sub_bits(tv, 5) << 8) |
274 (get_tarval_sub_bits(tv, 6) << 16) |
275 (get_tarval_sub_bits(tv, 7) << 24);
276 cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
277 load = new_bd_ia32_xMovd(dbgi, block, cnst);
278 set_ia32_ls_mode(load, mode);
279 psllq = new_bd_ia32_xPsllq(dbgi, block, load, imm32);
280 set_ia32_ls_mode(psllq, mode);
285 #endif /* CONSTRUCT_SSE_CONST */
286 floatent = create_float_const_entity(node);
288 base = get_symconst_base();
289 load = new_bd_ia32_xLoad(dbgi, block, base, noreg_GP, nomem,
291 set_ia32_op_type(load, ia32_AddrModeS);
292 set_ia32_am_sc(load, floatent);
293 arch_irn_add_flags(load, arch_irn_flags_rematerializable);
294 res = new_r_Proj(block, load, mode_xmm, pn_ia32_xLoad_res);
297 if (is_Const_null(node)) {
298 load = new_bd_ia32_vfldz(dbgi, block);
300 set_ia32_ls_mode(load, mode);
301 } else if (is_Const_one(node)) {
302 load = new_bd_ia32_vfld1(dbgi, block);
304 set_ia32_ls_mode(load, mode);
309 floatent = create_float_const_entity(node);
310 /* create_float_const_ent is smart and sometimes creates
312 ls_mode = get_type_mode(get_entity_type(floatent));
313 base = get_symconst_base();
314 load = new_bd_ia32_vfld(dbgi, block, base, noreg_GP, nomem,
316 set_ia32_op_type(load, ia32_AddrModeS);
317 set_ia32_am_sc(load, floatent);
318 arch_irn_add_flags(load, arch_irn_flags_rematerializable);
319 res = new_r_Proj(block, load, mode_vfp, pn_ia32_vfld_res);
322 #ifdef CONSTRUCT_SSE_CONST
324 #endif /* CONSTRUCT_SSE_CONST */
325 SET_IA32_ORIG_NODE(load, node);
327 be_dep_on_frame(load);
329 } else { /* non-float mode */
331 tarval *tv = get_Const_tarval(node);
334 tv = tarval_convert_to(tv, mode_Iu);
336 if (tv == get_tarval_bad() || tv == get_tarval_undefined() ||
338 panic("couldn't convert constant tarval (%+F)", node);
340 val = get_tarval_long(tv);
342 cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
343 SET_IA32_ORIG_NODE(cnst, node);
345 be_dep_on_frame(cnst);
351 * Transforms a SymConst.
353 static ir_node *gen_SymConst(ir_node *node)
355 ir_node *old_block = get_nodes_block(node);
356 ir_node *block = be_transform_node(old_block);
357 dbg_info *dbgi = get_irn_dbg_info(node);
358 ir_mode *mode = get_irn_mode(node);
361 if (mode_is_float(mode)) {
362 if (ia32_cg_config.use_sse2)
363 cnst = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E);
365 cnst = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E);
366 set_ia32_am_sc(cnst, get_SymConst_entity(node));
367 set_ia32_use_frame(cnst);
371 if (get_SymConst_kind(node) != symconst_addr_ent) {
372 panic("backend only support symconst_addr_ent (at %+F)", node);
374 entity = get_SymConst_entity(node);
375 cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0, 0);
378 SET_IA32_ORIG_NODE(cnst, node);
380 be_dep_on_frame(cnst);
385 * Create a float type for the given mode and cache it.
387 * @param mode the mode for the float type (might be integer mode for SSE2 types)
388 * @param align alignment
390 static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align)
396 if (mode == mode_Iu) {
397 static ir_type *int_Iu[16] = {NULL, };
399 if (int_Iu[align] == NULL) {
400 int_Iu[align] = tp = new_type_primitive(mode);
401 /* set the specified alignment */
402 set_type_alignment_bytes(tp, align);
404 return int_Iu[align];
405 } else if (mode == mode_Lu) {
406 static ir_type *int_Lu[16] = {NULL, };
408 if (int_Lu[align] == NULL) {
409 int_Lu[align] = tp = new_type_primitive(mode);
410 /* set the specified alignment */
411 set_type_alignment_bytes(tp, align);
413 return int_Lu[align];
414 } else if (mode == mode_F) {
415 static ir_type *float_F[16] = {NULL, };
417 if (float_F[align] == NULL) {
418 float_F[align] = tp = new_type_primitive(mode);
419 /* set the specified alignment */
420 set_type_alignment_bytes(tp, align);
422 return float_F[align];
423 } else if (mode == mode_D) {
424 static ir_type *float_D[16] = {NULL, };
426 if (float_D[align] == NULL) {
427 float_D[align] = tp = new_type_primitive(mode);
428 /* set the specified alignment */
429 set_type_alignment_bytes(tp, align);
431 return float_D[align];
433 static ir_type *float_E[16] = {NULL, };
435 if (float_E[align] == NULL) {
436 float_E[align] = tp = new_type_primitive(mode);
437 /* set the specified alignment */
438 set_type_alignment_bytes(tp, align);
440 return float_E[align];
445 * Create a float[2] array type for the given atomic type.
447 * @param tp the atomic type
449 static ir_type *ia32_create_float_array(ir_type *tp)
451 ir_mode *mode = get_type_mode(tp);
452 unsigned align = get_type_alignment_bytes(tp);
457 if (mode == mode_F) {
458 static ir_type *float_F[16] = {NULL, };
460 if (float_F[align] != NULL)
461 return float_F[align];
462 arr = float_F[align] = new_type_array(1, tp);
463 } else if (mode == mode_D) {
464 static ir_type *float_D[16] = {NULL, };
466 if (float_D[align] != NULL)
467 return float_D[align];
468 arr = float_D[align] = new_type_array(1, tp);
470 static ir_type *float_E[16] = {NULL, };
472 if (float_E[align] != NULL)
473 return float_E[align];
474 arr = float_E[align] = new_type_array(1, tp);
476 set_type_alignment_bytes(arr, align);
477 set_type_size_bytes(arr, 2 * get_type_size_bytes(tp));
478 set_type_state(arr, layout_fixed);
482 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
483 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct)
485 static const struct {
486 const char *ent_name;
487 const char *cnst_str;
490 } names [ia32_known_const_max] = {
491 { ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
492 { ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
493 { ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
494 { ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
495 { ENT_ULL_BIAS, ULL_BIAS, 2, 4 } /* ia32_ULLBIAS */
497 static ir_entity *ent_cache[ia32_known_const_max];
499 const char *ent_name, *cnst_str;
505 ent_name = names[kct].ent_name;
506 if (! ent_cache[kct]) {
507 cnst_str = names[kct].cnst_str;
509 switch (names[kct].mode) {
510 case 0: mode = mode_Iu; break;
511 case 1: mode = mode_Lu; break;
512 default: mode = mode_F; break;
514 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
515 tp = ia32_create_float_type(mode, names[kct].align);
517 if (kct == ia32_ULLBIAS)
518 tp = ia32_create_float_array(tp);
519 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
521 set_entity_ld_ident(ent, get_entity_ident(ent));
522 add_entity_linkage(ent, IR_LINKAGE_CONSTANT);
523 set_entity_visibility(ent, ir_visibility_local);
525 if (kct == ia32_ULLBIAS) {
526 ir_initializer_t *initializer = create_initializer_compound(2);
528 set_initializer_compound_value(initializer, 0,
529 create_initializer_tarval(get_tarval_null(mode)));
530 set_initializer_compound_value(initializer, 1,
531 create_initializer_tarval(tv));
533 set_entity_initializer(ent, initializer);
535 set_entity_initializer(ent, create_initializer_tarval(tv));
538 /* cache the entry */
539 ent_cache[kct] = ent;
542 return ent_cache[kct];
546 * return true if the node is a Proj(Load) and could be used in source address
547 * mode for another node. Will return only true if the @p other node is not
548 * dependent on the memory of the Load (for binary operations use the other
549 * input here, for unary operations use NULL).
551 static int ia32_use_source_address_mode(ir_node *block, ir_node *node,
552 ir_node *other, ir_node *other2, match_flags_t flags)
557 /* float constants are always available */
558 if (is_Const(node)) {
559 ir_mode *mode = get_irn_mode(node);
560 if (mode_is_float(mode)) {
561 if (ia32_cg_config.use_sse2) {
562 if (is_simple_sse_Const(node))
565 if (is_simple_x87_Const(node))
568 if (get_irn_n_edges(node) > 1)
576 load = get_Proj_pred(node);
577 pn = get_Proj_proj(node);
578 if (!is_Load(load) || pn != pn_Load_res)
580 if (get_nodes_block(load) != block)
582 /* we only use address mode if we're the only user of the load */
583 if (get_irn_n_edges(node) != (flags & match_two_users ? 2 : 1))
585 /* in some edge cases with address mode we might reach the load normally
586 * and through some AM sequence, if it is already materialized then we
587 * can't create an AM node from it */
588 if (be_is_transformed(node))
591 /* don't do AM if other node inputs depend on the load (via mem-proj) */
592 if (other != NULL && prevents_AM(block, load, other))
595 if (other2 != NULL && prevents_AM(block, load, other2))
601 typedef struct ia32_address_mode_t ia32_address_mode_t;
602 struct ia32_address_mode_t {
607 ia32_op_type_t op_type;
611 unsigned commutative : 1;
612 unsigned ins_permuted : 1;
615 static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
617 /* construct load address */
618 memset(addr, 0, sizeof(addr[0]));
619 ia32_create_address_mode(addr, ptr, 0);
621 addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP;
622 addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP;
623 addr->mem = be_transform_node(mem);
626 static void build_address(ia32_address_mode_t *am, ir_node *node,
627 ia32_create_am_flags_t flags)
629 ia32_address_t *addr = &am->addr;
635 /* floating point immediates */
636 if (is_Const(node)) {
637 ir_entity *entity = create_float_const_entity(node);
638 addr->base = get_symconst_base();
639 addr->index = noreg_GP;
641 addr->symconst_ent = entity;
643 am->ls_mode = get_type_mode(get_entity_type(entity));
644 am->pinned = op_pin_state_floats;
648 load = get_Proj_pred(node);
649 ptr = get_Load_ptr(load);
650 mem = get_Load_mem(load);
651 new_mem = be_transform_node(mem);
652 am->pinned = get_irn_pinned(load);
653 am->ls_mode = get_Load_mode(load);
654 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
657 /* construct load address */
658 ia32_create_address_mode(addr, ptr, flags);
660 addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP;
661 addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP;
665 static void set_address(ir_node *node, const ia32_address_t *addr)
667 set_ia32_am_scale(node, addr->scale);
668 set_ia32_am_sc(node, addr->symconst_ent);
669 set_ia32_am_offs_int(node, addr->offset);
670 if (addr->symconst_sign)
671 set_ia32_am_sc_sign(node);
673 set_ia32_use_frame(node);
674 set_ia32_frame_ent(node, addr->frame_entity);
678 * Apply attributes of a given address mode to a node.
680 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
682 set_address(node, &am->addr);
684 set_ia32_op_type(node, am->op_type);
685 set_ia32_ls_mode(node, am->ls_mode);
686 if (am->pinned == op_pin_state_pinned) {
687 /* beware: some nodes are already pinned and did not allow to change the state */
688 if (get_irn_pinned(node) != op_pin_state_pinned)
689 set_irn_pinned(node, op_pin_state_pinned);
692 set_ia32_commutative(node);
696 * Check, if a given node is a Down-Conv, ie. a integer Conv
697 * from a mode with a mode with more bits to a mode with lesser bits.
698 * Moreover, we return only true if the node has not more than 1 user.
700 * @param node the node
701 * @return non-zero if node is a Down-Conv
703 static int is_downconv(const ir_node *node)
711 /* we only want to skip the conv when we're the only user
712 * (not optimal but for now...)
714 if (get_irn_n_edges(node) > 1)
717 src_mode = get_irn_mode(get_Conv_op(node));
718 dest_mode = get_irn_mode(node);
720 ia32_mode_needs_gp_reg(src_mode) &&
721 ia32_mode_needs_gp_reg(dest_mode) &&
722 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
725 /* Skip all Down-Conv's on a given node and return the resulting node. */
726 ir_node *ia32_skip_downconv(ir_node *node)
728 while (is_downconv(node))
729 node = get_Conv_op(node);
734 static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
736 ir_mode *mode = get_irn_mode(node);
741 if (mode_is_signed(mode)) {
746 block = get_nodes_block(node);
747 dbgi = get_irn_dbg_info(node);
749 return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
753 * matches operands of a node into ia32 addressing/operand modes. This covers
754 * usage of source address mode, immediates, operations with non 32-bit modes,
756 * The resulting data is filled into the @p am struct. block is the block
757 * of the node whose arguments are matched. op1, op2 are the first and second
758 * input that are matched (op1 may be NULL). other_op is another unrelated
759 * input that is not matched! but which is needed sometimes to check if AM
760 * for op1/op2 is legal.
761 * @p flags describes the supported modes of the operation in detail.
763 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
764 ir_node *op1, ir_node *op2, ir_node *other_op,
767 ia32_address_t *addr = &am->addr;
768 ir_mode *mode = get_irn_mode(op2);
769 int mode_bits = get_mode_size_bits(mode);
770 ir_node *new_op1, *new_op2;
772 unsigned commutative;
773 int use_am_and_immediates;
776 memset(am, 0, sizeof(am[0]));
778 commutative = (flags & match_commutative) != 0;
779 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
780 use_am = (flags & match_am) != 0;
781 use_immediate = (flags & match_immediate) != 0;
782 assert(!use_am_and_immediates || use_immediate);
785 assert(!commutative || op1 != NULL);
786 assert(use_am || !(flags & match_8bit_am));
787 assert(use_am || !(flags & match_16bit_am));
789 if ((mode_bits == 8 && !(flags & match_8bit_am)) ||
790 (mode_bits == 16 && !(flags & match_16bit_am))) {
794 /* we can simply skip downconvs for mode neutral nodes: the upper bits
795 * can be random for these operations */
796 if (flags & match_mode_neutral) {
797 op2 = ia32_skip_downconv(op2);
799 op1 = ia32_skip_downconv(op1);
803 /* match immediates. firm nodes are normalized: constants are always on the
806 if (!(flags & match_try_am) && use_immediate) {
807 new_op2 = try_create_Immediate(op2, 0);
810 if (new_op2 == NULL &&
811 use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) {
812 build_address(am, op2, 0);
813 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
814 if (mode_is_float(mode)) {
815 new_op2 = ia32_new_NoReg_vfp(env_cg);
819 am->op_type = ia32_AddrModeS;
820 } else if (commutative && (new_op2 == NULL || use_am_and_immediates) &&
822 ia32_use_source_address_mode(block, op1, op2, other_op, flags)) {
824 build_address(am, op1, 0);
826 if (mode_is_float(mode)) {
827 noreg = ia32_new_NoReg_vfp(env_cg);
832 if (new_op2 != NULL) {
835 new_op1 = be_transform_node(op2);
837 am->ins_permuted = 1;
839 am->op_type = ia32_AddrModeS;
842 am->op_type = ia32_Normal;
844 if (flags & match_try_am) {
850 mode = get_irn_mode(op2);
851 if (flags & match_upconv_32 && get_mode_size_bits(mode) != 32) {
852 new_op1 = (op1 == NULL ? NULL : create_upconv(op1, NULL));
854 new_op2 = create_upconv(op2, NULL);
855 am->ls_mode = mode_Iu;
857 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
859 new_op2 = be_transform_node(op2);
860 am->ls_mode = (flags & match_mode_neutral) ? mode_Iu : mode;
863 if (addr->base == NULL)
864 addr->base = noreg_GP;
865 if (addr->index == NULL)
866 addr->index = noreg_GP;
867 if (addr->mem == NULL)
870 am->new_op1 = new_op1;
871 am->new_op2 = new_op2;
872 am->commutative = commutative;
876 * "Fixes" a node that uses address mode by turning it into mode_T
877 * and returning a pn_ia32_res Proj.
879 * @param node the node
880 * @param am its address mode
882 * @return a Proj(pn_ia32_res) if a memory address mode is used,
885 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
890 if (am->mem_proj == NULL)
893 /* we have to create a mode_T so the old MemProj can attach to us */
894 mode = get_irn_mode(node);
895 load = get_Proj_pred(am->mem_proj);
897 be_set_transformed_node(load, node);
899 if (mode != mode_T) {
900 set_irn_mode(node, mode_T);
901 return new_rd_Proj(NULL, get_nodes_block(node), node, mode, pn_ia32_res);
908 * Construct a standard binary operation, set AM and immediate if required.
910 * @param node The original node for which the binop is created
911 * @param op1 The first operand
912 * @param op2 The second operand
913 * @param func The node constructor function
914 * @return The constructed ia32 node.
916 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
917 construct_binop_func *func, match_flags_t flags)
920 ir_node *block, *new_block, *new_node;
921 ia32_address_mode_t am;
922 ia32_address_t *addr = &am.addr;
924 block = get_nodes_block(node);
925 match_arguments(&am, block, op1, op2, NULL, flags);
927 dbgi = get_irn_dbg_info(node);
928 new_block = be_transform_node(block);
929 new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem,
930 am.new_op1, am.new_op2);
931 set_am_attributes(new_node, &am);
932 /* we can't use source address mode anymore when using immediates */
933 if (!(flags & match_am_and_immediates) &&
934 (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)))
935 set_ia32_am_support(new_node, ia32_am_none);
936 SET_IA32_ORIG_NODE(new_node, node);
938 new_node = fix_mem_proj(new_node, &am);
944 * Generic names for the inputs of an ia32 binary op.
947 n_ia32_l_binop_left, /**< ia32 left input */
948 n_ia32_l_binop_right, /**< ia32 right input */
949 n_ia32_l_binop_eflags /**< ia32 eflags input */
951 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
952 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
953 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
954 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_minuend, n_Sbb_minuend)
955 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend)
956 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
959 * Construct a binary operation which also consumes the eflags.
961 * @param node The node to transform
962 * @param func The node constructor function
963 * @param flags The match flags
964 * @return The constructor ia32 node
966 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
969 ir_node *src_block = get_nodes_block(node);
970 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
971 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
972 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
974 ir_node *block, *new_node, *new_eflags;
975 ia32_address_mode_t am;
976 ia32_address_t *addr = &am.addr;
978 match_arguments(&am, src_block, op1, op2, eflags, flags);
980 dbgi = get_irn_dbg_info(node);
981 block = be_transform_node(src_block);
982 new_eflags = be_transform_node(eflags);
983 new_node = func(dbgi, block, addr->base, addr->index, addr->mem,
984 am.new_op1, am.new_op2, new_eflags);
985 set_am_attributes(new_node, &am);
986 /* we can't use source address mode anymore when using immediates */
987 if (!(flags & match_am_and_immediates) &&
988 (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)))
989 set_ia32_am_support(new_node, ia32_am_none);
990 SET_IA32_ORIG_NODE(new_node, node);
992 new_node = fix_mem_proj(new_node, &am);
997 static ir_node *get_fpcw(void)
1000 if (initial_fpcw != NULL)
1001 return initial_fpcw;
1003 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1004 &ia32_fp_cw_regs[REG_FPCW]);
1005 initial_fpcw = be_transform_node(fpcw);
1007 return initial_fpcw;
1011 * Construct a standard binary operation, set AM and immediate if required.
1013 * @param op1 The first operand
1014 * @param op2 The second operand
1015 * @param func The node constructor function
1016 * @return The constructed ia32 node.
1018 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
1019 construct_binop_float_func *func)
1021 ir_mode *mode = get_irn_mode(node);
1023 ir_node *block, *new_block, *new_node;
1024 ia32_address_mode_t am;
1025 ia32_address_t *addr = &am.addr;
1026 ia32_x87_attr_t *attr;
1027 /* All operations are considered commutative, because there are reverse
1029 match_flags_t flags = match_commutative;
1031 /* happens for div nodes... */
1033 mode = get_divop_resmod(node);
1035 /* cannot use address mode with long double on x87 */
1036 if (get_mode_size_bits(mode) <= 64)
1039 block = get_nodes_block(node);
1040 match_arguments(&am, block, op1, op2, NULL, flags);
1042 dbgi = get_irn_dbg_info(node);
1043 new_block = be_transform_node(block);
1044 new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem,
1045 am.new_op1, am.new_op2, get_fpcw());
1046 set_am_attributes(new_node, &am);
1048 attr = get_ia32_x87_attr(new_node);
1049 attr->attr.data.ins_permuted = am.ins_permuted;
1051 SET_IA32_ORIG_NODE(new_node, node);
1053 new_node = fix_mem_proj(new_node, &am);
1059 * Construct a shift/rotate binary operation, sets AM and immediate if required.
1061 * @param op1 The first operand
1062 * @param op2 The second operand
1063 * @param func The node constructor function
1064 * @return The constructed ia32 node.
1066 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
1067 construct_shift_func *func,
1068 match_flags_t flags)
1071 ir_node *block, *new_block, *new_op1, *new_op2, *new_node;
1073 assert(! mode_is_float(get_irn_mode(node)));
1074 assert(flags & match_immediate);
1075 assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
1077 if (flags & match_mode_neutral) {
1078 op1 = ia32_skip_downconv(op1);
1079 new_op1 = be_transform_node(op1);
1080 } else if (get_mode_size_bits(get_irn_mode(node)) != 32) {
1081 new_op1 = create_upconv(op1, node);
1083 new_op1 = be_transform_node(op1);
1086 /* the shift amount can be any mode that is bigger than 5 bits, since all
1087 * other bits are ignored anyway */
1088 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
1089 ir_node *const op = get_Conv_op(op2);
1090 if (mode_is_float(get_irn_mode(op)))
1093 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
1095 new_op2 = create_immediate_or_transform(op2, 0);
1097 dbgi = get_irn_dbg_info(node);
1098 block = get_nodes_block(node);
1099 new_block = be_transform_node(block);
1100 new_node = func(dbgi, new_block, new_op1, new_op2);
1101 SET_IA32_ORIG_NODE(new_node, node);
1103 /* lowered shift instruction may have a dependency operand, handle it here */
1104 if (get_irn_arity(node) == 3) {
1105 /* we have a dependency */
1106 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
1107 add_irn_dep(new_node, new_dep);
1115 * Construct a standard unary operation, set AM and immediate if required.
1117 * @param op The operand
1118 * @param func The node constructor function
1119 * @return The constructed ia32 node.
1121 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
1122 match_flags_t flags)
1125 ir_node *block, *new_block, *new_op, *new_node;
1127 assert(flags == 0 || flags == match_mode_neutral);
1128 if (flags & match_mode_neutral) {
1129 op = ia32_skip_downconv(op);
1132 new_op = be_transform_node(op);
1133 dbgi = get_irn_dbg_info(node);
1134 block = get_nodes_block(node);
1135 new_block = be_transform_node(block);
1136 new_node = func(dbgi, new_block, new_op);
1138 SET_IA32_ORIG_NODE(new_node, node);
1143 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
1144 ia32_address_t *addr)
1146 ir_node *base, *index, *res;
1152 base = be_transform_node(base);
1155 index = addr->index;
1156 if (index == NULL) {
1159 index = be_transform_node(index);
1162 res = new_bd_ia32_Lea(dbgi, block, base, index);
1163 set_address(res, addr);
1169 * Returns non-zero if a given address mode has a symbolic or
1170 * numerical offset != 0.
1172 static int am_has_immediates(const ia32_address_t *addr)
1174 return addr->offset != 0 || addr->symconst_ent != NULL
1175 || addr->frame_entity || addr->use_frame;
1179 * Creates an ia32 Add.
1181 * @return the created ia32 Add node
1183 static ir_node *gen_Add(ir_node *node)
1185 ir_mode *mode = get_irn_mode(node);
1186 ir_node *op1 = get_Add_left(node);
1187 ir_node *op2 = get_Add_right(node);
1189 ir_node *block, *new_block, *new_node, *add_immediate_op;
1190 ia32_address_t addr;
1191 ia32_address_mode_t am;
1193 if (mode_is_float(mode)) {
1194 if (ia32_cg_config.use_sse2)
1195 return gen_binop(node, op1, op2, new_bd_ia32_xAdd,
1196 match_commutative | match_am);
1198 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfadd);
1201 ia32_mark_non_am(node);
1203 op2 = ia32_skip_downconv(op2);
1204 op1 = ia32_skip_downconv(op1);
1208 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1209 * 1. Add with immediate -> Lea
1210 * 2. Add with possible source address mode -> Add
1211 * 3. Otherwise -> Lea
1213 memset(&addr, 0, sizeof(addr));
1214 ia32_create_address_mode(&addr, node, ia32_create_am_force);
1215 add_immediate_op = NULL;
1217 dbgi = get_irn_dbg_info(node);
1218 block = get_nodes_block(node);
1219 new_block = be_transform_node(block);
1222 if (addr.base == NULL && addr.index == NULL) {
1223 new_node = new_bd_ia32_Const(dbgi, new_block, addr.symconst_ent,
1224 addr.symconst_sign, 0, addr.offset);
1225 be_dep_on_frame(new_node);
1226 SET_IA32_ORIG_NODE(new_node, node);
1229 /* add with immediate? */
1230 if (addr.index == NULL) {
1231 add_immediate_op = addr.base;
1232 } else if (addr.base == NULL && addr.scale == 0) {
1233 add_immediate_op = addr.index;
1236 if (add_immediate_op != NULL) {
1237 if (!am_has_immediates(&addr)) {
1238 #ifdef DEBUG_libfirm
1239 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1242 return be_transform_node(add_immediate_op);
1245 new_node = create_lea_from_address(dbgi, new_block, &addr);
1246 SET_IA32_ORIG_NODE(new_node, node);
1250 /* test if we can use source address mode */
1251 match_arguments(&am, block, op1, op2, NULL, match_commutative
1252 | match_mode_neutral | match_am | match_immediate | match_try_am);
1254 /* construct an Add with source address mode */
1255 if (am.op_type == ia32_AddrModeS) {
1256 ia32_address_t *am_addr = &am.addr;
1257 new_node = new_bd_ia32_Add(dbgi, new_block, am_addr->base,
1258 am_addr->index, am_addr->mem, am.new_op1,
1260 set_am_attributes(new_node, &am);
1261 SET_IA32_ORIG_NODE(new_node, node);
1263 new_node = fix_mem_proj(new_node, &am);
1268 /* otherwise construct a lea */
1269 new_node = create_lea_from_address(dbgi, new_block, &addr);
1270 SET_IA32_ORIG_NODE(new_node, node);
1275 * Creates an ia32 Mul.
1277 * @return the created ia32 Mul node
1279 static ir_node *gen_Mul(ir_node *node)
1281 ir_node *op1 = get_Mul_left(node);
1282 ir_node *op2 = get_Mul_right(node);
1283 ir_mode *mode = get_irn_mode(node);
1285 if (mode_is_float(mode)) {
1286 if (ia32_cg_config.use_sse2)
1287 return gen_binop(node, op1, op2, new_bd_ia32_xMul,
1288 match_commutative | match_am);
1290 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfmul);
1292 return gen_binop(node, op1, op2, new_bd_ia32_IMul,
1293 match_commutative | match_am | match_mode_neutral |
1294 match_immediate | match_am_and_immediates);
1298 * Creates an ia32 Mulh.
1299 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1300 * this result while Mul returns the lower 32 bit.
1302 * @return the created ia32 Mulh node
1304 static ir_node *gen_Mulh(ir_node *node)
1306 ir_node *block = get_nodes_block(node);
1307 ir_node *new_block = be_transform_node(block);
1308 dbg_info *dbgi = get_irn_dbg_info(node);
1309 ir_node *op1 = get_Mulh_left(node);
1310 ir_node *op2 = get_Mulh_right(node);
1311 ir_mode *mode = get_irn_mode(node);
1313 ir_node *proj_res_high;
1315 if (get_mode_size_bits(mode) != 32) {
1316 panic("Mulh without 32bit size not supported in ia32 backend (%+F)", node);
1319 if (mode_is_signed(mode)) {
1320 new_node = gen_binop(node, op1, op2, new_bd_ia32_IMul1OP, match_commutative | match_am);
1321 proj_res_high = new_rd_Proj(dbgi, new_block, new_node, mode_Iu, pn_ia32_IMul1OP_res_high);
1323 new_node = gen_binop(node, op1, op2, new_bd_ia32_Mul, match_commutative | match_am);
1324 proj_res_high = new_rd_Proj(dbgi, new_block, new_node, mode_Iu, pn_ia32_Mul_res_high);
1326 return proj_res_high;
1330 * Creates an ia32 And.
1332 * @return The created ia32 And node
1334 static ir_node *gen_And(ir_node *node)
1336 ir_node *op1 = get_And_left(node);
1337 ir_node *op2 = get_And_right(node);
1338 assert(! mode_is_float(get_irn_mode(node)));
1340 /* is it a zero extension? */
1341 if (is_Const(op2)) {
1342 tarval *tv = get_Const_tarval(op2);
1343 long v = get_tarval_long(tv);
1345 if (v == 0xFF || v == 0xFFFF) {
1346 dbg_info *dbgi = get_irn_dbg_info(node);
1347 ir_node *block = get_nodes_block(node);
1354 assert(v == 0xFFFF);
1357 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1362 return gen_binop(node, op1, op2, new_bd_ia32_And,
1363 match_commutative | match_mode_neutral | match_am | match_immediate);
1369 * Creates an ia32 Or.
1371 * @return The created ia32 Or node
1373 static ir_node *gen_Or(ir_node *node)
1375 ir_node *op1 = get_Or_left(node);
1376 ir_node *op2 = get_Or_right(node);
1378 assert (! mode_is_float(get_irn_mode(node)));
1379 return gen_binop(node, op1, op2, new_bd_ia32_Or, match_commutative
1380 | match_mode_neutral | match_am | match_immediate);
1386 * Creates an ia32 Eor.
1388 * @return The created ia32 Eor node
1390 static ir_node *gen_Eor(ir_node *node)
1392 ir_node *op1 = get_Eor_left(node);
1393 ir_node *op2 = get_Eor_right(node);
1395 assert(! mode_is_float(get_irn_mode(node)));
1396 return gen_binop(node, op1, op2, new_bd_ia32_Xor, match_commutative
1397 | match_mode_neutral | match_am | match_immediate);
1402 * Creates an ia32 Sub.
1404 * @return The created ia32 Sub node
1406 static ir_node *gen_Sub(ir_node *node)
1408 ir_node *op1 = get_Sub_left(node);
1409 ir_node *op2 = get_Sub_right(node);
1410 ir_mode *mode = get_irn_mode(node);
1412 if (mode_is_float(mode)) {
1413 if (ia32_cg_config.use_sse2)
1414 return gen_binop(node, op1, op2, new_bd_ia32_xSub, match_am);
1416 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfsub);
1419 if (is_Const(op2)) {
1420 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1424 return gen_binop(node, op1, op2, new_bd_ia32_Sub, match_mode_neutral
1425 | match_am | match_immediate);
1428 static ir_node *transform_AM_mem(ir_node *const block,
1429 ir_node *const src_val,
1430 ir_node *const src_mem,
1431 ir_node *const am_mem)
1433 if (is_NoMem(am_mem)) {
1434 return be_transform_node(src_mem);
1435 } else if (is_Proj(src_val) &&
1437 get_Proj_pred(src_val) == get_Proj_pred(src_mem)) {
1438 /* avoid memory loop */
1440 } else if (is_Proj(src_val) && is_Sync(src_mem)) {
1441 ir_node *const ptr_pred = get_Proj_pred(src_val);
1442 int const arity = get_Sync_n_preds(src_mem);
1447 NEW_ARR_A(ir_node*, ins, arity + 1);
1449 /* NOTE: This sometimes produces dead-code because the old sync in
1450 * src_mem might not be used anymore, we should detect this case
1451 * and kill the sync... */
1452 for (i = arity - 1; i >= 0; --i) {
1453 ir_node *const pred = get_Sync_pred(src_mem, i);
1455 /* avoid memory loop */
1456 if (is_Proj(pred) && get_Proj_pred(pred) == ptr_pred)
1459 ins[n++] = be_transform_node(pred);
1464 return new_r_Sync(block, n, ins);
1468 ins[0] = be_transform_node(src_mem);
1470 return new_r_Sync(block, 2, ins);
1475 * Create a 32bit to 64bit signed extension.
1477 * @param dbgi debug info
1478 * @param block the block where node nodes should be placed
1479 * @param val the value to extend
1480 * @param orig the original node
1482 static ir_node *create_sex_32_64(dbg_info *dbgi, ir_node *block,
1483 ir_node *val, const ir_node *orig)
1488 if (ia32_cg_config.use_short_sex_eax) {
1489 ir_node *pval = new_bd_ia32_ProduceVal(dbgi, block);
1490 be_dep_on_frame(pval);
1491 res = new_bd_ia32_Cltd(dbgi, block, val, pval);
1493 ir_node *imm31 = ia32_create_Immediate(NULL, 0, 31);
1494 res = new_bd_ia32_Sar(dbgi, block, val, imm31);
1496 SET_IA32_ORIG_NODE(res, orig);
1501 * Generates an ia32 DivMod with additional infrastructure for the
1502 * register allocator if needed.
1504 static ir_node *create_Div(ir_node *node)
1506 dbg_info *dbgi = get_irn_dbg_info(node);
1507 ir_node *block = get_nodes_block(node);
1508 ir_node *new_block = be_transform_node(block);
1515 ir_node *sign_extension;
1516 ia32_address_mode_t am;
1517 ia32_address_t *addr = &am.addr;
1519 /* the upper bits have random contents for smaller modes */
1520 switch (get_irn_opcode(node)) {
1522 op1 = get_Div_left(node);
1523 op2 = get_Div_right(node);
1524 mem = get_Div_mem(node);
1525 mode = get_Div_resmode(node);
1528 op1 = get_Mod_left(node);
1529 op2 = get_Mod_right(node);
1530 mem = get_Mod_mem(node);
1531 mode = get_Mod_resmode(node);
1534 op1 = get_DivMod_left(node);
1535 op2 = get_DivMod_right(node);
1536 mem = get_DivMod_mem(node);
1537 mode = get_DivMod_resmode(node);
1540 panic("invalid divmod node %+F", node);
1543 match_arguments(&am, block, op1, op2, NULL, match_am | match_upconv_32);
1545 /* Beware: We don't need a Sync, if the memory predecessor of the Div node
1546 is the memory of the consumed address. We can have only the second op as address
1547 in Div nodes, so check only op2. */
1548 new_mem = transform_AM_mem(block, op2, mem, addr->mem);
1550 if (mode_is_signed(mode)) {
1551 sign_extension = create_sex_32_64(dbgi, new_block, am.new_op1, node);
1552 new_node = new_bd_ia32_IDiv(dbgi, new_block, addr->base,
1553 addr->index, new_mem, am.new_op2, am.new_op1, sign_extension);
1555 sign_extension = new_bd_ia32_Const(dbgi, new_block, NULL, 0, 0, 0);
1556 be_dep_on_frame(sign_extension);
1558 new_node = new_bd_ia32_Div(dbgi, new_block, addr->base,
1559 addr->index, new_mem, am.new_op2,
1560 am.new_op1, sign_extension);
1563 set_irn_pinned(new_node, get_irn_pinned(node));
1565 set_am_attributes(new_node, &am);
1566 SET_IA32_ORIG_NODE(new_node, node);
1568 new_node = fix_mem_proj(new_node, &am);
1574 * Generates an ia32 Mod.
1576 static ir_node *gen_Mod(ir_node *node)
1578 return create_Div(node);
1582 * Generates an ia32 Div.
1584 static ir_node *gen_Div(ir_node *node)
1586 return create_Div(node);
1590 * Generates an ia32 DivMod.
1592 static ir_node *gen_DivMod(ir_node *node)
1594 return create_Div(node);
1600 * Creates an ia32 floating Div.
1602 * @return The created ia32 xDiv node
1604 static ir_node *gen_Quot(ir_node *node)
1606 ir_node *op1 = get_Quot_left(node);
1607 ir_node *op2 = get_Quot_right(node);
1609 if (ia32_cg_config.use_sse2) {
1610 return gen_binop(node, op1, op2, new_bd_ia32_xDiv, match_am);
1612 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfdiv);
1618 * Creates an ia32 Shl.
1620 * @return The created ia32 Shl node
1622 static ir_node *gen_Shl(ir_node *node)
1624 ir_node *left = get_Shl_left(node);
1625 ir_node *right = get_Shl_right(node);
1627 return gen_shift_binop(node, left, right, new_bd_ia32_Shl,
1628 match_mode_neutral | match_immediate);
1632 * Creates an ia32 Shr.
1634 * @return The created ia32 Shr node
1636 static ir_node *gen_Shr(ir_node *node)
1638 ir_node *left = get_Shr_left(node);
1639 ir_node *right = get_Shr_right(node);
1641 return gen_shift_binop(node, left, right, new_bd_ia32_Shr, match_immediate);
1647 * Creates an ia32 Sar.
1649 * @return The created ia32 Shrs node
1651 static ir_node *gen_Shrs(ir_node *node)
1653 ir_node *left = get_Shrs_left(node);
1654 ir_node *right = get_Shrs_right(node);
1656 if (is_Const(right)) {
1657 tarval *tv = get_Const_tarval(right);
1658 long val = get_tarval_long(tv);
1660 /* this is a sign extension */
1661 dbg_info *dbgi = get_irn_dbg_info(node);
1662 ir_node *block = be_transform_node(get_nodes_block(node));
1663 ir_node *new_op = be_transform_node(left);
1665 return create_sex_32_64(dbgi, block, new_op, node);
1669 /* 8 or 16 bit sign extension? */
1670 if (is_Const(right) && is_Shl(left)) {
1671 ir_node *shl_left = get_Shl_left(left);
1672 ir_node *shl_right = get_Shl_right(left);
1673 if (is_Const(shl_right)) {
1674 tarval *tv1 = get_Const_tarval(right);
1675 tarval *tv2 = get_Const_tarval(shl_right);
1676 if (tv1 == tv2 && tarval_is_long(tv1)) {
1677 long val = get_tarval_long(tv1);
1678 if (val == 16 || val == 24) {
1679 dbg_info *dbgi = get_irn_dbg_info(node);
1680 ir_node *block = get_nodes_block(node);
1690 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1699 return gen_shift_binop(node, left, right, new_bd_ia32_Sar, match_immediate);
1705 * Creates an ia32 Rol.
1707 * @param op1 The first operator
1708 * @param op2 The second operator
1709 * @return The created ia32 RotL node
1711 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
1713 return gen_shift_binop(node, op1, op2, new_bd_ia32_Rol, match_immediate);
1719 * Creates an ia32 Ror.
1720 * NOTE: There is no RotR with immediate because this would always be a RotL
1721 * "imm-mode_size_bits" which can be pre-calculated.
1723 * @param op1 The first operator
1724 * @param op2 The second operator
1725 * @return The created ia32 RotR node
1727 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
1729 return gen_shift_binop(node, op1, op2, new_bd_ia32_Ror, match_immediate);
1735 * Creates an ia32 RotR or RotL (depending on the found pattern).
1737 * @return The created ia32 RotL or RotR node
1739 static ir_node *gen_Rotl(ir_node *node)
1741 ir_node *rotate = NULL;
1742 ir_node *op1 = get_Rotl_left(node);
1743 ir_node *op2 = get_Rotl_right(node);
1745 /* Firm has only RotL, so we are looking for a right (op2)
1746 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1747 that means we can create a RotR instead of an Add and a RotL */
1751 ir_node *left = get_Add_left(add);
1752 ir_node *right = get_Add_right(add);
1753 if (is_Const(right)) {
1754 tarval *tv = get_Const_tarval(right);
1755 ir_mode *mode = get_irn_mode(node);
1756 long bits = get_mode_size_bits(mode);
1758 if (is_Minus(left) &&
1759 tarval_is_long(tv) &&
1760 get_tarval_long(tv) == bits &&
1763 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1764 rotate = gen_Ror(node, op1, get_Minus_op(left));
1769 if (rotate == NULL) {
1770 rotate = gen_Rol(node, op1, op2);
1779 * Transforms a Minus node.
1781 * @return The created ia32 Minus node
1783 static ir_node *gen_Minus(ir_node *node)
1785 ir_node *op = get_Minus_op(node);
1786 ir_node *block = be_transform_node(get_nodes_block(node));
1787 dbg_info *dbgi = get_irn_dbg_info(node);
1788 ir_mode *mode = get_irn_mode(node);
1793 if (mode_is_float(mode)) {
1794 ir_node *new_op = be_transform_node(op);
1795 if (ia32_cg_config.use_sse2) {
1796 /* TODO: non-optimal... if we have many xXors, then we should
1797 * rather create a load for the const and use that instead of
1798 * several AM nodes... */
1799 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1801 new_node = new_bd_ia32_xXor(dbgi, block, get_symconst_base(),
1802 noreg_GP, nomem, new_op, noreg_xmm);
1804 size = get_mode_size_bits(mode);
1805 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1807 set_ia32_am_sc(new_node, ent);
1808 set_ia32_op_type(new_node, ia32_AddrModeS);
1809 set_ia32_ls_mode(new_node, mode);
1811 new_node = new_bd_ia32_vfchs(dbgi, block, new_op);
1814 new_node = gen_unop(node, op, new_bd_ia32_Neg, match_mode_neutral);
1817 SET_IA32_ORIG_NODE(new_node, node);
1823 * Transforms a Not node.
1825 * @return The created ia32 Not node
1827 static ir_node *gen_Not(ir_node *node)
1829 ir_node *op = get_Not_op(node);
1831 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1832 assert (! mode_is_float(get_irn_mode(node)));
1834 return gen_unop(node, op, new_bd_ia32_Not, match_mode_neutral);
1840 * Transforms an Abs node.
1842 * @return The created ia32 Abs node
1844 static ir_node *gen_Abs(ir_node *node)
1846 ir_node *block = get_nodes_block(node);
1847 ir_node *new_block = be_transform_node(block);
1848 ir_node *op = get_Abs_op(node);
1849 dbg_info *dbgi = get_irn_dbg_info(node);
1850 ir_mode *mode = get_irn_mode(node);
1856 if (mode_is_float(mode)) {
1857 new_op = be_transform_node(op);
1859 if (ia32_cg_config.use_sse2) {
1860 ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg);
1861 new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(),
1862 noreg_GP, nomem, new_op, noreg_fp);
1864 size = get_mode_size_bits(mode);
1865 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1867 set_ia32_am_sc(new_node, ent);
1869 SET_IA32_ORIG_NODE(new_node, node);
1871 set_ia32_op_type(new_node, ia32_AddrModeS);
1872 set_ia32_ls_mode(new_node, mode);
1874 new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op);
1875 SET_IA32_ORIG_NODE(new_node, node);
1878 ir_node *xor, *sign_extension;
1880 if (get_mode_size_bits(mode) == 32) {
1881 new_op = be_transform_node(op);
1883 new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node);
1886 sign_extension = create_sex_32_64(dbgi, new_block, new_op, node);
1888 xor = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP,
1889 nomem, new_op, sign_extension);
1890 SET_IA32_ORIG_NODE(xor, node);
1892 new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP,
1893 nomem, xor, sign_extension);
1894 SET_IA32_ORIG_NODE(new_node, node);
1901 * Create a bt instruction for x & (1 << n) and place it into the block of cmp.
1903 static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n)
1905 dbg_info *dbgi = get_irn_dbg_info(cmp);
1906 ir_node *block = get_nodes_block(cmp);
1907 ir_node *new_block = be_transform_node(block);
1908 ir_node *op1 = be_transform_node(x);
1909 ir_node *op2 = be_transform_node(n);
1911 return new_bd_ia32_Bt(dbgi, new_block, op1, op2);
1915 * Transform a node returning a "flag" result.
1917 * @param node the node to transform
1918 * @param pnc_out the compare mode to use
1920 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
1927 /* we have a Cmp as input */
1928 if (is_Proj(node)) {
1929 ir_node *pred = get_Proj_pred(node);
1931 pn_Cmp pnc = get_Proj_proj(node);
1932 if (ia32_cg_config.use_bt && (pnc == pn_Cmp_Lg || pnc == pn_Cmp_Eq)) {
1933 ir_node *l = get_Cmp_left(pred);
1934 ir_node *r = get_Cmp_right(pred);
1936 ir_node *la = get_And_left(l);
1937 ir_node *ra = get_And_right(l);
1939 ir_node *c = get_Shl_left(la);
1940 if (is_Const_1(c) && (is_Const_0(r) || r == la)) {
1941 /* (1 << n) & ra) */
1942 ir_node *n = get_Shl_right(la);
1943 flags = gen_bt(pred, ra, n);
1944 /* we must generate a Jc/Jnc jump */
1945 pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge;
1948 *pnc_out = ia32_pn_Cmp_unsigned | pnc;
1953 ir_node *c = get_Shl_left(ra);
1954 if (is_Const_1(c) && (is_Const_0(r) || r == ra)) {
1955 /* la & (1 << n)) */
1956 ir_node *n = get_Shl_right(ra);
1957 flags = gen_bt(pred, la, n);
1958 /* we must generate a Jc/Jnc jump */
1959 pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge;
1962 *pnc_out = ia32_pn_Cmp_unsigned | pnc;
1968 /* add ia32 compare flags */
1970 ir_node *l = get_Cmp_left(pred);
1971 ir_mode *mode = get_irn_mode(l);
1972 if (mode_is_float(mode))
1973 pnc |= ia32_pn_Cmp_float;
1974 else if (! mode_is_signed(mode))
1975 pnc |= ia32_pn_Cmp_unsigned;
1978 flags = be_transform_node(pred);
1983 /* a mode_b value, we have to compare it against 0 */
1984 dbgi = get_irn_dbg_info(node);
1985 new_block = be_transform_node(get_nodes_block(node));
1986 new_op = be_transform_node(node);
1987 flags = new_bd_ia32_Test(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op,
1988 new_op, /*is_permuted=*/0, /*cmp_unsigned=*/0);
1989 *pnc_out = pn_Cmp_Lg;
1994 * Transforms a Load.
1996 * @return the created ia32 Load node
1998 static ir_node *gen_Load(ir_node *node)
2000 ir_node *old_block = get_nodes_block(node);
2001 ir_node *block = be_transform_node(old_block);
2002 ir_node *ptr = get_Load_ptr(node);
2003 ir_node *mem = get_Load_mem(node);
2004 ir_node *new_mem = be_transform_node(mem);
2007 dbg_info *dbgi = get_irn_dbg_info(node);
2008 ir_mode *mode = get_Load_mode(node);
2011 ia32_address_t addr;
2013 /* construct load address */
2014 memset(&addr, 0, sizeof(addr));
2015 ia32_create_address_mode(&addr, ptr, 0);
2022 base = be_transform_node(base);
2025 if (index == NULL) {
2028 index = be_transform_node(index);
2031 if (mode_is_float(mode)) {
2032 if (ia32_cg_config.use_sse2) {
2033 new_node = new_bd_ia32_xLoad(dbgi, block, base, index, new_mem,
2035 res_mode = mode_xmm;
2037 new_node = new_bd_ia32_vfld(dbgi, block, base, index, new_mem,
2039 res_mode = mode_vfp;
2042 assert(mode != mode_b);
2044 /* create a conv node with address mode for smaller modes */
2045 if (get_mode_size_bits(mode) < 32) {
2046 new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, index,
2047 new_mem, noreg_GP, mode);
2049 new_node = new_bd_ia32_Load(dbgi, block, base, index, new_mem);
2054 set_irn_pinned(new_node, get_irn_pinned(node));
2055 set_ia32_op_type(new_node, ia32_AddrModeS);
2056 set_ia32_ls_mode(new_node, mode);
2057 set_address(new_node, &addr);
2059 if (get_irn_pinned(node) == op_pin_state_floats) {
2060 assert(pn_ia32_xLoad_res == pn_ia32_vfld_res
2061 && pn_ia32_vfld_res == pn_ia32_Load_res
2062 && pn_ia32_Load_res == pn_ia32_res);
2063 arch_irn_add_flags(new_node, arch_irn_flags_rematerializable);
2066 SET_IA32_ORIG_NODE(new_node, node);
2068 be_dep_on_frame(new_node);
2072 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
2073 ir_node *ptr, ir_node *other)
2080 /* we only use address mode if we're the only user of the load */
2081 if (get_irn_n_edges(node) > 1)
2084 load = get_Proj_pred(node);
2087 if (get_nodes_block(load) != block)
2090 /* store should have the same pointer as the load */
2091 if (get_Load_ptr(load) != ptr)
2094 /* don't do AM if other node inputs depend on the load (via mem-proj) */
2095 if (other != NULL &&
2096 get_nodes_block(other) == block &&
2097 heights_reachable_in_block(heights, other, load)) {
2101 if (prevents_AM(block, load, mem))
2103 /* Store should be attached to the load via mem */
2104 assert(heights_reachable_in_block(heights, mem, load));
2109 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
2110 ir_node *mem, ir_node *ptr, ir_mode *mode,
2111 construct_binop_dest_func *func,
2112 construct_binop_dest_func *func8bit,
2113 match_flags_t flags)
2115 ir_node *src_block = get_nodes_block(node);
2123 ia32_address_mode_t am;
2124 ia32_address_t *addr = &am.addr;
2125 memset(&am, 0, sizeof(am));
2127 assert(flags & match_immediate); /* there is no destam node without... */
2128 commutative = (flags & match_commutative) != 0;
2130 if (use_dest_am(src_block, op1, mem, ptr, op2)) {
2131 build_address(&am, op1, ia32_create_am_double_use);
2132 new_op = create_immediate_or_transform(op2, 0);
2133 } else if (commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
2134 build_address(&am, op2, ia32_create_am_double_use);
2135 new_op = create_immediate_or_transform(op1, 0);
2140 if (addr->base == NULL)
2141 addr->base = noreg_GP;
2142 if (addr->index == NULL)
2143 addr->index = noreg_GP;
2144 if (addr->mem == NULL)
2147 dbgi = get_irn_dbg_info(node);
2148 block = be_transform_node(src_block);
2149 new_mem = transform_AM_mem(block, am.am_node, mem, addr->mem);
2151 if (get_mode_size_bits(mode) == 8) {
2152 new_node = func8bit(dbgi, block, addr->base, addr->index, new_mem, new_op);
2154 new_node = func(dbgi, block, addr->base, addr->index, new_mem, new_op);
2156 set_address(new_node, addr);
2157 set_ia32_op_type(new_node, ia32_AddrModeD);
2158 set_ia32_ls_mode(new_node, mode);
2159 SET_IA32_ORIG_NODE(new_node, node);
2161 be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
2162 mem_proj = be_transform_node(am.mem_proj);
2163 be_set_transformed_node(mem_proj ? mem_proj : am.mem_proj, new_node);
2168 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
2169 ir_node *ptr, ir_mode *mode,
2170 construct_unop_dest_func *func)
2172 ir_node *src_block = get_nodes_block(node);
2178 ia32_address_mode_t am;
2179 ia32_address_t *addr = &am.addr;
2181 if (!use_dest_am(src_block, op, mem, ptr, NULL))
2184 memset(&am, 0, sizeof(am));
2185 build_address(&am, op, ia32_create_am_double_use);
2187 dbgi = get_irn_dbg_info(node);
2188 block = be_transform_node(src_block);
2189 new_mem = transform_AM_mem(block, am.am_node, mem, addr->mem);
2190 new_node = func(dbgi, block, addr->base, addr->index, new_mem);
2191 set_address(new_node, addr);
2192 set_ia32_op_type(new_node, ia32_AddrModeD);
2193 set_ia32_ls_mode(new_node, mode);
2194 SET_IA32_ORIG_NODE(new_node, node);
2196 be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
2197 mem_proj = be_transform_node(am.mem_proj);
2198 be_set_transformed_node(mem_proj ? mem_proj : am.mem_proj, new_node);
2203 static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
2205 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
2206 return get_negated_pnc(pnc, mode);
2209 static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem)
2211 ir_mode *mode = get_irn_mode(node);
2212 ir_node *mux_true = get_Mux_true(node);
2213 ir_node *mux_false = get_Mux_false(node);
2223 ia32_address_t addr;
2225 if (get_mode_size_bits(mode) != 8)
2228 if (is_Const_1(mux_true) && is_Const_0(mux_false)) {
2230 } else if (is_Const_0(mux_true) && is_Const_1(mux_false)) {
2236 cond = get_Mux_sel(node);
2237 flags = get_flags_node(cond, &pnc);
2238 /* we can't handle the float special cases with SetM */
2239 if (pnc & ia32_pn_Cmp_float)
2242 pnc = ia32_get_negated_pnc(pnc);
2244 build_address_ptr(&addr, ptr, mem);
2246 dbgi = get_irn_dbg_info(node);
2247 block = get_nodes_block(node);
2248 new_block = be_transform_node(block);
2249 new_mem = be_transform_node(mem);
2250 new_node = new_bd_ia32_SetccMem(dbgi, new_block, addr.base,
2251 addr.index, addr.mem, flags, pnc);
2252 set_address(new_node, &addr);
2253 set_ia32_op_type(new_node, ia32_AddrModeD);
2254 set_ia32_ls_mode(new_node, mode);
2255 SET_IA32_ORIG_NODE(new_node, node);
2260 static ir_node *try_create_dest_am(ir_node *node)
2262 ir_node *val = get_Store_value(node);
2263 ir_node *mem = get_Store_mem(node);
2264 ir_node *ptr = get_Store_ptr(node);
2265 ir_mode *mode = get_irn_mode(val);
2266 unsigned bits = get_mode_size_bits(mode);
2271 /* handle only GP modes for now... */
2272 if (!ia32_mode_needs_gp_reg(mode))
2276 /* store must be the only user of the val node */
2277 if (get_irn_n_edges(val) > 1)
2279 /* skip pointless convs */
2281 ir_node *conv_op = get_Conv_op(val);
2282 ir_mode *pred_mode = get_irn_mode(conv_op);
2283 if (!ia32_mode_needs_gp_reg(pred_mode))
2285 if (pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
2293 /* value must be in the same block */
2294 if (get_nodes_block(node) != get_nodes_block(val))
2297 switch (get_irn_opcode(val)) {
2299 op1 = get_Add_left(val);
2300 op2 = get_Add_right(val);
2301 if (ia32_cg_config.use_incdec) {
2302 if (is_Const_1(op2)) {
2303 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_IncMem);
2305 } else if (is_Const_Minus_1(op2)) {
2306 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_DecMem);
2310 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2311 new_bd_ia32_AddMem, new_bd_ia32_AddMem8Bit,
2312 match_commutative | match_immediate);
2315 op1 = get_Sub_left(val);
2316 op2 = get_Sub_right(val);
2317 if (is_Const(op2)) {
2318 ir_fprintf(stderr, "Optimisation warning: not-normalized sub ,C found\n");
2320 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2321 new_bd_ia32_SubMem, new_bd_ia32_SubMem8Bit,
2325 op1 = get_And_left(val);
2326 op2 = get_And_right(val);
2327 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2328 new_bd_ia32_AndMem, new_bd_ia32_AndMem8Bit,
2329 match_commutative | match_immediate);
2332 op1 = get_Or_left(val);
2333 op2 = get_Or_right(val);
2334 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2335 new_bd_ia32_OrMem, new_bd_ia32_OrMem8Bit,
2336 match_commutative | match_immediate);
2339 op1 = get_Eor_left(val);
2340 op2 = get_Eor_right(val);
2341 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2342 new_bd_ia32_XorMem, new_bd_ia32_XorMem8Bit,
2343 match_commutative | match_immediate);
2346 op1 = get_Shl_left(val);
2347 op2 = get_Shl_right(val);
2348 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2349 new_bd_ia32_ShlMem, new_bd_ia32_ShlMem,
2353 op1 = get_Shr_left(val);
2354 op2 = get_Shr_right(val);
2355 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2356 new_bd_ia32_ShrMem, new_bd_ia32_ShrMem,
2360 op1 = get_Shrs_left(val);
2361 op2 = get_Shrs_right(val);
2362 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2363 new_bd_ia32_SarMem, new_bd_ia32_SarMem,
2367 op1 = get_Rotl_left(val);
2368 op2 = get_Rotl_right(val);
2369 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2370 new_bd_ia32_RolMem, new_bd_ia32_RolMem,
2373 /* TODO: match ROR patterns... */
2375 new_node = try_create_SetMem(val, ptr, mem);
2379 op1 = get_Minus_op(val);
2380 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NegMem);
2383 /* should be lowered already */
2384 assert(mode != mode_b);
2385 op1 = get_Not_op(val);
2386 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NotMem);
2392 if (new_node != NULL) {
2393 if (get_irn_pinned(new_node) != op_pin_state_pinned &&
2394 get_irn_pinned(node) == op_pin_state_pinned) {
2395 set_irn_pinned(new_node, op_pin_state_pinned);
2402 static bool possible_int_mode_for_fp(ir_mode *mode)
2406 if (!mode_is_signed(mode))
2408 size = get_mode_size_bits(mode);
2409 if (size != 16 && size != 32)
2414 static int is_float_to_int_conv(const ir_node *node)
2416 ir_mode *mode = get_irn_mode(node);
2420 if (!possible_int_mode_for_fp(mode))
2425 conv_op = get_Conv_op(node);
2426 conv_mode = get_irn_mode(conv_op);
2428 if (!mode_is_float(conv_mode))
2435 * Transform a Store(floatConst) into a sequence of
2438 * @return the created ia32 Store node
2440 static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns)
2442 ir_mode *mode = get_irn_mode(cns);
2443 unsigned size = get_mode_size_bytes(mode);
2444 tarval *tv = get_Const_tarval(cns);
2445 ir_node *block = get_nodes_block(node);
2446 ir_node *new_block = be_transform_node(block);
2447 ir_node *ptr = get_Store_ptr(node);
2448 ir_node *mem = get_Store_mem(node);
2449 dbg_info *dbgi = get_irn_dbg_info(node);
2453 ia32_address_t addr;
2455 assert(size % 4 == 0);
2458 build_address_ptr(&addr, ptr, mem);
2462 get_tarval_sub_bits(tv, ofs) |
2463 (get_tarval_sub_bits(tv, ofs + 1) << 8) |
2464 (get_tarval_sub_bits(tv, ofs + 2) << 16) |
2465 (get_tarval_sub_bits(tv, ofs + 3) << 24);
2466 ir_node *imm = ia32_create_Immediate(NULL, 0, val);
2468 ir_node *new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
2469 addr.index, addr.mem, imm);
2471 set_irn_pinned(new_node, get_irn_pinned(node));
2472 set_ia32_op_type(new_node, ia32_AddrModeD);
2473 set_ia32_ls_mode(new_node, mode_Iu);
2474 set_address(new_node, &addr);
2475 SET_IA32_ORIG_NODE(new_node, node);
2478 ins[i++] = new_node;
2483 } while (size != 0);
2486 return new_rd_Sync(dbgi, new_block, i, ins);
2493 * Generate a vfist or vfisttp instruction.
2495 static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index,
2496 ir_node *mem, ir_node *val, ir_node **fist)
2500 if (ia32_cg_config.use_fisttp) {
2501 /* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied
2502 if other users exists */
2503 ir_node *vfisttp = new_bd_ia32_vfisttp(dbgi, block, base, index, mem, val);
2504 ir_node *value = new_r_Proj(block, vfisttp, mode_E, pn_ia32_vfisttp_res);
2505 be_new_Keep(block, 1, &value);
2507 new_node = new_r_Proj(block, vfisttp, mode_M, pn_ia32_vfisttp_M);
2510 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
2513 new_node = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode);
2519 * Transforms a general (no special case) Store.
2521 * @return the created ia32 Store node
2523 static ir_node *gen_general_Store(ir_node *node)
2525 ir_node *val = get_Store_value(node);
2526 ir_mode *mode = get_irn_mode(val);
2527 ir_node *block = get_nodes_block(node);
2528 ir_node *new_block = be_transform_node(block);
2529 ir_node *ptr = get_Store_ptr(node);
2530 ir_node *mem = get_Store_mem(node);
2531 dbg_info *dbgi = get_irn_dbg_info(node);
2532 ir_node *new_val, *new_node, *store;
2533 ia32_address_t addr;
2535 /* check for destination address mode */
2536 new_node = try_create_dest_am(node);
2537 if (new_node != NULL)
2540 /* construct store address */
2541 memset(&addr, 0, sizeof(addr));
2542 ia32_create_address_mode(&addr, ptr, 0);
2544 if (addr.base == NULL) {
2545 addr.base = noreg_GP;
2547 addr.base = be_transform_node(addr.base);
2550 if (addr.index == NULL) {
2551 addr.index = noreg_GP;
2553 addr.index = be_transform_node(addr.index);
2555 addr.mem = be_transform_node(mem);
2557 if (mode_is_float(mode)) {
2558 /* Convs (and strict-Convs) before stores are unnecessary if the mode
2560 while (is_Conv(val) && mode == get_irn_mode(val)) {
2561 ir_node *op = get_Conv_op(val);
2562 if (!mode_is_float(get_irn_mode(op)))
2566 new_val = be_transform_node(val);
2567 if (ia32_cg_config.use_sse2) {
2568 new_node = new_bd_ia32_xStore(dbgi, new_block, addr.base,
2569 addr.index, addr.mem, new_val);
2571 new_node = new_bd_ia32_vfst(dbgi, new_block, addr.base,
2572 addr.index, addr.mem, new_val, mode);
2575 } else if (!ia32_cg_config.use_sse2 && is_float_to_int_conv(val)) {
2576 val = get_Conv_op(val);
2578 /* TODO: is this optimisation still necessary at all (middleend)? */
2579 /* We can skip ALL float->float up-Convs (and strict-up-Convs) before stores. */
2580 while (is_Conv(val)) {
2581 ir_node *op = get_Conv_op(val);
2582 if (!mode_is_float(get_irn_mode(op)))
2584 if (get_mode_size_bits(get_irn_mode(op)) > get_mode_size_bits(get_irn_mode(val)))
2588 new_val = be_transform_node(val);
2589 new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val, &store);
2591 new_val = create_immediate_or_transform(val, 0);
2592 assert(mode != mode_b);
2594 if (get_mode_size_bits(mode) == 8) {
2595 new_node = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
2596 addr.index, addr.mem, new_val);
2598 new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
2599 addr.index, addr.mem, new_val);
2604 set_irn_pinned(store, get_irn_pinned(node));
2605 set_ia32_op_type(store, ia32_AddrModeD);
2606 set_ia32_ls_mode(store, mode);
2608 set_address(store, &addr);
2609 SET_IA32_ORIG_NODE(store, node);
2615 * Transforms a Store.
2617 * @return the created ia32 Store node
2619 static ir_node *gen_Store(ir_node *node)
2621 ir_node *val = get_Store_value(node);
2622 ir_mode *mode = get_irn_mode(val);
2624 if (mode_is_float(mode) && is_Const(val)) {
2625 /* We can transform every floating const store
2626 into a sequence of integer stores.
2627 If the constant is already in a register,
2628 it would be better to use it, but we don't
2629 have this information here. */
2630 return gen_float_const_Store(node, val);
2632 return gen_general_Store(node);
2636 * Transforms a Switch.
2638 * @return the created ia32 SwitchJmp node
2640 static ir_node *create_Switch(ir_node *node)
2642 dbg_info *dbgi = get_irn_dbg_info(node);
2643 ir_node *block = be_transform_node(get_nodes_block(node));
2644 ir_node *sel = get_Cond_selector(node);
2645 ir_node *new_sel = be_transform_node(sel);
2646 long switch_min = LONG_MAX;
2647 long switch_max = LONG_MIN;
2648 long default_pn = get_Cond_default_proj(node);
2650 const ir_edge_t *edge;
2652 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2654 /* determine the smallest switch case value */
2655 foreach_out_edge(node, edge) {
2656 ir_node *proj = get_edge_src_irn(edge);
2657 long pn = get_Proj_proj(proj);
2658 if (pn == default_pn)
2661 if (pn < switch_min)
2663 if (pn > switch_max)
2667 if ((unsigned long) (switch_max - switch_min) > 128000) {
2668 panic("Size of switch %+F bigger than 128000", node);
2671 if (switch_min != 0) {
2672 /* if smallest switch case is not 0 we need an additional sub */
2673 new_sel = new_bd_ia32_Lea(dbgi, block, new_sel, noreg_GP);
2674 add_ia32_am_offs_int(new_sel, -switch_min);
2675 set_ia32_op_type(new_sel, ia32_AddrModeS);
2677 SET_IA32_ORIG_NODE(new_sel, node);
2680 new_node = new_bd_ia32_SwitchJmp(dbgi, block, new_sel, default_pn);
2681 SET_IA32_ORIG_NODE(new_node, node);
2687 * Transform a Cond node.
2689 static ir_node *gen_Cond(ir_node *node)
2691 ir_node *block = get_nodes_block(node);
2692 ir_node *new_block = be_transform_node(block);
2693 dbg_info *dbgi = get_irn_dbg_info(node);
2694 ir_node *sel = get_Cond_selector(node);
2695 ir_mode *sel_mode = get_irn_mode(sel);
2696 ir_node *flags = NULL;
2700 if (sel_mode != mode_b) {
2701 return create_Switch(node);
2704 /* we get flags from a Cmp */
2705 flags = get_flags_node(sel, &pnc);
2707 new_node = new_bd_ia32_Jcc(dbgi, new_block, flags, pnc);
2708 SET_IA32_ORIG_NODE(new_node, node);
2714 * Transform a be_Copy.
2716 static ir_node *gen_be_Copy(ir_node *node)
2718 ir_node *new_node = be_duplicate_node(node);
2719 ir_mode *mode = get_irn_mode(new_node);
2721 if (ia32_mode_needs_gp_reg(mode)) {
2722 set_irn_mode(new_node, mode_Iu);
2728 static ir_node *create_Fucom(ir_node *node)
2730 dbg_info *dbgi = get_irn_dbg_info(node);
2731 ir_node *block = get_nodes_block(node);
2732 ir_node *new_block = be_transform_node(block);
2733 ir_node *left = get_Cmp_left(node);
2734 ir_node *new_left = be_transform_node(left);
2735 ir_node *right = get_Cmp_right(node);
2739 if (ia32_cg_config.use_fucomi) {
2740 new_right = be_transform_node(right);
2741 new_node = new_bd_ia32_vFucomi(dbgi, new_block, new_left,
2743 set_ia32_commutative(new_node);
2744 SET_IA32_ORIG_NODE(new_node, node);
2746 if (ia32_cg_config.use_ftst && is_Const_0(right)) {
2747 new_node = new_bd_ia32_vFtstFnstsw(dbgi, new_block, new_left, 0);
2749 new_right = be_transform_node(right);
2750 new_node = new_bd_ia32_vFucomFnstsw(dbgi, new_block, new_left, new_right, 0);
2753 set_ia32_commutative(new_node);
2755 SET_IA32_ORIG_NODE(new_node, node);
2757 new_node = new_bd_ia32_Sahf(dbgi, new_block, new_node);
2758 SET_IA32_ORIG_NODE(new_node, node);
2764 static ir_node *create_Ucomi(ir_node *node)
2766 dbg_info *dbgi = get_irn_dbg_info(node);
2767 ir_node *src_block = get_nodes_block(node);
2768 ir_node *new_block = be_transform_node(src_block);
2769 ir_node *left = get_Cmp_left(node);
2770 ir_node *right = get_Cmp_right(node);
2772 ia32_address_mode_t am;
2773 ia32_address_t *addr = &am.addr;
2775 match_arguments(&am, src_block, left, right, NULL,
2776 match_commutative | match_am);
2778 new_node = new_bd_ia32_Ucomi(dbgi, new_block, addr->base, addr->index,
2779 addr->mem, am.new_op1, am.new_op2,
2781 set_am_attributes(new_node, &am);
2783 SET_IA32_ORIG_NODE(new_node, node);
2785 new_node = fix_mem_proj(new_node, &am);
2791 * helper function: checks whether all Cmp projs are Lg or Eq which is needed
2792 * to fold an and into a test node
2794 static bool can_fold_test_and(ir_node *node)
2796 const ir_edge_t *edge;
2798 /** we can only have eq and lg projs */
2799 foreach_out_edge(node, edge) {
2800 ir_node *proj = get_edge_src_irn(edge);
2801 pn_Cmp pnc = get_Proj_proj(proj);
2802 if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2810 * returns true if it is assured, that the upper bits of a node are "clean"
2811 * which means for a 16 or 8 bit value, that the upper bits in the register
2812 * are 0 for unsigned and a copy of the last significant bit for signed
2815 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
2817 assert(ia32_mode_needs_gp_reg(mode));
2818 if (get_mode_size_bits(mode) >= 32)
2821 if (is_Proj(transformed_node))
2822 return upper_bits_clean(get_Proj_pred(transformed_node), mode);
2824 switch (get_ia32_irn_opcode(transformed_node)) {
2825 case iro_ia32_Conv_I2I:
2826 case iro_ia32_Conv_I2I8Bit: {
2827 ir_mode *smaller_mode = get_ia32_ls_mode(transformed_node);
2828 if (mode_is_signed(smaller_mode) != mode_is_signed(mode))
2830 if (get_mode_size_bits(smaller_mode) > get_mode_size_bits(mode))
2837 if (mode_is_signed(mode)) {
2838 return false; /* TODO handle signed modes */
2840 ir_node *right = get_irn_n(transformed_node, n_ia32_Shr_count);
2841 if (is_ia32_Immediate(right) || is_ia32_Const(right)) {
2842 const ia32_immediate_attr_t *attr
2843 = get_ia32_immediate_attr_const(right);
2844 if (attr->symconst == 0 &&
2845 (unsigned)attr->offset >= 32 - get_mode_size_bits(mode)) {
2849 return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Shr_val), mode);
2853 /* TODO too conservative if shift amount is constant */
2854 return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Sar_val), mode);
2857 if (!mode_is_signed(mode)) {
2859 upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_right), mode) ||
2860 upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_left), mode);
2862 /* TODO if one is known to be zero extended, then || is sufficient */
2867 upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_right), mode) &&
2868 upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_left), mode);
2870 case iro_ia32_Const:
2871 case iro_ia32_Immediate: {
2872 const ia32_immediate_attr_t *attr =
2873 get_ia32_immediate_attr_const(transformed_node);
2874 if (mode_is_signed(mode)) {
2875 long shifted = attr->offset >> (get_mode_size_bits(mode) - 1);
2876 return shifted == 0 || shifted == -1;
2878 unsigned long shifted = (unsigned long)attr->offset;
2879 shifted >>= get_mode_size_bits(mode);
2880 return shifted == 0;
2890 * Generate code for a Cmp.
2892 static ir_node *gen_Cmp(ir_node *node)
2894 dbg_info *dbgi = get_irn_dbg_info(node);
2895 ir_node *block = get_nodes_block(node);
2896 ir_node *new_block = be_transform_node(block);
2897 ir_node *left = get_Cmp_left(node);
2898 ir_node *right = get_Cmp_right(node);
2899 ir_mode *cmp_mode = get_irn_mode(left);
2901 ia32_address_mode_t am;
2902 ia32_address_t *addr = &am.addr;
2905 if (mode_is_float(cmp_mode)) {
2906 if (ia32_cg_config.use_sse2) {
2907 return create_Ucomi(node);
2909 return create_Fucom(node);
2913 assert(ia32_mode_needs_gp_reg(cmp_mode));
2915 /* Prefer the Test instruction, when encountering (x & y) ==/!= 0 */
2916 cmp_unsigned = !mode_is_signed(cmp_mode);
2917 if (is_Const_0(right) &&
2919 get_irn_n_edges(left) == 1 &&
2920 can_fold_test_and(node)) {
2921 /* Test(and_left, and_right) */
2922 ir_node *and_left = get_And_left(left);
2923 ir_node *and_right = get_And_right(left);
2925 /* matze: code here used mode instead of cmd_mode, I think it is always
2926 * the same as cmp_mode, but I leave this here to see if this is really
2929 assert(get_irn_mode(and_left) == cmp_mode);
2931 match_arguments(&am, block, and_left, and_right, NULL,
2933 match_am | match_8bit_am | match_16bit_am |
2934 match_am_and_immediates | match_immediate);
2936 /* use 32bit compare mode if possible since the opcode is smaller */
2937 if (upper_bits_clean(am.new_op1, cmp_mode) &&
2938 upper_bits_clean(am.new_op2, cmp_mode)) {
2939 cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
2942 if (get_mode_size_bits(cmp_mode) == 8) {
2943 new_node = new_bd_ia32_Test8Bit(dbgi, new_block, addr->base,
2944 addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted,
2947 new_node = new_bd_ia32_Test(dbgi, new_block, addr->base, addr->index,
2948 addr->mem, am.new_op1, am.new_op2, am.ins_permuted, cmp_unsigned);
2951 /* Cmp(left, right) */
2952 match_arguments(&am, block, left, right, NULL,
2953 match_commutative | match_am | match_8bit_am |
2954 match_16bit_am | match_am_and_immediates |
2956 /* use 32bit compare mode if possible since the opcode is smaller */
2957 if (upper_bits_clean(am.new_op1, cmp_mode) &&
2958 upper_bits_clean(am.new_op2, cmp_mode)) {
2959 cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
2962 if (get_mode_size_bits(cmp_mode) == 8) {
2963 new_node = new_bd_ia32_Cmp8Bit(dbgi, new_block, addr->base,
2964 addr->index, addr->mem, am.new_op1,
2965 am.new_op2, am.ins_permuted,
2968 new_node = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index,
2969 addr->mem, am.new_op1, am.new_op2, am.ins_permuted, cmp_unsigned);
2972 set_am_attributes(new_node, &am);
2973 set_ia32_ls_mode(new_node, cmp_mode);
2975 SET_IA32_ORIG_NODE(new_node, node);
2977 new_node = fix_mem_proj(new_node, &am);
2982 static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags,
2985 dbg_info *dbgi = get_irn_dbg_info(node);
2986 ir_node *block = get_nodes_block(node);
2987 ir_node *new_block = be_transform_node(block);
2988 ir_node *val_true = get_Mux_true(node);
2989 ir_node *val_false = get_Mux_false(node);
2991 ia32_address_mode_t am;
2992 ia32_address_t *addr;
2994 assert(ia32_cg_config.use_cmov);
2995 assert(ia32_mode_needs_gp_reg(get_irn_mode(val_true)));
2999 match_arguments(&am, block, val_false, val_true, flags,
3000 match_commutative | match_am | match_16bit_am | match_mode_neutral);
3002 if (am.ins_permuted)
3003 pnc = ia32_get_negated_pnc(pnc);
3005 new_node = new_bd_ia32_CMovcc(dbgi, new_block, addr->base, addr->index,
3006 addr->mem, am.new_op1, am.new_op2, new_flags,
3008 set_am_attributes(new_node, &am);
3010 SET_IA32_ORIG_NODE(new_node, node);
3012 new_node = fix_mem_proj(new_node, &am);
3018 * Creates a ia32 Setcc instruction.
3020 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
3021 ir_node *flags, pn_Cmp pnc,
3024 ir_mode *mode = get_irn_mode(orig_node);
3027 new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, pnc);
3028 SET_IA32_ORIG_NODE(new_node, orig_node);
3030 /* we might need to conv the result up */
3031 if (get_mode_size_bits(mode) > 8) {
3032 new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP,
3033 nomem, new_node, mode_Bu);
3034 SET_IA32_ORIG_NODE(new_node, orig_node);
3041 * Create instruction for an unsigned Difference or Zero.
3043 static ir_node *create_doz(ir_node *psi, ir_node *a, ir_node *b)
3045 ir_mode *mode = get_irn_mode(psi);
3055 new_node = gen_binop(psi, a, b, new_bd_ia32_Sub,
3056 match_mode_neutral | match_am | match_immediate | match_two_users);
3058 block = get_nodes_block(new_node);
3060 if (is_Proj(new_node)) {
3061 sub = get_Proj_pred(new_node);
3062 assert(is_ia32_Sub(sub));
3065 set_irn_mode(sub, mode_T);
3066 new_node = new_rd_Proj(NULL, block, sub, mode, pn_ia32_res);
3068 eflags = new_rd_Proj(NULL, block, sub, mode_Iu, pn_ia32_Sub_flags);
3070 dbgi = get_irn_dbg_info(psi);
3071 sbb = new_bd_ia32_Sbb0(dbgi, block, eflags);
3072 not = new_bd_ia32_Not(dbgi, block, sbb);
3074 new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, not);
3075 set_ia32_commutative(new_node);
3080 * Create an const array of two float consts.
3082 * @param c0 the first constant
3083 * @param c1 the second constant
3084 * @param new_mode IN/OUT for the mode of the constants, if NULL
3085 * smallest possible mode will be used
3087 static ir_entity *ia32_create_const_array(ir_node *c0, ir_node *c1, ir_mode **new_mode)
3090 ir_mode *mode = *new_mode;
3092 ir_initializer_t *initializer;
3093 tarval *tv0 = get_Const_tarval(c0);
3094 tarval *tv1 = get_Const_tarval(c1);
3097 /* detect the best mode for the constants */
3098 mode = get_tarval_mode(tv0);
3100 if (mode != mode_F) {
3101 if (tarval_ieee754_can_conv_lossless(tv0, mode_F) &&
3102 tarval_ieee754_can_conv_lossless(tv1, mode_F)) {
3104 tv0 = tarval_convert_to(tv0, mode);
3105 tv1 = tarval_convert_to(tv1, mode);
3106 } else if (mode != mode_D) {
3107 if (tarval_ieee754_can_conv_lossless(tv0, mode_D) &&
3108 tarval_ieee754_can_conv_lossless(tv1, mode_D)) {
3110 tv0 = tarval_convert_to(tv0, mode);
3111 tv1 = tarval_convert_to(tv1, mode);
3118 tp = ia32_create_float_type(mode, 4);
3119 tp = ia32_create_float_array(tp);
3121 ent = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp);
3123 set_entity_ld_ident(ent, get_entity_ident(ent));
3124 set_entity_visibility(ent, ir_visibility_local);
3125 add_entity_linkage(ent, IR_LINKAGE_CONSTANT);
3127 initializer = create_initializer_compound(2);
3129 set_initializer_compound_value(initializer, 0, create_initializer_tarval(tv0));
3130 set_initializer_compound_value(initializer, 1, create_initializer_tarval(tv1));
3132 set_entity_initializer(ent, initializer);
3139 * Possible transformations for creating a Setcc.
3141 enum setcc_transform_insn {
3154 typedef struct setcc_transform {
3156 unsigned permutate_cmp_ins;
3159 enum setcc_transform_insn transform;
3163 } setcc_transform_t;
3166 * Setcc can only handle 0 and 1 result.
3167 * Find a transformation that creates 0 and 1 from
3170 static void find_const_transform(pn_Cmp pnc, tarval *t, tarval *f,
3171 setcc_transform_t *res)
3176 res->permutate_cmp_ins = 0;
3178 if (tarval_is_null(t)) {
3182 pnc = ia32_get_negated_pnc(pnc);
3183 } else if (tarval_cmp(t, f) == pn_Cmp_Lt) {
3184 // now, t is the bigger one
3188 pnc = ia32_get_negated_pnc(pnc);
3192 if (! tarval_is_null(f)) {
3193 tarval *t_sub = tarval_sub(t, f, NULL);
3196 res->steps[step].transform = SETCC_TR_ADD;
3198 if (t == tarval_bad)
3199 panic("constant subtract failed");
3200 if (! tarval_is_long(f))
3201 panic("tarval is not long");
3203 res->steps[step].val = get_tarval_long(f);
3205 f = tarval_sub(f, f, NULL);
3206 assert(tarval_is_null(f));
3209 if (tarval_is_one(t)) {
3210 res->steps[step].transform = SETCC_TR_SET;
3211 res->num_steps = ++step;
3215 if (tarval_is_minus_one(t)) {
3216 res->steps[step].transform = SETCC_TR_NEG;
3218 res->steps[step].transform = SETCC_TR_SET;
3219 res->num_steps = ++step;
3222 if (tarval_is_long(t)) {
3223 long v = get_tarval_long(t);
3225 res->steps[step].val = 0;
3228 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3230 res->steps[step].transform = SETCC_TR_LEAxx;
3231 res->steps[step].scale = 3; /* (a << 3) + a */
3234 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3236 res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA;
3237 res->steps[step].scale = 3; /* (a << 3) */
3240 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3242 res->steps[step].transform = SETCC_TR_LEAxx;
3243 res->steps[step].scale = 2; /* (a << 2) + a */
3246 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3248 res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA;
3249 res->steps[step].scale = 2; /* (a << 2) */
3252 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3254 res->steps[step].transform = SETCC_TR_LEAxx;
3255 res->steps[step].scale = 1; /* (a << 1) + a */
3258 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3260 res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA;
3261 res->steps[step].scale = 1; /* (a << 1) */
3264 res->num_steps = step;
3267 if (! tarval_is_single_bit(t)) {
3268 res->steps[step].transform = SETCC_TR_AND;
3269 res->steps[step].val = v;
3271 res->steps[step].transform = SETCC_TR_NEG;
3273 int v = get_tarval_lowest_bit(t);
3276 res->steps[step].transform = SETCC_TR_SHL;
3277 res->steps[step].scale = v;
3281 res->steps[step].transform = SETCC_TR_SET;
3282 res->num_steps = ++step;
3285 panic("tarval is not long");
3289 * Transforms a Mux node into some code sequence.
3291 * @return The transformed node.
3293 static ir_node *gen_Mux(ir_node *node)
3295 dbg_info *dbgi = get_irn_dbg_info(node);
3296 ir_node *block = get_nodes_block(node);
3297 ir_node *new_block = be_transform_node(block);
3298 ir_node *mux_true = get_Mux_true(node);
3299 ir_node *mux_false = get_Mux_false(node);
3300 ir_node *cond = get_Mux_sel(node);
3301 ir_mode *mode = get_irn_mode(node);
3306 assert(get_irn_mode(cond) == mode_b);
3308 /* Note: a Mux node uses a Load two times IFF it's used in the compare AND in the result */
3309 if (mode_is_float(mode)) {
3310 ir_node *cmp = get_Proj_pred(cond);
3311 ir_node *cmp_left = get_Cmp_left(cmp);
3312 ir_node *cmp_right = get_Cmp_right(cmp);
3313 pn_Cmp pnc = get_Proj_proj(cond);
3315 if (ia32_cg_config.use_sse2) {
3316 if (pnc == pn_Cmp_Lt || pnc == pn_Cmp_Le) {
3317 if (cmp_left == mux_true && cmp_right == mux_false) {
3318 /* Mux(a <= b, a, b) => MIN */
3319 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
3320 match_commutative | match_am | match_two_users);
3321 } else if (cmp_left == mux_false && cmp_right == mux_true) {
3322 /* Mux(a <= b, b, a) => MAX */
3323 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
3324 match_commutative | match_am | match_two_users);
3326 } else if (pnc == pn_Cmp_Gt || pnc == pn_Cmp_Ge) {
3327 if (cmp_left == mux_true && cmp_right == mux_false) {
3328 /* Mux(a >= b, a, b) => MAX */
3329 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
3330 match_commutative | match_am | match_two_users);
3331 } else if (cmp_left == mux_false && cmp_right == mux_true) {
3332 /* Mux(a >= b, b, a) => MIN */
3333 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
3334 match_commutative | match_am | match_two_users);
3339 if (is_Const(mux_true) && is_Const(mux_false)) {
3340 ia32_address_mode_t am;
3345 flags = get_flags_node(cond, &pnc);
3346 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node);
3348 if (ia32_cg_config.use_sse2) {
3349 /* cannot load from different mode on SSE */
3352 /* x87 can load any mode */
3356 am.addr.symconst_ent = ia32_create_const_array(mux_false, mux_true, &new_mode);
3358 switch (get_mode_size_bytes(new_mode)) {
3368 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3369 set_ia32_am_scale(new_node, 2);
3374 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3375 set_ia32_am_scale(new_node, 1);
3378 /* arg, shift 16 NOT supported */
3380 new_node = new_bd_ia32_Add(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, new_node);
3383 panic("Unsupported constant size");
3386 am.ls_mode = new_mode;
3387 am.addr.base = get_symconst_base();
3388 am.addr.index = new_node;
3389 am.addr.mem = nomem;
3391 am.addr.scale = scale;
3392 am.addr.use_frame = 0;
3393 am.addr.frame_entity = NULL;
3394 am.addr.symconst_sign = 0;
3395 am.mem_proj = am.addr.mem;
3396 am.op_type = ia32_AddrModeS;
3399 am.pinned = op_pin_state_floats;
3401 am.ins_permuted = 0;
3403 if (ia32_cg_config.use_sse2)
3404 load = new_bd_ia32_xLoad(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
3406 load = new_bd_ia32_vfld(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
3407 set_am_attributes(load, &am);
3409 return new_rd_Proj(NULL, block, load, mode_vfp, pn_ia32_res);
3411 panic("cannot transform floating point Mux");
3414 assert(ia32_mode_needs_gp_reg(mode));
3416 if (is_Proj(cond)) {
3417 ir_node *cmp = get_Proj_pred(cond);
3419 ir_node *cmp_left = get_Cmp_left(cmp);
3420 ir_node *cmp_right = get_Cmp_right(cmp);
3421 pn_Cmp pnc = get_Proj_proj(cond);
3423 /* check for unsigned Doz first */
3424 if ((pnc & pn_Cmp_Gt) && !mode_is_signed(mode) &&
3425 is_Const_0(mux_false) && is_Sub(mux_true) &&
3426 get_Sub_left(mux_true) == cmp_left && get_Sub_right(mux_true) == cmp_right) {
3427 /* Mux(a >=u b, a - b, 0) unsigned Doz */
3428 return create_doz(node, cmp_left, cmp_right);
3429 } else if ((pnc & pn_Cmp_Lt) && !mode_is_signed(mode) &&
3430 is_Const_0(mux_true) && is_Sub(mux_false) &&
3431 get_Sub_left(mux_false) == cmp_left && get_Sub_right(mux_false) == cmp_right) {
3432 /* Mux(a <=u b, 0, a - b) unsigned Doz */
3433 return create_doz(node, cmp_left, cmp_right);
3438 flags = get_flags_node(cond, &pnc);
3440 if (is_Const(mux_true) && is_Const(mux_false)) {
3441 /* both are const, good */
3442 tarval *tv_true = get_Const_tarval(mux_true);
3443 tarval *tv_false = get_Const_tarval(mux_false);
3444 setcc_transform_t res;
3447 /* check if flags is a cmp node and we are the only user,
3448 i.e no other user yet */
3449 int permutate_allowed = 0;
3450 if (is_ia32_Cmp(flags) && get_irn_n_edges(flags) == 0) {
3451 /* yes, we can permutate its inputs */
3452 permutate_allowed = 1;
3454 find_const_transform(pnc, tv_true, tv_false, &res);
3456 if (res.permutate_cmp_ins) {
3457 ia32_attr_t *attr = get_ia32_attr(flags);
3458 attr->data.ins_permuted ^= 1;
3460 for (step = (int)res.num_steps - 1; step >= 0; --step) {
3463 switch (res.steps[step].transform) {
3465 imm = ia32_immediate_from_long(res.steps[step].val);
3466 new_node = new_bd_ia32_Add(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, imm);
3468 case SETCC_TR_ADDxx:
3469 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3472 new_node = new_bd_ia32_Lea(dbgi, new_block, noreg_GP, new_node);
3473 set_ia32_am_scale(new_node, res.steps[step].scale);
3474 set_ia32_am_offs_int(new_node, res.steps[step].val);
3476 case SETCC_TR_LEAxx:
3477 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3478 set_ia32_am_scale(new_node, res.steps[step].scale);
3479 set_ia32_am_offs_int(new_node, res.steps[step].val);
3482 imm = ia32_immediate_from_long(res.steps[step].scale);
3483 new_node = new_bd_ia32_Shl(dbgi, new_block, new_node, imm);
3486 new_node = new_bd_ia32_Neg(dbgi, new_block, new_node);
3489 new_node = new_bd_ia32_Not(dbgi, new_block, new_node);
3492 imm = ia32_immediate_from_long(res.steps[step].val);
3493 new_node = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, imm);
3496 new_node = create_set_32bit(dbgi, new_block, flags, res.pnc, new_node);
3499 new_node = new_bd_ia32_Sbb0(dbgi, new_block, flags);
3502 panic("unknown setcc transform");
3506 new_node = create_CMov(node, cond, flags, pnc);
3514 * Create a conversion from x87 state register to general purpose.
3516 static ir_node *gen_x87_fp_to_gp(ir_node *node)
3518 ir_node *block = be_transform_node(get_nodes_block(node));
3519 ir_node *op = get_Conv_op(node);
3520 ir_node *new_op = be_transform_node(op);
3521 ir_graph *irg = current_ir_graph;
3522 dbg_info *dbgi = get_irn_dbg_info(node);
3523 ir_mode *mode = get_irn_mode(node);
3524 ir_node *fist, *load, *mem;
3526 mem = gen_vfist(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, new_op, &fist);
3527 set_irn_pinned(fist, op_pin_state_floats);
3528 set_ia32_use_frame(fist);
3529 set_ia32_op_type(fist, ia32_AddrModeD);
3531 assert(get_mode_size_bits(mode) <= 32);
3532 /* exception we can only store signed 32 bit integers, so for unsigned
3533 we store a 64bit (signed) integer and load the lower bits */
3534 if (get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
3535 set_ia32_ls_mode(fist, mode_Ls);
3537 set_ia32_ls_mode(fist, mode_Is);
3539 SET_IA32_ORIG_NODE(fist, node);
3542 load = new_bd_ia32_Load(dbgi, block, get_irg_frame(irg), noreg_GP, mem);
3544 set_irn_pinned(load, op_pin_state_floats);
3545 set_ia32_use_frame(load);
3546 set_ia32_op_type(load, ia32_AddrModeS);
3547 set_ia32_ls_mode(load, mode_Is);
3548 if (get_ia32_ls_mode(fist) == mode_Ls) {
3549 ia32_attr_t *attr = get_ia32_attr(load);
3550 attr->data.need_64bit_stackent = 1;
3552 ia32_attr_t *attr = get_ia32_attr(load);
3553 attr->data.need_32bit_stackent = 1;
3555 SET_IA32_ORIG_NODE(load, node);
3557 return new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res);
3561 * Creates a x87 strict Conv by placing a Store and a Load
3563 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
3565 ir_node *block = get_nodes_block(node);
3566 ir_graph *irg = get_Block_irg(block);
3567 dbg_info *dbgi = get_irn_dbg_info(node);
3568 ir_node *frame = get_irg_frame(irg);
3569 ir_node *store, *load;
3572 store = new_bd_ia32_vfst(dbgi, block, frame, noreg_GP, nomem, node, tgt_mode);
3573 set_ia32_use_frame(store);
3574 set_ia32_op_type(store, ia32_AddrModeD);
3575 SET_IA32_ORIG_NODE(store, node);
3577 load = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store, tgt_mode);
3578 set_ia32_use_frame(load);
3579 set_ia32_op_type(load, ia32_AddrModeS);
3580 SET_IA32_ORIG_NODE(load, node);
3582 new_node = new_r_Proj(block, load, mode_E, pn_ia32_vfld_res);
3586 static ir_node *create_Conv_I2I(dbg_info *dbgi, ir_node *block, ir_node *base,
3587 ir_node *index, ir_node *mem, ir_node *val, ir_mode *mode)
3589 ir_node *(*func)(dbg_info*, ir_node*, ir_node*, ir_node*, ir_node*, ir_node*, ir_mode*);
3591 func = get_mode_size_bits(mode) == 8 ?
3592 new_bd_ia32_Conv_I2I8Bit : new_bd_ia32_Conv_I2I;
3593 return func(dbgi, block, base, index, mem, val, mode);
3597 * Create a conversion from general purpose to x87 register
3599 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode)
3601 ir_node *src_block = get_nodes_block(node);
3602 ir_node *block = be_transform_node(src_block);
3603 ir_graph *irg = get_Block_irg(block);
3604 dbg_info *dbgi = get_irn_dbg_info(node);
3605 ir_node *op = get_Conv_op(node);
3606 ir_node *new_op = NULL;
3608 ir_mode *store_mode;
3613 /* fild can use source AM if the operand is a signed 16bit or 32bit integer */
3614 if (possible_int_mode_for_fp(src_mode)) {
3615 ia32_address_mode_t am;
3617 match_arguments(&am, src_block, NULL, op, NULL, match_am | match_try_am | match_16bit_am);
3618 if (am.op_type == ia32_AddrModeS) {
3619 ia32_address_t *addr = &am.addr;
3621 fild = new_bd_ia32_vfild(dbgi, block, addr->base, addr->index, addr->mem);
3622 new_node = new_r_Proj(block, fild, mode_vfp, pn_ia32_vfild_res);
3624 set_am_attributes(fild, &am);
3625 SET_IA32_ORIG_NODE(fild, node);
3627 fix_mem_proj(fild, &am);
3632 if (new_op == NULL) {
3633 new_op = be_transform_node(op);
3636 mode = get_irn_mode(op);
3638 /* first convert to 32 bit signed if necessary */
3639 if (get_mode_size_bits(src_mode) < 32) {
3640 if (!upper_bits_clean(new_op, src_mode)) {
3641 new_op = create_Conv_I2I(dbgi, block, noreg_GP, noreg_GP, nomem, new_op, src_mode);
3642 SET_IA32_ORIG_NODE(new_op, node);
3647 assert(get_mode_size_bits(mode) == 32);
3650 store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, new_op);
3652 set_ia32_use_frame(store);
3653 set_ia32_op_type(store, ia32_AddrModeD);
3654 set_ia32_ls_mode(store, mode_Iu);
3656 /* exception for 32bit unsigned, do a 64bit spill+load */
3657 if (!mode_is_signed(mode)) {
3660 ir_node *zero_const = ia32_create_Immediate(NULL, 0, 0);
3662 ir_node *zero_store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg),
3663 noreg_GP, nomem, zero_const);
3665 set_ia32_use_frame(zero_store);
3666 set_ia32_op_type(zero_store, ia32_AddrModeD);
3667 add_ia32_am_offs_int(zero_store, 4);
3668 set_ia32_ls_mode(zero_store, mode_Iu);
3673 store = new_rd_Sync(dbgi, block, 2, in);
3674 store_mode = mode_Ls;
3676 store_mode = mode_Is;
3680 fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg_GP, store);
3682 set_ia32_use_frame(fild);
3683 set_ia32_op_type(fild, ia32_AddrModeS);
3684 set_ia32_ls_mode(fild, store_mode);
3686 new_node = new_r_Proj(block, fild, mode_vfp, pn_ia32_vfild_res);
3692 * Create a conversion from one integer mode into another one
3694 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
3695 dbg_info *dbgi, ir_node *block, ir_node *op,
3698 ir_node *new_block = be_transform_node(block);
3700 ir_mode *smaller_mode;
3701 ia32_address_mode_t am;
3702 ia32_address_t *addr = &am.addr;
3705 if (get_mode_size_bits(src_mode) < get_mode_size_bits(tgt_mode)) {
3706 smaller_mode = src_mode;
3708 smaller_mode = tgt_mode;
3711 #ifdef DEBUG_libfirm
3713 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
3718 match_arguments(&am, block, NULL, op, NULL,
3719 match_am | match_8bit_am | match_16bit_am);
3721 if (upper_bits_clean(am.new_op2, smaller_mode)) {
3722 /* unnecessary conv. in theory it shouldn't have been AM */
3723 assert(is_ia32_NoReg_GP(addr->base));
3724 assert(is_ia32_NoReg_GP(addr->index));
3725 assert(is_NoMem(addr->mem));
3726 assert(am.addr.offset == 0);
3727 assert(am.addr.symconst_ent == NULL);
3731 new_node = create_Conv_I2I(dbgi, new_block, addr->base, addr->index,
3732 addr->mem, am.new_op2, smaller_mode);
3733 set_am_attributes(new_node, &am);
3734 /* match_arguments assume that out-mode = in-mode, this isn't true here
3736 set_ia32_ls_mode(new_node, smaller_mode);
3737 SET_IA32_ORIG_NODE(new_node, node);
3738 new_node = fix_mem_proj(new_node, &am);
3743 * Transforms a Conv node.
3745 * @return The created ia32 Conv node
3747 static ir_node *gen_Conv(ir_node *node)
3749 ir_node *block = get_nodes_block(node);
3750 ir_node *new_block = be_transform_node(block);
3751 ir_node *op = get_Conv_op(node);
3752 ir_node *new_op = NULL;
3753 dbg_info *dbgi = get_irn_dbg_info(node);
3754 ir_mode *src_mode = get_irn_mode(op);
3755 ir_mode *tgt_mode = get_irn_mode(node);
3756 int src_bits = get_mode_size_bits(src_mode);
3757 int tgt_bits = get_mode_size_bits(tgt_mode);
3758 ir_node *res = NULL;
3760 assert(!mode_is_int(src_mode) || src_bits <= 32);
3761 assert(!mode_is_int(tgt_mode) || tgt_bits <= 32);
3763 /* modeB -> X should already be lowered by the lower_mode_b pass */
3764 if (src_mode == mode_b) {
3765 panic("ConvB not lowered %+F", node);
3768 if (src_mode == tgt_mode) {
3769 if (get_Conv_strict(node)) {
3770 if (ia32_cg_config.use_sse2) {
3771 /* when we are in SSE mode, we can kill all strict no-op conversion */
3772 return be_transform_node(op);
3775 /* this should be optimized already, but who knows... */
3776 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
3777 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
3778 return be_transform_node(op);
3782 if (mode_is_float(src_mode)) {
3783 new_op = be_transform_node(op);
3784 /* we convert from float ... */
3785 if (mode_is_float(tgt_mode)) {
3787 if (ia32_cg_config.use_sse2) {
3788 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
3789 res = new_bd_ia32_Conv_FP2FP(dbgi, new_block, noreg_GP, noreg_GP,
3791 set_ia32_ls_mode(res, tgt_mode);
3793 if (get_Conv_strict(node)) {
3794 /* if fp_no_float_fold is not set then we assume that we
3795 * don't have any float operations in a non
3796 * mode_float_arithmetic mode and can skip strict upconvs */
3797 if (src_bits < tgt_bits
3798 && !(get_irg_fp_model(current_ir_graph) & fp_no_float_fold)) {
3799 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3802 res = gen_x87_strict_conv(tgt_mode, new_op);
3803 SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
3807 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3812 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
3813 if (ia32_cg_config.use_sse2) {
3814 res = new_bd_ia32_Conv_FP2I(dbgi, new_block, noreg_GP, noreg_GP,
3816 set_ia32_ls_mode(res, src_mode);
3818 return gen_x87_fp_to_gp(node);
3822 /* we convert from int ... */
3823 if (mode_is_float(tgt_mode)) {
3825 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
3826 if (ia32_cg_config.use_sse2) {
3827 new_op = be_transform_node(op);
3828 res = new_bd_ia32_Conv_I2FP(dbgi, new_block, noreg_GP, noreg_GP,
3830 set_ia32_ls_mode(res, tgt_mode);
3832 unsigned int_mantissa = get_mode_size_bits(src_mode) - (mode_is_signed(src_mode) ? 1 : 0);
3833 unsigned float_mantissa = tarval_ieee754_get_mantissa_size(tgt_mode);
3834 res = gen_x87_gp_to_fp(node, src_mode);
3836 /* we need a strict-Conv, if the int mode has more bits than the
3838 if (float_mantissa < int_mantissa) {
3839 res = gen_x87_strict_conv(tgt_mode, res);
3840 SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
3844 } else if (tgt_mode == mode_b) {
3845 /* mode_b lowering already took care that we only have 0/1 values */
3846 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3847 src_mode, tgt_mode));
3848 return be_transform_node(op);
3851 if (src_bits == tgt_bits) {
3852 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3853 src_mode, tgt_mode));
3854 return be_transform_node(op);
3857 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
3865 static ir_node *create_immediate_or_transform(ir_node *node,
3866 char immediate_constraint_type)
3868 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
3869 if (new_node == NULL) {
3870 new_node = be_transform_node(node);
3876 * Transforms a FrameAddr into an ia32 Add.
3878 static ir_node *gen_be_FrameAddr(ir_node *node)
3880 ir_node *block = be_transform_node(get_nodes_block(node));
3881 ir_node *op = be_get_FrameAddr_frame(node);
3882 ir_node *new_op = be_transform_node(op);
3883 dbg_info *dbgi = get_irn_dbg_info(node);
3886 new_node = new_bd_ia32_Lea(dbgi, block, new_op, noreg_GP);
3887 set_ia32_frame_ent(new_node, arch_get_frame_entity(node));
3888 set_ia32_use_frame(new_node);
3890 SET_IA32_ORIG_NODE(new_node, node);
3896 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3898 static ir_node *gen_be_Return(ir_node *node)
3900 ir_graph *irg = current_ir_graph;
3901 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3902 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3903 ir_entity *ent = get_irg_entity(irg);
3904 ir_type *tp = get_entity_type(ent);
3909 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3910 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3912 int pn_ret_val, pn_ret_mem, arity, i;
3914 assert(ret_val != NULL);
3915 if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) {
3916 return be_duplicate_node(node);
3919 res_type = get_method_res_type(tp, 0);
3921 if (! is_Primitive_type(res_type)) {
3922 return be_duplicate_node(node);
3925 mode = get_type_mode(res_type);
3926 if (! mode_is_float(mode)) {
3927 return be_duplicate_node(node);
3930 assert(get_method_n_ress(tp) == 1);
3932 pn_ret_val = get_Proj_proj(ret_val);
3933 pn_ret_mem = get_Proj_proj(ret_mem);
3935 /* get the Barrier */
3936 barrier = get_Proj_pred(ret_val);
3938 /* get result input of the Barrier */
3939 ret_val = get_irn_n(barrier, pn_ret_val);
3940 new_ret_val = be_transform_node(ret_val);
3942 /* get memory input of the Barrier */
3943 ret_mem = get_irn_n(barrier, pn_ret_mem);
3944 new_ret_mem = be_transform_node(ret_mem);
3946 frame = get_irg_frame(irg);
3948 dbgi = get_irn_dbg_info(barrier);
3949 block = be_transform_node(get_nodes_block(barrier));
3951 /* store xmm0 onto stack */
3952 sse_store = new_bd_ia32_xStoreSimple(dbgi, block, frame, noreg_GP,
3953 new_ret_mem, new_ret_val);
3954 set_ia32_ls_mode(sse_store, mode);
3955 set_ia32_op_type(sse_store, ia32_AddrModeD);
3956 set_ia32_use_frame(sse_store);
3958 /* load into x87 register */
3959 fld = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, sse_store, mode);
3960 set_ia32_op_type(fld, ia32_AddrModeS);
3961 set_ia32_use_frame(fld);
3963 mproj = new_r_Proj(block, fld, mode_M, pn_ia32_vfld_M);
3964 fld = new_r_Proj(block, fld, mode_vfp, pn_ia32_vfld_res);
3966 /* create a new barrier */
3967 arity = get_irn_arity(barrier);
3968 in = ALLOCAN(ir_node*, arity);
3969 for (i = 0; i < arity; ++i) {
3972 if (i == pn_ret_val) {
3974 } else if (i == pn_ret_mem) {
3977 ir_node *in = get_irn_n(barrier, i);
3978 new_in = be_transform_node(in);
3983 new_barrier = new_ir_node(dbgi, irg, block,
3984 get_irn_op(barrier), get_irn_mode(barrier),
3986 copy_node_attr(barrier, new_barrier);
3987 be_duplicate_deps(barrier, new_barrier);
3988 be_set_transformed_node(barrier, new_barrier);
3990 /* transform normally */
3991 return be_duplicate_node(node);
3995 * Transform a be_AddSP into an ia32_SubSP.
3997 static ir_node *gen_be_AddSP(ir_node *node)
3999 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
4000 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
4002 return gen_binop(node, sp, sz, new_bd_ia32_SubSP,
4003 match_am | match_immediate);
4007 * Transform a be_SubSP into an ia32_AddSP
4009 static ir_node *gen_be_SubSP(ir_node *node)
4011 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
4012 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
4014 return gen_binop(node, sp, sz, new_bd_ia32_AddSP,
4015 match_am | match_immediate);
4019 * Change some phi modes
4021 static ir_node *gen_Phi(ir_node *node)
4023 const arch_register_req_t *req;
4024 ir_node *block = be_transform_node(get_nodes_block(node));
4025 ir_graph *irg = current_ir_graph;
4026 dbg_info *dbgi = get_irn_dbg_info(node);
4027 ir_mode *mode = get_irn_mode(node);
4030 if (ia32_mode_needs_gp_reg(mode)) {
4031 /* we shouldn't have any 64bit stuff around anymore */
4032 assert(get_mode_size_bits(mode) <= 32);
4033 /* all integer operations are on 32bit registers now */
4035 req = ia32_reg_classes[CLASS_ia32_gp].class_req;
4036 } else if (mode_is_float(mode)) {
4037 if (ia32_cg_config.use_sse2) {
4039 req = ia32_reg_classes[CLASS_ia32_xmm].class_req;
4042 req = ia32_reg_classes[CLASS_ia32_vfp].class_req;
4045 req = arch_no_register_req;
4048 /* phi nodes allow loops, so we use the old arguments for now
4049 * and fix this later */
4050 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
4051 get_irn_in(node) + 1);
4052 copy_node_attr(node, phi);
4053 be_duplicate_deps(node, phi);
4055 arch_set_out_register_req(phi, 0, req);
4057 be_enqueue_preds(node);
4062 static ir_node *gen_Jmp(ir_node *node)
4064 ir_node *block = get_nodes_block(node);
4065 ir_node *new_block = be_transform_node(block);
4066 dbg_info *dbgi = get_irn_dbg_info(node);
4069 new_node = new_bd_ia32_Jmp(dbgi, new_block);
4070 SET_IA32_ORIG_NODE(new_node, node);
4078 static ir_node *gen_IJmp(ir_node *node)
4080 ir_node *block = get_nodes_block(node);
4081 ir_node *new_block = be_transform_node(block);
4082 dbg_info *dbgi = get_irn_dbg_info(node);
4083 ir_node *op = get_IJmp_target(node);
4085 ia32_address_mode_t am;
4086 ia32_address_t *addr = &am.addr;
4088 assert(get_irn_mode(op) == mode_P);
4090 match_arguments(&am, block, NULL, op, NULL, match_am | match_immediate);
4092 new_node = new_bd_ia32_IJmp(dbgi, new_block, addr->base, addr->index,
4093 addr->mem, am.new_op2);
4094 set_am_attributes(new_node, &am);
4095 SET_IA32_ORIG_NODE(new_node, node);
4097 new_node = fix_mem_proj(new_node, &am);
4103 * Transform a Bound node.
4105 static ir_node *gen_Bound(ir_node *node)
4108 ir_node *lower = get_Bound_lower(node);
4109 dbg_info *dbgi = get_irn_dbg_info(node);
4111 if (is_Const_0(lower)) {
4112 /* typical case for Java */
4113 ir_node *sub, *res, *flags, *block;
4115 res = gen_binop(node, get_Bound_index(node), get_Bound_upper(node),
4116 new_bd_ia32_Sub, match_mode_neutral | match_am | match_immediate);
4118 block = get_nodes_block(res);
4119 if (! is_Proj(res)) {
4121 set_irn_mode(sub, mode_T);
4122 res = new_rd_Proj(NULL, block, sub, mode_Iu, pn_ia32_res);
4124 sub = get_Proj_pred(res);
4126 flags = new_rd_Proj(NULL, block, sub, mode_Iu, pn_ia32_Sub_flags);
4127 new_node = new_bd_ia32_Jcc(dbgi, block, flags, pn_Cmp_Lt | ia32_pn_Cmp_unsigned);
4128 SET_IA32_ORIG_NODE(new_node, node);
4130 panic("generic Bound not supported in ia32 Backend");
4136 static ir_node *gen_ia32_l_ShlDep(ir_node *node)
4138 ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val);
4139 ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_count);
4141 return gen_shift_binop(node, left, right, new_bd_ia32_Shl,
4142 match_immediate | match_mode_neutral);
4145 static ir_node *gen_ia32_l_ShrDep(ir_node *node)
4147 ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_val);
4148 ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_count);
4149 return gen_shift_binop(node, left, right, new_bd_ia32_Shr,
4153 static ir_node *gen_ia32_l_SarDep(ir_node *node)
4155 ir_node *left = get_irn_n(node, n_ia32_l_SarDep_val);
4156 ir_node *right = get_irn_n(node, n_ia32_l_SarDep_count);
4157 return gen_shift_binop(node, left, right, new_bd_ia32_Sar,
4161 static ir_node *gen_ia32_l_Add(ir_node *node)
4163 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
4164 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
4165 ir_node *lowered = gen_binop(node, left, right, new_bd_ia32_Add,
4166 match_commutative | match_am | match_immediate |
4167 match_mode_neutral);
4169 if (is_Proj(lowered)) {
4170 lowered = get_Proj_pred(lowered);
4172 assert(is_ia32_Add(lowered));
4173 set_irn_mode(lowered, mode_T);
4179 static ir_node *gen_ia32_l_Adc(ir_node *node)
4181 return gen_binop_flags(node, new_bd_ia32_Adc,
4182 match_commutative | match_am | match_immediate |
4183 match_mode_neutral);
4187 * Transforms a l_MulS into a "real" MulS node.
4189 * @return the created ia32 Mul node
4191 static ir_node *gen_ia32_l_Mul(ir_node *node)
4193 ir_node *left = get_binop_left(node);
4194 ir_node *right = get_binop_right(node);
4196 return gen_binop(node, left, right, new_bd_ia32_Mul,
4197 match_commutative | match_am | match_mode_neutral);
4201 * Transforms a l_IMulS into a "real" IMul1OPS node.
4203 * @return the created ia32 IMul1OP node
4205 static ir_node *gen_ia32_l_IMul(ir_node *node)
4207 ir_node *left = get_binop_left(node);
4208 ir_node *right = get_binop_right(node);
4210 return gen_binop(node, left, right, new_bd_ia32_IMul1OP,
4211 match_commutative | match_am | match_mode_neutral);
4214 static ir_node *gen_ia32_l_Sub(ir_node *node)
4216 ir_node *left = get_irn_n(node, n_ia32_l_Sub_minuend);
4217 ir_node *right = get_irn_n(node, n_ia32_l_Sub_subtrahend);
4218 ir_node *lowered = gen_binop(node, left, right, new_bd_ia32_Sub,
4219 match_am | match_immediate | match_mode_neutral);
4221 if (is_Proj(lowered)) {
4222 lowered = get_Proj_pred(lowered);
4224 assert(is_ia32_Sub(lowered));
4225 set_irn_mode(lowered, mode_T);
4231 static ir_node *gen_ia32_l_Sbb(ir_node *node)
4233 return gen_binop_flags(node, new_bd_ia32_Sbb,
4234 match_am | match_immediate | match_mode_neutral);
4238 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
4239 * op1 - target to be shifted
4240 * op2 - contains bits to be shifted into target
4242 * Only op3 can be an immediate.
4244 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
4245 ir_node *low, ir_node *count)
4247 ir_node *block = get_nodes_block(node);
4248 ir_node *new_block = be_transform_node(block);
4249 dbg_info *dbgi = get_irn_dbg_info(node);
4250 ir_node *new_high = be_transform_node(high);
4251 ir_node *new_low = be_transform_node(low);
4255 /* the shift amount can be any mode that is bigger than 5 bits, since all
4256 * other bits are ignored anyway */
4257 while (is_Conv(count) &&
4258 get_irn_n_edges(count) == 1 &&
4259 mode_is_int(get_irn_mode(count))) {
4260 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
4261 count = get_Conv_op(count);
4263 new_count = create_immediate_or_transform(count, 0);
4265 if (is_ia32_l_ShlD(node)) {
4266 new_node = new_bd_ia32_ShlD(dbgi, new_block, new_high, new_low,
4269 new_node = new_bd_ia32_ShrD(dbgi, new_block, new_high, new_low,
4272 SET_IA32_ORIG_NODE(new_node, node);
4277 static ir_node *gen_ia32_l_ShlD(ir_node *node)
4279 ir_node *high = get_irn_n(node, n_ia32_l_ShlD_val_high);
4280 ir_node *low = get_irn_n(node, n_ia32_l_ShlD_val_low);
4281 ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
4282 return gen_lowered_64bit_shifts(node, high, low, count);
4285 static ir_node *gen_ia32_l_ShrD(ir_node *node)
4287 ir_node *high = get_irn_n(node, n_ia32_l_ShrD_val_high);
4288 ir_node *low = get_irn_n(node, n_ia32_l_ShrD_val_low);
4289 ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
4290 return gen_lowered_64bit_shifts(node, high, low, count);
4293 static ir_node *gen_ia32_l_LLtoFloat(ir_node *node)
4295 ir_node *src_block = get_nodes_block(node);
4296 ir_node *block = be_transform_node(src_block);
4297 ir_graph *irg = current_ir_graph;
4298 dbg_info *dbgi = get_irn_dbg_info(node);
4299 ir_node *frame = get_irg_frame(irg);
4300 ir_node *val_low = get_irn_n(node, n_ia32_l_LLtoFloat_val_low);
4301 ir_node *val_high = get_irn_n(node, n_ia32_l_LLtoFloat_val_high);
4302 ir_node *new_val_low = be_transform_node(val_low);
4303 ir_node *new_val_high = be_transform_node(val_high);
4305 ir_node *sync, *fild, *res;
4306 ir_node *store_low, *store_high;
4308 if (ia32_cg_config.use_sse2) {
4309 panic("ia32_l_LLtoFloat not implemented for SSE2");
4313 store_low = new_bd_ia32_Store(dbgi, block, frame, noreg_GP, nomem,
4315 store_high = new_bd_ia32_Store(dbgi, block, frame, noreg_GP, nomem,
4317 SET_IA32_ORIG_NODE(store_low, node);
4318 SET_IA32_ORIG_NODE(store_high, node);
4320 set_ia32_use_frame(store_low);
4321 set_ia32_use_frame(store_high);
4322 set_ia32_op_type(store_low, ia32_AddrModeD);
4323 set_ia32_op_type(store_high, ia32_AddrModeD);
4324 set_ia32_ls_mode(store_low, mode_Iu);
4325 set_ia32_ls_mode(store_high, mode_Is);
4326 add_ia32_am_offs_int(store_high, 4);
4330 sync = new_rd_Sync(dbgi, block, 2, in);
4333 fild = new_bd_ia32_vfild(dbgi, block, frame, noreg_GP, sync);
4335 set_ia32_use_frame(fild);
4336 set_ia32_op_type(fild, ia32_AddrModeS);
4337 set_ia32_ls_mode(fild, mode_Ls);
4339 SET_IA32_ORIG_NODE(fild, node);
4341 res = new_r_Proj(block, fild, mode_vfp, pn_ia32_vfild_res);
4343 if (! mode_is_signed(get_irn_mode(val_high))) {
4344 ia32_address_mode_t am;
4346 ir_node *count = ia32_create_Immediate(NULL, 0, 31);
4349 am.addr.base = get_symconst_base();
4350 am.addr.index = new_bd_ia32_Shr(dbgi, block, new_val_high, count);
4351 am.addr.mem = nomem;
4354 am.addr.symconst_ent = ia32_gen_fp_known_const(ia32_ULLBIAS);
4355 am.addr.use_frame = 0;
4356 am.addr.frame_entity = NULL;
4357 am.addr.symconst_sign = 0;
4358 am.ls_mode = mode_F;
4359 am.mem_proj = nomem;
4360 am.op_type = ia32_AddrModeS;
4362 am.new_op2 = ia32_new_NoReg_vfp(env_cg);
4363 am.pinned = op_pin_state_floats;
4365 am.ins_permuted = 0;
4367 fadd = new_bd_ia32_vfadd(dbgi, block, am.addr.base, am.addr.index, am.addr.mem,
4368 am.new_op1, am.new_op2, get_fpcw());
4369 set_am_attributes(fadd, &am);
4371 set_irn_mode(fadd, mode_T);
4372 res = new_rd_Proj(NULL, block, fadd, mode_vfp, pn_ia32_res);
4377 static ir_node *gen_ia32_l_FloattoLL(ir_node *node)
4379 ir_node *src_block = get_nodes_block(node);
4380 ir_node *block = be_transform_node(src_block);
4381 ir_graph *irg = get_Block_irg(block);
4382 dbg_info *dbgi = get_irn_dbg_info(node);
4383 ir_node *frame = get_irg_frame(irg);
4384 ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val);
4385 ir_node *new_val = be_transform_node(val);
4386 ir_node *fist, *mem;
4388 mem = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_val, &fist);
4389 SET_IA32_ORIG_NODE(fist, node);
4390 set_ia32_use_frame(fist);
4391 set_ia32_op_type(fist, ia32_AddrModeD);
4392 set_ia32_ls_mode(fist, mode_Ls);
4398 * the BAD transformer.
4400 static ir_node *bad_transform(ir_node *node)
4402 panic("No transform function for %+F available.", node);
4406 static ir_node *gen_Proj_l_FloattoLL(ir_node *node)
4408 ir_node *block = be_transform_node(get_nodes_block(node));
4409 ir_graph *irg = get_Block_irg(block);
4410 ir_node *pred = get_Proj_pred(node);
4411 ir_node *new_pred = be_transform_node(pred);
4412 ir_node *frame = get_irg_frame(irg);
4413 dbg_info *dbgi = get_irn_dbg_info(node);
4414 long pn = get_Proj_proj(node);
4419 load = new_bd_ia32_Load(dbgi, block, frame, noreg_GP, new_pred);
4420 SET_IA32_ORIG_NODE(load, node);
4421 set_ia32_use_frame(load);
4422 set_ia32_op_type(load, ia32_AddrModeS);
4423 set_ia32_ls_mode(load, mode_Iu);
4424 /* we need a 64bit stackslot (fist stores 64bit) even though we only load
4425 * 32 bit from it with this particular load */
4426 attr = get_ia32_attr(load);
4427 attr->data.need_64bit_stackent = 1;
4429 if (pn == pn_ia32_l_FloattoLL_res_high) {
4430 add_ia32_am_offs_int(load, 4);
4432 assert(pn == pn_ia32_l_FloattoLL_res_low);
4435 proj = new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res);
4441 * Transform the Projs of an AddSP.
4443 static ir_node *gen_Proj_be_AddSP(ir_node *node)
4445 ir_node *block = be_transform_node(get_nodes_block(node));
4446 ir_node *pred = get_Proj_pred(node);
4447 ir_node *new_pred = be_transform_node(pred);
4448 dbg_info *dbgi = get_irn_dbg_info(node);
4449 long proj = get_Proj_proj(node);
4451 if (proj == pn_be_AddSP_sp) {
4452 ir_node *res = new_rd_Proj(dbgi, block, new_pred, mode_Iu,
4453 pn_ia32_SubSP_stack);
4454 arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]);
4456 } else if (proj == pn_be_AddSP_res) {
4457 return new_rd_Proj(dbgi, block, new_pred, mode_Iu,
4458 pn_ia32_SubSP_addr);
4459 } else if (proj == pn_be_AddSP_M) {
4460 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_SubSP_M);
4463 panic("No idea how to transform proj->AddSP");
4467 * Transform the Projs of a SubSP.
4469 static ir_node *gen_Proj_be_SubSP(ir_node *node)
4471 ir_node *block = be_transform_node(get_nodes_block(node));
4472 ir_node *pred = get_Proj_pred(node);
4473 ir_node *new_pred = be_transform_node(pred);
4474 dbg_info *dbgi = get_irn_dbg_info(node);
4475 long proj = get_Proj_proj(node);
4477 if (proj == pn_be_SubSP_sp) {
4478 ir_node *res = new_rd_Proj(dbgi, block, new_pred, mode_Iu,
4479 pn_ia32_AddSP_stack);
4480 arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]);
4482 } else if (proj == pn_be_SubSP_M) {
4483 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_AddSP_M);
4486 panic("No idea how to transform proj->SubSP");
4490 * Transform and renumber the Projs from a Load.
4492 static ir_node *gen_Proj_Load(ir_node *node)
4495 ir_node *block = be_transform_node(get_nodes_block(node));
4496 ir_node *pred = get_Proj_pred(node);
4497 dbg_info *dbgi = get_irn_dbg_info(node);
4498 long proj = get_Proj_proj(node);
4500 /* loads might be part of source address mode matches, so we don't
4501 * transform the ProjMs yet (with the exception of loads whose result is
4504 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4506 ir_node *old_block = get_nodes_block(node);
4508 /* this is needed, because sometimes we have loops that are only
4509 reachable through the ProjM */
4510 be_enqueue_preds(node);
4511 /* do it in 2 steps, to silence firm verifier */
4512 res = new_rd_Proj(dbgi, old_block, pred, mode_M, pn_Load_M);
4513 set_Proj_proj(res, pn_ia32_mem);
4517 /* renumber the proj */
4518 new_pred = be_transform_node(pred);
4519 if (is_ia32_Load(new_pred)) {
4522 return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Load_res);
4524 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Load_M);
4525 case pn_Load_X_regular:
4526 return new_rd_Jmp(dbgi, block);
4527 case pn_Load_X_except:
4528 /* This Load might raise an exception. Mark it. */
4529 set_ia32_exc_label(new_pred, 1);
4530 return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Load_X_exc);
4534 } else if (is_ia32_Conv_I2I(new_pred) ||
4535 is_ia32_Conv_I2I8Bit(new_pred)) {
4536 set_irn_mode(new_pred, mode_T);
4537 if (proj == pn_Load_res) {
4538 return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_res);
4539 } else if (proj == pn_Load_M) {
4540 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_mem);
4542 } else if (is_ia32_xLoad(new_pred)) {
4545 return new_rd_Proj(dbgi, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
4547 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_xLoad_M);
4548 case pn_Load_X_regular:
4549 return new_rd_Jmp(dbgi, block);
4550 case pn_Load_X_except:
4551 /* This Load might raise an exception. Mark it. */
4552 set_ia32_exc_label(new_pred, 1);
4553 return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_xLoad_X_exc);
4557 } else if (is_ia32_vfld(new_pred)) {
4560 return new_rd_Proj(dbgi, block, new_pred, mode_vfp, pn_ia32_vfld_res);
4562 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_vfld_M);
4563 case pn_Load_X_regular:
4564 return new_rd_Jmp(dbgi, block);
4565 case pn_Load_X_except:
4566 /* This Load might raise an exception. Mark it. */
4567 set_ia32_exc_label(new_pred, 1);
4568 return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_vfld_X_exc);
4573 /* can happen for ProJMs when source address mode happened for the
4576 /* however it should not be the result proj, as that would mean the
4577 load had multiple users and should not have been used for
4579 if (proj != pn_Load_M) {
4580 panic("internal error: transformed node not a Load");
4582 return new_rd_Proj(dbgi, block, new_pred, mode_M, 1);
4585 panic("No idea how to transform proj");
4589 * Transform and renumber the Projs from a DivMod like instruction.
4591 static ir_node *gen_Proj_DivMod(ir_node *node)
4593 ir_node *block = be_transform_node(get_nodes_block(node));
4594 ir_node *pred = get_Proj_pred(node);
4595 ir_node *new_pred = be_transform_node(pred);
4596 dbg_info *dbgi = get_irn_dbg_info(node);
4597 long proj = get_Proj_proj(node);
4599 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4601 switch (get_irn_opcode(pred)) {
4605 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Div_M);
4607 return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4608 case pn_Div_X_regular:
4609 return new_rd_Jmp(dbgi, block);
4610 case pn_Div_X_except:
4611 set_ia32_exc_label(new_pred, 1);
4612 return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Div_X_exc);
4620 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Div_M);
4622 return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4623 case pn_Mod_X_except:
4624 set_ia32_exc_label(new_pred, 1);
4625 return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Div_X_exc);
4633 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Div_M);
4634 case pn_DivMod_res_div:
4635 return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4636 case pn_DivMod_res_mod:
4637 return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4638 case pn_DivMod_X_regular:
4639 return new_rd_Jmp(dbgi, block);
4640 case pn_DivMod_X_except:
4641 set_ia32_exc_label(new_pred, 1);
4642 return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Div_X_exc);
4651 panic("No idea how to transform proj->DivMod");
4655 * Transform and renumber the Projs from a CopyB.
4657 static ir_node *gen_Proj_CopyB(ir_node *node)
4659 ir_node *block = be_transform_node(get_nodes_block(node));
4660 ir_node *pred = get_Proj_pred(node);
4661 ir_node *new_pred = be_transform_node(pred);
4662 dbg_info *dbgi = get_irn_dbg_info(node);
4663 long proj = get_Proj_proj(node);
4666 case pn_CopyB_M_regular:
4667 if (is_ia32_CopyB_i(new_pred)) {
4668 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4669 } else if (is_ia32_CopyB(new_pred)) {
4670 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_CopyB_M);
4677 panic("No idea how to transform proj->CopyB");
4681 * Transform and renumber the Projs from a Quot.
4683 static ir_node *gen_Proj_Quot(ir_node *node)
4685 ir_node *block = be_transform_node(get_nodes_block(node));
4686 ir_node *pred = get_Proj_pred(node);
4687 ir_node *new_pred = be_transform_node(pred);
4688 dbg_info *dbgi = get_irn_dbg_info(node);
4689 long proj = get_Proj_proj(node);
4693 if (is_ia32_xDiv(new_pred)) {
4694 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_xDiv_M);
4695 } else if (is_ia32_vfdiv(new_pred)) {
4696 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4700 if (is_ia32_xDiv(new_pred)) {
4701 return new_rd_Proj(dbgi, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4702 } else if (is_ia32_vfdiv(new_pred)) {
4703 return new_rd_Proj(dbgi, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4706 case pn_Quot_X_regular:
4707 case pn_Quot_X_except:
4712 panic("No idea how to transform proj->Quot");
4715 static ir_node *gen_be_Call(ir_node *node)
4717 dbg_info *const dbgi = get_irn_dbg_info(node);
4718 ir_node *const src_block = get_nodes_block(node);
4719 ir_node *const block = be_transform_node(src_block);
4720 ir_node *const src_mem = get_irn_n(node, be_pos_Call_mem);
4721 ir_node *const src_sp = get_irn_n(node, be_pos_Call_sp);
4722 ir_node *const sp = be_transform_node(src_sp);
4723 ir_node *const src_ptr = get_irn_n(node, be_pos_Call_ptr);
4724 ia32_address_mode_t am;
4725 ia32_address_t *const addr = &am.addr;
4730 ir_node * eax = noreg_GP;
4731 ir_node * ecx = noreg_GP;
4732 ir_node * edx = noreg_GP;
4733 unsigned const pop = be_Call_get_pop(node);
4734 ir_type *const call_tp = be_Call_get_type(node);
4735 int old_no_pic_adjust;
4737 /* Run the x87 simulator if the call returns a float value */
4738 if (get_method_n_ress(call_tp) > 0) {
4739 ir_type *const res_type = get_method_res_type(call_tp, 0);
4740 ir_mode *const res_mode = get_type_mode(res_type);
4742 if (res_mode != NULL && mode_is_float(res_mode)) {
4743 env_cg->do_x87_sim = 1;
4747 /* We do not want be_Call direct calls */
4748 assert(be_Call_get_entity(node) == NULL);
4750 /* special case for PIC trampoline calls */
4751 old_no_pic_adjust = no_pic_adjust;
4752 no_pic_adjust = env_cg->birg->main_env->options->pic;
4754 match_arguments(&am, src_block, NULL, src_ptr, src_mem,
4755 match_am | match_immediate);
4757 no_pic_adjust = old_no_pic_adjust;
4759 i = get_irn_arity(node) - 1;
4760 fpcw = be_transform_node(get_irn_n(node, i--));
4761 for (; i >= be_pos_Call_first_arg; --i) {
4762 arch_register_req_t const *const req = arch_get_register_req(node, i);
4763 ir_node *const reg_parm = be_transform_node(get_irn_n(node, i));
4765 assert(req->type == arch_register_req_type_limited);
4766 assert(req->cls == &ia32_reg_classes[CLASS_ia32_gp]);
4768 switch (*req->limited) {
4769 case 1 << REG_EAX: assert(eax == noreg_GP); eax = reg_parm; break;
4770 case 1 << REG_ECX: assert(ecx == noreg_GP); ecx = reg_parm; break;
4771 case 1 << REG_EDX: assert(edx == noreg_GP); edx = reg_parm; break;
4772 default: panic("Invalid GP register for register parameter");
4776 mem = transform_AM_mem(block, src_ptr, src_mem, addr->mem);
4777 call = new_bd_ia32_Call(dbgi, block, addr->base, addr->index, mem,
4778 am.new_op2, sp, fpcw, eax, ecx, edx, pop, call_tp);
4779 set_am_attributes(call, &am);
4780 call = fix_mem_proj(call, &am);
4782 if (get_irn_pinned(node) == op_pin_state_pinned)
4783 set_irn_pinned(call, op_pin_state_pinned);
4785 SET_IA32_ORIG_NODE(call, node);
4787 if (ia32_cg_config.use_sse2) {
4788 /* remember this call for post-processing */
4789 ARR_APP1(ir_node *, call_list, call);
4790 ARR_APP1(ir_type *, call_types, be_Call_get_type(node));
4797 * Transform Builtin trap
4799 static ir_node *gen_trap(ir_node *node)
4801 dbg_info *dbgi = get_irn_dbg_info(node);
4802 ir_node *block = be_transform_node(get_nodes_block(node));
4803 ir_node *mem = be_transform_node(get_Builtin_mem(node));
4805 return new_bd_ia32_UD2(dbgi, block, mem);
4809 * Transform Builtin debugbreak
4811 static ir_node *gen_debugbreak(ir_node *node)
4813 dbg_info *dbgi = get_irn_dbg_info(node);
4814 ir_node *block = be_transform_node(get_nodes_block(node));
4815 ir_node *mem = be_transform_node(get_Builtin_mem(node));
4817 return new_bd_ia32_Breakpoint(dbgi, block, mem);
4821 * Transform Builtin return_address
4823 static ir_node *gen_return_address(ir_node *node)
4825 ir_node *param = get_Builtin_param(node, 0);
4826 ir_node *frame = get_Builtin_param(node, 1);
4827 dbg_info *dbgi = get_irn_dbg_info(node);
4828 tarval *tv = get_Const_tarval(param);
4829 unsigned long value = get_tarval_long(tv);
4831 ir_node *block = be_transform_node(get_nodes_block(node));
4832 ir_node *ptr = be_transform_node(frame);
4836 ir_node *cnt = new_bd_ia32_ProduceVal(dbgi, block);
4837 ir_node *res = new_bd_ia32_ProduceVal(dbgi, block);
4838 ptr = new_bd_ia32_ClimbFrame(dbgi, block, ptr, cnt, res, value);
4841 /* load the return address from this frame */
4842 load = new_bd_ia32_Load(dbgi, block, ptr, noreg_GP, nomem);
4844 set_irn_pinned(load, get_irn_pinned(node));
4845 set_ia32_op_type(load, ia32_AddrModeS);
4846 set_ia32_ls_mode(load, mode_Iu);
4848 set_ia32_am_offs_int(load, 0);
4849 set_ia32_use_frame(load);
4850 set_ia32_frame_ent(load, ia32_get_return_address_entity());
4852 if (get_irn_pinned(node) == op_pin_state_floats) {
4853 assert(pn_ia32_xLoad_res == pn_ia32_vfld_res
4854 && pn_ia32_vfld_res == pn_ia32_Load_res
4855 && pn_ia32_Load_res == pn_ia32_res);
4856 arch_irn_add_flags(load, arch_irn_flags_rematerializable);
4859 SET_IA32_ORIG_NODE(load, node);
4860 return new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res);
4864 * Transform Builtin frame_address
4866 static ir_node *gen_frame_address(ir_node *node)
4868 ir_node *param = get_Builtin_param(node, 0);
4869 ir_node *frame = get_Builtin_param(node, 1);
4870 dbg_info *dbgi = get_irn_dbg_info(node);
4871 tarval *tv = get_Const_tarval(param);
4872 unsigned long value = get_tarval_long(tv);
4874 ir_node *block = be_transform_node(get_nodes_block(node));
4875 ir_node *ptr = be_transform_node(frame);
4880 ir_node *cnt = new_bd_ia32_ProduceVal(dbgi, block);
4881 ir_node *res = new_bd_ia32_ProduceVal(dbgi, block);
4882 ptr = new_bd_ia32_ClimbFrame(dbgi, block, ptr, cnt, res, value);
4885 /* load the frame address from this frame */
4886 load = new_bd_ia32_Load(dbgi, block, ptr, noreg_GP, nomem);
4888 set_irn_pinned(load, get_irn_pinned(node));
4889 set_ia32_op_type(load, ia32_AddrModeS);
4890 set_ia32_ls_mode(load, mode_Iu);
4892 ent = ia32_get_frame_address_entity();
4894 set_ia32_am_offs_int(load, 0);
4895 set_ia32_use_frame(load);
4896 set_ia32_frame_ent(load, ent);
4898 /* will fail anyway, but gcc does this: */
4899 set_ia32_am_offs_int(load, 0);
4902 if (get_irn_pinned(node) == op_pin_state_floats) {
4903 assert(pn_ia32_xLoad_res == pn_ia32_vfld_res
4904 && pn_ia32_vfld_res == pn_ia32_Load_res
4905 && pn_ia32_Load_res == pn_ia32_res);
4906 arch_irn_add_flags(load, arch_irn_flags_rematerializable);
4909 SET_IA32_ORIG_NODE(load, node);
4910 return new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res);
4914 * Transform Builtin frame_address
4916 static ir_node *gen_prefetch(ir_node *node)
4919 ir_node *ptr, *block, *mem, *base, *index;
4920 ir_node *param, *new_node;
4923 ia32_address_t addr;
4925 if (!ia32_cg_config.use_sse_prefetch && !ia32_cg_config.use_3dnow_prefetch) {
4926 /* no prefetch at all, route memory */
4927 return be_transform_node(get_Builtin_mem(node));
4930 param = get_Builtin_param(node, 1);
4931 tv = get_Const_tarval(param);
4932 rw = get_tarval_long(tv);
4934 /* construct load address */
4935 memset(&addr, 0, sizeof(addr));
4936 ptr = get_Builtin_param(node, 0);
4937 ia32_create_address_mode(&addr, ptr, 0);
4944 base = be_transform_node(base);
4947 if (index == NULL) {
4950 index = be_transform_node(index);
4953 dbgi = get_irn_dbg_info(node);
4954 block = be_transform_node(get_nodes_block(node));
4955 mem = be_transform_node(get_Builtin_mem(node));
4957 if (rw == 1 && ia32_cg_config.use_3dnow_prefetch) {
4958 /* we have 3DNow!, this was already checked above */
4959 new_node = new_bd_ia32_PrefetchW(dbgi, block, base, index, mem);
4960 } else if (ia32_cg_config.use_sse_prefetch) {
4961 /* note: rw == 1 is IGNORED in that case */
4962 param = get_Builtin_param(node, 2);
4963 tv = get_Const_tarval(param);
4964 locality = get_tarval_long(tv);
4966 /* SSE style prefetch */
4969 new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, index, mem);
4972 new_node = new_bd_ia32_Prefetch2(dbgi, block, base, index, mem);
4975 new_node = new_bd_ia32_Prefetch1(dbgi, block, base, index, mem);
4978 new_node = new_bd_ia32_Prefetch0(dbgi, block, base, index, mem);
4982 assert(ia32_cg_config.use_3dnow_prefetch);
4983 /* 3DNow! style prefetch */
4984 new_node = new_bd_ia32_Prefetch(dbgi, block, base, index, mem);
4987 set_irn_pinned(new_node, get_irn_pinned(node));
4988 set_ia32_op_type(new_node, ia32_AddrModeS);
4989 set_ia32_ls_mode(new_node, mode_Bu);
4990 set_address(new_node, &addr);
4992 SET_IA32_ORIG_NODE(new_node, node);
4994 be_dep_on_frame(new_node);
4995 return new_r_Proj(block, new_node, mode_M, pn_ia32_Prefetch_M);
4999 * Transform bsf like node
5001 static ir_node *gen_unop_AM(ir_node *node, construct_binop_dest_func *func)
5003 ir_node *param = get_Builtin_param(node, 0);
5004 dbg_info *dbgi = get_irn_dbg_info(node);
5006 ir_node *block = get_nodes_block(node);
5007 ir_node *new_block = be_transform_node(block);
5009 ia32_address_mode_t am;
5010 ia32_address_t *addr = &am.addr;
5013 match_arguments(&am, block, NULL, param, NULL, match_am);
5015 cnt = func(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2);
5016 set_am_attributes(cnt, &am);
5017 set_ia32_ls_mode(cnt, get_irn_mode(param));
5019 SET_IA32_ORIG_NODE(cnt, node);
5020 return fix_mem_proj(cnt, &am);
5024 * Transform builtin ffs.
5026 static ir_node *gen_ffs(ir_node *node)
5028 ir_node *bsf = gen_unop_AM(node, new_bd_ia32_Bsf);
5029 ir_node *real = skip_Proj(bsf);
5030 dbg_info *dbgi = get_irn_dbg_info(real);
5031 ir_node *block = get_nodes_block(real);
5032 ir_node *flag, *set, *conv, *neg, *or;
5035 if (get_irn_mode(real) != mode_T) {
5036 set_irn_mode(real, mode_T);
5037 bsf = new_r_Proj(block, real, mode_Iu, pn_ia32_res);
5040 flag = new_r_Proj(block, real, mode_b, pn_ia32_flags);
5043 set = new_bd_ia32_Setcc(dbgi, block, flag, pn_Cmp_Eq);
5044 SET_IA32_ORIG_NODE(set, node);
5047 conv = new_bd_ia32_Conv_I2I8Bit(dbgi, block, noreg_GP, noreg_GP, nomem, set, mode_Bu);
5048 SET_IA32_ORIG_NODE(conv, node);
5051 neg = new_bd_ia32_Neg(dbgi, block, conv);
5054 or = new_bd_ia32_Or(dbgi, block, noreg_GP, noreg_GP, nomem, bsf, neg);
5055 set_ia32_commutative(or);
5058 return new_bd_ia32_Add(dbgi, block, noreg_GP, noreg_GP, nomem, or, ia32_create_Immediate(NULL, 0, 1));
5062 * Transform builtin clz.
5064 static ir_node *gen_clz(ir_node *node)
5066 ir_node *bsr = gen_unop_AM(node, new_bd_ia32_Bsr);
5067 ir_node *real = skip_Proj(bsr);
5068 dbg_info *dbgi = get_irn_dbg_info(real);
5069 ir_node *block = get_nodes_block(real);
5070 ir_node *imm = ia32_create_Immediate(NULL, 0, 31);
5072 return new_bd_ia32_Xor(dbgi, block, noreg_GP, noreg_GP, nomem, bsr, imm);
5076 * Transform builtin ctz.
5078 static ir_node *gen_ctz(ir_node *node)
5080 return gen_unop_AM(node, new_bd_ia32_Bsf);
5084 * Transform builtin parity.
5086 static ir_node *gen_parity(ir_node *node)
5088 ir_node *param = get_Builtin_param(node, 0);
5089 dbg_info *dbgi = get_irn_dbg_info(node);
5091 ir_node *block = get_nodes_block(node);
5093 ir_node *new_block = be_transform_node(block);
5094 ir_node *imm, *cmp, *new_node;
5096 ia32_address_mode_t am;
5097 ia32_address_t *addr = &am.addr;
5101 match_arguments(&am, block, NULL, param, NULL, match_am);
5102 imm = ia32_create_Immediate(NULL, 0, 0);
5103 cmp = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index,
5104 addr->mem, imm, am.new_op2, am.ins_permuted, 0);
5105 set_am_attributes(cmp, &am);
5106 set_ia32_ls_mode(cmp, mode_Iu);
5108 SET_IA32_ORIG_NODE(cmp, node);
5110 cmp = fix_mem_proj(cmp, &am);
5113 new_node = new_bd_ia32_Setcc(dbgi, new_block, cmp, ia32_pn_Cmp_parity);
5114 SET_IA32_ORIG_NODE(new_node, node);
5117 new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP,
5118 nomem, new_node, mode_Bu);
5119 SET_IA32_ORIG_NODE(new_node, node);
5124 * Transform builtin popcount
5126 static ir_node *gen_popcount(ir_node *node)
5128 ir_node *param = get_Builtin_param(node, 0);
5129 dbg_info *dbgi = get_irn_dbg_info(node);
5131 ir_node *block = get_nodes_block(node);
5132 ir_node *new_block = be_transform_node(block);
5135 ir_node *imm, *simm, *m1, *s1, *s2, *s3, *s4, *s5, *m2, *m3, *m4, *m5, *m6, *m7, *m8, *m9, *m10, *m11, *m12, *m13;
5137 /* check for SSE4.2 or SSE4a and use the popcnt instruction */
5138 if (ia32_cg_config.use_popcnt) {
5139 ia32_address_mode_t am;
5140 ia32_address_t *addr = &am.addr;
5143 match_arguments(&am, block, NULL, param, NULL, match_am | match_16bit_am);
5145 cnt = new_bd_ia32_Popcnt(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2);
5146 set_am_attributes(cnt, &am);
5147 set_ia32_ls_mode(cnt, get_irn_mode(param));
5149 SET_IA32_ORIG_NODE(cnt, node);
5150 return fix_mem_proj(cnt, &am);
5153 new_param = be_transform_node(param);
5155 /* do the standard popcount algo */
5157 /* m1 = x & 0x55555555 */
5158 imm = ia32_create_Immediate(NULL, 0, 0x55555555);
5159 m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_param, imm);
5162 simm = ia32_create_Immediate(NULL, 0, 1);
5163 s1 = new_bd_ia32_Shl(dbgi, new_block, new_param, simm);
5165 /* m2 = s1 & 0x55555555 */
5166 m2 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s1, imm);
5169 m3 = new_bd_ia32_Lea(dbgi, new_block, m2, m1);
5171 /* m4 = m3 & 0x33333333 */
5172 imm = ia32_create_Immediate(NULL, 0, 0x33333333);
5173 m4 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m3, imm);
5176 simm = ia32_create_Immediate(NULL, 0, 2);
5177 s2 = new_bd_ia32_Shl(dbgi, new_block, m3, simm);
5179 /* m5 = s2 & 0x33333333 */
5180 m5 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, imm);
5183 m6 = new_bd_ia32_Lea(dbgi, new_block, m4, m5);
5185 /* m7 = m6 & 0x0F0F0F0F */
5186 imm = ia32_create_Immediate(NULL, 0, 0x0F0F0F0F);
5187 m7 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m6, imm);
5190 simm = ia32_create_Immediate(NULL, 0, 4);
5191 s3 = new_bd_ia32_Shl(dbgi, new_block, m6, simm);
5193 /* m8 = s3 & 0x0F0F0F0F */
5194 m8 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, imm);
5197 m9 = new_bd_ia32_Lea(dbgi, new_block, m7, m8);
5199 /* m10 = m9 & 0x00FF00FF */
5200 imm = ia32_create_Immediate(NULL, 0, 0x00FF00FF);
5201 m10 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m9, imm);
5204 simm = ia32_create_Immediate(NULL, 0, 8);
5205 s4 = new_bd_ia32_Shl(dbgi, new_block, m9, simm);
5207 /* m11 = s4 & 0x00FF00FF */
5208 m11 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s4, imm);
5210 /* m12 = m10 + m11 */
5211 m12 = new_bd_ia32_Lea(dbgi, new_block, m10, m11);
5213 /* m13 = m12 & 0x0000FFFF */
5214 imm = ia32_create_Immediate(NULL, 0, 0x0000FFFF);
5215 m13 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m12, imm);
5217 /* s5 = m12 >> 16 */
5218 simm = ia32_create_Immediate(NULL, 0, 16);
5219 s5 = new_bd_ia32_Shl(dbgi, new_block, m12, simm);
5221 /* res = m13 + s5 */
5222 return new_bd_ia32_Lea(dbgi, new_block, m13, s5);
5226 * Transform builtin byte swap.
5228 static ir_node *gen_bswap(ir_node *node)
5230 ir_node *param = be_transform_node(get_Builtin_param(node, 0));
5231 dbg_info *dbgi = get_irn_dbg_info(node);
5233 ir_node *block = get_nodes_block(node);
5234 ir_node *new_block = be_transform_node(block);
5235 ir_mode *mode = get_irn_mode(param);
5236 unsigned size = get_mode_size_bits(mode);
5237 ir_node *m1, *m2, *m3, *m4, *s1, *s2, *s3, *s4;
5241 if (ia32_cg_config.use_i486) {
5242 /* swap available */
5243 return new_bd_ia32_Bswap(dbgi, new_block, param);
5245 s1 = new_bd_ia32_Shl(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 24));
5246 s2 = new_bd_ia32_Shl(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 8));
5248 m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, ia32_create_Immediate(NULL, 0, 0xFF00));
5249 m2 = new_bd_ia32_Lea(dbgi, new_block, s1, m1);
5251 s3 = new_bd_ia32_Shr(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 8));
5253 m3 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, ia32_create_Immediate(NULL, 0, 0xFF0000));
5254 m4 = new_bd_ia32_Lea(dbgi, new_block, m2, m3);
5256 s4 = new_bd_ia32_Shr(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 24));
5257 return new_bd_ia32_Lea(dbgi, new_block, m4, s4);
5260 /* swap16 always available */
5261 return new_bd_ia32_Bswap16(dbgi, new_block, param);
5264 panic("Invalid bswap size (%d)", size);
5269 * Transform builtin outport.
5271 static ir_node *gen_outport(ir_node *node)
5273 ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0);
5274 ir_node *oldv = get_Builtin_param(node, 1);
5275 ir_mode *mode = get_irn_mode(oldv);
5276 ir_node *value = be_transform_node(oldv);
5277 ir_node *block = be_transform_node(get_nodes_block(node));
5278 ir_node *mem = be_transform_node(get_Builtin_mem(node));
5279 dbg_info *dbgi = get_irn_dbg_info(node);
5281 ir_node *res = new_bd_ia32_Outport(dbgi, block, port, value, mem);
5282 set_ia32_ls_mode(res, mode);
5287 * Transform builtin inport.
5289 static ir_node *gen_inport(ir_node *node)
5291 ir_type *tp = get_Builtin_type(node);
5292 ir_type *rstp = get_method_res_type(tp, 0);
5293 ir_mode *mode = get_type_mode(rstp);
5294 ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0);
5295 ir_node *block = be_transform_node(get_nodes_block(node));
5296 ir_node *mem = be_transform_node(get_Builtin_mem(node));
5297 dbg_info *dbgi = get_irn_dbg_info(node);
5299 ir_node *res = new_bd_ia32_Inport(dbgi, block, port, mem);
5300 set_ia32_ls_mode(res, mode);
5302 /* check for missing Result Proj */
5307 * Transform a builtin inner trampoline
5309 static ir_node *gen_inner_trampoline(ir_node *node)
5311 ir_node *ptr = get_Builtin_param(node, 0);
5312 ir_node *callee = get_Builtin_param(node, 1);
5313 ir_node *env = be_transform_node(get_Builtin_param(node, 2));
5314 ir_node *mem = get_Builtin_mem(node);
5315 ir_node *block = get_nodes_block(node);
5316 ir_node *new_block = be_transform_node(block);
5320 ir_node *trampoline;
5322 dbg_info *dbgi = get_irn_dbg_info(node);
5323 ia32_address_t addr;
5325 /* construct store address */
5326 memset(&addr, 0, sizeof(addr));
5327 ia32_create_address_mode(&addr, ptr, 0);
5329 if (addr.base == NULL) {
5330 addr.base = noreg_GP;
5332 addr.base = be_transform_node(addr.base);
5335 if (addr.index == NULL) {
5336 addr.index = noreg_GP;
5338 addr.index = be_transform_node(addr.index);
5340 addr.mem = be_transform_node(mem);
5342 /* mov ecx, <env> */
5343 val = ia32_create_Immediate(NULL, 0, 0xB9);
5344 store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
5345 addr.index, addr.mem, val);
5346 set_irn_pinned(store, get_irn_pinned(node));
5347 set_ia32_op_type(store, ia32_AddrModeD);
5348 set_ia32_ls_mode(store, mode_Bu);
5349 set_address(store, &addr);
5353 store = new_bd_ia32_Store(dbgi, new_block, addr.base,
5354 addr.index, addr.mem, env);
5355 set_irn_pinned(store, get_irn_pinned(node));
5356 set_ia32_op_type(store, ia32_AddrModeD);
5357 set_ia32_ls_mode(store, mode_Iu);
5358 set_address(store, &addr);
5362 /* jmp rel <callee> */
5363 val = ia32_create_Immediate(NULL, 0, 0xE9);
5364 store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
5365 addr.index, addr.mem, val);
5366 set_irn_pinned(store, get_irn_pinned(node));
5367 set_ia32_op_type(store, ia32_AddrModeD);
5368 set_ia32_ls_mode(store, mode_Bu);
5369 set_address(store, &addr);
5373 trampoline = be_transform_node(ptr);
5375 /* the callee is typically an immediate */
5376 if (is_SymConst(callee)) {
5377 rel = new_bd_ia32_Const(dbgi, new_block, get_SymConst_entity(callee), 0, 0, -10);
5379 rel = new_bd_ia32_Lea(dbgi, new_block, be_transform_node(callee), ia32_create_Immediate(NULL, 0, -10));
5381 rel = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, nomem, rel, trampoline);
5383 store = new_bd_ia32_Store(dbgi, new_block, addr.base,
5384 addr.index, addr.mem, rel);
5385 set_irn_pinned(store, get_irn_pinned(node));
5386 set_ia32_op_type(store, ia32_AddrModeD);
5387 set_ia32_ls_mode(store, mode_Iu);
5388 set_address(store, &addr);
5393 return new_r_Tuple(new_block, 2, in);
5397 * Transform Builtin node.
5399 static ir_node *gen_Builtin(ir_node *node)
5401 ir_builtin_kind kind = get_Builtin_kind(node);
5405 return gen_trap(node);
5406 case ir_bk_debugbreak:
5407 return gen_debugbreak(node);
5408 case ir_bk_return_address:
5409 return gen_return_address(node);
5410 case ir_bk_frame_address:
5411 return gen_frame_address(node);
5412 case ir_bk_prefetch:
5413 return gen_prefetch(node);
5415 return gen_ffs(node);
5417 return gen_clz(node);
5419 return gen_ctz(node);
5421 return gen_parity(node);
5422 case ir_bk_popcount:
5423 return gen_popcount(node);
5425 return gen_bswap(node);
5427 return gen_outport(node);
5429 return gen_inport(node);
5430 case ir_bk_inner_trampoline:
5431 return gen_inner_trampoline(node);
5433 panic("Builtin %s not implemented in IA32", get_builtin_kind_name(kind));
5437 * Transform Proj(Builtin) node.
5439 static ir_node *gen_Proj_Builtin(ir_node *proj)
5441 ir_node *node = get_Proj_pred(proj);
5442 ir_node *new_node = be_transform_node(node);
5443 ir_builtin_kind kind = get_Builtin_kind(node);
5446 case ir_bk_return_address:
5447 case ir_bk_frame_address:
5452 case ir_bk_popcount:
5454 assert(get_Proj_proj(proj) == pn_Builtin_1_result);
5457 case ir_bk_debugbreak:
5458 case ir_bk_prefetch:
5460 assert(get_Proj_proj(proj) == pn_Builtin_M);
5463 if (get_Proj_proj(proj) == pn_Builtin_1_result) {
5464 return new_r_Proj(get_nodes_block(new_node),
5465 new_node, get_irn_mode(proj), pn_ia32_Inport_res);
5467 assert(get_Proj_proj(proj) == pn_Builtin_M);
5468 return new_r_Proj(get_nodes_block(new_node),
5469 new_node, mode_M, pn_ia32_Inport_M);
5471 case ir_bk_inner_trampoline:
5472 if (get_Proj_proj(proj) == pn_Builtin_1_result) {
5473 return get_Tuple_pred(new_node, 1);
5475 assert(get_Proj_proj(proj) == pn_Builtin_M);
5476 return get_Tuple_pred(new_node, 0);
5479 panic("Builtin %s not implemented in IA32", get_builtin_kind_name(kind));
5482 static ir_node *gen_be_IncSP(ir_node *node)
5484 ir_node *res = be_duplicate_node(node);
5485 arch_irn_add_flags(res, arch_irn_flags_modify_flags);
5491 * Transform the Projs from a be_Call.
5493 static ir_node *gen_Proj_be_Call(ir_node *node)
5495 ir_node *block = be_transform_node(get_nodes_block(node));
5496 ir_node *call = get_Proj_pred(node);
5497 ir_node *new_call = be_transform_node(call);
5498 dbg_info *dbgi = get_irn_dbg_info(node);
5499 long proj = get_Proj_proj(node);
5500 ir_mode *mode = get_irn_mode(node);
5503 if (proj == pn_be_Call_M_regular) {
5504 return new_rd_Proj(dbgi, block, new_call, mode_M, n_ia32_Call_mem);
5506 /* transform call modes */
5507 if (mode_is_data(mode)) {
5508 const arch_register_class_t *cls = arch_get_irn_reg_class_out(node);
5512 /* Map from be_Call to ia32_Call proj number */
5513 if (proj == pn_be_Call_sp) {
5514 proj = pn_ia32_Call_stack;
5515 } else if (proj == pn_be_Call_M_regular) {
5516 proj = pn_ia32_Call_M;
5518 arch_register_req_t const *const req = arch_get_register_req_out(node);
5519 int const n_outs = arch_irn_get_n_outs(new_call);
5522 assert(proj >= pn_be_Call_first_res);
5523 assert(req->type & arch_register_req_type_limited);
5525 for (i = 0; i < n_outs; ++i) {
5526 arch_register_req_t const *const new_req
5527 = arch_get_out_register_req(new_call, i);
5529 if (!(new_req->type & arch_register_req_type_limited) ||
5530 new_req->cls != req->cls ||
5531 *new_req->limited != *req->limited)
5540 res = new_rd_Proj(dbgi, block, new_call, mode, proj);
5542 /* TODO arch_set_irn_register() only operates on Projs, need variant with index */
5544 case pn_ia32_Call_stack:
5545 arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]);
5548 case pn_ia32_Call_fpcw:
5549 arch_set_irn_register(res, &ia32_fp_cw_regs[REG_FPCW]);
5557 * Transform the Projs from a Cmp.
5559 static ir_node *gen_Proj_Cmp(ir_node *node)
5561 /* this probably means not all mode_b nodes were lowered... */
5562 panic("trying to directly transform Proj_Cmp %+F (mode_b not lowered?)",
5567 * Transform the Projs from a Bound.
5569 static ir_node *gen_Proj_Bound(ir_node *node)
5571 ir_node *new_node, *block;
5572 ir_node *pred = get_Proj_pred(node);
5574 switch (get_Proj_proj(node)) {
5576 return be_transform_node(get_Bound_mem(pred));
5577 case pn_Bound_X_regular:
5578 new_node = be_transform_node(pred);
5579 block = get_nodes_block(new_node);
5580 return new_r_Proj(block, new_node, mode_X, pn_ia32_Jcc_true);
5581 case pn_Bound_X_except:
5582 new_node = be_transform_node(pred);
5583 block = get_nodes_block(new_node);
5584 return new_r_Proj(block, new_node, mode_X, pn_ia32_Jcc_false);
5586 return be_transform_node(get_Bound_index(pred));
5588 panic("unsupported Proj from Bound");
5592 static ir_node *gen_Proj_ASM(ir_node *node)
5594 ir_mode *mode = get_irn_mode(node);
5595 ir_node *pred = get_Proj_pred(node);
5596 ir_node *new_pred = be_transform_node(pred);
5597 ir_node *block = get_nodes_block(new_pred);
5598 long pos = get_Proj_proj(node);
5600 if (mode == mode_M) {
5601 pos = arch_irn_get_n_outs(new_pred)-1;
5602 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
5604 } else if (mode_is_float(mode)) {
5607 panic("unexpected proj mode at ASM");
5610 return new_r_Proj(block, new_pred, mode, pos);
5614 * Transform and potentially renumber Proj nodes.
5616 static ir_node *gen_Proj(ir_node *node)
5618 ir_node *pred = get_Proj_pred(node);
5621 switch (get_irn_opcode(pred)) {
5623 proj = get_Proj_proj(node);
5624 if (proj == pn_Store_M) {
5625 return be_transform_node(pred);
5627 panic("No idea how to transform proj->Store");
5630 return gen_Proj_Load(node);
5632 return gen_Proj_ASM(node);
5634 return gen_Proj_Builtin(node);
5638 return gen_Proj_DivMod(node);
5640 return gen_Proj_CopyB(node);
5642 return gen_Proj_Quot(node);
5644 return gen_Proj_be_SubSP(node);
5646 return gen_Proj_be_AddSP(node);
5648 return gen_Proj_be_Call(node);
5650 return gen_Proj_Cmp(node);
5652 return gen_Proj_Bound(node);
5654 proj = get_Proj_proj(node);
5656 case pn_Start_X_initial_exec: {
5657 ir_node *block = get_nodes_block(pred);
5658 ir_node *new_block = be_transform_node(block);
5659 dbg_info *dbgi = get_irn_dbg_info(node);
5660 /* we exchange the ProjX with a jump */
5661 ir_node *jump = new_rd_Jmp(dbgi, new_block);
5666 case pn_Start_P_tls:
5667 return gen_Proj_tls(node);
5672 if (is_ia32_l_FloattoLL(pred)) {
5673 return gen_Proj_l_FloattoLL(node);
5675 } else if (!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
5679 ir_mode *mode = get_irn_mode(node);
5680 if (ia32_mode_needs_gp_reg(mode)) {
5681 ir_node *new_pred = be_transform_node(pred);
5682 ir_node *block = be_transform_node(get_nodes_block(node));
5683 ir_node *new_proj = new_r_Proj(block, new_pred,
5684 mode_Iu, get_Proj_proj(node));
5685 new_proj->node_nr = node->node_nr;
5690 return be_duplicate_node(node);
5694 * Enters all transform functions into the generic pointer
5696 static void register_transformers(void)
5698 /* first clear the generic function pointer for all ops */
5699 clear_irp_opcodes_generic_func();
5701 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
5702 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
5742 /* transform ops from intrinsic lowering */
5754 GEN(ia32_l_LLtoFloat);
5755 GEN(ia32_l_FloattoLL);
5761 /* we should never see these nodes */
5776 /* handle builtins */
5779 /* handle generic backend nodes */
5793 * Pre-transform all unknown and noreg nodes.
5795 static void ia32_pretransform_node(void)
5797 ia32_code_gen_t *cg = env_cg;
5799 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
5800 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
5801 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
5802 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
5803 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
5804 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
5806 nomem = get_irg_no_mem(current_ir_graph);
5807 noreg_GP = ia32_new_NoReg_gp(cg);
5813 * Walker, checks if all ia32 nodes producing more than one result have their
5814 * Projs, otherwise creates new Projs and keeps them using a be_Keep node.
5816 static void add_missing_keep_walker(ir_node *node, void *data)
5819 unsigned found_projs = 0;
5820 const ir_edge_t *edge;
5821 ir_mode *mode = get_irn_mode(node);
5826 if (!is_ia32_irn(node))
5829 n_outs = arch_irn_get_n_outs(node);
5832 if (is_ia32_SwitchJmp(node))
5835 assert(n_outs < (int) sizeof(unsigned) * 8);
5836 foreach_out_edge(node, edge) {
5837 ir_node *proj = get_edge_src_irn(edge);
5840 /* The node could be kept */
5844 if (get_irn_mode(proj) == mode_M)
5847 pn = get_Proj_proj(proj);
5848 assert(pn < n_outs);
5849 found_projs |= 1 << pn;
5853 /* are keeps missing? */
5855 for (i = 0; i < n_outs; ++i) {
5858 const arch_register_req_t *req;
5859 const arch_register_class_t *cls;
5861 if (found_projs & (1 << i)) {
5865 req = arch_get_out_register_req(node, i);
5870 if (cls == &ia32_reg_classes[CLASS_ia32_flags]) {
5874 block = get_nodes_block(node);
5875 in[0] = new_r_Proj(block, node, arch_register_class_mode(cls), i);
5876 if (last_keep != NULL) {
5877 be_Keep_add_node(last_keep, cls, in[0]);
5879 last_keep = be_new_Keep(block, 1, in);
5880 if (sched_is_scheduled(node)) {
5881 sched_add_after(node, last_keep);
5888 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
5891 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
5893 ir_graph *irg = be_get_birg_irg(cg->birg);
5894 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
5898 * Post-process all calls if we are in SSE mode.
5899 * The ABI requires that the results are in st0, copy them
5900 * to a xmm register.
5902 static void postprocess_fp_call_results(void)
5906 for (i = ARR_LEN(call_list) - 1; i >= 0; --i) {
5907 ir_node *call = call_list[i];
5908 ir_type *mtp = call_types[i];
5911 for (j = get_method_n_ress(mtp) - 1; j >= 0; --j) {
5912 ir_type *res_tp = get_method_res_type(mtp, j);
5913 ir_node *res, *new_res;
5914 const ir_edge_t *edge, *next;
5917 if (! is_atomic_type(res_tp)) {
5918 /* no floating point return */
5921 mode = get_type_mode(res_tp);
5922 if (! mode_is_float(mode)) {
5923 /* no floating point return */
5927 res = be_get_Proj_for_pn(call, pn_ia32_Call_vf0 + j);
5930 /* now patch the users */
5931 foreach_out_edge_safe(res, edge, next) {
5932 ir_node *succ = get_edge_src_irn(edge);
5935 if (be_is_Keep(succ))
5938 if (is_ia32_xStore(succ)) {
5939 /* an xStore can be patched into an vfst */
5940 dbg_info *db = get_irn_dbg_info(succ);
5941 ir_node *block = get_nodes_block(succ);
5942 ir_node *base = get_irn_n(succ, n_ia32_xStore_base);
5943 ir_node *index = get_irn_n(succ, n_ia32_xStore_index);
5944 ir_node *mem = get_irn_n(succ, n_ia32_xStore_mem);
5945 ir_node *value = get_irn_n(succ, n_ia32_xStore_val);
5946 ir_mode *mode = get_ia32_ls_mode(succ);
5948 ir_node *st = new_bd_ia32_vfst(db, block, base, index, mem, value, mode);
5949 set_ia32_am_offs_int(st, get_ia32_am_offs_int(succ));
5950 if (is_ia32_use_frame(succ))
5951 set_ia32_use_frame(st);
5952 set_ia32_frame_ent(st, get_ia32_frame_ent(succ));
5953 set_irn_pinned(st, get_irn_pinned(succ));
5954 set_ia32_op_type(st, ia32_AddrModeD);
5958 if (new_res == NULL) {
5959 dbg_info *db = get_irn_dbg_info(call);
5960 ir_node *block = get_nodes_block(call);
5961 ir_node *frame = get_irg_frame(current_ir_graph);
5962 ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M);
5963 ir_node *call_mem = new_r_Proj(block, call, mode_M, pn_ia32_Call_M);
5964 ir_node *vfst, *xld, *new_mem;
5966 /* store st(0) on stack */
5967 vfst = new_bd_ia32_vfst(db, block, frame, noreg_GP, call_mem, res, mode);
5968 set_ia32_op_type(vfst, ia32_AddrModeD);
5969 set_ia32_use_frame(vfst);
5971 /* load into SSE register */
5972 xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst, mode);
5973 set_ia32_op_type(xld, ia32_AddrModeS);
5974 set_ia32_use_frame(xld);
5976 new_res = new_r_Proj(block, xld, mode, pn_ia32_xLoad_res);
5977 new_mem = new_r_Proj(block, xld, mode_M, pn_ia32_xLoad_M);
5979 if (old_mem != NULL) {
5980 edges_reroute(old_mem, new_mem, current_ir_graph);
5984 set_irn_n(succ, get_edge_src_pos(edge), new_res);
5991 /* do the transformation */
5992 void ia32_transform_graph(ia32_code_gen_t *cg)
5996 register_transformers();
5998 initial_fpcw = NULL;
6001 be_timer_push(T_HEIGHTS);
6002 heights = heights_new(cg->irg);
6003 be_timer_pop(T_HEIGHTS);
6004 ia32_calculate_non_address_mode_nodes(cg->birg);
6006 /* the transform phase is not safe for CSE (yet) because several nodes get
6007 * attributes set after their creation */
6008 cse_last = get_opt_cse();
6011 call_list = NEW_ARR_F(ir_node *, 0);
6012 call_types = NEW_ARR_F(ir_type *, 0);
6013 be_transform_graph(cg->birg, ia32_pretransform_node);
6015 if (ia32_cg_config.use_sse2)
6016 postprocess_fp_call_results();
6017 DEL_ARR_F(call_types);
6018 DEL_ARR_F(call_list);
6020 set_opt_cse(cse_last);
6022 ia32_free_non_address_mode_nodes();
6023 heights_free(heights);
6027 void ia32_init_transform(void)
6029 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");