2 * This file implements the IR transformation from firm into
16 #include "irgraph_t.h"
21 #include "iredges_t.h"
29 #include "../benode_t.h"
30 #include "../besched.h"
33 #include "bearch_ia32_t.h"
35 #include "ia32_nodes_attr.h"
36 #include "../arch/archop.h" /* we need this for Min and Max nodes */
37 #include "ia32_transform.h"
38 #include "ia32_new_nodes.h"
39 #include "ia32_map_regs.h"
40 #include "ia32_dbg_stat.h"
42 #include "gen_ia32_regalloc_if.h"
44 #define SFP_SIGN "0x80000000"
45 #define DFP_SIGN "0x8000000000000000"
46 #define SFP_ABS "0x7FFFFFFF"
47 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
49 #define TP_SFP_SIGN "ia32_sfp_sign"
50 #define TP_DFP_SIGN "ia32_dfp_sign"
51 #define TP_SFP_ABS "ia32_sfp_abs"
52 #define TP_DFP_ABS "ia32_dfp_abs"
54 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
55 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
56 #define ENT_SFP_ABS "IA32_SFP_ABS"
57 #define ENT_DFP_ABS "IA32_DFP_ABS"
59 extern ir_op *get_op_Mulh(void);
61 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
62 ir_node *op1, ir_node *op2, ir_node *mem);
64 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
65 ir_node *op, ir_node *mem);
68 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
71 /****************************************************************************************************
73 * | | | | / _| | | (_)
74 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
75 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
76 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
77 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
79 ****************************************************************************************************/
82 * Returns 1 if irn is a Const representing 0, 0 otherwise
84 static INLINE int is_ia32_Const_0(ir_node *irn) {
85 return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
89 * Returns 1 if irn is a Const representing 1, 0 otherwise
91 static INLINE int is_ia32_Const_1(ir_node *irn) {
92 return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
96 * Returns the Proj representing the UNKNOWN register for given mode.
98 static ir_node *be_get_unknown_for_mode(ia32_code_gen_t *cg, ir_mode *mode) {
99 be_abi_irg_t *babi = cg->birg->abi;
100 const arch_register_t *unknwn_reg = NULL;
102 if (mode_is_float(mode)) {
103 unknwn_reg = USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_UKNWN] : &ia32_vfp_regs[REG_VFP_UKNWN];
106 unknwn_reg = &ia32_gp_regs[REG_GP_UKNWN];
109 return be_abi_get_callee_save_irn(babi, unknwn_reg);
113 * Gets the Proj with number pn from irn.
115 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
116 const ir_edge_t *edge;
118 assert(get_irn_mode(irn) == mode_T && "need mode_T");
120 foreach_out_edge(irn, edge) {
121 proj = get_edge_src_irn(edge);
123 if (get_Proj_proj(proj) == pn)
131 * SSE convert of an integer node into a floating point node.
133 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block,
134 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
136 ir_node *noreg = ia32_new_NoReg_gp(cg);
137 ir_node *nomem = new_rd_NoMem(irg);
139 ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
140 set_ia32_src_mode(conv, get_irn_mode(in));
141 set_ia32_tgt_mode(conv, tgt_mode);
142 set_ia32_am_support(conv, ia32_am_Source);
143 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
145 return new_rd_Proj(dbg, irg, block, conv, tgt_mode, pn_ia32_Conv_I2FP_res);
148 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
149 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
150 static const struct {
152 const char *ent_name;
153 const char *cnst_str;
154 } names [ia32_known_const_max] = {
155 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
156 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
157 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
158 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
160 static struct entity *ent_cache[ia32_known_const_max];
162 const char *tp_name, *ent_name, *cnst_str;
169 ent_name = names[kct].ent_name;
170 if (! ent_cache[kct]) {
171 tp_name = names[kct].tp_name;
172 cnst_str = names[kct].cnst_str;
174 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
175 tp = new_type_primitive(new_id_from_str(tp_name), mode);
176 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
178 set_entity_ld_ident(ent, get_entity_ident(ent));
179 set_entity_visibility(ent, visibility_local);
180 set_entity_variability(ent, variability_constant);
181 set_entity_allocation(ent, allocation_static);
183 /* we create a new entity here: It's initialization must resist on the
185 rem = current_ir_graph;
186 current_ir_graph = get_const_code_irg();
187 cnst = new_Const(mode, tv);
188 current_ir_graph = rem;
190 set_atomic_ent_value(ent, cnst);
192 /* cache the entry */
193 ent_cache[kct] = ent;
196 return get_entity_ident(ent_cache[kct]);
201 * Prints the old node name on cg obst and returns a pointer to it.
203 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
204 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
206 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
207 obstack_1grow(isa->name_obst, 0);
208 isa->name_obst_size += obstack_object_size(isa->name_obst);
209 return obstack_finish(isa->name_obst);
213 /* determine if one operator is an Imm */
214 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
216 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
217 else return is_ia32_Cnst(op2) ? op2 : NULL;
220 /* determine if one operator is not an Imm */
221 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
222 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
227 * Construct a standard binary operation, set AM and immediate if required.
229 * @param env The transformation environment
230 * @param op1 The first operand
231 * @param op2 The second operand
232 * @param func The node constructor function
233 * @return The constructed ia32 node.
235 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
236 ir_node *new_op = NULL;
237 ir_mode *mode = env->mode;
238 dbg_info *dbg = env->dbg;
239 ir_graph *irg = env->irg;
240 ir_node *block = env->block;
241 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
242 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
243 ir_node *nomem = new_NoMem();
244 ir_node *expr_op, *imm_op;
245 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
247 /* Check if immediate optimization is on and */
248 /* if it's an operation with immediate. */
249 if (! (env->cg->opt & IA32_OPT_IMMOPS)) {
253 else if (is_op_commutative(get_irn_op(env->irn))) {
254 imm_op = get_immediate_op(op1, op2);
255 expr_op = get_expr_op(op1, op2);
258 imm_op = get_immediate_op(NULL, op2);
259 expr_op = get_expr_op(op1, op2);
262 assert((expr_op || imm_op) && "invalid operands");
265 /* We have two consts here: not yet supported */
269 if (mode_is_float(mode)) {
270 /* floating point operations */
272 DB((mod, LEVEL_1, "FP with immediate ..."));
273 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
274 set_ia32_Immop_attr(new_op, imm_op);
275 set_ia32_am_support(new_op, ia32_am_None);
278 DB((mod, LEVEL_1, "FP binop ..."));
279 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
280 set_ia32_am_support(new_op, ia32_am_Source);
282 set_ia32_ls_mode(new_op, mode);
285 /* integer operations */
287 /* This is expr + const */
288 DB((mod, LEVEL_1, "INT with immediate ..."));
289 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
290 set_ia32_Immop_attr(new_op, imm_op);
293 set_ia32_am_support(new_op, ia32_am_Dest);
296 DB((mod, LEVEL_1, "INT binop ..."));
297 /* This is a normal operation */
298 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
301 set_ia32_am_support(new_op, ia32_am_Full);
305 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
307 set_ia32_res_mode(new_op, mode);
309 if (is_op_commutative(get_irn_op(env->irn))) {
310 set_ia32_commutative(new_op);
313 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
319 * Construct a shift/rotate binary operation, sets AM and immediate if required.
321 * @param env The transformation environment
322 * @param op1 The first operand
323 * @param op2 The second operand
324 * @param func The node constructor function
325 * @return The constructed ia32 node.
327 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
328 ir_node *new_op = NULL;
329 ir_mode *mode = env->mode;
330 dbg_info *dbg = env->dbg;
331 ir_graph *irg = env->irg;
332 ir_node *block = env->block;
333 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
334 ir_node *nomem = new_NoMem();
335 ir_node *expr_op, *imm_op;
337 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
339 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
341 /* Check if immediate optimization is on and */
342 /* if it's an operation with immediate. */
343 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
344 expr_op = get_expr_op(op1, op2);
346 assert((expr_op || imm_op) && "invalid operands");
349 /* We have two consts here: not yet supported */
353 /* Limit imm_op within range imm8 */
355 tv = get_ia32_Immop_tarval(imm_op);
358 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
365 /* integer operations */
367 /* This is shift/rot with const */
368 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
370 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
371 set_ia32_Immop_attr(new_op, imm_op);
374 /* This is a normal shift/rot */
375 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
376 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
380 set_ia32_am_support(new_op, ia32_am_Dest);
382 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
384 set_ia32_res_mode(new_op, mode);
385 set_ia32_emit_cl(new_op);
387 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
392 * Construct a standard unary operation, set AM and immediate if required.
394 * @param env The transformation environment
395 * @param op The operand
396 * @param func The node constructor function
397 * @return The constructed ia32 node.
399 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
400 ir_node *new_op = NULL;
401 ir_mode *mode = env->mode;
402 dbg_info *dbg = env->dbg;
403 ir_graph *irg = env->irg;
404 ir_node *block = env->block;
405 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
406 ir_node *nomem = new_NoMem();
407 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
409 new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
411 if (mode_is_float(mode)) {
412 DB((mod, LEVEL_1, "FP unop ..."));
413 /* floating point operations don't support implicit store */
414 set_ia32_am_support(new_op, ia32_am_None);
417 DB((mod, LEVEL_1, "INT unop ..."));
418 set_ia32_am_support(new_op, ia32_am_Dest);
421 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
423 set_ia32_res_mode(new_op, mode);
425 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
431 * Creates an ia32 Add with immediate.
433 * @param env The transformation environment
434 * @param expr_op The expression operator
435 * @param const_op The constant
436 * @return the created ia32 Add node
438 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
439 ir_node *new_op = NULL;
440 tarval *tv = get_ia32_Immop_tarval(const_op);
441 dbg_info *dbg = env->dbg;
442 ir_graph *irg = env->irg;
443 ir_node *block = env->block;
444 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
445 ir_node *nomem = new_NoMem();
447 tarval_classification_t class_tv, class_negtv;
448 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
450 /* try to optimize to inc/dec */
451 if ((env->cg->opt & IA32_OPT_INCDEC) && (get_ia32_op_type(const_op) == ia32_Const)) {
452 /* optimize tarvals */
453 class_tv = classify_tarval(tv);
454 class_negtv = classify_tarval(tarval_neg(tv));
456 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
457 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
458 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
461 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
462 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
463 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
469 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
470 set_ia32_Immop_attr(new_op, const_op);
471 set_ia32_commutative(new_op);
478 * Creates an ia32 Add.
480 * @param env The transformation environment
481 * @return the created ia32 Add node
483 static ir_node *gen_Add(ia32_transform_env_t *env) {
484 ir_node *new_op = NULL;
485 dbg_info *dbg = env->dbg;
486 ir_mode *mode = env->mode;
487 ir_graph *irg = env->irg;
488 ir_node *block = env->block;
489 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
490 ir_node *nomem = new_NoMem();
491 ir_node *expr_op, *imm_op;
492 ir_node *op1 = get_Add_left(env->irn);
493 ir_node *op2 = get_Add_right(env->irn);
495 /* Check if immediate optimization is on and */
496 /* if it's an operation with immediate. */
497 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
498 expr_op = get_expr_op(op1, op2);
500 assert((expr_op || imm_op) && "invalid operands");
502 if (mode_is_float(mode)) {
504 if (USE_SSE2(env->cg))
505 return gen_binop(env, op1, op2, new_rd_ia32_xAdd);
507 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
512 /* No expr_op means, that we have two const - one symconst and */
513 /* one tarval or another symconst - because this case is not */
514 /* covered by constant folding */
515 /* We need to check for: */
516 /* 1) symconst + const -> becomes a LEA */
517 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
518 /* linker doesn't support two symconsts */
520 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
521 /* this is the 2nd case */
522 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
523 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
524 set_ia32_am_flavour(new_op, ia32_am_OB);
526 DBG_OPT_LEA1(op2, new_op);
529 /* this is the 1st case */
530 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
532 DBG_OPT_LEA2(op1, op2, new_op);
534 if (get_ia32_op_type(op1) == ia32_SymConst) {
535 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
536 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
539 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
540 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
542 set_ia32_am_flavour(new_op, ia32_am_O);
546 set_ia32_am_support(new_op, ia32_am_Source);
547 set_ia32_op_type(new_op, ia32_AddrModeS);
549 /* Lea doesn't need a Proj */
553 /* This is expr + const */
554 new_op = gen_imm_Add(env, expr_op, imm_op);
557 set_ia32_am_support(new_op, ia32_am_Dest);
560 /* This is a normal add */
561 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
564 set_ia32_am_support(new_op, ia32_am_Full);
565 set_ia32_commutative(new_op);
569 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
571 set_ia32_res_mode(new_op, mode);
573 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Add_res);
579 * Creates an ia32 Mul.
581 * @param env The transformation environment
582 * @return the created ia32 Mul node
584 static ir_node *gen_Mul(ia32_transform_env_t *env) {
585 ir_node *op1 = get_Mul_left(env->irn);
586 ir_node *op2 = get_Mul_right(env->irn);
589 if (mode_is_float(env->mode)) {
591 if (USE_SSE2(env->cg))
592 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMul);
594 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
597 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
606 * Creates an ia32 Mulh.
607 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
608 * this result while Mul returns the lower 32 bit.
610 * @param env The transformation environment
611 * @return the created ia32 Mulh node
613 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
614 ir_node *op1 = get_irn_n(env->irn, 0);
615 ir_node *op2 = get_irn_n(env->irn, 1);
616 ir_node *proj_EAX, *proj_EDX, *mulh;
619 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
620 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
621 mulh = get_Proj_pred(proj_EAX);
622 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
624 /* to be on the save side */
625 set_Proj_proj(proj_EAX, pn_EAX);
627 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
628 /* Mulh with const cannot have AM */
629 set_ia32_am_support(mulh, ia32_am_None);
632 /* Mulh cannot have AM for destination */
633 set_ia32_am_support(mulh, ia32_am_Source);
639 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
647 * Creates an ia32 And.
649 * @param env The transformation environment
650 * @return The created ia32 And node
652 static ir_node *gen_And(ia32_transform_env_t *env) {
653 ir_node *op1 = get_And_left(env->irn);
654 ir_node *op2 = get_And_right(env->irn);
656 assert (! mode_is_float(env->mode));
657 return gen_binop(env, op1, op2, new_rd_ia32_And);
663 * Creates an ia32 Or.
665 * @param env The transformation environment
666 * @return The created ia32 Or node
668 static ir_node *gen_Or(ia32_transform_env_t *env) {
669 ir_node *op1 = get_Or_left(env->irn);
670 ir_node *op2 = get_Or_right(env->irn);
672 assert (! mode_is_float(env->mode));
673 return gen_binop(env, op1, op2, new_rd_ia32_Or);
679 * Creates an ia32 Eor.
681 * @param env The transformation environment
682 * @return The created ia32 Eor node
684 static ir_node *gen_Eor(ia32_transform_env_t *env) {
685 ir_node *op1 = get_Eor_left(env->irn);
686 ir_node *op2 = get_Eor_right(env->irn);
688 assert(! mode_is_float(env->mode));
689 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
695 * Creates an ia32 Max.
697 * @param env The transformation environment
698 * @return the created ia32 Max node
700 static ir_node *gen_Max(ia32_transform_env_t *env) {
701 ir_node *op1 = get_irn_n(env->irn, 0);
702 ir_node *op2 = get_irn_n(env->irn, 1);
705 if (mode_is_float(env->mode)) {
707 if (USE_SSE2(env->cg))
708 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMax);
714 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
715 set_ia32_am_support(new_op, ia32_am_None);
716 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
725 * Creates an ia32 Min.
727 * @param env The transformation environment
728 * @return the created ia32 Min node
730 static ir_node *gen_Min(ia32_transform_env_t *env) {
731 ir_node *op1 = get_irn_n(env->irn, 0);
732 ir_node *op2 = get_irn_n(env->irn, 1);
735 if (mode_is_float(env->mode)) {
737 if (USE_SSE2(env->cg))
738 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMin);
744 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
745 set_ia32_am_support(new_op, ia32_am_None);
746 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
755 * Creates an ia32 Sub with immediate.
757 * @param env The transformation environment
758 * @param expr_op The first operator
759 * @param const_op The constant operator
760 * @return The created ia32 Sub node
762 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
763 ir_node *new_op = NULL;
764 tarval *tv = get_ia32_Immop_tarval(const_op);
765 dbg_info *dbg = env->dbg;
766 ir_graph *irg = env->irg;
767 ir_node *block = env->block;
768 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
769 ir_node *nomem = new_NoMem();
771 tarval_classification_t class_tv, class_negtv;
772 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
774 /* try to optimize to inc/dec */
775 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
776 /* optimize tarvals */
777 class_tv = classify_tarval(tv);
778 class_negtv = classify_tarval(tarval_neg(tv));
780 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
781 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
782 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
785 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
786 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
787 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
793 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
794 set_ia32_Immop_attr(new_op, const_op);
801 * Creates an ia32 Sub.
803 * @param env The transformation environment
804 * @return The created ia32 Sub node
806 static ir_node *gen_Sub(ia32_transform_env_t *env) {
807 ir_node *new_op = NULL;
808 dbg_info *dbg = env->dbg;
809 ir_mode *mode = env->mode;
810 ir_graph *irg = env->irg;
811 ir_node *block = env->block;
812 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
813 ir_node *nomem = new_NoMem();
814 ir_node *op1 = get_Sub_left(env->irn);
815 ir_node *op2 = get_Sub_right(env->irn);
816 ir_node *expr_op, *imm_op;
818 /* Check if immediate optimization is on and */
819 /* if it's an operation with immediate. */
820 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
821 expr_op = get_expr_op(op1, op2);
823 assert((expr_op || imm_op) && "invalid operands");
825 if (mode_is_float(mode)) {
827 if (USE_SSE2(env->cg))
828 return gen_binop(env, op1, op2, new_rd_ia32_xSub);
830 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
835 /* No expr_op means, that we have two const - one symconst and */
836 /* one tarval or another symconst - because this case is not */
837 /* covered by constant folding */
838 /* We need to check for: */
839 /* 1) symconst + const -> becomes a LEA */
840 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
841 /* linker doesn't support two symconsts */
843 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
844 /* this is the 2nd case */
845 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
846 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
847 set_ia32_am_sc_sign(new_op);
848 set_ia32_am_flavour(new_op, ia32_am_OB);
850 DBG_OPT_LEA1(op2, new_op);
853 /* this is the 1st case */
854 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
856 DBG_OPT_LEA2(op1, op2, new_op);
858 if (get_ia32_op_type(op1) == ia32_SymConst) {
859 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
860 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
863 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
864 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
865 set_ia32_am_sc_sign(new_op);
867 set_ia32_am_flavour(new_op, ia32_am_O);
871 set_ia32_am_support(new_op, ia32_am_Source);
872 set_ia32_op_type(new_op, ia32_AddrModeS);
874 /* Lea doesn't need a Proj */
878 /* This is expr - const */
879 new_op = gen_imm_Sub(env, expr_op, imm_op);
882 set_ia32_am_support(new_op, ia32_am_Dest);
885 /* This is a normal sub */
886 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
889 set_ia32_am_support(new_op, ia32_am_Full);
893 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
895 set_ia32_res_mode(new_op, mode);
897 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Sub_res);
903 * Generates an ia32 DivMod with additional infrastructure for the
904 * register allocator if needed.
906 * @param env The transformation environment
907 * @param dividend -no comment- :)
908 * @param divisor -no comment- :)
909 * @param dm_flav flavour_Div/Mod/DivMod
910 * @return The created ia32 DivMod node
912 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
914 ir_node *edx_node, *cltd;
916 dbg_info *dbg = env->dbg;
917 ir_graph *irg = env->irg;
918 ir_node *block = env->block;
919 ir_mode *mode = env->mode;
920 ir_node *irn = env->irn;
925 mem = get_Div_mem(irn);
926 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
929 mem = get_Mod_mem(irn);
930 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
933 mem = get_DivMod_mem(irn);
934 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
940 if (mode_is_signed(mode)) {
941 /* in signed mode, we need to sign extend the dividend */
942 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
943 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
944 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
947 edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
948 set_ia32_Const_type(edx_node, ia32_Const);
949 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
952 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
954 set_ia32_n_res(res, 2);
956 /* Only one proj is used -> We must add a second proj and */
957 /* connect this one to a Keep node to eat up the second */
958 /* destroyed register. */
959 if (get_irn_n_edges(irn) == 1) {
960 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
961 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
963 if (get_irn_op(irn) == op_Div) {
964 set_Proj_proj(proj, pn_DivMod_res_div);
965 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
968 set_Proj_proj(proj, pn_DivMod_res_mod);
969 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
972 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
975 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
977 set_ia32_res_mode(res, mode_Is);
984 * Wrapper for generate_DivMod. Sets flavour_Mod.
986 * @param env The transformation environment
988 static ir_node *gen_Mod(ia32_transform_env_t *env) {
989 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
993 * Wrapper for generate_DivMod. Sets flavour_Div.
995 * @param env The transformation environment
997 static ir_node *gen_Div(ia32_transform_env_t *env) {
998 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
1002 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1004 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
1005 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
1011 * Creates an ia32 floating Div.
1013 * @param env The transformation environment
1014 * @return The created ia32 xDiv node
1016 static ir_node *gen_Quot(ia32_transform_env_t *env) {
1017 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1019 ir_node *nomem = new_rd_NoMem(env->irg);
1020 ir_node *op1 = get_Quot_left(env->irn);
1021 ir_node *op2 = get_Quot_right(env->irn);
1024 if (USE_SSE2(env->cg)) {
1025 if (is_ia32_xConst(op2)) {
1026 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
1027 set_ia32_am_support(new_op, ia32_am_None);
1028 set_ia32_Immop_attr(new_op, op2);
1031 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1032 set_ia32_am_support(new_op, ia32_am_Source);
1036 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1037 set_ia32_am_support(new_op, ia32_am_Source);
1039 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
1040 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1048 * Creates an ia32 Shl.
1050 * @param env The transformation environment
1051 * @return The created ia32 Shl node
1053 static ir_node *gen_Shl(ia32_transform_env_t *env) {
1054 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
1060 * Creates an ia32 Shr.
1062 * @param env The transformation environment
1063 * @return The created ia32 Shr node
1065 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1066 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1072 * Creates an ia32 Shrs.
1074 * @param env The transformation environment
1075 * @return The created ia32 Shrs node
1077 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1078 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1084 * Creates an ia32 RotL.
1086 * @param env The transformation environment
1087 * @param op1 The first operator
1088 * @param op2 The second operator
1089 * @return The created ia32 RotL node
1091 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1092 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1098 * Creates an ia32 RotR.
1099 * NOTE: There is no RotR with immediate because this would always be a RotL
1100 * "imm-mode_size_bits" which can be pre-calculated.
1102 * @param env The transformation environment
1103 * @param op1 The first operator
1104 * @param op2 The second operator
1105 * @return The created ia32 RotR node
1107 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1108 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1114 * Creates an ia32 RotR or RotL (depending on the found pattern).
1116 * @param env The transformation environment
1117 * @return The created ia32 RotL or RotR node
1119 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1120 ir_node *rotate = NULL;
1121 ir_node *op1 = get_Rot_left(env->irn);
1122 ir_node *op2 = get_Rot_right(env->irn);
1124 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1125 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1126 that means we can create a RotR instead of an Add and a RotL */
1129 ir_node *pred = get_Proj_pred(op2);
1131 if (is_ia32_Add(pred)) {
1132 ir_node *pred_pred = get_irn_n(pred, 2);
1133 tarval *tv = get_ia32_Immop_tarval(pred);
1134 long bits = get_mode_size_bits(env->mode);
1136 if (is_Proj(pred_pred)) {
1137 pred_pred = get_Proj_pred(pred_pred);
1140 if (is_ia32_Minus(pred_pred) &&
1141 tarval_is_long(tv) &&
1142 get_tarval_long(tv) == bits)
1144 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1145 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1152 rotate = gen_RotL(env, op1, op2);
1161 * Transforms a Minus node.
1163 * @param env The transformation environment
1164 * @param op The Minus operand
1165 * @return The created ia32 Minus node
1167 static ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1172 if (mode_is_float(env->mode)) {
1174 if (USE_SSE2(env->cg)) {
1175 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1176 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1177 ir_node *nomem = new_rd_NoMem(env->irg);
1179 new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1181 size = get_mode_size_bits(env->mode);
1182 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1184 set_ia32_sc(new_op, name);
1186 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1188 set_ia32_res_mode(new_op, env->mode);
1189 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1191 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
1194 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1195 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1199 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1206 * Transforms a Minus node.
1208 * @param env The transformation environment
1209 * @return The created ia32 Minus node
1211 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1212 return gen_Minus_ex(env, get_Minus_op(env->irn));
1217 * Transforms a Not node.
1219 * @param env The transformation environment
1220 * @return The created ia32 Not node
1222 static ir_node *gen_Not(ia32_transform_env_t *env) {
1223 assert (! mode_is_float(env->mode));
1224 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1230 * Transforms an Abs node.
1232 * @param env The transformation environment
1233 * @return The created ia32 Abs node
1235 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1236 ir_node *res, *p_eax, *p_edx;
1237 dbg_info *dbg = env->dbg;
1238 ir_mode *mode = env->mode;
1239 ir_graph *irg = env->irg;
1240 ir_node *block = env->block;
1241 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1242 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1243 ir_node *nomem = new_NoMem();
1244 ir_node *op = get_Abs_op(env->irn);
1248 if (mode_is_float(mode)) {
1250 if (USE_SSE2(env->cg)) {
1251 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1253 size = get_mode_size_bits(mode);
1254 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1256 set_ia32_sc(res, name);
1258 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1260 set_ia32_res_mode(res, mode);
1261 set_ia32_immop_type(res, ia32_ImmSymConst);
1263 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
1266 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1267 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1271 res = new_rd_ia32_Cdq(dbg, irg, block, op);
1272 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1273 set_ia32_res_mode(res, mode);
1275 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
1276 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
1278 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1279 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1280 set_ia32_res_mode(res, mode);
1282 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
1284 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1285 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1286 set_ia32_res_mode(res, mode);
1288 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
1297 * Transforms a Load.
1299 * @param env The transformation environment
1300 * @return the created ia32 Load node
1302 static ir_node *gen_Load(ia32_transform_env_t *env) {
1303 ir_node *node = env->irn;
1304 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1305 ir_node *ptr = get_Load_ptr(node);
1306 ir_node *lptr = ptr;
1307 ir_mode *mode = get_Load_mode(node);
1310 ia32_am_flavour_t am_flav = ia32_B;
1312 /* address might be a constant (symconst or absolute address) */
1313 if (is_ia32_Const(ptr)) {
1318 if (mode_is_float(mode)) {
1320 if (USE_SSE2(env->cg))
1321 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1323 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1326 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1329 /* base is an constant address */
1331 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1332 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1335 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1341 set_ia32_am_support(new_op, ia32_am_Source);
1342 set_ia32_op_type(new_op, ia32_AddrModeS);
1343 set_ia32_am_flavour(new_op, am_flav);
1344 set_ia32_ls_mode(new_op, mode);
1346 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1354 * Transforms a Store.
1356 * @param env The transformation environment
1357 * @return the created ia32 Store node
1359 static ir_node *gen_Store(ia32_transform_env_t *env) {
1360 ir_node *node = env->irn;
1361 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1362 ir_node *val = get_Store_value(node);
1363 ir_node *ptr = get_Store_ptr(node);
1364 ir_node *sptr = ptr;
1365 ir_node *mem = get_Store_mem(node);
1366 ir_mode *mode = get_irn_mode(val);
1367 ir_node *sval = val;
1370 ia32_am_flavour_t am_flav = ia32_B;
1371 ia32_immop_type_t immop = ia32_ImmNone;
1373 if (! mode_is_float(mode)) {
1374 /* in case of storing a const (but not a symconst) -> make it an attribute */
1375 if (is_ia32_Cnst(val)) {
1376 switch (get_ia32_op_type(val)) {
1378 immop = ia32_ImmConst;
1381 immop = ia32_ImmSymConst;
1384 assert(0 && "unsupported Const type");
1390 /* address might be a constant (symconst or absolute address) */
1391 if (is_ia32_Const(ptr)) {
1396 if (mode_is_float(mode)) {
1398 if (USE_SSE2(env->cg))
1399 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1401 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1403 else if (get_mode_size_bits(mode) == 8) {
1404 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1407 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1410 /* stored const is an attribute (saves a register) */
1411 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1412 set_ia32_Immop_attr(new_op, val);
1415 /* base is an constant address */
1417 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1418 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1421 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1427 set_ia32_am_support(new_op, ia32_am_Dest);
1428 set_ia32_op_type(new_op, ia32_AddrModeD);
1429 set_ia32_am_flavour(new_op, am_flav);
1430 set_ia32_ls_mode(new_op, get_irn_mode(val));
1431 set_ia32_immop_type(new_op, immop);
1433 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1441 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1443 * @param env The transformation environment
1444 * @return The transformed node.
1446 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1447 dbg_info *dbg = env->dbg;
1448 ir_graph *irg = env->irg;
1449 ir_node *block = env->block;
1450 ir_node *node = env->irn;
1451 ir_node *sel = get_Cond_selector(node);
1452 ir_mode *sel_mode = get_irn_mode(sel);
1453 ir_node *res = NULL;
1454 ir_node *pred = NULL;
1455 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1456 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1458 if (is_Proj(sel) && sel_mode == mode_b) {
1459 ir_node *nomem = new_NoMem();
1461 pred = get_Proj_pred(sel);
1463 /* get both compare operators */
1464 cmp_a = get_Cmp_left(pred);
1465 cmp_b = get_Cmp_right(pred);
1467 /* check if we can use a CondJmp with immediate */
1468 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1469 expr = get_expr_op(cmp_a, cmp_b);
1472 pn_Cmp pnc = get_Proj_proj(sel);
1474 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1475 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1476 /* a Cmp A =/!= 0 */
1477 ir_node *op1 = expr;
1478 ir_node *op2 = expr;
1479 ir_node *and = skip_Proj(expr);
1480 const char *cnst = NULL;
1482 /* check, if expr is an only once used And operation */
1483 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1484 op1 = get_irn_n(and, 2);
1485 op2 = get_irn_n(and, 3);
1487 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1489 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1490 set_ia32_pncode(res, get_Proj_proj(sel));
1491 set_ia32_res_mode(res, get_irn_mode(op1));
1494 copy_ia32_Immop_attr(res, and);
1497 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1502 if (mode_is_float(get_irn_mode(expr))) {
1504 if (USE_SSE2(env->cg))
1505 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1511 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1513 set_ia32_Immop_attr(res, cnst);
1514 set_ia32_res_mode(res, get_irn_mode(expr));
1517 if (mode_is_float(get_irn_mode(cmp_a))) {
1519 if (USE_SSE2(env->cg))
1520 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1523 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1524 proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
1525 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1529 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1530 set_ia32_commutative(res);
1532 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1535 set_ia32_pncode(res, get_Proj_proj(sel));
1536 //set_ia32_am_support(res, ia32_am_Source);
1539 /* determine the smallest switch case value */
1540 int switch_min = INT_MAX;
1541 const ir_edge_t *edge;
1544 foreach_out_edge(node, edge) {
1545 int pn = get_Proj_proj(get_edge_src_irn(edge));
1546 switch_min = pn < switch_min ? pn : switch_min;
1550 /* if smallest switch case is not 0 we need an additional sub */
1551 snprintf(buf, sizeof(buf), "%d", switch_min);
1552 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1553 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1554 sub_ia32_am_offs(res, buf);
1555 set_ia32_am_flavour(res, ia32_am_OB);
1556 set_ia32_am_support(res, ia32_am_Source);
1557 set_ia32_op_type(res, ia32_AddrModeS);
1560 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1561 set_ia32_pncode(res, get_Cond_defaultProj(node));
1562 set_ia32_res_mode(res, get_irn_mode(sel));
1565 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1572 * Transforms a CopyB node.
1574 * @param env The transformation environment
1575 * @return The transformed node.
1577 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1578 ir_node *res = NULL;
1579 dbg_info *dbg = env->dbg;
1580 ir_graph *irg = env->irg;
1581 ir_mode *mode = env->mode;
1582 ir_node *block = env->block;
1583 ir_node *node = env->irn;
1584 ir_node *src = get_CopyB_src(node);
1585 ir_node *dst = get_CopyB_dst(node);
1586 ir_node *mem = get_CopyB_mem(node);
1587 int size = get_type_size_bytes(get_CopyB_type(node));
1590 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1591 /* then we need the size explicitly in ECX. */
1592 if (size >= 16 * 4) {
1593 rem = size & 0x3; /* size % 4 */
1596 res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
1597 set_ia32_op_type(res, ia32_Const);
1598 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1600 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1601 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1604 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1605 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1606 set_ia32_immop_type(res, ia32_ImmConst);
1609 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1617 * Transforms a Mux node into CMov.
1619 * @param env The transformation environment
1620 * @return The transformed node.
1622 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1624 ir_node *node = env->irn;
1625 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1626 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1628 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1635 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *cmp_a, ir_node *cmp_b, \
1636 ir_node *psi_true, ir_node *psi_default, ir_mode *mode);
1639 * Transforms a Psi node into CMov.
1641 * @param env The transformation environment
1642 * @return The transformed node.
1644 static ir_node *gen_Psi(ia32_transform_env_t *env) {
1645 ia32_code_gen_t *cg = env->cg;
1646 dbg_info *dbg = env->dbg;
1647 ir_graph *irg = env->irg;
1648 ir_mode *mode = env->mode;
1649 ir_node *block = env->block;
1650 ir_node *node = env->irn;
1651 ir_node *cmp_proj = get_Mux_sel(node);
1652 ir_node *psi_true = get_Psi_val(node, 0);
1653 ir_node *psi_default = get_Psi_default(node);
1654 ir_node *noreg = ia32_new_NoReg_gp(cg);
1655 ir_node *nomem = new_rd_NoMem(irg);
1656 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
1659 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
1661 cmp = get_Proj_pred(cmp_proj);
1662 cmp_a = get_Cmp_left(cmp);
1663 cmp_b = get_Cmp_right(cmp);
1664 pnc = get_Proj_proj(cmp_proj);
1666 if (mode_is_float(mode)) {
1667 /* floating point psi */
1670 /* 1st case: compare operands are float too */
1672 /* psi(cmp(a, b), t, f) can be done as: */
1673 /* tmp = cmp a, b */
1674 /* tmp2 = t and tmp */
1675 /* tmp3 = f and not tmp */
1676 /* res = tmp2 or tmp3 */
1678 /* in case the compare operands are int, we move them into xmm register */
1679 if (! mode_is_float(get_irn_mode(cmp_a))) {
1680 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, node, mode_D);
1681 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, node, mode_D);
1683 pnc += pn_Cmp_Uo; /* transform integer compare to fp compare */
1686 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1687 set_ia32_pncode(new_op, pnc);
1688 set_ia32_am_support(new_op, ia32_am_Source);
1689 set_ia32_res_mode(new_op, mode);
1690 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1691 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xCmp_res);
1693 and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, psi_true, new_op, nomem);
1694 set_ia32_am_support(and1, ia32_am_Source);
1695 set_ia32_res_mode(and1, mode);
1696 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
1697 and1 = new_rd_Proj(dbg, irg, block, and1, mode, pn_ia32_xAnd_res);
1699 and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, psi_default, new_op, nomem);
1700 set_ia32_am_support(and2, ia32_am_Source);
1701 set_ia32_res_mode(and2, mode);
1702 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
1703 and2 = new_rd_Proj(dbg, irg, block, and2, mode, pn_ia32_xAndNot_res);
1705 new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
1706 set_ia32_am_support(new_op, ia32_am_Source);
1707 set_ia32_res_mode(new_op, mode);
1708 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1709 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xOr_res);
1713 new_op = new_rd_ia32_vfCMov(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1714 set_ia32_pncode(new_op, pnc);
1715 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1720 construct_binop_func *set_func = NULL;
1721 cmov_func_t *cmov_func = NULL;
1723 if (mode_is_float(get_irn_mode(cmp_a))) {
1724 /* 1st case: compare operands are floats */
1729 set_func = new_rd_ia32_xCmpSet;
1730 cmov_func = new_rd_ia32_xCmpCMov;
1734 set_func = new_rd_ia32_vfCmpSet;
1735 cmov_func = new_rd_ia32_vfCmpCMov;
1738 pnc -= pn_Cmp_Uo; /* fp compare -> int compare */
1741 /* 2nd case: compare operand are integer too */
1742 set_func = new_rd_ia32_CmpSet;
1743 cmov_func = new_rd_ia32_CmpCMov;
1746 /* create the nodes */
1748 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1749 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1750 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1751 set_ia32_pncode(get_Proj_pred(new_op), pnc);
1753 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1754 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1755 /* we invert condition and set default to 0 */
1756 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1757 set_ia32_pncode(get_Proj_pred(new_op), get_negated_pnc(pnc, mode));
1760 /* otherwise: use CMOVcc */
1761 new_op = cmov_func(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1762 set_ia32_pncode(new_op, pnc);
1763 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1772 * Following conversion rules apply:
1776 * 1) n bit -> m bit n > m (downscale)
1777 * a) target is signed: movsx
1778 * b) target is unsigned: and with lower bits sets
1779 * 2) n bit -> m bit n == m (sign change)
1781 * 3) n bit -> m bit n < m (upscale)
1782 * a) source is signed: movsx
1783 * b) source is unsigned: and with lower bits sets
1787 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1791 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1792 * if target mode < 32bit: additional INT -> INT conversion (see above)
1796 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1797 * x87 is mode_E internally, conversions happen only at load and store
1798 * in non-strict semantic
1802 * Create a conversion from x87 state register to general purpose.
1804 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1805 ia32_code_gen_t *cg = env->cg;
1806 entity *ent = cg->fp_to_gp;
1807 ir_graph *irg = env->irg;
1808 ir_node *block = env->block;
1809 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1810 ir_node *op = get_Conv_op(env->irn);
1811 ir_node *fist, *mem, *load;
1814 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1815 ent = cg->fp_to_gp =
1816 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1820 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
1822 set_ia32_frame_ent(fist, ent);
1823 set_ia32_use_frame(fist);
1824 set_ia32_am_support(fist, ia32_am_Dest);
1825 set_ia32_op_type(fist, ia32_AddrModeD);
1826 set_ia32_am_flavour(fist, ia32_B);
1827 set_ia32_ls_mode(fist, mode_E);
1829 mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
1832 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1834 set_ia32_frame_ent(load, ent);
1835 set_ia32_use_frame(load);
1836 set_ia32_am_support(load, ia32_am_Source);
1837 set_ia32_op_type(load, ia32_AddrModeS);
1838 set_ia32_am_flavour(load, ia32_B);
1839 set_ia32_ls_mode(load, tgt_mode);
1841 return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
1845 * Create a conversion from x87 state register to general purpose.
1847 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1848 ia32_code_gen_t *cg = env->cg;
1849 entity *ent = cg->gp_to_fp;
1850 ir_graph *irg = env->irg;
1851 ir_node *block = env->block;
1852 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1853 ir_node *nomem = get_irg_no_mem(irg);
1854 ir_node *op = get_Conv_op(env->irn);
1855 ir_node *fild, *store, *mem;
1859 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
1860 ent = cg->gp_to_fp =
1861 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
1864 /* first convert to 32 bit */
1865 src_bits = get_mode_size_bits(src_mode);
1866 if (src_bits == 8) {
1867 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
1868 op = new_r_Proj(irg, block, op, mode_Is, 0);
1870 else if (src_bits < 32) {
1871 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
1872 op = new_r_Proj(irg, block, op, mode_Is, 0);
1876 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
1878 set_ia32_frame_ent(store, ent);
1879 set_ia32_use_frame(store);
1881 set_ia32_am_support(store, ia32_am_Dest);
1882 set_ia32_op_type(store, ia32_AddrModeD);
1883 set_ia32_am_flavour(store, ia32_B);
1884 set_ia32_ls_mode(store, mode_Is);
1886 mem = new_r_Proj(irg, block, store, mode_M, 0);
1889 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1891 set_ia32_frame_ent(fild, ent);
1892 set_ia32_use_frame(fild);
1893 set_ia32_am_support(fild, ia32_am_Source);
1894 set_ia32_op_type(fild, ia32_AddrModeS);
1895 set_ia32_am_flavour(fild, ia32_B);
1896 set_ia32_ls_mode(fild, mode_E);
1898 return new_r_Proj(irg, block, fild, mode_E, 0);
1902 * Transforms a Conv node.
1904 * @param env The transformation environment
1905 * @return The created ia32 Conv node
1907 static ir_node *gen_Conv(ia32_transform_env_t *env) {
1908 dbg_info *dbg = env->dbg;
1909 ir_graph *irg = env->irg;
1910 ir_node *op = get_Conv_op(env->irn);
1911 ir_mode *src_mode = get_irn_mode(op);
1912 ir_mode *tgt_mode = env->mode;
1913 int src_bits = get_mode_size_bits(src_mode);
1914 int tgt_bits = get_mode_size_bits(tgt_mode);
1916 ir_node *block = env->block;
1917 ir_node *new_op = NULL;
1918 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1919 ir_node *nomem = new_rd_NoMem(irg);
1921 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1923 if (src_mode == tgt_mode) {
1924 /* this can happen when changing mode_P to mode_Is */
1925 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1926 edges_reroute(env->irn, op, irg);
1928 else if (mode_is_float(src_mode)) {
1929 /* we convert from float ... */
1930 if (mode_is_float(tgt_mode)) {
1932 if (USE_SSE2(env->cg)) {
1933 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1934 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
1935 pn = pn_ia32_Conv_FP2FP_res;
1938 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
1939 edges_reroute(env->irn, op, irg);
1944 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1945 if (USE_SSE2(env->cg)) {
1946 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
1947 pn = pn_ia32_Conv_FP2I_res;
1950 return gen_x87_fp_to_gp(env, tgt_mode);
1952 /* if target mode is not int: add an additional downscale convert */
1953 if (tgt_bits < 32) {
1954 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1955 set_ia32_am_support(new_op, ia32_am_Source);
1956 set_ia32_tgt_mode(new_op, tgt_mode);
1957 set_ia32_src_mode(new_op, src_mode);
1959 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, pn_ia32_Conv_FP2I_res);
1961 if (tgt_bits == 8 || src_bits == 8) {
1962 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
1963 pn = pn_ia32_Conv_I2I8Bit_res;
1966 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
1967 pn = pn_ia32_Conv_I2I_res;
1973 /* we convert from int ... */
1974 if (mode_is_float(tgt_mode)) {
1977 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1978 if (USE_SSE2(env->cg)) {
1979 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
1980 pn = pn_ia32_Conv_I2FP_res;
1983 return gen_x87_gp_to_fp(env, src_mode);
1987 if (get_mode_size_bits(src_mode) == tgt_bits) {
1988 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
1989 edges_reroute(env->irn, op, irg);
1992 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
1993 if (tgt_bits == 8 || src_bits == 8) {
1994 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
1995 pn = pn_ia32_Conv_I2I8Bit_res;
1998 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
1999 pn = pn_ia32_Conv_I2I_res;
2006 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2007 set_ia32_tgt_mode(new_op, tgt_mode);
2008 set_ia32_src_mode(new_op, src_mode);
2010 set_ia32_am_support(new_op, ia32_am_Source);
2012 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, pn);
2020 /********************************************
2023 * | |__ ___ _ __ ___ __| | ___ ___
2024 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2025 * | |_) | __/ | | | (_) | (_| | __/\__ \
2026 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2028 ********************************************/
2030 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
2031 ir_node *new_op = NULL;
2032 ir_node *node = env->irn;
2033 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2034 ir_node *mem = new_rd_NoMem(env->irg);
2035 ir_node *ptr = get_irn_n(node, 0);
2036 entity *ent = be_get_frame_entity(node);
2037 ir_mode *mode = env->mode;
2039 // /* If the StackParam has only one user -> */
2040 // /* put it in the Block where the user resides */
2041 // if (get_irn_n_edges(node) == 1) {
2042 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
2045 if (mode_is_float(mode)) {
2047 if (USE_SSE2(env->cg))
2048 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2050 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2053 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2056 set_ia32_frame_ent(new_op, ent);
2057 set_ia32_use_frame(new_op);
2059 set_ia32_am_support(new_op, ia32_am_Source);
2060 set_ia32_op_type(new_op, ia32_AddrModeS);
2061 set_ia32_am_flavour(new_op, ia32_B);
2062 set_ia32_ls_mode(new_op, mode);
2064 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2066 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
2070 * Transforms a FrameAddr into an ia32 Add.
2072 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
2073 ir_node *new_op = NULL;
2074 ir_node *node = env->irn;
2075 ir_node *op = get_irn_n(node, 0);
2076 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2077 ir_node *nomem = new_rd_NoMem(env->irg);
2079 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
2080 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
2081 set_ia32_am_support(new_op, ia32_am_Full);
2082 set_ia32_use_frame(new_op);
2083 set_ia32_immop_type(new_op, ia32_ImmConst);
2084 set_ia32_commutative(new_op);
2086 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2088 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
2092 * Transforms a FrameLoad into an ia32 Load.
2094 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
2095 ir_node *new_op = NULL;
2096 ir_node *node = env->irn;
2097 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2098 ir_node *mem = get_irn_n(node, 0);
2099 ir_node *ptr = get_irn_n(node, 1);
2100 entity *ent = be_get_frame_entity(node);
2101 ir_mode *mode = get_type_mode(get_entity_type(ent));
2103 if (mode_is_float(mode)) {
2105 if (USE_SSE2(env->cg))
2106 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2108 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2111 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2113 set_ia32_frame_ent(new_op, ent);
2114 set_ia32_use_frame(new_op);
2116 set_ia32_am_support(new_op, ia32_am_Source);
2117 set_ia32_op_type(new_op, ia32_AddrModeS);
2118 set_ia32_am_flavour(new_op, ia32_B);
2119 set_ia32_ls_mode(new_op, mode);
2121 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2128 * Transforms a FrameStore into an ia32 Store.
2130 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
2131 ir_node *new_op = NULL;
2132 ir_node *node = env->irn;
2133 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2134 ir_node *mem = get_irn_n(node, 0);
2135 ir_node *ptr = get_irn_n(node, 1);
2136 ir_node *val = get_irn_n(node, 2);
2137 entity *ent = be_get_frame_entity(node);
2138 ir_mode *mode = get_irn_mode(val);
2140 if (mode_is_float(mode)) {
2142 if (USE_SSE2(env->cg))
2143 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2145 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2147 else if (get_mode_size_bits(mode) == 8) {
2148 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2151 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2154 set_ia32_frame_ent(new_op, ent);
2155 set_ia32_use_frame(new_op);
2157 set_ia32_am_support(new_op, ia32_am_Dest);
2158 set_ia32_op_type(new_op, ia32_AddrModeD);
2159 set_ia32_am_flavour(new_op, ia32_B);
2160 set_ia32_ls_mode(new_op, mode);
2162 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2168 * This function just sets the register for the Unknown node
2169 * as this is not done during register allocation because Unknown
2170 * is an "ignore" node.
2172 static ir_node *gen_Unknown(ia32_transform_env_t *env) {
2173 ir_mode *mode = env->mode;
2174 ir_node *irn = env->irn;
2176 if (mode_is_float(mode)) {
2177 if (USE_SSE2(env->cg))
2178 arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
2180 arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
2182 else if (mode_is_int(mode) || mode_is_reference(mode)) {
2183 arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
2186 assert(0 && "unsupported Unknown-Mode");
2193 /*********************************************************
2196 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
2197 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
2198 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
2199 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
2201 *********************************************************/
2204 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
2205 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2207 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
2208 ia32_transform_env_t tenv;
2209 ir_node *in1, *in2, *noreg, *nomem, *res;
2210 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
2212 /* Return if AM node or not a Sub or xSub */
2213 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_xSub(irn)))
2216 noreg = ia32_new_NoReg_gp(cg);
2217 nomem = new_rd_NoMem(cg->irg);
2218 in1 = get_irn_n(irn, 2);
2219 in2 = get_irn_n(irn, 3);
2220 in1_reg = arch_get_irn_register(cg->arch_env, in1);
2221 in2_reg = arch_get_irn_register(cg->arch_env, in2);
2222 out_reg = get_ia32_out_reg(irn, 0);
2224 tenv.block = get_nodes_block(irn);
2225 tenv.dbg = get_irn_dbg_info(irn);
2228 tenv.mode = get_ia32_res_mode(irn);
2230 DEBUG_ONLY(tenv.mod = cg->mod;)
2232 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
2233 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
2234 /* generate the neg src2 */
2235 res = gen_Minus_ex(&tenv, in2);
2236 arch_set_irn_register(cg->arch_env, res, in2_reg);
2238 /* add to schedule */
2239 sched_add_before(irn, res);
2241 /* generate the add */
2242 if (mode_is_float(tenv.mode)) {
2243 res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2244 set_ia32_am_support(res, ia32_am_Source);
2247 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2248 set_ia32_am_support(res, ia32_am_Full);
2249 set_ia32_commutative(res);
2251 set_ia32_res_mode(res, tenv.mode);
2253 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
2255 slots = get_ia32_slots(res);
2258 /* add to schedule */
2259 sched_add_before(irn, res);
2261 /* remove the old sub */
2264 DBG_OPT_SUB2NEGADD(irn, res);
2266 /* exchange the add and the sub */
2272 * Transforms a LEA into an Add if possible
2273 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2275 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
2276 ia32_am_flavour_t am_flav;
2278 ir_node *res = NULL;
2279 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
2281 ia32_transform_env_t tenv;
2282 const arch_register_t *out_reg, *base_reg, *index_reg;
2285 if (! is_ia32_Lea(irn))
2288 am_flav = get_ia32_am_flavour(irn);
2290 /* only some LEAs can be transformed to an Add */
2291 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
2294 noreg = ia32_new_NoReg_gp(cg);
2295 nomem = new_rd_NoMem(cg->irg);
2298 base = get_irn_n(irn, 0);
2299 index = get_irn_n(irn,1);
2301 offs = get_ia32_am_offs(irn);
2303 /* offset has a explicit sign -> we need to skip + */
2304 if (offs && offs[0] == '+')
2307 out_reg = arch_get_irn_register(cg->arch_env, irn);
2308 base_reg = arch_get_irn_register(cg->arch_env, base);
2309 index_reg = arch_get_irn_register(cg->arch_env, index);
2311 tenv.block = get_nodes_block(irn);
2312 tenv.dbg = get_irn_dbg_info(irn);
2315 DEBUG_ONLY(tenv.mod = cg->mod;)
2316 tenv.mode = get_irn_mode(irn);
2319 switch(get_ia32_am_flavour(irn)) {
2321 /* out register must be same as base register */
2322 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2328 /* out register must be same as base register */
2329 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2336 /* out register must be same as index register */
2337 if (! REGS_ARE_EQUAL(out_reg, index_reg))
2344 /* out register must be same as one in register */
2345 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
2349 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
2354 /* in registers a different from out -> no Add possible */
2361 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
2362 arch_set_irn_register(cg->arch_env, res, out_reg);
2363 set_ia32_op_type(res, ia32_Normal);
2364 set_ia32_commutative(res);
2365 set_ia32_res_mode(res, tenv.mode);
2368 set_ia32_cnst(res, offs);
2369 set_ia32_immop_type(res, ia32_ImmConst);
2372 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
2374 /* add Add to schedule */
2375 sched_add_before(irn, res);
2377 DBG_OPT_LEA2ADD(irn, res);
2379 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, pn_ia32_Add_res);
2381 /* add result Proj to schedule */
2382 sched_add_before(irn, res);
2384 /* remove the old LEA */
2387 /* exchange the Add and the LEA */
2392 * the BAD transformer.
2394 static ir_node *bad_transform(ia32_transform_env_t *env) {
2395 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2401 * Enters all transform functions into the generic pointer
2403 void ia32_register_transformers(void) {
2404 ir_op *op_Max, *op_Min, *op_Mulh;
2406 /* first clear the generic function pointer for all ops */
2407 clear_irp_opcodes_generic_func();
2409 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2410 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
2457 /* constant transformation happens earlier */
2481 /* set the register for all Unknown nodes */
2484 op_Max = get_op_Max();
2487 op_Min = get_op_Min();
2490 op_Mulh = get_op_Mulh();
2499 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
2502 * Transforms the given firm node (and maybe some other related nodes)
2503 * into one or more assembler nodes.
2505 * @param node the firm node
2506 * @param env the debug module
2508 void ia32_transform_node(ir_node *node, void *env) {
2509 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2510 ir_op *op = get_irn_op(node);
2511 ir_node *asm_node = NULL;
2517 /* link arguments pointing to Unknown to the UNKNOWN Proj */
2518 for (i = get_irn_arity(node) - 1; i >= 0; i--) {
2519 if (is_Unknown(get_irn_n(node, i)))
2520 set_irn_n(node, i, be_get_unknown_for_mode(cg, get_irn_mode(get_irn_n(node, i))));
2523 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
2524 if (op->ops.generic) {
2525 ia32_transform_env_t tenv;
2526 transform_func *transform = (transform_func *)op->ops.generic;
2528 tenv.block = get_nodes_block(node);
2529 tenv.dbg = get_irn_dbg_info(node);
2530 tenv.irg = current_ir_graph;
2532 tenv.mode = get_irn_mode(node);
2534 DEBUG_ONLY(tenv.mod = cg->mod;)
2536 asm_node = (*transform)(&tenv);
2539 /* exchange nodes if a new one was generated */
2541 exchange(node, asm_node);
2542 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2545 DB((cg->mod, LEVEL_1, "ignored\n"));
2550 * Transforms a psi condition.
2552 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
2555 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
2556 set_irn_mode(cond, mode);
2558 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
2559 ir_node *in = get_irn_n(cond, i);
2561 /* if in is a compare: transform into Set/xCmp */
2563 ir_node *new_op = NULL;
2564 ir_node *cmp = get_Proj_pred(in);
2565 ir_node *cmp_a = get_Cmp_left(cmp);
2566 ir_node *cmp_b = get_Cmp_right(cmp);
2567 dbg_info *dbg = get_irn_dbg_info(cmp);
2568 ir_graph *irg = get_irn_irg(cmp);
2569 ir_node *block = get_nodes_block(cmp);
2570 ir_node *noreg = ia32_new_NoReg_gp(cg);
2571 ir_node *nomem = new_rd_NoMem(irg);
2572 int pnc = get_Proj_proj(in);
2574 /* this is a compare */
2575 if (mode_is_float(mode)) {
2576 /* Psi is float, we need a floating point compare */
2580 if (! mode_is_float(get_irn_mode(cmp_a))) {
2581 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
2582 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
2586 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
2587 set_ia32_pncode(new_op, pnc);
2588 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
2597 ia32_transform_env_t tenv;
2607 new_op = gen_binop(&tenv, cmp_a, cmp_b, new_rd_ia32_CmpSet);
2608 set_ia32_pncode(get_Proj_pred(new_op), pnc);
2611 /* exchange with old compare */
2612 exchange(in, new_op);
2615 /* another complex condition */
2616 transform_psi_cond(in, mode, cg);
2622 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
2623 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
2624 * compare, which causes the compare result to be stores in a register. The
2625 * "And"s and "Or"s are transformed later, we just have to set their mode right.
2627 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
2628 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2629 ir_node *psi_sel, *new_cmp, *block;
2634 if (get_irn_opcode(node) != iro_Psi)
2637 psi_sel = get_Psi_cond(node, 0);
2639 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
2640 if (is_Proj(psi_sel))
2643 mode = get_irn_mode(node);
2645 transform_psi_cond(psi_sel, mode, cg);
2647 irg = get_irn_irg(node);
2648 block = get_nodes_block(node);
2650 /* we need to compare the evaluated condition tree with 0 */
2652 /* BEWARE: new_r_Const_long works for floating point as well */
2653 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
2654 /* transform the const */
2655 ia32_place_consts_set_modes(new_cmp, cg);
2656 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne + (mode_is_float(mode) ? pn_Cmp_Uo : 0));
2658 set_Psi_cond(node, 0, new_cmp);