2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
98 static transform_config_t transform_config;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *op1, ir_node *op2);
109 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
110 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
113 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
116 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
117 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
118 ir_node *op1, ir_node *op2, ir_node *fpcw);
120 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *op);
123 /****************************************************************************************************
125 * | | | | / _| | | (_)
126 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
127 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
128 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
129 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
131 ****************************************************************************************************/
133 static ir_node *try_create_Immediate(ir_node *node,
134 char immediate_constraint_type);
136 static ir_node *create_immediate_or_transform(ir_node *node,
137 char immediate_constraint_type);
139 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
140 dbg_info *dbgi, ir_node *block,
141 ir_node *op, ir_node *orig_node);
144 * Return true if a mode can be stored in the GP register set
146 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
147 if(mode == mode_fpcw)
149 if(get_mode_size_bits(mode) > 32)
151 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
155 * creates a unique ident by adding a number to a tag
157 * @param tag the tag string, must contain a %d if a number
160 static ident *unique_id(const char *tag)
162 static unsigned id = 0;
165 snprintf(str, sizeof(str), tag, ++id);
166 return new_id_from_str(str);
170 * Get a primitive type for a mode.
172 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
174 pmap_entry *e = pmap_find(types, mode);
179 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
180 res = new_type_primitive(new_id_from_str(buf), mode);
181 set_type_alignment_bytes(res, 16);
182 pmap_insert(types, mode, res);
190 * Get an atomic entity that is initialized with a tarval
192 static ir_entity *create_float_const_entity(ir_node *cnst)
194 ia32_isa_t *isa = env_cg->isa;
195 tarval *tv = get_Const_tarval(cnst);
196 pmap_entry *e = pmap_find(isa->tv_ent, tv);
201 ir_mode *mode = get_irn_mode(cnst);
202 ir_type *tp = get_Const_type(cnst);
203 if (tp == firm_unknown_type)
204 tp = get_prim_type(isa->types, mode);
206 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
208 set_entity_ld_ident(res, get_entity_ident(res));
209 set_entity_visibility(res, visibility_local);
210 set_entity_variability(res, variability_constant);
211 set_entity_allocation(res, allocation_static);
213 /* we create a new entity here: It's initialization must resist on the
215 rem = current_ir_graph;
216 current_ir_graph = get_const_code_irg();
217 set_atomic_ent_value(res, new_Const_type(tv, tp));
218 current_ir_graph = rem;
220 pmap_insert(isa->tv_ent, tv, res);
228 static int is_Const_0(ir_node *node) {
229 return is_Const(node) && is_Const_null(node);
232 static int is_Const_1(ir_node *node) {
233 return is_Const(node) && is_Const_one(node);
236 static int is_Const_Minus_1(ir_node *node) {
237 return is_Const(node) && is_Const_all_one(node);
241 * returns true if constant can be created with a simple float command
243 static int is_simple_x87_Const(ir_node *node)
245 tarval *tv = get_Const_tarval(node);
247 if(tarval_is_null(tv) || tarval_is_one(tv))
250 /* TODO: match all the other float constants */
255 * Transforms a Const.
257 static ir_node *gen_Const(ir_node *node) {
258 ir_graph *irg = current_ir_graph;
259 ir_node *old_block = get_nodes_block(node);
260 ir_node *block = be_transform_node(old_block);
261 dbg_info *dbgi = get_irn_dbg_info(node);
262 ir_mode *mode = get_irn_mode(node);
264 if (mode_is_float(mode)) {
266 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
267 ir_node *nomem = new_NoMem();
271 if (USE_SSE2(env_cg)) {
272 if (is_Const_null(node)) {
273 load = new_rd_ia32_xZero(dbgi, irg, block);
274 set_ia32_ls_mode(load, mode);
277 floatent = create_float_const_entity(node);
279 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
281 set_ia32_op_type(load, ia32_AddrModeS);
282 set_ia32_am_sc(load, floatent);
283 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
284 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
287 if (is_Const_null(node)) {
288 load = new_rd_ia32_vfldz(dbgi, irg, block);
290 } else if (is_Const_one(node)) {
291 load = new_rd_ia32_vfld1(dbgi, irg, block);
294 floatent = create_float_const_entity(node);
296 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
297 set_ia32_op_type(load, ia32_AddrModeS);
298 set_ia32_am_sc(load, floatent);
299 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
300 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
302 set_ia32_ls_mode(load, mode);
305 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
307 /* Const Nodes before the initial IncSP are a bad idea, because
308 * they could be spilled and we have no SP ready at that point yet.
309 * So add a dependency to the initial frame pointer calculation to
310 * avoid that situation.
312 if (get_irg_start_block(irg) == block) {
313 add_irn_dep(load, get_irg_frame(irg));
316 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
320 tarval *tv = get_Const_tarval(node);
323 tv = tarval_convert_to(tv, mode_Iu);
325 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
327 panic("couldn't convert constant tarval (%+F)", node);
329 val = get_tarval_long(tv);
331 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
332 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
335 if (get_irg_start_block(irg) == block) {
336 add_irn_dep(cnst, get_irg_frame(irg));
344 * Transforms a SymConst.
346 static ir_node *gen_SymConst(ir_node *node) {
347 ir_graph *irg = current_ir_graph;
348 ir_node *old_block = get_nodes_block(node);
349 ir_node *block = be_transform_node(old_block);
350 dbg_info *dbgi = get_irn_dbg_info(node);
351 ir_mode *mode = get_irn_mode(node);
354 if (mode_is_float(mode)) {
355 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
356 ir_node *nomem = new_NoMem();
358 if (USE_SSE2(env_cg))
359 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
361 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
362 set_ia32_am_sc(cnst, get_SymConst_entity(node));
363 set_ia32_use_frame(cnst);
367 if(get_SymConst_kind(node) != symconst_addr_ent) {
368 panic("backend only support symconst_addr_ent (at %+F)", node);
370 entity = get_SymConst_entity(node);
371 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
374 /* Const Nodes before the initial IncSP are a bad idea, because
375 * they could be spilled and we have no SP ready at that point yet
377 if (get_irg_start_block(irg) == block) {
378 add_irn_dep(cnst, get_irg_frame(irg));
381 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
386 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
387 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
388 static const struct {
390 const char *ent_name;
391 const char *cnst_str;
394 } names [ia32_known_const_max] = {
395 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
396 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
397 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
398 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
399 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
401 static ir_entity *ent_cache[ia32_known_const_max];
403 const char *tp_name, *ent_name, *cnst_str;
411 ent_name = names[kct].ent_name;
412 if (! ent_cache[kct]) {
413 tp_name = names[kct].tp_name;
414 cnst_str = names[kct].cnst_str;
416 switch (names[kct].mode) {
417 case 0: mode = mode_Iu; break;
418 case 1: mode = mode_Lu; break;
419 default: mode = mode_F; break;
421 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
422 tp = new_type_primitive(new_id_from_str(tp_name), mode);
423 /* set the specified alignment */
424 set_type_alignment_bytes(tp, names[kct].align);
426 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
428 set_entity_ld_ident(ent, get_entity_ident(ent));
429 set_entity_visibility(ent, visibility_local);
430 set_entity_variability(ent, variability_constant);
431 set_entity_allocation(ent, allocation_static);
433 /* we create a new entity here: It's initialization must resist on the
435 rem = current_ir_graph;
436 current_ir_graph = get_const_code_irg();
437 cnst = new_Const(mode, tv);
438 current_ir_graph = rem;
440 set_atomic_ent_value(ent, cnst);
442 /* cache the entry */
443 ent_cache[kct] = ent;
446 return ent_cache[kct];
451 * Prints the old node name on cg obst and returns a pointer to it.
453 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
454 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
456 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
457 obstack_1grow(isa->name_obst, 0);
458 return obstack_finish(isa->name_obst);
462 int use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
464 ir_mode *mode = get_irn_mode(node);
468 /* float constants are always available */
469 if(is_Const(node) && mode_is_float(mode)
470 && !is_simple_x87_Const(node) && get_irn_n_edges(node) == 1) {
476 load = get_Proj_pred(node);
477 pn = get_Proj_proj(node);
478 if(!is_Load(load) || pn != pn_Load_res)
480 if(get_nodes_block(load) != block)
482 /* we only use address mode if we're the only user of the load */
483 if(get_irn_n_edges(node) > 1)
486 if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
489 /* don't do AM if other node inputs depend on the load (via mem-proj) */
490 if(other != NULL && get_nodes_block(other) == block
491 && heights_reachable_in_block(heights, other, load))
497 typedef struct ia32_address_mode_t ia32_address_mode_t;
498 struct ia32_address_mode_t {
502 ia32_op_type_t op_type;
509 static void build_address(ia32_address_mode_t *am, ir_node *node)
511 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
512 ia32_address_t *addr = &am->addr;
521 ir_entity *entity = create_float_const_entity(node);
522 addr->base = noreg_gp;
523 addr->index = noreg_gp;
524 addr->mem = new_NoMem();
525 addr->symconst_ent = entity;
527 am->ls_mode = get_irn_mode(node);
531 load = get_Proj_pred(node);
532 ptr = get_Load_ptr(load);
533 mem = get_Load_mem(load);
534 new_mem = be_transform_node(mem);
535 am->ls_mode = get_Load_mode(load);
536 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
538 /* construct load address */
539 ia32_create_address_mode(addr, ptr, 0);
546 base = be_transform_node(base);
552 index = be_transform_node(index);
560 static void set_address(ir_node *node, ia32_address_t *addr)
562 set_ia32_am_scale(node, addr->scale);
563 set_ia32_am_sc(node, addr->symconst_ent);
564 set_ia32_am_offs_int(node, addr->offset);
565 if(addr->symconst_sign)
566 set_ia32_am_sc_sign(node);
568 set_ia32_use_frame(node);
569 set_ia32_frame_ent(node, addr->frame_entity);
572 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
574 set_address(node, &am->addr);
576 set_ia32_op_type(node, am->op_type);
577 set_ia32_ls_mode(node, am->ls_mode);
579 set_ia32_commutative(node);
583 match_commutative = 1 << 0,
584 match_am_and_immediates = 1 << 1,
585 match_no_am = 1 << 2,
586 match_8_bit_am = 1 << 3,
587 match_16_bit_am = 1 << 4,
588 match_no_immediate = 1 << 5,
589 match_force_32bit_op = 1 << 6
592 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
593 ir_node *op1, ir_node *op2, match_flags_t flags)
595 ia32_address_t *addr = &am->addr;
596 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
599 ir_mode *mode = get_irn_mode(op2);
602 int use_am_and_immediates;
604 int mode_bits = get_mode_size_bits(mode);
606 memset(am, 0, sizeof(am[0]));
608 commutative = (flags & match_commutative) != 0;
609 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
610 use_am = ! (flags & match_no_am);
611 use_immediate = !(flags & match_no_immediate);
614 assert(!commutative || op1 != NULL);
616 if(mode_bits == 8 && !(flags & match_8_bit_am)) {
618 } else if(mode_bits == 16 && !(flags & match_16_bit_am)) {
622 new_op2 = (use_immediate ? try_create_Immediate(op2, 0) : NULL);
623 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
624 build_address(am, op2);
625 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
626 if(mode_is_float(mode)) {
627 new_op2 = ia32_new_NoReg_vfp(env_cg);
631 am->op_type = ia32_AddrModeS;
632 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
633 use_am && use_source_address_mode(block, op1, op2)) {
635 build_address(am, op1);
637 if(mode_is_float(mode)) {
638 noreg = ia32_new_NoReg_vfp(env_cg);
643 if(new_op2 != NULL) {
646 new_op1 = be_transform_node(op2);
650 am->op_type = ia32_AddrModeS;
652 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
654 new_op2 = be_transform_node(op2);
655 am->op_type = ia32_Normal;
656 if(flags & match_force_32bit_op) {
657 am->ls_mode = mode_Iu;
659 am->ls_mode = get_irn_mode(op2);
662 if(addr->base == NULL)
663 addr->base = noreg_gp;
664 if(addr->index == NULL)
665 addr->index = noreg_gp;
666 if(addr->mem == NULL)
667 addr->mem = new_NoMem();
669 am->new_op1 = new_op1;
670 am->new_op2 = new_op2;
671 am->commutative = commutative;
674 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
676 ir_graph *irg = current_ir_graph;
680 if(am->mem_proj == NULL)
683 /* we have to create a mode_T so the old MemProj can attach to us */
684 mode = get_irn_mode(node);
685 load = get_Proj_pred(am->mem_proj);
687 mark_irn_visited(load);
688 be_set_transformed_node(load, node);
691 set_irn_mode(node, mode_T);
692 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
699 * Construct a standard binary operation, set AM and immediate if required.
701 * @param op1 The first operand
702 * @param op2 The second operand
703 * @param func The node constructor function
704 * @return The constructed ia32 node.
706 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
707 construct_binop_func *func, int commutative)
709 ir_node *block = get_nodes_block(node);
710 ir_node *new_block = be_transform_node(block);
711 ir_graph *irg = current_ir_graph;
712 dbg_info *dbgi = get_irn_dbg_info(node);
714 ia32_address_mode_t am;
715 ia32_address_t *addr = &am.addr;
716 match_flags_t flags = match_force_32bit_op;
719 flags |= match_commutative;
721 match_arguments(&am, block, op1, op2, flags);
723 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
724 am.new_op1, am.new_op2);
725 set_am_attributes(new_node, &am);
726 /* we can't use source address mode anymore when using immediates */
727 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
728 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
729 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
731 new_node = fix_mem_proj(new_node, &am);
737 * Construct a standard binary operation, set AM and immediate if required.
739 * @param op1 The first operand
740 * @param op2 The second operand
741 * @param func The node constructor function
742 * @return The constructed ia32 node.
744 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
745 construct_binop_func *func,
748 ir_node *block = get_nodes_block(node);
749 ir_node *new_block = be_transform_node(block);
750 dbg_info *dbgi = get_irn_dbg_info(node);
751 ir_graph *irg = current_ir_graph;
753 ia32_address_mode_t am;
754 ia32_address_t *addr = &am.addr;
755 match_flags_t flags = 0;
758 flags |= match_commutative;
760 match_arguments(&am, block, op1, op2, flags);
762 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
763 am.new_op1, am.new_op2);
764 set_am_attributes(new_node, &am);
766 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
768 new_node = fix_mem_proj(new_node, &am);
773 static ir_node *get_fpcw(void)
776 if(initial_fpcw != NULL)
779 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
780 &ia32_fp_cw_regs[REG_FPCW]);
781 initial_fpcw = be_transform_node(fpcw);
787 * Construct a standard binary operation, set AM and immediate if required.
789 * @param op1 The first operand
790 * @param op2 The second operand
791 * @param func The node constructor function
792 * @return The constructed ia32 node.
794 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
795 construct_binop_float_func *func,
798 ir_graph *irg = current_ir_graph;
799 dbg_info *dbgi = get_irn_dbg_info(node);
800 ir_node *block = get_nodes_block(node);
801 ir_node *new_block = be_transform_node(block);
803 ia32_address_mode_t am;
804 ia32_address_t *addr = &am.addr;
805 match_flags_t flags = 0;
808 flags |= match_commutative;
810 match_arguments(&am, block, op1, op2, flags);
812 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
813 am.new_op1, am.new_op2, get_fpcw());
814 set_am_attributes(new_node, &am);
816 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
818 new_node = fix_mem_proj(new_node, &am);
824 * Construct a shift/rotate binary operation, sets AM and immediate if required.
826 * @param op1 The first operand
827 * @param op2 The second operand
828 * @param func The node constructor function
829 * @return The constructed ia32 node.
831 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
832 construct_shift_func *func)
834 dbg_info *dbgi = get_irn_dbg_info(node);
835 ir_graph *irg = current_ir_graph;
836 ir_node *block = get_nodes_block(node);
837 ir_node *new_block = be_transform_node(block);
838 ir_node *new_op1 = be_transform_node(op1);
839 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
842 assert(! mode_is_float(get_irn_mode(node))
843 && "Shift/Rotate with float not supported");
845 res = func(dbgi, irg, new_block, new_op1, new_op2);
846 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
848 /* lowered shift instruction may have a dependency operand, handle it here */
849 if (get_irn_arity(node) == 3) {
850 /* we have a dependency */
851 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
852 add_irn_dep(res, new_dep);
860 * Construct a standard unary operation, set AM and immediate if required.
862 * @param op The operand
863 * @param func The node constructor function
864 * @return The constructed ia32 node.
866 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
868 ir_node *block = be_transform_node(get_nodes_block(node));
869 ir_node *new_op = be_transform_node(op);
870 ir_node *new_node = NULL;
871 ir_graph *irg = current_ir_graph;
872 dbg_info *dbgi = get_irn_dbg_info(node);
874 new_node = func(dbgi, irg, block, new_op);
876 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
881 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
882 ia32_address_t *addr)
884 ir_graph *irg = current_ir_graph;
885 ir_node *base = addr->base;
886 ir_node *index = addr->index;
890 base = ia32_new_NoReg_gp(env_cg);
892 base = be_transform_node(base);
896 index = ia32_new_NoReg_gp(env_cg);
898 index = be_transform_node(index);
901 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
902 set_address(res, addr);
907 static int am_has_immediates(const ia32_address_t *addr)
909 return addr->offset != 0 || addr->symconst_ent != NULL
910 || addr->frame_entity || addr->use_frame;
914 * Creates an ia32 Add.
916 * @return the created ia32 Add node
918 static ir_node *gen_Add(ir_node *node) {
919 ir_graph *irg = current_ir_graph;
920 dbg_info *dbgi = get_irn_dbg_info(node);
921 ir_node *block = get_nodes_block(node);
922 ir_node *new_block = be_transform_node(block);
923 ir_node *op1 = get_Add_left(node);
924 ir_node *op2 = get_Add_right(node);
925 ir_mode *mode = get_irn_mode(node);
926 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
929 ir_node *add_immediate_op;
931 ia32_address_mode_t am;
933 if (mode_is_float(mode)) {
934 if (USE_SSE2(env_cg))
935 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd, 1);
937 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd, 1);
942 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
943 * 1. Add with immediate -> Lea
944 * 2. Add with possible source address mode -> Add
945 * 3. Otherwise -> Lea
947 memset(&addr, 0, sizeof(addr));
948 ia32_create_address_mode(&addr, node, 1);
949 add_immediate_op = NULL;
951 if(addr.base == NULL && addr.index == NULL) {
952 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
953 addr.symconst_sign, addr.offset);
954 add_irn_dep(new_node, get_irg_frame(irg));
955 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
958 /* add with immediate? */
959 if(addr.index == NULL) {
960 add_immediate_op = addr.base;
961 } else if(addr.base == NULL && addr.scale == 0) {
962 add_immediate_op = addr.index;
965 if(add_immediate_op != NULL) {
966 if(!am_has_immediates(&addr)) {
968 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
971 return be_transform_node(add_immediate_op);
974 new_node = create_lea_from_address(dbgi, new_block, &addr);
975 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
979 /* test if we can use source address mode */
980 memset(&am, 0, sizeof(am));
982 if(use_source_address_mode(block, op2, op1)) {
983 build_address(&am, op2);
984 new_op1 = be_transform_node(op1);
985 } else if(use_source_address_mode(block, op1, op2)) {
986 build_address(&am, op1);
987 new_op1 = be_transform_node(op2);
989 /* construct an Add with source address mode */
990 if(new_op1 != NULL) {
991 ia32_address_t *am_addr = &am.addr;
992 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
993 am_addr->index, am_addr->mem, new_op1, noreg);
994 set_address(new_node, am_addr);
995 set_ia32_op_type(new_node, ia32_AddrModeS);
996 set_ia32_ls_mode(new_node, am.ls_mode);
997 set_ia32_commutative(new_node);
998 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1000 new_node = fix_mem_proj(new_node, &am);
1005 /* otherwise construct a lea */
1006 new_node = create_lea_from_address(dbgi, new_block, &addr);
1007 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1012 * Creates an ia32 Mul.
1014 * @return the created ia32 Mul node
1016 static ir_node *gen_Mul(ir_node *node) {
1017 ir_node *op1 = get_Mul_left(node);
1018 ir_node *op2 = get_Mul_right(node);
1019 ir_mode *mode = get_irn_mode(node);
1021 if (mode_is_float(mode)) {
1022 if (USE_SSE2(env_cg))
1023 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul, 1);
1025 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul, 1);
1029 for the lower 32bit of the result it doesn't matter whether we use
1030 signed or unsigned multiplication so we use IMul as it has fewer
1033 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
1037 * Creates an ia32 Mulh.
1038 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1039 * this result while Mul returns the lower 32 bit.
1041 * @return the created ia32 Mulh node
1043 static ir_node *gen_Mulh(ir_node *node) {
1044 ir_node *block = be_transform_node(get_nodes_block(node));
1045 ir_node *op1 = get_irn_n(node, 0);
1046 ir_node *new_op1 = be_transform_node(op1);
1047 ir_node *op2 = get_irn_n(node, 1);
1048 ir_node *new_op2 = be_transform_node(op2);
1049 ir_graph *irg = current_ir_graph;
1050 dbg_info *dbgi = get_irn_dbg_info(node);
1051 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1052 ir_mode *mode = get_irn_mode(node);
1053 ir_node *proj_EDX, *res;
1055 assert(!mode_is_float(mode) && "Mulh with float not supported");
1056 if (mode_is_signed(mode)) {
1057 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_NoMem(),
1060 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(), new_op1,
1064 set_ia32_commutative(res);
1066 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_IMul1OP_EDX);
1074 * Creates an ia32 And.
1076 * @return The created ia32 And node
1078 static ir_node *gen_And(ir_node *node) {
1079 ir_node *op1 = get_And_left(node);
1080 ir_node *op2 = get_And_right(node);
1081 assert(! mode_is_float(get_irn_mode(node)));
1083 /* is it a zero extension? */
1084 if (is_Const(op2)) {
1085 tarval *tv = get_Const_tarval(op2);
1086 long v = get_tarval_long(tv);
1088 if (v == 0xFF || v == 0xFFFF) {
1089 dbg_info *dbgi = get_irn_dbg_info(node);
1090 ir_node *block = get_nodes_block(node);
1097 assert(v == 0xFFFF);
1100 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1106 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
1112 * Creates an ia32 Or.
1114 * @return The created ia32 Or node
1116 static ir_node *gen_Or(ir_node *node) {
1117 ir_node *op1 = get_Or_left(node);
1118 ir_node *op2 = get_Or_right(node);
1120 assert (! mode_is_float(get_irn_mode(node)));
1121 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
1127 * Creates an ia32 Eor.
1129 * @return The created ia32 Eor node
1131 static ir_node *gen_Eor(ir_node *node) {
1132 ir_node *op1 = get_Eor_left(node);
1133 ir_node *op2 = get_Eor_right(node);
1135 assert(! mode_is_float(get_irn_mode(node)));
1136 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
1141 * Creates an ia32 Sub.
1143 * @return The created ia32 Sub node
1145 static ir_node *gen_Sub(ir_node *node) {
1146 ir_node *op1 = get_Sub_left(node);
1147 ir_node *op2 = get_Sub_right(node);
1148 ir_mode *mode = get_irn_mode(node);
1150 if (mode_is_float(mode)) {
1151 if (USE_SSE2(env_cg))
1152 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub, 0);
1154 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub, 0);
1158 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1162 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1165 typedef enum { flavour_Div = 1, flavour_Mod, flavour_DivMod } ia32_op_flavour_t;
1168 * Generates an ia32 DivMod with additional infrastructure for the
1169 * register allocator if needed.
1171 * @param dividend -no comment- :)
1172 * @param divisor -no comment- :)
1173 * @param dm_flav flavour_Div/Mod/DivMod
1174 * @return The created ia32 DivMod node
1176 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1177 ir_node *divisor, ia32_op_flavour_t dm_flav)
1179 ir_node *block = be_transform_node(get_nodes_block(node));
1180 ir_node *new_dividend = be_transform_node(dividend);
1181 ir_node *new_divisor = be_transform_node(divisor);
1182 ir_graph *irg = current_ir_graph;
1183 dbg_info *dbgi = get_irn_dbg_info(node);
1184 ir_mode *mode = get_irn_mode(node);
1185 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1186 ir_node *res, *proj_div, *proj_mod;
1187 ir_node *sign_extension;
1188 ir_node *mem, *new_mem;
1191 proj_div = proj_mod = NULL;
1195 mem = get_Div_mem(node);
1196 mode = get_Div_resmode(node);
1197 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1198 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1201 mem = get_Mod_mem(node);
1202 mode = get_Mod_resmode(node);
1203 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1204 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1206 case flavour_DivMod:
1207 mem = get_DivMod_mem(node);
1208 mode = get_DivMod_resmode(node);
1209 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1210 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1211 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1214 panic("invalid divmod flavour!");
1216 new_mem = be_transform_node(mem);
1218 if (mode_is_signed(mode)) {
1219 /* in signed mode, we need to sign extend the dividend */
1220 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1221 add_irn_dep(produceval, get_irg_frame(irg));
1222 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1225 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1226 set_ia32_flags(sign_extension, get_ia32_flags(sign_extension) | arch_irn_flags_modify_flags);
1227 add_irn_dep(sign_extension, get_irg_frame(irg));
1230 if (mode_is_signed(mode)) {
1231 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
1232 new_dividend, sign_extension, new_divisor);
1234 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem,
1235 new_dividend, sign_extension, new_divisor);
1238 set_ia32_exc_label(res, has_exc);
1239 set_irn_pinned(res, get_irn_pinned(node));
1241 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1248 * Wrapper for generate_DivMod. Sets flavour_Mod.
1251 static ir_node *gen_Mod(ir_node *node) {
1252 return generate_DivMod(node, get_Mod_left(node),
1253 get_Mod_right(node), flavour_Mod);
1257 * Wrapper for generate_DivMod. Sets flavour_Div.
1260 static ir_node *gen_Div(ir_node *node) {
1261 return generate_DivMod(node, get_Div_left(node),
1262 get_Div_right(node), flavour_Div);
1266 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1268 static ir_node *gen_DivMod(ir_node *node) {
1269 return generate_DivMod(node, get_DivMod_left(node),
1270 get_DivMod_right(node), flavour_DivMod);
1276 * Creates an ia32 floating Div.
1278 * @return The created ia32 xDiv node
1280 static ir_node *gen_Quot(ir_node *node)
1282 ir_node *op1 = get_Quot_left(node);
1283 ir_node *op2 = get_Quot_right(node);
1285 if (USE_SSE2(env_cg)) {
1286 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xDiv, 0);
1288 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, 0);
1294 * Creates an ia32 Shl.
1296 * @return The created ia32 Shl node
1298 static ir_node *gen_Shl(ir_node *node) {
1299 ir_node *right = get_Shl_right(node);
1301 /* test whether we can build a lea */
1302 if(is_Const(right)) {
1303 tarval *tv = get_Const_tarval(right);
1304 if(tarval_is_long(tv)) {
1305 long val = get_tarval_long(tv);
1306 if(val >= 0 && val <= 3) {
1307 ir_graph *irg = current_ir_graph;
1308 dbg_info *dbgi = get_irn_dbg_info(node);
1309 ir_node *block = be_transform_node(get_nodes_block(node));
1310 ir_node *base = ia32_new_NoReg_gp(env_cg);
1311 ir_node *index = be_transform_node(get_Shl_left(node));
1312 ir_node *res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1313 set_ia32_am_scale(res, val);
1314 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1320 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1327 * Creates an ia32 Shr.
1329 * @return The created ia32 Shr node
1331 static ir_node *gen_Shr(ir_node *node) {
1332 return gen_shift_binop(node, get_Shr_left(node),
1333 get_Shr_right(node), new_rd_ia32_Shr);
1339 * Creates an ia32 Sar.
1341 * @return The created ia32 Shrs node
1343 static ir_node *gen_Shrs(ir_node *node) {
1344 ir_node *left = get_Shrs_left(node);
1345 ir_node *right = get_Shrs_right(node);
1346 ir_mode *mode = get_irn_mode(node);
1347 if(is_Const(right) && mode == mode_Is) {
1348 tarval *tv = get_Const_tarval(right);
1349 long val = get_tarval_long(tv);
1351 /* this is a sign extension */
1352 ir_graph *irg = current_ir_graph;
1353 dbg_info *dbgi = get_irn_dbg_info(node);
1354 ir_node *block = be_transform_node(get_nodes_block(node));
1356 ir_node *new_op = be_transform_node(op);
1357 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1358 add_irn_dep(pval, get_irg_frame(irg));
1360 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1364 /* 8 or 16 bit sign extension? */
1365 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1366 ir_node *shl_left = get_Shl_left(left);
1367 ir_node *shl_right = get_Shl_right(left);
1368 if(is_Const(shl_right)) {
1369 tarval *tv1 = get_Const_tarval(right);
1370 tarval *tv2 = get_Const_tarval(shl_right);
1371 if(tv1 == tv2 && tarval_is_long(tv1)) {
1372 long val = get_tarval_long(tv1);
1373 if(val == 16 || val == 24) {
1374 dbg_info *dbgi = get_irn_dbg_info(node);
1375 ir_node *block = get_nodes_block(node);
1385 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1394 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1400 * Creates an ia32 RotL.
1402 * @param op1 The first operator
1403 * @param op2 The second operator
1404 * @return The created ia32 RotL node
1406 static ir_node *gen_RotL(ir_node *node,
1407 ir_node *op1, ir_node *op2) {
1408 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1414 * Creates an ia32 RotR.
1415 * NOTE: There is no RotR with immediate because this would always be a RotL
1416 * "imm-mode_size_bits" which can be pre-calculated.
1418 * @param op1 The first operator
1419 * @param op2 The second operator
1420 * @return The created ia32 RotR node
1422 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1424 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1430 * Creates an ia32 RotR or RotL (depending on the found pattern).
1432 * @return The created ia32 RotL or RotR node
1434 static ir_node *gen_Rot(ir_node *node) {
1435 ir_node *rotate = NULL;
1436 ir_node *op1 = get_Rot_left(node);
1437 ir_node *op2 = get_Rot_right(node);
1439 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1440 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1441 that means we can create a RotR instead of an Add and a RotL */
1443 if (get_irn_op(op2) == op_Add) {
1445 ir_node *left = get_Add_left(add);
1446 ir_node *right = get_Add_right(add);
1447 if (is_Const(right)) {
1448 tarval *tv = get_Const_tarval(right);
1449 ir_mode *mode = get_irn_mode(node);
1450 long bits = get_mode_size_bits(mode);
1452 if (get_irn_op(left) == op_Minus &&
1453 tarval_is_long(tv) &&
1454 get_tarval_long(tv) == bits)
1456 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1457 rotate = gen_RotR(node, op1, get_Minus_op(left));
1462 if (rotate == NULL) {
1463 rotate = gen_RotL(node, op1, op2);
1472 * Transforms a Minus node.
1474 * @return The created ia32 Minus node
1476 static ir_node *gen_Minus(ir_node *node)
1478 ir_node *op = get_Minus_op(node);
1479 ir_node *block = be_transform_node(get_nodes_block(node));
1480 ir_graph *irg = current_ir_graph;
1481 dbg_info *dbgi = get_irn_dbg_info(node);
1482 ir_mode *mode = get_irn_mode(node);
1487 if (mode_is_float(mode)) {
1488 ir_node *new_op = be_transform_node(op);
1489 if (USE_SSE2(env_cg)) {
1490 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1491 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1492 ir_node *nomem = new_rd_NoMem(irg);
1494 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1497 size = get_mode_size_bits(mode);
1498 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1500 set_ia32_am_sc(res, ent);
1501 set_ia32_op_type(res, ia32_AddrModeS);
1502 set_ia32_ls_mode(res, mode);
1504 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1507 res = gen_unop(node, op, new_rd_ia32_Neg);
1510 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1516 * Transforms a Not node.
1518 * @return The created ia32 Not node
1520 static ir_node *gen_Not(ir_node *node) {
1521 ir_node *op = get_Not_op(node);
1522 ir_mode *mode = get_irn_mode(node);
1524 assert(mode != mode_b); /* should be lowered already */
1526 assert (! mode_is_float(get_irn_mode(node)));
1527 return gen_unop(node, op, new_rd_ia32_Not);
1533 * Transforms an Abs node.
1535 * @return The created ia32 Abs node
1537 static ir_node *gen_Abs(ir_node *node)
1539 ir_node *block = be_transform_node(get_nodes_block(node));
1540 ir_node *op = get_Abs_op(node);
1541 ir_node *new_op = be_transform_node(op);
1542 ir_graph *irg = current_ir_graph;
1543 dbg_info *dbgi = get_irn_dbg_info(node);
1544 ir_mode *mode = get_irn_mode(node);
1545 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1546 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1547 ir_node *nomem = new_NoMem();
1552 if (mode_is_float(mode)) {
1553 if (USE_SSE2(env_cg)) {
1554 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
1556 size = get_mode_size_bits(mode);
1557 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1559 set_ia32_am_sc(res, ent);
1561 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1563 set_ia32_op_type(res, ia32_AddrModeS);
1564 set_ia32_ls_mode(res, mode);
1566 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1567 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1571 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1572 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1575 add_irn_dep(pval, get_irg_frame(irg));
1576 SET_IA32_ORIG_NODE(sign_extension,
1577 ia32_get_old_node_name(env_cg, node));
1579 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
1581 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1583 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
1585 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1592 * Transforms a Load.
1594 * @return the created ia32 Load node
1596 static ir_node *gen_Load(ir_node *node) {
1597 ir_node *old_block = get_nodes_block(node);
1598 ir_node *block = be_transform_node(old_block);
1599 ir_node *ptr = get_Load_ptr(node);
1600 ir_node *mem = get_Load_mem(node);
1601 ir_node *new_mem = be_transform_node(mem);
1604 ir_graph *irg = current_ir_graph;
1605 dbg_info *dbgi = get_irn_dbg_info(node);
1606 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1607 ir_mode *mode = get_Load_mode(node);
1610 ia32_address_t addr;
1612 /* construct load address */
1613 memset(&addr, 0, sizeof(addr));
1614 ia32_create_address_mode(&addr, ptr, 0);
1621 base = be_transform_node(base);
1627 index = be_transform_node(index);
1630 if (mode_is_float(mode)) {
1631 if (USE_SSE2(env_cg)) {
1632 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1634 res_mode = mode_xmm;
1636 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1638 res_mode = mode_vfp;
1644 /* create a conv node with address mode for smaller modes */
1645 if(get_mode_size_bits(mode) < 32) {
1646 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1647 new_mem, noreg, mode);
1649 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1654 set_irn_pinned(new_op, get_irn_pinned(node));
1655 set_ia32_op_type(new_op, ia32_AddrModeS);
1656 set_ia32_ls_mode(new_op, mode);
1657 set_address(new_op, &addr);
1659 /* make sure we are scheduled behind the initial IncSP/Barrier
1660 * to avoid spills being placed before it
1662 if (block == get_irg_start_block(irg)) {
1663 add_irn_dep(new_op, get_irg_frame(irg));
1666 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1667 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1672 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1673 ir_node *ptr, ir_mode *mode, ir_node *other)
1680 /* we only use address mode if we're the only user of the load */
1681 if(get_irn_n_edges(node) > 1)
1684 load = get_Proj_pred(node);
1687 if(get_nodes_block(load) != block)
1690 /* Store should be attached to the load */
1691 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1693 /* store should have the same pointer as the load */
1694 if(get_Load_ptr(load) != ptr)
1697 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1698 if(other != NULL && get_nodes_block(other) == block
1699 && heights_reachable_in_block(heights, other, load))
1702 assert(get_Load_mode(load) == mode);
1707 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1708 ir_node *mem, ir_node *ptr, ir_mode *mode,
1709 construct_binop_dest_func *func,
1710 construct_binop_dest_func *func8bit,
1713 ir_node *src_block = get_nodes_block(node);
1715 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1716 ir_graph *irg = current_ir_graph;
1720 ia32_address_mode_t am;
1721 ia32_address_t *addr = &am.addr;
1722 memset(&am, 0, sizeof(am));
1724 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1725 build_address(&am, op1);
1726 new_op = create_immediate_or_transform(op2, 0);
1727 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1728 build_address(&am, op2);
1729 new_op = create_immediate_or_transform(op1, 0);
1734 if(addr->base == NULL)
1735 addr->base = noreg_gp;
1736 if(addr->index == NULL)
1737 addr->index = noreg_gp;
1738 if(addr->mem == NULL)
1739 addr->mem = new_NoMem();
1741 dbgi = get_irn_dbg_info(node);
1742 block = be_transform_node(src_block);
1743 if(get_mode_size_bits(mode) == 8) {
1744 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1747 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1750 set_address(new_node, addr);
1751 set_ia32_op_type(new_node, ia32_AddrModeD);
1752 set_ia32_ls_mode(new_node, mode);
1753 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1758 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1759 ir_node *ptr, ir_mode *mode,
1760 construct_unop_dest_func *func)
1762 ir_node *src_block = get_nodes_block(node);
1764 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1765 ir_graph *irg = current_ir_graph;
1768 ia32_address_mode_t am;
1769 ia32_address_t *addr = &am.addr;
1770 memset(&am, 0, sizeof(am));
1772 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1775 build_address(&am, op);
1777 if(addr->base == NULL)
1778 addr->base = noreg_gp;
1779 if(addr->index == NULL)
1780 addr->index = noreg_gp;
1781 if(addr->mem == NULL)
1782 addr->mem = new_NoMem();
1784 dbgi = get_irn_dbg_info(node);
1785 block = be_transform_node(src_block);
1786 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1787 set_address(new_node, addr);
1788 set_ia32_op_type(new_node, ia32_AddrModeD);
1789 set_ia32_ls_mode(new_node, mode);
1790 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1795 static ir_node *try_create_dest_am(ir_node *node) {
1796 ir_node *val = get_Store_value(node);
1797 ir_node *mem = get_Store_mem(node);
1798 ir_node *ptr = get_Store_ptr(node);
1799 ir_mode *mode = get_irn_mode(val);
1804 /* handle only GP modes for now... */
1805 if(!mode_needs_gp_reg(mode))
1808 /* store must be the only user of the val node */
1809 if(get_irn_n_edges(val) > 1)
1812 switch(get_irn_opcode(val)) {
1814 op1 = get_Add_left(val);
1815 op2 = get_Add_right(val);
1816 if(is_Const_1(op2)) {
1817 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1818 new_rd_ia32_IncMem);
1820 } else if(is_Const_Minus_1(op2)) {
1821 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1822 new_rd_ia32_DecMem);
1825 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1826 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, 1);
1829 op1 = get_Sub_left(val);
1830 op2 = get_Sub_right(val);
1832 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
1835 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1836 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, 0);
1839 op1 = get_And_left(val);
1840 op2 = get_And_right(val);
1841 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1842 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, 1);
1845 op1 = get_Or_left(val);
1846 op2 = get_Or_right(val);
1847 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1848 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, 1);
1851 op1 = get_Eor_left(val);
1852 op2 = get_Eor_right(val);
1853 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1854 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, 1);
1857 op1 = get_Shl_left(val);
1858 op2 = get_Shl_right(val);
1859 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1860 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, 0);
1863 op1 = get_Shr_left(val);
1864 op2 = get_Shr_right(val);
1865 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1866 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, 0);
1869 op1 = get_Shrs_left(val);
1870 op2 = get_Shrs_right(val);
1871 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1872 new_rd_ia32_SarMem, new_rd_ia32_SarMem, 0);
1875 op1 = get_Rot_left(val);
1876 op2 = get_Rot_right(val);
1877 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1878 new_rd_ia32_RolMem, new_rd_ia32_RolMem, 0);
1880 /* TODO: match ROR patterns... */
1882 op1 = get_Minus_op(val);
1883 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1886 /* should be lowered already */
1887 assert(mode != mode_b);
1888 op1 = get_Not_op(val);
1889 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1899 * Transforms a Store.
1901 * @return the created ia32 Store node
1903 static ir_node *gen_Store(ir_node *node) {
1904 ir_node *block = be_transform_node(get_nodes_block(node));
1905 ir_node *ptr = get_Store_ptr(node);
1908 ir_node *val = get_Store_value(node);
1910 ir_node *mem = get_Store_mem(node);
1911 ir_node *new_mem = be_transform_node(mem);
1912 ir_graph *irg = current_ir_graph;
1913 dbg_info *dbgi = get_irn_dbg_info(node);
1914 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1915 ir_mode *mode = get_irn_mode(val);
1917 ia32_address_t addr;
1919 /* check for destination address mode */
1920 new_op = try_create_dest_am(node);
1924 /* construct store address */
1925 memset(&addr, 0, sizeof(addr));
1926 ia32_create_address_mode(&addr, ptr, 0);
1933 base = be_transform_node(base);
1939 index = be_transform_node(index);
1942 if (mode_is_float(mode)) {
1943 new_val = be_transform_node(val);
1944 if (USE_SSE2(env_cg)) {
1945 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
1948 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
1952 new_val = create_immediate_or_transform(val, 0);
1956 if (get_mode_size_bits(mode) == 8) {
1957 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
1960 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
1965 set_irn_pinned(new_op, get_irn_pinned(node));
1966 set_ia32_op_type(new_op, ia32_AddrModeD);
1967 set_ia32_ls_mode(new_op, mode);
1969 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1970 set_address(new_op, &addr);
1971 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1976 static ir_node *create_Switch(ir_node *node)
1978 ir_graph *irg = current_ir_graph;
1979 dbg_info *dbgi = get_irn_dbg_info(node);
1980 ir_node *block = be_transform_node(get_nodes_block(node));
1981 ir_node *sel = get_Cond_selector(node);
1982 ir_node *new_sel = be_transform_node(sel);
1984 int switch_min = INT_MAX;
1985 const ir_edge_t *edge;
1987 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1989 /* determine the smallest switch case value */
1990 foreach_out_edge(node, edge) {
1991 ir_node *proj = get_edge_src_irn(edge);
1992 int pn = get_Proj_proj(proj);
1997 if (switch_min != 0) {
1998 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2000 /* if smallest switch case is not 0 we need an additional sub */
2001 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2002 add_ia32_am_offs_int(new_sel, -switch_min);
2003 set_ia32_op_type(new_sel, ia32_AddrModeS);
2005 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2008 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
2009 set_ia32_pncode(res, get_Cond_defaultProj(node));
2011 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2016 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
2018 ir_graph *irg = current_ir_graph;
2026 /* we have a Cmp as input */
2028 ir_node *pred = get_Proj_pred(node);
2030 flags = be_transform_node(pred);
2031 *pnc_out = get_Proj_proj(node);
2036 /* a mode_b value, we have to compare it against 0 */
2037 dbgi = get_irn_dbg_info(node);
2038 new_block = be_transform_node(get_nodes_block(node));
2039 new_op = be_transform_node(node);
2040 noreg = ia32_new_NoReg_gp(env_cg);
2041 nomem = new_NoMem();
2042 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
2043 new_op, new_op, 0, 0);
2044 *pnc_out = pn_Cmp_Lg;
2048 static ir_node *gen_Cond(ir_node *node) {
2049 ir_node *block = get_nodes_block(node);
2050 ir_node *new_block = be_transform_node(block);
2051 ir_graph *irg = current_ir_graph;
2052 dbg_info *dbgi = get_irn_dbg_info(node);
2053 ir_node *sel = get_Cond_selector(node);
2054 ir_mode *sel_mode = get_irn_mode(sel);
2056 ir_node *flags = NULL;
2059 if (sel_mode != mode_b) {
2060 return create_Switch(node);
2063 /* we get flags from a cmp */
2064 flags = get_flags_node(sel, &pnc);
2066 res = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2067 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2075 * Transforms a CopyB node.
2077 * @return The transformed node.
2079 static ir_node *gen_CopyB(ir_node *node) {
2080 ir_node *block = be_transform_node(get_nodes_block(node));
2081 ir_node *src = get_CopyB_src(node);
2082 ir_node *new_src = be_transform_node(src);
2083 ir_node *dst = get_CopyB_dst(node);
2084 ir_node *new_dst = be_transform_node(dst);
2085 ir_node *mem = get_CopyB_mem(node);
2086 ir_node *new_mem = be_transform_node(mem);
2087 ir_node *res = NULL;
2088 ir_graph *irg = current_ir_graph;
2089 dbg_info *dbgi = get_irn_dbg_info(node);
2090 int size = get_type_size_bytes(get_CopyB_type(node));
2093 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2094 /* then we need the size explicitly in ECX. */
2095 if (size >= 32 * 4) {
2096 rem = size & 0x3; /* size % 4 */
2099 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2101 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2103 set_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);
2105 add_irn_dep(res, get_irg_frame(irg));
2107 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2108 /* we misuse the pncode field for the copyb size */
2109 set_ia32_pncode(res, rem);
2111 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2112 set_ia32_pncode(res, size);
2115 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2120 static ir_node *gen_be_Copy(ir_node *node)
2122 ir_node *result = be_duplicate_node(node);
2123 ir_mode *mode = get_irn_mode(result);
2125 if (mode_needs_gp_reg(mode)) {
2126 set_irn_mode(result, mode_Iu);
2133 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2134 * to fold an and into a test node
2136 static int can_fold_test_and(ir_node *node)
2138 const ir_edge_t *edge;
2140 /** we can only have eq and lg projs */
2141 foreach_out_edge(node, edge) {
2142 ir_node *proj = get_edge_src_irn(edge);
2143 pn_Cmp pnc = get_Proj_proj(proj);
2144 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2151 static ir_node *try_create_Test(ir_node *node)
2153 ir_graph *irg = current_ir_graph;
2154 dbg_info *dbgi = get_irn_dbg_info(node);
2155 ir_node *block = get_nodes_block(node);
2156 ir_node *new_block = be_transform_node(block);
2157 ir_node *cmp_left = get_Cmp_left(node);
2158 ir_node *cmp_right = get_Cmp_right(node);
2163 ia32_address_mode_t am;
2164 ia32_address_t *addr = &am.addr;
2167 /* can we use a test instruction? */
2168 if(!is_Const_0(cmp_right))
2171 if(is_And(cmp_left) && get_irn_n_edges(cmp_left) == 1 &&
2172 can_fold_test_and(node)) {
2173 ir_node *and_left = get_And_left(cmp_left);
2174 ir_node *and_right = get_And_right(cmp_left);
2176 mode = get_irn_mode(and_left);
2180 mode = get_irn_mode(cmp_left);
2185 assert(get_mode_size_bits(mode) <= 32);
2187 match_arguments(&am, block, left, right, match_commutative |
2188 match_8_bit_am | match_16_bit_am | match_am_and_immediates);
2190 cmp_unsigned = !mode_is_signed(mode);
2191 if(get_mode_size_bits(mode) == 8) {
2192 res = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2193 addr->index, addr->mem, am.new_op1,
2194 am.new_op2, am.flipped, cmp_unsigned);
2196 res = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, addr->index,
2197 addr->mem, am.new_op1, am.new_op2, am.flipped,
2200 set_am_attributes(res, &am);
2201 assert(mode != NULL);
2202 set_ia32_ls_mode(res, mode);
2204 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2206 res = fix_mem_proj(res, &am);
2210 static ir_node *create_Fucom(ir_node *node)
2212 ir_graph *irg = current_ir_graph;
2213 dbg_info *dbgi = get_irn_dbg_info(node);
2214 ir_node *block = get_nodes_block(node);
2215 ir_node *new_block = be_transform_node(block);
2216 ir_node *left = get_Cmp_left(node);
2217 ir_node *new_left = be_transform_node(left);
2218 ir_node *right = get_Cmp_right(node);
2222 if(transform_config.use_fucomi) {
2223 new_right = be_transform_node(right);
2224 res = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left, new_right, 0);
2225 set_ia32_commutative(res);
2226 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2228 if(transform_config.use_ftst && is_Const_null(right)) {
2229 res = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left, 0);
2231 new_right = be_transform_node(right);
2232 res = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2236 set_ia32_commutative(res);
2238 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2240 res = new_rd_ia32_Sahf(dbgi, irg, new_block, res);
2241 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2247 static ir_node *create_Ucomi(ir_node *node)
2249 ir_graph *irg = current_ir_graph;
2250 dbg_info *dbgi = get_irn_dbg_info(node);
2251 ir_node *src_block = get_nodes_block(node);
2252 ir_node *new_block = be_transform_node(src_block);
2253 ir_node *left = get_Cmp_left(node);
2254 ir_node *right = get_Cmp_right(node);
2256 ia32_address_mode_t am;
2257 ia32_address_t *addr = &am.addr;
2259 match_arguments(&am, src_block, left, right, match_commutative);
2261 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2262 addr->mem, am.new_op1, am.new_op2, am.flipped);
2263 set_am_attributes(new_node, &am);
2265 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2267 new_node = fix_mem_proj(new_node, &am);
2272 static ir_node *gen_Cmp(ir_node *node)
2274 ir_graph *irg = current_ir_graph;
2275 dbg_info *dbgi = get_irn_dbg_info(node);
2276 ir_node *block = get_nodes_block(node);
2277 ir_node *new_block = be_transform_node(block);
2278 ir_node *left = get_Cmp_left(node);
2279 ir_node *right = get_Cmp_right(node);
2280 ir_mode *cmp_mode = get_irn_mode(left);
2282 ia32_address_mode_t am;
2283 ia32_address_t *addr = &am.addr;
2286 if(mode_is_float(cmp_mode)) {
2287 if (USE_SSE2(env_cg)) {
2288 return create_Ucomi(node);
2290 return create_Fucom(node);
2294 assert(mode_needs_gp_reg(cmp_mode));
2296 /* we prefer the Test instruction where possible except cases where
2297 * we can use SourceAM */
2298 if(!use_source_address_mode(block, left, right) &&
2299 !use_source_address_mode(block, right, left)) {
2300 res = try_create_Test(node);
2305 match_arguments(&am, block, left, right,
2306 match_commutative | match_8_bit_am | match_16_bit_am |
2307 match_am_and_immediates);
2309 cmp_unsigned = !mode_is_signed(get_irn_mode(left));
2310 if(get_mode_size_bits(cmp_mode) == 8) {
2311 res = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, addr->index,
2312 addr->mem, am.new_op1, am.new_op2,
2313 am.flipped, cmp_unsigned);
2315 res = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, addr->index,
2316 addr->mem, am.new_op1, am.new_op2, am.flipped,
2319 set_am_attributes(res, &am);
2320 assert(cmp_mode != NULL);
2321 set_ia32_ls_mode(res, cmp_mode);
2323 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2325 res = fix_mem_proj(res, &am);
2330 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2332 ir_graph *irg = current_ir_graph;
2333 dbg_info *dbgi = get_irn_dbg_info(node);
2334 ir_node *block = get_nodes_block(node);
2335 ir_node *new_block = be_transform_node(block);
2336 ir_node *val_true = get_Psi_val(node, 0);
2337 ir_node *val_false = get_Psi_default(node);
2339 match_flags_t match_flags;
2341 assert(transform_config.use_cmov);
2343 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2345 ia32_address_mode_t am;
2346 ia32_address_t *addr = &am.addr;
2348 match_flags = match_commutative | match_no_immediate | match_16_bit_am
2349 | match_force_32bit_op;
2351 match_arguments(&am, block, val_false, val_true, match_flags);
2353 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2354 addr->mem, am.new_op1, am.new_op2, new_flags,
2356 set_am_attributes(new_node, &am);
2358 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2360 new_node = fix_mem_proj(new_node, &am);
2367 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2368 ir_node *flags, pn_Cmp pnc, ir_node *orig_node)
2370 ir_graph *irg = current_ir_graph;
2371 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2372 ir_node *nomem = new_NoMem();
2375 res = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc);
2376 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2377 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2378 nomem, res, mode_Bu);
2379 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2385 * Transforms a Psi node into CMov.
2387 * @return The transformed node.
2389 static ir_node *gen_Psi(ir_node *node)
2391 dbg_info *dbgi = get_irn_dbg_info(node);
2392 ir_node *block = get_nodes_block(node);
2393 ir_node *new_block = be_transform_node(block);
2394 ir_node *psi_true = get_Psi_val(node, 0);
2395 ir_node *psi_default = get_Psi_default(node);
2396 ir_node *cond = get_Psi_cond(node, 0);
2397 ir_node *flags = NULL;
2402 assert(get_Psi_n_conds(node) == 1);
2403 assert(get_irn_mode(cond) == mode_b);
2404 assert(mode_needs_gp_reg(get_irn_mode(node)));
2406 flags = get_flags_node(cond, &pnc);
2408 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2409 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2410 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2411 pnc = get_negated_pnc(pnc, cmp_mode);
2412 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2414 res = create_CMov(node, flags, pnc);
2421 * Create a conversion from x87 state register to general purpose.
2423 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2424 ir_node *block = be_transform_node(get_nodes_block(node));
2425 ir_node *op = get_Conv_op(node);
2426 ir_node *new_op = be_transform_node(op);
2427 ia32_code_gen_t *cg = env_cg;
2428 ir_graph *irg = current_ir_graph;
2429 dbg_info *dbgi = get_irn_dbg_info(node);
2430 ir_node *noreg = ia32_new_NoReg_gp(cg);
2431 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2432 ir_mode *mode = get_irn_mode(node);
2433 ir_node *fist, *load;
2436 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2437 new_NoMem(), new_op, trunc_mode);
2439 set_irn_pinned(fist, op_pin_state_floats);
2440 set_ia32_use_frame(fist);
2441 set_ia32_op_type(fist, ia32_AddrModeD);
2443 assert(get_mode_size_bits(mode) <= 32);
2444 /* exception we can only store signed 32 bit integers, so for unsigned
2445 we store a 64bit (signed) integer and load the lower bits */
2446 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2447 set_ia32_ls_mode(fist, mode_Ls);
2449 set_ia32_ls_mode(fist, mode_Is);
2451 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2454 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2456 set_irn_pinned(load, op_pin_state_floats);
2457 set_ia32_use_frame(load);
2458 set_ia32_op_type(load, ia32_AddrModeS);
2459 set_ia32_ls_mode(load, mode_Is);
2460 if(get_ia32_ls_mode(fist) == mode_Ls) {
2461 ia32_attr_t *attr = get_ia32_attr(load);
2462 attr->data.need_64bit_stackent = 1;
2464 ia32_attr_t *attr = get_ia32_attr(load);
2465 attr->data.need_32bit_stackent = 1;
2467 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2469 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2473 * Creates a x87 strict Conv by placing a Sore and a Load
2475 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2477 ir_node *block = get_nodes_block(node);
2478 ir_graph *irg = current_ir_graph;
2479 dbg_info *dbgi = get_irn_dbg_info(node);
2480 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2481 ir_node *nomem = new_NoMem();
2482 ir_node *frame = get_irg_frame(irg);
2483 ir_node *store, *load;
2486 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2488 set_ia32_use_frame(store);
2489 set_ia32_op_type(store, ia32_AddrModeD);
2490 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2492 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2494 set_ia32_use_frame(load);
2495 set_ia32_op_type(load, ia32_AddrModeS);
2496 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2498 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2502 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2504 ir_graph *irg = current_ir_graph;
2505 ir_node *start_block = get_irg_start_block(irg);
2506 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2507 symconst, symconst_sign, val);
2508 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2514 * Create a conversion from general purpose to x87 register
2516 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2517 ir_node *src_block = get_nodes_block(node);
2518 ir_node *block = be_transform_node(src_block);
2519 ir_graph *irg = current_ir_graph;
2520 dbg_info *dbgi = get_irn_dbg_info(node);
2521 ir_node *op = get_Conv_op(node);
2526 ir_mode *store_mode;
2532 /* fild can use source AM if the operand is a signed 32bit integer */
2533 if (src_mode == mode_Is) {
2534 ia32_address_mode_t am;
2536 match_arguments(&am, src_block, NULL, op, match_no_immediate);
2537 if (am.op_type == ia32_AddrModeS) {
2538 ia32_address_t *addr = &am.addr;
2540 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base, addr->index, addr->mem);
2541 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2543 set_am_attributes(fild, &am);
2544 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2546 fix_mem_proj(fild, &am);
2550 new_op = am.new_op2;
2552 new_op = be_transform_node(op);
2555 noreg = ia32_new_NoReg_gp(env_cg);
2556 nomem = new_NoMem();
2557 mode = get_irn_mode(op);
2559 /* first convert to 32 bit signed if necessary */
2560 src_bits = get_mode_size_bits(src_mode);
2561 if (src_bits == 8) {
2562 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2564 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2566 } else if (src_bits < 32) {
2567 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2569 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2573 assert(get_mode_size_bits(mode) == 32);
2576 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2579 set_ia32_use_frame(store);
2580 set_ia32_op_type(store, ia32_AddrModeD);
2581 set_ia32_ls_mode(store, mode_Iu);
2583 /* exception for 32bit unsigned, do a 64bit spill+load */
2584 if(!mode_is_signed(mode)) {
2587 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2589 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2590 get_irg_frame(irg), noreg, nomem,
2593 set_ia32_use_frame(zero_store);
2594 set_ia32_op_type(zero_store, ia32_AddrModeD);
2595 add_ia32_am_offs_int(zero_store, 4);
2596 set_ia32_ls_mode(zero_store, mode_Iu);
2601 store = new_rd_Sync(dbgi, irg, block, 2, in);
2602 store_mode = mode_Ls;
2604 store_mode = mode_Is;
2608 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2610 set_ia32_use_frame(fild);
2611 set_ia32_op_type(fild, ia32_AddrModeS);
2612 set_ia32_ls_mode(fild, store_mode);
2614 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2620 * Crete a conversion from one integer mode into another one
2622 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2623 dbg_info *dbgi, ir_node *block, ir_node *op,
2626 ir_graph *irg = current_ir_graph;
2627 int src_bits = get_mode_size_bits(src_mode);
2628 int tgt_bits = get_mode_size_bits(tgt_mode);
2629 ir_node *new_block = be_transform_node(block);
2630 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2633 ir_mode *smaller_mode;
2635 ia32_address_mode_t am;
2636 ia32_address_t *addr = &am.addr;
2638 if (src_bits < tgt_bits) {
2639 smaller_mode = src_mode;
2640 smaller_bits = src_bits;
2642 smaller_mode = tgt_mode;
2643 smaller_bits = tgt_bits;
2646 memset(&am, 0, sizeof(am));
2647 if(use_source_address_mode(block, op, NULL)) {
2648 build_address(&am, op);
2650 am.op_type = ia32_AddrModeS;
2652 new_op = be_transform_node(op);
2653 am.op_type = ia32_Normal;
2655 if(addr->base == NULL)
2657 if(addr->index == NULL)
2658 addr->index = noreg;
2659 if(addr->mem == NULL)
2660 addr->mem = new_NoMem();
2662 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2663 if (smaller_bits == 8) {
2664 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2665 addr->index, addr->mem, new_op,
2668 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2669 addr->index, addr->mem, new_op,
2673 set_am_attributes(res, &am);
2674 set_ia32_ls_mode(res, smaller_mode);
2675 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2676 res = fix_mem_proj(res, &am);
2682 * Transforms a Conv node.
2684 * @return The created ia32 Conv node
2686 static ir_node *gen_Conv(ir_node *node) {
2687 ir_node *block = get_nodes_block(node);
2688 ir_node *new_block = be_transform_node(block);
2689 ir_node *op = get_Conv_op(node);
2690 ir_node *new_op = NULL;
2691 ir_graph *irg = current_ir_graph;
2692 dbg_info *dbgi = get_irn_dbg_info(node);
2693 ir_mode *src_mode = get_irn_mode(op);
2694 ir_mode *tgt_mode = get_irn_mode(node);
2695 int src_bits = get_mode_size_bits(src_mode);
2696 int tgt_bits = get_mode_size_bits(tgt_mode);
2697 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2698 ir_node *nomem = new_rd_NoMem(irg);
2699 ir_node *res = NULL;
2701 if (src_mode == mode_b) {
2702 assert(mode_is_int(tgt_mode));
2703 /* nothing to do, we already model bools as 0/1 ints */
2704 return be_transform_node(op);
2707 if (src_mode == tgt_mode) {
2708 if (get_Conv_strict(node)) {
2709 if (USE_SSE2(env_cg)) {
2710 /* when we are in SSE mode, we can kill all strict no-op conversion */
2711 return be_transform_node(op);
2714 /* this should be optimized already, but who knows... */
2715 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2716 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2717 return be_transform_node(op);
2721 if (mode_is_float(src_mode)) {
2722 new_op = be_transform_node(op);
2723 /* we convert from float ... */
2724 if (mode_is_float(tgt_mode)) {
2725 if(src_mode == mode_E && tgt_mode == mode_D
2726 && !get_Conv_strict(node)) {
2727 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2732 if (USE_SSE2(env_cg)) {
2733 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2734 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2736 set_ia32_ls_mode(res, tgt_mode);
2738 if(get_Conv_strict(node)) {
2739 res = gen_x87_strict_conv(tgt_mode, new_op);
2740 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2743 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2748 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2749 if (USE_SSE2(env_cg)) {
2750 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2752 set_ia32_ls_mode(res, src_mode);
2754 return gen_x87_fp_to_gp(node);
2758 /* we convert from int ... */
2759 if (mode_is_float(tgt_mode)) {
2761 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2762 if (USE_SSE2(env_cg)) {
2763 new_op = be_transform_node(op);
2764 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2766 set_ia32_ls_mode(res, tgt_mode);
2768 res = gen_x87_gp_to_fp(node, src_mode);
2769 if(get_Conv_strict(node)) {
2770 res = gen_x87_strict_conv(tgt_mode, res);
2771 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2772 ia32_get_old_node_name(env_cg, node));
2776 } else if(tgt_mode == mode_b) {
2777 /* mode_b lowering already took care that we only have 0/1 values */
2778 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2779 src_mode, tgt_mode));
2780 return be_transform_node(op);
2783 if (src_bits == tgt_bits) {
2784 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2785 src_mode, tgt_mode));
2786 return be_transform_node(op);
2789 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2797 static int check_immediate_constraint(long val, char immediate_constraint_type)
2799 switch (immediate_constraint_type) {
2803 return val >= 0 && val <= 32;
2805 return val >= 0 && val <= 63;
2807 return val >= -128 && val <= 127;
2809 return val == 0xff || val == 0xffff;
2811 return val >= 0 && val <= 3;
2813 return val >= 0 && val <= 255;
2815 return val >= 0 && val <= 127;
2819 panic("Invalid immediate constraint found");
2823 static ir_node *try_create_Immediate(ir_node *node,
2824 char immediate_constraint_type)
2827 tarval *offset = NULL;
2828 int offset_sign = 0;
2830 ir_entity *symconst_ent = NULL;
2831 int symconst_sign = 0;
2833 ir_node *cnst = NULL;
2834 ir_node *symconst = NULL;
2837 mode = get_irn_mode(node);
2838 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2842 if(is_Minus(node)) {
2844 node = get_Minus_op(node);
2847 if(is_Const(node)) {
2850 offset_sign = minus;
2851 } else if(is_SymConst(node)) {
2854 symconst_sign = minus;
2855 } else if(is_Add(node)) {
2856 ir_node *left = get_Add_left(node);
2857 ir_node *right = get_Add_right(node);
2858 if(is_Const(left) && is_SymConst(right)) {
2861 symconst_sign = minus;
2862 offset_sign = minus;
2863 } else if(is_SymConst(left) && is_Const(right)) {
2866 symconst_sign = minus;
2867 offset_sign = minus;
2869 } else if(is_Sub(node)) {
2870 ir_node *left = get_Sub_left(node);
2871 ir_node *right = get_Sub_right(node);
2872 if(is_Const(left) && is_SymConst(right)) {
2875 symconst_sign = !minus;
2876 offset_sign = minus;
2877 } else if(is_SymConst(left) && is_Const(right)) {
2880 symconst_sign = minus;
2881 offset_sign = !minus;
2888 offset = get_Const_tarval(cnst);
2889 if(tarval_is_long(offset)) {
2890 val = get_tarval_long(offset);
2892 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2897 if(!check_immediate_constraint(val, immediate_constraint_type))
2900 if(symconst != NULL) {
2901 if(immediate_constraint_type != 0) {
2902 /* we need full 32bits for symconsts */
2906 /* unfortunately the assembler/linker doesn't support -symconst */
2910 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2912 symconst_ent = get_SymConst_entity(symconst);
2914 if(cnst == NULL && symconst == NULL)
2917 if(offset_sign && offset != NULL) {
2918 offset = tarval_neg(offset);
2921 res = create_Immediate(symconst_ent, symconst_sign, val);
2926 static ir_node *create_immediate_or_transform(ir_node *node,
2927 char immediate_constraint_type)
2929 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2930 if (new_node == NULL) {
2931 new_node = be_transform_node(node);
2936 typedef struct constraint_t constraint_t;
2937 struct constraint_t {
2940 const arch_register_req_t **out_reqs;
2942 const arch_register_req_t *req;
2943 unsigned immediate_possible;
2944 char immediate_type;
2947 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2949 int immediate_possible = 0;
2950 char immediate_type = 0;
2951 unsigned limited = 0;
2952 const arch_register_class_t *cls = NULL;
2953 ir_graph *irg = current_ir_graph;
2954 struct obstack *obst = get_irg_obstack(irg);
2955 arch_register_req_t *req;
2956 unsigned *limited_ptr;
2960 /* TODO: replace all the asserts with nice error messages */
2962 printf("Constraint: %s\n", c);
2972 assert(cls == NULL ||
2973 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2974 cls = &ia32_reg_classes[CLASS_ia32_gp];
2975 limited |= 1 << REG_EAX;
2978 assert(cls == NULL ||
2979 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2980 cls = &ia32_reg_classes[CLASS_ia32_gp];
2981 limited |= 1 << REG_EBX;
2984 assert(cls == NULL ||
2985 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2986 cls = &ia32_reg_classes[CLASS_ia32_gp];
2987 limited |= 1 << REG_ECX;
2990 assert(cls == NULL ||
2991 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2992 cls = &ia32_reg_classes[CLASS_ia32_gp];
2993 limited |= 1 << REG_EDX;
2996 assert(cls == NULL ||
2997 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2998 cls = &ia32_reg_classes[CLASS_ia32_gp];
2999 limited |= 1 << REG_EDI;
3002 assert(cls == NULL ||
3003 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3004 cls = &ia32_reg_classes[CLASS_ia32_gp];
3005 limited |= 1 << REG_ESI;
3008 case 'q': /* q means lower part of the regs only, this makes no
3009 * difference to Q for us (we only assigne whole registers) */
3010 assert(cls == NULL ||
3011 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3012 cls = &ia32_reg_classes[CLASS_ia32_gp];
3013 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3017 assert(cls == NULL ||
3018 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3019 cls = &ia32_reg_classes[CLASS_ia32_gp];
3020 limited |= 1 << REG_EAX | 1 << REG_EDX;
3023 assert(cls == NULL ||
3024 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3025 cls = &ia32_reg_classes[CLASS_ia32_gp];
3026 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3027 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3034 assert(cls == NULL);
3035 cls = &ia32_reg_classes[CLASS_ia32_gp];
3041 /* TODO: mark values so the x87 simulator knows about t and u */
3042 assert(cls == NULL);
3043 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3048 assert(cls == NULL);
3049 /* TODO: check that sse2 is supported */
3050 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3060 assert(!immediate_possible);
3061 immediate_possible = 1;
3062 immediate_type = *c;
3066 assert(!immediate_possible);
3067 immediate_possible = 1;
3071 assert(!immediate_possible && cls == NULL);
3072 immediate_possible = 1;
3073 cls = &ia32_reg_classes[CLASS_ia32_gp];
3086 assert(constraint->is_in && "can only specify same constraint "
3089 sscanf(c, "%d%n", &same_as, &p);
3096 case 'E': /* no float consts yet */
3097 case 'F': /* no float consts yet */
3098 case 's': /* makes no sense on x86 */
3099 case 'X': /* we can't support that in firm */
3103 case '<': /* no autodecrement on x86 */
3104 case '>': /* no autoincrement on x86 */
3105 case 'C': /* sse constant not supported yet */
3106 case 'G': /* 80387 constant not supported yet */
3107 case 'y': /* we don't support mmx registers yet */
3108 case 'Z': /* not available in 32 bit mode */
3109 case 'e': /* not available in 32 bit mode */
3110 panic("unsupported asm constraint '%c' found in (%+F)",
3111 *c, current_ir_graph);
3114 panic("unknown asm constraint '%c' found in (%+F)", *c,
3122 const arch_register_req_t *other_constr;
3124 assert(cls == NULL && "same as and register constraint not supported");
3125 assert(!immediate_possible && "same as and immediate constraint not "
3127 assert(same_as < constraint->n_outs && "wrong constraint number in "
3128 "same_as constraint");
3130 other_constr = constraint->out_reqs[same_as];
3132 req = obstack_alloc(obst, sizeof(req[0]));
3133 req->cls = other_constr->cls;
3134 req->type = arch_register_req_type_should_be_same;
3135 req->limited = NULL;
3136 req->other_same[0] = pos;
3137 req->other_same[1] = -1;
3138 req->other_different = -1;
3140 /* switch constraints. This is because in firm we have same_as
3141 * constraints on the output constraints while in the gcc asm syntax
3142 * they are specified on the input constraints */
3143 constraint->req = other_constr;
3144 constraint->out_reqs[same_as] = req;
3145 constraint->immediate_possible = 0;
3149 if(immediate_possible && cls == NULL) {
3150 cls = &ia32_reg_classes[CLASS_ia32_gp];
3152 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3153 assert(cls != NULL);
3155 if(immediate_possible) {
3156 assert(constraint->is_in
3157 && "imeediates make no sense for output constraints");
3159 /* todo: check types (no float input on 'r' constrained in and such... */
3162 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3163 limited_ptr = (unsigned*) (req+1);
3165 req = obstack_alloc(obst, sizeof(req[0]));
3167 memset(req, 0, sizeof(req[0]));
3170 req->type = arch_register_req_type_limited;
3171 *limited_ptr = limited;
3172 req->limited = limited_ptr;
3174 req->type = arch_register_req_type_normal;
3178 constraint->req = req;
3179 constraint->immediate_possible = immediate_possible;
3180 constraint->immediate_type = immediate_type;
3183 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3190 panic("Clobbers not supported yet");
3194 * generates code for a ASM node
3196 static ir_node *gen_ASM(ir_node *node)
3199 ir_graph *irg = current_ir_graph;
3200 ir_node *block = be_transform_node(get_nodes_block(node));
3201 dbg_info *dbgi = get_irn_dbg_info(node);
3208 ia32_asm_attr_t *attr;
3209 const arch_register_req_t **out_reqs;
3210 const arch_register_req_t **in_reqs;
3211 struct obstack *obst;
3212 constraint_t parsed_constraint;
3214 /* transform inputs */
3215 arity = get_irn_arity(node);
3216 in = alloca(arity * sizeof(in[0]));
3217 memset(in, 0, arity * sizeof(in[0]));
3219 n_outs = get_ASM_n_output_constraints(node);
3220 n_clobbers = get_ASM_n_clobbers(node);
3221 out_arity = n_outs + n_clobbers;
3223 /* construct register constraints */
3224 obst = get_irg_obstack(irg);
3225 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
3226 parsed_constraint.out_reqs = out_reqs;
3227 parsed_constraint.n_outs = n_outs;
3228 parsed_constraint.is_in = 0;
3229 for(i = 0; i < out_arity; ++i) {
3233 const ir_asm_constraint *constraint;
3234 constraint = & get_ASM_output_constraints(node) [i];
3235 c = get_id_str(constraint->constraint);
3236 parse_asm_constraint(i, &parsed_constraint, c);
3238 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
3239 c = get_id_str(glob_id);
3240 parse_clobber(node, i, &parsed_constraint, c);
3242 out_reqs[i] = parsed_constraint.req;
3245 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
3246 parsed_constraint.is_in = 1;
3247 for(i = 0; i < arity; ++i) {
3248 const ir_asm_constraint *constraint;
3252 constraint = & get_ASM_input_constraints(node) [i];
3253 constr_id = constraint->constraint;
3254 c = get_id_str(constr_id);
3255 parse_asm_constraint(i, &parsed_constraint, c);
3256 in_reqs[i] = parsed_constraint.req;
3258 if(parsed_constraint.immediate_possible) {
3259 ir_node *pred = get_irn_n(node, i);
3260 char imm_type = parsed_constraint.immediate_type;
3261 ir_node *immediate = try_create_Immediate(pred, imm_type);
3263 if(immediate != NULL) {
3269 /* transform inputs */
3270 for(i = 0; i < arity; ++i) {
3272 ir_node *transformed;
3277 pred = get_irn_n(node, i);
3278 transformed = be_transform_node(pred);
3279 in[i] = transformed;
3282 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
3284 generic_attr = get_irn_generic_attr(res);
3285 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
3286 attr->asm_text = get_ASM_text(node);
3287 set_ia32_out_req_all(res, out_reqs);
3288 set_ia32_in_req_all(res, in_reqs);
3290 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3295 /********************************************
3298 * | |__ ___ _ __ ___ __| | ___ ___
3299 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3300 * | |_) | __/ | | | (_) | (_| | __/\__ \
3301 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3303 ********************************************/
3306 * Transforms a FrameAddr into an ia32 Add.
3308 static ir_node *gen_be_FrameAddr(ir_node *node) {
3309 ir_node *block = be_transform_node(get_nodes_block(node));
3310 ir_node *op = be_get_FrameAddr_frame(node);
3311 ir_node *new_op = be_transform_node(op);
3312 ir_graph *irg = current_ir_graph;
3313 dbg_info *dbgi = get_irn_dbg_info(node);
3314 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3317 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3318 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3319 set_ia32_use_frame(res);
3321 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3327 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3329 static ir_node *gen_be_Return(ir_node *node) {
3330 ir_graph *irg = current_ir_graph;
3331 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3332 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3333 ir_entity *ent = get_irg_entity(irg);
3334 ir_type *tp = get_entity_type(ent);
3339 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3340 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3343 int pn_ret_val, pn_ret_mem, arity, i;
3345 assert(ret_val != NULL);
3346 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3347 return be_duplicate_node(node);
3350 res_type = get_method_res_type(tp, 0);
3352 if (! is_Primitive_type(res_type)) {
3353 return be_duplicate_node(node);
3356 mode = get_type_mode(res_type);
3357 if (! mode_is_float(mode)) {
3358 return be_duplicate_node(node);
3361 assert(get_method_n_ress(tp) == 1);
3363 pn_ret_val = get_Proj_proj(ret_val);
3364 pn_ret_mem = get_Proj_proj(ret_mem);
3366 /* get the Barrier */
3367 barrier = get_Proj_pred(ret_val);
3369 /* get result input of the Barrier */
3370 ret_val = get_irn_n(barrier, pn_ret_val);
3371 new_ret_val = be_transform_node(ret_val);
3373 /* get memory input of the Barrier */
3374 ret_mem = get_irn_n(barrier, pn_ret_mem);
3375 new_ret_mem = be_transform_node(ret_mem);
3377 frame = get_irg_frame(irg);
3379 dbgi = get_irn_dbg_info(barrier);
3380 block = be_transform_node(get_nodes_block(barrier));
3382 noreg = ia32_new_NoReg_gp(env_cg);
3384 /* store xmm0 onto stack */
3385 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3386 new_ret_mem, new_ret_val);
3387 set_ia32_ls_mode(sse_store, mode);
3388 set_ia32_op_type(sse_store, ia32_AddrModeD);
3389 set_ia32_use_frame(sse_store);
3391 /* load into x87 register */
3392 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3393 set_ia32_op_type(fld, ia32_AddrModeS);
3394 set_ia32_use_frame(fld);
3396 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3397 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3399 /* create a new barrier */
3400 arity = get_irn_arity(barrier);
3401 in = alloca(arity * sizeof(in[0]));
3402 for (i = 0; i < arity; ++i) {
3405 if (i == pn_ret_val) {
3407 } else if (i == pn_ret_mem) {
3410 ir_node *in = get_irn_n(barrier, i);
3411 new_in = be_transform_node(in);
3416 new_barrier = new_ir_node(dbgi, irg, block,
3417 get_irn_op(barrier), get_irn_mode(barrier),
3419 copy_node_attr(barrier, new_barrier);
3420 be_duplicate_deps(barrier, new_barrier);
3421 be_set_transformed_node(barrier, new_barrier);
3422 mark_irn_visited(barrier);
3424 /* transform normally */
3425 return be_duplicate_node(node);
3429 * Transform a be_AddSP into an ia32_SubSP.
3431 static ir_node *gen_be_AddSP(ir_node *node)
3433 ir_node *src_block = get_nodes_block(node);
3434 ir_node *new_block = be_transform_node(src_block);
3435 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3436 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3437 ir_graph *irg = current_ir_graph;
3438 dbg_info *dbgi = get_irn_dbg_info(node);
3440 ia32_address_mode_t am;
3441 ia32_address_t *addr = &am.addr;
3442 match_flags_t flags = 0;
3444 match_arguments(&am, src_block, sp, sz, flags);
3446 new_node = new_rd_ia32_SubSP(dbgi, irg, new_block, addr->base, addr->index,
3447 addr->mem, am.new_op1, am.new_op2);
3448 set_am_attributes(new_node, &am);
3449 /* we can't use source address mode anymore when using immediates */
3450 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3451 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3452 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3454 new_node = fix_mem_proj(new_node, &am);
3460 * Transform a be_SubSP into an ia32_AddSP
3462 static ir_node *gen_be_SubSP(ir_node *node)
3464 ir_node *src_block = get_nodes_block(node);
3465 ir_node *new_block = be_transform_node(src_block);
3466 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3467 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3468 ir_graph *irg = current_ir_graph;
3469 dbg_info *dbgi = get_irn_dbg_info(node);
3471 ia32_address_mode_t am;
3472 ia32_address_t *addr = &am.addr;
3473 match_flags_t flags = 0;
3475 match_arguments(&am, src_block, sp, sz, flags);
3477 new_node = new_rd_ia32_AddSP(dbgi, irg, new_block, addr->base, addr->index,
3478 addr->mem, am.new_op1, am.new_op2);
3479 set_am_attributes(new_node, &am);
3480 /* we can't use source address mode anymore when using immediates */
3481 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3482 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3483 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3485 new_node = fix_mem_proj(new_node, &am);
3491 * This function just sets the register for the Unknown node
3492 * as this is not done during register allocation because Unknown
3493 * is an "ignore" node.
3495 static ir_node *gen_Unknown(ir_node *node) {
3496 ir_mode *mode = get_irn_mode(node);
3498 if (mode_is_float(mode)) {
3499 if (USE_SSE2(env_cg)) {
3500 return ia32_new_Unknown_xmm(env_cg);
3502 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3503 ir_graph *irg = current_ir_graph;
3504 dbg_info *dbgi = get_irn_dbg_info(node);
3505 ir_node *block = get_irg_start_block(irg);
3506 return new_rd_ia32_vfldz(dbgi, irg, block);
3508 } else if (mode_needs_gp_reg(mode)) {
3509 return ia32_new_Unknown_gp(env_cg);
3511 assert(0 && "unsupported Unknown-Mode");
3518 * Change some phi modes
3520 static ir_node *gen_Phi(ir_node *node) {
3521 ir_node *block = be_transform_node(get_nodes_block(node));
3522 ir_graph *irg = current_ir_graph;
3523 dbg_info *dbgi = get_irn_dbg_info(node);
3524 ir_mode *mode = get_irn_mode(node);
3527 if(mode_needs_gp_reg(mode)) {
3528 /* we shouldn't have any 64bit stuff around anymore */
3529 assert(get_mode_size_bits(mode) <= 32);
3530 /* all integer operations are on 32bit registers now */
3532 } else if(mode_is_float(mode)) {
3533 if (USE_SSE2(env_cg)) {
3540 /* phi nodes allow loops, so we use the old arguments for now
3541 * and fix this later */
3542 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3543 get_irn_in(node) + 1);
3544 copy_node_attr(node, phi);
3545 be_duplicate_deps(node, phi);
3547 be_set_transformed_node(node, phi);
3548 be_enqueue_preds(node);
3556 static ir_node *gen_IJmp(ir_node *node) {
3557 /* TODO: support AM */
3558 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3562 /**********************************************************************
3565 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3566 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3567 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3568 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3570 **********************************************************************/
3572 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3574 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3577 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3578 ir_node *val, ir_node *mem);
3581 * Transforms a lowered Load into a "real" one.
3583 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3585 ir_node *block = be_transform_node(get_nodes_block(node));
3586 ir_node *ptr = get_irn_n(node, 0);
3587 ir_node *new_ptr = be_transform_node(ptr);
3588 ir_node *mem = get_irn_n(node, 1);
3589 ir_node *new_mem = be_transform_node(mem);
3590 ir_graph *irg = current_ir_graph;
3591 dbg_info *dbgi = get_irn_dbg_info(node);
3592 ir_mode *mode = get_ia32_ls_mode(node);
3593 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3596 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3598 set_ia32_op_type(new_op, ia32_AddrModeS);
3599 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3600 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3601 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3602 if (is_ia32_am_sc_sign(node))
3603 set_ia32_am_sc_sign(new_op);
3604 set_ia32_ls_mode(new_op, mode);
3605 if (is_ia32_use_frame(node)) {
3606 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3607 set_ia32_use_frame(new_op);
3610 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3616 * Transforms a lowered Store into a "real" one.
3618 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3620 ir_node *block = be_transform_node(get_nodes_block(node));
3621 ir_node *ptr = get_irn_n(node, 0);
3622 ir_node *new_ptr = be_transform_node(ptr);
3623 ir_node *val = get_irn_n(node, 1);
3624 ir_node *new_val = be_transform_node(val);
3625 ir_node *mem = get_irn_n(node, 2);
3626 ir_node *new_mem = be_transform_node(mem);
3627 ir_graph *irg = current_ir_graph;
3628 dbg_info *dbgi = get_irn_dbg_info(node);
3629 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3630 ir_mode *mode = get_ia32_ls_mode(node);
3634 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3636 am_offs = get_ia32_am_offs_int(node);
3637 add_ia32_am_offs_int(new_op, am_offs);
3639 set_ia32_op_type(new_op, ia32_AddrModeD);
3640 set_ia32_ls_mode(new_op, mode);
3641 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3642 set_ia32_use_frame(new_op);
3644 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3651 * Transforms an ia32_l_XXX into a "real" XXX node
3653 * @param node The node to transform
3654 * @return the created ia32 XXX node
3656 #define GEN_LOWERED_OP(op) \
3657 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3658 return gen_binop(node, get_binop_left(node), \
3659 get_binop_right(node), new_rd_ia32_##op,0); \
3662 #define GEN_LOWERED_x87_OP(op) \
3663 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3665 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3666 get_binop_right(node), new_rd_ia32_##op, 0); \
3670 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3671 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3672 return gen_shift_binop(node, get_irn_n(node, 0), \
3673 get_irn_n(node, 1), new_rd_ia32_##op); \
3676 GEN_LOWERED_x87_OP(vfprem)
3677 GEN_LOWERED_x87_OP(vfmul)
3678 GEN_LOWERED_x87_OP(vfsub)
3679 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3680 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3681 GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
3682 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3684 static ir_node *gen_ia32_l_Add(ir_node *node) {
3685 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3686 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3687 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, 1);
3689 if(is_Proj(lowered)) {
3690 lowered = get_Proj_pred(lowered);
3692 assert(is_ia32_Add(lowered));
3693 set_irn_mode(lowered, mode_T);
3699 static ir_node *gen_ia32_l_Adc(ir_node *node) {
3700 ir_node *src_block = get_nodes_block(node);
3701 ir_node *block = be_transform_node(src_block);
3702 ir_node *op1 = get_irn_n(node, n_ia32_l_Adc_left);
3703 ir_node *op2 = get_irn_n(node, n_ia32_l_Adc_right);
3704 ir_node *flags = get_irn_n(node, n_ia32_l_Adc_eflags);
3705 ir_node *new_flags = be_transform_node(flags);
3706 ir_graph *irg = current_ir_graph;
3707 dbg_info *dbgi = get_irn_dbg_info(node);
3709 ia32_address_mode_t am;
3710 ia32_address_t *addr = &am.addr;
3712 match_arguments(&am, src_block, op1, op2, match_commutative);
3714 new_node = new_rd_ia32_Adc(dbgi, irg, block, addr->base, addr->index,
3715 addr->mem, am.new_op1, am.new_op2, new_flags);
3716 set_am_attributes(new_node, &am);
3717 /* we can't use source address mode anymore when using immediates */
3718 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3719 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3720 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3722 new_node = fix_mem_proj(new_node, &am);
3728 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3730 * @param node The node to transform
3731 * @return the created ia32 Neg node
3733 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3734 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3738 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3740 * @param node The node to transform
3741 * @return the created ia32 vfild node
3743 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3744 return gen_lowered_Load(node, new_rd_ia32_vfild);
3748 * Transforms an ia32_l_Load into a "real" ia32_Load node
3750 * @param node The node to transform
3751 * @return the created ia32 Load node
3753 static ir_node *gen_ia32_l_Load(ir_node *node) {
3754 return gen_lowered_Load(node, new_rd_ia32_Load);
3758 * Transforms an ia32_l_Store into a "real" ia32_Store node
3760 * @param node The node to transform
3761 * @return the created ia32 Store node
3763 static ir_node *gen_ia32_l_Store(ir_node *node) {
3764 return gen_lowered_Store(node, new_rd_ia32_Store);
3768 * Transforms a l_vfist into a "real" vfist node.
3770 * @param node The node to transform
3771 * @return the created ia32 vfist node
3773 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3774 ir_node *block = be_transform_node(get_nodes_block(node));
3775 ir_node *ptr = get_irn_n(node, 0);
3776 ir_node *new_ptr = be_transform_node(ptr);
3777 ir_node *val = get_irn_n(node, 1);
3778 ir_node *new_val = be_transform_node(val);
3779 ir_node *mem = get_irn_n(node, 2);
3780 ir_node *new_mem = be_transform_node(mem);
3781 ir_graph *irg = current_ir_graph;
3782 dbg_info *dbgi = get_irn_dbg_info(node);
3783 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3784 ir_mode *mode = get_ia32_ls_mode(node);
3785 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3789 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3790 new_val, trunc_mode);
3792 am_offs = get_ia32_am_offs_int(node);
3793 add_ia32_am_offs_int(new_op, am_offs);
3795 set_ia32_op_type(new_op, ia32_AddrModeD);
3796 set_ia32_ls_mode(new_op, mode);
3797 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3798 set_ia32_use_frame(new_op);
3800 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3806 * Transforms a l_vfdiv into a "real" vfdiv node.
3808 * @param env The transformation environment
3809 * @return the created ia32 vfdiv node
3811 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3812 ir_node *block = be_transform_node(get_nodes_block(node));
3813 ir_node *left = get_binop_left(node);
3814 ir_node *new_left = be_transform_node(left);
3815 ir_node *right = get_binop_right(node);
3816 ir_node *new_right = be_transform_node(right);
3817 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3818 ir_graph *irg = current_ir_graph;
3819 dbg_info *dbgi = get_irn_dbg_info(node);
3820 ir_node *fpcw = get_fpcw();
3823 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_NoMem(),
3824 new_left, new_right, fpcw);
3825 clear_ia32_commutative(vfdiv);
3827 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3833 * Transforms a l_MulS into a "real" MulS node.
3835 * @param env The transformation environment
3836 * @return the created ia32 Mul node
3838 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3839 ir_node *block = be_transform_node(get_nodes_block(node));
3840 ir_node *left = get_binop_left(node);
3841 ir_node *new_left = be_transform_node(left);
3842 ir_node *right = get_binop_right(node);
3843 ir_node *new_right = be_transform_node(right);
3844 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3845 ir_graph *irg = current_ir_graph;
3846 dbg_info *dbgi = get_irn_dbg_info(node);
3848 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3849 /* and then skip the result Proj, because all needed Projs are already there. */
3850 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(),
3851 new_left, new_right);
3852 clear_ia32_commutative(muls);
3854 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3860 * Transforms a l_IMulS into a "real" IMul1OPS node.
3862 * @param env The transformation environment
3863 * @return the created ia32 IMul1OP node
3865 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3866 ir_node *block = be_transform_node(get_nodes_block(node));
3867 ir_node *left = get_binop_left(node);
3868 ir_node *new_left = be_transform_node(left);
3869 ir_node *right = get_binop_right(node);
3870 ir_node *new_right = be_transform_node(right);
3871 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3872 ir_graph *irg = current_ir_graph;
3873 dbg_info *dbgi = get_irn_dbg_info(node);
3875 /* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */
3876 /* and then skip the result Proj, because all needed Projs are already there. */
3877 ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg,
3878 new_NoMem(), new_left, new_right);
3879 clear_ia32_commutative(muls);
3881 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3886 static ir_node *gen_ia32_l_Sub(ir_node *node) {
3887 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
3888 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
3889 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, 0);
3891 if(is_Proj(lowered)) {
3892 lowered = get_Proj_pred(lowered);
3894 assert(is_ia32_Sub(lowered));
3895 set_irn_mode(lowered, mode_T);
3901 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
3902 ir_node *src_block = get_nodes_block(node);
3903 ir_node *block = be_transform_node(src_block);
3904 ir_node *op1 = get_irn_n(node, n_ia32_l_Sbb_left);
3905 ir_node *op2 = get_irn_n(node, n_ia32_l_Sbb_right);
3906 ir_node *flags = get_irn_n(node, n_ia32_l_Sbb_eflags);
3907 ir_node *new_flags = be_transform_node(flags);
3908 ir_graph *irg = current_ir_graph;
3909 dbg_info *dbgi = get_irn_dbg_info(node);
3911 ia32_address_mode_t am;
3912 ia32_address_t *addr = &am.addr;
3914 match_arguments(&am, src_block, op1, op2, match_commutative);
3916 new_node = new_rd_ia32_Sbb(dbgi, irg, block, addr->base, addr->index,
3917 addr->mem, am.new_op1, am.new_op2, new_flags);
3918 set_am_attributes(new_node, &am);
3919 /* we can't use source address mode anymore when using immediates */
3920 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3921 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3922 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3924 new_node = fix_mem_proj(new_node, &am);
3930 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3931 * op1 - target to be shifted
3932 * op2 - contains bits to be shifted into target
3934 * Only op3 can be an immediate.
3936 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3937 ir_node *op2, ir_node *count)
3939 ir_node *block = be_transform_node(get_nodes_block(node));
3940 ir_node *new_op = NULL;
3941 ir_graph *irg = current_ir_graph;
3942 dbg_info *dbgi = get_irn_dbg_info(node);
3943 ir_node *new_op1 = be_transform_node(op1);
3944 ir_node *new_op2 = be_transform_node(op2);
3945 ir_node *new_count = create_immediate_or_transform(count, 'I');
3947 /* TODO proper AM support */
3949 if (is_ia32_l_ShlD(node))
3950 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3952 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3954 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3959 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3960 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3961 get_irn_n(node, 1), get_irn_n(node, 2));
3964 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3965 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3966 get_irn_n(node, 1), get_irn_n(node, 2));
3970 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3972 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3973 ir_node *block = be_transform_node(get_nodes_block(node));
3974 ir_node *val = get_irn_n(node, 1);
3975 ir_node *new_val = be_transform_node(val);
3976 ia32_code_gen_t *cg = env_cg;
3977 ir_node *res = NULL;
3978 ir_graph *irg = current_ir_graph;
3980 ir_node *noreg, *new_ptr, *new_mem;
3987 mem = get_irn_n(node, 2);
3988 new_mem = be_transform_node(mem);
3989 ptr = get_irn_n(node, 0);
3990 new_ptr = be_transform_node(ptr);
3991 noreg = ia32_new_NoReg_gp(cg);
3992 dbgi = get_irn_dbg_info(node);
3994 /* Store x87 -> MEM */
3995 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
3996 get_ia32_ls_mode(node));
3997 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3998 set_ia32_use_frame(res);
3999 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
4000 set_ia32_op_type(res, ia32_AddrModeD);
4002 /* Load MEM -> SSE */
4003 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
4004 get_ia32_ls_mode(node));
4005 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4006 set_ia32_use_frame(res);
4007 set_ia32_op_type(res, ia32_AddrModeS);
4008 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
4014 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
4016 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
4017 ir_node *block = be_transform_node(get_nodes_block(node));
4018 ir_node *val = get_irn_n(node, 1);
4019 ir_node *new_val = be_transform_node(val);
4020 ia32_code_gen_t *cg = env_cg;
4021 ir_graph *irg = current_ir_graph;
4022 ir_node *res = NULL;
4023 ir_entity *fent = get_ia32_frame_ent(node);
4024 ir_mode *lsmode = get_ia32_ls_mode(node);
4026 ir_node *noreg, *new_ptr, *new_mem;
4030 if (! USE_SSE2(cg)) {
4031 /* SSE unit is not used -> skip this node. */
4035 ptr = get_irn_n(node, 0);
4036 new_ptr = be_transform_node(ptr);
4037 mem = get_irn_n(node, 2);
4038 new_mem = be_transform_node(mem);
4039 noreg = ia32_new_NoReg_gp(cg);
4040 dbgi = get_irn_dbg_info(node);
4042 /* Store SSE -> MEM */
4043 if (is_ia32_xLoad(skip_Proj(new_val))) {
4044 ir_node *ld = skip_Proj(new_val);
4046 /* we can vfld the value directly into the fpu */
4047 fent = get_ia32_frame_ent(ld);
4048 ptr = get_irn_n(ld, 0);
4049 offs = get_ia32_am_offs_int(ld);
4051 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
4053 set_ia32_frame_ent(res, fent);
4054 set_ia32_use_frame(res);
4055 set_ia32_ls_mode(res, lsmode);
4056 set_ia32_op_type(res, ia32_AddrModeD);
4060 /* Load MEM -> x87 */
4061 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4062 set_ia32_frame_ent(res, fent);
4063 set_ia32_use_frame(res);
4064 add_ia32_am_offs_int(res, offs);
4065 set_ia32_op_type(res, ia32_AddrModeS);
4066 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4071 /*********************************************************
4074 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
4075 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
4076 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4077 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4079 *********************************************************/
4082 * the BAD transformer.
4084 static ir_node *bad_transform(ir_node *node) {
4085 panic("No transform function for %+F available.\n", node);
4090 * Transform the Projs of an AddSP.
4092 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4093 ir_node *block = be_transform_node(get_nodes_block(node));
4094 ir_node *pred = get_Proj_pred(node);
4095 ir_node *new_pred = be_transform_node(pred);
4096 ir_graph *irg = current_ir_graph;
4097 dbg_info *dbgi = get_irn_dbg_info(node);
4098 long proj = get_Proj_proj(node);
4100 if (proj == pn_be_AddSP_sp) {
4101 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4102 pn_ia32_SubSP_stack);
4103 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4105 } else if(proj == pn_be_AddSP_res) {
4106 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4107 pn_ia32_SubSP_addr);
4108 } else if (proj == pn_be_AddSP_M) {
4109 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4113 return new_rd_Unknown(irg, get_irn_mode(node));
4117 * Transform the Projs of a SubSP.
4119 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4120 ir_node *block = be_transform_node(get_nodes_block(node));
4121 ir_node *pred = get_Proj_pred(node);
4122 ir_node *new_pred = be_transform_node(pred);
4123 ir_graph *irg = current_ir_graph;
4124 dbg_info *dbgi = get_irn_dbg_info(node);
4125 long proj = get_Proj_proj(node);
4127 if (proj == pn_be_SubSP_sp) {
4128 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4129 pn_ia32_AddSP_stack);
4130 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4132 } else if (proj == pn_be_SubSP_M) {
4133 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4137 return new_rd_Unknown(irg, get_irn_mode(node));
4141 * Transform and renumber the Projs from a Load.
4143 static ir_node *gen_Proj_Load(ir_node *node) {
4145 ir_node *block = be_transform_node(get_nodes_block(node));
4146 ir_node *pred = get_Proj_pred(node);
4147 ir_graph *irg = current_ir_graph;
4148 dbg_info *dbgi = get_irn_dbg_info(node);
4149 long proj = get_Proj_proj(node);
4152 /* loads might be part of source address mode matches, so we don't
4153 transform the ProjMs yet (with the exception of loads whose result is
4156 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4159 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4161 /* this is needed, because sometimes we have loops that are only
4162 reachable through the ProjM */
4163 be_enqueue_preds(node);
4164 /* do it in 2 steps, to silence firm verifier */
4165 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4166 set_Proj_proj(res, pn_ia32_Load_M);
4170 /* renumber the proj */
4171 new_pred = be_transform_node(pred);
4172 if (is_ia32_Load(new_pred)) {
4173 if (proj == pn_Load_res) {
4174 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4176 } else if (proj == pn_Load_M) {
4177 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4180 } else if(is_ia32_Conv_I2I(new_pred)) {
4181 set_irn_mode(new_pred, mode_T);
4182 if (proj == pn_Load_res) {
4183 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4184 } else if (proj == pn_Load_M) {
4185 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4187 } else if (is_ia32_xLoad(new_pred)) {
4188 if (proj == pn_Load_res) {
4189 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4191 } else if (proj == pn_Load_M) {
4192 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4195 } else if (is_ia32_vfld(new_pred)) {
4196 if (proj == pn_Load_res) {
4197 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4199 } else if (proj == pn_Load_M) {
4200 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4204 /* can happen for ProJMs when source address mode happened for the
4207 /* however it should not be the result proj, as that would mean the
4208 load had multiple users and should not have been used for
4210 if(proj != pn_Load_M) {
4211 panic("internal error: transformed node not a Load");
4213 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4217 return new_rd_Unknown(irg, get_irn_mode(node));
4221 * Transform and renumber the Projs from a DivMod like instruction.
4223 static ir_node *gen_Proj_DivMod(ir_node *node) {
4224 ir_node *block = be_transform_node(get_nodes_block(node));
4225 ir_node *pred = get_Proj_pred(node);
4226 ir_node *new_pred = be_transform_node(pred);
4227 ir_graph *irg = current_ir_graph;
4228 dbg_info *dbgi = get_irn_dbg_info(node);
4229 ir_mode *mode = get_irn_mode(node);
4230 long proj = get_Proj_proj(node);
4232 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4234 switch (get_irn_opcode(pred)) {
4238 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4240 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4248 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4250 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4258 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4259 case pn_DivMod_res_div:
4260 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4261 case pn_DivMod_res_mod:
4262 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4272 return new_rd_Unknown(irg, mode);
4276 * Transform and renumber the Projs from a CopyB.
4278 static ir_node *gen_Proj_CopyB(ir_node *node) {
4279 ir_node *block = be_transform_node(get_nodes_block(node));
4280 ir_node *pred = get_Proj_pred(node);
4281 ir_node *new_pred = be_transform_node(pred);
4282 ir_graph *irg = current_ir_graph;
4283 dbg_info *dbgi = get_irn_dbg_info(node);
4284 ir_mode *mode = get_irn_mode(node);
4285 long proj = get_Proj_proj(node);
4288 case pn_CopyB_M_regular:
4289 if (is_ia32_CopyB_i(new_pred)) {
4290 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4291 } else if (is_ia32_CopyB(new_pred)) {
4292 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4300 return new_rd_Unknown(irg, mode);
4304 * Transform and renumber the Projs from a vfdiv.
4306 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
4307 ir_node *block = be_transform_node(get_nodes_block(node));
4308 ir_node *pred = get_Proj_pred(node);
4309 ir_node *new_pred = be_transform_node(pred);
4310 ir_graph *irg = current_ir_graph;
4311 dbg_info *dbgi = get_irn_dbg_info(node);
4312 ir_mode *mode = get_irn_mode(node);
4313 long proj = get_Proj_proj(node);
4316 case pn_ia32_l_vfdiv_M:
4317 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4318 case pn_ia32_l_vfdiv_res:
4319 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4324 return new_rd_Unknown(irg, mode);
4328 * Transform and renumber the Projs from a Quot.
4330 static ir_node *gen_Proj_Quot(ir_node *node) {
4331 ir_node *block = be_transform_node(get_nodes_block(node));
4332 ir_node *pred = get_Proj_pred(node);
4333 ir_node *new_pred = be_transform_node(pred);
4334 ir_graph *irg = current_ir_graph;
4335 dbg_info *dbgi = get_irn_dbg_info(node);
4336 ir_mode *mode = get_irn_mode(node);
4337 long proj = get_Proj_proj(node);
4341 if (is_ia32_xDiv(new_pred)) {
4342 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4343 } else if (is_ia32_vfdiv(new_pred)) {
4344 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4348 if (is_ia32_xDiv(new_pred)) {
4349 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4350 } else if (is_ia32_vfdiv(new_pred)) {
4351 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4359 return new_rd_Unknown(irg, mode);
4363 * Transform the Thread Local Storage Proj.
4365 static ir_node *gen_Proj_tls(ir_node *node) {
4366 ir_node *block = be_transform_node(get_nodes_block(node));
4367 ir_graph *irg = current_ir_graph;
4368 dbg_info *dbgi = NULL;
4369 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4374 static ir_node *gen_be_Call(ir_node *node) {
4375 ir_node *res = be_duplicate_node(node);
4376 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4381 static ir_node *gen_be_IncSP(ir_node *node) {
4382 ir_node *res = be_duplicate_node(node);
4383 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4389 * Transform the Projs from a be_Call.
4391 static ir_node *gen_Proj_be_Call(ir_node *node) {
4392 ir_node *block = be_transform_node(get_nodes_block(node));
4393 ir_node *call = get_Proj_pred(node);
4394 ir_node *new_call = be_transform_node(call);
4395 ir_graph *irg = current_ir_graph;
4396 dbg_info *dbgi = get_irn_dbg_info(node);
4397 ir_type *method_type = be_Call_get_type(call);
4398 int n_res = get_method_n_ress(method_type);
4399 long proj = get_Proj_proj(node);
4400 ir_mode *mode = get_irn_mode(node);
4402 const arch_register_class_t *cls;
4404 /* The following is kinda tricky: If we're using SSE, then we have to
4405 * move the result value of the call in floating point registers to an
4406 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4407 * after the call, we have to make sure to correctly make the
4408 * MemProj and the result Proj use these 2 nodes
4410 if (proj == pn_be_Call_M_regular) {
4411 // get new node for result, are we doing the sse load/store hack?
4412 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4413 ir_node *call_res_new;
4414 ir_node *call_res_pred = NULL;
4416 if (call_res != NULL) {
4417 call_res_new = be_transform_node(call_res);
4418 call_res_pred = get_Proj_pred(call_res_new);
4421 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4422 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4423 pn_be_Call_M_regular);
4425 assert(is_ia32_xLoad(call_res_pred));
4426 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4430 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4431 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4432 && USE_SSE2(env_cg)) {
4434 ir_node *frame = get_irg_frame(irg);
4435 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4437 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4440 /* in case there is no memory output: create one to serialize the copy
4442 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4443 pn_be_Call_M_regular);
4444 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4445 pn_be_Call_first_res);
4447 /* store st(0) onto stack */
4448 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4450 set_ia32_op_type(fstp, ia32_AddrModeD);
4451 set_ia32_use_frame(fstp);
4453 /* load into SSE register */
4454 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4456 set_ia32_op_type(sse_load, ia32_AddrModeS);
4457 set_ia32_use_frame(sse_load);
4459 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4465 /* transform call modes */
4466 if (mode_is_data(mode)) {
4467 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4471 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4475 * Transform the Projs from a Cmp.
4477 static ir_node *gen_Proj_Cmp(ir_node *node)
4479 /* normally Cmps are processed when looking at Cond nodes, but this case
4480 * can happen in complicated Psi conditions */
4481 dbg_info *dbgi = get_irn_dbg_info(node);
4482 ir_node *block = get_nodes_block(node);
4483 ir_node *new_block = be_transform_node(block);
4484 ir_node *cmp = get_Proj_pred(node);
4485 ir_node *new_cmp = be_transform_node(cmp);
4486 long pnc = get_Proj_proj(node);
4489 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node);
4495 * Transform and potentially renumber Proj nodes.
4497 static ir_node *gen_Proj(ir_node *node) {
4498 ir_graph *irg = current_ir_graph;
4499 dbg_info *dbgi = get_irn_dbg_info(node);
4500 ir_node *pred = get_Proj_pred(node);
4501 long proj = get_Proj_proj(node);
4503 if (is_Store(pred)) {
4504 if (proj == pn_Store_M) {
4505 return be_transform_node(pred);
4508 return new_r_Bad(irg);
4510 } else if (is_Load(pred)) {
4511 return gen_Proj_Load(node);
4512 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4513 return gen_Proj_DivMod(node);
4514 } else if (is_CopyB(pred)) {
4515 return gen_Proj_CopyB(node);
4516 } else if (is_Quot(pred)) {
4517 return gen_Proj_Quot(node);
4518 } else if (is_ia32_l_vfdiv(pred)) {
4519 return gen_Proj_l_vfdiv(node);
4520 } else if (be_is_SubSP(pred)) {
4521 return gen_Proj_be_SubSP(node);
4522 } else if (be_is_AddSP(pred)) {
4523 return gen_Proj_be_AddSP(node);
4524 } else if (be_is_Call(pred)) {
4525 return gen_Proj_be_Call(node);
4526 } else if (is_Cmp(pred)) {
4527 return gen_Proj_Cmp(node);
4528 } else if (get_irn_op(pred) == op_Start) {
4529 if (proj == pn_Start_X_initial_exec) {
4530 ir_node *block = get_nodes_block(pred);
4533 /* we exchange the ProjX with a jump */
4534 block = be_transform_node(block);
4535 jump = new_rd_Jmp(dbgi, irg, block);
4538 if (node == be_get_old_anchor(anchor_tls)) {
4539 return gen_Proj_tls(node);
4542 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4546 ir_node *new_pred = be_transform_node(pred);
4547 ir_node *block = be_transform_node(get_nodes_block(node));
4548 ir_mode *mode = get_irn_mode(node);
4549 if (mode_needs_gp_reg(mode)) {
4550 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4551 get_Proj_proj(node));
4552 #ifdef DEBUG_libfirm
4553 new_proj->node_nr = node->node_nr;
4559 return be_duplicate_node(node);
4563 * Enters all transform functions into the generic pointer
4565 static void register_transformers(void)
4569 /* first clear the generic function pointer for all ops */
4570 clear_irp_opcodes_generic_func();
4572 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4573 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4611 /* transform ops from intrinsic lowering */
4633 GEN(ia32_l_X87toSSE);
4634 GEN(ia32_l_SSEtoX87);
4640 /* we should never see these nodes */
4655 /* handle generic backend nodes */
4664 op_Mulh = get_op_Mulh();
4673 * Pre-transform all unknown and noreg nodes.
4675 static void ia32_pretransform_node(void *arch_cg) {
4676 ia32_code_gen_t *cg = arch_cg;
4678 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4679 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4680 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4681 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4682 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4683 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4688 * Walker, checks if all ia32 nodes producing more than one result have
4689 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4691 static void add_missing_keep_walker(ir_node *node, void *data)
4694 unsigned found_projs = 0;
4695 const ir_edge_t *edge;
4696 ir_mode *mode = get_irn_mode(node);
4701 if(!is_ia32_irn(node))
4704 n_outs = get_ia32_n_res(node);
4707 if(is_ia32_SwitchJmp(node))
4710 assert(n_outs < (int) sizeof(unsigned) * 8);
4711 foreach_out_edge(node, edge) {
4712 ir_node *proj = get_edge_src_irn(edge);
4713 int pn = get_Proj_proj(proj);
4715 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4716 found_projs |= 1 << pn;
4720 /* are keeps missing? */
4722 for(i = 0; i < n_outs; ++i) {
4725 const arch_register_req_t *req;
4726 const arch_register_class_t *class;
4728 if(found_projs & (1 << i)) {
4732 req = get_ia32_out_req(node, i);
4737 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4741 block = get_nodes_block(node);
4742 in[0] = new_r_Proj(current_ir_graph, block, node,
4743 arch_register_class_mode(class), i);
4744 if(last_keep != NULL) {
4745 be_Keep_add_node(last_keep, class, in[0]);
4747 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4748 if(sched_is_scheduled(node)) {
4749 sched_add_after(node, last_keep);
4756 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4759 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4761 ir_graph *irg = be_get_birg_irg(cg->birg);
4762 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4765 /* do the transformation */
4766 void ia32_transform_graph(ia32_code_gen_t *cg) {
4767 ir_graph *irg = cg->irg;
4769 /* TODO: look at cpu and fill transform config in with that... */
4770 transform_config.use_incdec = 1;
4771 transform_config.use_sse2 = 0;
4772 transform_config.use_ffreep = 0;
4773 transform_config.use_ftst = 0;
4774 transform_config.use_femms = 0;
4775 transform_config.use_fucomi = 1;
4776 transform_config.use_cmov = 1;
4778 register_transformers();
4780 initial_fpcw = NULL;
4782 heights = heights_new(irg);
4783 calculate_non_address_mode_nodes(irg);
4785 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4787 free_non_address_mode_nodes();
4788 heights_free(heights);
4792 void ia32_init_transform(void)
4794 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");