2 * This file implements the IR transformation from firm into
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
26 #include "../benode_t.h"
27 #include "../besched.h"
29 #include "bearch_ia32_t.h"
31 #include "ia32_nodes_attr.h"
32 #include "../arch/archop.h" /* we need this for Min and Max nodes */
33 #include "ia32_transform.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
37 #include "gen_ia32_regalloc_if.h"
40 #define SET_IA32_ORIG_NODE(n, o)
42 #define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
46 #define SFP_SIGN "0x80000000"
47 #define DFP_SIGN "0x8000000000000000"
48 #define SFP_ABS "0x7FFFFFFF"
49 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
51 #define TP_SFP_SIGN "ia32_sfp_sign"
52 #define TP_DFP_SIGN "ia32_dfp_sign"
53 #define TP_SFP_ABS "ia32_sfp_abs"
54 #define TP_DFP_ABS "ia32_dfp_abs"
56 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
57 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
58 #define ENT_SFP_ABS "IA32_SFP_ABS"
59 #define ENT_DFP_ABS "IA32_DFP_ABS"
61 extern ir_op *get_op_Mulh(void);
63 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
64 ir_node *op1, ir_node *op2, ir_node *mem, ir_mode *mode);
66 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
67 ir_node *op, ir_node *mem, ir_mode *mode);
70 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS
73 /****************************************************************************************************
75 * | | | | / _| | | (_)
76 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
77 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
78 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
79 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
81 ****************************************************************************************************/
88 /* Compares two (entity, tarval) combinations */
89 static int cmp_tv_ent(const void *a, const void *b, size_t len) {
90 const struct tv_ent *e1 = a;
91 const struct tv_ent *e2 = b;
93 return !(e1->tv == e2->tv);
96 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
97 static char *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
98 static set *const_set = NULL;
100 struct tv_ent *entry;
110 const_set = new_set(cmp_tv_ent, 10);
115 tp_name = TP_SFP_SIGN;
116 ent_name = ENT_SFP_SIGN;
120 tp_name = TP_DFP_SIGN;
121 ent_name = ENT_DFP_SIGN;
125 tp_name = TP_SFP_ABS;
126 ent_name = ENT_SFP_ABS;
130 tp_name = TP_DFP_ABS;
131 ent_name = ENT_DFP_ABS;
137 key.tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
140 entry = set_insert(const_set, &key, sizeof(key), HASH_PTR(key.tv));
143 tp = new_type_primitive(new_id_from_str(tp_name), mode);
144 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
146 set_entity_ld_ident(ent, get_entity_ident(ent));
147 set_entity_visibility(ent, visibility_local);
148 set_entity_variability(ent, variability_constant);
149 set_entity_allocation(ent, allocation_static);
151 /* we create a new entity here: It's initialization must resist on the
153 rem = current_ir_graph;
154 current_ir_graph = get_const_code_irg();
155 cnst = new_Const(mode, key.tv);
156 current_ir_graph = rem;
158 set_atomic_ent_value(ent, cnst);
160 /* set the entry for hashmap */
169 * Prints the old node name on cg obst and returns a pointer to it.
171 const char *get_old_node_name(ia32_transform_env_t *env) {
172 static int name_cnt = 0;
173 ia32_isa_t *isa = (ia32_isa_t *)env->cg->arch_env->isa;
175 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", env->irn);
176 obstack_1grow(isa->name_obst, 0);
177 isa->name_obst_size += obstack_object_size(isa->name_obst);
179 if (name_cnt % 1024 == 0) {
180 printf("name obst size reached %d bytes after %d nodes\n", isa->name_obst_size, name_cnt);
182 return obstack_finish(isa->name_obst);
186 /* determine if one operator is an Imm */
187 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
189 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
190 else return is_ia32_Cnst(op2) ? op2 : NULL;
193 /* determine if one operator is not an Imm */
194 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
195 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
200 * Construct a standard binary operation, set AM and immediate if required.
202 * @param env The transformation environment
203 * @param op1 The first operand
204 * @param op2 The second operand
205 * @param func The node constructor function
206 * @return The constructed ia32 node.
208 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
209 ir_node *new_op = NULL;
210 ir_mode *mode = env->mode;
211 dbg_info *dbg = env->dbg;
212 ir_graph *irg = env->irg;
213 ir_node *block = env->block;
214 firm_dbg_module_t *mod = env->mod;
215 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
216 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
217 ir_node *nomem = new_NoMem();
218 ir_node *expr_op, *imm_op;
220 /* Check if immediate optimization is on and */
221 /* if it's an operation with immediate. */
222 if (! env->cg->opt.immops) {
226 else if (is_op_commutative(get_irn_op(env->irn))) {
227 imm_op = get_immediate_op(op1, op2);
228 expr_op = get_expr_op(op1, op2);
231 imm_op = get_immediate_op(NULL, op2);
232 expr_op = get_expr_op(op1, op2);
235 assert((expr_op || imm_op) && "invalid operands");
238 /* We have two consts here: not yet supported */
242 if (mode_is_float(mode)) {
243 /* floating point operations */
245 DB((mod, LEVEL_1, "FP with immediate ..."));
246 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem, mode_T);
247 set_ia32_Immop_attr(new_op, imm_op);
248 set_ia32_am_support(new_op, ia32_am_None);
251 DB((mod, LEVEL_1, "FP binop ..."));
252 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
253 set_ia32_am_support(new_op, ia32_am_Source);
257 /* integer operations */
259 /* This is expr + const */
260 DB((mod, LEVEL_1, "INT with immediate ..."));
261 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem, mode_T);
262 set_ia32_Immop_attr(new_op, imm_op);
265 set_ia32_am_support(new_op, ia32_am_Dest);
268 DB((mod, LEVEL_1, "INT binop ..."));
269 /* This is a normal operation */
270 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
273 set_ia32_am_support(new_op, ia32_am_Full);
277 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
279 set_ia32_res_mode(new_op, mode);
281 if (is_op_commutative(get_irn_op(env->irn))) {
282 set_ia32_commutative(new_op);
285 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
291 * Construct a shift/rotate binary operation, sets AM and immediate if required.
293 * @param env The transformation environment
294 * @param op1 The first operand
295 * @param op2 The second operand
296 * @param func The node constructor function
297 * @return The constructed ia32 node.
299 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
300 ir_node *new_op = NULL;
301 ir_mode *mode = env->mode;
302 dbg_info *dbg = env->dbg;
303 ir_graph *irg = env->irg;
304 ir_node *block = env->block;
305 firm_dbg_module_t *mod = env->mod;
306 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
307 ir_node *nomem = new_NoMem();
308 ir_node *expr_op, *imm_op;
311 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
313 /* Check if immediate optimization is on and */
314 /* if it's an operation with immediate. */
315 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
316 expr_op = get_expr_op(op1, op2);
318 assert((expr_op || imm_op) && "invalid operands");
321 /* We have two consts here: not yet supported */
325 /* Limit imm_op within range imm8 */
327 tv = get_ia32_Immop_tarval(imm_op);
330 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
337 /* integer operations */
339 /* This is shift/rot with const */
340 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
342 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
343 set_ia32_Immop_attr(new_op, imm_op);
346 /* This is a normal shift/rot */
347 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
348 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
352 set_ia32_am_support(new_op, ia32_am_Dest);
354 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
356 set_ia32_res_mode(new_op, mode);
358 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
363 * Construct a standard unary operation, set AM and immediate if required.
365 * @param env The transformation environment
366 * @param op The operand
367 * @param func The node constructor function
368 * @return The constructed ia32 node.
370 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
371 ir_node *new_op = NULL;
372 ir_mode *mode = env->mode;
373 dbg_info *dbg = env->dbg;
374 firm_dbg_module_t *mod = env->mod;
375 ir_graph *irg = env->irg;
376 ir_node *block = env->block;
377 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
378 ir_node *nomem = new_NoMem();
380 new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
382 if (mode_is_float(mode)) {
383 DB((mod, LEVEL_1, "FP unop ..."));
384 /* floating point operations don't support implicit store */
385 set_ia32_am_support(new_op, ia32_am_None);
388 DB((mod, LEVEL_1, "INT unop ..."));
389 set_ia32_am_support(new_op, ia32_am_Dest);
392 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
394 set_ia32_res_mode(new_op, mode);
396 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
402 * Creates an ia32 Add with immediate.
404 * @param env The transformation environment
405 * @param expr_op The expression operator
406 * @param const_op The constant
407 * @return the created ia32 Add node
409 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
410 ir_node *new_op = NULL;
411 tarval *tv = get_ia32_Immop_tarval(const_op);
412 firm_dbg_module_t *mod = env->mod;
413 dbg_info *dbg = env->dbg;
414 ir_graph *irg = env->irg;
415 ir_node *block = env->block;
416 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
417 ir_node *nomem = new_NoMem();
419 tarval_classification_t class_tv, class_negtv;
421 /* try to optimize to inc/dec */
422 if (env->cg->opt.incdec && tv) {
423 /* optimize tarvals */
424 class_tv = classify_tarval(tv);
425 class_negtv = classify_tarval(tarval_neg(tv));
427 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
428 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
429 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
432 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
433 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
434 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
440 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
441 set_ia32_Immop_attr(new_op, const_op);
448 * Creates an ia32 Add.
450 * @param dbg firm node dbg
451 * @param block the block the new node should belong to
452 * @param op1 first operator
453 * @param op2 second operator
454 * @param mode node mode
455 * @return the created ia32 Add node
457 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
458 ir_node *new_op = NULL;
459 dbg_info *dbg = env->dbg;
460 ir_mode *mode = env->mode;
461 ir_graph *irg = env->irg;
462 ir_node *block = env->block;
463 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
464 ir_node *nomem = new_NoMem();
465 ir_node *expr_op, *imm_op;
467 /* Check if immediate optimization is on and */
468 /* if it's an operation with immediate. */
469 imm_op = env->cg->opt.immops ? get_immediate_op(op1, op2) : NULL;
470 expr_op = get_expr_op(op1, op2);
472 assert((expr_op || imm_op) && "invalid operands");
474 if (mode_is_float(mode)) {
475 return gen_binop(env, op1, op2, new_rd_ia32_fAdd);
480 /* No expr_op means, that we have two const - one symconst and */
481 /* one tarval or another symconst - because this case is not */
482 /* covered by constant folding */
484 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
485 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
486 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
489 set_ia32_am_support(new_op, ia32_am_Source);
490 set_ia32_op_type(new_op, ia32_AddrModeS);
491 set_ia32_am_flavour(new_op, ia32_am_O);
493 /* Lea doesn't need a Proj */
497 /* This is expr + const */
498 new_op = gen_imm_Add(env, expr_op, imm_op);
501 set_ia32_am_support(new_op, ia32_am_Dest);
504 /* This is a normal add */
505 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
508 set_ia32_am_support(new_op, ia32_am_Full);
512 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
514 set_ia32_res_mode(new_op, mode);
516 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
522 * Creates an ia32 Mul.
524 * @param dbg firm node dbg
525 * @param block the block the new node should belong to
526 * @param op1 first operator
527 * @param op2 second operator
528 * @param mode node mode
529 * @return the created ia32 Mul node
531 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
534 if (mode_is_float(env->mode)) {
535 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul);
538 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
547 * Creates an ia32 Mulh.
548 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
549 * this result while Mul returns the lower 32 bit.
551 * @param env The transformation environment
552 * @param op1 The first operator
553 * @param op2 The second operator
554 * @return the created ia32 Mulh node
556 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
557 ir_node *proj_EAX, *proj_EDX, *mulh;
560 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
561 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
562 mulh = get_Proj_pred(proj_EAX);
563 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
565 /* to be on the save side */
566 set_Proj_proj(proj_EAX, pn_EAX);
568 if (get_ia32_cnst(mulh)) {
569 /* Mulh with const cannot have AM */
570 set_ia32_am_support(mulh, ia32_am_None);
573 /* Mulh cannot have AM for destination */
574 set_ia32_am_support(mulh, ia32_am_Source);
580 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
588 * Creates an ia32 And.
590 * @param env The transformation environment
591 * @param op1 The first operator
592 * @param op2 The second operator
593 * @return The created ia32 And node
595 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
596 if (mode_is_float(env->mode)) {
597 return gen_binop(env, op1, op2, new_rd_ia32_fAnd);
600 return gen_binop(env, op1, op2, new_rd_ia32_And);
607 * Creates an ia32 Or.
609 * @param env The transformation environment
610 * @param op1 The first operator
611 * @param op2 The second operator
612 * @return The created ia32 Or node
614 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
615 if (mode_is_float(env->mode)) {
616 return gen_binop(env, op1, op2, new_rd_ia32_fOr);
619 return gen_binop(env, op1, op2, new_rd_ia32_Or);
626 * Creates an ia32 Eor.
628 * @param env The transformation environment
629 * @param op1 The first operator
630 * @param op2 The second operator
631 * @return The created ia32 Eor node
633 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
634 if (mode_is_float(env->mode)) {
635 return gen_binop(env, op1, op2, new_rd_ia32_fEor);
638 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
645 * Creates an ia32 Max.
647 * @param env The transformation environment
648 * @param op1 The first operator
649 * @param op2 The second operator
650 * @return the created ia32 Max node
652 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
655 if (mode_is_float(env->mode)) {
656 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
659 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
660 set_ia32_am_support(new_op, ia32_am_None);
661 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
670 * Creates an ia32 Min.
672 * @param env The transformation environment
673 * @param op1 The first operator
674 * @param op2 The second operator
675 * @return the created ia32 Min node
677 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
680 if (mode_is_float(env->mode)) {
681 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
684 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
685 set_ia32_am_support(new_op, ia32_am_None);
686 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
695 * Creates an ia32 Sub with immediate.
697 * @param env The transformation environment
698 * @param op1 The first operator
699 * @param op2 The second operator
700 * @return The created ia32 Sub node
702 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
703 ir_node *new_op = NULL;
704 tarval *tv = get_ia32_Immop_tarval(const_op);
705 firm_dbg_module_t *mod = env->mod;
706 dbg_info *dbg = env->dbg;
707 ir_graph *irg = env->irg;
708 ir_node *block = env->block;
709 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
710 ir_node *nomem = new_NoMem();
712 tarval_classification_t class_tv, class_negtv;
714 /* try to optimize to inc/dec */
715 if (env->cg->opt.incdec && tv) {
716 /* optimize tarvals */
717 class_tv = classify_tarval(tv);
718 class_negtv = classify_tarval(tarval_neg(tv));
720 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
721 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
722 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
725 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
726 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
727 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
733 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
734 set_ia32_Immop_attr(new_op, const_op);
741 * Creates an ia32 Sub.
743 * @param env The transformation environment
744 * @param op1 The first operator
745 * @param op2 The second operator
746 * @return The created ia32 Sub node
748 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
749 ir_node *new_op = NULL;
750 dbg_info *dbg = env->dbg;
751 ir_mode *mode = env->mode;
752 ir_graph *irg = env->irg;
753 ir_node *block = env->block;
754 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
755 ir_node *nomem = new_NoMem();
756 ir_node *expr_op, *imm_op;
758 /* Check if immediate optimization is on and */
759 /* if it's an operation with immediate. */
760 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
761 expr_op = get_expr_op(op1, op2);
763 assert((expr_op || imm_op) && "invalid operands");
765 if (mode_is_float(mode)) {
766 return gen_binop(env, op1, op2, new_rd_ia32_fSub);
771 /* No expr_op means, that we have two const - one symconst and */
772 /* one tarval or another symconst - because this case is not */
773 /* covered by constant folding */
775 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
776 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
777 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
780 set_ia32_am_support(new_op, ia32_am_Source);
781 set_ia32_op_type(new_op, ia32_AddrModeS);
782 set_ia32_am_flavour(new_op, ia32_am_O);
784 /* Lea doesn't need a Proj */
788 /* This is expr - const */
789 new_op = gen_imm_Sub(env, expr_op, imm_op);
792 set_ia32_am_support(new_op, ia32_am_Dest);
795 /* This is a normal sub */
796 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
799 set_ia32_am_support(new_op, ia32_am_Full);
803 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
805 set_ia32_res_mode(new_op, mode);
807 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
813 * Generates an ia32 DivMod with additional infrastructure for the
814 * register allocator if needed.
816 * @param env The transformation environment
817 * @param dividend -no comment- :)
818 * @param divisor -no comment- :)
819 * @param dm_flav flavour_Div/Mod/DivMod
820 * @return The created ia32 DivMod node
822 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
824 ir_node *edx_node, *cltd;
826 dbg_info *dbg = env->dbg;
827 ir_graph *irg = env->irg;
828 ir_node *block = env->block;
829 ir_mode *mode = env->mode;
830 ir_node *irn = env->irn;
835 mem = get_Div_mem(irn);
838 mem = get_Mod_mem(irn);
841 mem = get_DivMod_mem(irn);
847 if (mode_is_signed(mode)) {
848 /* in signed mode, we need to sign extend the dividend */
849 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend, mode_T);
850 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EAX);
851 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EDX);
854 edx_node = new_rd_ia32_Const(dbg, irg, block, mode_Iu);
855 set_ia32_Const_type(edx_node, ia32_Const);
856 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
859 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode_T);
861 set_ia32_flavour(res, dm_flav);
862 set_ia32_n_res(res, 2);
864 /* Only one proj is used -> We must add a second proj and */
865 /* connect this one to a Keep node to eat up the second */
866 /* destroyed register. */
867 if (get_irn_n_edges(irn) == 1) {
868 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
869 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
871 if (get_Proj_proj(proj) == pn_DivMod_res_div) {
872 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
875 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
878 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
881 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
883 set_ia32_res_mode(res, mode_Is);
890 * Wrapper for generate_DivMod. Sets flavour_Mod.
892 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
893 return generate_DivMod(env, op1, op2, flavour_Mod);
899 * Wrapper for generate_DivMod. Sets flavour_Div.
901 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
902 return generate_DivMod(env, op1, op2, flavour_Div);
908 * Wrapper for generate_DivMod. Sets flavour_DivMod.
910 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
911 return generate_DivMod(env, op1, op2, flavour_DivMod);
917 * Creates an ia32 floating Div.
919 * @param env The transformation environment
920 * @param op1 The first operator
921 * @param op2 The second operator
922 * @return The created ia32 fDiv node
924 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
925 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
926 ir_node *nomem = new_rd_NoMem(env->irg);
929 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, env->mode);
930 set_ia32_am_support(new_op, ia32_am_Source);
932 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
940 * Creates an ia32 Shl.
942 * @param env The transformation environment
943 * @param op1 The first operator
944 * @param op2 The second operator
945 * @return The created ia32 Shl node
947 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
948 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shl);
954 * Creates an ia32 Shr.
956 * @param env The transformation environment
957 * @param op1 The first operator
958 * @param op2 The second operator
959 * @return The created ia32 Shr node
961 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
962 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shr);
968 * Creates an ia32 Shrs.
970 * @param env The transformation environment
971 * @param op1 The first operator
972 * @param op2 The second operator
973 * @return The created ia32 Shrs node
975 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
976 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shrs);
982 * Creates an ia32 RotL.
984 * @param env The transformation environment
985 * @param op1 The first operator
986 * @param op2 The second operator
987 * @return The created ia32 RotL node
989 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
990 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
996 * Creates an ia32 RotR.
997 * NOTE: There is no RotR with immediate because this would always be a RotL
998 * "imm-mode_size_bits" which can be pre-calculated.
1000 * @param env The transformation environment
1001 * @param op1 The first operator
1002 * @param op2 The second operator
1003 * @return The created ia32 RotR node
1005 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1006 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1012 * Creates an ia32 RotR or RotL (depending on the found pattern).
1014 * @param env The transformation environment
1015 * @param op1 The first operator
1016 * @param op2 The second operator
1017 * @return The created ia32 RotL or RotR node
1019 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1020 ir_node *rotate = NULL;
1022 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1023 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1024 that means we can create a RotR instead of an Add and a RotL */
1027 ir_node *pred = get_Proj_pred(op2);
1029 if (is_ia32_Add(pred)) {
1030 ir_node *pred_pred = get_irn_n(pred, 2);
1031 tarval *tv = get_ia32_Immop_tarval(pred);
1032 long bits = get_mode_size_bits(env->mode);
1034 if (is_Proj(pred_pred)) {
1035 pred_pred = get_Proj_pred(pred_pred);
1038 if (is_ia32_Minus(pred_pred) &&
1039 tarval_is_long(tv) &&
1040 get_tarval_long(tv) == bits)
1042 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1043 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1050 rotate = gen_RotL(env, op1, op2);
1059 * Transforms a Minus node.
1061 * @param env The transformation environment
1062 * @param op The operator
1063 * @return The created ia32 Minus node
1065 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
1068 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1069 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1070 ir_node *nomem = new_rd_NoMem(env->irg);
1073 if (mode_is_float(env->mode)) {
1074 new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1076 size = get_mode_size_bits(env->mode);
1077 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1079 set_ia32_sc(new_op, name);
1081 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1083 set_ia32_res_mode(new_op, env->mode);
1085 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1088 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1097 * Transforms a Not node.
1099 * @param env The transformation environment
1100 * @param op The operator
1101 * @return The created ia32 Not node
1103 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) {
1106 if (mode_is_float(env->mode)) {
1110 new_op = gen_unop(env, op, new_rd_ia32_Not);
1119 * Transforms an Abs node.
1121 * @param env The transformation environment
1122 * @param op The operator
1123 * @return The created ia32 Abs node
1125 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
1126 ir_node *res, *p_eax, *p_edx;
1127 dbg_info *dbg = env->dbg;
1128 ir_mode *mode = env->mode;
1129 ir_graph *irg = env->irg;
1130 ir_node *block = env->block;
1131 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1132 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1133 ir_node *nomem = new_NoMem();
1137 if (mode_is_float(mode)) {
1138 res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1140 size = get_mode_size_bits(mode);
1141 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1143 set_ia32_sc(res, name);
1145 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1147 set_ia32_res_mode(res, mode);
1149 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1152 res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T);
1153 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1154 set_ia32_res_mode(res, mode);
1156 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
1157 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
1159 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T);
1160 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1161 set_ia32_res_mode(res, mode);
1163 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1165 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T);
1166 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1167 set_ia32_res_mode(res, mode);
1169 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1178 * Transforms a Load.
1180 * @param mod the debug module
1181 * @param block the block the new node should belong to
1182 * @param node the ir Load node
1183 * @param mode node mode
1184 * @return the created ia32 Load node
1186 static ir_node *gen_Load(ia32_transform_env_t *env) {
1187 ir_node *node = env->irn;
1188 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1191 if (mode_is_float(env->mode)) {
1192 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1195 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1198 set_ia32_am_support(new_op, ia32_am_Source);
1199 set_ia32_op_type(new_op, ia32_AddrModeS);
1200 set_ia32_am_flavour(new_op, ia32_B);
1201 set_ia32_ls_mode(new_op, get_Load_mode(node));
1203 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1211 * Transforms a Store.
1213 * @param mod the debug module
1214 * @param block the block the new node should belong to
1215 * @param node the ir Store node
1216 * @param mode node mode
1217 * @return the created ia32 Store node
1219 static ir_node *gen_Store(ia32_transform_env_t *env) {
1220 ir_node *node = env->irn;
1221 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1222 ir_node *val = get_Store_value(node);
1223 ir_node *ptr = get_Store_ptr(node);
1224 ir_node *mem = get_Store_mem(node);
1225 ir_node *sval = val;
1228 /* in case of storing a const -> make it an attribute */
1229 if (is_ia32_Cnst(val)) {
1233 if (mode_is_float(env->mode)) {
1234 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode);
1237 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode);
1240 /* stored const is an attribute (saves a register) */
1241 if (is_ia32_Cnst(val)) {
1242 set_ia32_Immop_attr(new_op, val);
1245 set_ia32_am_support(new_op, ia32_am_Dest);
1246 set_ia32_op_type(new_op, ia32_AddrModeD);
1247 set_ia32_am_flavour(new_op, ia32_B);
1248 set_ia32_ls_mode(new_op, get_irn_mode(val));
1250 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1258 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp or CondJmp_i
1260 * @param env The transformation environment
1261 * @return The transformed node.
1263 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1264 dbg_info *dbg = env->dbg;
1265 ir_graph *irg = env->irg;
1266 ir_node *block = env->block;
1267 ir_node *node = env->irn;
1268 ir_node *sel = get_Cond_selector(node);
1269 ir_mode *sel_mode = get_irn_mode(sel);
1270 ir_node *res = NULL;
1271 ir_node *pred = NULL;
1272 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1273 ir_node *nomem = new_NoMem();
1274 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1276 if (is_Proj(sel) && sel_mode == mode_b) {
1277 pred = get_Proj_pred(sel);
1279 /* get both compare operators */
1280 cmp_a = get_Cmp_left(pred);
1281 cmp_b = get_Cmp_right(pred);
1283 /* check if we can use a CondJmp with immediate */
1284 cnst = env->cg->opt.immops ? get_immediate_op(cmp_a, cmp_b) : NULL;
1285 expr = get_expr_op(cmp_a, cmp_b);
1288 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1289 set_ia32_Immop_attr(res, cnst);
1292 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1295 set_ia32_pncode(res, get_Proj_proj(sel));
1296 set_ia32_am_support(res, ia32_am_Source);
1299 res = new_rd_ia32_SwitchJmp(dbg, irg, block, sel, mode_T);
1300 set_ia32_pncode(res, get_Cond_defaultProj(node));
1303 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1311 * Transforms a CopyB node.
1313 * @param env The transformation environment
1314 * @return The transformed node.
1316 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1317 ir_node *res = NULL;
1318 dbg_info *dbg = env->dbg;
1319 ir_graph *irg = env->irg;
1320 ir_mode *mode = env->mode;
1321 ir_node *block = env->block;
1322 ir_node *node = env->irn;
1323 ir_node *src = get_CopyB_src(node);
1324 ir_node *dst = get_CopyB_dst(node);
1325 ir_node *mem = get_CopyB_mem(node);
1326 int size = get_type_size_bytes(get_CopyB_type(node));
1329 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1330 /* then we need the size explicitly in ECX. */
1331 if (size >= 16 * 4) {
1332 rem = size & 0x3; /* size % 4 */
1335 res = new_rd_ia32_Const(dbg, irg, block, mode_Is);
1336 set_ia32_op_type(res, ia32_Const);
1337 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1339 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1340 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1343 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1344 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1347 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1355 * Transforms a Mux node into CMov.
1357 * @param env The transformation environment
1358 * @return The transformed node.
1360 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1361 ir_node *node = env->irn;
1362 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1363 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1365 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1372 * Following conversion rules apply:
1376 * 1) n bit -> m bit n < m (upscale)
1378 * 2) n bit -> m bit n == m (sign change)
1380 * 3) n bit -> m bit n > m (downscale)
1381 * a) Un -> Um = AND Un, (1 << m) - 1
1382 * b) Sn -> Um same as a)
1383 * c) Un -> Sm same as a)
1384 * d) Sn -> Sm = ASHL Sn, (n - m); ASHR Sn, (n - m)
1388 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1392 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1393 * if target mode < 32bit: additional INT -> INT conversion (see above)
1397 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1400 static ir_node *gen_int_downscale_conv(ia32_transform_env_t *env, ir_node *op,
1401 ir_mode *src_mode, ir_mode *tgt_mode)
1403 int n = get_mode_size_bits(src_mode);
1404 int m = get_mode_size_bits(tgt_mode);
1405 dbg_info *dbg = env->dbg;
1406 ir_graph *irg = env->irg;
1407 ir_node *block = env->block;
1408 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1409 ir_node *nomem = new_rd_NoMem(irg);
1410 ir_node *new_op, *proj;
1412 assert(n > m && "downscale expected");
1414 if (mode_is_signed(src_mode) && mode_is_signed(tgt_mode)) {
1415 /* ASHL Sn, n - m */
1416 new_op = new_rd_ia32_Shl(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
1417 proj = new_rd_Proj(dbg, irg, block, new_op, src_mode, 0);
1418 set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
1419 set_ia32_am_support(new_op, ia32_am_Source);
1420 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1422 /* ASHR Sn, n - m */
1423 new_op = new_rd_ia32_Shrs(dbg, irg, block, noreg, noreg, proj, noreg, nomem, mode_T);
1424 set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
1427 new_op = new_rd_ia32_And(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
1428 set_ia32_Immop_tarval(new_op, new_tarval_from_long((1 << m) - 1, mode_Is));
1435 * Transforms a Conv node.
1437 * @param env The transformation environment
1438 * @param op The operator
1439 * @return The created ia32 Conv node
1441 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
1442 dbg_info *dbg = env->dbg;
1443 ir_graph *irg = env->irg;
1444 ir_mode *src_mode = get_irn_mode(op);
1445 ir_mode *tgt_mode = env->mode;
1446 ir_node *block = env->block;
1447 ir_node *new_op = NULL;
1448 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1449 ir_node *nomem = new_rd_NoMem(irg);
1450 firm_dbg_module_t *mod = env->mod;
1453 if (src_mode == tgt_mode) {
1454 /* this can happen when changing mode_P to mode_Is */
1455 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1456 edges_reroute(env->irn, op, irg);
1458 else if (mode_is_float(src_mode)) {
1459 /* we convert from float ... */
1460 if (mode_is_float(tgt_mode)) {
1462 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1463 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1467 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1468 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1469 /* if target mode is not int: add an additional downscale convert */
1470 if (get_mode_size_bits(tgt_mode) < 32) {
1471 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1472 set_ia32_res_mode(new_op, tgt_mode);
1473 set_ia32_am_support(new_op, ia32_am_Source);
1475 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
1476 new_op = gen_int_downscale_conv(env, proj, src_mode, tgt_mode);
1481 /* we convert from int ... */
1482 if (mode_is_float(tgt_mode)) {
1484 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1485 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1489 if (get_mode_size_bits(src_mode) <= get_mode_size_bits(tgt_mode)) {
1490 DB((mod, LEVEL_1, "omitting upscale Conv(%+F, %+F) ...", src_mode, tgt_mode));
1491 edges_reroute(env->irn, op, irg);
1494 DB((mod, LEVEL_1, "create downscale Conv(%+F, %+F) ...", src_mode, tgt_mode));
1495 new_op = gen_int_downscale_conv(env, op, src_mode, tgt_mode);
1501 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1502 set_ia32_res_mode(new_op, tgt_mode);
1504 set_ia32_am_support(new_op, ia32_am_Source);
1506 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
1514 /********************************************
1517 * | |__ ___ _ __ ___ __| | ___ ___
1518 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1519 * | |_) | __/ | | | (_) | (_| | __/\__ \
1520 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1522 ********************************************/
1524 static ir_node *gen_StackParam(ia32_transform_env_t *env) {
1525 ir_node *new_op = NULL;
1526 ir_node *node = env->irn;
1527 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1528 ir_node *mem = new_rd_NoMem(env->irg);
1529 ir_node *ptr = get_irn_n(node, 0);
1530 entity *ent = be_get_frame_entity(node);
1531 ir_mode *mode = env->mode;
1533 if (mode_is_float(mode)) {
1534 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1537 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1540 set_ia32_frame_ent(new_op, ent);
1541 set_ia32_use_frame(new_op);
1543 set_ia32_am_support(new_op, ia32_am_Source);
1544 set_ia32_op_type(new_op, ia32_AddrModeS);
1545 set_ia32_am_flavour(new_op, ia32_B);
1546 set_ia32_ls_mode(new_op, mode);
1548 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1550 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
1554 * Transforms a FrameAddr into an ia32 Add.
1556 static ir_node *gen_FrameAddr(ia32_transform_env_t *env) {
1557 ir_node *new_op = NULL;
1558 ir_node *node = env->irn;
1559 ir_node *op = get_irn_n(node, 0);
1560 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1561 ir_node *nomem = new_rd_NoMem(env->irg);
1563 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem, mode_T);
1564 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1565 set_ia32_am_support(new_op, ia32_am_Full);
1566 set_ia32_use_frame(new_op);
1568 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1570 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1574 * Transforms a FrameLoad into an ia32 Load.
1576 static ir_node *gen_FrameLoad(ia32_transform_env_t *env) {
1577 ir_node *new_op = NULL;
1578 ir_node *node = env->irn;
1579 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1580 ir_node *mem = get_irn_n(node, 0);
1581 ir_node *ptr = get_irn_n(node, 1);
1582 entity *ent = be_get_frame_entity(node);
1583 ir_mode *mode = get_type_mode(get_entity_type(ent));
1585 if (mode_is_float(mode)) {
1586 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1589 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1592 set_ia32_frame_ent(new_op, ent);
1593 set_ia32_use_frame(new_op);
1595 set_ia32_am_support(new_op, ia32_am_Source);
1596 set_ia32_op_type(new_op, ia32_AddrModeS);
1597 set_ia32_am_flavour(new_op, ia32_B);
1598 set_ia32_ls_mode(new_op, mode);
1600 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1607 * Transforms a FrameStore into an ia32 Store.
1609 static ir_node *gen_FrameStore(ia32_transform_env_t *env) {
1610 ir_node *new_op = NULL;
1611 ir_node *node = env->irn;
1612 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1613 ir_node *mem = get_irn_n(node, 0);
1614 ir_node *ptr = get_irn_n(node, 1);
1615 ir_node *val = get_irn_n(node, 2);
1616 entity *ent = be_get_frame_entity(node);
1617 ir_mode *mode = get_irn_mode(val);
1619 if (mode_is_float(mode)) {
1620 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1623 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1626 set_ia32_frame_ent(new_op, ent);
1627 set_ia32_use_frame(new_op);
1629 set_ia32_am_support(new_op, ia32_am_Dest);
1630 set_ia32_op_type(new_op, ia32_AddrModeD);
1631 set_ia32_am_flavour(new_op, ia32_B);
1632 set_ia32_ls_mode(new_op, mode);
1634 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1641 /*********************************************************
1644 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1645 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1646 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1647 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1649 *********************************************************/
1652 * Transforms a Sub or fSub into Neg--Add iff OUT_REG == SRC2_REG.
1653 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
1655 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
1656 ia32_transform_env_t tenv;
1657 ir_node *in1, *in2, *noreg, *nomem, *res;
1658 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
1660 /* Return if AM node or not a Sub or fSub */
1661 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_fSub(irn)))
1664 noreg = ia32_new_NoReg_gp(cg);
1665 nomem = new_rd_NoMem(cg->irg);
1666 in1 = get_irn_n(irn, 2);
1667 in2 = get_irn_n(irn, 3);
1668 in1_reg = arch_get_irn_register(cg->arch_env, in1);
1669 in2_reg = arch_get_irn_register(cg->arch_env, in2);
1670 out_reg = get_ia32_out_reg(irn, 0);
1672 tenv.block = get_nodes_block(irn);
1673 tenv.dbg = get_irn_dbg_info(irn);
1677 tenv.mode = get_ia32_res_mode(irn);
1680 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
1681 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
1682 /* generate the neg src2 */
1683 res = gen_Minus(&tenv, in2);
1684 arch_set_irn_register(cg->arch_env, res, in2_reg);
1686 /* add to schedule */
1687 sched_add_before(irn, res);
1689 /* generate the add */
1690 if (mode_is_float(tenv.mode)) {
1691 res = new_rd_ia32_fAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
1694 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
1697 SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv));
1699 slots = get_ia32_slots(res);
1702 /* add to schedule */
1703 sched_add_before(irn, res);
1705 /* remove the old sub */
1708 /* exchange the add and the sub */
1714 * Transforms the given firm node (and maybe some other related nodes)
1715 * into one or more assembler nodes.
1717 * @param node the firm node
1718 * @param env the debug module
1720 void ia32_transform_node(ir_node *node, void *env) {
1721 ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env;
1722 opcode code = get_irn_opcode(node);
1723 ir_node *asm_node = NULL;
1724 ia32_transform_env_t tenv;
1729 tenv.block = get_nodes_block(node);
1730 tenv.dbg = get_irn_dbg_info(node);
1731 tenv.irg = current_ir_graph;
1733 tenv.mod = cgenv->mod;
1734 tenv.mode = get_irn_mode(node);
1737 #define UNOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_op(node)); break
1738 #define BINOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_left(node), get_##a##_right(node)); break
1739 #define GEN(a) case iro_##a: asm_node = gen_##a(&tenv); break
1740 #define IGN(a) case iro_##a: break
1741 #define BAD(a) case iro_##a: goto bad
1742 #define OTHER_BIN(a) \
1743 if (get_irn_op(node) == get_op_##a()) { \
1744 asm_node = gen_##a(&tenv, get_irn_n(node, 0), get_irn_n(node, 1)); \
1748 if (be_is_##a(node)) { \
1749 asm_node = gen_##a(&tenv); \
1753 DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
1800 /* constant transformation happens earlier */
1830 fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
1834 /* exchange nodes if a new one was generated */
1836 exchange(node, asm_node);
1837 DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
1840 DB((tenv.mod, LEVEL_1, "ignored\n"));