2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_map_regs.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
67 #include "gen_ia32_regalloc_if.h"
69 #define SFP_SIGN "0x80000000"
70 #define DFP_SIGN "0x8000000000000000"
71 #define SFP_ABS "0x7FFFFFFF"
72 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
74 #define TP_SFP_SIGN "ia32_sfp_sign"
75 #define TP_DFP_SIGN "ia32_dfp_sign"
76 #define TP_SFP_ABS "ia32_sfp_abs"
77 #define TP_DFP_ABS "ia32_dfp_abs"
79 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
80 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
81 #define ENT_SFP_ABS "IA32_SFP_ABS"
82 #define ENT_DFP_ABS "IA32_DFP_ABS"
84 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
85 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
87 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 /** hold the current code generator during transformation */
90 static ia32_code_gen_t *env_cg = NULL;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
119 static ir_node *create_immediate_or_transform(ir_node *node,
120 char immediate_constraint_type);
123 * Return true if a mode can be stored in the GP register set
125 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
126 if(mode == mode_fpcw)
128 return mode_is_int(mode) || mode_is_character(mode)
129 || mode_is_reference(mode) || mode == mode_b;
133 * Returns 1 if irn is a Const representing 0, 0 otherwise
135 static INLINE int is_ia32_Const_0(ir_node *irn) {
136 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
137 && tarval_is_null(get_ia32_Immop_tarval(irn));
141 * Returns 1 if irn is a Const representing 1, 0 otherwise
143 static INLINE int is_ia32_Const_1(ir_node *irn) {
144 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
145 && tarval_is_one(get_ia32_Immop_tarval(irn));
149 * Collects all Projs of a node into the node array. Index is the projnum.
150 * BEWARE: The caller has to assure the appropriate array size!
152 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
153 const ir_edge_t *edge;
154 assert(get_irn_mode(irn) == mode_T && "need mode_T");
156 memset(projs, 0, size * sizeof(projs[0]));
158 foreach_out_edge(irn, edge) {
159 ir_node *proj = get_edge_src_irn(edge);
160 int proj_proj = get_Proj_proj(proj);
161 assert(proj_proj < size);
162 projs[proj_proj] = proj;
167 * Renumbers the proj having pn_old in the array tp pn_new
168 * and removes the proj from the array.
170 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
171 fprintf(stderr, "Warning: renumber_Proj used!\n");
173 set_Proj_proj(projs[pn_old], pn_new);
174 projs[pn_old] = NULL;
179 * creates a unique ident by adding a number to a tag
181 * @param tag the tag string, must contain a %d if a number
184 static ident *unique_id(const char *tag)
186 static unsigned id = 0;
189 snprintf(str, sizeof(str), tag, ++id);
190 return new_id_from_str(str);
194 * Get a primitive type for a mode.
196 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
198 pmap_entry *e = pmap_find(types, mode);
203 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
204 res = new_type_primitive(new_id_from_str(buf), mode);
205 set_type_alignment_bytes(res, 16);
206 pmap_insert(types, mode, res);
214 * Get an entity that is initialized with a tarval
216 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
218 tarval *tv = get_Const_tarval(cnst);
219 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
224 ir_mode *mode = get_irn_mode(cnst);
225 ir_type *tp = get_Const_type(cnst);
226 if (tp == firm_unknown_type)
227 tp = get_prim_type(cg->isa->types, mode);
229 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
231 set_entity_ld_ident(res, get_entity_ident(res));
232 set_entity_visibility(res, visibility_local);
233 set_entity_variability(res, variability_constant);
234 set_entity_allocation(res, allocation_static);
236 /* we create a new entity here: It's initialization must resist on the
238 rem = current_ir_graph;
239 current_ir_graph = get_const_code_irg();
240 set_atomic_ent_value(res, new_Const_type(tv, tp));
241 current_ir_graph = rem;
243 pmap_insert(cg->isa->tv_ent, tv, res);
251 static int is_Const_0(ir_node *node) {
255 return classify_Const(node) == CNST_NULL;
258 static int is_Const_1(ir_node *node) {
262 return classify_Const(node) == CNST_ONE;
266 * Transforms a Const.
268 static ir_node *gen_Const(ir_node *node) {
269 ir_graph *irg = current_ir_graph;
270 ir_node *block = be_transform_node(get_nodes_block(node));
271 dbg_info *dbgi = get_irn_dbg_info(node);
272 ir_mode *mode = get_irn_mode(node);
274 if (mode_is_float(mode)) {
276 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
277 ir_node *nomem = new_NoMem();
282 if (! USE_SSE2(env_cg)) {
283 cnst_classify_t clss = classify_Const(node);
285 if (clss == CNST_NULL) {
286 load = new_rd_ia32_vfldz(dbgi, irg, block);
288 } else if (clss == CNST_ONE) {
289 load = new_rd_ia32_vfld1(dbgi, irg, block);
292 floatent = get_entity_for_tv(env_cg, node);
294 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
295 set_ia32_op_type(load, ia32_AddrModeS);
296 set_ia32_am_flavour(load, ia32_am_N);
297 set_ia32_am_sc(load, floatent);
298 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
299 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
301 set_ia32_ls_mode(load, mode);
303 floatent = get_entity_for_tv(env_cg, node);
305 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
306 set_ia32_op_type(load, ia32_AddrModeS);
307 set_ia32_am_flavour(load, ia32_am_N);
308 set_ia32_am_sc(load, floatent);
309 set_ia32_ls_mode(load, mode);
310 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
312 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
315 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
317 /* Const Nodes before the initial IncSP are a bad idea, because
318 * they could be spilled and we have no SP ready at that point yet.
319 * So add a dependency to the initial frame pointer calculation to
320 * avoid that situation.
322 if (get_irg_start_block(irg) == block) {
323 add_irn_dep(load, get_irg_frame(irg));
326 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
329 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
332 if (get_irg_start_block(irg) == block) {
333 add_irn_dep(cnst, get_irg_frame(irg));
336 set_ia32_Const_attr(cnst, node);
337 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
342 return new_r_Bad(irg);
346 * Transforms a SymConst.
348 static ir_node *gen_SymConst(ir_node *node) {
349 ir_graph *irg = current_ir_graph;
350 ir_node *block = be_transform_node(get_nodes_block(node));
351 dbg_info *dbgi = get_irn_dbg_info(node);
352 ir_mode *mode = get_irn_mode(node);
355 if (mode_is_float(mode)) {
357 if (USE_SSE2(env_cg))
358 cnst = new_rd_ia32_xConst(dbgi, irg, block);
360 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
361 //set_ia32_ls_mode(cnst, mode);
362 set_ia32_ls_mode(cnst, mode_E);
364 cnst = new_rd_ia32_Const(dbgi, irg, block);
367 /* Const Nodes before the initial IncSP are a bad idea, because
368 * they could be spilled and we have no SP ready at that point yet
370 if (get_irg_start_block(irg) == block) {
371 add_irn_dep(cnst, get_irg_frame(irg));
374 set_ia32_Const_attr(cnst, node);
375 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
380 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
381 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
382 static const struct {
384 const char *ent_name;
385 const char *cnst_str;
386 } names [ia32_known_const_max] = {
387 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
388 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
389 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
390 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
392 static ir_entity *ent_cache[ia32_known_const_max];
394 const char *tp_name, *ent_name, *cnst_str;
402 ent_name = names[kct].ent_name;
403 if (! ent_cache[kct]) {
404 tp_name = names[kct].tp_name;
405 cnst_str = names[kct].cnst_str;
407 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
409 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
410 tp = new_type_primitive(new_id_from_str(tp_name), mode);
411 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
413 set_entity_ld_ident(ent, get_entity_ident(ent));
414 set_entity_visibility(ent, visibility_local);
415 set_entity_variability(ent, variability_constant);
416 set_entity_allocation(ent, allocation_static);
418 /* we create a new entity here: It's initialization must resist on the
420 rem = current_ir_graph;
421 current_ir_graph = get_const_code_irg();
422 cnst = new_Const(mode, tv);
423 current_ir_graph = rem;
425 set_atomic_ent_value(ent, cnst);
427 /* cache the entry */
428 ent_cache[kct] = ent;
431 return ent_cache[kct];
436 * Prints the old node name on cg obst and returns a pointer to it.
438 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
439 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
441 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
442 obstack_1grow(isa->name_obst, 0);
443 return obstack_finish(isa->name_obst);
447 /* determine if one operator is an Imm */
448 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
450 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
452 return is_ia32_Cnst(op2) ? op2 : NULL;
456 /* determine if one operator is not an Imm */
457 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
458 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
461 static void fold_immediate(ir_node *node, int in1, int in2) {
465 if (!(env_cg->opt & IA32_OPT_IMMOPS))
468 left = get_irn_n(node, in1);
469 right = get_irn_n(node, in2);
470 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
471 /* we can only set right operand to immediate */
472 if(!is_ia32_commutative(node))
474 /* exchange left/right */
475 set_irn_n(node, in1, right);
476 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
477 copy_ia32_Immop_attr(node, left);
478 } else if(is_ia32_Cnst(right)) {
479 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
480 copy_ia32_Immop_attr(node, right);
485 clear_ia32_commutative(node);
486 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
487 get_ia32_am_arity(node));
491 * Construct a standard binary operation, set AM and immediate if required.
493 * @param op1 The first operand
494 * @param op2 The second operand
495 * @param func The node constructor function
496 * @return The constructed ia32 node.
498 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
499 construct_binop_func *func, int commutative)
501 ir_node *block = be_transform_node(get_nodes_block(node));
502 ir_graph *irg = current_ir_graph;
503 dbg_info *dbgi = get_irn_dbg_info(node);
504 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
505 ir_node *nomem = new_NoMem();
508 ir_node *new_op1 = be_transform_node(op1);
509 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
510 if (is_ia32_Immediate(new_op2)) {
514 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
515 if (func == new_rd_ia32_IMul) {
516 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
518 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
521 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
523 set_ia32_commutative(new_node);
530 * Construct a standard binary operation, set AM and immediate if required.
532 * @param op1 The first operand
533 * @param op2 The second operand
534 * @param func The node constructor function
535 * @return The constructed ia32 node.
537 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
538 construct_binop_func *func)
540 ir_node *block = be_transform_node(get_nodes_block(node));
541 ir_node *new_op1 = be_transform_node(op1);
542 ir_node *new_op2 = be_transform_node(op2);
543 ir_node *new_node = NULL;
544 dbg_info *dbgi = get_irn_dbg_info(node);
545 ir_graph *irg = current_ir_graph;
546 ir_mode *mode = get_irn_mode(node);
547 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
548 ir_node *nomem = new_NoMem();
550 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
552 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
553 if (is_op_commutative(get_irn_op(node))) {
554 set_ia32_commutative(new_node);
556 set_ia32_ls_mode(new_node, mode);
558 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
564 * Construct a standard binary operation, set AM and immediate if required.
566 * @param op1 The first operand
567 * @param op2 The second operand
568 * @param func The node constructor function
569 * @return The constructed ia32 node.
571 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
572 construct_binop_float_func *func)
574 ir_node *block = be_transform_node(get_nodes_block(node));
575 ir_node *new_op1 = be_transform_node(op1);
576 ir_node *new_op2 = be_transform_node(op2);
577 ir_node *new_node = NULL;
578 dbg_info *dbgi = get_irn_dbg_info(node);
579 ir_graph *irg = current_ir_graph;
580 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
581 ir_node *nomem = new_NoMem();
582 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
583 &ia32_fp_cw_regs[REG_FPCW]);
585 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
587 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
588 if (is_op_commutative(get_irn_op(node))) {
589 set_ia32_commutative(new_node);
592 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
598 * Construct a shift/rotate binary operation, sets AM and immediate if required.
600 * @param op1 The first operand
601 * @param op2 The second operand
602 * @param func The node constructor function
603 * @return The constructed ia32 node.
605 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
606 construct_binop_func *func)
608 ir_node *block = be_transform_node(get_nodes_block(node));
609 ir_node *new_op1 = be_transform_node(op1);
611 ir_node *new_op = NULL;
612 dbg_info *dbgi = get_irn_dbg_info(node);
613 ir_graph *irg = current_ir_graph;
614 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
615 ir_node *nomem = new_NoMem();
617 assert(! mode_is_float(get_irn_mode(node))
618 && "Shift/Rotate with float not supported");
620 new_op2 = create_immediate_or_transform(op2, 'N');
622 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
625 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
627 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
629 set_ia32_emit_cl(new_op);
636 * Construct a standard unary operation, set AM and immediate if required.
638 * @param op The operand
639 * @param func The node constructor function
640 * @return The constructed ia32 node.
642 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
644 ir_node *block = be_transform_node(get_nodes_block(node));
645 ir_node *new_op = be_transform_node(op);
646 ir_node *new_node = NULL;
647 ir_graph *irg = current_ir_graph;
648 dbg_info *dbgi = get_irn_dbg_info(node);
649 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
650 ir_node *nomem = new_NoMem();
652 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
653 DB((dbg, LEVEL_1, "INT unop ..."));
654 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
656 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
662 * Creates an ia32 Add.
664 * @return the created ia32 Add node
666 static ir_node *gen_Add(ir_node *node) {
667 ir_node *block = be_transform_node(get_nodes_block(node));
668 ir_node *op1 = get_Add_left(node);
669 ir_node *new_op1 = be_transform_node(op1);
670 ir_node *op2 = get_Add_right(node);
671 ir_node *new_op2 = be_transform_node(op2);
672 ir_node *new_op = NULL;
673 ir_graph *irg = current_ir_graph;
674 dbg_info *dbgi = get_irn_dbg_info(node);
675 ir_mode *mode = get_irn_mode(node);
676 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
677 ir_node *nomem = new_NoMem();
678 ir_node *expr_op, *imm_op;
680 /* Check if immediate optimization is on and */
681 /* if it's an operation with immediate. */
682 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
683 expr_op = get_expr_op(new_op1, new_op2);
685 assert((expr_op || imm_op) && "invalid operands");
687 if (mode_is_float(mode)) {
689 if (USE_SSE2(env_cg))
690 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
692 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
697 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
698 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
700 /* No expr_op means, that we have two const - one symconst and */
701 /* one tarval or another symconst - because this case is not */
702 /* covered by constant folding */
703 /* We need to check for: */
704 /* 1) symconst + const -> becomes a LEA */
705 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
706 /* linker doesn't support two symconsts */
708 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
709 /* this is the 2nd case */
710 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
711 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
712 set_ia32_am_flavour(new_op, ia32_am_B);
713 set_ia32_op_type(new_op, ia32_AddrModeS);
715 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
716 } else if (tp1 == ia32_ImmSymConst) {
717 tarval *tv = get_ia32_Immop_tarval(new_op2);
718 long offs = get_tarval_long(tv);
720 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
721 add_irn_dep(new_op, get_irg_frame(irg));
722 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
724 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
725 add_ia32_am_offs_int(new_op, offs);
726 set_ia32_am_flavour(new_op, ia32_am_OB);
727 set_ia32_op_type(new_op, ia32_AddrModeS);
728 } else if (tp2 == ia32_ImmSymConst) {
729 tarval *tv = get_ia32_Immop_tarval(new_op1);
730 long offs = get_tarval_long(tv);
732 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
733 add_irn_dep(new_op, get_irg_frame(irg));
734 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
736 add_ia32_am_offs_int(new_op, offs);
737 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
738 set_ia32_am_flavour(new_op, ia32_am_OB);
739 set_ia32_op_type(new_op, ia32_AddrModeS);
741 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
742 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
743 tarval *restv = tarval_add(tv1, tv2);
745 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
747 new_op = new_rd_ia32_Const(dbgi, irg, block);
748 set_ia32_Const_tarval(new_op, restv);
749 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
752 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
755 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
756 tarval_classification_t class_tv, class_negtv;
757 tarval *tv = get_ia32_Immop_tarval(imm_op);
759 /* optimize tarvals */
760 class_tv = classify_tarval(tv);
761 class_negtv = classify_tarval(tarval_neg(tv));
763 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
764 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
765 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
766 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
768 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
769 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
770 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
771 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
777 /* This is a normal add */
778 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
781 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
782 set_ia32_commutative(new_op);
784 fold_immediate(new_op, 2, 3);
786 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
792 * Creates an ia32 Mul.
794 * @return the created ia32 Mul node
796 static ir_node *gen_Mul(ir_node *node) {
797 ir_node *op1 = get_Mul_left(node);
798 ir_node *op2 = get_Mul_right(node);
799 ir_mode *mode = get_irn_mode(node);
801 if (mode_is_float(mode)) {
803 if (USE_SSE2(env_cg))
804 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
806 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
810 for the lower 32bit of the result it doesn't matter whether we use
811 signed or unsigned multiplication so we use IMul as it has fewer
814 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
818 * Creates an ia32 Mulh.
819 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
820 * this result while Mul returns the lower 32 bit.
822 * @return the created ia32 Mulh node
824 static ir_node *gen_Mulh(ir_node *node) {
825 ir_node *block = be_transform_node(get_nodes_block(node));
826 ir_node *op1 = get_irn_n(node, 0);
827 ir_node *new_op1 = be_transform_node(op1);
828 ir_node *op2 = get_irn_n(node, 1);
829 ir_node *new_op2 = be_transform_node(op2);
830 ir_graph *irg = current_ir_graph;
831 dbg_info *dbgi = get_irn_dbg_info(node);
832 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
833 ir_mode *mode = get_irn_mode(node);
834 ir_node *proj_EDX, *res;
836 assert(!mode_is_float(mode) && "Mulh with float not supported");
837 if (mode_is_signed(mode)) {
838 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
839 new_op2, new_NoMem());
841 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
845 set_ia32_commutative(res);
846 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
848 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
856 * Creates an ia32 And.
858 * @return The created ia32 And node
860 static ir_node *gen_And(ir_node *node) {
861 ir_node *op1 = get_And_left(node);
862 ir_node *op2 = get_And_right(node);
864 assert (! mode_is_float(get_irn_mode(node)));
865 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
871 * Creates an ia32 Or.
873 * @return The created ia32 Or node
875 static ir_node *gen_Or(ir_node *node) {
876 ir_node *op1 = get_Or_left(node);
877 ir_node *op2 = get_Or_right(node);
879 assert (! mode_is_float(get_irn_mode(node)));
880 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
886 * Creates an ia32 Eor.
888 * @return The created ia32 Eor node
890 static ir_node *gen_Eor(ir_node *node) {
891 ir_node *op1 = get_Eor_left(node);
892 ir_node *op2 = get_Eor_right(node);
894 assert(! mode_is_float(get_irn_mode(node)));
895 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
900 * Creates an ia32 Sub.
902 * @return The created ia32 Sub node
904 static ir_node *gen_Sub(ir_node *node) {
905 ir_node *block = be_transform_node(get_nodes_block(node));
906 ir_node *op1 = get_Sub_left(node);
907 ir_node *new_op1 = be_transform_node(op1);
908 ir_node *op2 = get_Sub_right(node);
909 ir_node *new_op2 = be_transform_node(op2);
910 ir_node *new_op = NULL;
911 ir_graph *irg = current_ir_graph;
912 dbg_info *dbgi = get_irn_dbg_info(node);
913 ir_mode *mode = get_irn_mode(node);
914 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
915 ir_node *nomem = new_NoMem();
916 ir_node *expr_op, *imm_op;
918 /* Check if immediate optimization is on and */
919 /* if it's an operation with immediate. */
920 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
921 expr_op = get_expr_op(new_op1, new_op2);
923 assert((expr_op || imm_op) && "invalid operands");
925 if (mode_is_float(mode)) {
927 if (USE_SSE2(env_cg))
928 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
930 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
935 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
936 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
938 /* No expr_op means, that we have two const - one symconst and */
939 /* one tarval or another symconst - because this case is not */
940 /* covered by constant folding */
941 /* We need to check for: */
942 /* 1) symconst - const -> becomes a LEA */
943 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
944 /* linker doesn't support two symconsts */
945 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
946 /* this is the 2nd case */
947 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
948 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
949 set_ia32_am_sc_sign(new_op);
950 set_ia32_am_flavour(new_op, ia32_am_B);
952 DBG_OPT_LEA3(op1, op2, node, new_op);
953 } else if (tp1 == ia32_ImmSymConst) {
954 tarval *tv = get_ia32_Immop_tarval(new_op2);
955 long offs = get_tarval_long(tv);
957 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
958 add_irn_dep(new_op, get_irg_frame(irg));
959 DBG_OPT_LEA3(op1, op2, node, new_op);
961 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
962 add_ia32_am_offs_int(new_op, -offs);
963 set_ia32_am_flavour(new_op, ia32_am_OB);
964 set_ia32_op_type(new_op, ia32_AddrModeS);
965 } else if (tp2 == ia32_ImmSymConst) {
966 tarval *tv = get_ia32_Immop_tarval(new_op1);
967 long offs = get_tarval_long(tv);
969 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
970 add_irn_dep(new_op, get_irg_frame(irg));
971 DBG_OPT_LEA3(op1, op2, node, new_op);
973 add_ia32_am_offs_int(new_op, offs);
974 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
975 set_ia32_am_sc_sign(new_op);
976 set_ia32_am_flavour(new_op, ia32_am_OB);
977 set_ia32_op_type(new_op, ia32_AddrModeS);
979 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
980 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
981 tarval *restv = tarval_sub(tv1, tv2);
983 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
985 new_op = new_rd_ia32_Const(dbgi, irg, block);
986 set_ia32_Const_tarval(new_op, restv);
987 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
990 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
993 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
994 tarval_classification_t class_tv, class_negtv;
995 tarval *tv = get_ia32_Immop_tarval(imm_op);
997 /* optimize tarvals */
998 class_tv = classify_tarval(tv);
999 class_negtv = classify_tarval(tarval_neg(tv));
1001 if (class_tv == TV_CLASSIFY_ONE) {
1002 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1003 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1004 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1006 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1007 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1008 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1009 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1015 /* This is a normal sub */
1016 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1018 /* set AM support */
1019 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1021 fold_immediate(new_op, 2, 3);
1023 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1031 * Generates an ia32 DivMod with additional infrastructure for the
1032 * register allocator if needed.
1034 * @param dividend -no comment- :)
1035 * @param divisor -no comment- :)
1036 * @param dm_flav flavour_Div/Mod/DivMod
1037 * @return The created ia32 DivMod node
1039 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1040 ir_node *divisor, ia32_op_flavour_t dm_flav)
1042 ir_node *block = be_transform_node(get_nodes_block(node));
1043 ir_node *new_dividend = be_transform_node(dividend);
1044 ir_node *new_divisor = be_transform_node(divisor);
1045 ir_graph *irg = current_ir_graph;
1046 dbg_info *dbgi = get_irn_dbg_info(node);
1047 ir_mode *mode = get_irn_mode(node);
1048 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1049 ir_node *res, *proj_div, *proj_mod;
1050 ir_node *sign_extension;
1051 ir_node *mem, *new_mem;
1052 ir_node *projs[pn_DivMod_max];
1055 ia32_collect_Projs(node, projs, pn_DivMod_max);
1057 proj_div = proj_mod = NULL;
1061 mem = get_Div_mem(node);
1062 mode = get_Div_resmode(node);
1063 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1064 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1067 mem = get_Mod_mem(node);
1068 mode = get_Mod_resmode(node);
1069 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1070 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1072 case flavour_DivMod:
1073 mem = get_DivMod_mem(node);
1074 mode = get_DivMod_resmode(node);
1075 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1076 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1077 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1080 panic("invalid divmod flavour!");
1082 new_mem = be_transform_node(mem);
1084 if (mode_is_signed(mode)) {
1085 /* in signed mode, we need to sign extend the dividend */
1086 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1088 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1089 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1091 add_irn_dep(sign_extension, get_irg_frame(irg));
1094 if (mode_is_signed(mode)) {
1095 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1096 sign_extension, new_divisor, new_mem, dm_flav);
1098 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1099 sign_extension, new_divisor, new_mem, dm_flav);
1102 set_ia32_exc_label(res, has_exc);
1103 set_irn_pinned(res, get_irn_pinned(node));
1104 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1106 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1113 * Wrapper for generate_DivMod. Sets flavour_Mod.
1116 static ir_node *gen_Mod(ir_node *node) {
1117 return generate_DivMod(node, get_Mod_left(node),
1118 get_Mod_right(node), flavour_Mod);
1122 * Wrapper for generate_DivMod. Sets flavour_Div.
1125 static ir_node *gen_Div(ir_node *node) {
1126 return generate_DivMod(node, get_Div_left(node),
1127 get_Div_right(node), flavour_Div);
1131 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1133 static ir_node *gen_DivMod(ir_node *node) {
1134 return generate_DivMod(node, get_DivMod_left(node),
1135 get_DivMod_right(node), flavour_DivMod);
1141 * Creates an ia32 floating Div.
1143 * @return The created ia32 xDiv node
1145 static ir_node *gen_Quot(ir_node *node) {
1146 ir_node *block = be_transform_node(get_nodes_block(node));
1147 ir_node *op1 = get_Quot_left(node);
1148 ir_node *new_op1 = be_transform_node(op1);
1149 ir_node *op2 = get_Quot_right(node);
1150 ir_node *new_op2 = be_transform_node(op2);
1151 ir_graph *irg = current_ir_graph;
1152 dbg_info *dbgi = get_irn_dbg_info(node);
1153 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1154 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1158 if (USE_SSE2(env_cg)) {
1159 ir_mode *mode = get_irn_mode(op1);
1160 if (is_ia32_xConst(new_op2)) {
1161 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1162 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1163 copy_ia32_Immop_attr(new_op, new_op2);
1165 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1166 // Matze: disabled for now, spillslot coalescer fails
1167 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1169 set_ia32_ls_mode(new_op, mode);
1171 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1172 &ia32_fp_cw_regs[REG_FPCW]);
1173 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1174 new_op2, nomem, fpcw);
1175 // Matze: disabled for now (spillslot coalescer fails)
1176 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1178 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1184 * Creates an ia32 Shl.
1186 * @return The created ia32 Shl node
1188 static ir_node *gen_Shl(ir_node *node) {
1189 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1196 * Creates an ia32 Shr.
1198 * @return The created ia32 Shr node
1200 static ir_node *gen_Shr(ir_node *node) {
1201 return gen_shift_binop(node, get_Shr_left(node),
1202 get_Shr_right(node), new_rd_ia32_Shr);
1208 * Creates an ia32 Sar.
1210 * @return The created ia32 Shrs node
1212 static ir_node *gen_Shrs(ir_node *node) {
1213 ir_node *left = get_Shrs_left(node);
1214 ir_node *right = get_Shrs_right(node);
1215 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1216 tarval *tv = get_Const_tarval(right);
1217 long val = get_tarval_long(tv);
1219 /* this is a sign extension */
1220 ir_graph *irg = current_ir_graph;
1221 dbg_info *dbgi = get_irn_dbg_info(node);
1222 ir_node *block = be_transform_node(get_nodes_block(node));
1224 ir_node *new_op = be_transform_node(op);
1226 return new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1230 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1236 * Creates an ia32 RotL.
1238 * @param op1 The first operator
1239 * @param op2 The second operator
1240 * @return The created ia32 RotL node
1242 static ir_node *gen_RotL(ir_node *node,
1243 ir_node *op1, ir_node *op2) {
1244 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1250 * Creates an ia32 RotR.
1251 * NOTE: There is no RotR with immediate because this would always be a RotL
1252 * "imm-mode_size_bits" which can be pre-calculated.
1254 * @param op1 The first operator
1255 * @param op2 The second operator
1256 * @return The created ia32 RotR node
1258 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1260 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1266 * Creates an ia32 RotR or RotL (depending on the found pattern).
1268 * @return The created ia32 RotL or RotR node
1270 static ir_node *gen_Rot(ir_node *node) {
1271 ir_node *rotate = NULL;
1272 ir_node *op1 = get_Rot_left(node);
1273 ir_node *op2 = get_Rot_right(node);
1275 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1276 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1277 that means we can create a RotR instead of an Add and a RotL */
1279 if (get_irn_op(op2) == op_Add) {
1281 ir_node *left = get_Add_left(add);
1282 ir_node *right = get_Add_right(add);
1283 if (is_Const(right)) {
1284 tarval *tv = get_Const_tarval(right);
1285 ir_mode *mode = get_irn_mode(node);
1286 long bits = get_mode_size_bits(mode);
1288 if (get_irn_op(left) == op_Minus &&
1289 tarval_is_long(tv) &&
1290 get_tarval_long(tv) == bits)
1292 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1293 rotate = gen_RotR(node, op1, get_Minus_op(left));
1298 if (rotate == NULL) {
1299 rotate = gen_RotL(node, op1, op2);
1308 * Transforms a Minus node.
1310 * @param op The Minus operand
1311 * @return The created ia32 Minus node
1313 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1314 ir_node *block = be_transform_node(get_nodes_block(node));
1315 ir_graph *irg = current_ir_graph;
1316 dbg_info *dbgi = get_irn_dbg_info(node);
1317 ir_mode *mode = get_irn_mode(node);
1322 if (mode_is_float(mode)) {
1323 ir_node *new_op = be_transform_node(op);
1325 if (USE_SSE2(env_cg)) {
1326 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1327 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1328 ir_node *nomem = new_rd_NoMem(irg);
1330 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1332 size = get_mode_size_bits(mode);
1333 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1335 set_ia32_am_sc(res, ent);
1336 set_ia32_op_type(res, ia32_AddrModeS);
1337 set_ia32_ls_mode(res, mode);
1339 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1342 res = gen_unop(node, op, new_rd_ia32_Neg);
1345 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1351 * Transforms a Minus node.
1353 * @return The created ia32 Minus node
1355 static ir_node *gen_Minus(ir_node *node) {
1356 return gen_Minus_ex(node, get_Minus_op(node));
1359 static ir_node *gen_bin_Not(ir_node *node)
1361 ir_graph *irg = current_ir_graph;
1362 dbg_info *dbgi = get_irn_dbg_info(node);
1363 ir_node *block = be_transform_node(get_nodes_block(node));
1364 ir_node *op = get_Not_op(node);
1365 ir_node *new_op = be_transform_node(op);
1366 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1367 ir_node *nomem = new_NoMem();
1368 ir_node *one = new_rd_ia32_Immediate(dbgi, irg, block, NULL, 0, 1);
1369 arch_set_irn_register(env_cg->arch_env, one, &ia32_gp_regs[REG_GP_NOREG]);
1371 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1375 * Transforms a Not node.
1377 * @return The created ia32 Not node
1379 static ir_node *gen_Not(ir_node *node) {
1380 ir_node *op = get_Not_op(node);
1381 ir_mode *mode = get_irn_mode(node);
1383 if(mode == mode_b) {
1384 return gen_bin_Not(node);
1387 assert (! mode_is_float(get_irn_mode(node)));
1388 return gen_unop(node, op, new_rd_ia32_Not);
1394 * Transforms an Abs node.
1396 * @return The created ia32 Abs node
1398 static ir_node *gen_Abs(ir_node *node) {
1399 ir_node *block = be_transform_node(get_nodes_block(node));
1400 ir_node *op = get_Abs_op(node);
1401 ir_node *new_op = be_transform_node(op);
1402 ir_graph *irg = current_ir_graph;
1403 dbg_info *dbgi = get_irn_dbg_info(node);
1404 ir_mode *mode = get_irn_mode(node);
1405 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1406 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1407 ir_node *nomem = new_NoMem();
1412 if (mode_is_float(mode)) {
1414 if (USE_SSE2(env_cg)) {
1415 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1417 size = get_mode_size_bits(mode);
1418 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1420 set_ia32_am_sc(res, ent);
1422 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1424 set_ia32_op_type(res, ia32_AddrModeS);
1425 set_ia32_ls_mode(res, mode);
1428 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1429 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1433 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1434 SET_IA32_ORIG_NODE(sign_extension,
1435 ia32_get_old_node_name(env_cg, node));
1437 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1438 sign_extension, nomem);
1439 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1441 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1442 sign_extension, nomem);
1443 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1452 * Transforms a Load.
1454 * @return the created ia32 Load node
1456 static ir_node *gen_Load(ir_node *node) {
1457 ir_node *block = be_transform_node(get_nodes_block(node));
1458 ir_node *ptr = get_Load_ptr(node);
1459 ir_node *new_ptr = be_transform_node(ptr);
1460 ir_node *mem = get_Load_mem(node);
1461 ir_node *new_mem = be_transform_node(mem);
1462 ir_graph *irg = current_ir_graph;
1463 dbg_info *dbgi = get_irn_dbg_info(node);
1464 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1465 ir_mode *mode = get_Load_mode(node);
1467 ir_node *lptr = new_ptr;
1470 ia32_am_flavour_t am_flav = ia32_am_B;
1472 /* address might be a constant (symconst or absolute address) */
1473 if (is_ia32_Const(new_ptr)) {
1478 if (mode_is_float(mode)) {
1480 if (USE_SSE2(env_cg)) {
1481 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1482 res_mode = mode_xmm;
1484 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1485 res_mode = mode_vfp;
1488 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1492 /* base is a constant address */
1494 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1495 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1496 am_flav = ia32_am_N;
1498 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1499 long offs = get_tarval_long(tv);
1501 add_ia32_am_offs_int(new_op, offs);
1502 am_flav = ia32_am_O;
1506 set_irn_pinned(new_op, get_irn_pinned(node));
1507 set_ia32_op_type(new_op, ia32_AddrModeS);
1508 set_ia32_am_flavour(new_op, am_flav);
1509 set_ia32_ls_mode(new_op, mode);
1511 /* make sure we are scheduled behind the initial IncSP/Barrier
1512 * to avoid spills being placed before it
1514 if (block == get_irg_start_block(irg)) {
1515 add_irn_dep(new_op, get_irg_frame(irg));
1518 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1519 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1527 * Transforms a Store.
1529 * @return the created ia32 Store node
1531 static ir_node *gen_Store(ir_node *node) {
1532 ir_node *block = be_transform_node(get_nodes_block(node));
1533 ir_node *ptr = get_Store_ptr(node);
1534 ir_node *new_ptr = be_transform_node(ptr);
1535 ir_node *val = get_Store_value(node);
1537 ir_node *mem = get_Store_mem(node);
1538 ir_node *new_mem = be_transform_node(mem);
1539 ir_graph *irg = current_ir_graph;
1540 dbg_info *dbgi = get_irn_dbg_info(node);
1541 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1542 ir_node *sptr = new_ptr;
1543 ir_mode *mode = get_irn_mode(val);
1546 ia32_am_flavour_t am_flav = ia32_am_B;
1548 /* address might be a constant (symconst or absolute address) */
1549 if (is_ia32_Const(new_ptr)) {
1554 if (mode_is_float(mode)) {
1557 new_val = be_transform_node(val);
1558 if (USE_SSE2(env_cg)) {
1559 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1562 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1566 new_val = create_immediate_or_transform(val, 0);
1568 if (get_mode_size_bits(mode) == 8) {
1569 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1572 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1577 /* base is an constant address */
1579 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1580 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1581 am_flav = ia32_am_N;
1583 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1584 long offs = get_tarval_long(tv);
1586 add_ia32_am_offs_int(new_op, offs);
1587 am_flav = ia32_am_O;
1591 set_irn_pinned(new_op, get_irn_pinned(node));
1592 set_ia32_op_type(new_op, ia32_AddrModeD);
1593 set_ia32_am_flavour(new_op, am_flav);
1594 set_ia32_ls_mode(new_op, mode);
1596 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1597 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1602 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1603 ir_node *cmp_left, ir_node *cmp_right)
1605 ir_node *new_cmp_left;
1606 ir_node *new_cmp_right;
1612 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1614 if(cmp_right != NULL && !is_Const_0(cmp_right))
1617 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1618 and_left = get_And_left(cmp_left);
1619 and_right = get_And_right(cmp_left);
1621 new_cmp_left = be_transform_node(and_left);
1622 new_cmp_right = create_immediate_or_transform(and_right, 0);
1624 new_cmp_left = be_transform_node(cmp_left);
1625 new_cmp_right = be_transform_node(cmp_left);
1628 noreg = ia32_new_NoReg_gp(env_cg);
1629 nomem = new_NoMem();
1631 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1632 new_cmp_left, new_cmp_right, nomem, pnc);
1633 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1638 static ir_node *create_Switch(ir_node *node)
1640 ir_graph *irg = current_ir_graph;
1641 dbg_info *dbgi = get_irn_dbg_info(node);
1642 ir_node *block = be_transform_node(get_nodes_block(node));
1643 ir_node *sel = get_Cond_selector(node);
1644 ir_node *new_sel = be_transform_node(sel);
1646 int switch_min = INT_MAX;
1647 const ir_edge_t *edge;
1649 /* determine the smallest switch case value */
1650 foreach_out_edge(node, edge) {
1651 ir_node *proj = get_edge_src_irn(edge);
1652 int pn = get_Proj_proj(proj);
1657 if (switch_min != 0) {
1658 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1660 /* if smallest switch case is not 0 we need an additional sub */
1661 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1662 add_ia32_am_offs_int(new_sel, -switch_min);
1663 set_ia32_am_flavour(new_sel, ia32_am_OB);
1664 set_ia32_op_type(new_sel, ia32_AddrModeS);
1666 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1669 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1670 set_ia32_pncode(res, get_Cond_defaultProj(node));
1672 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1678 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1680 * @return The transformed node.
1682 static ir_node *gen_Cond(ir_node *node) {
1683 ir_node *block = be_transform_node(get_nodes_block(node));
1684 ir_graph *irg = current_ir_graph;
1685 dbg_info *dbgi = get_irn_dbg_info(node);
1686 ir_node *sel = get_Cond_selector(node);
1687 ir_mode *sel_mode = get_irn_mode(sel);
1688 ir_node *res = NULL;
1689 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1696 ir_node *nomem = new_NoMem();
1699 if (sel_mode != mode_b) {
1700 return create_Switch(node);
1703 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
1704 /* it's some mode_b value not a direct comparison -> create a testjmp */
1705 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
1706 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1710 cmp = get_Proj_pred(sel);
1711 cmp_a = get_Cmp_left(cmp);
1712 cmp_b = get_Cmp_right(cmp);
1713 cmp_mode = get_irn_mode(cmp_a);
1714 pnc = get_Proj_proj(sel);
1715 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1716 pnc |= ia32_pn_Cmp_Unsigned;
1719 if(mode_needs_gp_reg(cmp_mode)) {
1720 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b);
1722 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1727 new_cmp_a = be_transform_node(cmp_a);
1728 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1730 if (mode_is_float(cmp_mode)) {
1732 if (USE_SSE2(env_cg)) {
1733 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1735 set_ia32_commutative(res);
1736 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1737 set_ia32_ls_mode(res, cmp_mode);
1739 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1740 set_ia32_commutative(res);
1743 assert(get_mode_size_bits(cmp_mode) == 32);
1744 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1745 new_cmp_a, new_cmp_b, nomem, pnc);
1746 set_ia32_commutative(res);
1747 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1750 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1758 * Transforms a CopyB node.
1760 * @return The transformed node.
1762 static ir_node *gen_CopyB(ir_node *node) {
1763 ir_node *block = be_transform_node(get_nodes_block(node));
1764 ir_node *src = get_CopyB_src(node);
1765 ir_node *new_src = be_transform_node(src);
1766 ir_node *dst = get_CopyB_dst(node);
1767 ir_node *new_dst = be_transform_node(dst);
1768 ir_node *mem = get_CopyB_mem(node);
1769 ir_node *new_mem = be_transform_node(mem);
1770 ir_node *res = NULL;
1771 ir_graph *irg = current_ir_graph;
1772 dbg_info *dbgi = get_irn_dbg_info(node);
1773 int size = get_type_size_bytes(get_CopyB_type(node));
1776 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1777 /* then we need the size explicitly in ECX. */
1778 if (size >= 32 * 4) {
1779 rem = size & 0x3; /* size % 4 */
1782 res = new_rd_ia32_Const(dbgi, irg, block);
1783 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1784 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1786 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1787 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1789 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1790 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1793 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1799 ir_node *gen_be_Copy(ir_node *node)
1801 ir_node *result = be_duplicate_node(node);
1802 ir_mode *mode = get_irn_mode(result);
1804 if (mode_needs_gp_reg(mode)) {
1805 set_irn_mode(result, mode_Iu);
1812 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1813 dbg_info *dbgi, ir_node *block)
1815 ir_graph *irg = current_ir_graph;
1816 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1817 ir_node *nomem = new_rd_NoMem(irg);
1818 ir_node *new_cmp_left;
1819 ir_node *new_cmp_right;
1822 /* can we use a test instruction? */
1823 if(cmp_right == NULL || is_Const_0(cmp_right)) {
1824 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1825 if(is_And(cmp_left) &&
1826 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1827 ir_node *and_left = get_And_left(cmp_left);
1828 ir_node *and_right = get_And_right(cmp_left);
1830 new_cmp_left = be_transform_node(and_left);
1831 new_cmp_right = create_immediate_or_transform(and_right, 0);
1833 new_cmp_left = be_transform_node(cmp_left);
1834 new_cmp_right = be_transform_node(cmp_left);
1837 res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
1838 new_cmp_left, new_cmp_right, nomem, pnc);
1839 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1844 new_cmp_left = be_transform_node(cmp_left);
1845 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1846 res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
1847 new_cmp_left, new_cmp_right, nomem, pnc);
1852 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1853 ir_node *val_true, ir_node *val_false,
1854 dbg_info *dbgi, ir_node *block)
1856 ir_graph *irg = current_ir_graph;
1857 ir_node *new_val_true = be_transform_node(val_true);
1858 ir_node *new_val_false = be_transform_node(val_false);
1859 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1860 ir_node *nomem = new_NoMem();
1861 ir_node *new_cmp_left;
1862 ir_node *new_cmp_right;
1865 /* cmovs with unknowns are pointless... */
1866 if(is_Unknown(val_true)) {
1867 #ifdef DEBUG_libfirm
1868 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1870 return new_val_false;
1872 if(is_Unknown(val_false)) {
1873 #ifdef DEBUG_libfirm
1874 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1876 return new_val_true;
1879 /* can we use a test instruction? */
1880 if(is_Const_0(cmp_right)) {
1881 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1882 if(is_And(cmp_left) &&
1883 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1884 ir_node *and_left = get_And_left(cmp_left);
1885 ir_node *and_right = get_And_right(cmp_left);
1887 new_cmp_left = be_transform_node(and_left);
1888 new_cmp_right = create_immediate_or_transform(and_right, 0);
1890 new_cmp_left = be_transform_node(cmp_left);
1891 new_cmp_right = be_transform_node(cmp_left);
1894 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, block, noreg, noreg,
1895 new_cmp_left, new_cmp_right, nomem,
1896 new_val_true, new_val_false, pnc);
1897 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1902 new_cmp_left = be_transform_node(cmp_left);
1903 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1905 res = new_rd_ia32_CmpCMov(dbgi, irg, block, noreg, noreg, new_cmp_left,
1906 new_cmp_right, nomem, new_val_true, new_val_false,
1908 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1915 * Transforms a Psi node into CMov.
1917 * @return The transformed node.
1919 static ir_node *gen_Psi(ir_node *node) {
1920 ir_node *psi_true = get_Psi_val(node, 0);
1921 ir_node *psi_default = get_Psi_default(node);
1922 ia32_code_gen_t *cg = env_cg;
1923 ir_node *cond = get_Psi_cond(node, 0);
1924 ir_node *block = be_transform_node(get_nodes_block(node));
1925 dbg_info *dbgi = get_irn_dbg_info(node);
1932 assert(get_Psi_n_conds(node) == 1);
1933 assert(get_irn_mode(cond) == mode_b);
1935 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
1936 /* a mode_b value, we have to compare it against 0 */
1938 cmp_right = new_Const_long(mode_Iu, 0);
1942 ir_node *cmp = get_Proj_pred(cond);
1944 cmp_left = get_Cmp_left(cmp);
1945 cmp_right = get_Cmp_right(cmp);
1946 cmp_mode = get_irn_mode(cmp_left);
1947 pnc = get_Proj_proj(cond);
1949 assert(!mode_is_float(cmp_mode));
1951 if (!mode_is_signed(cmp_mode)) {
1952 pnc |= ia32_pn_Cmp_Unsigned;
1956 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
1957 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
1958 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
1959 pnc = get_negated_pnc(pnc, cmp_mode);
1960 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
1962 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
1965 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1971 * Following conversion rules apply:
1975 * 1) n bit -> m bit n > m (downscale)
1977 * 2) n bit -> m bit n == m (sign change)
1979 * 3) n bit -> m bit n < m (upscale)
1980 * a) source is signed: movsx
1981 * b) source is unsigned: and with lower bits sets
1985 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1989 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1993 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1994 * x87 is mode_E internally, conversions happen only at load and store
1995 * in non-strict semantic
1999 * Create a conversion from x87 state register to general purpose.
2001 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2002 ir_node *block = be_transform_node(get_nodes_block(node));
2003 ir_node *op = get_Conv_op(node);
2004 ir_node *new_op = be_transform_node(op);
2005 ia32_code_gen_t *cg = env_cg;
2006 ir_graph *irg = current_ir_graph;
2007 dbg_info *dbgi = get_irn_dbg_info(node);
2008 ir_node *noreg = ia32_new_NoReg_gp(cg);
2009 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2010 ir_node *fist, *load;
2013 fist = new_rd_ia32_vfist(dbgi, irg, block,
2014 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2016 set_irn_pinned(fist, op_pin_state_floats);
2017 set_ia32_use_frame(fist);
2018 set_ia32_op_type(fist, ia32_AddrModeD);
2019 set_ia32_am_flavour(fist, ia32_am_B);
2020 set_ia32_ls_mode(fist, mode_Iu);
2021 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2024 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2026 set_irn_pinned(load, op_pin_state_floats);
2027 set_ia32_use_frame(load);
2028 set_ia32_op_type(load, ia32_AddrModeS);
2029 set_ia32_am_flavour(load, ia32_am_B);
2030 set_ia32_ls_mode(load, mode_Iu);
2031 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2033 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2037 * Create a conversion from general purpose to x87 register
2039 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2040 ir_node *block = be_transform_node(get_nodes_block(node));
2041 ir_node *op = get_Conv_op(node);
2042 ir_node *new_op = be_transform_node(op);
2043 ir_graph *irg = current_ir_graph;
2044 dbg_info *dbgi = get_irn_dbg_info(node);
2045 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2046 ir_node *nomem = new_NoMem();
2047 ir_node *fild, *store;
2050 /* first convert to 32 bit if necessary */
2051 src_bits = get_mode_size_bits(src_mode);
2052 if (src_bits == 8) {
2053 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2054 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2055 set_ia32_ls_mode(new_op, src_mode);
2056 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2057 } else if (src_bits < 32) {
2058 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2059 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2060 set_ia32_ls_mode(new_op, src_mode);
2061 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2065 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2067 set_ia32_use_frame(store);
2068 set_ia32_op_type(store, ia32_AddrModeD);
2069 set_ia32_am_flavour(store, ia32_am_OB);
2070 set_ia32_ls_mode(store, mode_Iu);
2073 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2075 set_ia32_use_frame(fild);
2076 set_ia32_op_type(fild, ia32_AddrModeS);
2077 set_ia32_am_flavour(fild, ia32_am_OB);
2078 set_ia32_ls_mode(fild, mode_Iu);
2080 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2083 static ir_node *create_Strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
2086 ir_node *block = get_nodes_block(node);
2087 ir_graph *irg = current_ir_graph;
2088 dbg_info *dbgi = get_irn_dbg_info(node);
2089 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2090 ir_node *nomem = new_NoMem();
2091 int src_bits = get_mode_size_bits(src_mode);
2092 int tgt_bits = get_mode_size_bits(tgt_mode);
2093 ir_node *frame = get_irg_frame(irg);
2094 ir_mode *smaller_mode;
2095 ir_node *store, *load;
2098 if(src_bits <= tgt_bits)
2099 smaller_mode = src_mode;
2101 smaller_mode = tgt_mode;
2103 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2105 set_ia32_use_frame(store);
2106 set_ia32_op_type(store, ia32_AddrModeD);
2107 set_ia32_am_flavour(store, ia32_am_OB);
2109 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2111 set_ia32_use_frame(load);
2112 set_ia32_op_type(load, ia32_AddrModeS);
2113 set_ia32_am_flavour(load, ia32_am_OB);
2115 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2120 * Transforms a Conv node.
2122 * @return The created ia32 Conv node
2124 static ir_node *gen_Conv(ir_node *node) {
2125 ir_node *block = be_transform_node(get_nodes_block(node));
2126 ir_node *op = get_Conv_op(node);
2127 ir_node *new_op = be_transform_node(op);
2128 ir_graph *irg = current_ir_graph;
2129 dbg_info *dbgi = get_irn_dbg_info(node);
2130 ir_mode *src_mode = get_irn_mode(op);
2131 ir_mode *tgt_mode = get_irn_mode(node);
2132 int src_bits = get_mode_size_bits(src_mode);
2133 int tgt_bits = get_mode_size_bits(tgt_mode);
2134 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2135 ir_node *nomem = new_rd_NoMem(irg);
2138 if (src_mode == mode_b) {
2139 assert(mode_is_int(tgt_mode));
2140 /* nothing to do, we already model bools as 0/1 ints */
2144 if (src_mode == tgt_mode) {
2145 if (get_Conv_strict(node)) {
2146 if (USE_SSE2(env_cg)) {
2147 /* when we are in SSE mode, we can kill all strict no-op conversion */
2151 /* this should be optimized already, but who knows... */
2152 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2153 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2158 if (mode_is_float(src_mode)) {
2159 /* we convert from float ... */
2160 if (mode_is_float(tgt_mode)) {
2161 if(src_mode == mode_E && tgt_mode == mode_D
2162 && !get_Conv_strict(node)) {
2163 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2168 if (USE_SSE2(env_cg)) {
2169 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2170 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2171 set_ia32_ls_mode(res, tgt_mode);
2173 // Matze: TODO what about strict convs?
2174 if(get_Conv_strict(node)) {
2175 res = create_Strict_conv(src_mode, tgt_mode, new_op);
2176 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2179 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2184 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2185 if (USE_SSE2(env_cg)) {
2186 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2187 set_ia32_ls_mode(res, src_mode);
2189 return gen_x87_fp_to_gp(node);
2193 /* we convert from int ... */
2194 if (mode_is_float(tgt_mode)) {
2197 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2198 if (USE_SSE2(env_cg)) {
2199 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2200 set_ia32_ls_mode(res, tgt_mode);
2201 if(src_bits == 32) {
2202 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2205 return gen_x87_gp_to_fp(node, src_mode);
2207 } else if(tgt_mode == mode_b) {
2209 res = create_set(pn_Cmp_Lg, op, NULL, dbgi, block);
2212 ir_mode *smaller_mode;
2215 if (src_bits == tgt_bits) {
2216 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2220 if (src_bits < tgt_bits) {
2221 smaller_mode = src_mode;
2222 smaller_bits = src_bits;
2224 smaller_mode = tgt_mode;
2225 smaller_bits = tgt_bits;
2228 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2229 if (smaller_bits == 8) {
2230 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2231 set_ia32_ls_mode(res, smaller_mode);
2233 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2234 set_ia32_ls_mode(res, smaller_mode);
2236 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2240 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2246 int check_immediate_constraint(long val, char immediate_constraint_type)
2248 switch (immediate_constraint_type) {
2252 return val >= 0 && val <= 32;
2254 return val >= 0 && val <= 63;
2256 return val >= -128 && val <= 127;
2258 return val == 0xff || val == 0xffff;
2260 return val >= 0 && val <= 3;
2262 return val >= 0 && val <= 255;
2264 return val >= 0 && val <= 127;
2268 panic("Invalid immediate constraint found");
2273 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2276 tarval *offset = NULL;
2277 int offset_sign = 0;
2279 ir_entity *symconst_ent = NULL;
2280 int symconst_sign = 0;
2282 ir_node *cnst = NULL;
2283 ir_node *symconst = NULL;
2289 mode = get_irn_mode(node);
2290 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2291 !mode_is_reference(mode)) {
2295 if(is_Minus(node)) {
2297 node = get_Minus_op(node);
2300 if(is_Const(node)) {
2303 offset_sign = minus;
2304 } else if(is_SymConst(node)) {
2307 symconst_sign = minus;
2308 } else if(is_Add(node)) {
2309 ir_node *left = get_Add_left(node);
2310 ir_node *right = get_Add_right(node);
2311 if(is_Const(left) && is_SymConst(right)) {
2314 symconst_sign = minus;
2315 offset_sign = minus;
2316 } else if(is_SymConst(left) && is_Const(right)) {
2319 symconst_sign = minus;
2320 offset_sign = minus;
2322 } else if(is_Sub(node)) {
2323 ir_node *left = get_Sub_left(node);
2324 ir_node *right = get_Sub_right(node);
2325 if(is_Const(left) && is_SymConst(right)) {
2328 symconst_sign = !minus;
2329 offset_sign = minus;
2330 } else if(is_SymConst(left) && is_Const(right)) {
2333 symconst_sign = minus;
2334 offset_sign = !minus;
2341 offset = get_Const_tarval(cnst);
2342 if(tarval_is_long(offset)) {
2343 val = get_tarval_long(offset);
2344 } else if(tarval_is_null(offset)) {
2347 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2352 if(!check_immediate_constraint(val, immediate_constraint_type))
2355 if(symconst != NULL) {
2356 if(immediate_constraint_type != 0) {
2357 /* we need full 32bits for symconsts */
2361 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2363 symconst_ent = get_SymConst_entity(symconst);
2365 if(cnst == NULL && symconst == NULL)
2368 if(offset_sign && offset != NULL) {
2369 offset = tarval_neg(offset);
2372 irg = current_ir_graph;
2373 dbgi = get_irn_dbg_info(node);
2374 block = get_irg_start_block(irg);
2375 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2377 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2379 /* make sure we don't schedule stuff before the barrier */
2380 add_irn_dep(res, get_irg_frame(irg));
2386 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2388 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2389 if (new_node == NULL) {
2390 new_node = be_transform_node(node);
2395 typedef struct constraint_t constraint_t;
2396 struct constraint_t {
2399 const arch_register_req_t **out_reqs;
2401 const arch_register_req_t *req;
2402 unsigned immediate_possible;
2403 char immediate_type;
2406 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2408 int immediate_possible = 0;
2409 char immediate_type = 0;
2410 unsigned limited = 0;
2411 const arch_register_class_t *cls = NULL;
2413 struct obstack *obst;
2414 arch_register_req_t *req;
2415 unsigned *limited_ptr;
2419 /* TODO: replace all the asserts with nice error messages */
2421 printf("Constraint: %s\n", c);
2431 assert(cls == NULL ||
2432 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2433 cls = &ia32_reg_classes[CLASS_ia32_gp];
2434 limited |= 1 << REG_EAX;
2437 assert(cls == NULL ||
2438 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2439 cls = &ia32_reg_classes[CLASS_ia32_gp];
2440 limited |= 1 << REG_EBX;
2443 assert(cls == NULL ||
2444 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2445 cls = &ia32_reg_classes[CLASS_ia32_gp];
2446 limited |= 1 << REG_ECX;
2449 assert(cls == NULL ||
2450 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2451 cls = &ia32_reg_classes[CLASS_ia32_gp];
2452 limited |= 1 << REG_EDX;
2455 assert(cls == NULL ||
2456 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2457 cls = &ia32_reg_classes[CLASS_ia32_gp];
2458 limited |= 1 << REG_EDI;
2461 assert(cls == NULL ||
2462 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2463 cls = &ia32_reg_classes[CLASS_ia32_gp];
2464 limited |= 1 << REG_ESI;
2467 case 'q': /* q means lower part of the regs only, this makes no
2468 * difference to Q for us (we only assigne whole registers) */
2469 assert(cls == NULL ||
2470 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2471 cls = &ia32_reg_classes[CLASS_ia32_gp];
2472 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2476 assert(cls == NULL ||
2477 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2478 cls = &ia32_reg_classes[CLASS_ia32_gp];
2479 limited |= 1 << REG_EAX | 1 << REG_EDX;
2482 assert(cls == NULL ||
2483 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2484 cls = &ia32_reg_classes[CLASS_ia32_gp];
2485 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2486 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2493 assert(cls == NULL);
2494 cls = &ia32_reg_classes[CLASS_ia32_gp];
2500 /* TODO: mark values so the x87 simulator knows about t and u */
2501 assert(cls == NULL);
2502 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2507 assert(cls == NULL);
2508 /* TODO: check that sse2 is supported */
2509 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2519 assert(!immediate_possible);
2520 immediate_possible = 1;
2521 immediate_type = *c;
2525 assert(!immediate_possible);
2526 immediate_possible = 1;
2530 assert(!immediate_possible && cls == NULL);
2531 immediate_possible = 1;
2532 cls = &ia32_reg_classes[CLASS_ia32_gp];
2545 assert(constraint->is_in && "can only specify same constraint "
2548 sscanf(c, "%d%n", &same_as, &p);
2555 case 'E': /* no float consts yet */
2556 case 'F': /* no float consts yet */
2557 case 's': /* makes no sense on x86 */
2558 case 'X': /* we can't support that in firm */
2562 case '<': /* no autodecrement on x86 */
2563 case '>': /* no autoincrement on x86 */
2564 case 'C': /* sse constant not supported yet */
2565 case 'G': /* 80387 constant not supported yet */
2566 case 'y': /* we don't support mmx registers yet */
2567 case 'Z': /* not available in 32 bit mode */
2568 case 'e': /* not available in 32 bit mode */
2569 assert(0 && "asm constraint not supported");
2572 assert(0 && "unknown asm constraint found");
2579 const arch_register_req_t *other_constr;
2581 assert(cls == NULL && "same as and register constraint not supported");
2582 assert(!immediate_possible && "same as and immediate constraint not "
2584 assert(same_as < constraint->n_outs && "wrong constraint number in "
2585 "same_as constraint");
2587 other_constr = constraint->out_reqs[same_as];
2589 req = obstack_alloc(obst, sizeof(req[0]));
2590 req->cls = other_constr->cls;
2591 req->type = arch_register_req_type_should_be_same;
2592 req->limited = NULL;
2593 req->other_same = pos;
2594 req->other_different = -1;
2596 /* switch constraints. This is because in firm we have same_as
2597 * constraints on the output constraints while in the gcc asm syntax
2598 * they are specified on the input constraints */
2599 constraint->req = other_constr;
2600 constraint->out_reqs[same_as] = req;
2601 constraint->immediate_possible = 0;
2605 if(immediate_possible && cls == NULL) {
2606 cls = &ia32_reg_classes[CLASS_ia32_gp];
2608 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2609 assert(cls != NULL);
2611 if(immediate_possible) {
2612 assert(constraint->is_in
2613 && "imeediates make no sense for output constraints");
2615 /* todo: check types (no float input on 'r' constrainted in and such... */
2617 irg = current_ir_graph;
2618 obst = get_irg_obstack(irg);
2621 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2622 limited_ptr = (unsigned*) (req+1);
2624 req = obstack_alloc(obst, sizeof(req[0]));
2626 memset(req, 0, sizeof(req[0]));
2629 req->type = arch_register_req_type_limited;
2630 *limited_ptr = limited;
2631 req->limited = limited_ptr;
2633 req->type = arch_register_req_type_normal;
2637 constraint->req = req;
2638 constraint->immediate_possible = immediate_possible;
2639 constraint->immediate_type = immediate_type;
2643 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2650 panic("Clobbers not supported yet");
2653 ir_node *gen_ASM(ir_node *node)
2656 ir_graph *irg = current_ir_graph;
2657 ir_node *block = be_transform_node(get_nodes_block(node));
2658 dbg_info *dbgi = get_irn_dbg_info(node);
2665 ia32_asm_attr_t *attr;
2666 const arch_register_req_t **out_reqs;
2667 const arch_register_req_t **in_reqs;
2668 struct obstack *obst;
2669 constraint_t parsed_constraint;
2671 /* assembler could contain float statements */
2674 /* transform inputs */
2675 arity = get_irn_arity(node);
2676 in = alloca(arity * sizeof(in[0]));
2677 memset(in, 0, arity * sizeof(in[0]));
2679 n_outs = get_ASM_n_output_constraints(node);
2680 n_clobbers = get_ASM_n_clobbers(node);
2681 out_arity = n_outs + n_clobbers;
2683 /* construct register constraints */
2684 obst = get_irg_obstack(irg);
2685 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2686 parsed_constraint.out_reqs = out_reqs;
2687 parsed_constraint.n_outs = n_outs;
2688 parsed_constraint.is_in = 0;
2689 for(i = 0; i < out_arity; ++i) {
2693 const ir_asm_constraint *constraint;
2694 constraint = & get_ASM_output_constraints(node) [i];
2695 c = get_id_str(constraint->constraint);
2696 parse_asm_constraint(i, &parsed_constraint, c);
2698 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2699 c = get_id_str(glob_id);
2700 parse_clobber(node, i, &parsed_constraint, c);
2702 out_reqs[i] = parsed_constraint.req;
2705 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2706 parsed_constraint.is_in = 1;
2707 for(i = 0; i < arity; ++i) {
2708 const ir_asm_constraint *constraint;
2712 constraint = & get_ASM_input_constraints(node) [i];
2713 constr_id = constraint->constraint;
2714 c = get_id_str(constr_id);
2715 parse_asm_constraint(i, &parsed_constraint, c);
2716 in_reqs[i] = parsed_constraint.req;
2718 if(parsed_constraint.immediate_possible) {
2719 ir_node *pred = get_irn_n(node, i);
2720 char imm_type = parsed_constraint.immediate_type;
2721 ir_node *immediate = try_create_Immediate(pred, imm_type);
2723 if(immediate != NULL) {
2729 /* transform inputs */
2730 for(i = 0; i < arity; ++i) {
2732 ir_node *transformed;
2737 pred = get_irn_n(node, i);
2738 transformed = be_transform_node(pred);
2739 in[i] = transformed;
2742 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2744 generic_attr = get_irn_generic_attr(res);
2745 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2746 attr->asm_text = get_ASM_text(node);
2747 set_ia32_out_req_all(res, out_reqs);
2748 set_ia32_in_req_all(res, in_reqs);
2750 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2755 /********************************************
2758 * | |__ ___ _ __ ___ __| | ___ ___
2759 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2760 * | |_) | __/ | | | (_) | (_| | __/\__ \
2761 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2763 ********************************************/
2765 static ir_node *gen_be_StackParam(ir_node *node) {
2766 ir_node *block = be_transform_node(get_nodes_block(node));
2767 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2768 ir_node *new_ptr = be_transform_node(ptr);
2769 ir_node *new_op = NULL;
2770 ir_graph *irg = current_ir_graph;
2771 dbg_info *dbgi = get_irn_dbg_info(node);
2772 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2773 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2774 ir_mode *load_mode = get_irn_mode(node);
2775 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2779 if (mode_is_float(load_mode)) {
2781 if (USE_SSE2(env_cg)) {
2782 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2783 pn_res = pn_ia32_xLoad_res;
2784 proj_mode = mode_xmm;
2786 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2787 pn_res = pn_ia32_vfld_res;
2788 proj_mode = mode_vfp;
2791 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2792 proj_mode = mode_Iu;
2793 pn_res = pn_ia32_Load_res;
2796 set_irn_pinned(new_op, op_pin_state_floats);
2797 set_ia32_frame_ent(new_op, ent);
2798 set_ia32_use_frame(new_op);
2800 set_ia32_op_type(new_op, ia32_AddrModeS);
2801 set_ia32_am_flavour(new_op, ia32_am_B);
2802 set_ia32_ls_mode(new_op, load_mode);
2803 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2805 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2807 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2811 * Transforms a FrameAddr into an ia32 Add.
2813 static ir_node *gen_be_FrameAddr(ir_node *node) {
2814 ir_node *block = be_transform_node(get_nodes_block(node));
2815 ir_node *op = be_get_FrameAddr_frame(node);
2816 ir_node *new_op = be_transform_node(op);
2817 ir_graph *irg = current_ir_graph;
2818 dbg_info *dbgi = get_irn_dbg_info(node);
2819 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2822 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2823 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2824 set_ia32_use_frame(res);
2825 set_ia32_am_flavour(res, ia32_am_OB);
2827 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2833 * Transforms a FrameLoad into an ia32 Load.
2835 static ir_node *gen_be_FrameLoad(ir_node *node) {
2836 ir_node *block = be_transform_node(get_nodes_block(node));
2837 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2838 ir_node *new_mem = be_transform_node(mem);
2839 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2840 ir_node *new_ptr = be_transform_node(ptr);
2841 ir_node *new_op = NULL;
2842 ir_graph *irg = current_ir_graph;
2843 dbg_info *dbgi = get_irn_dbg_info(node);
2844 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2845 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2846 ir_mode *mode = get_type_mode(get_entity_type(ent));
2847 ir_node *projs[pn_Load_max];
2849 ia32_collect_Projs(node, projs, pn_Load_max);
2851 if (mode_is_float(mode)) {
2853 if (USE_SSE2(env_cg)) {
2854 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2857 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2861 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2864 set_irn_pinned(new_op, op_pin_state_floats);
2865 set_ia32_frame_ent(new_op, ent);
2866 set_ia32_use_frame(new_op);
2868 set_ia32_op_type(new_op, ia32_AddrModeS);
2869 set_ia32_am_flavour(new_op, ia32_am_B);
2870 set_ia32_ls_mode(new_op, mode);
2871 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2873 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2880 * Transforms a FrameStore into an ia32 Store.
2882 static ir_node *gen_be_FrameStore(ir_node *node) {
2883 ir_node *block = be_transform_node(get_nodes_block(node));
2884 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2885 ir_node *new_mem = be_transform_node(mem);
2886 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2887 ir_node *new_ptr = be_transform_node(ptr);
2888 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2889 ir_node *new_val = be_transform_node(val);
2890 ir_node *new_op = NULL;
2891 ir_graph *irg = current_ir_graph;
2892 dbg_info *dbgi = get_irn_dbg_info(node);
2893 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2894 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2895 ir_mode *mode = get_irn_mode(val);
2897 if (mode_is_float(mode)) {
2899 if (USE_SSE2(env_cg)) {
2900 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2902 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2904 } else if (get_mode_size_bits(mode) == 8) {
2905 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2907 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2910 set_ia32_frame_ent(new_op, ent);
2911 set_ia32_use_frame(new_op);
2913 set_ia32_op_type(new_op, ia32_AddrModeD);
2914 set_ia32_am_flavour(new_op, ia32_am_B);
2915 set_ia32_ls_mode(new_op, mode);
2917 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2923 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2925 static ir_node *gen_be_Return(ir_node *node) {
2926 ir_graph *irg = current_ir_graph;
2927 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2928 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2929 ir_entity *ent = get_irg_entity(irg);
2930 ir_type *tp = get_entity_type(ent);
2935 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2936 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2939 int pn_ret_val, pn_ret_mem, arity, i;
2941 assert(ret_val != NULL);
2942 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
2943 return be_duplicate_node(node);
2946 res_type = get_method_res_type(tp, 0);
2948 if (! is_Primitive_type(res_type)) {
2949 return be_duplicate_node(node);
2952 mode = get_type_mode(res_type);
2953 if (! mode_is_float(mode)) {
2954 return be_duplicate_node(node);
2957 assert(get_method_n_ress(tp) == 1);
2959 pn_ret_val = get_Proj_proj(ret_val);
2960 pn_ret_mem = get_Proj_proj(ret_mem);
2962 /* get the Barrier */
2963 barrier = get_Proj_pred(ret_val);
2965 /* get result input of the Barrier */
2966 ret_val = get_irn_n(barrier, pn_ret_val);
2967 new_ret_val = be_transform_node(ret_val);
2969 /* get memory input of the Barrier */
2970 ret_mem = get_irn_n(barrier, pn_ret_mem);
2971 new_ret_mem = be_transform_node(ret_mem);
2973 frame = get_irg_frame(irg);
2975 dbgi = get_irn_dbg_info(barrier);
2976 block = be_transform_node(get_nodes_block(barrier));
2978 noreg = ia32_new_NoReg_gp(env_cg);
2980 /* store xmm0 onto stack */
2981 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
2982 set_ia32_ls_mode(sse_store, mode);
2983 set_ia32_op_type(sse_store, ia32_AddrModeD);
2984 set_ia32_use_frame(sse_store);
2985 set_ia32_am_flavour(sse_store, ia32_am_B);
2988 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
2989 set_ia32_ls_mode(fld, mode);
2990 set_ia32_op_type(fld, ia32_AddrModeS);
2991 set_ia32_use_frame(fld);
2992 set_ia32_am_flavour(fld, ia32_am_B);
2994 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
2995 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
2996 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2998 /* create a new barrier */
2999 arity = get_irn_arity(barrier);
3000 in = alloca(arity * sizeof(in[0]));
3001 for (i = 0; i < arity; ++i) {
3004 if (i == pn_ret_val) {
3006 } else if (i == pn_ret_mem) {
3009 ir_node *in = get_irn_n(barrier, i);
3010 new_in = be_transform_node(in);
3015 new_barrier = new_ir_node(dbgi, irg, block,
3016 get_irn_op(barrier), get_irn_mode(barrier),
3018 copy_node_attr(barrier, new_barrier);
3019 be_duplicate_deps(barrier, new_barrier);
3020 be_set_transformed_node(barrier, new_barrier);
3021 mark_irn_visited(barrier);
3023 /* transform normally */
3024 return be_duplicate_node(node);
3028 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3030 static ir_node *gen_be_AddSP(ir_node *node) {
3031 ir_node *block = be_transform_node(get_nodes_block(node));
3032 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3034 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3035 ir_node *new_sp = be_transform_node(sp);
3036 ir_graph *irg = current_ir_graph;
3037 dbg_info *dbgi = get_irn_dbg_info(node);
3038 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3039 ir_node *nomem = new_NoMem();
3042 new_sz = create_immediate_or_transform(sz, 0);
3044 /* ia32 stack grows in reverse direction, make a SubSP */
3045 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3047 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3048 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3054 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3056 static ir_node *gen_be_SubSP(ir_node *node) {
3057 ir_node *block = be_transform_node(get_nodes_block(node));
3058 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3060 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3061 ir_node *new_sp = be_transform_node(sp);
3062 ir_graph *irg = current_ir_graph;
3063 dbg_info *dbgi = get_irn_dbg_info(node);
3064 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3065 ir_node *nomem = new_NoMem();
3068 new_sz = create_immediate_or_transform(sz, 0);
3070 /* ia32 stack grows in reverse direction, make an AddSP */
3071 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3072 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3073 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3079 * This function just sets the register for the Unknown node
3080 * as this is not done during register allocation because Unknown
3081 * is an "ignore" node.
3083 static ir_node *gen_Unknown(ir_node *node) {
3084 ir_mode *mode = get_irn_mode(node);
3086 if (mode_is_float(mode)) {
3088 if (USE_SSE2(env_cg))
3089 return ia32_new_Unknown_xmm(env_cg);
3091 return ia32_new_Unknown_vfp(env_cg);
3092 } else if (mode_needs_gp_reg(mode)) {
3093 return ia32_new_Unknown_gp(env_cg);
3095 assert(0 && "unsupported Unknown-Mode");
3102 * Change some phi modes
3104 static ir_node *gen_Phi(ir_node *node) {
3105 ir_node *block = be_transform_node(get_nodes_block(node));
3106 ir_graph *irg = current_ir_graph;
3107 dbg_info *dbgi = get_irn_dbg_info(node);
3108 ir_mode *mode = get_irn_mode(node);
3111 if(mode_needs_gp_reg(mode)) {
3112 /* we shouldn't have any 64bit stuff around anymore */
3113 assert(get_mode_size_bits(mode) <= 32);
3114 /* all integer operations are on 32bit registers now */
3116 } else if(mode_is_float(mode)) {
3117 if (USE_SSE2(env_cg)) {
3124 /* phi nodes allow loops, so we use the old arguments for now
3125 * and fix this later */
3126 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3127 copy_node_attr(node, phi);
3128 be_duplicate_deps(node, phi);
3130 be_set_transformed_node(node, phi);
3131 be_enqueue_preds(node);
3136 /**********************************************************************
3139 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3140 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3141 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3142 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3144 **********************************************************************/
3146 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3148 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3151 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3152 ir_node *val, ir_node *mem);
3155 * Transforms a lowered Load into a "real" one.
3157 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3158 ir_node *block = be_transform_node(get_nodes_block(node));
3159 ir_node *ptr = get_irn_n(node, 0);
3160 ir_node *new_ptr = be_transform_node(ptr);
3161 ir_node *mem = get_irn_n(node, 1);
3162 ir_node *new_mem = be_transform_node(mem);
3163 ir_graph *irg = current_ir_graph;
3164 dbg_info *dbgi = get_irn_dbg_info(node);
3165 ir_mode *mode = get_ia32_ls_mode(node);
3166 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3170 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3171 lowering we have x87 nodes, so we need to enforce simulation.
3173 if (mode_is_float(mode)) {
3175 if (fp_unit == fp_x87)
3179 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3181 set_ia32_op_type(new_op, ia32_AddrModeS);
3182 set_ia32_am_flavour(new_op, ia32_am_OB);
3183 set_ia32_am_offs_int(new_op, 0);
3184 set_ia32_am_scale(new_op, 1);
3185 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3186 if (is_ia32_am_sc_sign(node))
3187 set_ia32_am_sc_sign(new_op);
3188 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3189 if (is_ia32_use_frame(node)) {
3190 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3191 set_ia32_use_frame(new_op);
3194 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3200 * Transforms a lowered Store into a "real" one.
3202 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3203 ir_node *block = be_transform_node(get_nodes_block(node));
3204 ir_node *ptr = get_irn_n(node, 0);
3205 ir_node *new_ptr = be_transform_node(ptr);
3206 ir_node *val = get_irn_n(node, 1);
3207 ir_node *new_val = be_transform_node(val);
3208 ir_node *mem = get_irn_n(node, 2);
3209 ir_node *new_mem = be_transform_node(mem);
3210 ir_graph *irg = current_ir_graph;
3211 dbg_info *dbgi = get_irn_dbg_info(node);
3212 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3213 ir_mode *mode = get_ia32_ls_mode(node);
3216 ia32_am_flavour_t am_flav = ia32_B;
3219 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3220 lowering we have x87 nodes, so we need to enforce simulation.
3222 if (mode_is_float(mode)) {
3224 if (fp_unit == fp_x87)
3228 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3230 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3232 add_ia32_am_offs_int(new_op, am_offs);
3235 set_ia32_op_type(new_op, ia32_AddrModeD);
3236 set_ia32_am_flavour(new_op, am_flav);
3237 set_ia32_ls_mode(new_op, mode);
3238 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3239 set_ia32_use_frame(new_op);
3241 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3248 * Transforms an ia32_l_XXX into a "real" XXX node
3250 * @param env The transformation environment
3251 * @return the created ia32 XXX node
3253 #define GEN_LOWERED_OP(op) \
3254 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3255 ir_mode *mode = get_irn_mode(node); \
3256 if (mode_is_float(mode)) \
3258 return gen_binop(node, get_binop_left(node), \
3259 get_binop_right(node), new_rd_ia32_##op,0); \
3262 #define GEN_LOWERED_x87_OP(op) \
3263 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3265 FORCE_x87(env_cg); \
3266 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3267 get_binop_right(node), new_rd_ia32_##op); \
3271 #define GEN_LOWERED_UNOP(op) \
3272 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3273 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3276 #define GEN_LOWERED_SHIFT_OP(op) \
3277 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3278 return gen_shift_binop(node, get_binop_left(node), \
3279 get_binop_right(node), new_rd_ia32_##op); \
3282 #define GEN_LOWERED_LOAD(op, fp_unit) \
3283 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3284 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3287 #define GEN_LOWERED_STORE(op, fp_unit) \
3288 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3289 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3296 GEN_LOWERED_OP(IMul)
3298 GEN_LOWERED_x87_OP(vfprem)
3299 GEN_LOWERED_x87_OP(vfmul)
3300 GEN_LOWERED_x87_OP(vfsub)
3302 GEN_LOWERED_UNOP(Neg)
3304 GEN_LOWERED_LOAD(vfild, fp_x87)
3305 GEN_LOWERED_LOAD(Load, fp_none)
3306 /*GEN_LOWERED_STORE(vfist, fp_x87)
3309 GEN_LOWERED_STORE(Store, fp_none)
3311 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3312 ir_node *block = be_transform_node(get_nodes_block(node));
3313 ir_node *left = get_binop_left(node);
3314 ir_node *new_left = be_transform_node(left);
3315 ir_node *right = get_binop_right(node);
3316 ir_node *new_right = be_transform_node(right);
3317 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3318 ir_graph *irg = current_ir_graph;
3319 dbg_info *dbgi = get_irn_dbg_info(node);
3320 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
3321 &ia32_fp_cw_regs[REG_FPCW]);
3324 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3325 new_right, new_NoMem(), fpcw);
3326 clear_ia32_commutative(vfdiv);
3327 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3329 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3337 * Transforms a l_MulS into a "real" MulS node.
3339 * @param env The transformation environment
3340 * @return the created ia32 Mul node
3342 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3343 ir_node *block = be_transform_node(get_nodes_block(node));
3344 ir_node *left = get_binop_left(node);
3345 ir_node *new_left = be_transform_node(left);
3346 ir_node *right = get_binop_right(node);
3347 ir_node *new_right = be_transform_node(right);
3348 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3349 ir_graph *irg = current_ir_graph;
3350 dbg_info *dbgi = get_irn_dbg_info(node);
3352 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3353 /* and then skip the result Proj, because all needed Projs are already there. */
3354 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3355 new_right, new_NoMem());
3356 clear_ia32_commutative(muls);
3357 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3359 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3364 GEN_LOWERED_SHIFT_OP(Shl)
3365 GEN_LOWERED_SHIFT_OP(Shr)
3366 GEN_LOWERED_SHIFT_OP(Sar)
3369 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3370 * op1 - target to be shifted
3371 * op2 - contains bits to be shifted into target
3373 * Only op3 can be an immediate.
3375 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3376 ir_node *op2, ir_node *count)
3378 ir_node *block = be_transform_node(get_nodes_block(node));
3379 ir_node *new_op1 = be_transform_node(op1);
3380 ir_node *new_op2 = be_transform_node(op2);
3381 ir_node *new_count = be_transform_node(count);
3382 ir_node *new_op = NULL;
3383 ir_graph *irg = current_ir_graph;
3384 dbg_info *dbgi = get_irn_dbg_info(node);
3385 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3386 ir_node *nomem = new_NoMem();
3390 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3392 /* Check if immediate optimization is on and */
3393 /* if it's an operation with immediate. */
3394 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3396 /* Limit imm_op within range imm8 */
3398 tv = get_ia32_Immop_tarval(imm_op);
3401 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3402 set_ia32_Immop_tarval(imm_op, tv);
3409 /* integer operations */
3411 /* This is ShiftD with const */
3412 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3414 if (is_ia32_l_ShlD(node))
3415 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3416 new_op1, new_op2, noreg, nomem);
3418 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3419 new_op1, new_op2, noreg, nomem);
3420 copy_ia32_Immop_attr(new_op, imm_op);
3423 /* This is a normal ShiftD */
3424 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3425 if (is_ia32_l_ShlD(node))
3426 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3427 new_op1, new_op2, new_count, nomem);
3429 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3430 new_op1, new_op2, new_count, nomem);
3433 /* set AM support */
3434 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3436 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3438 set_ia32_emit_cl(new_op);
3443 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3444 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3445 get_irn_n(node, 1), get_irn_n(node, 2));
3448 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3449 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3450 get_irn_n(node, 1), get_irn_n(node, 2));
3454 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3456 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3457 ir_node *block = be_transform_node(get_nodes_block(node));
3458 ir_node *val = get_irn_n(node, 1);
3459 ir_node *new_val = be_transform_node(val);
3460 ia32_code_gen_t *cg = env_cg;
3461 ir_node *res = NULL;
3462 ir_graph *irg = current_ir_graph;
3464 ir_node *noreg, *new_ptr, *new_mem;
3471 mem = get_irn_n(node, 2);
3472 new_mem = be_transform_node(mem);
3473 ptr = get_irn_n(node, 0);
3474 new_ptr = be_transform_node(ptr);
3475 noreg = ia32_new_NoReg_gp(cg);
3476 dbgi = get_irn_dbg_info(node);
3478 /* Store x87 -> MEM */
3479 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3480 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3481 set_ia32_use_frame(res);
3482 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3483 set_ia32_am_flavour(res, ia32_B);
3484 set_ia32_op_type(res, ia32_AddrModeD);
3486 /* Load MEM -> SSE */
3487 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3488 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3489 set_ia32_use_frame(res);
3490 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3491 set_ia32_am_flavour(res, ia32_B);
3492 set_ia32_op_type(res, ia32_AddrModeS);
3493 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3499 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3501 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3502 ir_node *block = be_transform_node(get_nodes_block(node));
3503 ir_node *val = get_irn_n(node, 1);
3504 ir_node *new_val = be_transform_node(val);
3505 ia32_code_gen_t *cg = env_cg;
3506 ir_graph *irg = current_ir_graph;
3507 ir_node *res = NULL;
3508 ir_entity *fent = get_ia32_frame_ent(node);
3509 ir_mode *lsmode = get_ia32_ls_mode(node);
3511 ir_node *noreg, *new_ptr, *new_mem;
3515 if (! USE_SSE2(cg)) {
3516 /* SSE unit is not used -> skip this node. */
3520 ptr = get_irn_n(node, 0);
3521 new_ptr = be_transform_node(ptr);
3522 mem = get_irn_n(node, 2);
3523 new_mem = be_transform_node(mem);
3524 noreg = ia32_new_NoReg_gp(cg);
3525 dbgi = get_irn_dbg_info(node);
3527 /* Store SSE -> MEM */
3528 if (is_ia32_xLoad(skip_Proj(new_val))) {
3529 ir_node *ld = skip_Proj(new_val);
3531 /* we can vfld the value directly into the fpu */
3532 fent = get_ia32_frame_ent(ld);
3533 ptr = get_irn_n(ld, 0);
3534 offs = get_ia32_am_offs_int(ld);
3536 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3537 set_ia32_frame_ent(res, fent);
3538 set_ia32_use_frame(res);
3539 set_ia32_ls_mode(res, lsmode);
3540 set_ia32_am_flavour(res, ia32_B);
3541 set_ia32_op_type(res, ia32_AddrModeD);
3545 /* Load MEM -> x87 */
3546 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3547 set_ia32_frame_ent(res, fent);
3548 set_ia32_use_frame(res);
3549 add_ia32_am_offs_int(res, offs);
3550 set_ia32_am_flavour(res, ia32_B);
3551 set_ia32_op_type(res, ia32_AddrModeS);
3552 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3557 /*********************************************************
3560 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3561 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3562 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3563 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3565 *********************************************************/
3568 * the BAD transformer.
3570 static ir_node *bad_transform(ir_node *node) {
3571 panic("No transform function for %+F available.\n", node);
3576 * Transform the Projs of an AddSP.
3578 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3579 ir_node *block = be_transform_node(get_nodes_block(node));
3580 ir_node *pred = get_Proj_pred(node);
3581 ir_node *new_pred = be_transform_node(pred);
3582 ir_graph *irg = current_ir_graph;
3583 dbg_info *dbgi = get_irn_dbg_info(node);
3584 long proj = get_Proj_proj(node);
3586 if (proj == pn_be_AddSP_res) {
3587 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3588 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3590 } else if (proj == pn_be_AddSP_M) {
3591 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3595 return new_rd_Unknown(irg, get_irn_mode(node));
3599 * Transform the Projs of a SubSP.
3601 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3602 ir_node *block = be_transform_node(get_nodes_block(node));
3603 ir_node *pred = get_Proj_pred(node);
3604 ir_node *new_pred = be_transform_node(pred);
3605 ir_graph *irg = current_ir_graph;
3606 dbg_info *dbgi = get_irn_dbg_info(node);
3607 long proj = get_Proj_proj(node);
3609 if (proj == pn_be_SubSP_res) {
3610 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3611 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3613 } else if (proj == pn_be_SubSP_M) {
3614 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3618 return new_rd_Unknown(irg, get_irn_mode(node));
3622 * Transform and renumber the Projs from a Load.
3624 static ir_node *gen_Proj_Load(ir_node *node) {
3625 ir_node *block = be_transform_node(get_nodes_block(node));
3626 ir_node *pred = get_Proj_pred(node);
3627 ir_node *new_pred = be_transform_node(pred);
3628 ir_graph *irg = current_ir_graph;
3629 dbg_info *dbgi = get_irn_dbg_info(node);
3630 long proj = get_Proj_proj(node);
3632 /* renumber the proj */
3633 if (is_ia32_Load(new_pred)) {
3634 if (proj == pn_Load_res) {
3635 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3636 } else if (proj == pn_Load_M) {
3637 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3639 } else if (is_ia32_xLoad(new_pred)) {
3640 if (proj == pn_Load_res) {
3641 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3642 } else if (proj == pn_Load_M) {
3643 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3645 } else if (is_ia32_vfld(new_pred)) {
3646 if (proj == pn_Load_res) {
3647 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3648 } else if (proj == pn_Load_M) {
3649 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3654 return new_rd_Unknown(irg, get_irn_mode(node));
3658 * Transform and renumber the Projs from a DivMod like instruction.
3660 static ir_node *gen_Proj_DivMod(ir_node *node) {
3661 ir_node *block = be_transform_node(get_nodes_block(node));
3662 ir_node *pred = get_Proj_pred(node);
3663 ir_node *new_pred = be_transform_node(pred);
3664 ir_graph *irg = current_ir_graph;
3665 dbg_info *dbgi = get_irn_dbg_info(node);
3666 ir_mode *mode = get_irn_mode(node);
3667 long proj = get_Proj_proj(node);
3669 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3671 switch (get_irn_opcode(pred)) {
3675 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3677 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3685 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3687 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3695 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3696 case pn_DivMod_res_div:
3697 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3698 case pn_DivMod_res_mod:
3699 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3709 return new_rd_Unknown(irg, mode);
3713 * Transform and renumber the Projs from a CopyB.
3715 static ir_node *gen_Proj_CopyB(ir_node *node) {
3716 ir_node *block = be_transform_node(get_nodes_block(node));
3717 ir_node *pred = get_Proj_pred(node);
3718 ir_node *new_pred = be_transform_node(pred);
3719 ir_graph *irg = current_ir_graph;
3720 dbg_info *dbgi = get_irn_dbg_info(node);
3721 ir_mode *mode = get_irn_mode(node);
3722 long proj = get_Proj_proj(node);
3725 case pn_CopyB_M_regular:
3726 if (is_ia32_CopyB_i(new_pred)) {
3727 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3728 } else if (is_ia32_CopyB(new_pred)) {
3729 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3737 return new_rd_Unknown(irg, mode);
3741 * Transform and renumber the Projs from a vfdiv.
3743 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3744 ir_node *block = be_transform_node(get_nodes_block(node));
3745 ir_node *pred = get_Proj_pred(node);
3746 ir_node *new_pred = be_transform_node(pred);
3747 ir_graph *irg = current_ir_graph;
3748 dbg_info *dbgi = get_irn_dbg_info(node);
3749 ir_mode *mode = get_irn_mode(node);
3750 long proj = get_Proj_proj(node);
3753 case pn_ia32_l_vfdiv_M:
3754 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3755 case pn_ia32_l_vfdiv_res:
3756 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3761 return new_rd_Unknown(irg, mode);
3765 * Transform and renumber the Projs from a Quot.
3767 static ir_node *gen_Proj_Quot(ir_node *node) {
3768 ir_node *block = be_transform_node(get_nodes_block(node));
3769 ir_node *pred = get_Proj_pred(node);
3770 ir_node *new_pred = be_transform_node(pred);
3771 ir_graph *irg = current_ir_graph;
3772 dbg_info *dbgi = get_irn_dbg_info(node);
3773 ir_mode *mode = get_irn_mode(node);
3774 long proj = get_Proj_proj(node);
3778 if (is_ia32_xDiv(new_pred)) {
3779 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3780 } else if (is_ia32_vfdiv(new_pred)) {
3781 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3785 if (is_ia32_xDiv(new_pred)) {
3786 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3787 } else if (is_ia32_vfdiv(new_pred)) {
3788 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3796 return new_rd_Unknown(irg, mode);
3800 * Transform the Thread Local Storage Proj.
3802 static ir_node *gen_Proj_tls(ir_node *node) {
3803 ir_node *block = be_transform_node(get_nodes_block(node));
3804 ir_graph *irg = current_ir_graph;
3805 dbg_info *dbgi = NULL;
3806 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3812 * Transform the Projs from a be_Call.
3814 static ir_node *gen_Proj_be_Call(ir_node *node) {
3815 ir_node *block = be_transform_node(get_nodes_block(node));
3816 ir_node *call = get_Proj_pred(node);
3817 ir_node *new_call = be_transform_node(call);
3818 ir_graph *irg = current_ir_graph;
3819 dbg_info *dbgi = get_irn_dbg_info(node);
3820 long proj = get_Proj_proj(node);
3821 ir_mode *mode = get_irn_mode(node);
3823 const arch_register_class_t *cls;
3825 /* The following is kinda tricky: If we're using SSE, then we have to
3826 * move the result value of the call in floating point registers to an
3827 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3828 * after the call, we have to make sure to correctly make the
3829 * MemProj and the result Proj use these 2 nodes
3831 if (proj == pn_be_Call_M_regular) {
3832 // get new node for result, are we doing the sse load/store hack?
3833 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3834 ir_node *call_res_new;
3835 ir_node *call_res_pred = NULL;
3837 if (call_res != NULL) {
3838 call_res_new = be_transform_node(call_res);
3839 call_res_pred = get_Proj_pred(call_res_new);
3842 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3843 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3845 assert(is_ia32_xLoad(call_res_pred));
3846 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3849 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3851 ir_node *frame = get_irg_frame(irg);
3852 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3854 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3856 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3857 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3859 /* store st(0) onto stack */
3860 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3862 set_ia32_ls_mode(fstp, mode);
3863 set_ia32_op_type(fstp, ia32_AddrModeD);
3864 set_ia32_use_frame(fstp);
3865 set_ia32_am_flavour(fstp, ia32_am_B);
3867 /* load into SSE register */
3868 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3869 set_ia32_ls_mode(sse_load, mode);
3870 set_ia32_op_type(sse_load, ia32_AddrModeS);
3871 set_ia32_use_frame(sse_load);
3872 set_ia32_am_flavour(sse_load, ia32_am_B);
3874 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3876 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3878 /* get a Proj representing a caller save register */
3879 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3880 assert(is_Proj(p) && "Proj expected.");
3882 /* user of the the proj is the Keep */
3883 p = get_edge_src_irn(get_irn_out_edge_first(p));
3884 assert(be_is_Keep(p) && "Keep expected.");
3889 /* transform call modes */
3890 if (mode_is_data(mode)) {
3891 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
3895 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3899 * Transform the Projs from a Cmp.
3901 static ir_node *gen_Proj_Cmp(ir_node *node)
3903 /* normally Cmps are processed when looking at Cond nodes, but this case
3904 * can happen in complicated Psi conditions */
3906 ir_node *cmp = get_Proj_pred(node);
3907 long pnc = get_Proj_proj(node);
3908 ir_node *cmp_left = get_Cmp_left(cmp);
3909 ir_node *cmp_right = get_Cmp_right(cmp);
3910 ir_mode *cmp_mode = get_irn_mode(cmp_left);
3911 dbg_info *dbgi = get_irn_dbg_info(cmp);
3912 ir_node *block = be_transform_node(get_nodes_block(node));
3915 assert(!mode_is_float(cmp_mode));
3917 if(!mode_is_signed(cmp_mode)) {
3918 pnc |= ia32_pn_Cmp_Unsigned;
3921 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
3922 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
3928 * Transform and potentially renumber Proj nodes.
3930 static ir_node *gen_Proj(ir_node *node) {
3931 ir_graph *irg = current_ir_graph;
3932 dbg_info *dbgi = get_irn_dbg_info(node);
3933 ir_node *pred = get_Proj_pred(node);
3934 long proj = get_Proj_proj(node);
3936 if (is_Store(pred) || be_is_FrameStore(pred)) {
3937 if (proj == pn_Store_M) {
3938 return be_transform_node(pred);
3941 return new_r_Bad(irg);
3943 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
3944 return gen_Proj_Load(node);
3945 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3946 return gen_Proj_DivMod(node);
3947 } else if (is_CopyB(pred)) {
3948 return gen_Proj_CopyB(node);
3949 } else if (is_Quot(pred)) {
3950 return gen_Proj_Quot(node);
3951 } else if (is_ia32_l_vfdiv(pred)) {
3952 return gen_Proj_l_vfdiv(node);
3953 } else if (be_is_SubSP(pred)) {
3954 return gen_Proj_be_SubSP(node);
3955 } else if (be_is_AddSP(pred)) {
3956 return gen_Proj_be_AddSP(node);
3957 } else if (be_is_Call(pred)) {
3958 return gen_Proj_be_Call(node);
3959 } else if (is_Cmp(pred)) {
3960 return gen_Proj_Cmp(node);
3961 } else if (get_irn_op(pred) == op_Start) {
3962 if (proj == pn_Start_X_initial_exec) {
3963 ir_node *block = get_nodes_block(pred);
3966 /* we exchange the ProjX with a jump */
3967 block = be_transform_node(block);
3968 jump = new_rd_Jmp(dbgi, irg, block);
3971 if (node == be_get_old_anchor(anchor_tls)) {
3972 return gen_Proj_tls(node);
3975 ir_node *new_pred = be_transform_node(pred);
3976 ir_node *block = be_transform_node(get_nodes_block(node));
3977 ir_mode *mode = get_irn_mode(node);
3978 if (mode_needs_gp_reg(mode)) {
3979 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
3980 get_Proj_proj(node));
3981 #ifdef DEBUG_libfirm
3982 new_proj->node_nr = node->node_nr;
3988 return be_duplicate_node(node);
3992 * Enters all transform functions into the generic pointer
3994 static void register_transformers(void)
3998 /* first clear the generic function pointer for all ops */
3999 clear_irp_opcodes_generic_func();
4001 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4002 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4038 /* transform ops from intrinsic lowering */
4058 /* GEN(ia32_l_vfist); TODO */
4060 GEN(ia32_l_X87toSSE);
4061 GEN(ia32_l_SSEtoX87);
4066 /* we should never see these nodes */
4081 /* handle generic backend nodes */
4092 /* set the register for all Unknown nodes */
4095 op_Mulh = get_op_Mulh();
4104 * Pre-transform all unknown and noreg nodes.
4106 static void ia32_pretransform_node(void *arch_cg) {
4107 ia32_code_gen_t *cg = arch_cg;
4109 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4110 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4111 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4112 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4113 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4114 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4118 void add_missing_keep_walker(ir_node *node, void *data)
4121 unsigned found_projs = 0;
4122 const ir_edge_t *edge;
4123 ir_mode *mode = get_irn_mode(node);
4127 if(!is_ia32_irn(node))
4130 n_outs = get_ia32_n_res(node);
4133 if(is_ia32_SwitchJmp(node))
4136 assert(n_outs < (int) sizeof(unsigned) * 8);
4137 foreach_out_edge(node, edge) {
4138 ir_node *proj = get_edge_src_irn(edge);
4139 int pn = get_Proj_proj(proj);
4141 assert(pn < n_outs);
4142 found_projs |= 1 << pn;
4145 /* are keeps missing? */
4146 for(i = 0; i < n_outs; ++i) {
4149 const arch_register_req_t *req;
4150 const arch_register_class_t *class;
4152 if(found_projs & (1 << i)) {
4156 req = get_ia32_out_req(node, i);
4162 ir_fprintf(stderr, "Adding keep at out %d of %+F\n", i, node);
4163 block = get_nodes_block(node);
4164 in[0] = new_r_Proj(current_ir_graph, block, node,
4165 arch_register_class_mode(class), i);
4166 be_new_Keep(class, current_ir_graph, block, 1, in);
4171 * Adds missing keeps to nodes
4174 void add_missing_keeps(ia32_code_gen_t *cg)
4176 ir_graph *irg = be_get_birg_irg(cg->birg);
4177 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4180 /* do the transformation */
4181 void ia32_transform_graph(ia32_code_gen_t *cg) {
4182 register_transformers();
4184 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4185 edges_verify(cg->irg);
4186 add_missing_keeps(cg);
4187 edges_verify(cg->irg);
4190 void ia32_init_transform(void)
4192 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");