2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
50 #include "../benode_t.h"
51 #include "../besched.h"
53 #include "../beutil.h"
54 #include "../beirg_t.h"
55 #include "../betranshlp.h"
57 #include "bearch_ia32_t.h"
58 #include "ia32_nodes_attr.h"
59 #include "ia32_transform.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_dbg_stat.h"
63 #include "ia32_optimize.h"
64 #include "ia32_util.h"
66 #include "gen_ia32_regalloc_if.h"
68 #define SFP_SIGN "0x80000000"
69 #define DFP_SIGN "0x8000000000000000"
70 #define SFP_ABS "0x7FFFFFFF"
71 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
73 #define TP_SFP_SIGN "ia32_sfp_sign"
74 #define TP_DFP_SIGN "ia32_dfp_sign"
75 #define TP_SFP_ABS "ia32_sfp_abs"
76 #define TP_DFP_ABS "ia32_dfp_abs"
78 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
79 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
80 #define ENT_SFP_ABS "IA32_SFP_ABS"
81 #define ENT_DFP_ABS "IA32_DFP_ABS"
83 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
84 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
86 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
88 /** hold the current code generator during transformation */
89 static ia32_code_gen_t *env_cg = NULL;
90 static ir_node *initial_fpcw = NULL;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
119 static ir_node *create_immediate_or_transform(ir_node *node,
120 char immediate_constraint_type);
123 * Return true if a mode can be stored in the GP register set
125 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
126 if(mode == mode_fpcw)
128 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
132 * Returns 1 if irn is a Const representing 0, 0 otherwise
134 static INLINE int is_ia32_Const_0(ir_node *irn) {
135 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
136 && tarval_is_null(get_ia32_Immop_tarval(irn));
140 * Returns 1 if irn is a Const representing 1, 0 otherwise
142 static INLINE int is_ia32_Const_1(ir_node *irn) {
143 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
144 && tarval_is_one(get_ia32_Immop_tarval(irn));
148 * Collects all Projs of a node into the node array. Index is the projnum.
149 * BEWARE: The caller has to assure the appropriate array size!
151 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
152 const ir_edge_t *edge;
153 assert(get_irn_mode(irn) == mode_T && "need mode_T");
155 memset(projs, 0, size * sizeof(projs[0]));
157 foreach_out_edge(irn, edge) {
158 ir_node *proj = get_edge_src_irn(edge);
159 int proj_proj = get_Proj_proj(proj);
160 assert(proj_proj < size);
161 projs[proj_proj] = proj;
166 * Renumbers the proj having pn_old in the array tp pn_new
167 * and removes the proj from the array.
169 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
170 fprintf(stderr, "Warning: renumber_Proj used!\n");
172 set_Proj_proj(projs[pn_old], pn_new);
173 projs[pn_old] = NULL;
178 * creates a unique ident by adding a number to a tag
180 * @param tag the tag string, must contain a %d if a number
183 static ident *unique_id(const char *tag)
185 static unsigned id = 0;
188 snprintf(str, sizeof(str), tag, ++id);
189 return new_id_from_str(str);
193 * Get a primitive type for a mode.
195 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
197 pmap_entry *e = pmap_find(types, mode);
202 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
203 res = new_type_primitive(new_id_from_str(buf), mode);
204 set_type_alignment_bytes(res, 16);
205 pmap_insert(types, mode, res);
213 * Get an entity that is initialized with a tarval
215 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
217 tarval *tv = get_Const_tarval(cnst);
218 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
223 ir_mode *mode = get_irn_mode(cnst);
224 ir_type *tp = get_Const_type(cnst);
225 if (tp == firm_unknown_type)
226 tp = get_prim_type(cg->isa->types, mode);
228 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
230 set_entity_ld_ident(res, get_entity_ident(res));
231 set_entity_visibility(res, visibility_local);
232 set_entity_variability(res, variability_constant);
233 set_entity_allocation(res, allocation_static);
235 /* we create a new entity here: It's initialization must resist on the
237 rem = current_ir_graph;
238 current_ir_graph = get_const_code_irg();
239 set_atomic_ent_value(res, new_Const_type(tv, tp));
240 current_ir_graph = rem;
242 pmap_insert(cg->isa->tv_ent, tv, res);
250 static int is_Const_0(ir_node *node) {
254 return classify_Const(node) == CNST_NULL;
257 static int is_Const_1(ir_node *node) {
261 return classify_Const(node) == CNST_ONE;
265 * Transforms a Const.
267 static ir_node *gen_Const(ir_node *node) {
268 ir_graph *irg = current_ir_graph;
269 ir_node *old_block = get_nodes_block(node);
270 ir_node *block = be_transform_node(old_block);
271 dbg_info *dbgi = get_irn_dbg_info(node);
272 ir_mode *mode = get_irn_mode(node);
274 if (mode_is_float(mode)) {
276 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
277 ir_node *nomem = new_NoMem();
281 if (! USE_SSE2(env_cg)) {
282 cnst_classify_t clss = classify_Const(node);
284 if (clss == CNST_NULL) {
285 load = new_rd_ia32_vfldz(dbgi, irg, block);
287 } else if (clss == CNST_ONE) {
288 load = new_rd_ia32_vfld1(dbgi, irg, block);
291 floatent = get_entity_for_tv(env_cg, node);
293 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
294 set_ia32_op_type(load, ia32_AddrModeS);
295 set_ia32_am_flavour(load, ia32_am_N);
296 set_ia32_am_sc(load, floatent);
297 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
298 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
300 set_ia32_ls_mode(load, mode);
302 floatent = get_entity_for_tv(env_cg, node);
304 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
305 set_ia32_op_type(load, ia32_AddrModeS);
306 set_ia32_am_flavour(load, ia32_am_N);
307 set_ia32_am_sc(load, floatent);
308 set_ia32_ls_mode(load, mode);
309 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
311 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
314 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
316 /* Const Nodes before the initial IncSP are a bad idea, because
317 * they could be spilled and we have no SP ready at that point yet.
318 * So add a dependency to the initial frame pointer calculation to
319 * avoid that situation.
321 if (get_irg_start_block(irg) == block) {
322 add_irn_dep(load, get_irg_frame(irg));
325 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
328 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
331 if (get_irg_start_block(irg) == block) {
332 add_irn_dep(cnst, get_irg_frame(irg));
335 set_ia32_Const_attr(cnst, node);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
341 return new_r_Bad(irg);
345 * Transforms a SymConst.
347 static ir_node *gen_SymConst(ir_node *node) {
348 ir_graph *irg = current_ir_graph;
349 ir_node *old_block = get_nodes_block(node);
350 ir_node *block = be_transform_node(old_block);
351 dbg_info *dbgi = get_irn_dbg_info(node);
352 ir_mode *mode = get_irn_mode(node);
355 if (mode_is_float(mode)) {
356 if (USE_SSE2(env_cg))
357 cnst = new_rd_ia32_xConst(dbgi, irg, block);
359 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
360 //set_ia32_ls_mode(cnst, mode);
361 set_ia32_ls_mode(cnst, mode_E);
363 cnst = new_rd_ia32_Const(dbgi, irg, block);
366 /* Const Nodes before the initial IncSP are a bad idea, because
367 * they could be spilled and we have no SP ready at that point yet
369 if (get_irg_start_block(irg) == block) {
370 add_irn_dep(cnst, get_irg_frame(irg));
373 set_ia32_Const_attr(cnst, node);
374 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
379 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
380 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
381 static const struct {
383 const char *ent_name;
384 const char *cnst_str;
385 } names [ia32_known_const_max] = {
386 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
387 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
388 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
389 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
391 static ir_entity *ent_cache[ia32_known_const_max];
393 const char *tp_name, *ent_name, *cnst_str;
401 ent_name = names[kct].ent_name;
402 if (! ent_cache[kct]) {
403 tp_name = names[kct].tp_name;
404 cnst_str = names[kct].cnst_str;
406 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
408 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
409 tp = new_type_primitive(new_id_from_str(tp_name), mode);
410 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
412 set_entity_ld_ident(ent, get_entity_ident(ent));
413 set_entity_visibility(ent, visibility_local);
414 set_entity_variability(ent, variability_constant);
415 set_entity_allocation(ent, allocation_static);
417 /* we create a new entity here: It's initialization must resist on the
419 rem = current_ir_graph;
420 current_ir_graph = get_const_code_irg();
421 cnst = new_Const(mode, tv);
422 current_ir_graph = rem;
424 set_atomic_ent_value(ent, cnst);
426 /* cache the entry */
427 ent_cache[kct] = ent;
430 return ent_cache[kct];
435 * Prints the old node name on cg obst and returns a pointer to it.
437 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
438 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
440 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
441 obstack_1grow(isa->name_obst, 0);
442 return obstack_finish(isa->name_obst);
446 /* determine if one operator is an Imm */
447 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
449 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
451 return is_ia32_Cnst(op2) ? op2 : NULL;
455 /* determine if one operator is not an Imm */
456 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
457 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
460 static void fold_immediate(ir_node *node, int in1, int in2) {
464 if (!(env_cg->opt & IA32_OPT_IMMOPS))
467 left = get_irn_n(node, in1);
468 right = get_irn_n(node, in2);
469 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
470 /* we can only set right operand to immediate */
471 if(!is_ia32_commutative(node))
473 /* exchange left/right */
474 set_irn_n(node, in1, right);
475 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
476 copy_ia32_Immop_attr(node, left);
477 } else if(is_ia32_Cnst(right)) {
478 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
479 copy_ia32_Immop_attr(node, right);
484 clear_ia32_commutative(node);
485 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
486 get_ia32_am_arity(node));
490 * Construct a standard binary operation, set AM and immediate if required.
492 * @param op1 The first operand
493 * @param op2 The second operand
494 * @param func The node constructor function
495 * @return The constructed ia32 node.
497 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
498 construct_binop_func *func, int commutative)
500 ir_node *block = be_transform_node(get_nodes_block(node));
501 ir_graph *irg = current_ir_graph;
502 dbg_info *dbgi = get_irn_dbg_info(node);
503 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
504 ir_node *nomem = new_NoMem();
507 ir_node *new_op1 = be_transform_node(op1);
508 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
509 if (is_ia32_Immediate(new_op2)) {
513 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
514 if (func == new_rd_ia32_IMul) {
515 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
517 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
520 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
522 set_ia32_commutative(new_node);
529 * Construct a standard binary operation, set AM and immediate if required.
531 * @param op1 The first operand
532 * @param op2 The second operand
533 * @param func The node constructor function
534 * @return The constructed ia32 node.
536 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
537 construct_binop_func *func)
539 ir_node *block = be_transform_node(get_nodes_block(node));
540 ir_node *new_op1 = be_transform_node(op1);
541 ir_node *new_op2 = be_transform_node(op2);
542 ir_node *new_node = NULL;
543 dbg_info *dbgi = get_irn_dbg_info(node);
544 ir_graph *irg = current_ir_graph;
545 ir_mode *mode = get_irn_mode(node);
546 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
547 ir_node *nomem = new_NoMem();
549 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
551 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
552 if (is_op_commutative(get_irn_op(node))) {
553 set_ia32_commutative(new_node);
555 set_ia32_ls_mode(new_node, mode);
557 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
562 static ir_node *get_fpcw(void)
565 if(initial_fpcw != NULL)
568 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
569 &ia32_fp_cw_regs[REG_FPCW]);
570 initial_fpcw = be_transform_node(fpcw);
576 * Construct a standard binary operation, set AM and immediate if required.
578 * @param op1 The first operand
579 * @param op2 The second operand
580 * @param func The node constructor function
581 * @return The constructed ia32 node.
583 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
584 construct_binop_float_func *func)
586 ir_node *block = be_transform_node(get_nodes_block(node));
587 ir_node *new_op1 = be_transform_node(op1);
588 ir_node *new_op2 = be_transform_node(op2);
589 ir_node *new_node = NULL;
590 dbg_info *dbgi = get_irn_dbg_info(node);
591 ir_graph *irg = current_ir_graph;
592 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
593 ir_node *nomem = new_NoMem();
595 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
597 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
598 if (is_op_commutative(get_irn_op(node))) {
599 set_ia32_commutative(new_node);
602 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
608 * Construct a shift/rotate binary operation, sets AM and immediate if required.
610 * @param op1 The first operand
611 * @param op2 The second operand
612 * @param func The node constructor function
613 * @return The constructed ia32 node.
615 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
616 construct_binop_func *func)
618 ir_node *block = be_transform_node(get_nodes_block(node));
619 ir_node *new_op1 = be_transform_node(op1);
621 ir_node *new_op = NULL;
622 dbg_info *dbgi = get_irn_dbg_info(node);
623 ir_graph *irg = current_ir_graph;
624 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
625 ir_node *nomem = new_NoMem();
627 assert(! mode_is_float(get_irn_mode(node))
628 && "Shift/Rotate with float not supported");
630 new_op2 = create_immediate_or_transform(op2, 'N');
632 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
635 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
637 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
639 set_ia32_emit_cl(new_op);
646 * Construct a standard unary operation, set AM and immediate if required.
648 * @param op The operand
649 * @param func The node constructor function
650 * @return The constructed ia32 node.
652 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
654 ir_node *block = be_transform_node(get_nodes_block(node));
655 ir_node *new_op = be_transform_node(op);
656 ir_node *new_node = NULL;
657 ir_graph *irg = current_ir_graph;
658 dbg_info *dbgi = get_irn_dbg_info(node);
659 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
660 ir_node *nomem = new_NoMem();
662 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
663 DB((dbg, LEVEL_1, "INT unop ..."));
664 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
666 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
672 * Creates an ia32 Add.
674 * @return the created ia32 Add node
676 static ir_node *gen_Add(ir_node *node) {
677 ir_node *block = be_transform_node(get_nodes_block(node));
678 ir_node *op1 = get_Add_left(node);
679 ir_node *new_op1 = be_transform_node(op1);
680 ir_node *op2 = get_Add_right(node);
681 ir_node *new_op2 = be_transform_node(op2);
682 ir_node *new_op = NULL;
683 ir_graph *irg = current_ir_graph;
684 dbg_info *dbgi = get_irn_dbg_info(node);
685 ir_mode *mode = get_irn_mode(node);
686 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
687 ir_node *nomem = new_NoMem();
688 ir_node *expr_op, *imm_op;
690 /* Check if immediate optimization is on and */
691 /* if it's an operation with immediate. */
692 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
693 expr_op = get_expr_op(new_op1, new_op2);
695 assert((expr_op || imm_op) && "invalid operands");
697 if (mode_is_float(mode)) {
698 if (USE_SSE2(env_cg))
699 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
701 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
706 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
707 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
709 /* No expr_op means, that we have two const - one symconst and */
710 /* one tarval or another symconst - because this case is not */
711 /* covered by constant folding */
712 /* We need to check for: */
713 /* 1) symconst + const -> becomes a LEA */
714 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
715 /* linker doesn't support two symconsts */
717 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
718 /* this is the 2nd case */
719 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
720 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
721 set_ia32_am_flavour(new_op, ia32_am_B);
722 set_ia32_op_type(new_op, ia32_AddrModeS);
724 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
725 } else if (tp1 == ia32_ImmSymConst) {
726 tarval *tv = get_ia32_Immop_tarval(new_op2);
727 long offs = get_tarval_long(tv);
729 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
730 add_irn_dep(new_op, get_irg_frame(irg));
731 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
733 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
734 add_ia32_am_offs_int(new_op, offs);
735 set_ia32_am_flavour(new_op, ia32_am_OB);
736 set_ia32_op_type(new_op, ia32_AddrModeS);
737 } else if (tp2 == ia32_ImmSymConst) {
738 tarval *tv = get_ia32_Immop_tarval(new_op1);
739 long offs = get_tarval_long(tv);
741 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
742 add_irn_dep(new_op, get_irg_frame(irg));
743 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
745 add_ia32_am_offs_int(new_op, offs);
746 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
747 set_ia32_am_flavour(new_op, ia32_am_OB);
748 set_ia32_op_type(new_op, ia32_AddrModeS);
750 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
751 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
752 tarval *restv = tarval_add(tv1, tv2);
754 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
756 new_op = new_rd_ia32_Const(dbgi, irg, block);
757 set_ia32_Const_tarval(new_op, restv);
758 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
761 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
764 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
765 tarval_classification_t class_tv, class_negtv;
766 tarval *tv = get_ia32_Immop_tarval(imm_op);
768 /* optimize tarvals */
769 class_tv = classify_tarval(tv);
770 class_negtv = classify_tarval(tarval_neg(tv));
772 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
773 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
774 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
775 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
777 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
778 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
779 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
780 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
786 /* This is a normal add */
787 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
790 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
791 set_ia32_commutative(new_op);
793 fold_immediate(new_op, 2, 3);
795 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
801 * Creates an ia32 Mul.
803 * @return the created ia32 Mul node
805 static ir_node *gen_Mul(ir_node *node) {
806 ir_node *op1 = get_Mul_left(node);
807 ir_node *op2 = get_Mul_right(node);
808 ir_mode *mode = get_irn_mode(node);
810 if (mode_is_float(mode)) {
811 if (USE_SSE2(env_cg))
812 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
814 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
818 for the lower 32bit of the result it doesn't matter whether we use
819 signed or unsigned multiplication so we use IMul as it has fewer
822 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
826 * Creates an ia32 Mulh.
827 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
828 * this result while Mul returns the lower 32 bit.
830 * @return the created ia32 Mulh node
832 static ir_node *gen_Mulh(ir_node *node) {
833 ir_node *block = be_transform_node(get_nodes_block(node));
834 ir_node *op1 = get_irn_n(node, 0);
835 ir_node *new_op1 = be_transform_node(op1);
836 ir_node *op2 = get_irn_n(node, 1);
837 ir_node *new_op2 = be_transform_node(op2);
838 ir_graph *irg = current_ir_graph;
839 dbg_info *dbgi = get_irn_dbg_info(node);
840 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
841 ir_mode *mode = get_irn_mode(node);
842 ir_node *proj_EDX, *res;
844 assert(!mode_is_float(mode) && "Mulh with float not supported");
845 if (mode_is_signed(mode)) {
846 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
847 new_op2, new_NoMem());
849 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
853 set_ia32_commutative(res);
854 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
856 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
864 * Creates an ia32 And.
866 * @return The created ia32 And node
868 static ir_node *gen_And(ir_node *node) {
869 ir_node *op1 = get_And_left(node);
870 ir_node *op2 = get_And_right(node);
872 assert (! mode_is_float(get_irn_mode(node)));
873 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
879 * Creates an ia32 Or.
881 * @return The created ia32 Or node
883 static ir_node *gen_Or(ir_node *node) {
884 ir_node *op1 = get_Or_left(node);
885 ir_node *op2 = get_Or_right(node);
887 assert (! mode_is_float(get_irn_mode(node)));
888 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
894 * Creates an ia32 Eor.
896 * @return The created ia32 Eor node
898 static ir_node *gen_Eor(ir_node *node) {
899 ir_node *op1 = get_Eor_left(node);
900 ir_node *op2 = get_Eor_right(node);
902 assert(! mode_is_float(get_irn_mode(node)));
903 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
908 * Creates an ia32 Sub.
910 * @return The created ia32 Sub node
912 static ir_node *gen_Sub(ir_node *node) {
913 ir_node *block = be_transform_node(get_nodes_block(node));
914 ir_node *op1 = get_Sub_left(node);
915 ir_node *new_op1 = be_transform_node(op1);
916 ir_node *op2 = get_Sub_right(node);
917 ir_node *new_op2 = be_transform_node(op2);
918 ir_node *new_op = NULL;
919 ir_graph *irg = current_ir_graph;
920 dbg_info *dbgi = get_irn_dbg_info(node);
921 ir_mode *mode = get_irn_mode(node);
922 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
923 ir_node *nomem = new_NoMem();
924 ir_node *expr_op, *imm_op;
926 /* Check if immediate optimization is on and */
927 /* if it's an operation with immediate. */
928 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
929 expr_op = get_expr_op(new_op1, new_op2);
931 assert((expr_op || imm_op) && "invalid operands");
933 if (mode_is_float(mode)) {
934 if (USE_SSE2(env_cg))
935 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
937 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
942 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
943 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
945 /* No expr_op means, that we have two const - one symconst and */
946 /* one tarval or another symconst - because this case is not */
947 /* covered by constant folding */
948 /* We need to check for: */
949 /* 1) symconst - const -> becomes a LEA */
950 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
951 /* linker doesn't support two symconsts */
952 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
953 /* this is the 2nd case */
954 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
955 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
956 set_ia32_am_sc_sign(new_op);
957 set_ia32_am_flavour(new_op, ia32_am_B);
959 DBG_OPT_LEA3(op1, op2, node, new_op);
960 } else if (tp1 == ia32_ImmSymConst) {
961 tarval *tv = get_ia32_Immop_tarval(new_op2);
962 long offs = get_tarval_long(tv);
964 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
965 add_irn_dep(new_op, get_irg_frame(irg));
966 DBG_OPT_LEA3(op1, op2, node, new_op);
968 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
969 add_ia32_am_offs_int(new_op, -offs);
970 set_ia32_am_flavour(new_op, ia32_am_OB);
971 set_ia32_op_type(new_op, ia32_AddrModeS);
972 } else if (tp2 == ia32_ImmSymConst) {
973 tarval *tv = get_ia32_Immop_tarval(new_op1);
974 long offs = get_tarval_long(tv);
976 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
977 add_irn_dep(new_op, get_irg_frame(irg));
978 DBG_OPT_LEA3(op1, op2, node, new_op);
980 add_ia32_am_offs_int(new_op, offs);
981 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
982 set_ia32_am_sc_sign(new_op);
983 set_ia32_am_flavour(new_op, ia32_am_OB);
984 set_ia32_op_type(new_op, ia32_AddrModeS);
986 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
987 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
988 tarval *restv = tarval_sub(tv1, tv2);
990 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
992 new_op = new_rd_ia32_Const(dbgi, irg, block);
993 set_ia32_Const_tarval(new_op, restv);
994 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
997 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1000 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1001 tarval_classification_t class_tv, class_negtv;
1002 tarval *tv = get_ia32_Immop_tarval(imm_op);
1004 /* optimize tarvals */
1005 class_tv = classify_tarval(tv);
1006 class_negtv = classify_tarval(tarval_neg(tv));
1008 if (class_tv == TV_CLASSIFY_ONE) {
1009 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1010 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1011 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1013 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1014 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1015 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1016 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1022 /* This is a normal sub */
1023 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1025 /* set AM support */
1026 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1028 fold_immediate(new_op, 2, 3);
1030 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1038 * Generates an ia32 DivMod with additional infrastructure for the
1039 * register allocator if needed.
1041 * @param dividend -no comment- :)
1042 * @param divisor -no comment- :)
1043 * @param dm_flav flavour_Div/Mod/DivMod
1044 * @return The created ia32 DivMod node
1046 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1047 ir_node *divisor, ia32_op_flavour_t dm_flav)
1049 ir_node *block = be_transform_node(get_nodes_block(node));
1050 ir_node *new_dividend = be_transform_node(dividend);
1051 ir_node *new_divisor = be_transform_node(divisor);
1052 ir_graph *irg = current_ir_graph;
1053 dbg_info *dbgi = get_irn_dbg_info(node);
1054 ir_mode *mode = get_irn_mode(node);
1055 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1056 ir_node *res, *proj_div, *proj_mod;
1057 ir_node *sign_extension;
1058 ir_node *mem, *new_mem;
1059 ir_node *projs[pn_DivMod_max];
1062 ia32_collect_Projs(node, projs, pn_DivMod_max);
1064 proj_div = proj_mod = NULL;
1068 mem = get_Div_mem(node);
1069 mode = get_Div_resmode(node);
1070 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1071 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1074 mem = get_Mod_mem(node);
1075 mode = get_Mod_resmode(node);
1076 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1077 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1079 case flavour_DivMod:
1080 mem = get_DivMod_mem(node);
1081 mode = get_DivMod_resmode(node);
1082 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1083 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1084 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1087 panic("invalid divmod flavour!");
1089 new_mem = be_transform_node(mem);
1091 if (mode_is_signed(mode)) {
1092 /* in signed mode, we need to sign extend the dividend */
1093 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1094 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1097 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1098 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1100 add_irn_dep(sign_extension, get_irg_frame(irg));
1103 if (mode_is_signed(mode)) {
1104 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1105 sign_extension, new_divisor, new_mem, dm_flav);
1107 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1108 sign_extension, new_divisor, new_mem, dm_flav);
1111 set_ia32_exc_label(res, has_exc);
1112 set_irn_pinned(res, get_irn_pinned(node));
1113 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1115 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1122 * Wrapper for generate_DivMod. Sets flavour_Mod.
1125 static ir_node *gen_Mod(ir_node *node) {
1126 return generate_DivMod(node, get_Mod_left(node),
1127 get_Mod_right(node), flavour_Mod);
1131 * Wrapper for generate_DivMod. Sets flavour_Div.
1134 static ir_node *gen_Div(ir_node *node) {
1135 return generate_DivMod(node, get_Div_left(node),
1136 get_Div_right(node), flavour_Div);
1140 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1142 static ir_node *gen_DivMod(ir_node *node) {
1143 return generate_DivMod(node, get_DivMod_left(node),
1144 get_DivMod_right(node), flavour_DivMod);
1150 * Creates an ia32 floating Div.
1152 * @return The created ia32 xDiv node
1154 static ir_node *gen_Quot(ir_node *node) {
1155 ir_node *block = be_transform_node(get_nodes_block(node));
1156 ir_node *op1 = get_Quot_left(node);
1157 ir_node *new_op1 = be_transform_node(op1);
1158 ir_node *op2 = get_Quot_right(node);
1159 ir_node *new_op2 = be_transform_node(op2);
1160 ir_graph *irg = current_ir_graph;
1161 dbg_info *dbgi = get_irn_dbg_info(node);
1162 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1163 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1166 if (USE_SSE2(env_cg)) {
1167 ir_mode *mode = get_irn_mode(op1);
1168 if (is_ia32_xConst(new_op2)) {
1169 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1170 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1171 copy_ia32_Immop_attr(new_op, new_op2);
1173 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1174 // Matze: disabled for now, spillslot coalescer fails
1175 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1177 set_ia32_ls_mode(new_op, mode);
1179 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1180 new_op2, nomem, get_fpcw());
1181 // Matze: disabled for now (spillslot coalescer fails)
1182 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1184 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1190 * Creates an ia32 Shl.
1192 * @return The created ia32 Shl node
1194 static ir_node *gen_Shl(ir_node *node) {
1195 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1202 * Creates an ia32 Shr.
1204 * @return The created ia32 Shr node
1206 static ir_node *gen_Shr(ir_node *node) {
1207 return gen_shift_binop(node, get_Shr_left(node),
1208 get_Shr_right(node), new_rd_ia32_Shr);
1214 * Creates an ia32 Sar.
1216 * @return The created ia32 Shrs node
1218 static ir_node *gen_Shrs(ir_node *node) {
1219 ir_node *left = get_Shrs_left(node);
1220 ir_node *right = get_Shrs_right(node);
1221 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1222 tarval *tv = get_Const_tarval(right);
1223 long val = get_tarval_long(tv);
1225 /* this is a sign extension */
1226 ir_graph *irg = current_ir_graph;
1227 dbg_info *dbgi = get_irn_dbg_info(node);
1228 ir_node *block = be_transform_node(get_nodes_block(node));
1230 ir_node *new_op = be_transform_node(op);
1231 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1233 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1237 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1243 * Creates an ia32 RotL.
1245 * @param op1 The first operator
1246 * @param op2 The second operator
1247 * @return The created ia32 RotL node
1249 static ir_node *gen_RotL(ir_node *node,
1250 ir_node *op1, ir_node *op2) {
1251 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1257 * Creates an ia32 RotR.
1258 * NOTE: There is no RotR with immediate because this would always be a RotL
1259 * "imm-mode_size_bits" which can be pre-calculated.
1261 * @param op1 The first operator
1262 * @param op2 The second operator
1263 * @return The created ia32 RotR node
1265 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1267 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1273 * Creates an ia32 RotR or RotL (depending on the found pattern).
1275 * @return The created ia32 RotL or RotR node
1277 static ir_node *gen_Rot(ir_node *node) {
1278 ir_node *rotate = NULL;
1279 ir_node *op1 = get_Rot_left(node);
1280 ir_node *op2 = get_Rot_right(node);
1282 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1283 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1284 that means we can create a RotR instead of an Add and a RotL */
1286 if (get_irn_op(op2) == op_Add) {
1288 ir_node *left = get_Add_left(add);
1289 ir_node *right = get_Add_right(add);
1290 if (is_Const(right)) {
1291 tarval *tv = get_Const_tarval(right);
1292 ir_mode *mode = get_irn_mode(node);
1293 long bits = get_mode_size_bits(mode);
1295 if (get_irn_op(left) == op_Minus &&
1296 tarval_is_long(tv) &&
1297 get_tarval_long(tv) == bits)
1299 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1300 rotate = gen_RotR(node, op1, get_Minus_op(left));
1305 if (rotate == NULL) {
1306 rotate = gen_RotL(node, op1, op2);
1315 * Transforms a Minus node.
1317 * @param op The Minus operand
1318 * @return The created ia32 Minus node
1320 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1321 ir_node *block = be_transform_node(get_nodes_block(node));
1322 ir_graph *irg = current_ir_graph;
1323 dbg_info *dbgi = get_irn_dbg_info(node);
1324 ir_mode *mode = get_irn_mode(node);
1329 if (mode_is_float(mode)) {
1330 ir_node *new_op = be_transform_node(op);
1331 if (USE_SSE2(env_cg)) {
1332 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1333 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1334 ir_node *nomem = new_rd_NoMem(irg);
1336 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1338 size = get_mode_size_bits(mode);
1339 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1341 set_ia32_am_sc(res, ent);
1342 set_ia32_op_type(res, ia32_AddrModeS);
1343 set_ia32_ls_mode(res, mode);
1345 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1348 res = gen_unop(node, op, new_rd_ia32_Neg);
1351 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1357 * Transforms a Minus node.
1359 * @return The created ia32 Minus node
1361 static ir_node *gen_Minus(ir_node *node) {
1362 return gen_Minus_ex(node, get_Minus_op(node));
1365 static ir_node *gen_bin_Not(ir_node *node)
1367 ir_graph *irg = current_ir_graph;
1368 dbg_info *dbgi = get_irn_dbg_info(node);
1369 ir_node *block = be_transform_node(get_nodes_block(node));
1370 ir_node *op = get_Not_op(node);
1371 ir_node *new_op = be_transform_node(op);
1372 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1373 ir_node *nomem = new_NoMem();
1374 ir_node *one = new_rd_ia32_Immediate(dbgi, irg, block, NULL, 0, 1);
1375 arch_set_irn_register(env_cg->arch_env, one, &ia32_gp_regs[REG_GP_NOREG]);
1377 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1381 * Transforms a Not node.
1383 * @return The created ia32 Not node
1385 static ir_node *gen_Not(ir_node *node) {
1386 ir_node *op = get_Not_op(node);
1387 ir_mode *mode = get_irn_mode(node);
1389 if(mode == mode_b) {
1390 return gen_bin_Not(node);
1393 assert (! mode_is_float(get_irn_mode(node)));
1394 return gen_unop(node, op, new_rd_ia32_Not);
1400 * Transforms an Abs node.
1402 * @return The created ia32 Abs node
1404 static ir_node *gen_Abs(ir_node *node) {
1405 ir_node *block = be_transform_node(get_nodes_block(node));
1406 ir_node *op = get_Abs_op(node);
1407 ir_node *new_op = be_transform_node(op);
1408 ir_graph *irg = current_ir_graph;
1409 dbg_info *dbgi = get_irn_dbg_info(node);
1410 ir_mode *mode = get_irn_mode(node);
1411 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1412 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1413 ir_node *nomem = new_NoMem();
1418 if (mode_is_float(mode)) {
1419 if (USE_SSE2(env_cg)) {
1420 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1422 size = get_mode_size_bits(mode);
1423 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1425 set_ia32_am_sc(res, ent);
1427 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1429 set_ia32_op_type(res, ia32_AddrModeS);
1430 set_ia32_ls_mode(res, mode);
1433 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1434 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1438 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1439 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1441 SET_IA32_ORIG_NODE(sign_extension,
1442 ia32_get_old_node_name(env_cg, node));
1444 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1445 sign_extension, nomem);
1446 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1448 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1449 sign_extension, nomem);
1450 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1459 * Transforms a Load.
1461 * @return the created ia32 Load node
1463 static ir_node *gen_Load(ir_node *node) {
1464 ir_node *old_block = get_nodes_block(node);
1465 ir_node *block = be_transform_node(old_block);
1466 ir_node *ptr = get_Load_ptr(node);
1467 ir_node *new_ptr = be_transform_node(ptr);
1468 ir_node *mem = get_Load_mem(node);
1469 ir_node *new_mem = be_transform_node(mem);
1470 ir_graph *irg = current_ir_graph;
1471 dbg_info *dbgi = get_irn_dbg_info(node);
1472 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1473 ir_mode *mode = get_Load_mode(node);
1475 ir_node *lptr = new_ptr;
1478 ia32_am_flavour_t am_flav = ia32_am_B;
1480 /* address might be a constant (symconst or absolute address) */
1481 if (is_ia32_Const(new_ptr)) {
1486 if (mode_is_float(mode)) {
1487 if (USE_SSE2(env_cg)) {
1488 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1489 res_mode = mode_xmm;
1491 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1492 res_mode = mode_vfp;
1495 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1499 /* base is a constant address */
1501 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1502 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1503 am_flav = ia32_am_N;
1505 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1506 long offs = get_tarval_long(tv);
1508 add_ia32_am_offs_int(new_op, offs);
1509 am_flav = ia32_am_O;
1513 set_irn_pinned(new_op, get_irn_pinned(node));
1514 set_ia32_op_type(new_op, ia32_AddrModeS);
1515 set_ia32_am_flavour(new_op, am_flav);
1516 set_ia32_ls_mode(new_op, mode);
1518 /* make sure we are scheduled behind the initial IncSP/Barrier
1519 * to avoid spills being placed before it
1521 if (block == get_irg_start_block(irg)) {
1522 add_irn_dep(new_op, get_irg_frame(irg));
1525 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1526 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1534 * Transforms a Store.
1536 * @return the created ia32 Store node
1538 static ir_node *gen_Store(ir_node *node) {
1539 ir_node *block = be_transform_node(get_nodes_block(node));
1540 ir_node *ptr = get_Store_ptr(node);
1541 ir_node *new_ptr = be_transform_node(ptr);
1542 ir_node *val = get_Store_value(node);
1544 ir_node *mem = get_Store_mem(node);
1545 ir_node *new_mem = be_transform_node(mem);
1546 ir_graph *irg = current_ir_graph;
1547 dbg_info *dbgi = get_irn_dbg_info(node);
1548 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1549 ir_node *sptr = new_ptr;
1550 ir_mode *mode = get_irn_mode(val);
1553 ia32_am_flavour_t am_flav = ia32_am_B;
1555 /* address might be a constant (symconst or absolute address) */
1556 if (is_ia32_Const(new_ptr)) {
1561 if (mode_is_float(mode)) {
1562 new_val = be_transform_node(val);
1563 if (USE_SSE2(env_cg)) {
1564 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1567 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1571 new_val = create_immediate_or_transform(val, 0);
1573 if (get_mode_size_bits(mode) == 8) {
1574 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1577 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1582 /* base is an constant address */
1584 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1585 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1586 am_flav = ia32_am_N;
1588 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1589 long offs = get_tarval_long(tv);
1591 add_ia32_am_offs_int(new_op, offs);
1592 am_flav = ia32_am_O;
1596 set_irn_pinned(new_op, get_irn_pinned(node));
1597 set_ia32_op_type(new_op, ia32_AddrModeD);
1598 set_ia32_am_flavour(new_op, am_flav);
1599 set_ia32_ls_mode(new_op, mode);
1601 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1602 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1607 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1608 ir_node *cmp_left, ir_node *cmp_right)
1610 ir_node *new_cmp_left;
1611 ir_node *new_cmp_right;
1617 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1619 if(cmp_right != NULL && !is_Const_0(cmp_right))
1622 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1623 and_left = get_And_left(cmp_left);
1624 and_right = get_And_right(cmp_left);
1626 new_cmp_left = be_transform_node(and_left);
1627 new_cmp_right = create_immediate_or_transform(and_right, 0);
1629 new_cmp_left = be_transform_node(cmp_left);
1630 new_cmp_right = be_transform_node(cmp_left);
1633 noreg = ia32_new_NoReg_gp(env_cg);
1634 nomem = new_NoMem();
1636 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1637 new_cmp_left, new_cmp_right, nomem, pnc);
1638 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1643 static ir_node *create_Switch(ir_node *node)
1645 ir_graph *irg = current_ir_graph;
1646 dbg_info *dbgi = get_irn_dbg_info(node);
1647 ir_node *block = be_transform_node(get_nodes_block(node));
1648 ir_node *sel = get_Cond_selector(node);
1649 ir_node *new_sel = be_transform_node(sel);
1651 int switch_min = INT_MAX;
1652 const ir_edge_t *edge;
1654 /* determine the smallest switch case value */
1655 foreach_out_edge(node, edge) {
1656 ir_node *proj = get_edge_src_irn(edge);
1657 int pn = get_Proj_proj(proj);
1662 if (switch_min != 0) {
1663 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1665 /* if smallest switch case is not 0 we need an additional sub */
1666 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1667 add_ia32_am_offs_int(new_sel, -switch_min);
1668 set_ia32_am_flavour(new_sel, ia32_am_OB);
1669 set_ia32_op_type(new_sel, ia32_AddrModeS);
1671 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1674 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1675 set_ia32_pncode(res, get_Cond_defaultProj(node));
1677 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1683 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1685 * @return The transformed node.
1687 static ir_node *gen_Cond(ir_node *node) {
1688 ir_node *block = be_transform_node(get_nodes_block(node));
1689 ir_graph *irg = current_ir_graph;
1690 dbg_info *dbgi = get_irn_dbg_info(node);
1691 ir_node *sel = get_Cond_selector(node);
1692 ir_mode *sel_mode = get_irn_mode(sel);
1693 ir_node *res = NULL;
1694 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1701 ir_node *nomem = new_NoMem();
1704 if (sel_mode != mode_b) {
1705 return create_Switch(node);
1708 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
1709 /* it's some mode_b value not a direct comparison -> create a testjmp */
1710 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
1711 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1715 cmp = get_Proj_pred(sel);
1716 cmp_a = get_Cmp_left(cmp);
1717 cmp_b = get_Cmp_right(cmp);
1718 cmp_mode = get_irn_mode(cmp_a);
1719 pnc = get_Proj_proj(sel);
1720 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1721 pnc |= ia32_pn_Cmp_Unsigned;
1724 if(mode_needs_gp_reg(cmp_mode)) {
1725 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b);
1727 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1732 new_cmp_a = be_transform_node(cmp_a);
1733 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1735 if (mode_is_float(cmp_mode)) {
1736 if (USE_SSE2(env_cg)) {
1737 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1739 set_ia32_commutative(res);
1740 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1741 set_ia32_ls_mode(res, cmp_mode);
1743 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1744 set_ia32_commutative(res);
1747 assert(get_mode_size_bits(cmp_mode) == 32);
1748 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1749 new_cmp_a, new_cmp_b, nomem, pnc);
1750 set_ia32_commutative(res);
1751 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1754 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1762 * Transforms a CopyB node.
1764 * @return The transformed node.
1766 static ir_node *gen_CopyB(ir_node *node) {
1767 ir_node *block = be_transform_node(get_nodes_block(node));
1768 ir_node *src = get_CopyB_src(node);
1769 ir_node *new_src = be_transform_node(src);
1770 ir_node *dst = get_CopyB_dst(node);
1771 ir_node *new_dst = be_transform_node(dst);
1772 ir_node *mem = get_CopyB_mem(node);
1773 ir_node *new_mem = be_transform_node(mem);
1774 ir_node *res = NULL;
1775 ir_graph *irg = current_ir_graph;
1776 dbg_info *dbgi = get_irn_dbg_info(node);
1777 int size = get_type_size_bytes(get_CopyB_type(node));
1780 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1781 /* then we need the size explicitly in ECX. */
1782 if (size >= 32 * 4) {
1783 rem = size & 0x3; /* size % 4 */
1786 res = new_rd_ia32_Const(dbgi, irg, block);
1787 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1788 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1790 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1791 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1793 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1794 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1797 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1803 ir_node *gen_be_Copy(ir_node *node)
1805 ir_node *result = be_duplicate_node(node);
1806 ir_mode *mode = get_irn_mode(result);
1808 if (mode_needs_gp_reg(mode)) {
1809 set_irn_mode(result, mode_Iu);
1816 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1817 dbg_info *dbgi, ir_node *block)
1819 ir_graph *irg = current_ir_graph;
1820 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1821 ir_node *nomem = new_rd_NoMem(irg);
1822 ir_node *new_cmp_left;
1823 ir_node *new_cmp_right;
1826 /* can we use a test instruction? */
1827 if(cmp_right == NULL || is_Const_0(cmp_right)) {
1828 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1829 if(is_And(cmp_left) &&
1830 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1831 ir_node *and_left = get_And_left(cmp_left);
1832 ir_node *and_right = get_And_right(cmp_left);
1834 new_cmp_left = be_transform_node(and_left);
1835 new_cmp_right = create_immediate_or_transform(and_right, 0);
1837 new_cmp_left = be_transform_node(cmp_left);
1838 new_cmp_right = be_transform_node(cmp_left);
1841 res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
1842 new_cmp_left, new_cmp_right, nomem, pnc);
1843 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1848 new_cmp_left = be_transform_node(cmp_left);
1849 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1850 res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
1851 new_cmp_left, new_cmp_right, nomem, pnc);
1856 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1857 ir_node *val_true, ir_node *val_false,
1858 dbg_info *dbgi, ir_node *block)
1860 ir_graph *irg = current_ir_graph;
1861 ir_node *new_val_true = be_transform_node(val_true);
1862 ir_node *new_val_false = be_transform_node(val_false);
1863 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1864 ir_node *nomem = new_NoMem();
1865 ir_node *new_cmp_left;
1866 ir_node *new_cmp_right;
1869 /* cmovs with unknowns are pointless... */
1870 if(is_Unknown(val_true)) {
1871 #ifdef DEBUG_libfirm
1872 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1874 return new_val_false;
1876 if(is_Unknown(val_false)) {
1877 #ifdef DEBUG_libfirm
1878 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1880 return new_val_true;
1883 /* can we use a test instruction? */
1884 if(is_Const_0(cmp_right)) {
1885 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1886 if(is_And(cmp_left) &&
1887 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1888 ir_node *and_left = get_And_left(cmp_left);
1889 ir_node *and_right = get_And_right(cmp_left);
1891 new_cmp_left = be_transform_node(and_left);
1892 new_cmp_right = create_immediate_or_transform(and_right, 0);
1894 new_cmp_left = be_transform_node(cmp_left);
1895 new_cmp_right = be_transform_node(cmp_left);
1898 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, block, noreg, noreg,
1899 new_cmp_left, new_cmp_right, nomem,
1900 new_val_true, new_val_false, pnc);
1901 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1906 new_cmp_left = be_transform_node(cmp_left);
1907 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1909 res = new_rd_ia32_CmpCMov(dbgi, irg, block, noreg, noreg, new_cmp_left,
1910 new_cmp_right, nomem, new_val_true, new_val_false,
1912 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1919 * Transforms a Psi node into CMov.
1921 * @return The transformed node.
1923 static ir_node *gen_Psi(ir_node *node) {
1924 ir_node *psi_true = get_Psi_val(node, 0);
1925 ir_node *psi_default = get_Psi_default(node);
1926 ia32_code_gen_t *cg = env_cg;
1927 ir_node *cond = get_Psi_cond(node, 0);
1928 ir_node *block = be_transform_node(get_nodes_block(node));
1929 dbg_info *dbgi = get_irn_dbg_info(node);
1936 assert(get_Psi_n_conds(node) == 1);
1937 assert(get_irn_mode(cond) == mode_b);
1939 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
1940 /* a mode_b value, we have to compare it against 0 */
1942 cmp_right = new_Const_long(mode_Iu, 0);
1946 ir_node *cmp = get_Proj_pred(cond);
1948 cmp_left = get_Cmp_left(cmp);
1949 cmp_right = get_Cmp_right(cmp);
1950 cmp_mode = get_irn_mode(cmp_left);
1951 pnc = get_Proj_proj(cond);
1953 assert(!mode_is_float(cmp_mode));
1955 if (!mode_is_signed(cmp_mode)) {
1956 pnc |= ia32_pn_Cmp_Unsigned;
1960 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
1961 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
1962 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
1963 pnc = get_negated_pnc(pnc, cmp_mode);
1964 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
1966 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
1969 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1975 * Following conversion rules apply:
1979 * 1) n bit -> m bit n > m (downscale)
1981 * 2) n bit -> m bit n == m (sign change)
1983 * 3) n bit -> m bit n < m (upscale)
1984 * a) source is signed: movsx
1985 * b) source is unsigned: and with lower bits sets
1989 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1993 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1997 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1998 * x87 is mode_E internally, conversions happen only at load and store
1999 * in non-strict semantic
2003 * Create a conversion from x87 state register to general purpose.
2005 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2006 ir_node *block = be_transform_node(get_nodes_block(node));
2007 ir_node *op = get_Conv_op(node);
2008 ir_node *new_op = be_transform_node(op);
2009 ia32_code_gen_t *cg = env_cg;
2010 ir_graph *irg = current_ir_graph;
2011 dbg_info *dbgi = get_irn_dbg_info(node);
2012 ir_node *noreg = ia32_new_NoReg_gp(cg);
2013 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2014 ir_node *fist, *load;
2017 fist = new_rd_ia32_vfist(dbgi, irg, block,
2018 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2020 set_irn_pinned(fist, op_pin_state_floats);
2021 set_ia32_use_frame(fist);
2022 set_ia32_op_type(fist, ia32_AddrModeD);
2023 set_ia32_am_flavour(fist, ia32_am_B);
2024 set_ia32_ls_mode(fist, mode_Iu);
2025 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2028 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2030 set_irn_pinned(load, op_pin_state_floats);
2031 set_ia32_use_frame(load);
2032 set_ia32_op_type(load, ia32_AddrModeS);
2033 set_ia32_am_flavour(load, ia32_am_B);
2034 set_ia32_ls_mode(load, mode_Iu);
2035 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2037 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2040 static ir_node *create_strict_conv(ir_mode *tgt_mode, ir_node *node)
2042 ir_node *block = get_nodes_block(node);
2043 ir_graph *irg = current_ir_graph;
2044 dbg_info *dbgi = get_irn_dbg_info(node);
2045 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2046 ir_node *nomem = new_NoMem();
2047 ir_node *frame = get_irg_frame(irg);
2048 ir_node *store, *load;
2051 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2053 set_ia32_use_frame(store);
2054 set_ia32_op_type(store, ia32_AddrModeD);
2055 set_ia32_am_flavour(store, ia32_am_OB);
2056 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2058 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2060 set_ia32_use_frame(load);
2061 set_ia32_op_type(load, ia32_AddrModeS);
2062 set_ia32_am_flavour(load, ia32_am_OB);
2063 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2065 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2070 * Create a conversion from general purpose to x87 register
2072 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2073 ir_node *block = be_transform_node(get_nodes_block(node));
2074 ir_node *op = get_Conv_op(node);
2075 ir_node *new_op = be_transform_node(op);
2076 ir_graph *irg = current_ir_graph;
2077 dbg_info *dbgi = get_irn_dbg_info(node);
2078 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2079 ir_node *nomem = new_NoMem();
2080 ir_node *fild, *store;
2084 /* first convert to 32 bit if necessary */
2085 src_bits = get_mode_size_bits(src_mode);
2086 if (src_bits == 8) {
2087 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2088 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2089 set_ia32_ls_mode(new_op, src_mode);
2090 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2091 } else if (src_bits < 32) {
2092 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2093 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2094 set_ia32_ls_mode(new_op, src_mode);
2095 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2099 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2101 set_ia32_use_frame(store);
2102 set_ia32_op_type(store, ia32_AddrModeD);
2103 set_ia32_am_flavour(store, ia32_am_OB);
2104 set_ia32_ls_mode(store, mode_Iu);
2107 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2109 set_ia32_use_frame(fild);
2110 set_ia32_op_type(fild, ia32_AddrModeS);
2111 set_ia32_am_flavour(fild, ia32_am_OB);
2112 set_ia32_ls_mode(fild, mode_Iu);
2114 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2120 * Transforms a Conv node.
2122 * @return The created ia32 Conv node
2124 static ir_node *gen_Conv(ir_node *node) {
2125 ir_node *block = be_transform_node(get_nodes_block(node));
2126 ir_node *op = get_Conv_op(node);
2127 ir_node *new_op = be_transform_node(op);
2128 ir_graph *irg = current_ir_graph;
2129 dbg_info *dbgi = get_irn_dbg_info(node);
2130 ir_mode *src_mode = get_irn_mode(op);
2131 ir_mode *tgt_mode = get_irn_mode(node);
2132 int src_bits = get_mode_size_bits(src_mode);
2133 int tgt_bits = get_mode_size_bits(tgt_mode);
2134 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2135 ir_node *nomem = new_rd_NoMem(irg);
2138 if (src_mode == mode_b) {
2139 assert(mode_is_int(tgt_mode));
2140 /* nothing to do, we already model bools as 0/1 ints */
2144 if (src_mode == tgt_mode) {
2145 if (get_Conv_strict(node)) {
2146 if (USE_SSE2(env_cg)) {
2147 /* when we are in SSE mode, we can kill all strict no-op conversion */
2151 /* this should be optimized already, but who knows... */
2152 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2153 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2158 if (mode_is_float(src_mode)) {
2159 /* we convert from float ... */
2160 if (mode_is_float(tgt_mode)) {
2161 if(src_mode == mode_E && tgt_mode == mode_D
2162 && !get_Conv_strict(node)) {
2163 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2168 if (USE_SSE2(env_cg)) {
2169 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2170 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2171 set_ia32_ls_mode(res, tgt_mode);
2173 if(get_Conv_strict(node)) {
2174 res = create_strict_conv(tgt_mode, new_op);
2175 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2178 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2183 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2184 if (USE_SSE2(env_cg)) {
2185 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2186 set_ia32_ls_mode(res, src_mode);
2188 return gen_x87_fp_to_gp(node);
2192 /* we convert from int ... */
2193 if (mode_is_float(tgt_mode)) {
2195 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2196 if (USE_SSE2(env_cg)) {
2197 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2198 set_ia32_ls_mode(res, tgt_mode);
2199 if(src_bits == 32) {
2200 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2203 res = gen_x87_gp_to_fp(node, src_mode);
2204 if(get_Conv_strict(node)) {
2205 res = create_strict_conv(tgt_mode, res);
2206 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2207 ia32_get_old_node_name(env_cg, node));
2211 } else if(tgt_mode == mode_b) {
2214 res = create_set(pn_Cmp_Lg, op, NULL, dbgi, block);
2216 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2221 ir_mode *smaller_mode;
2224 if (src_bits == tgt_bits) {
2225 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2226 src_mode, tgt_mode));
2230 if (src_bits < tgt_bits) {
2231 smaller_mode = src_mode;
2232 smaller_bits = src_bits;
2234 smaller_mode = tgt_mode;
2235 smaller_bits = tgt_bits;
2238 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2239 if (smaller_bits == 8) {
2240 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2241 set_ia32_ls_mode(res, smaller_mode);
2243 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2244 set_ia32_ls_mode(res, smaller_mode);
2246 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2250 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2256 int check_immediate_constraint(long val, char immediate_constraint_type)
2258 switch (immediate_constraint_type) {
2262 return val >= 0 && val <= 32;
2264 return val >= 0 && val <= 63;
2266 return val >= -128 && val <= 127;
2268 return val == 0xff || val == 0xffff;
2270 return val >= 0 && val <= 3;
2272 return val >= 0 && val <= 255;
2274 return val >= 0 && val <= 127;
2278 panic("Invalid immediate constraint found");
2283 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2286 tarval *offset = NULL;
2287 int offset_sign = 0;
2289 ir_entity *symconst_ent = NULL;
2290 int symconst_sign = 0;
2292 ir_node *cnst = NULL;
2293 ir_node *symconst = NULL;
2299 mode = get_irn_mode(node);
2300 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2304 if(is_Minus(node)) {
2306 node = get_Minus_op(node);
2309 if(is_Const(node)) {
2312 offset_sign = minus;
2313 } else if(is_SymConst(node)) {
2316 symconst_sign = minus;
2317 } else if(is_Add(node)) {
2318 ir_node *left = get_Add_left(node);
2319 ir_node *right = get_Add_right(node);
2320 if(is_Const(left) && is_SymConst(right)) {
2323 symconst_sign = minus;
2324 offset_sign = minus;
2325 } else if(is_SymConst(left) && is_Const(right)) {
2328 symconst_sign = minus;
2329 offset_sign = minus;
2331 } else if(is_Sub(node)) {
2332 ir_node *left = get_Sub_left(node);
2333 ir_node *right = get_Sub_right(node);
2334 if(is_Const(left) && is_SymConst(right)) {
2337 symconst_sign = !minus;
2338 offset_sign = minus;
2339 } else if(is_SymConst(left) && is_Const(right)) {
2342 symconst_sign = minus;
2343 offset_sign = !minus;
2350 offset = get_Const_tarval(cnst);
2351 if(tarval_is_long(offset)) {
2352 val = get_tarval_long(offset);
2353 } else if(tarval_is_null(offset)) {
2356 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2361 if(!check_immediate_constraint(val, immediate_constraint_type))
2364 if(symconst != NULL) {
2365 if(immediate_constraint_type != 0) {
2366 /* we need full 32bits for symconsts */
2370 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2372 symconst_ent = get_SymConst_entity(symconst);
2374 if(cnst == NULL && symconst == NULL)
2377 if(offset_sign && offset != NULL) {
2378 offset = tarval_neg(offset);
2381 irg = current_ir_graph;
2382 dbgi = get_irn_dbg_info(node);
2383 block = get_irg_start_block(irg);
2384 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2385 symconst_sign, val);
2386 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2392 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2394 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2395 if (new_node == NULL) {
2396 new_node = be_transform_node(node);
2401 typedef struct constraint_t constraint_t;
2402 struct constraint_t {
2405 const arch_register_req_t **out_reqs;
2407 const arch_register_req_t *req;
2408 unsigned immediate_possible;
2409 char immediate_type;
2412 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2414 int immediate_possible = 0;
2415 char immediate_type = 0;
2416 unsigned limited = 0;
2417 const arch_register_class_t *cls = NULL;
2419 struct obstack *obst;
2420 arch_register_req_t *req;
2421 unsigned *limited_ptr;
2425 /* TODO: replace all the asserts with nice error messages */
2427 printf("Constraint: %s\n", c);
2437 assert(cls == NULL ||
2438 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2439 cls = &ia32_reg_classes[CLASS_ia32_gp];
2440 limited |= 1 << REG_EAX;
2443 assert(cls == NULL ||
2444 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2445 cls = &ia32_reg_classes[CLASS_ia32_gp];
2446 limited |= 1 << REG_EBX;
2449 assert(cls == NULL ||
2450 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2451 cls = &ia32_reg_classes[CLASS_ia32_gp];
2452 limited |= 1 << REG_ECX;
2455 assert(cls == NULL ||
2456 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2457 cls = &ia32_reg_classes[CLASS_ia32_gp];
2458 limited |= 1 << REG_EDX;
2461 assert(cls == NULL ||
2462 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2463 cls = &ia32_reg_classes[CLASS_ia32_gp];
2464 limited |= 1 << REG_EDI;
2467 assert(cls == NULL ||
2468 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2469 cls = &ia32_reg_classes[CLASS_ia32_gp];
2470 limited |= 1 << REG_ESI;
2473 case 'q': /* q means lower part of the regs only, this makes no
2474 * difference to Q for us (we only assigne whole registers) */
2475 assert(cls == NULL ||
2476 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2477 cls = &ia32_reg_classes[CLASS_ia32_gp];
2478 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2482 assert(cls == NULL ||
2483 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2484 cls = &ia32_reg_classes[CLASS_ia32_gp];
2485 limited |= 1 << REG_EAX | 1 << REG_EDX;
2488 assert(cls == NULL ||
2489 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2490 cls = &ia32_reg_classes[CLASS_ia32_gp];
2491 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2492 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2499 assert(cls == NULL);
2500 cls = &ia32_reg_classes[CLASS_ia32_gp];
2506 /* TODO: mark values so the x87 simulator knows about t and u */
2507 assert(cls == NULL);
2508 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2513 assert(cls == NULL);
2514 /* TODO: check that sse2 is supported */
2515 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2525 assert(!immediate_possible);
2526 immediate_possible = 1;
2527 immediate_type = *c;
2531 assert(!immediate_possible);
2532 immediate_possible = 1;
2536 assert(!immediate_possible && cls == NULL);
2537 immediate_possible = 1;
2538 cls = &ia32_reg_classes[CLASS_ia32_gp];
2551 assert(constraint->is_in && "can only specify same constraint "
2554 sscanf(c, "%d%n", &same_as, &p);
2561 case 'E': /* no float consts yet */
2562 case 'F': /* no float consts yet */
2563 case 's': /* makes no sense on x86 */
2564 case 'X': /* we can't support that in firm */
2568 case '<': /* no autodecrement on x86 */
2569 case '>': /* no autoincrement on x86 */
2570 case 'C': /* sse constant not supported yet */
2571 case 'G': /* 80387 constant not supported yet */
2572 case 'y': /* we don't support mmx registers yet */
2573 case 'Z': /* not available in 32 bit mode */
2574 case 'e': /* not available in 32 bit mode */
2575 assert(0 && "asm constraint not supported");
2578 assert(0 && "unknown asm constraint found");
2585 const arch_register_req_t *other_constr;
2587 assert(cls == NULL && "same as and register constraint not supported");
2588 assert(!immediate_possible && "same as and immediate constraint not "
2590 assert(same_as < constraint->n_outs && "wrong constraint number in "
2591 "same_as constraint");
2593 other_constr = constraint->out_reqs[same_as];
2595 req = obstack_alloc(obst, sizeof(req[0]));
2596 req->cls = other_constr->cls;
2597 req->type = arch_register_req_type_should_be_same;
2598 req->limited = NULL;
2599 req->other_same = pos;
2600 req->other_different = -1;
2602 /* switch constraints. This is because in firm we have same_as
2603 * constraints on the output constraints while in the gcc asm syntax
2604 * they are specified on the input constraints */
2605 constraint->req = other_constr;
2606 constraint->out_reqs[same_as] = req;
2607 constraint->immediate_possible = 0;
2611 if(immediate_possible && cls == NULL) {
2612 cls = &ia32_reg_classes[CLASS_ia32_gp];
2614 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2615 assert(cls != NULL);
2617 if(immediate_possible) {
2618 assert(constraint->is_in
2619 && "imeediates make no sense for output constraints");
2621 /* todo: check types (no float input on 'r' constrainted in and such... */
2623 irg = current_ir_graph;
2624 obst = get_irg_obstack(irg);
2627 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2628 limited_ptr = (unsigned*) (req+1);
2630 req = obstack_alloc(obst, sizeof(req[0]));
2632 memset(req, 0, sizeof(req[0]));
2635 req->type = arch_register_req_type_limited;
2636 *limited_ptr = limited;
2637 req->limited = limited_ptr;
2639 req->type = arch_register_req_type_normal;
2643 constraint->req = req;
2644 constraint->immediate_possible = immediate_possible;
2645 constraint->immediate_type = immediate_type;
2649 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2656 panic("Clobbers not supported yet");
2659 ir_node *gen_ASM(ir_node *node)
2662 ir_graph *irg = current_ir_graph;
2663 ir_node *block = be_transform_node(get_nodes_block(node));
2664 dbg_info *dbgi = get_irn_dbg_info(node);
2671 ia32_asm_attr_t *attr;
2672 const arch_register_req_t **out_reqs;
2673 const arch_register_req_t **in_reqs;
2674 struct obstack *obst;
2675 constraint_t parsed_constraint;
2677 /* transform inputs */
2678 arity = get_irn_arity(node);
2679 in = alloca(arity * sizeof(in[0]));
2680 memset(in, 0, arity * sizeof(in[0]));
2682 n_outs = get_ASM_n_output_constraints(node);
2683 n_clobbers = get_ASM_n_clobbers(node);
2684 out_arity = n_outs + n_clobbers;
2686 /* construct register constraints */
2687 obst = get_irg_obstack(irg);
2688 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2689 parsed_constraint.out_reqs = out_reqs;
2690 parsed_constraint.n_outs = n_outs;
2691 parsed_constraint.is_in = 0;
2692 for(i = 0; i < out_arity; ++i) {
2696 const ir_asm_constraint *constraint;
2697 constraint = & get_ASM_output_constraints(node) [i];
2698 c = get_id_str(constraint->constraint);
2699 parse_asm_constraint(i, &parsed_constraint, c);
2701 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2702 c = get_id_str(glob_id);
2703 parse_clobber(node, i, &parsed_constraint, c);
2705 out_reqs[i] = parsed_constraint.req;
2708 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2709 parsed_constraint.is_in = 1;
2710 for(i = 0; i < arity; ++i) {
2711 const ir_asm_constraint *constraint;
2715 constraint = & get_ASM_input_constraints(node) [i];
2716 constr_id = constraint->constraint;
2717 c = get_id_str(constr_id);
2718 parse_asm_constraint(i, &parsed_constraint, c);
2719 in_reqs[i] = parsed_constraint.req;
2721 if(parsed_constraint.immediate_possible) {
2722 ir_node *pred = get_irn_n(node, i);
2723 char imm_type = parsed_constraint.immediate_type;
2724 ir_node *immediate = try_create_Immediate(pred, imm_type);
2726 if(immediate != NULL) {
2732 /* transform inputs */
2733 for(i = 0; i < arity; ++i) {
2735 ir_node *transformed;
2740 pred = get_irn_n(node, i);
2741 transformed = be_transform_node(pred);
2742 in[i] = transformed;
2745 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2747 generic_attr = get_irn_generic_attr(res);
2748 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2749 attr->asm_text = get_ASM_text(node);
2750 set_ia32_out_req_all(res, out_reqs);
2751 set_ia32_in_req_all(res, in_reqs);
2753 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2758 /********************************************
2761 * | |__ ___ _ __ ___ __| | ___ ___
2762 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2763 * | |_) | __/ | | | (_) | (_| | __/\__ \
2764 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2766 ********************************************/
2768 static ir_node *gen_be_StackParam(ir_node *node) {
2769 ir_node *block = be_transform_node(get_nodes_block(node));
2770 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2771 ir_node *new_ptr = be_transform_node(ptr);
2772 ir_node *new_op = NULL;
2773 ir_graph *irg = current_ir_graph;
2774 dbg_info *dbgi = get_irn_dbg_info(node);
2775 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2776 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2777 ir_mode *load_mode = get_irn_mode(node);
2778 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2782 if (mode_is_float(load_mode)) {
2783 if (USE_SSE2(env_cg)) {
2784 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2785 pn_res = pn_ia32_xLoad_res;
2786 proj_mode = mode_xmm;
2788 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2789 pn_res = pn_ia32_vfld_res;
2790 proj_mode = mode_vfp;
2793 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2794 proj_mode = mode_Iu;
2795 pn_res = pn_ia32_Load_res;
2798 set_irn_pinned(new_op, op_pin_state_floats);
2799 set_ia32_frame_ent(new_op, ent);
2800 set_ia32_use_frame(new_op);
2802 set_ia32_op_type(new_op, ia32_AddrModeS);
2803 set_ia32_am_flavour(new_op, ia32_am_B);
2804 set_ia32_ls_mode(new_op, load_mode);
2805 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2807 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2809 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2813 * Transforms a FrameAddr into an ia32 Add.
2815 static ir_node *gen_be_FrameAddr(ir_node *node) {
2816 ir_node *block = be_transform_node(get_nodes_block(node));
2817 ir_node *op = be_get_FrameAddr_frame(node);
2818 ir_node *new_op = be_transform_node(op);
2819 ir_graph *irg = current_ir_graph;
2820 dbg_info *dbgi = get_irn_dbg_info(node);
2821 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2824 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2825 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2826 set_ia32_use_frame(res);
2827 set_ia32_am_flavour(res, ia32_am_OB);
2829 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2835 * Transforms a FrameLoad into an ia32 Load.
2837 static ir_node *gen_be_FrameLoad(ir_node *node) {
2838 ir_node *block = be_transform_node(get_nodes_block(node));
2839 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2840 ir_node *new_mem = be_transform_node(mem);
2841 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2842 ir_node *new_ptr = be_transform_node(ptr);
2843 ir_node *new_op = NULL;
2844 ir_graph *irg = current_ir_graph;
2845 dbg_info *dbgi = get_irn_dbg_info(node);
2846 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2847 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2848 ir_mode *mode = get_type_mode(get_entity_type(ent));
2849 ir_node *projs[pn_Load_max];
2851 ia32_collect_Projs(node, projs, pn_Load_max);
2853 if (mode_is_float(mode)) {
2854 if (USE_SSE2(env_cg)) {
2855 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2858 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2862 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2865 set_irn_pinned(new_op, op_pin_state_floats);
2866 set_ia32_frame_ent(new_op, ent);
2867 set_ia32_use_frame(new_op);
2869 set_ia32_op_type(new_op, ia32_AddrModeS);
2870 set_ia32_am_flavour(new_op, ia32_am_B);
2871 set_ia32_ls_mode(new_op, mode);
2872 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2874 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2881 * Transforms a FrameStore into an ia32 Store.
2883 static ir_node *gen_be_FrameStore(ir_node *node) {
2884 ir_node *block = be_transform_node(get_nodes_block(node));
2885 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2886 ir_node *new_mem = be_transform_node(mem);
2887 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2888 ir_node *new_ptr = be_transform_node(ptr);
2889 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2890 ir_node *new_val = be_transform_node(val);
2891 ir_node *new_op = NULL;
2892 ir_graph *irg = current_ir_graph;
2893 dbg_info *dbgi = get_irn_dbg_info(node);
2894 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2895 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2896 ir_mode *mode = get_irn_mode(val);
2898 if (mode_is_float(mode)) {
2899 if (USE_SSE2(env_cg)) {
2900 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2902 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2904 } else if (get_mode_size_bits(mode) == 8) {
2905 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2907 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2910 set_ia32_frame_ent(new_op, ent);
2911 set_ia32_use_frame(new_op);
2913 set_ia32_op_type(new_op, ia32_AddrModeD);
2914 set_ia32_am_flavour(new_op, ia32_am_B);
2915 set_ia32_ls_mode(new_op, mode);
2917 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2923 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2925 static ir_node *gen_be_Return(ir_node *node) {
2926 ir_graph *irg = current_ir_graph;
2927 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2928 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2929 ir_entity *ent = get_irg_entity(irg);
2930 ir_type *tp = get_entity_type(ent);
2935 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2936 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2939 int pn_ret_val, pn_ret_mem, arity, i;
2941 assert(ret_val != NULL);
2942 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
2943 return be_duplicate_node(node);
2946 res_type = get_method_res_type(tp, 0);
2948 if (! is_Primitive_type(res_type)) {
2949 return be_duplicate_node(node);
2952 mode = get_type_mode(res_type);
2953 if (! mode_is_float(mode)) {
2954 return be_duplicate_node(node);
2957 assert(get_method_n_ress(tp) == 1);
2959 pn_ret_val = get_Proj_proj(ret_val);
2960 pn_ret_mem = get_Proj_proj(ret_mem);
2962 /* get the Barrier */
2963 barrier = get_Proj_pred(ret_val);
2965 /* get result input of the Barrier */
2966 ret_val = get_irn_n(barrier, pn_ret_val);
2967 new_ret_val = be_transform_node(ret_val);
2969 /* get memory input of the Barrier */
2970 ret_mem = get_irn_n(barrier, pn_ret_mem);
2971 new_ret_mem = be_transform_node(ret_mem);
2973 frame = get_irg_frame(irg);
2975 dbgi = get_irn_dbg_info(barrier);
2976 block = be_transform_node(get_nodes_block(barrier));
2978 noreg = ia32_new_NoReg_gp(env_cg);
2980 /* store xmm0 onto stack */
2981 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
2982 new_ret_val, new_ret_mem);
2983 set_ia32_ls_mode(sse_store, mode);
2984 set_ia32_op_type(sse_store, ia32_AddrModeD);
2985 set_ia32_use_frame(sse_store);
2986 set_ia32_am_flavour(sse_store, ia32_am_B);
2988 /* load into x87 register */
2989 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
2990 set_ia32_op_type(fld, ia32_AddrModeS);
2991 set_ia32_use_frame(fld);
2992 set_ia32_am_flavour(fld, ia32_am_B);
2994 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
2995 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
2997 /* create a new barrier */
2998 arity = get_irn_arity(barrier);
2999 in = alloca(arity * sizeof(in[0]));
3000 for (i = 0; i < arity; ++i) {
3003 if (i == pn_ret_val) {
3005 } else if (i == pn_ret_mem) {
3008 ir_node *in = get_irn_n(barrier, i);
3009 new_in = be_transform_node(in);
3014 new_barrier = new_ir_node(dbgi, irg, block,
3015 get_irn_op(barrier), get_irn_mode(barrier),
3017 copy_node_attr(barrier, new_barrier);
3018 be_duplicate_deps(barrier, new_barrier);
3019 be_set_transformed_node(barrier, new_barrier);
3020 mark_irn_visited(barrier);
3022 /* transform normally */
3023 return be_duplicate_node(node);
3027 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3029 static ir_node *gen_be_AddSP(ir_node *node) {
3030 ir_node *block = be_transform_node(get_nodes_block(node));
3031 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3033 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3034 ir_node *new_sp = be_transform_node(sp);
3035 ir_graph *irg = current_ir_graph;
3036 dbg_info *dbgi = get_irn_dbg_info(node);
3037 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3038 ir_node *nomem = new_NoMem();
3041 new_sz = create_immediate_or_transform(sz, 0);
3043 /* ia32 stack grows in reverse direction, make a SubSP */
3044 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3046 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3047 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3053 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3055 static ir_node *gen_be_SubSP(ir_node *node) {
3056 ir_node *block = be_transform_node(get_nodes_block(node));
3057 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3059 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3060 ir_node *new_sp = be_transform_node(sp);
3061 ir_graph *irg = current_ir_graph;
3062 dbg_info *dbgi = get_irn_dbg_info(node);
3063 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3064 ir_node *nomem = new_NoMem();
3067 new_sz = create_immediate_or_transform(sz, 0);
3069 /* ia32 stack grows in reverse direction, make an AddSP */
3070 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3071 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3072 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3078 * This function just sets the register for the Unknown node
3079 * as this is not done during register allocation because Unknown
3080 * is an "ignore" node.
3082 static ir_node *gen_Unknown(ir_node *node) {
3083 ir_mode *mode = get_irn_mode(node);
3085 if (mode_is_float(mode)) {
3087 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3088 if (USE_SSE2(env_cg))
3089 return ia32_new_Unknown_xmm(env_cg);
3091 return ia32_new_Unknown_vfp(env_cg);
3093 ir_graph *irg = current_ir_graph;
3094 dbg_info *dbgi = get_irn_dbg_info(node);
3095 ir_node *block = get_irg_start_block(irg);
3096 return new_rd_ia32_vfldz(dbgi, irg, block);
3098 } else if (mode_needs_gp_reg(mode)) {
3099 return ia32_new_Unknown_gp(env_cg);
3101 assert(0 && "unsupported Unknown-Mode");
3108 * Change some phi modes
3110 static ir_node *gen_Phi(ir_node *node) {
3111 ir_node *block = be_transform_node(get_nodes_block(node));
3112 ir_graph *irg = current_ir_graph;
3113 dbg_info *dbgi = get_irn_dbg_info(node);
3114 ir_mode *mode = get_irn_mode(node);
3117 if(mode_needs_gp_reg(mode)) {
3118 /* we shouldn't have any 64bit stuff around anymore */
3119 assert(get_mode_size_bits(mode) <= 32);
3120 /* all integer operations are on 32bit registers now */
3122 } else if(mode_is_float(mode)) {
3123 if (USE_SSE2(env_cg)) {
3130 /* phi nodes allow loops, so we use the old arguments for now
3131 * and fix this later */
3132 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3133 copy_node_attr(node, phi);
3134 be_duplicate_deps(node, phi);
3136 be_set_transformed_node(node, phi);
3137 be_enqueue_preds(node);
3142 /**********************************************************************
3145 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3146 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3147 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3148 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3150 **********************************************************************/
3152 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3154 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3157 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3158 ir_node *val, ir_node *mem);
3161 * Transforms a lowered Load into a "real" one.
3163 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3165 ir_node *block = be_transform_node(get_nodes_block(node));
3166 ir_node *ptr = get_irn_n(node, 0);
3167 ir_node *new_ptr = be_transform_node(ptr);
3168 ir_node *mem = get_irn_n(node, 1);
3169 ir_node *new_mem = be_transform_node(mem);
3170 ir_graph *irg = current_ir_graph;
3171 dbg_info *dbgi = get_irn_dbg_info(node);
3172 ir_mode *mode = get_ia32_ls_mode(node);
3173 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3176 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3178 set_ia32_op_type(new_op, ia32_AddrModeS);
3179 set_ia32_am_flavour(new_op, ia32_am_OB);
3180 set_ia32_am_offs_int(new_op, 0);
3181 set_ia32_am_scale(new_op, 1);
3182 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3183 if (is_ia32_am_sc_sign(node))
3184 set_ia32_am_sc_sign(new_op);
3185 set_ia32_ls_mode(new_op, mode);
3186 if (is_ia32_use_frame(node)) {
3187 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3188 set_ia32_use_frame(new_op);
3191 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3197 * Transforms a lowered Store into a "real" one.
3199 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3201 ir_node *block = be_transform_node(get_nodes_block(node));
3202 ir_node *ptr = get_irn_n(node, 0);
3203 ir_node *new_ptr = be_transform_node(ptr);
3204 ir_node *val = get_irn_n(node, 1);
3205 ir_node *new_val = be_transform_node(val);
3206 ir_node *mem = get_irn_n(node, 2);
3207 ir_node *new_mem = be_transform_node(mem);
3208 ir_graph *irg = current_ir_graph;
3209 dbg_info *dbgi = get_irn_dbg_info(node);
3210 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3211 ir_mode *mode = get_ia32_ls_mode(node);
3214 ia32_am_flavour_t am_flav = ia32_B;
3216 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3218 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3220 add_ia32_am_offs_int(new_op, am_offs);
3223 set_ia32_op_type(new_op, ia32_AddrModeD);
3224 set_ia32_am_flavour(new_op, am_flav);
3225 set_ia32_ls_mode(new_op, mode);
3226 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3227 set_ia32_use_frame(new_op);
3229 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3236 * Transforms an ia32_l_XXX into a "real" XXX node
3238 * @param env The transformation environment
3239 * @return the created ia32 XXX node
3241 #define GEN_LOWERED_OP(op) \
3242 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3243 return gen_binop(node, get_binop_left(node), \
3244 get_binop_right(node), new_rd_ia32_##op,0); \
3247 #define GEN_LOWERED_x87_OP(op) \
3248 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3250 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3251 get_binop_right(node), new_rd_ia32_##op); \
3255 #define GEN_LOWERED_UNOP(op) \
3256 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3257 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3260 #define GEN_LOWERED_SHIFT_OP(op) \
3261 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3262 return gen_shift_binop(node, get_binop_left(node), \
3263 get_binop_right(node), new_rd_ia32_##op); \
3266 #define GEN_LOWERED_LOAD(op) \
3267 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3268 return gen_lowered_Load(node, new_rd_ia32_##op); \
3271 #define GEN_LOWERED_STORE(op) \
3272 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3273 return gen_lowered_Store(node, new_rd_ia32_##op); \
3280 GEN_LOWERED_OP(IMul)
3282 GEN_LOWERED_x87_OP(vfprem)
3283 GEN_LOWERED_x87_OP(vfmul)
3284 GEN_LOWERED_x87_OP(vfsub)
3286 GEN_LOWERED_UNOP(Neg)
3288 GEN_LOWERED_LOAD(vfild)
3289 GEN_LOWERED_LOAD(Load)
3290 // GEN_LOWERED_STORE(vfist) TODO
3291 GEN_LOWERED_STORE(Store)
3293 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3294 ir_node *block = be_transform_node(get_nodes_block(node));
3295 ir_node *left = get_binop_left(node);
3296 ir_node *new_left = be_transform_node(left);
3297 ir_node *right = get_binop_right(node);
3298 ir_node *new_right = be_transform_node(right);
3299 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3300 ir_graph *irg = current_ir_graph;
3301 dbg_info *dbgi = get_irn_dbg_info(node);
3302 ir_node *fpcw = get_fpcw();
3305 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3306 new_right, new_NoMem(), fpcw);
3307 clear_ia32_commutative(vfdiv);
3308 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3310 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3316 * Transforms a l_MulS into a "real" MulS node.
3318 * @param env The transformation environment
3319 * @return the created ia32 Mul node
3321 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3322 ir_node *block = be_transform_node(get_nodes_block(node));
3323 ir_node *left = get_binop_left(node);
3324 ir_node *new_left = be_transform_node(left);
3325 ir_node *right = get_binop_right(node);
3326 ir_node *new_right = be_transform_node(right);
3327 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3328 ir_graph *irg = current_ir_graph;
3329 dbg_info *dbgi = get_irn_dbg_info(node);
3331 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3332 /* and then skip the result Proj, because all needed Projs are already there. */
3333 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3334 new_right, new_NoMem());
3335 clear_ia32_commutative(muls);
3336 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3338 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3343 GEN_LOWERED_SHIFT_OP(Shl)
3344 GEN_LOWERED_SHIFT_OP(Shr)
3345 GEN_LOWERED_SHIFT_OP(Sar)
3348 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3349 * op1 - target to be shifted
3350 * op2 - contains bits to be shifted into target
3352 * Only op3 can be an immediate.
3354 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3355 ir_node *op2, ir_node *count)
3357 ir_node *block = be_transform_node(get_nodes_block(node));
3358 ir_node *new_op1 = be_transform_node(op1);
3359 ir_node *new_op2 = be_transform_node(op2);
3360 ir_node *new_count = be_transform_node(count);
3361 ir_node *new_op = NULL;
3362 ir_graph *irg = current_ir_graph;
3363 dbg_info *dbgi = get_irn_dbg_info(node);
3364 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3365 ir_node *nomem = new_NoMem();
3369 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3371 /* Check if immediate optimization is on and */
3372 /* if it's an operation with immediate. */
3373 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3375 /* Limit imm_op within range imm8 */
3377 tv = get_ia32_Immop_tarval(imm_op);
3380 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3381 set_ia32_Immop_tarval(imm_op, tv);
3388 /* integer operations */
3390 /* This is ShiftD with const */
3391 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3393 if (is_ia32_l_ShlD(node))
3394 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3395 new_op1, new_op2, noreg, nomem);
3397 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3398 new_op1, new_op2, noreg, nomem);
3399 copy_ia32_Immop_attr(new_op, imm_op);
3402 /* This is a normal ShiftD */
3403 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3404 if (is_ia32_l_ShlD(node))
3405 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3406 new_op1, new_op2, new_count, nomem);
3408 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3409 new_op1, new_op2, new_count, nomem);
3412 /* set AM support */
3413 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3415 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3417 set_ia32_emit_cl(new_op);
3422 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3423 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3424 get_irn_n(node, 1), get_irn_n(node, 2));
3427 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3428 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3429 get_irn_n(node, 1), get_irn_n(node, 2));
3433 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3435 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3436 ir_node *block = be_transform_node(get_nodes_block(node));
3437 ir_node *val = get_irn_n(node, 1);
3438 ir_node *new_val = be_transform_node(val);
3439 ia32_code_gen_t *cg = env_cg;
3440 ir_node *res = NULL;
3441 ir_graph *irg = current_ir_graph;
3443 ir_node *noreg, *new_ptr, *new_mem;
3450 mem = get_irn_n(node, 2);
3451 new_mem = be_transform_node(mem);
3452 ptr = get_irn_n(node, 0);
3453 new_ptr = be_transform_node(ptr);
3454 noreg = ia32_new_NoReg_gp(cg);
3455 dbgi = get_irn_dbg_info(node);
3457 /* Store x87 -> MEM */
3458 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3459 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3460 set_ia32_use_frame(res);
3461 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3462 set_ia32_am_flavour(res, ia32_B);
3463 set_ia32_op_type(res, ia32_AddrModeD);
3465 /* Load MEM -> SSE */
3466 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3467 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3468 set_ia32_use_frame(res);
3469 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3470 set_ia32_am_flavour(res, ia32_B);
3471 set_ia32_op_type(res, ia32_AddrModeS);
3472 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3478 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3480 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3481 ir_node *block = be_transform_node(get_nodes_block(node));
3482 ir_node *val = get_irn_n(node, 1);
3483 ir_node *new_val = be_transform_node(val);
3484 ia32_code_gen_t *cg = env_cg;
3485 ir_graph *irg = current_ir_graph;
3486 ir_node *res = NULL;
3487 ir_entity *fent = get_ia32_frame_ent(node);
3488 ir_mode *lsmode = get_ia32_ls_mode(node);
3490 ir_node *noreg, *new_ptr, *new_mem;
3494 if (! USE_SSE2(cg)) {
3495 /* SSE unit is not used -> skip this node. */
3499 ptr = get_irn_n(node, 0);
3500 new_ptr = be_transform_node(ptr);
3501 mem = get_irn_n(node, 2);
3502 new_mem = be_transform_node(mem);
3503 noreg = ia32_new_NoReg_gp(cg);
3504 dbgi = get_irn_dbg_info(node);
3506 /* Store SSE -> MEM */
3507 if (is_ia32_xLoad(skip_Proj(new_val))) {
3508 ir_node *ld = skip_Proj(new_val);
3510 /* we can vfld the value directly into the fpu */
3511 fent = get_ia32_frame_ent(ld);
3512 ptr = get_irn_n(ld, 0);
3513 offs = get_ia32_am_offs_int(ld);
3515 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3516 set_ia32_frame_ent(res, fent);
3517 set_ia32_use_frame(res);
3518 set_ia32_ls_mode(res, lsmode);
3519 set_ia32_am_flavour(res, ia32_B);
3520 set_ia32_op_type(res, ia32_AddrModeD);
3524 /* Load MEM -> x87 */
3525 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3526 set_ia32_frame_ent(res, fent);
3527 set_ia32_use_frame(res);
3528 add_ia32_am_offs_int(res, offs);
3529 set_ia32_am_flavour(res, ia32_B);
3530 set_ia32_op_type(res, ia32_AddrModeS);
3531 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3536 /*********************************************************
3539 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3540 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3541 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3542 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3544 *********************************************************/
3547 * the BAD transformer.
3549 static ir_node *bad_transform(ir_node *node) {
3550 panic("No transform function for %+F available.\n", node);
3555 * Transform the Projs of an AddSP.
3557 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3558 ir_node *block = be_transform_node(get_nodes_block(node));
3559 ir_node *pred = get_Proj_pred(node);
3560 ir_node *new_pred = be_transform_node(pred);
3561 ir_graph *irg = current_ir_graph;
3562 dbg_info *dbgi = get_irn_dbg_info(node);
3563 long proj = get_Proj_proj(node);
3565 if (proj == pn_be_AddSP_sp) {
3566 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3567 pn_ia32_SubSP_stack);
3568 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3570 } else if(proj == pn_be_AddSP_res) {
3571 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3572 pn_ia32_SubSP_addr);
3573 } else if (proj == pn_be_AddSP_M) {
3574 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3578 return new_rd_Unknown(irg, get_irn_mode(node));
3582 * Transform the Projs of a SubSP.
3584 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3585 ir_node *block = be_transform_node(get_nodes_block(node));
3586 ir_node *pred = get_Proj_pred(node);
3587 ir_node *new_pred = be_transform_node(pred);
3588 ir_graph *irg = current_ir_graph;
3589 dbg_info *dbgi = get_irn_dbg_info(node);
3590 long proj = get_Proj_proj(node);
3592 if (proj == pn_be_SubSP_sp) {
3593 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3594 pn_ia32_AddSP_stack);
3595 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3597 } else if (proj == pn_be_SubSP_M) {
3598 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3602 return new_rd_Unknown(irg, get_irn_mode(node));
3606 * Transform and renumber the Projs from a Load.
3608 static ir_node *gen_Proj_Load(ir_node *node) {
3609 ir_node *block = be_transform_node(get_nodes_block(node));
3610 ir_node *pred = get_Proj_pred(node);
3611 ir_node *new_pred = be_transform_node(pred);
3612 ir_graph *irg = current_ir_graph;
3613 dbg_info *dbgi = get_irn_dbg_info(node);
3614 long proj = get_Proj_proj(node);
3616 /* renumber the proj */
3617 if (is_ia32_Load(new_pred)) {
3618 if (proj == pn_Load_res) {
3619 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3620 } else if (proj == pn_Load_M) {
3621 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3623 } else if (is_ia32_xLoad(new_pred)) {
3624 if (proj == pn_Load_res) {
3625 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3626 } else if (proj == pn_Load_M) {
3627 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3629 } else if (is_ia32_vfld(new_pred)) {
3630 if (proj == pn_Load_res) {
3631 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3632 } else if (proj == pn_Load_M) {
3633 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3638 return new_rd_Unknown(irg, get_irn_mode(node));
3642 * Transform and renumber the Projs from a DivMod like instruction.
3644 static ir_node *gen_Proj_DivMod(ir_node *node) {
3645 ir_node *block = be_transform_node(get_nodes_block(node));
3646 ir_node *pred = get_Proj_pred(node);
3647 ir_node *new_pred = be_transform_node(pred);
3648 ir_graph *irg = current_ir_graph;
3649 dbg_info *dbgi = get_irn_dbg_info(node);
3650 ir_mode *mode = get_irn_mode(node);
3651 long proj = get_Proj_proj(node);
3653 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3655 switch (get_irn_opcode(pred)) {
3659 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3661 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3669 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3671 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3679 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3680 case pn_DivMod_res_div:
3681 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3682 case pn_DivMod_res_mod:
3683 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3693 return new_rd_Unknown(irg, mode);
3697 * Transform and renumber the Projs from a CopyB.
3699 static ir_node *gen_Proj_CopyB(ir_node *node) {
3700 ir_node *block = be_transform_node(get_nodes_block(node));
3701 ir_node *pred = get_Proj_pred(node);
3702 ir_node *new_pred = be_transform_node(pred);
3703 ir_graph *irg = current_ir_graph;
3704 dbg_info *dbgi = get_irn_dbg_info(node);
3705 ir_mode *mode = get_irn_mode(node);
3706 long proj = get_Proj_proj(node);
3709 case pn_CopyB_M_regular:
3710 if (is_ia32_CopyB_i(new_pred)) {
3711 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3712 } else if (is_ia32_CopyB(new_pred)) {
3713 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3721 return new_rd_Unknown(irg, mode);
3725 * Transform and renumber the Projs from a vfdiv.
3727 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3728 ir_node *block = be_transform_node(get_nodes_block(node));
3729 ir_node *pred = get_Proj_pred(node);
3730 ir_node *new_pred = be_transform_node(pred);
3731 ir_graph *irg = current_ir_graph;
3732 dbg_info *dbgi = get_irn_dbg_info(node);
3733 ir_mode *mode = get_irn_mode(node);
3734 long proj = get_Proj_proj(node);
3737 case pn_ia32_l_vfdiv_M:
3738 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3739 case pn_ia32_l_vfdiv_res:
3740 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3745 return new_rd_Unknown(irg, mode);
3749 * Transform and renumber the Projs from a Quot.
3751 static ir_node *gen_Proj_Quot(ir_node *node) {
3752 ir_node *block = be_transform_node(get_nodes_block(node));
3753 ir_node *pred = get_Proj_pred(node);
3754 ir_node *new_pred = be_transform_node(pred);
3755 ir_graph *irg = current_ir_graph;
3756 dbg_info *dbgi = get_irn_dbg_info(node);
3757 ir_mode *mode = get_irn_mode(node);
3758 long proj = get_Proj_proj(node);
3762 if (is_ia32_xDiv(new_pred)) {
3763 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3764 } else if (is_ia32_vfdiv(new_pred)) {
3765 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3769 if (is_ia32_xDiv(new_pred)) {
3770 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3771 } else if (is_ia32_vfdiv(new_pred)) {
3772 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3780 return new_rd_Unknown(irg, mode);
3784 * Transform the Thread Local Storage Proj.
3786 static ir_node *gen_Proj_tls(ir_node *node) {
3787 ir_node *block = be_transform_node(get_nodes_block(node));
3788 ir_graph *irg = current_ir_graph;
3789 dbg_info *dbgi = NULL;
3790 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3796 * Transform the Projs from a be_Call.
3798 static ir_node *gen_Proj_be_Call(ir_node *node) {
3799 ir_node *block = be_transform_node(get_nodes_block(node));
3800 ir_node *call = get_Proj_pred(node);
3801 ir_node *new_call = be_transform_node(call);
3802 ir_graph *irg = current_ir_graph;
3803 dbg_info *dbgi = get_irn_dbg_info(node);
3804 long proj = get_Proj_proj(node);
3805 ir_mode *mode = get_irn_mode(node);
3807 const arch_register_class_t *cls;
3809 /* The following is kinda tricky: If we're using SSE, then we have to
3810 * move the result value of the call in floating point registers to an
3811 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3812 * after the call, we have to make sure to correctly make the
3813 * MemProj and the result Proj use these 2 nodes
3815 if (proj == pn_be_Call_M_regular) {
3816 // get new node for result, are we doing the sse load/store hack?
3817 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3818 ir_node *call_res_new;
3819 ir_node *call_res_pred = NULL;
3821 if (call_res != NULL) {
3822 call_res_new = be_transform_node(call_res);
3823 call_res_pred = get_Proj_pred(call_res_new);
3826 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3827 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
3828 pn_be_Call_M_regular);
3830 assert(is_ia32_xLoad(call_res_pred));
3831 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
3835 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3837 ir_node *frame = get_irg_frame(irg);
3838 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3840 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3843 /* in case there is no memory output: create one to serialize the copy
3845 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
3846 pn_be_Call_M_regular);
3847 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
3848 pn_be_Call_first_res);
3850 /* store st(0) onto stack */
3851 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
3853 set_ia32_op_type(fstp, ia32_AddrModeD);
3854 set_ia32_use_frame(fstp);
3855 set_ia32_am_flavour(fstp, ia32_am_B);
3857 /* load into SSE register */
3858 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3859 set_ia32_ls_mode(sse_load, mode);
3860 set_ia32_op_type(sse_load, ia32_AddrModeS);
3861 set_ia32_use_frame(sse_load);
3862 set_ia32_am_flavour(sse_load, ia32_am_B);
3864 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
3868 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3870 /* get a Proj representing a caller save register */
3871 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3872 assert(is_Proj(p) && "Proj expected.");
3874 /* user of the the proj is the Keep */
3875 p = get_edge_src_irn(get_irn_out_edge_first(p));
3876 assert(be_is_Keep(p) && "Keep expected.");
3882 /* transform call modes */
3883 if (mode_is_data(mode)) {
3884 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
3888 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3892 * Transform the Projs from a Cmp.
3894 static ir_node *gen_Proj_Cmp(ir_node *node)
3896 /* normally Cmps are processed when looking at Cond nodes, but this case
3897 * can happen in complicated Psi conditions */
3899 ir_node *cmp = get_Proj_pred(node);
3900 long pnc = get_Proj_proj(node);
3901 ir_node *cmp_left = get_Cmp_left(cmp);
3902 ir_node *cmp_right = get_Cmp_right(cmp);
3903 ir_mode *cmp_mode = get_irn_mode(cmp_left);
3904 dbg_info *dbgi = get_irn_dbg_info(cmp);
3905 ir_node *block = be_transform_node(get_nodes_block(node));
3908 assert(!mode_is_float(cmp_mode));
3910 if(!mode_is_signed(cmp_mode)) {
3911 pnc |= ia32_pn_Cmp_Unsigned;
3914 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
3915 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
3921 * Transform and potentially renumber Proj nodes.
3923 static ir_node *gen_Proj(ir_node *node) {
3924 ir_graph *irg = current_ir_graph;
3925 dbg_info *dbgi = get_irn_dbg_info(node);
3926 ir_node *pred = get_Proj_pred(node);
3927 long proj = get_Proj_proj(node);
3929 if (is_Store(pred) || be_is_FrameStore(pred)) {
3930 if (proj == pn_Store_M) {
3931 return be_transform_node(pred);
3934 return new_r_Bad(irg);
3936 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
3937 return gen_Proj_Load(node);
3938 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3939 return gen_Proj_DivMod(node);
3940 } else if (is_CopyB(pred)) {
3941 return gen_Proj_CopyB(node);
3942 } else if (is_Quot(pred)) {
3943 return gen_Proj_Quot(node);
3944 } else if (is_ia32_l_vfdiv(pred)) {
3945 return gen_Proj_l_vfdiv(node);
3946 } else if (be_is_SubSP(pred)) {
3947 return gen_Proj_be_SubSP(node);
3948 } else if (be_is_AddSP(pred)) {
3949 return gen_Proj_be_AddSP(node);
3950 } else if (be_is_Call(pred)) {
3951 return gen_Proj_be_Call(node);
3952 } else if (is_Cmp(pred)) {
3953 return gen_Proj_Cmp(node);
3954 } else if (get_irn_op(pred) == op_Start) {
3955 if (proj == pn_Start_X_initial_exec) {
3956 ir_node *block = get_nodes_block(pred);
3959 /* we exchange the ProjX with a jump */
3960 block = be_transform_node(block);
3961 jump = new_rd_Jmp(dbgi, irg, block);
3964 if (node == be_get_old_anchor(anchor_tls)) {
3965 return gen_Proj_tls(node);
3968 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
3972 ir_node *new_pred = be_transform_node(pred);
3973 ir_node *block = be_transform_node(get_nodes_block(node));
3974 ir_mode *mode = get_irn_mode(node);
3975 if (mode_needs_gp_reg(mode)) {
3976 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
3977 get_Proj_proj(node));
3978 #ifdef DEBUG_libfirm
3979 new_proj->node_nr = node->node_nr;
3985 return be_duplicate_node(node);
3989 * Enters all transform functions into the generic pointer
3991 static void register_transformers(void)
3995 /* first clear the generic function pointer for all ops */
3996 clear_irp_opcodes_generic_func();
3998 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3999 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4035 /* transform ops from intrinsic lowering */
4055 /* GEN(ia32_l_vfist); TODO */
4057 GEN(ia32_l_X87toSSE);
4058 GEN(ia32_l_SSEtoX87);
4063 /* we should never see these nodes */
4078 /* handle generic backend nodes */
4089 /* set the register for all Unknown nodes */
4092 op_Mulh = get_op_Mulh();
4101 * Pre-transform all unknown and noreg nodes.
4103 static void ia32_pretransform_node(void *arch_cg) {
4104 ia32_code_gen_t *cg = arch_cg;
4106 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4107 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4108 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4109 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4110 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4111 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4116 void add_missing_keep_walker(ir_node *node, void *data)
4119 unsigned found_projs = 0;
4120 const ir_edge_t *edge;
4121 ir_mode *mode = get_irn_mode(node);
4126 if(!is_ia32_irn(node))
4129 n_outs = get_ia32_n_res(node);
4132 if(is_ia32_SwitchJmp(node))
4135 assert(n_outs < (int) sizeof(unsigned) * 8);
4136 foreach_out_edge(node, edge) {
4137 ir_node *proj = get_edge_src_irn(edge);
4138 int pn = get_Proj_proj(proj);
4140 assert(pn < n_outs);
4141 found_projs |= 1 << pn;
4145 /* are keeps missing? */
4147 for(i = 0; i < n_outs; ++i) {
4150 const arch_register_req_t *req;
4151 const arch_register_class_t *class;
4153 if(found_projs & (1 << i)) {
4157 req = get_ia32_out_req(node, i);
4163 block = get_nodes_block(node);
4164 in[0] = new_r_Proj(current_ir_graph, block, node,
4165 arch_register_class_mode(class), i);
4166 if(last_keep != NULL) {
4167 be_Keep_add_node(last_keep, class, in[0]);
4169 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4175 * Adds missing keeps to nodes
4178 void add_missing_keeps(ia32_code_gen_t *cg)
4180 ir_graph *irg = be_get_birg_irg(cg->birg);
4181 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4184 /* do the transformation */
4185 void ia32_transform_graph(ia32_code_gen_t *cg) {
4186 register_transformers();
4188 initial_fpcw = NULL;
4189 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4190 edges_verify(cg->irg);
4191 add_missing_keeps(cg);
4192 edges_verify(cg->irg);
4195 void ia32_init_transform(void)
4197 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");