2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
55 #include "../benode_t.h"
56 #include "../besched.h"
58 #include "../beutil.h"
59 #include "../beirg_t.h"
61 #include "bearch_ia32_t.h"
62 #include "ia32_nodes_attr.h"
63 #include "ia32_transform.h"
64 #include "ia32_new_nodes.h"
65 #include "ia32_map_regs.h"
66 #include "ia32_dbg_stat.h"
67 #include "ia32_optimize.h"
68 #include "ia32_util.h"
70 #include "gen_ia32_regalloc_if.h"
72 #define SFP_SIGN "0x80000000"
73 #define DFP_SIGN "0x8000000000000000"
74 #define SFP_ABS "0x7FFFFFFF"
75 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
82 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
83 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
84 #define ENT_SFP_ABS "IA32_SFP_ABS"
85 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
88 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
90 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
92 typedef struct ia32_transform_env_t {
93 ir_graph *irg; /**< The irg, the node should be created in */
94 ia32_code_gen_t *cg; /**< The code generator */
95 int visited; /**< visited count that indicates whether a
96 node is already transformed */
97 pdeq *worklist; /**< worklist of nodes that still need to be
99 ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/
100 } ia32_transform_env_t;
102 extern ir_op *get_op_Mulh(void);
104 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
105 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
106 ir_node *op2, ir_node *mem);
108 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
109 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
112 typedef ir_node *(transform_func)(ia32_transform_env_t *env, ir_node *node);
114 /****************************************************************************************************
116 * | | | | / _| | | (_)
117 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
118 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
119 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
120 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
122 ****************************************************************************************************/
124 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node);
125 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node);
126 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
129 static INLINE int mode_needs_gp_reg(ir_mode *mode)
131 if(mode == mode_fpcw)
134 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
137 static INLINE void set_new_node(ir_node *old_node, ir_node *new_node)
139 set_irn_link(old_node, new_node);
142 static INLINE ir_node *get_new_node(ir_node *old_node)
144 assert(irn_visited(old_node));
145 return (ir_node*) get_irn_link(old_node);
149 * Returns 1 if irn is a Const representing 0, 0 otherwise
151 static INLINE int is_ia32_Const_0(ir_node *irn) {
152 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
153 && tarval_is_null(get_ia32_Immop_tarval(irn));
157 * Returns 1 if irn is a Const representing 1, 0 otherwise
159 static INLINE int is_ia32_Const_1(ir_node *irn) {
160 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
161 && tarval_is_one(get_ia32_Immop_tarval(irn));
165 * Collects all Projs of a node into the node array. Index is the projnum.
166 * BEWARE: The caller has to assure the appropriate array size!
168 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
169 const ir_edge_t *edge;
170 assert(get_irn_mode(irn) == mode_T && "need mode_T");
172 memset(projs, 0, size * sizeof(projs[0]));
174 foreach_out_edge(irn, edge) {
175 ir_node *proj = get_edge_src_irn(edge);
176 int proj_proj = get_Proj_proj(proj);
177 assert(proj_proj < size);
178 projs[proj_proj] = proj;
183 * Renumbers the proj having pn_old in the array tp pn_new
184 * and removes the proj from the array.
186 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
187 fprintf(stderr, "Warning: renumber_Proj used!\n");
189 set_Proj_proj(projs[pn_old], pn_new);
190 projs[pn_old] = NULL;
195 * creates a unique ident by adding a number to a tag
197 * @param tag the tag string, must contain a %d if a number
200 static ident *unique_id(const char *tag)
202 static unsigned id = 0;
205 snprintf(str, sizeof(str), tag, ++id);
206 return new_id_from_str(str);
210 * Get a primitive type for a mode.
212 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
214 pmap_entry *e = pmap_find(types, mode);
219 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
220 res = new_type_primitive(new_id_from_str(buf), mode);
221 pmap_insert(types, mode, res);
229 * Get an entity that is initialized with a tarval
231 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
233 tarval *tv = get_Const_tarval(cnst);
234 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
239 ir_mode *mode = get_irn_mode(cnst);
240 ir_type *tp = get_Const_type(cnst);
241 if (tp == firm_unknown_type)
242 tp = get_prim_type(cg->isa->types, mode);
244 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
246 set_entity_ld_ident(res, get_entity_ident(res));
247 set_entity_visibility(res, visibility_local);
248 set_entity_variability(res, variability_constant);
249 set_entity_allocation(res, allocation_static);
251 /* we create a new entity here: It's initialization must resist on the
253 rem = current_ir_graph;
254 current_ir_graph = get_const_code_irg();
255 set_atomic_ent_value(res, new_Const_type(tv, tp));
256 current_ir_graph = rem;
258 pmap_insert(cg->isa->tv_ent, tv, res);
267 * Transforms a Const.
269 static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) {
270 ir_graph *irg = env->irg;
271 ir_node *block = transform_node(env, get_nodes_block(node));
272 dbg_info *dbgi = get_irn_dbg_info(node);
273 ir_mode *mode = get_irn_mode(node);
275 if (mode_is_float(mode)) {
277 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
278 ir_node *nomem = new_NoMem();
283 if (! USE_SSE2(env->cg)) {
284 cnst_classify_t clss = classify_Const(node);
286 if (clss == CNST_NULL) {
287 load = new_rd_ia32_vfldz(dbgi, irg, block);
289 } else if (clss == CNST_ONE) {
290 load = new_rd_ia32_vfld1(dbgi, irg, block);
293 floatent = get_entity_for_tv(env->cg, node);
295 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem);
296 set_ia32_am_support(load, ia32_am_Source);
297 set_ia32_op_type(load, ia32_AddrModeS);
298 set_ia32_am_flavour(load, ia32_am_N);
299 set_ia32_am_sc(load, floatent);
300 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
302 set_ia32_ls_mode(load, mode);
304 floatent = get_entity_for_tv(env->cg, node);
306 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
307 set_ia32_am_support(load, ia32_am_Source);
308 set_ia32_op_type(load, ia32_AddrModeS);
309 set_ia32_am_flavour(load, ia32_am_N);
310 set_ia32_am_sc(load, floatent);
311 set_ia32_ls_mode(load, mode);
313 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
316 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
318 /* Const Nodes before the initial IncSP are a bad idea, because
319 * they could be spilled and we have no SP ready at that point yet
321 if (get_irg_start_block(irg) == block) {
322 add_irn_dep(load, get_irg_frame(irg));
325 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
328 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
331 if (get_irg_start_block(irg) == block) {
332 add_irn_dep(cnst, get_irg_frame(irg));
335 set_ia32_Const_attr(cnst, node);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
341 return new_r_Bad(irg);
345 * Transforms a SymConst.
347 static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) {
348 ir_graph *irg = env->irg;
349 ir_node *block = transform_node(env, get_nodes_block(node));
350 dbg_info *dbgi = get_irn_dbg_info(node);
351 ir_mode *mode = get_irn_mode(node);
354 if (mode_is_float(mode)) {
356 if (USE_SSE2(env->cg))
357 cnst = new_rd_ia32_xConst(dbgi, irg, block);
359 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
360 set_ia32_ls_mode(cnst, mode);
362 cnst = new_rd_ia32_Const(dbgi, irg, block);
365 /* Const Nodes before the initial IncSP are a bad idea, because
366 * they could be spilled and we have no SP ready at that point yet
368 if (get_irg_start_block(irg) == block) {
369 add_irn_dep(cnst, get_irg_frame(irg));
372 set_ia32_Const_attr(cnst, node);
373 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
379 * SSE convert of an integer node into a floating point node.
381 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbgi,
382 ir_graph *irg, ir_node *block,
383 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
385 ir_node *noreg = ia32_new_NoReg_gp(cg);
386 ir_node *nomem = new_rd_NoMem(irg);
387 ir_node *old_pred = get_Cmp_left(old_node);
388 ir_mode *in_mode = get_irn_mode(old_pred);
389 int in_bits = get_mode_size_bits(in_mode);
390 ir_node *conv = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, in, nomem);
392 set_ia32_ls_mode(conv, tgt_mode);
394 set_ia32_am_support(conv, ia32_am_Source);
396 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
402 * SSE convert of an float node into a double node.
404 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbgi,
405 ir_graph *irg, ir_node *block,
406 ir_node *in, ir_node *old_node)
408 ir_node *noreg = ia32_new_NoReg_gp(cg);
409 ir_node *nomem = new_rd_NoMem(irg);
410 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, in, nomem);
412 set_ia32_am_support(conv, ia32_am_Source);
413 set_ia32_ls_mode(conv, mode_xmm);
414 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
419 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
420 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
421 static const struct {
423 const char *ent_name;
424 const char *cnst_str;
425 } names [ia32_known_const_max] = {
426 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
427 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
428 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
429 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
431 static ir_entity *ent_cache[ia32_known_const_max];
433 const char *tp_name, *ent_name, *cnst_str;
441 ent_name = names[kct].ent_name;
442 if (! ent_cache[kct]) {
443 tp_name = names[kct].tp_name;
444 cnst_str = names[kct].cnst_str;
446 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
448 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
449 tp = new_type_primitive(new_id_from_str(tp_name), mode);
450 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
452 set_entity_ld_ident(ent, get_entity_ident(ent));
453 set_entity_visibility(ent, visibility_local);
454 set_entity_variability(ent, variability_constant);
455 set_entity_allocation(ent, allocation_static);
457 /* we create a new entity here: It's initialization must resist on the
459 rem = current_ir_graph;
460 current_ir_graph = get_const_code_irg();
461 cnst = new_Const(mode, tv);
462 current_ir_graph = rem;
464 set_atomic_ent_value(ent, cnst);
466 /* cache the entry */
467 ent_cache[kct] = ent;
470 return ent_cache[kct];
475 * Prints the old node name on cg obst and returns a pointer to it.
477 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
478 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
480 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
481 obstack_1grow(isa->name_obst, 0);
482 return obstack_finish(isa->name_obst);
486 /* determine if one operator is an Imm */
487 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
489 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
491 return is_ia32_Cnst(op2) ? op2 : NULL;
495 /* determine if one operator is not an Imm */
496 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
497 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
500 static void fold_immediate(ia32_transform_env_t *env, ir_node *node, int in1, int in2) {
504 if (! (env->cg->opt & IA32_OPT_IMMOPS))
507 left = get_irn_n(node, in1);
508 right = get_irn_n(node, in2);
509 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
510 /* we can only set right operand to immediate */
511 if(!is_ia32_commutative(node))
513 /* exchange left/right */
514 set_irn_n(node, in1, right);
515 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
516 copy_ia32_Immop_attr(node, left);
517 } else if(is_ia32_Cnst(right)) {
518 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
519 copy_ia32_Immop_attr(node, right);
524 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
528 * Construct a standard binary operation, set AM and immediate if required.
530 * @param env The transformation environment
531 * @param op1 The first operand
532 * @param op2 The second operand
533 * @param func The node constructor function
534 * @return The constructed ia32 node.
536 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *node,
537 ir_node *op1, ir_node *op2,
538 construct_binop_func *func)
540 ir_node *block = transform_node(env, get_nodes_block(node));
541 ir_node *new_op1 = transform_node(env, op1);
542 ir_node *new_op2 = transform_node(env, op2);
543 ir_node *new_node = NULL;
544 ir_graph *irg = env->irg;
545 dbg_info *dbgi = get_irn_dbg_info(node);
546 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
547 ir_node *nomem = new_NoMem();
549 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
550 if (func == new_rd_ia32_IMul) {
551 set_ia32_am_support(new_node, ia32_am_Source);
553 set_ia32_am_support(new_node, ia32_am_Full);
556 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
557 if (is_op_commutative(get_irn_op(node))) {
558 set_ia32_commutative(new_node);
560 fold_immediate(env, new_node, 2, 3);
566 * Construct a standard binary operation, set AM and immediate if required.
568 * @param env The transformation environment
569 * @param op1 The first operand
570 * @param op2 The second operand
571 * @param func The node constructor function
572 * @return The constructed ia32 node.
574 static ir_node *gen_binop_float(ia32_transform_env_t *env, ir_node *node,
575 ir_node *op1, ir_node *op2,
576 construct_binop_func *func)
578 ir_node *block = transform_node(env, get_nodes_block(node));
579 ir_node *new_op1 = transform_node(env, op1);
580 ir_node *new_op2 = transform_node(env, op2);
581 ir_node *new_node = NULL;
582 dbg_info *dbgi = get_irn_dbg_info(node);
583 ir_graph *irg = env->irg;
584 ir_mode *mode = get_irn_mode(node);
585 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
586 ir_node *nomem = new_NoMem();
588 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
589 set_ia32_am_support(new_node, ia32_am_Source);
590 if (is_op_commutative(get_irn_op(node))) {
591 set_ia32_commutative(new_node);
593 if (USE_SSE2(env->cg)) {
594 set_ia32_ls_mode(new_node, mode);
597 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
604 * Construct a shift/rotate binary operation, sets AM and immediate if required.
606 * @param env The transformation environment
607 * @param op1 The first operand
608 * @param op2 The second operand
609 * @param func The node constructor function
610 * @return The constructed ia32 node.
612 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node,
613 ir_node *op1, ir_node *op2,
614 construct_binop_func *func)
616 ir_node *block = transform_node(env, get_nodes_block(node));
617 ir_node *new_op1 = transform_node(env, op1);
618 ir_node *new_op2 = transform_node(env, op2);
619 ir_node *new_op = NULL;
620 dbg_info *dbgi = get_irn_dbg_info(node);
621 ir_graph *irg = env->irg;
622 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
623 ir_node *nomem = new_NoMem();
628 assert(! mode_is_float(get_irn_mode(node))
629 && "Shift/Rotate with float not supported");
631 /* Check if immediate optimization is on and */
632 /* if it's an operation with immediate. */
633 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
634 expr_op = get_expr_op(new_op1, new_op2);
636 assert((expr_op || imm_op) && "invalid operands");
639 /* We have two consts here: not yet supported */
643 /* Limit imm_op within range imm8 */
645 tv = get_ia32_Immop_tarval(imm_op);
648 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
649 set_ia32_Immop_tarval(imm_op, tv);
656 /* integer operations */
658 /* This is shift/rot with const */
659 DB((dbg, LEVEL_1, "Shift/Rot with immediate ..."));
661 new_op = func(dbgi, irg, block, noreg, noreg, expr_op, noreg, nomem);
662 copy_ia32_Immop_attr(new_op, imm_op);
664 /* This is a normal shift/rot */
665 DB((dbg, LEVEL_1, "Shift/Rot binop ..."));
666 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
670 set_ia32_am_support(new_op, ia32_am_Dest);
672 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
674 set_ia32_emit_cl(new_op);
681 * Construct a standard unary operation, set AM and immediate if required.
683 * @param env The transformation environment
684 * @param op The operand
685 * @param func The node constructor function
686 * @return The constructed ia32 node.
688 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *node, ir_node *op,
689 construct_unop_func *func)
691 ir_node *block = transform_node(env, get_nodes_block(node));
692 ir_node *new_op = transform_node(env, op);
693 ir_node *new_node = NULL;
694 ir_graph *irg = env->irg;
695 dbg_info *dbgi = get_irn_dbg_info(node);
696 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
697 ir_node *nomem = new_NoMem();
699 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
700 DB((dbg, LEVEL_1, "INT unop ..."));
701 set_ia32_am_support(new_node, ia32_am_Dest);
703 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
710 * Creates an ia32 Add.
712 * @param env The transformation environment
713 * @return the created ia32 Add node
715 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) {
716 ir_node *block = transform_node(env, get_nodes_block(node));
717 ir_node *op1 = get_Add_left(node);
718 ir_node *new_op1 = transform_node(env, op1);
719 ir_node *op2 = get_Add_right(node);
720 ir_node *new_op2 = transform_node(env, op2);
721 ir_node *new_op = NULL;
722 ir_graph *irg = env->irg;
723 dbg_info *dbgi = get_irn_dbg_info(node);
724 ir_mode *mode = get_irn_mode(node);
725 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
726 ir_node *nomem = new_NoMem();
727 ir_node *expr_op, *imm_op;
729 /* Check if immediate optimization is on and */
730 /* if it's an operation with immediate. */
731 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
732 expr_op = get_expr_op(new_op1, new_op2);
734 assert((expr_op || imm_op) && "invalid operands");
736 if (mode_is_float(mode)) {
738 if (USE_SSE2(env->cg))
739 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xAdd);
741 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfadd);
746 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
747 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
749 /* No expr_op means, that we have two const - one symconst and */
750 /* one tarval or another symconst - because this case is not */
751 /* covered by constant folding */
752 /* We need to check for: */
753 /* 1) symconst + const -> becomes a LEA */
754 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
755 /* linker doesn't support two symconsts */
757 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
758 /* this is the 2nd case */
759 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
760 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
761 set_ia32_am_flavour(new_op, ia32_am_OB);
762 set_ia32_am_support(new_op, ia32_am_Source);
763 set_ia32_op_type(new_op, ia32_AddrModeS);
765 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
766 } else if (tp1 == ia32_ImmSymConst) {
767 tarval *tv = get_ia32_Immop_tarval(new_op2);
768 long offs = get_tarval_long(tv);
770 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
771 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
773 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
774 add_ia32_am_offs_int(new_op, offs);
775 set_ia32_am_flavour(new_op, ia32_am_O);
776 set_ia32_am_support(new_op, ia32_am_Source);
777 set_ia32_op_type(new_op, ia32_AddrModeS);
778 } else if (tp2 == ia32_ImmSymConst) {
779 tarval *tv = get_ia32_Immop_tarval(new_op1);
780 long offs = get_tarval_long(tv);
782 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
783 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
785 add_ia32_am_offs_int(new_op, offs);
786 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
787 set_ia32_am_flavour(new_op, ia32_am_O);
788 set_ia32_am_support(new_op, ia32_am_Source);
789 set_ia32_op_type(new_op, ia32_AddrModeS);
791 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
792 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
793 tarval *restv = tarval_add(tv1, tv2);
795 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
797 new_op = new_rd_ia32_Const(dbgi, irg, block);
798 set_ia32_Const_tarval(new_op, restv);
799 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
802 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
805 if ((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
806 tarval_classification_t class_tv, class_negtv;
807 tarval *tv = get_ia32_Immop_tarval(imm_op);
809 /* optimize tarvals */
810 class_tv = classify_tarval(tv);
811 class_negtv = classify_tarval(tarval_neg(tv));
813 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
814 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
815 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
816 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
818 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
819 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
820 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
821 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
827 /* This is a normal add */
828 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
831 set_ia32_am_support(new_op, ia32_am_Full);
832 set_ia32_commutative(new_op);
834 fold_immediate(env, new_op, 2, 3);
836 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
842 static ir_node *create_ia32_Mul(ia32_transform_env_t *env, ir_node *node) {
843 ir_graph *irg = env->irg;
844 dbg_info *dbgi = get_irn_dbg_info(node);
845 ir_node *block = transform_node(env, get_nodes_block(node));
846 ir_node *op1 = get_Mul_left(node);
847 ir_node *op2 = get_Mul_right(node);
848 ir_node *new_op1 = transform_node(env, op1);
849 ir_node *new_op2 = transform_node(env, op2);
850 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
851 ir_node *proj_EAX, *proj_EDX, *res;
854 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
855 set_ia32_commutative(res);
856 set_ia32_am_support(res, ia32_am_Source);
858 /* imediates are not supported, so no fold_immediate */
859 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
860 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
864 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
872 * Creates an ia32 Mul.
874 * @param env The transformation environment
875 * @return the created ia32 Mul node
877 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) {
878 ir_node *op1 = get_Mul_left(node);
879 ir_node *op2 = get_Mul_right(node);
880 ir_mode *mode = get_irn_mode(node);
882 if (mode_is_float(mode)) {
884 if (USE_SSE2(env->cg))
885 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul);
887 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul);
891 for the lower 32bit of the result it doesn't matter whether we use
892 signed or unsigned multiplication so we use IMul as it has fewer
895 return gen_binop(env, node, op1, op2, new_rd_ia32_IMul);
899 * Creates an ia32 Mulh.
900 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
901 * this result while Mul returns the lower 32 bit.
903 * @param env The transformation environment
904 * @return the created ia32 Mulh node
906 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) {
907 ir_node *block = transform_node(env, get_nodes_block(node));
908 ir_node *op1 = get_irn_n(node, 0);
909 ir_node *new_op1 = transform_node(env, op1);
910 ir_node *op2 = get_irn_n(node, 1);
911 ir_node *new_op2 = transform_node(env, op2);
912 ir_graph *irg = env->irg;
913 dbg_info *dbgi = get_irn_dbg_info(node);
914 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
915 ir_mode *mode = get_irn_mode(node);
916 ir_node *proj_EAX, *proj_EDX, *res;
919 assert(!mode_is_float(mode) && "Mulh with float not supported");
920 if (mode_is_signed(mode)) {
921 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
923 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
926 set_ia32_commutative(res);
927 set_ia32_am_support(res, ia32_am_Source);
929 set_ia32_am_support(res, ia32_am_Source);
931 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
932 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
936 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
944 * Creates an ia32 And.
946 * @param env The transformation environment
947 * @return The created ia32 And node
949 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *node) {
950 ir_node *op1 = get_And_left(node);
951 ir_node *op2 = get_And_right(node);
953 assert (! mode_is_float(get_irn_mode(node)));
954 return gen_binop(env, node, op1, op2, new_rd_ia32_And);
960 * Creates an ia32 Or.
962 * @param env The transformation environment
963 * @return The created ia32 Or node
965 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *node) {
966 ir_node *op1 = get_Or_left(node);
967 ir_node *op2 = get_Or_right(node);
969 assert (! mode_is_float(get_irn_mode(node)));
970 return gen_binop(env, node, op1, op2, new_rd_ia32_Or);
976 * Creates an ia32 Eor.
978 * @param env The transformation environment
979 * @return The created ia32 Eor node
981 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *node) {
982 ir_node *op1 = get_Eor_left(node);
983 ir_node *op2 = get_Eor_right(node);
985 assert(! mode_is_float(get_irn_mode(node)));
986 return gen_binop(env, node, op1, op2, new_rd_ia32_Xor);
992 * Creates an ia32 Max.
994 * @param env The transformation environment
995 * @return the created ia32 Max node
997 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *node) {
998 ir_node *block = transform_node(env, get_nodes_block(node));
999 ir_node *op1 = get_irn_n(node, 0);
1000 ir_node *new_op1 = transform_node(env, op1);
1001 ir_node *op2 = get_irn_n(node, 1);
1002 ir_node *new_op2 = transform_node(env, op2);
1003 ir_graph *irg = env->irg;
1004 ir_mode *mode = get_irn_mode(node);
1005 dbg_info *dbgi = get_irn_dbg_info(node);
1006 ir_mode *op_mode = get_irn_mode(op1);
1009 assert(get_mode_size_bits(mode) == 32);
1011 if (mode_is_float(mode)) {
1013 if (USE_SSE2(env->cg)) {
1014 new_op = gen_binop_float(env, node, new_op1, new_op2, new_rd_ia32_xMax);
1016 panic("Can't create Max node");
1019 long pnc = pn_Cmp_Gt;
1020 if (! mode_is_signed(op_mode)) {
1021 pnc |= ia32_pn_Cmp_Unsigned;
1023 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1024 set_ia32_pncode(new_op, pnc);
1025 set_ia32_am_support(new_op, ia32_am_None);
1027 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1033 * Creates an ia32 Min.
1035 * @param env The transformation environment
1036 * @return the created ia32 Min node
1038 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *node) {
1039 ir_node *block = transform_node(env, get_nodes_block(node));
1040 ir_node *op1 = get_irn_n(node, 0);
1041 ir_node *new_op1 = transform_node(env, op1);
1042 ir_node *op2 = get_irn_n(node, 1);
1043 ir_node *new_op2 = transform_node(env, op2);
1044 ir_graph *irg = env->irg;
1045 ir_mode *mode = get_irn_mode(node);
1046 dbg_info *dbgi = get_irn_dbg_info(node);
1047 ir_mode *op_mode = get_irn_mode(op1);
1050 assert(get_mode_size_bits(mode) == 32);
1052 if (mode_is_float(mode)) {
1054 if (USE_SSE2(env->cg)) {
1055 new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMin);
1057 panic("can't create Min node");
1060 long pnc = pn_Cmp_Lt;
1061 if (! mode_is_signed(op_mode)) {
1062 pnc |= ia32_pn_Cmp_Unsigned;
1064 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1065 set_ia32_pncode(new_op, pnc);
1066 set_ia32_am_support(new_op, ia32_am_None);
1068 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1075 * Creates an ia32 Sub.
1077 * @param env The transformation environment
1078 * @return The created ia32 Sub node
1080 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) {
1081 ir_node *block = transform_node(env, get_nodes_block(node));
1082 ir_node *op1 = get_Sub_left(node);
1083 ir_node *new_op1 = transform_node(env, op1);
1084 ir_node *op2 = get_Sub_right(node);
1085 ir_node *new_op2 = transform_node(env, op2);
1086 ir_node *new_op = NULL;
1087 ir_graph *irg = env->irg;
1088 dbg_info *dbgi = get_irn_dbg_info(node);
1089 ir_mode *mode = get_irn_mode(node);
1090 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1091 ir_node *nomem = new_NoMem();
1092 ir_node *expr_op, *imm_op;
1094 /* Check if immediate optimization is on and */
1095 /* if it's an operation with immediate. */
1096 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1097 expr_op = get_expr_op(new_op1, new_op2);
1099 assert((expr_op || imm_op) && "invalid operands");
1101 if (mode_is_float(mode)) {
1103 if (USE_SSE2(env->cg))
1104 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xSub);
1106 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfsub);
1111 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1112 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1114 /* No expr_op means, that we have two const - one symconst and */
1115 /* one tarval or another symconst - because this case is not */
1116 /* covered by constant folding */
1117 /* We need to check for: */
1118 /* 1) symconst - const -> becomes a LEA */
1119 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1120 /* linker doesn't support two symconsts */
1121 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1122 /* this is the 2nd case */
1123 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1124 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1125 set_ia32_am_sc_sign(new_op);
1126 set_ia32_am_flavour(new_op, ia32_am_OB);
1128 DBG_OPT_LEA3(op1, op2, node, new_op);
1129 } else if (tp1 == ia32_ImmSymConst) {
1130 tarval *tv = get_ia32_Immop_tarval(new_op2);
1131 long offs = get_tarval_long(tv);
1133 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1134 DBG_OPT_LEA3(op1, op2, node, new_op);
1136 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1137 add_ia32_am_offs_int(new_op, -offs);
1138 set_ia32_am_flavour(new_op, ia32_am_O);
1139 set_ia32_am_support(new_op, ia32_am_Source);
1140 set_ia32_op_type(new_op, ia32_AddrModeS);
1141 } else if (tp2 == ia32_ImmSymConst) {
1142 tarval *tv = get_ia32_Immop_tarval(new_op1);
1143 long offs = get_tarval_long(tv);
1145 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1146 DBG_OPT_LEA3(op1, op2, node, new_op);
1148 add_ia32_am_offs_int(new_op, offs);
1149 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1150 set_ia32_am_sc_sign(new_op);
1151 set_ia32_am_flavour(new_op, ia32_am_O);
1152 set_ia32_am_support(new_op, ia32_am_Source);
1153 set_ia32_op_type(new_op, ia32_AddrModeS);
1155 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1156 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1157 tarval *restv = tarval_sub(tv1, tv2);
1159 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1161 new_op = new_rd_ia32_Const(dbgi, irg, block);
1162 set_ia32_Const_tarval(new_op, restv);
1163 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1166 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1168 } else if (imm_op) {
1169 if ((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1170 tarval_classification_t class_tv, class_negtv;
1171 tarval *tv = get_ia32_Immop_tarval(imm_op);
1173 /* optimize tarvals */
1174 class_tv = classify_tarval(tv);
1175 class_negtv = classify_tarval(tarval_neg(tv));
1177 if (class_tv == TV_CLASSIFY_ONE) {
1178 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1179 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1180 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1182 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1183 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1184 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1185 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1191 /* This is a normal sub */
1192 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1194 /* set AM support */
1195 set_ia32_am_support(new_op, ia32_am_Full);
1197 fold_immediate(env, new_op, 2, 3);
1199 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1207 * Generates an ia32 DivMod with additional infrastructure for the
1208 * register allocator if needed.
1210 * @param env The transformation environment
1211 * @param dividend -no comment- :)
1212 * @param divisor -no comment- :)
1213 * @param dm_flav flavour_Div/Mod/DivMod
1214 * @return The created ia32 DivMod node
1216 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *node,
1217 ir_node *dividend, ir_node *divisor,
1218 ia32_op_flavour_t dm_flav)
1220 ir_node *block = transform_node(env, get_nodes_block(node));
1221 ir_node *new_dividend = transform_node(env, dividend);
1222 ir_node *new_divisor = transform_node(env, divisor);
1223 ir_graph *irg = env->irg;
1224 dbg_info *dbgi = get_irn_dbg_info(node);
1225 ir_mode *mode = get_irn_mode(node);
1226 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1227 ir_node *res, *proj_div, *proj_mod;
1228 ir_node *edx_node, *cltd;
1229 ir_node *in_keep[2];
1230 ir_node *mem, *new_mem;
1231 ir_node *projs[pn_DivMod_max];
1234 ia32_collect_Projs(node, projs, pn_DivMod_max);
1236 proj_div = proj_mod = NULL;
1240 mem = get_Div_mem(node);
1241 mode = get_Div_resmode(node);
1242 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1243 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1246 mem = get_Mod_mem(node);
1247 mode = get_Mod_resmode(node);
1248 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1249 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1251 case flavour_DivMod:
1252 mem = get_DivMod_mem(node);
1253 mode = get_DivMod_resmode(node);
1254 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1255 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1256 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1259 panic("invalid divmod flavour!");
1261 new_mem = transform_node(env, mem);
1263 if (mode_is_signed(mode)) {
1264 /* in signed mode, we need to sign extend the dividend */
1265 cltd = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1266 new_dividend = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1267 edx_node = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1269 edx_node = new_rd_ia32_Const(dbgi, irg, block);
1270 add_irn_dep(edx_node, be_abi_get_start_barrier(env->cg->birg->abi));
1271 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1274 if (mode_is_signed(mode)) {
1275 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1277 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1280 set_ia32_exc_label(res, has_exc);
1282 /* Matze: code can't handle this at the moment... */
1284 /* set AM support */
1285 set_ia32_am_support(res, ia32_am_Source);
1288 set_ia32_n_res(res, 2);
1290 /* check, which Proj-Keep, we need to add */
1292 if (proj_div == NULL) {
1293 /* We have only mod result: add div res Proj-Keep */
1294 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1297 if (proj_mod == NULL) {
1298 /* We have only div result: add mod res Proj-Keep */
1299 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1303 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1305 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1312 * Wrapper for generate_DivMod. Sets flavour_Mod.
1314 * @param env The transformation environment
1316 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *node) {
1317 return generate_DivMod(env, node, get_Mod_left(node),
1318 get_Mod_right(node), flavour_Mod);
1322 * Wrapper for generate_DivMod. Sets flavour_Div.
1324 * @param env The transformation environment
1326 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *node) {
1327 return generate_DivMod(env, node, get_Div_left(node),
1328 get_Div_right(node), flavour_Div);
1332 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1334 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *node) {
1335 return generate_DivMod(env, node, get_DivMod_left(node),
1336 get_DivMod_right(node), flavour_DivMod);
1342 * Creates an ia32 floating Div.
1344 * @param env The transformation environment
1345 * @return The created ia32 xDiv node
1347 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *node) {
1348 ir_node *block = transform_node(env, get_nodes_block(node));
1349 ir_node *op1 = get_Quot_left(node);
1350 ir_node *new_op1 = transform_node(env, op1);
1351 ir_node *op2 = get_Quot_right(node);
1352 ir_node *new_op2 = transform_node(env, op2);
1353 ir_graph *irg = env->irg;
1354 dbg_info *dbgi = get_irn_dbg_info(node);
1355 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1356 ir_node *nomem = new_rd_NoMem(env->irg);
1360 if (USE_SSE2(env->cg)) {
1361 ir_mode *mode = get_irn_mode(op1);
1362 if (is_ia32_xConst(new_op2)) {
1363 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1364 set_ia32_am_support(new_op, ia32_am_None);
1365 copy_ia32_Immop_attr(new_op, new_op2);
1367 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1368 // Matze: disabled for now, spillslot coalescer fails
1369 //set_ia32_am_support(new_op, ia32_am_Source);
1371 set_ia32_ls_mode(new_op, mode);
1373 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1374 // Matze: disabled for now (spillslot coalescer fails)
1375 //set_ia32_am_support(new_op, ia32_am_Source);
1377 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1383 * Creates an ia32 Shl.
1385 * @param env The transformation environment
1386 * @return The created ia32 Shl node
1388 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *node) {
1389 return gen_shift_binop(env, node, get_Shl_left(node), get_Shl_right(node),
1396 * Creates an ia32 Shr.
1398 * @param env The transformation environment
1399 * @return The created ia32 Shr node
1401 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *node) {
1402 return gen_shift_binop(env, node, get_Shr_left(node),
1403 get_Shr_right(node), new_rd_ia32_Shr);
1409 * Creates an ia32 Sar.
1411 * @param env The transformation environment
1412 * @return The created ia32 Shrs node
1414 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) {
1415 return gen_shift_binop(env, node, get_Shrs_left(node),
1416 get_Shrs_right(node), new_rd_ia32_Sar);
1422 * Creates an ia32 RotL.
1424 * @param env The transformation environment
1425 * @param op1 The first operator
1426 * @param op2 The second operator
1427 * @return The created ia32 RotL node
1429 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node,
1430 ir_node *op1, ir_node *op2) {
1431 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Rol);
1437 * Creates an ia32 RotR.
1438 * NOTE: There is no RotR with immediate because this would always be a RotL
1439 * "imm-mode_size_bits" which can be pre-calculated.
1441 * @param env The transformation environment
1442 * @param op1 The first operator
1443 * @param op2 The second operator
1444 * @return The created ia32 RotR node
1446 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1,
1448 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Ror);
1454 * Creates an ia32 RotR or RotL (depending on the found pattern).
1456 * @param env The transformation environment
1457 * @return The created ia32 RotL or RotR node
1459 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) {
1460 ir_node *rotate = NULL;
1461 ir_node *op1 = get_Rot_left(node);
1462 ir_node *op2 = get_Rot_right(node);
1464 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1465 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1466 that means we can create a RotR instead of an Add and a RotL */
1468 if (get_irn_op(op2) == op_Add) {
1470 ir_node *left = get_Add_left(add);
1471 ir_node *right = get_Add_right(add);
1472 if (is_Const(right)) {
1473 tarval *tv = get_Const_tarval(right);
1474 ir_mode *mode = get_irn_mode(node);
1475 long bits = get_mode_size_bits(mode);
1477 if (get_irn_op(left) == op_Minus &&
1478 tarval_is_long(tv) &&
1479 get_tarval_long(tv) == bits)
1481 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1482 rotate = gen_RotR(env, node, op1, get_Minus_op(left));
1487 if (rotate == NULL) {
1488 rotate = gen_RotL(env, node, op1, op2);
1497 * Transforms a Minus node.
1499 * @param env The transformation environment
1500 * @param op The Minus operand
1501 * @return The created ia32 Minus node
1503 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *node, ir_node *op) {
1504 ir_node *block = transform_node(env, get_nodes_block(node));
1505 ir_graph *irg = env->irg;
1506 dbg_info *dbgi = get_irn_dbg_info(node);
1507 ir_mode *mode = get_irn_mode(node);
1512 if (mode_is_float(mode)) {
1513 ir_node *new_op = transform_node(env, op);
1515 if (USE_SSE2(env->cg)) {
1516 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1517 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1518 ir_node *nomem = new_rd_NoMem(irg);
1520 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1522 size = get_mode_size_bits(mode);
1523 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1525 set_ia32_am_sc(res, ent);
1526 set_ia32_op_type(res, ia32_AddrModeS);
1527 set_ia32_ls_mode(res, mode);
1529 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1532 res = gen_unop(env, node, op, new_rd_ia32_Neg);
1535 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1541 * Transforms a Minus node.
1543 * @param env The transformation environment
1544 * @return The created ia32 Minus node
1546 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *node) {
1547 return gen_Minus_ex(env, node, get_Minus_op(node));
1552 * Transforms a Not node.
1554 * @param env The transformation environment
1555 * @return The created ia32 Not node
1557 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *node) {
1558 ir_node *op = get_Not_op(node);
1560 assert (! mode_is_float(get_irn_mode(node)));
1561 return gen_unop(env, node, op, new_rd_ia32_Not);
1567 * Transforms an Abs node.
1569 * @param env The transformation environment
1570 * @return The created ia32 Abs node
1572 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *node) {
1573 ir_node *block = transform_node(env, get_nodes_block(node));
1574 ir_node *op = get_Abs_op(node);
1575 ir_node *new_op = transform_node(env, op);
1576 ir_graph *irg = env->irg;
1577 dbg_info *dbgi = get_irn_dbg_info(node);
1578 ir_mode *mode = get_irn_mode(node);
1579 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1580 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1581 ir_node *nomem = new_NoMem();
1582 ir_node *res, *p_eax, *p_edx;
1586 if (mode_is_float(mode)) {
1588 if (USE_SSE2(env->cg)) {
1589 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1591 size = get_mode_size_bits(mode);
1592 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1594 set_ia32_am_sc(res, ent);
1596 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1598 set_ia32_op_type(res, ia32_AddrModeS);
1599 set_ia32_ls_mode(res, mode);
1602 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1603 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1607 res = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1608 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1610 p_eax = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
1611 p_edx = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1613 res = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1614 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1616 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1617 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1626 * Transforms a Load.
1628 * @param env The transformation environment
1629 * @return the created ia32 Load node
1631 static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) {
1632 ir_node *block = transform_node(env, get_nodes_block(node));
1633 ir_node *ptr = get_Load_ptr(node);
1634 ir_node *new_ptr = transform_node(env, ptr);
1635 ir_node *mem = get_Load_mem(node);
1636 ir_node *new_mem = transform_node(env, mem);
1637 ir_graph *irg = env->irg;
1638 dbg_info *dbgi = get_irn_dbg_info(node);
1639 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1640 ir_mode *mode = get_Load_mode(node);
1641 ir_node *lptr = new_ptr;
1644 ir_node *projs[pn_Load_max];
1645 ia32_am_flavour_t am_flav = ia32_am_B;
1647 ia32_collect_Projs(node, projs, pn_Load_max);
1650 check for special case: the loaded value might not be used (optimized, volatile, ...)
1651 we add a Proj + Keep for volatile loads and ignore all other cases
1653 if (! be_get_Proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1654 /* add a result proj and a Keep to produce a pseudo use */
1655 ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res);
1656 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), irg, block, 1, &proj);
1659 /* address might be a constant (symconst or absolute address) */
1660 if (is_ia32_Const(new_ptr)) {
1665 if (mode_is_float(mode)) {
1667 if (USE_SSE2(env->cg)) {
1668 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1670 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem);
1673 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1676 /* base is a constant address */
1678 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1679 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1680 am_flav = ia32_am_N;
1682 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1683 long offs = get_tarval_long(tv);
1685 add_ia32_am_offs_int(new_op, offs);
1686 am_flav = ia32_am_O;
1690 set_ia32_am_support(new_op, ia32_am_Source);
1691 set_ia32_op_type(new_op, ia32_AddrModeS);
1692 set_ia32_am_flavour(new_op, am_flav);
1693 set_ia32_ls_mode(new_op, mode);
1695 /* make sure we are scheduled behind the initial IncSP/Barrier
1696 * to avoid spills being placed before it
1698 if (block == get_irg_start_block(irg)) {
1699 add_irn_dep(new_op, get_irg_frame(irg));
1702 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1710 * Transforms a Store.
1712 * @param env The transformation environment
1713 * @return the created ia32 Store node
1715 static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) {
1716 ir_node *block = transform_node(env, get_nodes_block(node));
1717 ir_node *ptr = get_Store_ptr(node);
1718 ir_node *new_ptr = transform_node(env, ptr);
1719 ir_node *val = get_Store_value(node);
1720 ir_node *new_val = transform_node(env, val);
1721 ir_node *mem = get_Store_mem(node);
1722 ir_node *new_mem = transform_node(env, mem);
1723 ir_graph *irg = env->irg;
1724 dbg_info *dbgi = get_irn_dbg_info(node);
1725 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1726 ir_node *sptr = new_ptr;
1727 ir_mode *mode = get_irn_mode(val);
1728 ir_node *sval = new_val;
1731 ia32_am_flavour_t am_flav = ia32_am_B;
1733 if (is_ia32_Const(new_val)) {
1734 assert(!mode_is_float(mode));
1738 /* address might be a constant (symconst or absolute address) */
1739 if (is_ia32_Const(new_ptr)) {
1744 if (mode_is_float(mode)) {
1746 if (USE_SSE2(env->cg)) {
1747 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, sval, new_mem);
1749 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, sval, new_mem);
1751 } else if (get_mode_size_bits(mode) == 8) {
1752 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg, sval, new_mem);
1754 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, sval, new_mem);
1757 /* stored const is an immediate value */
1758 if (is_ia32_Const(new_val)) {
1759 assert(!mode_is_float(mode));
1760 copy_ia32_Immop_attr(new_op, new_val);
1763 /* base is an constant address */
1765 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1766 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1767 am_flav = ia32_am_N;
1769 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1770 long offs = get_tarval_long(tv);
1772 add_ia32_am_offs_int(new_op, offs);
1773 am_flav = ia32_am_O;
1777 set_ia32_am_support(new_op, ia32_am_Dest);
1778 set_ia32_op_type(new_op, ia32_AddrModeD);
1779 set_ia32_am_flavour(new_op, am_flav);
1780 set_ia32_ls_mode(new_op, mode);
1782 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1790 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1792 * @param env The transformation environment
1793 * @return The transformed node.
1795 static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) {
1796 ir_node *block = transform_node(env, get_nodes_block(node));
1797 ir_graph *irg = env->irg;
1798 dbg_info *dbgi = get_irn_dbg_info(node);
1799 ir_node *sel = get_Cond_selector(node);
1800 ir_mode *sel_mode = get_irn_mode(sel);
1801 ir_node *res = NULL;
1802 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1803 ir_node *cnst, *expr;
1805 if (is_Proj(sel) && sel_mode == mode_b) {
1806 ir_node *pred = get_Proj_pred(sel);
1807 ir_node *cmp_a = get_Cmp_left(pred);
1808 ir_node *new_cmp_a = transform_node(env, cmp_a);
1809 ir_node *cmp_b = get_Cmp_right(pred);
1810 ir_node *new_cmp_b = transform_node(env, cmp_b);
1811 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1812 ir_node *nomem = new_NoMem();
1814 int pnc = get_Proj_proj(sel);
1815 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1816 pnc |= ia32_pn_Cmp_Unsigned;
1819 /* check if we can use a CondJmp with immediate */
1820 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1821 expr = get_expr_op(new_cmp_a, new_cmp_b);
1823 if (cnst != NULL && expr != NULL) {
1824 /* immop has to be the right operand, we might need to flip pnc */
1825 if(cnst != new_cmp_b) {
1826 pnc = get_inversed_pnc(pnc);
1829 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_needs_gp_reg(get_irn_mode(expr))) {
1830 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1831 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1833 /* a Cmp A =/!= 0 */
1834 ir_node *op1 = expr;
1835 ir_node *op2 = expr;
1838 /* check, if expr is an only once used And operation */
1839 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1840 op1 = get_irn_n(expr, 2);
1841 op2 = get_irn_n(expr, 3);
1843 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1845 res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2);
1846 set_ia32_pncode(res, pnc);
1849 copy_ia32_Immop_attr(res, expr);
1852 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1857 if (mode_is_float(cmp_mode)) {
1859 if (USE_SSE2(env->cg)) {
1860 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1861 set_ia32_ls_mode(res, cmp_mode);
1867 assert(get_mode_size_bits(cmp_mode) == 32);
1868 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1870 copy_ia32_Immop_attr(res, cnst);
1873 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1875 if (mode_is_float(cmp_mode)) {
1877 if (USE_SSE2(env->cg)) {
1878 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1879 set_ia32_ls_mode(res, cmp_mode);
1882 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1883 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1884 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1888 assert(get_mode_size_bits(cmp_mode) == 32);
1889 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1890 set_ia32_commutative(res);
1894 set_ia32_pncode(res, pnc);
1895 // Matze: disabled for now, because the default collect_spills_walker
1896 // is not able to detect the mode of the spilled value
1897 // moreover, the lea optimize phase freely exchanges left/right
1898 // without updating the pnc
1899 //set_ia32_am_support(res, ia32_am_Source);
1902 /* determine the smallest switch case value */
1903 ir_node *new_sel = transform_node(env, sel);
1904 int switch_min = INT_MAX;
1905 const ir_edge_t *edge;
1907 foreach_out_edge(node, edge) {
1908 int pn = get_Proj_proj(get_edge_src_irn(edge));
1909 switch_min = pn < switch_min ? pn : switch_min;
1913 /* if smallest switch case is not 0 we need an additional sub */
1914 res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1915 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1916 add_ia32_am_offs_int(res, -switch_min);
1917 set_ia32_am_flavour(res, ia32_am_OB);
1918 set_ia32_am_support(res, ia32_am_Source);
1919 set_ia32_op_type(res, ia32_AddrModeS);
1922 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T);
1923 set_ia32_pncode(res, get_Cond_defaultProj(node));
1926 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1933 * Transforms a CopyB node.
1935 * @param env The transformation environment
1936 * @return The transformed node.
1938 static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) {
1939 ir_node *block = transform_node(env, get_nodes_block(node));
1940 ir_node *src = get_CopyB_src(node);
1941 ir_node *new_src = transform_node(env, src);
1942 ir_node *dst = get_CopyB_dst(node);
1943 ir_node *new_dst = transform_node(env, dst);
1944 ir_node *mem = get_CopyB_mem(node);
1945 ir_node *new_mem = transform_node(env, mem);
1946 ir_node *res = NULL;
1947 ir_graph *irg = env->irg;
1948 dbg_info *dbgi = get_irn_dbg_info(node);
1949 int size = get_type_size_bytes(get_CopyB_type(node));
1950 ir_mode *dst_mode = get_irn_mode(dst);
1951 ir_mode *src_mode = get_irn_mode(src);
1955 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1956 /* then we need the size explicitly in ECX. */
1957 if (size >= 32 * 4) {
1958 rem = size & 0x3; /* size % 4 */
1961 res = new_rd_ia32_Const(dbgi, irg, block);
1962 add_irn_dep(res, be_abi_get_start_barrier(env->cg->birg->abi));
1963 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1965 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1966 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1968 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1969 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1970 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1971 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1972 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1975 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1976 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1978 /* ok: now attach Proj's because movsd will destroy esi and edi */
1979 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1980 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1981 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1984 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1992 * Transforms a Mux node into CMov.
1994 * @param env The transformation environment
1995 * @return The transformed node.
1997 static ir_node *gen_Mux(ia32_transform_env_t *env, ir_node *node) {
1998 ir_node *new_op = new_rd_ia32_CMov(env->dbgi, env->irg, env->block, \
1999 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
2001 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2007 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
2008 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
2009 ir_node *psi_default);
2012 * Transforms a Psi node into CMov.
2014 * @param env The transformation environment
2015 * @return The transformed node.
2017 static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) {
2018 ir_node *block = transform_node(env, get_nodes_block(node));
2019 ir_node *psi_true = get_Psi_val(node, 0);
2020 ir_node *new_psi_true = transform_node(env, psi_true);
2021 ir_node *psi_default = get_Psi_default(node);
2022 ir_node *new_psi_default = transform_node(env, psi_default);
2023 ia32_code_gen_t *cg = env->cg;
2024 ir_graph *irg = env->irg;
2025 dbg_info *dbgi = get_irn_dbg_info(node);
2026 ir_mode *mode = get_irn_mode(node);
2027 ir_node *cmp_proj = get_Mux_sel(node);
2028 ir_node *noreg = ia32_new_NoReg_gp(cg);
2029 ir_node *nomem = new_rd_NoMem(irg);
2030 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
2031 ir_node *new_cmp_a, *new_cmp_b;
2035 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
2037 cmp = get_Proj_pred(cmp_proj);
2038 cmp_a = get_Cmp_left(cmp);
2039 cmp_b = get_Cmp_right(cmp);
2040 cmp_mode = get_irn_mode(cmp_a);
2041 new_cmp_a = transform_node(env, cmp_a);
2042 new_cmp_b = transform_node(env, cmp_b);
2044 pnc = get_Proj_proj(cmp_proj);
2045 if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2046 pnc |= ia32_pn_Cmp_Unsigned;
2049 if (mode_is_float(mode)) {
2050 /* floating point psi */
2053 /* 1st case: compare operands are float too */
2055 /* psi(cmp(a, b), t, f) can be done as: */
2056 /* tmp = cmp a, b */
2057 /* tmp2 = t and tmp */
2058 /* tmp3 = f and not tmp */
2059 /* res = tmp2 or tmp3 */
2061 /* in case the compare operands are int, we move them into xmm register */
2062 if (! mode_is_float(get_irn_mode(cmp_a))) {
2063 new_cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_a, node, mode_xmm);
2064 new_cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_b, node, mode_xmm);
2066 pnc |= 8; /* transform integer compare to fp compare */
2069 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2070 set_ia32_pncode(new_op, pnc);
2071 set_ia32_am_support(new_op, ia32_am_Source);
2072 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2074 and1 = new_rd_ia32_xAnd(dbgi, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2075 set_ia32_am_support(and1, ia32_am_None);
2076 set_ia32_commutative(and1);
2077 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2079 and2 = new_rd_ia32_xAndNot(dbgi, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2080 set_ia32_am_support(and2, ia32_am_None);
2081 set_ia32_commutative(and2);
2082 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2084 new_op = new_rd_ia32_xOr(dbgi, irg, block, noreg, noreg, and1, and2, nomem);
2085 set_ia32_am_support(new_op, ia32_am_None);
2086 set_ia32_commutative(new_op);
2087 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2091 new_op = new_rd_ia32_vfCMov(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2092 set_ia32_pncode(new_op, pnc);
2093 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2098 construct_binop_func *set_func = NULL;
2099 cmov_func_t *cmov_func = NULL;
2101 if (mode_is_float(get_irn_mode(cmp_a))) {
2102 /* 1st case: compare operands are floats */
2107 set_func = new_rd_ia32_xCmpSet;
2108 cmov_func = new_rd_ia32_xCmpCMov;
2112 set_func = new_rd_ia32_vfCmpSet;
2113 cmov_func = new_rd_ia32_vfCmpCMov;
2116 pnc &= ~0x8; /* fp compare -> int compare */
2119 /* 2nd case: compare operand are integer too */
2120 set_func = new_rd_ia32_CmpSet;
2121 cmov_func = new_rd_ia32_CmpCMov;
2124 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2125 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2126 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2127 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2128 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2129 set_ia32_pncode(new_op, pnc);
2131 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2132 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2133 /* we invert condition and set default to 0 */
2134 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2135 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2138 /* otherwise: use CMOVcc */
2139 new_op = new_rd_ia32_PsiCondCMov(dbgi, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2140 set_ia32_pncode(new_op, pnc);
2143 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2146 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2147 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2148 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2149 set_ia32_pncode(new_op, pnc);
2150 set_ia32_am_support(new_op, ia32_am_Source);
2152 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2153 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2154 /* we invert condition and set default to 0 */
2155 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2156 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2157 set_ia32_am_support(new_op, ia32_am_Source);
2160 /* otherwise: use CMOVcc */
2161 new_op = cmov_func(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2162 set_ia32_pncode(new_op, pnc);
2163 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2173 * Following conversion rules apply:
2177 * 1) n bit -> m bit n > m (downscale)
2179 * 2) n bit -> m bit n == m (sign change)
2181 * 3) n bit -> m bit n < m (upscale)
2182 * a) source is signed: movsx
2183 * b) source is unsigned: and with lower bits sets
2187 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2191 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2195 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2196 * x87 is mode_E internally, conversions happen only at load and store
2197 * in non-strict semantic
2201 * Create a conversion from x87 state register to general purpose.
2203 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) {
2204 ir_node *block = transform_node(env, get_nodes_block(node));
2205 ir_node *op = get_Conv_op(node);
2206 ir_node *new_op = transform_node(env, op);
2207 ia32_code_gen_t *cg = env->cg;
2208 ir_graph *irg = env->irg;
2209 dbg_info *dbgi = get_irn_dbg_info(node);
2210 ir_node *noreg = ia32_new_NoReg_gp(cg);
2211 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2212 ir_node *fist, *load;
2215 fist = new_rd_ia32_vfist(dbgi, irg, block,
2216 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2218 set_ia32_use_frame(fist);
2219 set_ia32_am_support(fist, ia32_am_Dest);
2220 set_ia32_op_type(fist, ia32_AddrModeD);
2221 set_ia32_am_flavour(fist, ia32_am_B);
2222 set_ia32_ls_mode(fist, mode_Iu);
2223 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2226 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2228 set_ia32_use_frame(load);
2229 set_ia32_am_support(load, ia32_am_Source);
2230 set_ia32_op_type(load, ia32_AddrModeS);
2231 set_ia32_am_flavour(load, ia32_am_B);
2232 set_ia32_ls_mode(load, mode_Iu);
2233 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2235 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2239 * Create a conversion from general purpose to x87 register
2241 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mode *src_mode) {
2242 ir_node *block = transform_node(env, get_nodes_block(node));
2243 ir_node *op = get_Conv_op(node);
2244 ir_node *new_op = transform_node(env, op);
2245 ir_graph *irg = env->irg;
2246 dbg_info *dbgi = get_irn_dbg_info(node);
2247 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2248 ir_node *nomem = new_NoMem();
2249 ir_node *fild, *store;
2252 /* first convert to 32 bit if necessary */
2253 src_bits = get_mode_size_bits(src_mode);
2254 if (src_bits == 8) {
2255 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2256 set_ia32_am_support(new_op, ia32_am_Source);
2257 set_ia32_ls_mode(new_op, src_mode);
2258 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2259 } else if (src_bits < 32) {
2260 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2261 set_ia32_am_support(new_op, ia32_am_Source);
2262 set_ia32_ls_mode(new_op, src_mode);
2263 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2267 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2269 set_ia32_use_frame(store);
2270 set_ia32_am_support(store, ia32_am_Dest);
2271 set_ia32_op_type(store, ia32_AddrModeD);
2272 set_ia32_am_flavour(store, ia32_am_OB);
2273 set_ia32_ls_mode(store, mode_Iu);
2276 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2278 set_ia32_use_frame(fild);
2279 set_ia32_am_support(fild, ia32_am_Source);
2280 set_ia32_op_type(fild, ia32_AddrModeS);
2281 set_ia32_am_flavour(fild, ia32_am_OB);
2282 set_ia32_ls_mode(fild, mode_Iu);
2284 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2288 * Transforms a Conv node.
2290 * @param env The transformation environment
2291 * @return The created ia32 Conv node
2293 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) {
2294 ir_node *block = transform_node(env, get_nodes_block(node));
2295 ir_node *op = get_Conv_op(node);
2296 ir_node *new_op = transform_node(env, op);
2297 ir_graph *irg = env->irg;
2298 dbg_info *dbgi = get_irn_dbg_info(node);
2299 ir_mode *src_mode = get_irn_mode(op);
2300 ir_mode *tgt_mode = get_irn_mode(node);
2301 int src_bits = get_mode_size_bits(src_mode);
2302 int tgt_bits = get_mode_size_bits(tgt_mode);
2303 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2304 ir_node *nomem = new_rd_NoMem(irg);
2307 if (src_mode == tgt_mode) {
2308 if (get_Conv_strict(node)) {
2309 if (USE_SSE2(env->cg)) {
2310 /* when we are in SSE mode, we can kill all strict no-op conversion */
2314 /* this should be optimized already, but who knows... */
2315 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2316 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2321 if (mode_is_float(src_mode)) {
2322 /* we convert from float ... */
2323 if (mode_is_float(tgt_mode)) {
2325 if (USE_SSE2(env->cg)) {
2326 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2327 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2328 set_ia32_ls_mode(res, tgt_mode);
2330 // Matze: TODO what about strict convs?
2331 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: strict conv %+F ignored yet\n", node));
2332 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2337 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2338 if (USE_SSE2(env->cg)) {
2339 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2340 set_ia32_ls_mode(res, src_mode);
2342 return gen_x87_fp_to_gp(env, node);
2346 /* we convert from int ... */
2347 if (mode_is_float(tgt_mode)) {
2350 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2351 if (USE_SSE2(env->cg)) {
2352 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2353 set_ia32_ls_mode(res, tgt_mode);
2354 if(src_bits == 32) {
2355 set_ia32_am_support(res, ia32_am_Source);
2358 return gen_x87_gp_to_fp(env, node, src_mode);
2362 ir_mode *smaller_mode;
2365 if (src_bits == tgt_bits) {
2366 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2370 if (src_bits < tgt_bits) {
2371 smaller_mode = src_mode;
2372 smaller_bits = src_bits;
2374 smaller_mode = tgt_mode;
2375 smaller_bits = tgt_bits;
2378 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2379 if (smaller_bits == 8) {
2380 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2381 set_ia32_ls_mode(res, smaller_mode);
2383 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2384 set_ia32_ls_mode(res, smaller_mode);
2386 set_ia32_am_support(res, ia32_am_Source);
2390 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2396 ir_node *try_create_Immediate(ia32_transform_env_t *env, ir_node *node,
2397 unsigned immediate_max)
2400 tarval *offset = NULL;
2401 int offset_sign = 0;
2402 ir_entity *symconst_ent = NULL;
2403 int symconst_sign = 0;
2405 ir_node *cnst = NULL;
2406 ir_node *symconst = NULL;
2413 mode = get_irn_mode(node);
2414 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2415 !mode_is_reference(mode)) {
2419 if(is_Minus(node)) {
2421 node = get_Minus_op(node);
2424 if(is_Const(node)) {
2427 offset_sign = minus;
2428 } else if(is_SymConst(node)) {
2431 symconst_sign = minus;
2432 } else if(is_Add(node)) {
2433 ir_node *left = get_Add_left(node);
2434 ir_node *right = get_Add_right(node);
2435 if(is_Const(left) && is_SymConst(right)) {
2438 symconst_sign = minus;
2439 offset_sign = minus;
2440 } else if(is_SymConst(left) && is_Const(right)) {
2443 symconst_sign = minus;
2444 offset_sign = minus;
2446 } else if(is_Sub(node)) {
2447 ir_node *left = get_Add_left(node);
2448 ir_node *right = get_Add_right(node);
2449 if(is_Const(left) && is_SymConst(right)) {
2452 symconst_sign = !minus;
2453 offset_sign = minus;
2454 } else if(is_SymConst(left) && is_Const(right)) {
2457 symconst_sign = minus;
2458 offset_sign = !minus;
2469 tv = get_Const_tarval(cnst);
2470 if(!tarval_is_long(tv)) {
2471 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2476 tvu = tarval_convert_to(tv, mode_Iu);
2477 val = get_tarval_long(tvu);
2478 if(val > immediate_max)
2483 if(symconst != NULL) {
2484 if(immediate_max != 0xffffffff) {
2485 /* we need full 32bits for symconsts */
2489 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2491 symconst_ent = get_SymConst_entity(symconst);
2495 dbgi = get_irn_dbg_info(node);
2496 block = get_irg_start_block(irg);
2497 res = new_rd_ia32_Immediate(dbgi, irg, block);
2498 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2500 /* make sure we don't schedule stuff before the barrier */
2501 add_irn_dep(res, get_irg_frame(irg));
2503 /* misuse some fields for now... */
2504 attr = get_ia32_attr(res);
2505 attr->am_sc = symconst_ent;
2506 attr->data.am_sc_sign = symconst_sign;
2507 if(offset_sign && offset != NULL) {
2508 offset = tarval_neg(offset);
2510 attr->cnst_val.tv = offset;
2511 attr->data.imm_tp = ia32_ImmConst;
2516 typedef struct constraint_t constraint_t;
2517 struct constraint_t {
2518 const arch_register_req_t *req;
2519 unsigned immediate_possible;
2520 unsigned immediate_max;
2524 void parse_asm_constraint(ia32_transform_env_t *env, ir_node *node,
2525 constraint_t *constraint, const char *c, int is_in)
2527 int immediate_possible = 0;
2528 unsigned immediate_max = 0xffffffff;
2529 unsigned limited = 0;
2530 const arch_register_class_t *cls = NULL;
2532 struct obstack *obst;
2533 arch_register_req_t *req;
2534 unsigned *limited_ptr;
2536 printf("Constraint: %s\n", c);
2546 assert(cls == NULL ||
2547 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2548 cls = &ia32_reg_classes[CLASS_ia32_gp];
2549 limited |= 1 << REG_EAX;
2552 assert(cls == NULL ||
2553 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2554 cls = &ia32_reg_classes[CLASS_ia32_gp];
2555 limited |= 1 << REG_EBX;
2558 assert(cls == NULL ||
2559 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2560 cls = &ia32_reg_classes[CLASS_ia32_gp];
2561 limited |= 1 << REG_ECX;
2564 assert(cls == NULL ||
2565 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2566 cls = &ia32_reg_classes[CLASS_ia32_gp];
2567 limited |= 1 << REG_EDX;
2570 assert(cls == NULL ||
2571 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2572 cls = &ia32_reg_classes[CLASS_ia32_gp];
2573 limited |= 1 << REG_EDI;
2576 assert(cls == NULL ||
2577 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2578 cls = &ia32_reg_classes[CLASS_ia32_gp];
2579 limited |= 1 << REG_ESI;
2585 assert(cls == NULL);
2586 cls = &ia32_reg_classes[CLASS_ia32_gp];
2592 assert(cls == NULL);
2593 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2597 assert(cls == NULL);
2598 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2602 assert(!immediate_possible);
2603 immediate_possible = 1;
2607 assert(!immediate_possible);
2608 immediate_possible = 1;
2613 assert(!immediate_possible);
2614 immediate_possible = 1;
2617 assert(!immediate_possible);
2618 immediate_possible = 1;
2622 assert(!immediate_possible);
2623 immediate_possible = 1;
2624 immediate_max = 0xff;
2628 assert(!immediate_possible && cls == NULL);
2629 immediate_possible = 1;
2630 cls = &ia32_reg_classes[CLASS_ia32_gp];
2644 assert(0 && "other_same not implemented yet");
2647 case 'E': /* no float consts yet */
2648 case 'F': /* no float consts yet */
2649 case 's': /* makes no sense on x86 */
2650 case 'X': /* we can't support that in firm */
2654 case '<': /* no autodecrement on x86 */
2655 case '>': /* no autoincrement on x86 */
2656 case 'C': /* sse constant not supported yet */
2657 case 'G': /* 80387 constant not supported yet */
2658 case 'y': /* we don't support mmx registers yet */
2659 case 'Z': /* not available in 32 bit mode */
2660 case 'e': /* not available in 32 bit mode */
2661 case 'K': /* gcc docu is cryptic */
2662 case 'L': /* gcc docu is cryptic */
2672 if(immediate_possible && cls == NULL) {
2673 cls = &ia32_reg_classes[CLASS_ia32_gp];
2675 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2676 assert(cls != NULL);
2678 if(immediate_possible) {
2679 assert(is_in && "imeediates make no sense for output constraints");
2680 printf("Immediate possible 0-%x\n", immediate_max);
2682 /* todo: check types (no float input on 'r' constrainted in and such... */
2685 obst = get_irg_obstack(irg);
2688 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2689 limited_ptr = (unsigned*) (req+1);
2691 req = obstack_alloc(obst, sizeof(req[0]));
2693 memset(req, 0, sizeof(req[0]));
2696 req->type = arch_register_req_type_limited;
2697 *limited_ptr = limited;
2698 req->limited = limited_ptr;
2700 req->type = arch_register_req_type_normal;
2704 constraint->req = req;
2705 constraint->immediate_possible = immediate_possible;
2706 constraint->immediate_max = immediate_max;
2710 ir_node *gen_ASM(ia32_transform_env_t *env, ir_node *node)
2713 ir_graph *irg = env->irg;
2714 ir_node *block = transform_node(env, get_nodes_block(node));
2715 dbg_info *dbgi = get_irn_dbg_info(node);
2722 const arch_register_req_t **out_reqs;
2723 const arch_register_req_t **in_reqs;
2724 struct obstack *obst;
2727 /* assembler could contain float statements */
2730 /* transform inputs */
2731 arity = get_irn_arity(node);
2732 in = alloca(arity * sizeof(in[0]));
2733 memset(in, 0, arity * sizeof(in[0]));
2735 n_outs = get_ASM_n_output_constraints(node);
2736 n_clobbers = get_ASM_n_clobbers(node);
2737 out_arity = n_outs + n_clobbers;
2739 /* construct register constraints */
2740 obst = get_irg_obstack(irg);
2741 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2742 for(i = 0; i < out_arity; ++i) {
2744 constraint_t parsed_constr;
2747 const ir_asm_constraint *constraint;
2748 constraint = & get_ASM_output_constraints(node) [i];
2749 c = get_id_str(constraint->constraint);
2751 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2752 c = get_id_str(glob_id);
2754 parse_asm_constraint(env, node, &parsed_constr, c, 0);
2755 out_reqs[i] = parsed_constr.req;
2758 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2759 for(i = 0; i < arity; ++i) {
2760 const ir_asm_constraint *constraint;
2763 constraint_t parsed_constr;
2765 constraint = & get_ASM_input_constraints(node) [i];
2766 constr_id = constraint->constraint;
2767 c = get_id_str(constr_id);
2768 parse_asm_constraint(env, node, &parsed_constr, c, 1);
2769 in_reqs[i] = parsed_constr.req;
2771 if(parsed_constr.immediate_possible) {
2772 ir_node *pred = get_irn_n(node, i);
2774 = try_create_Immediate(env, pred, parsed_constr.immediate_max);
2776 if(immediate != NULL) {
2782 /* transform inputs */
2783 for(i = 0; i < arity; ++i) {
2785 ir_node *transformed;
2790 pred = get_irn_n(node, i);
2791 transformed = transform_node(env, pred);
2792 in[i] = transformed;
2795 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2797 attr = get_ia32_attr(res);
2798 attr->cnst_val.asm_text = get_ASM_text(node);
2799 attr->data.imm_tp = ia32_ImmAsm;
2800 set_ia32_out_req_all(res, out_reqs);
2801 set_ia32_in_req_all(res, in_reqs);
2803 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2808 /********************************************
2811 * | |__ ___ _ __ ___ __| | ___ ___
2812 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2813 * | |_) | __/ | | | (_) | (_| | __/\__ \
2814 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2816 ********************************************/
2818 static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) {
2819 ir_node *block = transform_node(env, get_nodes_block(node));
2820 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2821 ir_node *new_ptr = transform_node(env, ptr);
2822 ir_node *new_op = NULL;
2823 ir_graph *irg = env->irg;
2824 dbg_info *dbgi = get_irn_dbg_info(node);
2825 ir_node *nomem = new_rd_NoMem(env->irg);
2826 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2827 ir_mode *load_mode = get_irn_mode(node);
2828 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2832 if (mode_is_float(load_mode)) {
2834 if (USE_SSE2(env->cg)) {
2835 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2836 pn_res = pn_ia32_xLoad_res;
2837 proj_mode = mode_xmm;
2839 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem);
2840 pn_res = pn_ia32_vfld_res;
2841 proj_mode = mode_vfp;
2844 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2845 proj_mode = mode_Iu;
2846 pn_res = pn_ia32_Load_res;
2849 set_ia32_frame_ent(new_op, ent);
2850 set_ia32_use_frame(new_op);
2852 set_ia32_am_support(new_op, ia32_am_Source);
2853 set_ia32_op_type(new_op, ia32_AddrModeS);
2854 set_ia32_am_flavour(new_op, ia32_am_B);
2855 set_ia32_ls_mode(new_op, load_mode);
2856 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2858 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2860 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2864 * Transforms a FrameAddr into an ia32 Add.
2866 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) {
2867 ir_node *block = transform_node(env, get_nodes_block(node));
2868 ir_node *op = get_irn_n(node, be_pos_FrameAddr_ptr);
2869 ir_node *new_op = transform_node(env, op);
2870 ir_graph *irg = env->irg;
2871 dbg_info *dbgi = get_irn_dbg_info(node);
2872 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2875 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2876 set_ia32_frame_ent(res, arch_get_frame_entity(env->cg->arch_env, node));
2877 set_ia32_am_support(res, ia32_am_Full);
2878 set_ia32_use_frame(res);
2879 set_ia32_am_flavour(res, ia32_am_OB);
2881 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2887 * Transforms a FrameLoad into an ia32 Load.
2889 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) {
2890 ir_node *block = transform_node(env, get_nodes_block(node));
2891 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2892 ir_node *new_mem = transform_node(env, mem);
2893 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2894 ir_node *new_ptr = transform_node(env, ptr);
2895 ir_node *new_op = NULL;
2896 ir_graph *irg = env->irg;
2897 dbg_info *dbgi = get_irn_dbg_info(node);
2898 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2899 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2900 ir_mode *mode = get_type_mode(get_entity_type(ent));
2901 ir_node *projs[pn_Load_max];
2903 ia32_collect_Projs(node, projs, pn_Load_max);
2905 if (mode_is_float(mode)) {
2907 if (USE_SSE2(env->cg)) {
2908 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2911 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
2915 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2918 set_ia32_frame_ent(new_op, ent);
2919 set_ia32_use_frame(new_op);
2921 set_ia32_am_support(new_op, ia32_am_Source);
2922 set_ia32_op_type(new_op, ia32_AddrModeS);
2923 set_ia32_am_flavour(new_op, ia32_am_B);
2924 set_ia32_ls_mode(new_op, mode);
2926 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2933 * Transforms a FrameStore into an ia32 Store.
2935 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) {
2936 ir_node *block = transform_node(env, get_nodes_block(node));
2937 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2938 ir_node *new_mem = transform_node(env, mem);
2939 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2940 ir_node *new_ptr = transform_node(env, ptr);
2941 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2942 ir_node *new_val = transform_node(env, val);
2943 ir_node *new_op = NULL;
2944 ir_graph *irg = env->irg;
2945 dbg_info *dbgi = get_irn_dbg_info(node);
2946 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2947 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2948 ir_mode *mode = get_irn_mode(val);
2950 if (mode_is_float(mode)) {
2952 if (USE_SSE2(env->cg)) {
2953 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2955 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2957 } else if (get_mode_size_bits(mode) == 8) {
2958 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2960 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2963 set_ia32_frame_ent(new_op, ent);
2964 set_ia32_use_frame(new_op);
2966 set_ia32_am_support(new_op, ia32_am_Dest);
2967 set_ia32_op_type(new_op, ia32_AddrModeD);
2968 set_ia32_am_flavour(new_op, ia32_am_B);
2969 set_ia32_ls_mode(new_op, mode);
2971 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2977 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2979 static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
2980 ir_graph *irg = env->irg;
2981 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2982 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2983 ir_entity *ent = get_irg_entity(irg);
2984 ir_type *tp = get_entity_type(ent);
2989 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2990 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2993 int pn_ret_val, pn_ret_mem, arity, i;
2995 assert(ret_val != NULL);
2996 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env->cg)) {
2997 return duplicate_node(env, node);
3000 res_type = get_method_res_type(tp, 0);
3002 if (! is_Primitive_type(res_type)) {
3003 return duplicate_node(env, node);
3006 mode = get_type_mode(res_type);
3007 if (! mode_is_float(mode)) {
3008 return duplicate_node(env, node);
3011 assert(get_method_n_ress(tp) == 1);
3013 pn_ret_val = get_Proj_proj(ret_val);
3014 pn_ret_mem = get_Proj_proj(ret_mem);
3016 /* get the Barrier */
3017 barrier = get_Proj_pred(ret_val);
3019 /* get result input of the Barrier */
3020 ret_val = get_irn_n(barrier, pn_ret_val);
3021 new_ret_val = transform_node(env, ret_val);
3023 /* get memory input of the Barrier */
3024 ret_mem = get_irn_n(barrier, pn_ret_mem);
3025 new_ret_mem = transform_node(env, ret_mem);
3027 frame = get_irg_frame(irg);
3029 dbgi = get_irn_dbg_info(barrier);
3030 block = transform_node(env, get_nodes_block(barrier));
3032 noreg = ia32_new_NoReg_gp(env->cg);
3034 /* store xmm0 onto stack */
3035 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
3036 set_ia32_ls_mode(sse_store, mode);
3037 set_ia32_op_type(sse_store, ia32_AddrModeD);
3038 set_ia32_use_frame(sse_store);
3039 set_ia32_am_flavour(sse_store, ia32_am_B);
3040 set_ia32_am_support(sse_store, ia32_am_Dest);
3043 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
3044 set_ia32_ls_mode(fld, mode);
3045 set_ia32_op_type(fld, ia32_AddrModeS);
3046 set_ia32_use_frame(fld);
3047 set_ia32_am_flavour(fld, ia32_am_B);
3048 set_ia32_am_support(fld, ia32_am_Source);
3050 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3051 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3052 arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3054 /* create a new barrier */
3055 arity = get_irn_arity(barrier);
3056 in = alloca(arity * sizeof(in[0]));
3057 for (i = 0; i < arity; ++i) {
3060 if (i == pn_ret_val) {
3062 } else if (i == pn_ret_mem) {
3065 ir_node *in = get_irn_n(barrier, i);
3066 new_in = transform_node(env, in);
3071 new_barrier = new_ir_node(dbgi, irg, block,
3072 get_irn_op(barrier), get_irn_mode(barrier),
3074 copy_node_attr(barrier, new_barrier);
3075 duplicate_deps(env, barrier, new_barrier);
3076 set_new_node(barrier, new_barrier);
3077 mark_irn_visited(barrier);
3079 /* transform normally */
3080 return duplicate_node(env, node);
3084 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3086 static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
3087 ir_node *block = transform_node(env, get_nodes_block(node));
3088 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3089 ir_node *new_sz = transform_node(env, sz);
3090 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3091 ir_node *new_sp = transform_node(env, sp);
3092 ir_graph *irg = env->irg;
3093 dbg_info *dbgi = get_irn_dbg_info(node);
3094 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3095 ir_node *nomem = new_NoMem();
3098 /* ia32 stack grows in reverse direction, make a SubSP */
3099 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3100 set_ia32_am_support(new_op, ia32_am_Source);
3101 fold_immediate(env, new_op, 2, 3);
3103 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3109 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3111 static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
3112 ir_node *block = transform_node(env, get_nodes_block(node));
3113 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3114 ir_node *new_sz = transform_node(env, sz);
3115 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3116 ir_node *new_sp = transform_node(env, sp);
3117 ir_graph *irg = env->irg;
3118 dbg_info *dbgi = get_irn_dbg_info(node);
3119 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3120 ir_node *nomem = new_NoMem();
3123 /* ia32 stack grows in reverse direction, make an AddSP */
3124 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3125 set_ia32_am_support(new_op, ia32_am_Source);
3126 fold_immediate(env, new_op, 2, 3);
3128 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3134 * This function just sets the register for the Unknown node
3135 * as this is not done during register allocation because Unknown
3136 * is an "ignore" node.
3138 static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) {
3139 ir_mode *mode = get_irn_mode(node);
3141 if (mode_is_float(mode)) {
3142 if (USE_SSE2(env->cg))
3143 return ia32_new_Unknown_xmm(env->cg);
3145 return ia32_new_Unknown_vfp(env->cg);
3146 } else if (mode_needs_gp_reg(mode)) {
3147 return ia32_new_Unknown_gp(env->cg);
3149 assert(0 && "unsupported Unknown-Mode");
3156 * Change some phi modes
3158 static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
3159 ir_node *block = transform_node(env, get_nodes_block(node));
3160 ir_graph *irg = env->irg;
3161 dbg_info *dbgi = get_irn_dbg_info(node);
3162 ir_mode *mode = get_irn_mode(node);
3166 if(mode_needs_gp_reg(mode)) {
3167 /* we shouldn't have any 64bit stuff around anymore */
3168 assert(get_mode_size_bits(mode) <= 32);
3169 /* all integer operations are on 32bit registers now */
3171 } else if(mode_is_float(mode)) {
3172 assert(mode == mode_D || mode == mode_F);
3173 if (USE_SSE2(env->cg)) {
3180 /* phi nodes allow loops, so we use the old arguments for now
3181 * and fix this later */
3182 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3183 copy_node_attr(node, phi);
3184 duplicate_deps(env, node, phi);
3186 set_new_node(node, phi);
3188 /* put the preds in the worklist */
3189 arity = get_irn_arity(node);
3190 for (i = 0; i < arity; ++i) {
3191 ir_node *pred = get_irn_n(node, i);
3192 pdeq_putr(env->worklist, pred);
3198 /**********************************************************************
3201 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3202 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3203 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3204 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3206 **********************************************************************/
3208 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3210 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3213 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3214 ir_node *val, ir_node *mem);
3217 * Transforms a lowered Load into a "real" one.
3219 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) {
3220 ir_node *block = transform_node(env, get_nodes_block(node));
3221 ir_node *ptr = get_irn_n(node, 0);
3222 ir_node *new_ptr = transform_node(env, ptr);
3223 ir_node *mem = get_irn_n(node, 1);
3224 ir_node *new_mem = transform_node(env, mem);
3225 ir_graph *irg = env->irg;
3226 dbg_info *dbgi = get_irn_dbg_info(node);
3227 ir_mode *mode = get_ia32_ls_mode(node);
3228 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3232 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3233 lowering we have x87 nodes, so we need to enforce simulation.
3235 if (mode_is_float(mode)) {
3237 if (fp_unit == fp_x87)
3241 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3243 set_ia32_am_support(new_op, ia32_am_Source);
3244 set_ia32_op_type(new_op, ia32_AddrModeS);
3245 set_ia32_am_flavour(new_op, ia32_am_OB);
3246 set_ia32_am_offs_int(new_op, 0);
3247 set_ia32_am_scale(new_op, 1);
3248 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3249 if (is_ia32_am_sc_sign(node))
3250 set_ia32_am_sc_sign(new_op);
3251 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3252 if (is_ia32_use_frame(node)) {
3253 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3254 set_ia32_use_frame(new_op);
3257 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3263 * Transforms a lowered Store into a "real" one.
3265 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) {
3266 ir_node *block = transform_node(env, get_nodes_block(node));
3267 ir_node *ptr = get_irn_n(node, 0);
3268 ir_node *new_ptr = transform_node(env, ptr);
3269 ir_node *val = get_irn_n(node, 1);
3270 ir_node *new_val = transform_node(env, val);
3271 ir_node *mem = get_irn_n(node, 2);
3272 ir_node *new_mem = transform_node(env, mem);
3273 ir_graph *irg = env->irg;
3274 dbg_info *dbgi = get_irn_dbg_info(node);
3275 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3276 ir_mode *mode = get_ia32_ls_mode(node);
3279 ia32_am_flavour_t am_flav = ia32_B;
3282 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3283 lowering we have x87 nodes, so we need to enforce simulation.
3285 if (mode_is_float(mode)) {
3287 if (fp_unit == fp_x87)
3291 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3293 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3295 add_ia32_am_offs_int(new_op, am_offs);
3298 set_ia32_am_support(new_op, ia32_am_Dest);
3299 set_ia32_op_type(new_op, ia32_AddrModeD);
3300 set_ia32_am_flavour(new_op, am_flav);
3301 set_ia32_ls_mode(new_op, mode);
3302 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3303 set_ia32_use_frame(new_op);
3305 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3312 * Transforms an ia32_l_XXX into a "real" XXX node
3314 * @param env The transformation environment
3315 * @return the created ia32 XXX node
3317 #define GEN_LOWERED_OP(op) \
3318 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
3319 ir_mode *mode = get_irn_mode(node); \
3320 if (mode_is_float(mode)) \
3322 return gen_binop(env, node, get_binop_left(node), \
3323 get_binop_right(node), new_rd_ia32_##op); \
3326 #define GEN_LOWERED_x87_OP(op) \
3327 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
3329 FORCE_x87(env->cg); \
3330 new_op = gen_binop_float(env, node, get_binop_left(node), \
3331 get_binop_right(node), new_rd_ia32_##op); \
3335 #define GEN_LOWERED_UNOP(op) \
3336 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
3337 return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \
3340 #define GEN_LOWERED_SHIFT_OP(op) \
3341 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
3342 return gen_shift_binop(env, node, get_binop_left(node), \
3343 get_binop_right(node), new_rd_ia32_##op); \
3346 #define GEN_LOWERED_LOAD(op, fp_unit) \
3347 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
3348 return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \
3351 #define GEN_LOWERED_STORE(op, fp_unit) \
3352 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
3353 return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \
3360 GEN_LOWERED_OP(IMul)
3362 GEN_LOWERED_x87_OP(vfprem)
3363 GEN_LOWERED_x87_OP(vfmul)
3364 GEN_LOWERED_x87_OP(vfsub)
3366 GEN_LOWERED_UNOP(Neg)
3368 GEN_LOWERED_LOAD(vfild, fp_x87)
3369 GEN_LOWERED_LOAD(Load, fp_none)
3370 /*GEN_LOWERED_STORE(vfist, fp_x87)
3373 GEN_LOWERED_STORE(Store, fp_none)
3375 static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
3376 ir_node *block = transform_node(env, get_nodes_block(node));
3377 ir_node *left = get_binop_left(node);
3378 ir_node *new_left = transform_node(env, left);
3379 ir_node *right = get_binop_right(node);
3380 ir_node *new_right = transform_node(env, right);
3381 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3382 ir_graph *irg = env->irg;
3383 dbg_info *dbgi = get_irn_dbg_info(node);
3386 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3387 clear_ia32_commutative(vfdiv);
3388 set_ia32_am_support(vfdiv, ia32_am_Source);
3389 fold_immediate(env, vfdiv, 2, 3);
3391 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env->cg, node));
3399 * Transforms a l_MulS into a "real" MulS node.
3401 * @param env The transformation environment
3402 * @return the created ia32 Mul node
3404 static ir_node *gen_ia32_l_Mul(ia32_transform_env_t *env, ir_node *node) {
3405 ir_node *block = transform_node(env, get_nodes_block(node));
3406 ir_node *left = get_binop_left(node);
3407 ir_node *new_left = transform_node(env, left);
3408 ir_node *right = get_binop_right(node);
3409 ir_node *new_right = transform_node(env, right);
3410 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3411 ir_graph *irg = env->irg;
3412 dbg_info *dbgi = get_irn_dbg_info(node);
3415 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3416 /* and then skip the result Proj, because all needed Projs are already there. */
3417 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3418 clear_ia32_commutative(muls);
3419 set_ia32_am_support(muls, ia32_am_Source);
3420 fold_immediate(env, muls, 2, 3);
3422 /* check if EAX and EDX proj exist, add missing one */
3423 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3424 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3425 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3427 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env->cg, node));
3432 GEN_LOWERED_SHIFT_OP(Shl)
3433 GEN_LOWERED_SHIFT_OP(Shr)
3434 GEN_LOWERED_SHIFT_OP(Sar)
3437 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3438 * op1 - target to be shifted
3439 * op2 - contains bits to be shifted into target
3441 * Only op3 can be an immediate.
3443 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *node,
3444 ir_node *op1, ir_node *op2,
3447 ir_node *block = transform_node(env, get_nodes_block(node));
3448 ir_node *new_op1 = transform_node(env, op1);
3449 ir_node *new_op2 = transform_node(env, op2);
3450 ir_node *new_count = transform_node(env, count);
3451 ir_node *new_op = NULL;
3452 ir_graph *irg = env->irg;
3453 dbg_info *dbgi = get_irn_dbg_info(node);
3454 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3455 ir_node *nomem = new_NoMem();
3459 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3461 /* Check if immediate optimization is on and */
3462 /* if it's an operation with immediate. */
3463 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3465 /* Limit imm_op within range imm8 */
3467 tv = get_ia32_Immop_tarval(imm_op);
3470 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3471 set_ia32_Immop_tarval(imm_op, tv);
3478 /* integer operations */
3480 /* This is ShiftD with const */
3481 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3483 if (is_ia32_l_ShlD(node))
3484 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3485 new_op1, new_op2, noreg, nomem);
3487 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3488 new_op1, new_op2, noreg, nomem);
3489 copy_ia32_Immop_attr(new_op, imm_op);
3492 /* This is a normal ShiftD */
3493 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3494 if (is_ia32_l_ShlD(node))
3495 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3496 new_op1, new_op2, new_count, nomem);
3498 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3499 new_op1, new_op2, new_count, nomem);
3502 /* set AM support */
3503 // Matze: node has unsupported format (6inputs)
3504 //set_ia32_am_support(new_op, ia32_am_Dest);
3506 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3508 set_ia32_emit_cl(new_op);
3513 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env, ir_node *node) {
3514 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3515 get_irn_n(node, 1), get_irn_n(node, 2));
3518 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env, ir_node *node) {
3519 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3520 get_irn_n(node, 1), get_irn_n(node, 2));
3524 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3526 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) {
3527 ir_node *block = transform_node(env, get_nodes_block(node));
3528 ir_node *val = get_irn_n(node, 1);
3529 ir_node *new_val = transform_node(env, val);
3530 ia32_code_gen_t *cg = env->cg;
3531 ir_node *res = NULL;
3532 ir_graph *irg = env->irg;
3534 ir_node *noreg, *new_ptr, *new_mem;
3541 mem = get_irn_n(node, 2);
3542 new_mem = transform_node(env, mem);
3543 ptr = get_irn_n(node, 0);
3544 new_ptr = transform_node(env, ptr);
3545 noreg = ia32_new_NoReg_gp(cg);
3546 dbgi = get_irn_dbg_info(node);
3548 /* Store x87 -> MEM */
3549 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3550 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3551 set_ia32_use_frame(res);
3552 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3553 set_ia32_am_support(res, ia32_am_Dest);
3554 set_ia32_am_flavour(res, ia32_B);
3555 set_ia32_op_type(res, ia32_AddrModeD);
3557 /* Load MEM -> SSE */
3558 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3559 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3560 set_ia32_use_frame(res);
3561 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3562 set_ia32_am_support(res, ia32_am_Source);
3563 set_ia32_am_flavour(res, ia32_B);
3564 set_ia32_op_type(res, ia32_AddrModeS);
3565 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3571 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3573 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) {
3574 ir_node *block = transform_node(env, get_nodes_block(node));
3575 ir_node *val = get_irn_n(node, 1);
3576 ir_node *new_val = transform_node(env, val);
3577 ia32_code_gen_t *cg = env->cg;
3578 ir_graph *irg = env->irg;
3579 ir_node *res = NULL;
3580 ir_entity *fent = get_ia32_frame_ent(node);
3581 ir_mode *lsmode = get_ia32_ls_mode(node);
3583 ir_node *noreg, *new_ptr, *new_mem;
3587 if (! USE_SSE2(cg)) {
3588 /* SSE unit is not used -> skip this node. */
3592 ptr = get_irn_n(node, 0);
3593 new_ptr = transform_node(env, ptr);
3594 mem = get_irn_n(node, 2);
3595 new_mem = transform_node(env, mem);
3596 noreg = ia32_new_NoReg_gp(cg);
3597 dbgi = get_irn_dbg_info(node);
3599 /* Store SSE -> MEM */
3600 if (is_ia32_xLoad(skip_Proj(new_val))) {
3601 ir_node *ld = skip_Proj(new_val);
3603 /* we can vfld the value directly into the fpu */
3604 fent = get_ia32_frame_ent(ld);
3605 ptr = get_irn_n(ld, 0);
3606 offs = get_ia32_am_offs_int(ld);
3608 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3609 set_ia32_frame_ent(res, fent);
3610 set_ia32_use_frame(res);
3611 set_ia32_ls_mode(res, lsmode);
3612 set_ia32_am_support(res, ia32_am_Dest);
3613 set_ia32_am_flavour(res, ia32_B);
3614 set_ia32_op_type(res, ia32_AddrModeD);
3618 /* Load MEM -> x87 */
3619 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
3620 set_ia32_frame_ent(res, fent);
3621 set_ia32_use_frame(res);
3622 set_ia32_ls_mode(res, lsmode);
3623 add_ia32_am_offs_int(res, offs);
3624 set_ia32_am_support(res, ia32_am_Source);
3625 set_ia32_am_flavour(res, ia32_B);
3626 set_ia32_op_type(res, ia32_AddrModeS);
3627 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3632 /*********************************************************
3635 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3636 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3637 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3638 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3640 *********************************************************/
3643 * the BAD transformer.
3645 static ir_node *bad_transform(ia32_transform_env_t *env, ir_node *node) {
3646 panic("No transform function for %+F available.\n", node);
3650 static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) {
3651 /* end has to be duplicated manually because we need a dynamic in array */
3652 ir_graph *irg = env->irg;
3653 dbg_info *dbgi = get_irn_dbg_info(node);
3654 ir_node *block = transform_node(env, get_nodes_block(node));
3658 new_end = new_ir_node(dbgi, irg, block, op_End, mode_X, -1, NULL);
3659 copy_node_attr(node, new_end);
3660 duplicate_deps(env, node, new_end);
3662 set_irg_end(irg, new_end);
3663 set_new_node(new_end, new_end);
3665 /* transform preds */
3666 arity = get_irn_arity(node);
3667 for (i = 0; i < arity; ++i) {
3668 ir_node *in = get_irn_n(node, i);
3669 ir_node *new_in = transform_node(env, in);
3671 add_End_keepalive(new_end, new_in);
3677 static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) {
3678 ir_graph *irg = env->irg;
3679 dbg_info *dbgi = get_irn_dbg_info(node);
3680 ir_node *start_block = env->old_anchors[anchor_start_block];
3685 * We replace the ProjX from the start node with a jump,
3686 * so the startblock has no preds anymore now
3688 if (node == start_block) {
3689 return new_rd_Block(dbgi, irg, 0, NULL);
3692 /* we use the old blocks for now, because jumps allow cycles in the graph
3693 * we have to fix this later */
3694 block = new_ir_node(dbgi, irg, NULL, get_irn_op(node), get_irn_mode(node),
3695 get_irn_arity(node), get_irn_in(node) + 1);
3696 copy_node_attr(node, block);
3698 #ifdef DEBUG_libfirm
3699 block->node_nr = node->node_nr;
3701 set_new_node(node, block);
3703 /* put the preds in the worklist */
3704 arity = get_irn_arity(node);
3705 for (i = 0; i < arity; ++i) {
3706 ir_node *in = get_irn_n(node, i);
3707 pdeq_putr(env->worklist, in);
3713 static ir_node *gen_Proj_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
3714 ir_node *block = transform_node(env, get_nodes_block(node));
3715 ir_node *pred = get_Proj_pred(node);
3716 ir_node *new_pred = transform_node(env, pred);
3717 ir_graph *irg = env->irg;
3718 dbg_info *dbgi = get_irn_dbg_info(node);
3719 long proj = get_Proj_proj(node);
3721 if (proj == pn_be_AddSP_res) {
3722 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3723 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3725 } else if (proj == pn_be_AddSP_M) {
3726 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3730 return new_rd_Unknown(irg, get_irn_mode(node));
3733 static ir_node *gen_Proj_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
3734 ir_node *block = transform_node(env, get_nodes_block(node));
3735 ir_node *pred = get_Proj_pred(node);
3736 ir_node *new_pred = transform_node(env, pred);
3737 ir_graph *irg = env->irg;
3738 dbg_info *dbgi = get_irn_dbg_info(node);
3739 long proj = get_Proj_proj(node);
3741 if (proj == pn_be_SubSP_res) {
3742 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3743 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3745 } else if (proj == pn_be_SubSP_M) {
3746 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3750 return new_rd_Unknown(irg, get_irn_mode(node));
3753 static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) {
3754 ir_node *block = transform_node(env, get_nodes_block(node));
3755 ir_node *pred = get_Proj_pred(node);
3756 ir_node *new_pred = transform_node(env, pred);
3757 ir_graph *irg = env->irg;
3758 dbg_info *dbgi = get_irn_dbg_info(node);
3759 long proj = get_Proj_proj(node);
3761 /* renumber the proj */
3762 if (is_ia32_Load(new_pred)) {
3763 if (proj == pn_Load_res) {
3764 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3765 } else if (proj == pn_Load_M) {
3766 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3768 } else if (is_ia32_xLoad(new_pred)) {
3769 if (proj == pn_Load_res) {
3770 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3771 } else if (proj == pn_Load_M) {
3772 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3774 } else if (is_ia32_vfld(new_pred)) {
3775 if (proj == pn_Load_res) {
3776 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3777 } else if (proj == pn_Load_M) {
3778 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3783 return new_rd_Unknown(irg, get_irn_mode(node));
3786 static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) {
3787 ir_node *block = transform_node(env, get_nodes_block(node));
3788 ir_node *pred = get_Proj_pred(node);
3789 ir_node *new_pred = transform_node(env, pred);
3790 ir_graph *irg = env->irg;
3791 dbg_info *dbgi = get_irn_dbg_info(node);
3792 ir_mode *mode = get_irn_mode(node);
3793 long proj = get_Proj_proj(node);
3795 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3797 switch (get_irn_opcode(pred)) {
3801 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3803 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3811 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3813 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3821 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3822 case pn_DivMod_res_div:
3823 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3824 case pn_DivMod_res_mod:
3825 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3835 return new_rd_Unknown(irg, mode);
3838 static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node) {
3839 ir_node *block = transform_node(env, get_nodes_block(node));
3840 ir_node *pred = get_Proj_pred(node);
3841 ir_node *new_pred = transform_node(env, pred);
3842 ir_graph *irg = env->irg;
3843 dbg_info *dbgi = get_irn_dbg_info(node);
3844 ir_mode *mode = get_irn_mode(node);
3845 long proj = get_Proj_proj(node);
3848 case pn_CopyB_M_regular:
3849 if (is_ia32_CopyB_i(new_pred)) {
3850 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3851 } else if (is_ia32_CopyB(new_pred)) {
3852 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3860 return new_rd_Unknown(irg, mode);
3863 static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
3864 ir_node *block = transform_node(env, get_nodes_block(node));
3865 ir_node *pred = get_Proj_pred(node);
3866 ir_node *new_pred = transform_node(env, pred);
3867 ir_graph *irg = env->irg;
3868 dbg_info *dbgi = get_irn_dbg_info(node);
3869 ir_mode *mode = get_irn_mode(node);
3870 long proj = get_Proj_proj(node);
3873 case pn_ia32_l_vfdiv_M:
3874 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3875 case pn_ia32_l_vfdiv_res:
3876 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3881 return new_rd_Unknown(irg, mode);
3884 static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node) {
3885 ir_node *block = transform_node(env, get_nodes_block(node));
3886 ir_node *pred = get_Proj_pred(node);
3887 ir_node *new_pred = transform_node(env, pred);
3888 ir_graph *irg = env->irg;
3889 dbg_info *dbgi = get_irn_dbg_info(node);
3890 ir_mode *mode = get_irn_mode(node);
3891 long proj = get_Proj_proj(node);
3895 if (is_ia32_xDiv(new_pred)) {
3896 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3897 } else if (is_ia32_vfdiv(new_pred)) {
3898 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3902 if (is_ia32_xDiv(new_pred)) {
3903 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3904 } else if (is_ia32_vfdiv(new_pred)) {
3905 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3913 return new_rd_Unknown(irg, mode);
3916 static ir_node *gen_Proj_tls(ia32_transform_env_t *env, ir_node *node) {
3917 ir_node *block = transform_node(env, get_nodes_block(node));
3918 ir_graph *irg = env->irg;
3919 dbg_info *dbgi = NULL;
3920 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3925 static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) {
3926 ir_node *block = transform_node(env, get_nodes_block(node));
3927 ir_node *call = get_Proj_pred(node);
3928 ir_node *new_call = transform_node(env, call);
3929 ir_graph *irg = env->irg;
3930 dbg_info *dbgi = get_irn_dbg_info(node);
3931 long proj = get_Proj_proj(node);
3932 ir_mode *mode = get_irn_mode(node);
3934 const arch_register_class_t *cls;
3936 /* The following is kinda tricky: If we're using SSE, then we have to
3937 * move the result value of the call in floating point registers to an
3938 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3939 * after the call, we have to make sure to correctly make the
3940 * MemProj and the result Proj use these 2 nodes
3942 if (proj == pn_be_Call_M_regular) {
3943 // get new node for result, are we doing the sse load/store hack?
3944 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3945 ir_node *call_res_new;
3946 ir_node *call_res_pred = NULL;
3948 if (call_res != NULL) {
3949 call_res_new = transform_node(env, call_res);
3950 call_res_pred = get_Proj_pred(call_res_new);
3953 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3954 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3956 assert(is_ia32_xLoad(call_res_pred));
3957 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3960 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env->cg)) {
3962 ir_node *frame = get_irg_frame(irg);
3963 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3965 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3967 const arch_register_class_t *cls;
3969 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3970 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3972 /* store st(0) onto stack */
3973 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3975 set_ia32_ls_mode(fstp, mode);
3976 set_ia32_op_type(fstp, ia32_AddrModeD);
3977 set_ia32_use_frame(fstp);
3978 set_ia32_am_flavour(fstp, ia32_am_B);
3979 set_ia32_am_support(fstp, ia32_am_Dest);
3981 /* load into SSE register */
3982 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3983 set_ia32_ls_mode(sse_load, mode);
3984 set_ia32_op_type(sse_load, ia32_AddrModeS);
3985 set_ia32_use_frame(sse_load);
3986 set_ia32_am_flavour(sse_load, ia32_am_B);
3987 set_ia32_am_support(sse_load, ia32_am_Source);
3989 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3991 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3993 /* get a Proj representing a caller save register */
3994 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3995 assert(is_Proj(p) && "Proj expected.");
3997 /* user of the the proj is the Keep */
3998 p = get_edge_src_irn(get_irn_out_edge_first(p));
3999 assert(be_is_Keep(p) && "Keep expected.");
4001 /* keep the result */
4002 cls = arch_get_irn_reg_class(env->cg->arch_env, sse_load, -1);
4003 keepin[0] = sse_load;
4004 be_new_Keep(cls, irg, block, 1, keepin);
4009 /* transform call modes */
4010 if (mode_is_data(mode)) {
4011 cls = arch_get_irn_reg_class(env->cg->arch_env, node, -1);
4015 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4018 static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) {
4019 ir_graph *irg = env->irg;
4020 dbg_info *dbgi = get_irn_dbg_info(node);
4021 ir_node *pred = get_Proj_pred(node);
4022 long proj = get_Proj_proj(node);
4024 if (is_Store(pred) || be_is_FrameStore(pred)) {
4025 if (proj == pn_Store_M) {
4026 return transform_node(env, pred);
4029 return new_r_Bad(irg);
4031 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4032 return gen_Proj_Load(env, node);
4033 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4034 return gen_Proj_DivMod(env, node);
4035 } else if (is_CopyB(pred)) {
4036 return gen_Proj_CopyB(env, node);
4037 } else if (is_Quot(pred)) {
4038 return gen_Proj_Quot(env, node);
4039 } else if (is_ia32_l_vfdiv(pred)) {
4040 return gen_Proj_l_vfdiv(env, node);
4041 } else if (be_is_SubSP(pred)) {
4042 return gen_Proj_be_SubSP(env, node);
4043 } else if (be_is_AddSP(pred)) {
4044 return gen_Proj_be_AddSP(env, node);
4045 } else if (be_is_Call(pred)) {
4046 return gen_Proj_be_Call(env, node);
4047 } else if (get_irn_op(pred) == op_Start) {
4048 if (proj == pn_Start_X_initial_exec) {
4049 ir_node *block = get_nodes_block(pred);
4052 /* we exchange the ProjX with a jump */
4053 block = transform_node(env, block);
4054 jump = new_rd_Jmp(dbgi, irg, block);
4055 ir_fprintf(stderr, "created jump: %+F\n", jump);
4058 if (node == env->old_anchors[anchor_tls]) {
4059 return gen_Proj_tls(env, node);
4062 ir_node *new_pred = transform_node(env, pred);
4063 ir_node *block = transform_node(env, get_nodes_block(node));
4064 ir_mode *mode = get_irn_mode(node);
4065 if (mode_needs_gp_reg(mode)) {
4066 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4067 get_Proj_proj(node));
4068 #ifdef DEBUG_libfirm
4069 new_proj->node_nr = node->node_nr;
4075 return duplicate_node(env, node);
4079 * Enters all transform functions into the generic pointer
4081 static void register_transformers(void) {
4082 ir_op *op_Max, *op_Min, *op_Mulh;
4084 /* first clear the generic function pointer for all ops */
4085 clear_irp_opcodes_generic_func();
4087 #define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4088 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4128 /* transform ops from intrinsic lowering */
4148 /* GEN(ia32_l_vfist); TODO */
4150 GEN(ia32_l_X87toSSE);
4151 GEN(ia32_l_SSEtoX87);
4156 /* we should never see these nodes */
4171 /* handle generic backend nodes */
4181 /* set the register for all Unknown nodes */
4184 op_Max = get_op_Max();
4187 op_Min = get_op_Min();
4190 op_Mulh = get_op_Mulh();
4198 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
4202 int deps = get_irn_deps(old_node);
4204 for (i = 0; i < deps; ++i) {
4205 ir_node *dep = get_irn_dep(old_node, i);
4206 ir_node *new_dep = transform_node(env, dep);
4208 add_irn_dep(new_node, new_dep);
4212 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node)
4214 ir_node *block = transform_node(env, get_nodes_block(node));
4215 ir_graph *irg = env->irg;
4216 dbg_info *dbgi = get_irn_dbg_info(node);
4217 ir_mode *mode = get_irn_mode(node);
4218 ir_op *op = get_irn_op(node);
4222 arity = get_irn_arity(node);
4223 if (op->opar == oparity_dynamic) {
4224 new_node = new_ir_node(dbgi, irg, block, op, mode, -1, NULL);
4225 for (i = 0; i < arity; ++i) {
4226 ir_node *in = get_irn_n(node, i);
4227 in = transform_node(env, in);
4228 add_irn_n(new_node, in);
4231 ir_node **ins = alloca(arity * sizeof(ins[0]));
4232 for (i = 0; i < arity; ++i) {
4233 ir_node *in = get_irn_n(node, i);
4234 ins[i] = transform_node(env, in);
4237 new_node = new_ir_node(dbgi, irg, block, op, mode, arity, ins);
4240 copy_node_attr(node, new_node);
4241 duplicate_deps(env, node, new_node);
4243 #ifdef DEBUG_libfirm
4244 new_node->node_nr = node->node_nr;
4251 * Calls transformation function for given node and marks it visited.
4253 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node) {
4255 ir_op *op = get_irn_op(node);
4257 if (irn_visited(node)) {
4258 assert(get_new_node(node) != NULL);
4259 return get_new_node(node);
4262 mark_irn_visited(node);
4263 DEBUG_ONLY(set_new_node(node, NULL));
4265 if (op->ops.generic) {
4266 transform_func *transform = (transform_func *)op->ops.generic;
4268 new_node = (*transform)(env, node);
4269 assert(new_node != NULL);
4271 new_node = duplicate_node(env, node);
4273 DB((dbg, LEVEL_4, "%+F -> %+F\n", node, new_node));
4275 set_new_node(node, new_node);
4276 mark_irn_visited(new_node);
4277 hook_dead_node_elim_subst(current_ir_graph, node, new_node);
4282 * Rewire nodes which are potential loops (like Phis) to avoid endless loops.
4284 static void fix_loops(ia32_transform_env_t *env, ir_node *node) {
4287 if (irn_visited(node))
4290 mark_irn_visited(node);
4292 assert(node_is_in_irgs_storage(env->irg, node));
4294 if (! is_Block(node)) {
4295 ir_node *block = get_nodes_block(node);
4296 ir_node *new_block = (ir_node *)get_irn_link(block);
4298 if (new_block != NULL) {
4299 set_nodes_block(node, new_block);
4303 fix_loops(env, block);
4306 arity = get_irn_arity(node);
4307 for (i = 0; i < arity; ++i) {
4308 ir_node *in = get_irn_n(node, i);
4309 ir_node *nw = (ir_node *)get_irn_link(in);
4311 if (nw != NULL && nw != in) {
4312 set_irn_n(node, i, nw);
4319 arity = get_irn_deps(node);
4320 for (i = 0; i < arity; ++i) {
4321 ir_node *in = get_irn_dep(node, i);
4322 ir_node *nw = (ir_node *)get_irn_link(in);
4324 if (nw != NULL && nw != in) {
4325 set_irn_dep(node, i, nw);
4333 static void pre_transform_node(ir_node **place, ia32_transform_env_t *env)
4338 *place = transform_node(env, *place);
4342 * Transforms all nodes. Deletes the old obstack and creates a new one.
4344 static void transform_nodes(ia32_code_gen_t *cg) {
4346 ir_graph *irg = cg->irg;
4348 ia32_transform_env_t env;
4350 hook_dead_node_elim(irg, 1);
4352 inc_irg_visited(irg);
4356 env.visited = get_irg_visited(irg);
4357 env.worklist = new_pdeq();
4358 env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
4360 old_end = get_irg_end(irg);
4362 /* put all anchor nodes in the worklist */
4363 for (i = 0; i < anchor_max; ++i) {
4364 ir_node *anchor = irg->anchors[i];
4368 pdeq_putr(env.worklist, anchor);
4370 /* remember anchor */
4371 env.old_anchors[i] = anchor;
4372 /* and set it to NULL to make sure we don't accidently use it */
4373 irg->anchors[i] = NULL;
4376 /* pre transform some anchors (so they are available in the other transform
4378 set_irg_bad(irg, transform_node(&env, env.old_anchors[anchor_bad]));
4379 set_irg_no_mem(irg, transform_node(&env, env.old_anchors[anchor_no_mem]));
4380 set_irg_start_block(irg, transform_node(&env, env.old_anchors[anchor_start_block]));
4381 set_irg_start(irg, transform_node(&env, env.old_anchors[anchor_start]));
4382 set_irg_frame(irg, transform_node(&env, env.old_anchors[anchor_frame]));
4384 pre_transform_node(&cg->unknown_gp, &env);
4385 pre_transform_node(&cg->unknown_vfp, &env);
4386 pre_transform_node(&cg->unknown_xmm, &env);
4387 pre_transform_node(&cg->noreg_gp, &env);
4388 pre_transform_node(&cg->noreg_vfp, &env);
4389 pre_transform_node(&cg->noreg_xmm, &env);
4391 /* process worklist (this should transform all nodes in the graph) */
4392 while (! pdeq_empty(env.worklist)) {
4393 ir_node *node = pdeq_getl(env.worklist);
4394 transform_node(&env, node);
4397 /* fix loops and set new anchors*/
4398 inc_irg_visited(irg);
4399 for (i = 0; i < anchor_max; ++i) {
4400 ir_node *anchor = env.old_anchors[i];
4405 anchor = get_irn_link(anchor);
4406 fix_loops(&env, anchor);
4407 assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
4408 irg->anchors[i] = anchor;
4411 del_pdeq(env.worklist);
4413 hook_dead_node_elim(irg, 0);
4416 void ia32_transform_graph(ia32_code_gen_t *cg)
4418 ir_graph *irg = cg->irg;
4419 be_irg_t *birg = cg->birg;
4420 ir_graph *old_current_ir_graph = current_ir_graph;
4421 int old_interprocedural_view = get_interprocedural_view();
4422 struct obstack *old_obst = NULL;
4423 struct obstack *new_obst = NULL;
4425 current_ir_graph = irg;
4426 set_interprocedural_view(0);
4427 register_transformers();
4429 /* most analysis info is wrong after transformation */
4430 free_callee_info(irg);
4432 irg->outs_state = outs_none;
4434 free_loop_information(irg);
4435 set_irg_doms_inconsistent(irg);
4436 be_invalidate_liveness(birg);
4437 be_invalidate_dom_front(birg);
4439 /* create a new obstack */
4440 old_obst = irg->obst;
4441 new_obst = xmalloc(sizeof(*new_obst));
4442 obstack_init(new_obst);
4443 irg->obst = new_obst;
4444 irg->last_node_idx = 0;
4446 /* create new value table for CSE */
4447 del_identities(irg->value_table);
4448 irg->value_table = new_identities();
4450 /* do the main transformation */
4451 transform_nodes(cg);
4453 /* we don't want the globals anchor anymore */
4454 set_irg_globals(irg, new_r_Bad(irg));
4456 /* free the old obstack */
4457 obstack_free(old_obst, 0);
4461 current_ir_graph = old_current_ir_graph;
4462 set_interprocedural_view(old_interprocedural_view);
4464 /* recalculate edges */
4465 edges_deactivate(irg);
4466 edges_activate(irg);
4470 * Transforms a psi condition.
4472 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
4475 /* if the mode is target mode, we have already seen this part of the tree */
4476 if (get_irn_mode(cond) == mode)
4479 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
4481 set_irn_mode(cond, mode);
4483 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
4484 ir_node *in = get_irn_n(cond, i);
4486 /* if in is a compare: transform into Set/xCmp */
4488 ir_node *new_op = NULL;
4489 ir_node *cmp = get_Proj_pred(in);
4490 ir_node *cmp_a = get_Cmp_left(cmp);
4491 ir_node *cmp_b = get_Cmp_right(cmp);
4492 dbg_info *dbgi = get_irn_dbg_info(cmp);
4493 ir_graph *irg = get_irn_irg(cmp);
4494 ir_node *block = get_nodes_block(cmp);
4495 ir_node *noreg = ia32_new_NoReg_gp(cg);
4496 ir_node *nomem = new_rd_NoMem(irg);
4497 int pnc = get_Proj_proj(in);
4499 /* this is a compare */
4500 if (mode_is_float(mode)) {
4501 /* Psi is float, we need a floating point compare */
4504 ir_mode *m = get_irn_mode(cmp_a);
4506 if (! mode_is_float(m)) {
4507 cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_a, cmp_a, mode);
4508 cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_b, cmp_b, mode);
4509 } else if (m == mode_F) {
4510 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
4511 cmp_a = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_a, cmp_a);
4512 cmp_b = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_b, cmp_b);
4515 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4516 set_ia32_pncode(new_op, pnc);
4517 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
4524 construct_binop_func *set_func = NULL;
4526 if (mode_is_float(get_irn_mode(cmp_a))) {
4527 /* 1st case: compare operands are floats */
4532 set_func = new_rd_ia32_xCmpSet;
4535 set_func = new_rd_ia32_vfCmpSet;
4538 pnc &= 7; /* fp compare -> int compare */
4540 /* 2nd case: compare operand are integer too */
4541 set_func = new_rd_ia32_CmpSet;
4544 new_op = set_func(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4545 if (! mode_is_signed(mode))
4546 pnc |= ia32_pn_Cmp_Unsigned;
4548 set_ia32_pncode(new_op, pnc);
4549 set_ia32_am_support(new_op, ia32_am_Source);
4552 /* the the new compare as in */
4553 set_irn_n(cond, i, new_op);
4555 /* another complex condition */
4556 transform_psi_cond(in, mode, cg);
4562 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
4563 * We create a Set node, respectively a xCmp in case the Psi is a float, for
4564 * each compare, which causes the compare result to be stored in a register. The
4565 * "And"s and "Or"s are transformed later, we just have to set their mode right.
4567 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
4568 ia32_code_gen_t *cg = env;
4569 ir_node *psi_sel, *new_cmp, *block;
4574 if (get_irn_opcode(node) != iro_Psi)
4577 psi_sel = get_Psi_cond(node, 0);
4579 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
4580 if (is_Proj(psi_sel)) {
4581 assert(is_Cmp(get_Proj_pred(psi_sel)));
4585 //mode = get_irn_mode(node);
4586 // TODO probably wrong...
4589 transform_psi_cond(psi_sel, mode, cg);
4591 irg = get_irn_irg(node);
4592 block = get_nodes_block(node);
4594 /* we need to compare the evaluated condition tree with 0 */
4595 mode = get_irn_mode(node);
4596 if (mode_is_float(mode)) {
4597 /* BEWARE: new_r_Const_long works for floating point as well */
4598 ir_node *zero = new_r_Const_long(irg, block, mode, 0);
4600 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
4601 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4602 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
4604 ir_node *zero = new_r_Const_long(irg, block, mode_Iu, 0);
4605 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4606 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
4609 set_Psi_cond(node, 0, new_cmp);
4612 void ia32_init_transform(void)
4614 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");