2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_map_regs.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
67 #include "gen_ia32_regalloc_if.h"
69 #define SFP_SIGN "0x80000000"
70 #define DFP_SIGN "0x8000000000000000"
71 #define SFP_ABS "0x7FFFFFFF"
72 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
74 #define TP_SFP_SIGN "ia32_sfp_sign"
75 #define TP_DFP_SIGN "ia32_dfp_sign"
76 #define TP_SFP_ABS "ia32_sfp_abs"
77 #define TP_DFP_ABS "ia32_dfp_abs"
79 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
80 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
81 #define ENT_SFP_ABS "IA32_SFP_ABS"
82 #define ENT_DFP_ABS "IA32_DFP_ABS"
84 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
85 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
87 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 /** hold the current code generator during transformation */
90 static ia32_code_gen_t *env_cg = NULL;
91 static ir_node *initial_fpcw = NULL;
93 extern ir_op *get_op_Mulh(void);
95 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
96 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
97 ir_node *op2, ir_node *mem);
99 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
100 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
101 ir_node *op2, ir_node *mem, ir_node *fpcw);
103 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
104 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
107 /****************************************************************************************************
109 * | | | | / _| | | (_)
110 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
111 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
112 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
113 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
115 ****************************************************************************************************/
117 static ir_node *try_create_Immediate(ir_node *node,
118 char immediate_constraint_type);
120 static ir_node *create_immediate_or_transform(ir_node *node,
121 char immediate_constraint_type);
123 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
124 dbg_info *dbgi, ir_node *new_block,
128 * Return true if a mode can be stored in the GP register set
130 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
131 if(mode == mode_fpcw)
133 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
137 * Returns 1 if irn is a Const representing 0, 0 otherwise
139 static INLINE int is_ia32_Const_0(ir_node *irn) {
140 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
141 && tarval_is_null(get_ia32_Immop_tarval(irn));
145 * Returns 1 if irn is a Const representing 1, 0 otherwise
147 static INLINE int is_ia32_Const_1(ir_node *irn) {
148 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
149 && tarval_is_one(get_ia32_Immop_tarval(irn));
153 * Collects all Projs of a node into the node array. Index is the projnum.
154 * BEWARE: The caller has to assure the appropriate array size!
156 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
157 const ir_edge_t *edge;
158 assert(get_irn_mode(irn) == mode_T && "need mode_T");
160 memset(projs, 0, size * sizeof(projs[0]));
162 foreach_out_edge(irn, edge) {
163 ir_node *proj = get_edge_src_irn(edge);
164 int proj_proj = get_Proj_proj(proj);
165 assert(proj_proj < size);
166 projs[proj_proj] = proj;
171 * Renumbers the proj having pn_old in the array tp pn_new
172 * and removes the proj from the array.
174 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
175 fprintf(stderr, "Warning: renumber_Proj used!\n");
177 set_Proj_proj(projs[pn_old], pn_new);
178 projs[pn_old] = NULL;
183 * creates a unique ident by adding a number to a tag
185 * @param tag the tag string, must contain a %d if a number
188 static ident *unique_id(const char *tag)
190 static unsigned id = 0;
193 snprintf(str, sizeof(str), tag, ++id);
194 return new_id_from_str(str);
198 * Get a primitive type for a mode.
200 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
202 pmap_entry *e = pmap_find(types, mode);
207 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
208 res = new_type_primitive(new_id_from_str(buf), mode);
209 set_type_alignment_bytes(res, 16);
210 pmap_insert(types, mode, res);
218 * Get an entity that is initialized with a tarval
220 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
222 tarval *tv = get_Const_tarval(cnst);
223 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
228 ir_mode *mode = get_irn_mode(cnst);
229 ir_type *tp = get_Const_type(cnst);
230 if (tp == firm_unknown_type)
231 tp = get_prim_type(cg->isa->types, mode);
233 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
235 set_entity_ld_ident(res, get_entity_ident(res));
236 set_entity_visibility(res, visibility_local);
237 set_entity_variability(res, variability_constant);
238 set_entity_allocation(res, allocation_static);
240 /* we create a new entity here: It's initialization must resist on the
242 rem = current_ir_graph;
243 current_ir_graph = get_const_code_irg();
244 set_atomic_ent_value(res, new_Const_type(tv, tp));
245 current_ir_graph = rem;
247 pmap_insert(cg->isa->tv_ent, tv, res);
255 static int is_Const_0(ir_node *node) {
259 return classify_Const(node) == CNST_NULL;
262 static int is_Const_1(ir_node *node) {
266 return classify_Const(node) == CNST_ONE;
270 * Transforms a Const.
272 static ir_node *gen_Const(ir_node *node) {
273 ir_graph *irg = current_ir_graph;
274 ir_node *old_block = get_nodes_block(node);
275 ir_node *block = be_transform_node(old_block);
276 dbg_info *dbgi = get_irn_dbg_info(node);
277 ir_mode *mode = get_irn_mode(node);
279 if (mode_is_float(mode)) {
281 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
282 ir_node *nomem = new_NoMem();
286 if (! USE_SSE2(env_cg)) {
287 cnst_classify_t clss = classify_Const(node);
289 if (clss == CNST_NULL) {
290 load = new_rd_ia32_vfldz(dbgi, irg, block);
292 } else if (clss == CNST_ONE) {
293 load = new_rd_ia32_vfld1(dbgi, irg, block);
296 floatent = get_entity_for_tv(env_cg, node);
298 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
299 set_ia32_op_type(load, ia32_AddrModeS);
300 set_ia32_am_flavour(load, ia32_am_N);
301 set_ia32_am_sc(load, floatent);
302 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
303 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
305 set_ia32_ls_mode(load, mode);
307 floatent = get_entity_for_tv(env_cg, node);
309 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
310 set_ia32_op_type(load, ia32_AddrModeS);
311 set_ia32_am_flavour(load, ia32_am_N);
312 set_ia32_am_sc(load, floatent);
313 set_ia32_ls_mode(load, mode);
314 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
316 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
319 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
321 /* Const Nodes before the initial IncSP are a bad idea, because
322 * they could be spilled and we have no SP ready at that point yet.
323 * So add a dependency to the initial frame pointer calculation to
324 * avoid that situation.
326 if (get_irg_start_block(irg) == block) {
327 add_irn_dep(load, get_irg_frame(irg));
330 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
333 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
336 if (get_irg_start_block(irg) == block) {
337 add_irn_dep(cnst, get_irg_frame(irg));
340 set_ia32_Const_attr(cnst, node);
341 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
346 return new_r_Bad(irg);
350 * Transforms a SymConst.
352 static ir_node *gen_SymConst(ir_node *node) {
353 ir_graph *irg = current_ir_graph;
354 ir_node *old_block = get_nodes_block(node);
355 ir_node *block = be_transform_node(old_block);
356 dbg_info *dbgi = get_irn_dbg_info(node);
357 ir_mode *mode = get_irn_mode(node);
360 if (mode_is_float(mode)) {
361 if (USE_SSE2(env_cg))
362 cnst = new_rd_ia32_xConst(dbgi, irg, block);
364 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
365 //set_ia32_ls_mode(cnst, mode);
366 set_ia32_ls_mode(cnst, mode_E);
368 cnst = new_rd_ia32_Const(dbgi, irg, block);
371 /* Const Nodes before the initial IncSP are a bad idea, because
372 * they could be spilled and we have no SP ready at that point yet
374 if (get_irg_start_block(irg) == block) {
375 add_irn_dep(cnst, get_irg_frame(irg));
378 set_ia32_Const_attr(cnst, node);
379 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
384 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
385 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
386 static const struct {
388 const char *ent_name;
389 const char *cnst_str;
390 } names [ia32_known_const_max] = {
391 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
392 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
393 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
394 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
396 static ir_entity *ent_cache[ia32_known_const_max];
398 const char *tp_name, *ent_name, *cnst_str;
406 ent_name = names[kct].ent_name;
407 if (! ent_cache[kct]) {
408 tp_name = names[kct].tp_name;
409 cnst_str = names[kct].cnst_str;
411 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
413 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
414 tp = new_type_primitive(new_id_from_str(tp_name), mode);
415 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
417 set_entity_ld_ident(ent, get_entity_ident(ent));
418 set_entity_visibility(ent, visibility_local);
419 set_entity_variability(ent, variability_constant);
420 set_entity_allocation(ent, allocation_static);
422 /* we create a new entity here: It's initialization must resist on the
424 rem = current_ir_graph;
425 current_ir_graph = get_const_code_irg();
426 cnst = new_Const(mode, tv);
427 current_ir_graph = rem;
429 set_atomic_ent_value(ent, cnst);
431 /* cache the entry */
432 ent_cache[kct] = ent;
435 return ent_cache[kct];
440 * Prints the old node name on cg obst and returns a pointer to it.
442 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
443 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
445 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
446 obstack_1grow(isa->name_obst, 0);
447 return obstack_finish(isa->name_obst);
451 /* determine if one operator is an Imm */
452 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
454 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
456 return is_ia32_Cnst(op2) ? op2 : NULL;
460 /* determine if one operator is not an Imm */
461 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
462 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
465 static void fold_immediate(ir_node *node, int in1, int in2) {
469 if (!(env_cg->opt & IA32_OPT_IMMOPS))
472 left = get_irn_n(node, in1);
473 right = get_irn_n(node, in2);
474 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
475 /* we can only set right operand to immediate */
476 if(!is_ia32_commutative(node))
478 /* exchange left/right */
479 set_irn_n(node, in1, right);
480 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
481 copy_ia32_Immop_attr(node, left);
482 } else if(is_ia32_Cnst(right)) {
483 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
484 copy_ia32_Immop_attr(node, right);
489 clear_ia32_commutative(node);
490 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
491 get_ia32_am_arity(node));
495 * Construct a standard binary operation, set AM and immediate if required.
497 * @param op1 The first operand
498 * @param op2 The second operand
499 * @param func The node constructor function
500 * @return The constructed ia32 node.
502 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
503 construct_binop_func *func, int commutative)
505 ir_node *block = be_transform_node(get_nodes_block(node));
506 ir_graph *irg = current_ir_graph;
507 dbg_info *dbgi = get_irn_dbg_info(node);
508 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
509 ir_node *nomem = new_NoMem();
512 ir_node *new_op1 = be_transform_node(op1);
513 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
514 if (is_ia32_Immediate(new_op2)) {
518 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
519 if (func == new_rd_ia32_IMul) {
520 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
522 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
525 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
527 set_ia32_commutative(new_node);
534 * Construct a standard binary operation, set AM and immediate if required.
536 * @param op1 The first operand
537 * @param op2 The second operand
538 * @param func The node constructor function
539 * @return The constructed ia32 node.
541 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
542 construct_binop_func *func)
544 ir_node *block = be_transform_node(get_nodes_block(node));
545 ir_node *new_op1 = be_transform_node(op1);
546 ir_node *new_op2 = be_transform_node(op2);
547 ir_node *new_node = NULL;
548 dbg_info *dbgi = get_irn_dbg_info(node);
549 ir_graph *irg = current_ir_graph;
550 ir_mode *mode = get_irn_mode(node);
551 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
552 ir_node *nomem = new_NoMem();
554 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
556 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
557 if (is_op_commutative(get_irn_op(node))) {
558 set_ia32_commutative(new_node);
560 set_ia32_ls_mode(new_node, mode);
562 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
567 static ir_node *get_fpcw(void)
570 if(initial_fpcw != NULL)
573 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
574 &ia32_fp_cw_regs[REG_FPCW]);
575 initial_fpcw = be_transform_node(fpcw);
581 * Construct a standard binary operation, set AM and immediate if required.
583 * @param op1 The first operand
584 * @param op2 The second operand
585 * @param func The node constructor function
586 * @return The constructed ia32 node.
588 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
589 construct_binop_float_func *func)
591 ir_node *block = be_transform_node(get_nodes_block(node));
592 ir_node *new_op1 = be_transform_node(op1);
593 ir_node *new_op2 = be_transform_node(op2);
594 ir_node *new_node = NULL;
595 dbg_info *dbgi = get_irn_dbg_info(node);
596 ir_graph *irg = current_ir_graph;
597 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
598 ir_node *nomem = new_NoMem();
600 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
602 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
603 if (is_op_commutative(get_irn_op(node))) {
604 set_ia32_commutative(new_node);
607 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
613 * Construct a shift/rotate binary operation, sets AM and immediate if required.
615 * @param op1 The first operand
616 * @param op2 The second operand
617 * @param func The node constructor function
618 * @return The constructed ia32 node.
620 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
621 construct_binop_func *func)
623 ir_node *block = be_transform_node(get_nodes_block(node));
624 ir_node *new_op1 = be_transform_node(op1);
626 ir_node *new_op = NULL;
627 dbg_info *dbgi = get_irn_dbg_info(node);
628 ir_graph *irg = current_ir_graph;
629 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
630 ir_node *nomem = new_NoMem();
632 assert(! mode_is_float(get_irn_mode(node))
633 && "Shift/Rotate with float not supported");
635 new_op2 = create_immediate_or_transform(op2, 'N');
637 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
640 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
642 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
644 set_ia32_emit_cl(new_op);
646 /* lowered shift instruction may have a dependency operand, handle it here */
647 if (get_irn_arity(node) == 3) {
648 /* we have a dependency */
649 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
650 add_irn_dep(new_op, new_dep);
658 * Construct a standard unary operation, set AM and immediate if required.
660 * @param op The operand
661 * @param func The node constructor function
662 * @return The constructed ia32 node.
664 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
666 ir_node *block = be_transform_node(get_nodes_block(node));
667 ir_node *new_op = be_transform_node(op);
668 ir_node *new_node = NULL;
669 ir_graph *irg = current_ir_graph;
670 dbg_info *dbgi = get_irn_dbg_info(node);
671 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
672 ir_node *nomem = new_NoMem();
674 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
675 DB((dbg, LEVEL_1, "INT unop ..."));
676 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
678 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
684 * Creates an ia32 Add.
686 * @return the created ia32 Add node
688 static ir_node *gen_Add(ir_node *node) {
689 ir_node *block = be_transform_node(get_nodes_block(node));
690 ir_node *op1 = get_Add_left(node);
691 ir_node *new_op1 = be_transform_node(op1);
692 ir_node *op2 = get_Add_right(node);
693 ir_node *new_op2 = be_transform_node(op2);
694 ir_node *new_op = NULL;
695 ir_graph *irg = current_ir_graph;
696 dbg_info *dbgi = get_irn_dbg_info(node);
697 ir_mode *mode = get_irn_mode(node);
698 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
699 ir_node *nomem = new_NoMem();
700 ir_node *expr_op, *imm_op;
702 /* Check if immediate optimization is on and */
703 /* if it's an operation with immediate. */
704 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
705 expr_op = get_expr_op(new_op1, new_op2);
707 assert((expr_op || imm_op) && "invalid operands");
709 if (mode_is_float(mode)) {
710 if (USE_SSE2(env_cg))
711 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
713 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
718 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
719 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
721 /* No expr_op means, that we have two const - one symconst and */
722 /* one tarval or another symconst - because this case is not */
723 /* covered by constant folding */
724 /* We need to check for: */
725 /* 1) symconst + const -> becomes a LEA */
726 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
727 /* linker doesn't support two symconsts */
729 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
730 /* this is the 2nd case */
731 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
732 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
733 set_ia32_am_flavour(new_op, ia32_am_B);
734 set_ia32_op_type(new_op, ia32_AddrModeS);
736 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
737 } else if (tp1 == ia32_ImmSymConst) {
738 tarval *tv = get_ia32_Immop_tarval(new_op2);
739 long offs = get_tarval_long(tv);
741 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
742 add_irn_dep(new_op, get_irg_frame(irg));
743 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
745 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
746 add_ia32_am_offs_int(new_op, offs);
747 set_ia32_am_flavour(new_op, ia32_am_OB);
748 set_ia32_op_type(new_op, ia32_AddrModeS);
749 } else if (tp2 == ia32_ImmSymConst) {
750 tarval *tv = get_ia32_Immop_tarval(new_op1);
751 long offs = get_tarval_long(tv);
753 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
754 add_irn_dep(new_op, get_irg_frame(irg));
755 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
757 add_ia32_am_offs_int(new_op, offs);
758 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
759 set_ia32_am_flavour(new_op, ia32_am_OB);
760 set_ia32_op_type(new_op, ia32_AddrModeS);
762 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
763 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
764 tarval *restv = tarval_add(tv1, tv2);
766 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
768 new_op = new_rd_ia32_Const(dbgi, irg, block);
769 set_ia32_Const_tarval(new_op, restv);
770 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
773 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
776 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
777 tarval_classification_t class_tv, class_negtv;
778 tarval *tv = get_ia32_Immop_tarval(imm_op);
780 /* optimize tarvals */
781 class_tv = classify_tarval(tv);
782 class_negtv = classify_tarval(tarval_neg(tv));
784 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
785 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
786 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
787 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
789 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
790 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
791 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
792 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
798 /* This is a normal add */
799 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
802 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
803 set_ia32_commutative(new_op);
805 fold_immediate(new_op, 2, 3);
807 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
813 * Creates an ia32 Mul.
815 * @return the created ia32 Mul node
817 static ir_node *gen_Mul(ir_node *node) {
818 ir_node *op1 = get_Mul_left(node);
819 ir_node *op2 = get_Mul_right(node);
820 ir_mode *mode = get_irn_mode(node);
822 if (mode_is_float(mode)) {
823 if (USE_SSE2(env_cg))
824 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
826 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
830 for the lower 32bit of the result it doesn't matter whether we use
831 signed or unsigned multiplication so we use IMul as it has fewer
834 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
838 * Creates an ia32 Mulh.
839 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
840 * this result while Mul returns the lower 32 bit.
842 * @return the created ia32 Mulh node
844 static ir_node *gen_Mulh(ir_node *node) {
845 ir_node *block = be_transform_node(get_nodes_block(node));
846 ir_node *op1 = get_irn_n(node, 0);
847 ir_node *new_op1 = be_transform_node(op1);
848 ir_node *op2 = get_irn_n(node, 1);
849 ir_node *new_op2 = be_transform_node(op2);
850 ir_graph *irg = current_ir_graph;
851 dbg_info *dbgi = get_irn_dbg_info(node);
852 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
853 ir_mode *mode = get_irn_mode(node);
854 ir_node *proj_EDX, *res;
856 assert(!mode_is_float(mode) && "Mulh with float not supported");
857 if (mode_is_signed(mode)) {
858 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
859 new_op2, new_NoMem());
861 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
865 set_ia32_commutative(res);
866 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
868 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
876 * Creates an ia32 And.
878 * @return The created ia32 And node
880 static ir_node *gen_And(ir_node *node) {
881 ir_node *op1 = get_And_left(node);
882 ir_node *op2 = get_And_right(node);
883 assert(! mode_is_float(get_irn_mode(node)));
885 /* check for zero extension first */
887 tarval *tv = get_Const_tarval(op2);
888 long v = get_tarval_long(tv);
890 if (v == 0xFF || v == 0xFFFF) {
891 dbg_info *dbgi = get_irn_dbg_info(node);
892 ir_node *block = be_transform_node(get_nodes_block(node));
893 ir_node *new_op = be_transform_node(op1);
903 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, new_op);
904 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
910 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
916 * Creates an ia32 Or.
918 * @return The created ia32 Or node
920 static ir_node *gen_Or(ir_node *node) {
921 ir_node *op1 = get_Or_left(node);
922 ir_node *op2 = get_Or_right(node);
924 assert (! mode_is_float(get_irn_mode(node)));
925 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
931 * Creates an ia32 Eor.
933 * @return The created ia32 Eor node
935 static ir_node *gen_Eor(ir_node *node) {
936 ir_node *op1 = get_Eor_left(node);
937 ir_node *op2 = get_Eor_right(node);
939 assert(! mode_is_float(get_irn_mode(node)));
940 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
945 * Creates an ia32 Sub.
947 * @return The created ia32 Sub node
949 static ir_node *gen_Sub(ir_node *node) {
950 ir_node *block = be_transform_node(get_nodes_block(node));
951 ir_node *op1 = get_Sub_left(node);
952 ir_node *new_op1 = be_transform_node(op1);
953 ir_node *op2 = get_Sub_right(node);
954 ir_node *new_op2 = be_transform_node(op2);
955 ir_node *new_op = NULL;
956 ir_graph *irg = current_ir_graph;
957 dbg_info *dbgi = get_irn_dbg_info(node);
958 ir_mode *mode = get_irn_mode(node);
959 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
960 ir_node *nomem = new_NoMem();
961 ir_node *expr_op, *imm_op;
963 /* Check if immediate optimization is on and */
964 /* if it's an operation with immediate. */
965 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
966 expr_op = get_expr_op(new_op1, new_op2);
968 assert((expr_op || imm_op) && "invalid operands");
970 if (mode_is_float(mode)) {
971 if (USE_SSE2(env_cg))
972 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
974 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
979 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
980 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
982 /* No expr_op means, that we have two const - one symconst and */
983 /* one tarval or another symconst - because this case is not */
984 /* covered by constant folding */
985 /* We need to check for: */
986 /* 1) symconst - const -> becomes a LEA */
987 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
988 /* linker doesn't support two symconsts */
989 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
990 /* this is the 2nd case */
991 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
992 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
993 set_ia32_am_sc_sign(new_op);
994 set_ia32_am_flavour(new_op, ia32_am_B);
996 DBG_OPT_LEA3(op1, op2, node, new_op);
997 } else if (tp1 == ia32_ImmSymConst) {
998 tarval *tv = get_ia32_Immop_tarval(new_op2);
999 long offs = get_tarval_long(tv);
1001 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1002 add_irn_dep(new_op, get_irg_frame(irg));
1003 DBG_OPT_LEA3(op1, op2, node, new_op);
1005 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1006 add_ia32_am_offs_int(new_op, -offs);
1007 set_ia32_am_flavour(new_op, ia32_am_OB);
1008 set_ia32_op_type(new_op, ia32_AddrModeS);
1009 } else if (tp2 == ia32_ImmSymConst) {
1010 tarval *tv = get_ia32_Immop_tarval(new_op1);
1011 long offs = get_tarval_long(tv);
1013 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1014 add_irn_dep(new_op, get_irg_frame(irg));
1015 DBG_OPT_LEA3(op1, op2, node, new_op);
1017 add_ia32_am_offs_int(new_op, offs);
1018 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1019 set_ia32_am_sc_sign(new_op);
1020 set_ia32_am_flavour(new_op, ia32_am_OB);
1021 set_ia32_op_type(new_op, ia32_AddrModeS);
1023 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1024 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1025 tarval *restv = tarval_sub(tv1, tv2);
1027 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1029 new_op = new_rd_ia32_Const(dbgi, irg, block);
1030 set_ia32_Const_tarval(new_op, restv);
1031 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1034 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1036 } else if (imm_op) {
1037 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1038 tarval_classification_t class_tv, class_negtv;
1039 tarval *tv = get_ia32_Immop_tarval(imm_op);
1041 /* optimize tarvals */
1042 class_tv = classify_tarval(tv);
1043 class_negtv = classify_tarval(tarval_neg(tv));
1045 if (class_tv == TV_CLASSIFY_ONE) {
1046 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1047 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1048 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1050 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1051 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1052 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1053 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1059 /* This is a normal sub */
1060 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1062 /* set AM support */
1063 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1065 fold_immediate(new_op, 2, 3);
1067 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1075 * Generates an ia32 DivMod with additional infrastructure for the
1076 * register allocator if needed.
1078 * @param dividend -no comment- :)
1079 * @param divisor -no comment- :)
1080 * @param dm_flav flavour_Div/Mod/DivMod
1081 * @return The created ia32 DivMod node
1083 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1084 ir_node *divisor, ia32_op_flavour_t dm_flav)
1086 ir_node *block = be_transform_node(get_nodes_block(node));
1087 ir_node *new_dividend = be_transform_node(dividend);
1088 ir_node *new_divisor = be_transform_node(divisor);
1089 ir_graph *irg = current_ir_graph;
1090 dbg_info *dbgi = get_irn_dbg_info(node);
1091 ir_mode *mode = get_irn_mode(node);
1092 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1093 ir_node *res, *proj_div, *proj_mod;
1094 ir_node *sign_extension;
1095 ir_node *mem, *new_mem;
1096 ir_node *projs[pn_DivMod_max];
1099 ia32_collect_Projs(node, projs, pn_DivMod_max);
1101 proj_div = proj_mod = NULL;
1105 mem = get_Div_mem(node);
1106 mode = get_Div_resmode(node);
1107 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1108 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1111 mem = get_Mod_mem(node);
1112 mode = get_Mod_resmode(node);
1113 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1114 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1116 case flavour_DivMod:
1117 mem = get_DivMod_mem(node);
1118 mode = get_DivMod_resmode(node);
1119 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1120 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1121 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1124 panic("invalid divmod flavour!");
1126 new_mem = be_transform_node(mem);
1128 if (mode_is_signed(mode)) {
1129 /* in signed mode, we need to sign extend the dividend */
1130 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1131 add_irn_dep(produceval, get_irg_frame(irg));
1132 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1135 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1136 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1138 add_irn_dep(sign_extension, get_irg_frame(irg));
1141 if (mode_is_signed(mode)) {
1142 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1143 sign_extension, new_divisor, new_mem, dm_flav);
1145 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1146 sign_extension, new_divisor, new_mem, dm_flav);
1149 set_ia32_exc_label(res, has_exc);
1150 set_irn_pinned(res, get_irn_pinned(node));
1151 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1153 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1160 * Wrapper for generate_DivMod. Sets flavour_Mod.
1163 static ir_node *gen_Mod(ir_node *node) {
1164 return generate_DivMod(node, get_Mod_left(node),
1165 get_Mod_right(node), flavour_Mod);
1169 * Wrapper for generate_DivMod. Sets flavour_Div.
1172 static ir_node *gen_Div(ir_node *node) {
1173 return generate_DivMod(node, get_Div_left(node),
1174 get_Div_right(node), flavour_Div);
1178 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1180 static ir_node *gen_DivMod(ir_node *node) {
1181 return generate_DivMod(node, get_DivMod_left(node),
1182 get_DivMod_right(node), flavour_DivMod);
1188 * Creates an ia32 floating Div.
1190 * @return The created ia32 xDiv node
1192 static ir_node *gen_Quot(ir_node *node) {
1193 ir_node *block = be_transform_node(get_nodes_block(node));
1194 ir_node *op1 = get_Quot_left(node);
1195 ir_node *new_op1 = be_transform_node(op1);
1196 ir_node *op2 = get_Quot_right(node);
1197 ir_node *new_op2 = be_transform_node(op2);
1198 ir_graph *irg = current_ir_graph;
1199 dbg_info *dbgi = get_irn_dbg_info(node);
1200 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1201 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1204 if (USE_SSE2(env_cg)) {
1205 ir_mode *mode = get_irn_mode(op1);
1206 if (is_ia32_xConst(new_op2)) {
1207 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1208 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1209 copy_ia32_Immop_attr(new_op, new_op2);
1211 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1212 // Matze: disabled for now, spillslot coalescer fails
1213 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1215 set_ia32_ls_mode(new_op, mode);
1217 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1218 new_op2, nomem, get_fpcw());
1219 // Matze: disabled for now (spillslot coalescer fails)
1220 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1222 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1228 * Creates an ia32 Shl.
1230 * @return The created ia32 Shl node
1232 static ir_node *gen_Shl(ir_node *node) {
1233 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1240 * Creates an ia32 Shr.
1242 * @return The created ia32 Shr node
1244 static ir_node *gen_Shr(ir_node *node) {
1245 return gen_shift_binop(node, get_Shr_left(node),
1246 get_Shr_right(node), new_rd_ia32_Shr);
1252 * Creates an ia32 Sar.
1254 * @return The created ia32 Shrs node
1256 static ir_node *gen_Shrs(ir_node *node) {
1257 ir_node *left = get_Shrs_left(node);
1258 ir_node *right = get_Shrs_right(node);
1259 ir_mode *mode = get_irn_mode(node);
1260 if(is_Const(right) && mode == mode_Is) {
1261 tarval *tv = get_Const_tarval(right);
1262 long val = get_tarval_long(tv);
1264 /* this is a sign extension */
1265 ir_graph *irg = current_ir_graph;
1266 dbg_info *dbgi = get_irn_dbg_info(node);
1267 ir_node *block = be_transform_node(get_nodes_block(node));
1269 ir_node *new_op = be_transform_node(op);
1270 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1271 add_irn_dep(pval, get_irg_frame(irg));
1273 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1277 /* 8 or 16 bit sign extension? */
1278 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1279 ir_node *shl_left = get_Shl_left(left);
1280 ir_node *shl_right = get_Shl_right(left);
1281 if(is_Const(shl_right)) {
1282 tarval *tv1 = get_Const_tarval(right);
1283 tarval *tv2 = get_Const_tarval(shl_right);
1284 if(tv1 == tv2 && tarval_is_long(tv1)) {
1285 long val = get_tarval_long(tv1);
1286 if(val == 16 || val == 24) {
1287 dbg_info *dbgi = get_irn_dbg_info(node);
1288 ir_node *block = be_transform_node(get_nodes_block(node));
1289 ir_node *new_op = be_transform_node(shl_left);
1299 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1301 SET_IA32_ORIG_NODE(res,
1302 ia32_get_old_node_name(env_cg, node));
1311 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1317 * Creates an ia32 RotL.
1319 * @param op1 The first operator
1320 * @param op2 The second operator
1321 * @return The created ia32 RotL node
1323 static ir_node *gen_RotL(ir_node *node,
1324 ir_node *op1, ir_node *op2) {
1325 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1331 * Creates an ia32 RotR.
1332 * NOTE: There is no RotR with immediate because this would always be a RotL
1333 * "imm-mode_size_bits" which can be pre-calculated.
1335 * @param op1 The first operator
1336 * @param op2 The second operator
1337 * @return The created ia32 RotR node
1339 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1341 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1347 * Creates an ia32 RotR or RotL (depending on the found pattern).
1349 * @return The created ia32 RotL or RotR node
1351 static ir_node *gen_Rot(ir_node *node) {
1352 ir_node *rotate = NULL;
1353 ir_node *op1 = get_Rot_left(node);
1354 ir_node *op2 = get_Rot_right(node);
1356 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1357 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1358 that means we can create a RotR instead of an Add and a RotL */
1360 if (get_irn_op(op2) == op_Add) {
1362 ir_node *left = get_Add_left(add);
1363 ir_node *right = get_Add_right(add);
1364 if (is_Const(right)) {
1365 tarval *tv = get_Const_tarval(right);
1366 ir_mode *mode = get_irn_mode(node);
1367 long bits = get_mode_size_bits(mode);
1369 if (get_irn_op(left) == op_Minus &&
1370 tarval_is_long(tv) &&
1371 get_tarval_long(tv) == bits)
1373 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1374 rotate = gen_RotR(node, op1, get_Minus_op(left));
1379 if (rotate == NULL) {
1380 rotate = gen_RotL(node, op1, op2);
1389 * Transforms a Minus node.
1391 * @param op The Minus operand
1392 * @return The created ia32 Minus node
1394 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1395 ir_node *block = be_transform_node(get_nodes_block(node));
1396 ir_graph *irg = current_ir_graph;
1397 dbg_info *dbgi = get_irn_dbg_info(node);
1398 ir_mode *mode = get_irn_mode(node);
1403 if (mode_is_float(mode)) {
1404 ir_node *new_op = be_transform_node(op);
1405 if (USE_SSE2(env_cg)) {
1406 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1407 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1408 ir_node *nomem = new_rd_NoMem(irg);
1410 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1412 size = get_mode_size_bits(mode);
1413 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1415 set_ia32_am_sc(res, ent);
1416 set_ia32_op_type(res, ia32_AddrModeS);
1417 set_ia32_ls_mode(res, mode);
1419 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1422 res = gen_unop(node, op, new_rd_ia32_Neg);
1425 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1431 * Transforms a Minus node.
1433 * @return The created ia32 Minus node
1435 static ir_node *gen_Minus(ir_node *node) {
1436 return gen_Minus_ex(node, get_Minus_op(node));
1439 static ir_node *create_Immediate_from_int(int val)
1441 ir_graph *irg = current_ir_graph;
1442 ir_node *start_block = get_irg_start_block(irg);
1443 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, 0, val);
1444 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
1449 static ir_node *gen_bin_Not(ir_node *node)
1451 ir_graph *irg = current_ir_graph;
1452 dbg_info *dbgi = get_irn_dbg_info(node);
1453 ir_node *block = be_transform_node(get_nodes_block(node));
1454 ir_node *op = get_Not_op(node);
1455 ir_node *new_op = be_transform_node(op);
1456 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1457 ir_node *nomem = new_NoMem();
1458 ir_node *one = create_Immediate_from_int(1);
1460 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1464 * Transforms a Not node.
1466 * @return The created ia32 Not node
1468 static ir_node *gen_Not(ir_node *node) {
1469 ir_node *op = get_Not_op(node);
1470 ir_mode *mode = get_irn_mode(node);
1472 if(mode == mode_b) {
1473 return gen_bin_Not(node);
1476 assert (! mode_is_float(get_irn_mode(node)));
1477 return gen_unop(node, op, new_rd_ia32_Not);
1483 * Transforms an Abs node.
1485 * @return The created ia32 Abs node
1487 static ir_node *gen_Abs(ir_node *node) {
1488 ir_node *block = be_transform_node(get_nodes_block(node));
1489 ir_node *op = get_Abs_op(node);
1490 ir_node *new_op = be_transform_node(op);
1491 ir_graph *irg = current_ir_graph;
1492 dbg_info *dbgi = get_irn_dbg_info(node);
1493 ir_mode *mode = get_irn_mode(node);
1494 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1495 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1496 ir_node *nomem = new_NoMem();
1501 if (mode_is_float(mode)) {
1502 if (USE_SSE2(env_cg)) {
1503 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1505 size = get_mode_size_bits(mode);
1506 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1508 set_ia32_am_sc(res, ent);
1510 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1512 set_ia32_op_type(res, ia32_AddrModeS);
1513 set_ia32_ls_mode(res, mode);
1516 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1517 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1521 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1522 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1525 add_irn_dep(pval, get_irg_frame(irg));
1526 SET_IA32_ORIG_NODE(sign_extension,
1527 ia32_get_old_node_name(env_cg, node));
1529 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1530 sign_extension, nomem);
1531 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1533 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1534 sign_extension, nomem);
1535 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1544 * Transforms a Load.
1546 * @return the created ia32 Load node
1548 static ir_node *gen_Load(ir_node *node) {
1549 ir_node *old_block = get_nodes_block(node);
1550 ir_node *block = be_transform_node(old_block);
1551 ir_node *ptr = get_Load_ptr(node);
1552 ir_node *new_ptr = be_transform_node(ptr);
1553 ir_node *mem = get_Load_mem(node);
1554 ir_node *new_mem = be_transform_node(mem);
1555 ir_graph *irg = current_ir_graph;
1556 dbg_info *dbgi = get_irn_dbg_info(node);
1557 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1558 ir_mode *mode = get_Load_mode(node);
1560 ir_node *lptr = new_ptr;
1563 ia32_am_flavour_t am_flav = ia32_am_B;
1565 /* address might be a constant (symconst or absolute address) */
1566 if (is_ia32_Const(new_ptr)) {
1571 if (mode_is_float(mode)) {
1572 if (USE_SSE2(env_cg)) {
1573 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1574 res_mode = mode_xmm;
1576 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1577 res_mode = mode_vfp;
1583 /* create a conv node with address mode for smaller modes */
1584 if(get_mode_size_bits(mode) < 32) {
1585 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, lptr, noreg, noreg,
1588 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1593 /* base is a constant address */
1595 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1596 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1597 am_flav = ia32_am_N;
1599 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1600 long offs = get_tarval_long(tv);
1602 add_ia32_am_offs_int(new_op, offs);
1603 am_flav = ia32_am_O;
1607 set_irn_pinned(new_op, get_irn_pinned(node));
1608 set_ia32_op_type(new_op, ia32_AddrModeS);
1609 set_ia32_am_flavour(new_op, am_flav);
1610 set_ia32_ls_mode(new_op, mode);
1612 /* make sure we are scheduled behind the initial IncSP/Barrier
1613 * to avoid spills being placed before it
1615 if (block == get_irg_start_block(irg)) {
1616 add_irn_dep(new_op, get_irg_frame(irg));
1619 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1620 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1628 * Transforms a Store.
1630 * @return the created ia32 Store node
1632 static ir_node *gen_Store(ir_node *node) {
1633 ir_node *block = be_transform_node(get_nodes_block(node));
1634 ir_node *ptr = get_Store_ptr(node);
1635 ir_node *new_ptr = be_transform_node(ptr);
1636 ir_node *val = get_Store_value(node);
1638 ir_node *mem = get_Store_mem(node);
1639 ir_node *new_mem = be_transform_node(mem);
1640 ir_graph *irg = current_ir_graph;
1641 dbg_info *dbgi = get_irn_dbg_info(node);
1642 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1643 ir_node *sptr = new_ptr;
1644 ir_mode *mode = get_irn_mode(val);
1647 ia32_am_flavour_t am_flav = ia32_am_B;
1649 /* address might be a constant (symconst or absolute address) */
1650 if (is_ia32_Const(new_ptr)) {
1655 if (mode_is_float(mode)) {
1656 new_val = be_transform_node(val);
1657 if (USE_SSE2(env_cg)) {
1658 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1661 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1665 new_val = create_immediate_or_transform(val, 0);
1669 if (get_mode_size_bits(mode) == 8) {
1670 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1673 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1678 /* base is an constant address */
1680 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1681 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1682 am_flav = ia32_am_N;
1684 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1685 long offs = get_tarval_long(tv);
1687 add_ia32_am_offs_int(new_op, offs);
1688 am_flav = ia32_am_O;
1692 set_irn_pinned(new_op, get_irn_pinned(node));
1693 set_ia32_op_type(new_op, ia32_AddrModeD);
1694 set_ia32_am_flavour(new_op, am_flav);
1695 set_ia32_ls_mode(new_op, mode);
1697 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1698 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1703 static ir_node *maybe_scale_up(ir_node *new_op, ir_mode *mode, dbg_info *dbgi)
1708 if(get_mode_size_bits(mode) == 32)
1712 if(is_ia32_Immediate(new_op))
1715 if(mode_is_signed(mode))
1720 block = get_nodes_block(new_op);
1721 return create_I2I_Conv(mode, tgt_mode, dbgi, block, new_op);
1724 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1725 ir_node *cmp_left, ir_node *cmp_right)
1727 ir_node *new_cmp_left;
1728 ir_node *new_cmp_right;
1735 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1737 if(cmp_right != NULL && !is_Const_0(cmp_right))
1740 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1741 and_left = get_And_left(cmp_left);
1742 and_right = get_And_right(cmp_left);
1744 mode = get_irn_mode(and_left);
1745 new_cmp_left = be_transform_node(and_left);
1746 new_cmp_right = create_immediate_or_transform(and_right, 0);
1748 mode = get_irn_mode(cmp_left);
1749 new_cmp_left = be_transform_node(cmp_left);
1750 new_cmp_right = be_transform_node(cmp_left);
1753 assert(get_mode_size_bits(mode) <= 32);
1754 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1755 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1756 noreg = ia32_new_NoReg_gp(env_cg);
1757 nomem = new_NoMem();
1759 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1760 new_cmp_left, new_cmp_right, nomem, pnc);
1761 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1766 static ir_node *create_Switch(ir_node *node)
1768 ir_graph *irg = current_ir_graph;
1769 dbg_info *dbgi = get_irn_dbg_info(node);
1770 ir_node *block = be_transform_node(get_nodes_block(node));
1771 ir_node *sel = get_Cond_selector(node);
1772 ir_node *new_sel = be_transform_node(sel);
1774 int switch_min = INT_MAX;
1775 const ir_edge_t *edge;
1777 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1779 /* determine the smallest switch case value */
1780 foreach_out_edge(node, edge) {
1781 ir_node *proj = get_edge_src_irn(edge);
1782 int pn = get_Proj_proj(proj);
1787 if (switch_min != 0) {
1788 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1790 /* if smallest switch case is not 0 we need an additional sub */
1791 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1792 add_ia32_am_offs_int(new_sel, -switch_min);
1793 set_ia32_am_flavour(new_sel, ia32_am_OB);
1794 set_ia32_op_type(new_sel, ia32_AddrModeS);
1796 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1799 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1800 set_ia32_pncode(res, get_Cond_defaultProj(node));
1802 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1808 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1810 * @return The transformed node.
1812 static ir_node *gen_Cond(ir_node *node) {
1813 ir_node *block = be_transform_node(get_nodes_block(node));
1814 ir_graph *irg = current_ir_graph;
1815 dbg_info *dbgi = get_irn_dbg_info(node);
1816 ir_node *sel = get_Cond_selector(node);
1817 ir_mode *sel_mode = get_irn_mode(sel);
1818 ir_node *res = NULL;
1819 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1826 ir_node *nomem = new_NoMem();
1829 if (sel_mode != mode_b) {
1830 return create_Switch(node);
1833 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
1834 /* it's some mode_b value but not a direct comparison -> create a
1836 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
1837 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1841 cmp = get_Proj_pred(sel);
1842 cmp_a = get_Cmp_left(cmp);
1843 cmp_b = get_Cmp_right(cmp);
1844 cmp_mode = get_irn_mode(cmp_a);
1845 pnc = get_Proj_proj(sel);
1846 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1847 pnc |= ia32_pn_Cmp_Unsigned;
1850 if(mode_needs_gp_reg(cmp_mode)) {
1851 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b);
1853 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1858 new_cmp_a = be_transform_node(cmp_a);
1859 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1861 if (mode_is_float(cmp_mode)) {
1862 if (USE_SSE2(env_cg)) {
1863 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1865 set_ia32_commutative(res);
1866 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1867 set_ia32_ls_mode(res, cmp_mode);
1869 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1870 set_ia32_commutative(res);
1873 /** workaround smaller compare modes with converts...
1874 * We could easily support 16bit compares, for 8 bit we have to set
1875 * additional register constraints, which we don't do yet
1877 new_cmp_a = maybe_scale_up(new_cmp_a, cmp_mode, dbgi);
1878 new_cmp_b = maybe_scale_up(new_cmp_b, cmp_mode, dbgi);
1880 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1881 new_cmp_a, new_cmp_b, nomem, pnc);
1882 set_ia32_commutative(res);
1883 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1886 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1894 * Transforms a CopyB node.
1896 * @return The transformed node.
1898 static ir_node *gen_CopyB(ir_node *node) {
1899 ir_node *block = be_transform_node(get_nodes_block(node));
1900 ir_node *src = get_CopyB_src(node);
1901 ir_node *new_src = be_transform_node(src);
1902 ir_node *dst = get_CopyB_dst(node);
1903 ir_node *new_dst = be_transform_node(dst);
1904 ir_node *mem = get_CopyB_mem(node);
1905 ir_node *new_mem = be_transform_node(mem);
1906 ir_node *res = NULL;
1907 ir_graph *irg = current_ir_graph;
1908 dbg_info *dbgi = get_irn_dbg_info(node);
1909 int size = get_type_size_bytes(get_CopyB_type(node));
1912 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1913 /* then we need the size explicitly in ECX. */
1914 if (size >= 32 * 4) {
1915 rem = size & 0x3; /* size % 4 */
1918 res = new_rd_ia32_Const(dbgi, irg, block);
1919 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1920 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1922 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1923 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1925 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1926 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1929 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1935 ir_node *gen_be_Copy(ir_node *node)
1937 ir_node *result = be_duplicate_node(node);
1938 ir_mode *mode = get_irn_mode(result);
1940 if (mode_needs_gp_reg(mode)) {
1941 set_irn_mode(result, mode_Iu);
1948 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1949 dbg_info *dbgi, ir_node *block)
1951 ir_graph *irg = current_ir_graph;
1952 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1953 ir_node *nomem = new_rd_NoMem(irg);
1955 ir_node *new_cmp_left;
1956 ir_node *new_cmp_right;
1959 /* can we use a test instruction? */
1960 if(cmp_right == NULL || is_Const_0(cmp_right)) {
1961 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1962 if(is_And(cmp_left) &&
1963 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1964 ir_node *and_left = get_And_left(cmp_left);
1965 ir_node *and_right = get_And_right(cmp_left);
1967 mode = get_irn_mode(and_left);
1968 new_cmp_left = be_transform_node(and_left);
1969 new_cmp_right = create_immediate_or_transform(and_right, 0);
1971 mode = get_irn_mode(cmp_left);
1972 new_cmp_left = be_transform_node(cmp_left);
1973 new_cmp_right = be_transform_node(cmp_left);
1976 assert(get_mode_size_bits(mode) <= 32);
1977 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1978 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1980 res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
1981 new_cmp_left, new_cmp_right, nomem, pnc);
1982 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1987 mode = get_irn_mode(cmp_left);
1989 new_cmp_left = be_transform_node(cmp_left);
1990 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1992 assert(get_mode_size_bits(mode) <= 32);
1993 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1994 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1996 res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
1997 new_cmp_left, new_cmp_right, nomem, pnc);
2002 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
2003 ir_node *val_true, ir_node *val_false,
2004 dbg_info *dbgi, ir_node *block)
2006 ir_graph *irg = current_ir_graph;
2007 ir_node *new_val_true = be_transform_node(val_true);
2008 ir_node *new_val_false = be_transform_node(val_false);
2009 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2010 ir_node *nomem = new_NoMem();
2011 ir_node *new_cmp_left;
2012 ir_node *new_cmp_right;
2015 /* cmovs with unknowns are pointless... */
2016 if(is_Unknown(val_true)) {
2017 #ifdef DEBUG_libfirm
2018 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2020 return new_val_false;
2022 if(is_Unknown(val_false)) {
2023 #ifdef DEBUG_libfirm
2024 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2026 return new_val_true;
2029 /* can we use a test instruction? */
2030 if(is_Const_0(cmp_right)) {
2031 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2032 if(is_And(cmp_left) &&
2033 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2034 ir_node *and_left = get_And_left(cmp_left);
2035 ir_node *and_right = get_And_right(cmp_left);
2037 new_cmp_left = be_transform_node(and_left);
2038 new_cmp_right = create_immediate_or_transform(and_right, 0);
2040 new_cmp_left = be_transform_node(cmp_left);
2041 new_cmp_right = be_transform_node(cmp_left);
2044 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, block, noreg, noreg,
2045 new_cmp_left, new_cmp_right, nomem,
2046 new_val_true, new_val_false, pnc);
2047 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
2052 new_cmp_left = be_transform_node(cmp_left);
2053 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
2055 res = new_rd_ia32_CmpCMov(dbgi, irg, block, noreg, noreg, new_cmp_left,
2056 new_cmp_right, nomem, new_val_true, new_val_false,
2058 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
2065 * Transforms a Psi node into CMov.
2067 * @return The transformed node.
2069 static ir_node *gen_Psi(ir_node *node) {
2070 ir_node *psi_true = get_Psi_val(node, 0);
2071 ir_node *psi_default = get_Psi_default(node);
2072 ia32_code_gen_t *cg = env_cg;
2073 ir_node *cond = get_Psi_cond(node, 0);
2074 ir_node *block = be_transform_node(get_nodes_block(node));
2075 dbg_info *dbgi = get_irn_dbg_info(node);
2082 assert(get_Psi_n_conds(node) == 1);
2083 assert(get_irn_mode(cond) == mode_b);
2084 assert(mode_needs_gp_reg(get_irn_mode(node)));
2086 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
2087 /* a mode_b value, we have to compare it against 0 */
2089 cmp_right = new_Const_long(mode_Iu, 0);
2093 ir_node *cmp = get_Proj_pred(cond);
2095 cmp_left = get_Cmp_left(cmp);
2096 cmp_right = get_Cmp_right(cmp);
2097 cmp_mode = get_irn_mode(cmp_left);
2098 pnc = get_Proj_proj(cond);
2100 assert(!mode_is_float(cmp_mode));
2102 if (!mode_is_signed(cmp_mode)) {
2103 pnc |= ia32_pn_Cmp_Unsigned;
2107 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2108 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2109 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2110 pnc = get_negated_pnc(pnc, cmp_mode);
2111 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2113 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
2116 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2122 * Following conversion rules apply:
2126 * 1) n bit -> m bit n > m (downscale)
2128 * 2) n bit -> m bit n == m (sign change)
2130 * 3) n bit -> m bit n < m (upscale)
2131 * a) source is signed: movsx
2132 * b) source is unsigned: and with lower bits sets
2136 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2140 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2144 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2145 * x87 is mode_E internally, conversions happen only at load and store
2146 * in non-strict semantic
2150 * Create a conversion from x87 state register to general purpose.
2152 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2153 ir_node *block = be_transform_node(get_nodes_block(node));
2154 ir_node *op = get_Conv_op(node);
2155 ir_node *new_op = be_transform_node(op);
2156 ia32_code_gen_t *cg = env_cg;
2157 ir_graph *irg = current_ir_graph;
2158 dbg_info *dbgi = get_irn_dbg_info(node);
2159 ir_node *noreg = ia32_new_NoReg_gp(cg);
2160 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2161 ir_mode *mode = get_irn_mode(node);
2162 ir_node *fist, *load;
2165 fist = new_rd_ia32_vfist(dbgi, irg, block,
2166 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2168 set_irn_pinned(fist, op_pin_state_floats);
2169 set_ia32_use_frame(fist);
2170 set_ia32_op_type(fist, ia32_AddrModeD);
2171 set_ia32_am_flavour(fist, ia32_am_B);
2173 assert(get_mode_size_bits(mode) <= 32);
2174 /* exception we can only store signed 32 bit integers, so for unsigned
2175 we store a 64bit (signed) integer and load the lower bits */
2176 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2177 set_ia32_ls_mode(fist, mode_Ls);
2179 set_ia32_ls_mode(fist, mode_Is);
2181 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2184 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2186 set_irn_pinned(load, op_pin_state_floats);
2187 set_ia32_use_frame(load);
2188 set_ia32_op_type(load, ia32_AddrModeS);
2189 set_ia32_am_flavour(load, ia32_am_B);
2190 set_ia32_ls_mode(load, mode_Is);
2191 if(get_ia32_ls_mode(fist) == mode_Ls) {
2192 ia32_attr_t *attr = get_ia32_attr(load);
2193 attr->data.need_64bit_stackent = 1;
2195 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2197 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2200 static ir_node *create_strict_conv(ir_mode *tgt_mode, ir_node *node)
2202 ir_node *block = get_nodes_block(node);
2203 ir_graph *irg = current_ir_graph;
2204 dbg_info *dbgi = get_irn_dbg_info(node);
2205 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2206 ir_node *nomem = new_NoMem();
2207 ir_node *frame = get_irg_frame(irg);
2208 ir_node *store, *load;
2211 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2213 set_ia32_use_frame(store);
2214 set_ia32_op_type(store, ia32_AddrModeD);
2215 set_ia32_am_flavour(store, ia32_am_OB);
2216 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2218 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2220 set_ia32_use_frame(load);
2221 set_ia32_op_type(load, ia32_AddrModeS);
2222 set_ia32_am_flavour(load, ia32_am_OB);
2223 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2225 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2230 * Create a conversion from general purpose to x87 register
2232 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2233 ir_node *block = be_transform_node(get_nodes_block(node));
2234 ir_node *op = get_Conv_op(node);
2235 ir_node *new_op = be_transform_node(op);
2236 ir_graph *irg = current_ir_graph;
2237 dbg_info *dbgi = get_irn_dbg_info(node);
2238 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2239 ir_node *nomem = new_NoMem();
2240 ir_mode *mode = get_irn_mode(op);
2241 ir_mode *store_mode;
2242 ir_node *fild, *store;
2246 /* first convert to 32 bit signed if necessary */
2247 src_bits = get_mode_size_bits(src_mode);
2248 if (src_bits == 8) {
2249 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem,
2251 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2252 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2254 } else if (src_bits < 32) {
2255 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem, src_mode);
2256 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2257 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2261 assert(get_mode_size_bits(mode) == 32);
2264 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2266 set_ia32_use_frame(store);
2267 set_ia32_op_type(store, ia32_AddrModeD);
2268 set_ia32_am_flavour(store, ia32_am_OB);
2269 set_ia32_ls_mode(store, mode_Iu);
2271 /* exception for 32bit unsigned, do a 64bit spill+load */
2272 if(!mode_is_signed(mode)) {
2275 ir_node *zero_const = create_Immediate_from_int(0);
2277 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg,
2280 set_ia32_use_frame(zero_store);
2281 set_ia32_op_type(zero_store, ia32_AddrModeD);
2282 add_ia32_am_offs_int(zero_store, 4);
2283 set_ia32_ls_mode(zero_store, mode_Iu);
2288 store = new_rd_Sync(dbgi, irg, block, 2, in);
2289 store_mode = mode_Ls;
2291 store_mode = mode_Is;
2295 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2297 set_ia32_use_frame(fild);
2298 set_ia32_op_type(fild, ia32_AddrModeS);
2299 set_ia32_am_flavour(fild, ia32_am_OB);
2300 set_ia32_ls_mode(fild, store_mode);
2302 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2308 * Crete a conversion from one integer mode into another one
2310 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2311 dbg_info *dbgi, ir_node *new_block,
2314 ir_graph *irg = current_ir_graph;
2315 int src_bits = get_mode_size_bits(src_mode);
2316 int tgt_bits = get_mode_size_bits(tgt_mode);
2317 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2318 ir_node *nomem = new_rd_NoMem(irg);
2320 ir_mode *smaller_mode;
2323 if (src_bits < tgt_bits) {
2324 smaller_mode = src_mode;
2325 smaller_bits = src_bits;
2327 smaller_mode = tgt_mode;
2328 smaller_bits = tgt_bits;
2331 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2332 if (smaller_bits == 8) {
2333 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2334 new_op, nomem, smaller_mode);
2336 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, noreg, noreg, new_op,
2337 nomem, smaller_mode);
2339 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2345 * Transforms a Conv node.
2347 * @return The created ia32 Conv node
2349 static ir_node *gen_Conv(ir_node *node) {
2350 ir_node *block = be_transform_node(get_nodes_block(node));
2351 ir_node *op = get_Conv_op(node);
2352 ir_node *new_op = be_transform_node(op);
2353 ir_graph *irg = current_ir_graph;
2354 dbg_info *dbgi = get_irn_dbg_info(node);
2355 ir_mode *src_mode = get_irn_mode(op);
2356 ir_mode *tgt_mode = get_irn_mode(node);
2357 int src_bits = get_mode_size_bits(src_mode);
2358 int tgt_bits = get_mode_size_bits(tgt_mode);
2359 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2360 ir_node *nomem = new_rd_NoMem(irg);
2363 if (src_mode == mode_b) {
2364 assert(mode_is_int(tgt_mode));
2365 /* nothing to do, we already model bools as 0/1 ints */
2369 if (src_mode == tgt_mode) {
2370 if (get_Conv_strict(node)) {
2371 if (USE_SSE2(env_cg)) {
2372 /* when we are in SSE mode, we can kill all strict no-op conversion */
2376 /* this should be optimized already, but who knows... */
2377 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2378 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2383 if (mode_is_float(src_mode)) {
2384 /* we convert from float ... */
2385 if (mode_is_float(tgt_mode)) {
2386 if(src_mode == mode_E && tgt_mode == mode_D
2387 && !get_Conv_strict(node)) {
2388 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2393 if (USE_SSE2(env_cg)) {
2394 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2395 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2396 set_ia32_ls_mode(res, tgt_mode);
2398 if(get_Conv_strict(node)) {
2399 res = create_strict_conv(tgt_mode, new_op);
2400 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2403 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2408 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2409 if (USE_SSE2(env_cg)) {
2410 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2411 set_ia32_ls_mode(res, src_mode);
2413 return gen_x87_fp_to_gp(node);
2417 /* we convert from int ... */
2418 if (mode_is_float(tgt_mode)) {
2420 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2421 if (USE_SSE2(env_cg)) {
2422 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2423 set_ia32_ls_mode(res, tgt_mode);
2424 if(src_bits == 32) {
2425 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2428 res = gen_x87_gp_to_fp(node, src_mode);
2429 if(get_Conv_strict(node)) {
2430 res = create_strict_conv(tgt_mode, res);
2431 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2432 ia32_get_old_node_name(env_cg, node));
2436 } else if(tgt_mode == mode_b) {
2437 /* mode_b lowering already took care that we only have 0/1 values */
2438 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2439 src_mode, tgt_mode));
2443 if (src_bits == tgt_bits) {
2444 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2445 src_mode, tgt_mode));
2449 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, new_op);
2453 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2459 int check_immediate_constraint(long val, char immediate_constraint_type)
2461 switch (immediate_constraint_type) {
2465 return val >= 0 && val <= 32;
2467 return val >= 0 && val <= 63;
2469 return val >= -128 && val <= 127;
2471 return val == 0xff || val == 0xffff;
2473 return val >= 0 && val <= 3;
2475 return val >= 0 && val <= 255;
2477 return val >= 0 && val <= 127;
2481 panic("Invalid immediate constraint found");
2486 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2489 tarval *offset = NULL;
2490 int offset_sign = 0;
2492 ir_entity *symconst_ent = NULL;
2493 int symconst_sign = 0;
2495 ir_node *cnst = NULL;
2496 ir_node *symconst = NULL;
2502 mode = get_irn_mode(node);
2503 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2507 if(is_Minus(node)) {
2509 node = get_Minus_op(node);
2512 if(is_Const(node)) {
2515 offset_sign = minus;
2516 } else if(is_SymConst(node)) {
2519 symconst_sign = minus;
2520 } else if(is_Add(node)) {
2521 ir_node *left = get_Add_left(node);
2522 ir_node *right = get_Add_right(node);
2523 if(is_Const(left) && is_SymConst(right)) {
2526 symconst_sign = minus;
2527 offset_sign = minus;
2528 } else if(is_SymConst(left) && is_Const(right)) {
2531 symconst_sign = minus;
2532 offset_sign = minus;
2534 } else if(is_Sub(node)) {
2535 ir_node *left = get_Sub_left(node);
2536 ir_node *right = get_Sub_right(node);
2537 if(is_Const(left) && is_SymConst(right)) {
2540 symconst_sign = !minus;
2541 offset_sign = minus;
2542 } else if(is_SymConst(left) && is_Const(right)) {
2545 symconst_sign = minus;
2546 offset_sign = !minus;
2553 offset = get_Const_tarval(cnst);
2554 if(tarval_is_long(offset)) {
2555 val = get_tarval_long(offset);
2556 } else if(tarval_is_null(offset)) {
2559 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2564 if(!check_immediate_constraint(val, immediate_constraint_type))
2567 if(symconst != NULL) {
2568 if(immediate_constraint_type != 0) {
2569 /* we need full 32bits for symconsts */
2573 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2575 symconst_ent = get_SymConst_entity(symconst);
2577 if(cnst == NULL && symconst == NULL)
2580 if(offset_sign && offset != NULL) {
2581 offset = tarval_neg(offset);
2584 irg = current_ir_graph;
2585 dbgi = get_irn_dbg_info(node);
2586 block = get_irg_start_block(irg);
2587 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2588 symconst_sign, val);
2589 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2595 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2597 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2598 if (new_node == NULL) {
2599 new_node = be_transform_node(node);
2604 typedef struct constraint_t constraint_t;
2605 struct constraint_t {
2608 const arch_register_req_t **out_reqs;
2610 const arch_register_req_t *req;
2611 unsigned immediate_possible;
2612 char immediate_type;
2615 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2617 int immediate_possible = 0;
2618 char immediate_type = 0;
2619 unsigned limited = 0;
2620 const arch_register_class_t *cls = NULL;
2622 struct obstack *obst;
2623 arch_register_req_t *req;
2624 unsigned *limited_ptr;
2628 /* TODO: replace all the asserts with nice error messages */
2630 printf("Constraint: %s\n", c);
2640 assert(cls == NULL ||
2641 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2642 cls = &ia32_reg_classes[CLASS_ia32_gp];
2643 limited |= 1 << REG_EAX;
2646 assert(cls == NULL ||
2647 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2648 cls = &ia32_reg_classes[CLASS_ia32_gp];
2649 limited |= 1 << REG_EBX;
2652 assert(cls == NULL ||
2653 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2654 cls = &ia32_reg_classes[CLASS_ia32_gp];
2655 limited |= 1 << REG_ECX;
2658 assert(cls == NULL ||
2659 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2660 cls = &ia32_reg_classes[CLASS_ia32_gp];
2661 limited |= 1 << REG_EDX;
2664 assert(cls == NULL ||
2665 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2666 cls = &ia32_reg_classes[CLASS_ia32_gp];
2667 limited |= 1 << REG_EDI;
2670 assert(cls == NULL ||
2671 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2672 cls = &ia32_reg_classes[CLASS_ia32_gp];
2673 limited |= 1 << REG_ESI;
2676 case 'q': /* q means lower part of the regs only, this makes no
2677 * difference to Q for us (we only assigne whole registers) */
2678 assert(cls == NULL ||
2679 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2680 cls = &ia32_reg_classes[CLASS_ia32_gp];
2681 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2685 assert(cls == NULL ||
2686 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2687 cls = &ia32_reg_classes[CLASS_ia32_gp];
2688 limited |= 1 << REG_EAX | 1 << REG_EDX;
2691 assert(cls == NULL ||
2692 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2693 cls = &ia32_reg_classes[CLASS_ia32_gp];
2694 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2695 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2702 assert(cls == NULL);
2703 cls = &ia32_reg_classes[CLASS_ia32_gp];
2709 /* TODO: mark values so the x87 simulator knows about t and u */
2710 assert(cls == NULL);
2711 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2716 assert(cls == NULL);
2717 /* TODO: check that sse2 is supported */
2718 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2728 assert(!immediate_possible);
2729 immediate_possible = 1;
2730 immediate_type = *c;
2734 assert(!immediate_possible);
2735 immediate_possible = 1;
2739 assert(!immediate_possible && cls == NULL);
2740 immediate_possible = 1;
2741 cls = &ia32_reg_classes[CLASS_ia32_gp];
2754 assert(constraint->is_in && "can only specify same constraint "
2757 sscanf(c, "%d%n", &same_as, &p);
2764 case 'E': /* no float consts yet */
2765 case 'F': /* no float consts yet */
2766 case 's': /* makes no sense on x86 */
2767 case 'X': /* we can't support that in firm */
2771 case '<': /* no autodecrement on x86 */
2772 case '>': /* no autoincrement on x86 */
2773 case 'C': /* sse constant not supported yet */
2774 case 'G': /* 80387 constant not supported yet */
2775 case 'y': /* we don't support mmx registers yet */
2776 case 'Z': /* not available in 32 bit mode */
2777 case 'e': /* not available in 32 bit mode */
2778 assert(0 && "asm constraint not supported");
2781 assert(0 && "unknown asm constraint found");
2788 const arch_register_req_t *other_constr;
2790 assert(cls == NULL && "same as and register constraint not supported");
2791 assert(!immediate_possible && "same as and immediate constraint not "
2793 assert(same_as < constraint->n_outs && "wrong constraint number in "
2794 "same_as constraint");
2796 other_constr = constraint->out_reqs[same_as];
2798 req = obstack_alloc(obst, sizeof(req[0]));
2799 req->cls = other_constr->cls;
2800 req->type = arch_register_req_type_should_be_same;
2801 req->limited = NULL;
2802 req->other_same = pos;
2803 req->other_different = -1;
2805 /* switch constraints. This is because in firm we have same_as
2806 * constraints on the output constraints while in the gcc asm syntax
2807 * they are specified on the input constraints */
2808 constraint->req = other_constr;
2809 constraint->out_reqs[same_as] = req;
2810 constraint->immediate_possible = 0;
2814 if(immediate_possible && cls == NULL) {
2815 cls = &ia32_reg_classes[CLASS_ia32_gp];
2817 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2818 assert(cls != NULL);
2820 if(immediate_possible) {
2821 assert(constraint->is_in
2822 && "imeediates make no sense for output constraints");
2824 /* todo: check types (no float input on 'r' constrainted in and such... */
2826 irg = current_ir_graph;
2827 obst = get_irg_obstack(irg);
2830 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2831 limited_ptr = (unsigned*) (req+1);
2833 req = obstack_alloc(obst, sizeof(req[0]));
2835 memset(req, 0, sizeof(req[0]));
2838 req->type = arch_register_req_type_limited;
2839 *limited_ptr = limited;
2840 req->limited = limited_ptr;
2842 req->type = arch_register_req_type_normal;
2846 constraint->req = req;
2847 constraint->immediate_possible = immediate_possible;
2848 constraint->immediate_type = immediate_type;
2852 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2859 panic("Clobbers not supported yet");
2862 ir_node *gen_ASM(ir_node *node)
2865 ir_graph *irg = current_ir_graph;
2866 ir_node *block = be_transform_node(get_nodes_block(node));
2867 dbg_info *dbgi = get_irn_dbg_info(node);
2874 ia32_asm_attr_t *attr;
2875 const arch_register_req_t **out_reqs;
2876 const arch_register_req_t **in_reqs;
2877 struct obstack *obst;
2878 constraint_t parsed_constraint;
2880 /* transform inputs */
2881 arity = get_irn_arity(node);
2882 in = alloca(arity * sizeof(in[0]));
2883 memset(in, 0, arity * sizeof(in[0]));
2885 n_outs = get_ASM_n_output_constraints(node);
2886 n_clobbers = get_ASM_n_clobbers(node);
2887 out_arity = n_outs + n_clobbers;
2889 /* construct register constraints */
2890 obst = get_irg_obstack(irg);
2891 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2892 parsed_constraint.out_reqs = out_reqs;
2893 parsed_constraint.n_outs = n_outs;
2894 parsed_constraint.is_in = 0;
2895 for(i = 0; i < out_arity; ++i) {
2899 const ir_asm_constraint *constraint;
2900 constraint = & get_ASM_output_constraints(node) [i];
2901 c = get_id_str(constraint->constraint);
2902 parse_asm_constraint(i, &parsed_constraint, c);
2904 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2905 c = get_id_str(glob_id);
2906 parse_clobber(node, i, &parsed_constraint, c);
2908 out_reqs[i] = parsed_constraint.req;
2911 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2912 parsed_constraint.is_in = 1;
2913 for(i = 0; i < arity; ++i) {
2914 const ir_asm_constraint *constraint;
2918 constraint = & get_ASM_input_constraints(node) [i];
2919 constr_id = constraint->constraint;
2920 c = get_id_str(constr_id);
2921 parse_asm_constraint(i, &parsed_constraint, c);
2922 in_reqs[i] = parsed_constraint.req;
2924 if(parsed_constraint.immediate_possible) {
2925 ir_node *pred = get_irn_n(node, i);
2926 char imm_type = parsed_constraint.immediate_type;
2927 ir_node *immediate = try_create_Immediate(pred, imm_type);
2929 if(immediate != NULL) {
2935 /* transform inputs */
2936 for(i = 0; i < arity; ++i) {
2938 ir_node *transformed;
2943 pred = get_irn_n(node, i);
2944 transformed = be_transform_node(pred);
2945 in[i] = transformed;
2948 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2950 generic_attr = get_irn_generic_attr(res);
2951 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2952 attr->asm_text = get_ASM_text(node);
2953 set_ia32_out_req_all(res, out_reqs);
2954 set_ia32_in_req_all(res, in_reqs);
2956 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2961 /********************************************
2964 * | |__ ___ _ __ ___ __| | ___ ___
2965 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2966 * | |_) | __/ | | | (_) | (_| | __/\__ \
2967 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2969 ********************************************/
2971 static ir_node *gen_be_StackParam(ir_node *node) {
2972 ir_node *block = be_transform_node(get_nodes_block(node));
2973 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2974 ir_node *new_ptr = be_transform_node(ptr);
2975 ir_node *new_op = NULL;
2976 ir_graph *irg = current_ir_graph;
2977 dbg_info *dbgi = get_irn_dbg_info(node);
2978 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2979 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2980 ir_mode *load_mode = get_irn_mode(node);
2981 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2985 if (mode_is_float(load_mode)) {
2986 if (USE_SSE2(env_cg)) {
2987 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2988 pn_res = pn_ia32_xLoad_res;
2989 proj_mode = mode_xmm;
2991 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2992 pn_res = pn_ia32_vfld_res;
2993 proj_mode = mode_vfp;
2996 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2997 proj_mode = mode_Iu;
2998 pn_res = pn_ia32_Load_res;
3001 set_irn_pinned(new_op, op_pin_state_floats);
3002 set_ia32_frame_ent(new_op, ent);
3003 set_ia32_use_frame(new_op);
3005 set_ia32_op_type(new_op, ia32_AddrModeS);
3006 set_ia32_am_flavour(new_op, ia32_am_B);
3007 set_ia32_ls_mode(new_op, load_mode);
3008 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
3010 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3012 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
3016 * Transforms a FrameAddr into an ia32 Add.
3018 static ir_node *gen_be_FrameAddr(ir_node *node) {
3019 ir_node *block = be_transform_node(get_nodes_block(node));
3020 ir_node *op = be_get_FrameAddr_frame(node);
3021 ir_node *new_op = be_transform_node(op);
3022 ir_graph *irg = current_ir_graph;
3023 dbg_info *dbgi = get_irn_dbg_info(node);
3024 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3027 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3028 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3029 set_ia32_use_frame(res);
3030 set_ia32_am_flavour(res, ia32_am_OB);
3032 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3038 * Transforms a FrameLoad into an ia32 Load.
3040 static ir_node *gen_be_FrameLoad(ir_node *node) {
3041 ir_node *block = be_transform_node(get_nodes_block(node));
3042 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
3043 ir_node *new_mem = be_transform_node(mem);
3044 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
3045 ir_node *new_ptr = be_transform_node(ptr);
3046 ir_node *new_op = NULL;
3047 ir_graph *irg = current_ir_graph;
3048 dbg_info *dbgi = get_irn_dbg_info(node);
3049 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3050 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
3051 ir_mode *mode = get_type_mode(get_entity_type(ent));
3052 ir_node *projs[pn_Load_max];
3054 ia32_collect_Projs(node, projs, pn_Load_max);
3056 if (mode_is_float(mode)) {
3057 if (USE_SSE2(env_cg)) {
3058 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
3061 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
3065 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
3068 set_irn_pinned(new_op, op_pin_state_floats);
3069 set_ia32_frame_ent(new_op, ent);
3070 set_ia32_use_frame(new_op);
3072 set_ia32_op_type(new_op, ia32_AddrModeS);
3073 set_ia32_am_flavour(new_op, ia32_am_B);
3074 set_ia32_ls_mode(new_op, mode);
3075 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
3077 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3084 * Transforms a FrameStore into an ia32 Store.
3086 static ir_node *gen_be_FrameStore(ir_node *node) {
3087 ir_node *block = be_transform_node(get_nodes_block(node));
3088 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
3089 ir_node *new_mem = be_transform_node(mem);
3090 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
3091 ir_node *new_ptr = be_transform_node(ptr);
3092 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
3093 ir_node *new_val = be_transform_node(val);
3094 ir_node *new_op = NULL;
3095 ir_graph *irg = current_ir_graph;
3096 dbg_info *dbgi = get_irn_dbg_info(node);
3097 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3098 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
3099 ir_mode *mode = get_irn_mode(val);
3101 if (mode_is_float(mode)) {
3102 if (USE_SSE2(env_cg)) {
3103 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3105 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
3107 } else if (get_mode_size_bits(mode) == 8) {
3108 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3110 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3113 set_ia32_frame_ent(new_op, ent);
3114 set_ia32_use_frame(new_op);
3116 set_ia32_op_type(new_op, ia32_AddrModeD);
3117 set_ia32_am_flavour(new_op, ia32_am_B);
3118 set_ia32_ls_mode(new_op, mode);
3120 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3126 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3128 static ir_node *gen_be_Return(ir_node *node) {
3129 ir_graph *irg = current_ir_graph;
3130 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3131 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3132 ir_entity *ent = get_irg_entity(irg);
3133 ir_type *tp = get_entity_type(ent);
3138 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3139 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3142 int pn_ret_val, pn_ret_mem, arity, i;
3144 assert(ret_val != NULL);
3145 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3146 return be_duplicate_node(node);
3149 res_type = get_method_res_type(tp, 0);
3151 if (! is_Primitive_type(res_type)) {
3152 return be_duplicate_node(node);
3155 mode = get_type_mode(res_type);
3156 if (! mode_is_float(mode)) {
3157 return be_duplicate_node(node);
3160 assert(get_method_n_ress(tp) == 1);
3162 pn_ret_val = get_Proj_proj(ret_val);
3163 pn_ret_mem = get_Proj_proj(ret_mem);
3165 /* get the Barrier */
3166 barrier = get_Proj_pred(ret_val);
3168 /* get result input of the Barrier */
3169 ret_val = get_irn_n(barrier, pn_ret_val);
3170 new_ret_val = be_transform_node(ret_val);
3172 /* get memory input of the Barrier */
3173 ret_mem = get_irn_n(barrier, pn_ret_mem);
3174 new_ret_mem = be_transform_node(ret_mem);
3176 frame = get_irg_frame(irg);
3178 dbgi = get_irn_dbg_info(barrier);
3179 block = be_transform_node(get_nodes_block(barrier));
3181 noreg = ia32_new_NoReg_gp(env_cg);
3183 /* store xmm0 onto stack */
3184 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3185 new_ret_val, new_ret_mem);
3186 set_ia32_ls_mode(sse_store, mode);
3187 set_ia32_op_type(sse_store, ia32_AddrModeD);
3188 set_ia32_use_frame(sse_store);
3189 set_ia32_am_flavour(sse_store, ia32_am_B);
3191 /* load into x87 register */
3192 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3193 set_ia32_op_type(fld, ia32_AddrModeS);
3194 set_ia32_use_frame(fld);
3195 set_ia32_am_flavour(fld, ia32_am_B);
3197 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3198 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3200 /* create a new barrier */
3201 arity = get_irn_arity(barrier);
3202 in = alloca(arity * sizeof(in[0]));
3203 for (i = 0; i < arity; ++i) {
3206 if (i == pn_ret_val) {
3208 } else if (i == pn_ret_mem) {
3211 ir_node *in = get_irn_n(barrier, i);
3212 new_in = be_transform_node(in);
3217 new_barrier = new_ir_node(dbgi, irg, block,
3218 get_irn_op(barrier), get_irn_mode(barrier),
3220 copy_node_attr(barrier, new_barrier);
3221 be_duplicate_deps(barrier, new_barrier);
3222 be_set_transformed_node(barrier, new_barrier);
3223 mark_irn_visited(barrier);
3225 /* transform normally */
3226 return be_duplicate_node(node);
3230 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3232 static ir_node *gen_be_AddSP(ir_node *node) {
3233 ir_node *block = be_transform_node(get_nodes_block(node));
3234 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3236 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3237 ir_node *new_sp = be_transform_node(sp);
3238 ir_graph *irg = current_ir_graph;
3239 dbg_info *dbgi = get_irn_dbg_info(node);
3240 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3241 ir_node *nomem = new_NoMem();
3244 new_sz = create_immediate_or_transform(sz, 0);
3246 /* ia32 stack grows in reverse direction, make a SubSP */
3247 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3249 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3250 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3256 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3258 static ir_node *gen_be_SubSP(ir_node *node) {
3259 ir_node *block = be_transform_node(get_nodes_block(node));
3260 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3262 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3263 ir_node *new_sp = be_transform_node(sp);
3264 ir_graph *irg = current_ir_graph;
3265 dbg_info *dbgi = get_irn_dbg_info(node);
3266 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3267 ir_node *nomem = new_NoMem();
3270 new_sz = create_immediate_or_transform(sz, 0);
3272 /* ia32 stack grows in reverse direction, make an AddSP */
3273 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3274 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3275 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3281 * This function just sets the register for the Unknown node
3282 * as this is not done during register allocation because Unknown
3283 * is an "ignore" node.
3285 static ir_node *gen_Unknown(ir_node *node) {
3286 ir_mode *mode = get_irn_mode(node);
3288 if (mode_is_float(mode)) {
3290 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3291 if (USE_SSE2(env_cg))
3292 return ia32_new_Unknown_xmm(env_cg);
3294 return ia32_new_Unknown_vfp(env_cg);
3296 ir_graph *irg = current_ir_graph;
3297 dbg_info *dbgi = get_irn_dbg_info(node);
3298 ir_node *block = get_irg_start_block(irg);
3299 return new_rd_ia32_vfldz(dbgi, irg, block);
3301 } else if (mode_needs_gp_reg(mode)) {
3302 return ia32_new_Unknown_gp(env_cg);
3304 assert(0 && "unsupported Unknown-Mode");
3311 * Change some phi modes
3313 static ir_node *gen_Phi(ir_node *node) {
3314 ir_node *block = be_transform_node(get_nodes_block(node));
3315 ir_graph *irg = current_ir_graph;
3316 dbg_info *dbgi = get_irn_dbg_info(node);
3317 ir_mode *mode = get_irn_mode(node);
3320 if(mode_needs_gp_reg(mode)) {
3321 /* we shouldn't have any 64bit stuff around anymore */
3322 assert(get_mode_size_bits(mode) <= 32);
3323 /* all integer operations are on 32bit registers now */
3325 } else if(mode_is_float(mode)) {
3326 if (USE_SSE2(env_cg)) {
3333 /* phi nodes allow loops, so we use the old arguments for now
3334 * and fix this later */
3335 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3336 copy_node_attr(node, phi);
3337 be_duplicate_deps(node, phi);
3339 be_set_transformed_node(node, phi);
3340 be_enqueue_preds(node);
3348 static ir_node *gen_IJmp(ir_node *node) {
3349 ir_node *block = be_transform_node(get_nodes_block(node));
3350 ir_graph *irg = current_ir_graph;
3351 dbg_info *dbgi = get_irn_dbg_info(node);
3352 ir_node *new_op = be_transform_node(get_IJmp_target(node));
3353 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3354 ir_node *nomem = new_NoMem();
3357 new_node = new_rd_ia32_IJmp(dbgi, irg, block, noreg, noreg, new_op, nomem);
3358 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_unary);
3360 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3366 /**********************************************************************
3369 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3370 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3371 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3372 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3374 **********************************************************************/
3376 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3378 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3381 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3382 ir_node *val, ir_node *mem);
3385 * Transforms a lowered Load into a "real" one.
3387 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3389 ir_node *block = be_transform_node(get_nodes_block(node));
3390 ir_node *ptr = get_irn_n(node, 0);
3391 ir_node *new_ptr = be_transform_node(ptr);
3392 ir_node *mem = get_irn_n(node, 1);
3393 ir_node *new_mem = be_transform_node(mem);
3394 ir_graph *irg = current_ir_graph;
3395 dbg_info *dbgi = get_irn_dbg_info(node);
3396 ir_mode *mode = get_ia32_ls_mode(node);
3397 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3400 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3402 set_ia32_op_type(new_op, ia32_AddrModeS);
3403 set_ia32_am_flavour(new_op, ia32_am_OB);
3404 set_ia32_am_offs_int(new_op, 0);
3405 set_ia32_am_scale(new_op, 1);
3406 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3407 if (is_ia32_am_sc_sign(node))
3408 set_ia32_am_sc_sign(new_op);
3409 set_ia32_ls_mode(new_op, mode);
3410 if (is_ia32_use_frame(node)) {
3411 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3412 set_ia32_use_frame(new_op);
3415 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3421 * Transforms a lowered Store into a "real" one.
3423 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3425 ir_node *block = be_transform_node(get_nodes_block(node));
3426 ir_node *ptr = get_irn_n(node, 0);
3427 ir_node *new_ptr = be_transform_node(ptr);
3428 ir_node *val = get_irn_n(node, 1);
3429 ir_node *new_val = be_transform_node(val);
3430 ir_node *mem = get_irn_n(node, 2);
3431 ir_node *new_mem = be_transform_node(mem);
3432 ir_graph *irg = current_ir_graph;
3433 dbg_info *dbgi = get_irn_dbg_info(node);
3434 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3435 ir_mode *mode = get_ia32_ls_mode(node);
3438 ia32_am_flavour_t am_flav = ia32_B;
3440 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3442 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3444 add_ia32_am_offs_int(new_op, am_offs);
3447 set_ia32_op_type(new_op, ia32_AddrModeD);
3448 set_ia32_am_flavour(new_op, am_flav);
3449 set_ia32_ls_mode(new_op, mode);
3450 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3451 set_ia32_use_frame(new_op);
3453 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3460 * Transforms an ia32_l_XXX into a "real" XXX node
3462 * @param env The transformation environment
3463 * @return the created ia32 XXX node
3465 #define GEN_LOWERED_OP(op) \
3466 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3467 return gen_binop(node, get_binop_left(node), \
3468 get_binop_right(node), new_rd_ia32_##op,0); \
3471 #define GEN_LOWERED_x87_OP(op) \
3472 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3474 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3475 get_binop_right(node), new_rd_ia32_##op); \
3479 #define GEN_LOWERED_UNOP(op) \
3480 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3481 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3484 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3485 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3486 return gen_shift_binop(node, get_irn_n(node, 0), \
3487 get_irn_n(node, 1), new_rd_ia32_##op); \
3490 #define GEN_LOWERED_LOAD(op) \
3491 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3492 return gen_lowered_Load(node, new_rd_ia32_##op); \
3495 #define GEN_LOWERED_STORE(op) \
3496 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3497 return gen_lowered_Store(node, new_rd_ia32_##op); \
3504 GEN_LOWERED_OP(IMul)
3506 GEN_LOWERED_x87_OP(vfprem)
3507 GEN_LOWERED_x87_OP(vfmul)
3508 GEN_LOWERED_x87_OP(vfsub)
3510 GEN_LOWERED_UNOP(Neg)
3512 GEN_LOWERED_LOAD(vfild)
3513 GEN_LOWERED_LOAD(Load)
3514 GEN_LOWERED_STORE(Store)
3517 * Transforms a l_vfist into a "real" vfist node.
3519 * @param env The transformation environment
3520 * @return the created ia32 vfist node
3522 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3523 ir_node *block = be_transform_node(get_nodes_block(node));
3524 ir_node *ptr = get_irn_n(node, 0);
3525 ir_node *new_ptr = be_transform_node(ptr);
3526 ir_node *val = get_irn_n(node, 1);
3527 ir_node *new_val = be_transform_node(val);
3528 ir_node *mem = get_irn_n(node, 2);
3529 ir_node *new_mem = be_transform_node(mem);
3530 ir_graph *irg = current_ir_graph;
3531 dbg_info *dbgi = get_irn_dbg_info(node);
3532 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3533 ir_mode *mode = get_ia32_ls_mode(node);
3534 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3537 ia32_am_flavour_t am_flav = ia32_B;
3539 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_val, trunc_mode, new_mem);
3541 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3543 add_ia32_am_offs_int(new_op, am_offs);
3546 set_ia32_op_type(new_op, ia32_AddrModeD);
3547 set_ia32_am_flavour(new_op, am_flav);
3548 set_ia32_ls_mode(new_op, mode);
3549 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3550 set_ia32_use_frame(new_op);
3552 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3558 * Transforms a l_vfdiv into a "real" vfdiv node.
3560 * @param env The transformation environment
3561 * @return the created ia32 vfdiv node
3563 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3564 ir_node *block = be_transform_node(get_nodes_block(node));
3565 ir_node *left = get_binop_left(node);
3566 ir_node *new_left = be_transform_node(left);
3567 ir_node *right = get_binop_right(node);
3568 ir_node *new_right = be_transform_node(right);
3569 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3570 ir_graph *irg = current_ir_graph;
3571 dbg_info *dbgi = get_irn_dbg_info(node);
3572 ir_node *fpcw = get_fpcw();
3575 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3576 new_right, new_NoMem(), fpcw);
3577 clear_ia32_commutative(vfdiv);
3578 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3580 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3586 * Transforms a l_MulS into a "real" MulS node.
3588 * @param env The transformation environment
3589 * @return the created ia32 Mul node
3591 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3592 ir_node *block = be_transform_node(get_nodes_block(node));
3593 ir_node *left = get_binop_left(node);
3594 ir_node *new_left = be_transform_node(left);
3595 ir_node *right = get_binop_right(node);
3596 ir_node *new_right = be_transform_node(right);
3597 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3598 ir_graph *irg = current_ir_graph;
3599 dbg_info *dbgi = get_irn_dbg_info(node);
3601 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3602 /* and then skip the result Proj, because all needed Projs are already there. */
3603 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3604 new_right, new_NoMem());
3605 clear_ia32_commutative(muls);
3606 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3608 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3613 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3614 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3615 GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
3616 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3619 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3620 * op1 - target to be shifted
3621 * op2 - contains bits to be shifted into target
3623 * Only op3 can be an immediate.
3625 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3626 ir_node *op2, ir_node *count)
3628 ir_node *block = be_transform_node(get_nodes_block(node));
3629 ir_node *new_op1 = be_transform_node(op1);
3630 ir_node *new_op2 = be_transform_node(op2);
3631 ir_node *new_op = NULL;
3632 ir_node *new_count = be_transform_node(count);
3633 ir_graph *irg = current_ir_graph;
3634 dbg_info *dbgi = get_irn_dbg_info(node);
3635 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3636 ir_node *nomem = new_NoMem();
3640 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3642 /* Check if immediate optimization is on and */
3643 /* if it's an operation with immediate. */
3644 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3646 /* Limit imm_op within range imm8 */
3648 tv = get_ia32_Immop_tarval(imm_op);
3651 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3652 set_ia32_Immop_tarval(imm_op, tv);
3659 /* integer operations */
3661 /* This is ShiftD with const */
3662 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3664 if (is_ia32_l_ShlD(node))
3665 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3666 new_op1, new_op2, noreg, nomem);
3668 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3669 new_op1, new_op2, noreg, nomem);
3670 copy_ia32_Immop_attr(new_op, imm_op);
3673 /* This is a normal ShiftD */
3674 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3675 if (is_ia32_l_ShlD(node))
3676 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3677 new_op1, new_op2, new_count, nomem);
3679 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3680 new_op1, new_op2, new_count, nomem);
3683 /* set AM support */
3684 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3686 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3688 set_ia32_emit_cl(new_op);
3693 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3694 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3695 get_irn_n(node, 1), get_irn_n(node, 2));
3698 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3699 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3700 get_irn_n(node, 1), get_irn_n(node, 2));
3704 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3706 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3707 ir_node *block = be_transform_node(get_nodes_block(node));
3708 ir_node *val = get_irn_n(node, 1);
3709 ir_node *new_val = be_transform_node(val);
3710 ia32_code_gen_t *cg = env_cg;
3711 ir_node *res = NULL;
3712 ir_graph *irg = current_ir_graph;
3714 ir_node *noreg, *new_ptr, *new_mem;
3721 mem = get_irn_n(node, 2);
3722 new_mem = be_transform_node(mem);
3723 ptr = get_irn_n(node, 0);
3724 new_ptr = be_transform_node(ptr);
3725 noreg = ia32_new_NoReg_gp(cg);
3726 dbgi = get_irn_dbg_info(node);
3728 /* Store x87 -> MEM */
3729 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3730 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3731 set_ia32_use_frame(res);
3732 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3733 set_ia32_am_flavour(res, ia32_B);
3734 set_ia32_op_type(res, ia32_AddrModeD);
3736 /* Load MEM -> SSE */
3737 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3738 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3739 set_ia32_use_frame(res);
3740 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3741 set_ia32_am_flavour(res, ia32_B);
3742 set_ia32_op_type(res, ia32_AddrModeS);
3743 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3749 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3751 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3752 ir_node *block = be_transform_node(get_nodes_block(node));
3753 ir_node *val = get_irn_n(node, 1);
3754 ir_node *new_val = be_transform_node(val);
3755 ia32_code_gen_t *cg = env_cg;
3756 ir_graph *irg = current_ir_graph;
3757 ir_node *res = NULL;
3758 ir_entity *fent = get_ia32_frame_ent(node);
3759 ir_mode *lsmode = get_ia32_ls_mode(node);
3761 ir_node *noreg, *new_ptr, *new_mem;
3765 if (! USE_SSE2(cg)) {
3766 /* SSE unit is not used -> skip this node. */
3770 ptr = get_irn_n(node, 0);
3771 new_ptr = be_transform_node(ptr);
3772 mem = get_irn_n(node, 2);
3773 new_mem = be_transform_node(mem);
3774 noreg = ia32_new_NoReg_gp(cg);
3775 dbgi = get_irn_dbg_info(node);
3777 /* Store SSE -> MEM */
3778 if (is_ia32_xLoad(skip_Proj(new_val))) {
3779 ir_node *ld = skip_Proj(new_val);
3781 /* we can vfld the value directly into the fpu */
3782 fent = get_ia32_frame_ent(ld);
3783 ptr = get_irn_n(ld, 0);
3784 offs = get_ia32_am_offs_int(ld);
3786 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3787 set_ia32_frame_ent(res, fent);
3788 set_ia32_use_frame(res);
3789 set_ia32_ls_mode(res, lsmode);
3790 set_ia32_am_flavour(res, ia32_B);
3791 set_ia32_op_type(res, ia32_AddrModeD);
3795 /* Load MEM -> x87 */
3796 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3797 set_ia32_frame_ent(res, fent);
3798 set_ia32_use_frame(res);
3799 add_ia32_am_offs_int(res, offs);
3800 set_ia32_am_flavour(res, ia32_B);
3801 set_ia32_op_type(res, ia32_AddrModeS);
3802 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3807 /*********************************************************
3810 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3811 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3812 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3813 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3815 *********************************************************/
3818 * the BAD transformer.
3820 static ir_node *bad_transform(ir_node *node) {
3821 panic("No transform function for %+F available.\n", node);
3826 * Transform the Projs of an AddSP.
3828 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3829 ir_node *block = be_transform_node(get_nodes_block(node));
3830 ir_node *pred = get_Proj_pred(node);
3831 ir_node *new_pred = be_transform_node(pred);
3832 ir_graph *irg = current_ir_graph;
3833 dbg_info *dbgi = get_irn_dbg_info(node);
3834 long proj = get_Proj_proj(node);
3836 if (proj == pn_be_AddSP_sp) {
3837 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3838 pn_ia32_SubSP_stack);
3839 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3841 } else if(proj == pn_be_AddSP_res) {
3842 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3843 pn_ia32_SubSP_addr);
3844 } else if (proj == pn_be_AddSP_M) {
3845 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3849 return new_rd_Unknown(irg, get_irn_mode(node));
3853 * Transform the Projs of a SubSP.
3855 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3856 ir_node *block = be_transform_node(get_nodes_block(node));
3857 ir_node *pred = get_Proj_pred(node);
3858 ir_node *new_pred = be_transform_node(pred);
3859 ir_graph *irg = current_ir_graph;
3860 dbg_info *dbgi = get_irn_dbg_info(node);
3861 long proj = get_Proj_proj(node);
3863 if (proj == pn_be_SubSP_sp) {
3864 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3865 pn_ia32_AddSP_stack);
3866 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3868 } else if (proj == pn_be_SubSP_M) {
3869 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3873 return new_rd_Unknown(irg, get_irn_mode(node));
3877 * Transform and renumber the Projs from a Load.
3879 static ir_node *gen_Proj_Load(ir_node *node) {
3880 ir_node *block = be_transform_node(get_nodes_block(node));
3881 ir_node *pred = get_Proj_pred(node);
3882 ir_node *new_pred = be_transform_node(pred);
3883 ir_graph *irg = current_ir_graph;
3884 dbg_info *dbgi = get_irn_dbg_info(node);
3885 long proj = get_Proj_proj(node);
3887 /* renumber the proj */
3888 if (is_ia32_Load(new_pred)) {
3889 if (proj == pn_Load_res) {
3890 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3891 } else if (proj == pn_Load_M) {
3892 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3894 } else if(is_ia32_Conv_I2I(new_pred)) {
3895 set_irn_mode(new_pred, mode_T);
3896 if (proj == pn_Load_res) {
3897 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, 0);
3898 } else if (proj == pn_Load_M) {
3899 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
3901 } else if (is_ia32_xLoad(new_pred)) {
3902 if (proj == pn_Load_res) {
3903 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3904 } else if (proj == pn_Load_M) {
3905 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3907 } else if (is_ia32_vfld(new_pred)) {
3908 if (proj == pn_Load_res) {
3909 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3910 } else if (proj == pn_Load_M) {
3911 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3916 return new_rd_Unknown(irg, get_irn_mode(node));
3920 * Transform and renumber the Projs from a DivMod like instruction.
3922 static ir_node *gen_Proj_DivMod(ir_node *node) {
3923 ir_node *block = be_transform_node(get_nodes_block(node));
3924 ir_node *pred = get_Proj_pred(node);
3925 ir_node *new_pred = be_transform_node(pred);
3926 ir_graph *irg = current_ir_graph;
3927 dbg_info *dbgi = get_irn_dbg_info(node);
3928 ir_mode *mode = get_irn_mode(node);
3929 long proj = get_Proj_proj(node);
3931 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3933 switch (get_irn_opcode(pred)) {
3937 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3939 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3947 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3949 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3957 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3958 case pn_DivMod_res_div:
3959 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3960 case pn_DivMod_res_mod:
3961 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3971 return new_rd_Unknown(irg, mode);
3975 * Transform and renumber the Projs from a CopyB.
3977 static ir_node *gen_Proj_CopyB(ir_node *node) {
3978 ir_node *block = be_transform_node(get_nodes_block(node));
3979 ir_node *pred = get_Proj_pred(node);
3980 ir_node *new_pred = be_transform_node(pred);
3981 ir_graph *irg = current_ir_graph;
3982 dbg_info *dbgi = get_irn_dbg_info(node);
3983 ir_mode *mode = get_irn_mode(node);
3984 long proj = get_Proj_proj(node);
3987 case pn_CopyB_M_regular:
3988 if (is_ia32_CopyB_i(new_pred)) {
3989 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3990 } else if (is_ia32_CopyB(new_pred)) {
3991 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3999 return new_rd_Unknown(irg, mode);
4003 * Transform and renumber the Projs from a vfdiv.
4005 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
4006 ir_node *block = be_transform_node(get_nodes_block(node));
4007 ir_node *pred = get_Proj_pred(node);
4008 ir_node *new_pred = be_transform_node(pred);
4009 ir_graph *irg = current_ir_graph;
4010 dbg_info *dbgi = get_irn_dbg_info(node);
4011 ir_mode *mode = get_irn_mode(node);
4012 long proj = get_Proj_proj(node);
4015 case pn_ia32_l_vfdiv_M:
4016 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4017 case pn_ia32_l_vfdiv_res:
4018 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4023 return new_rd_Unknown(irg, mode);
4027 * Transform and renumber the Projs from a Quot.
4029 static ir_node *gen_Proj_Quot(ir_node *node) {
4030 ir_node *block = be_transform_node(get_nodes_block(node));
4031 ir_node *pred = get_Proj_pred(node);
4032 ir_node *new_pred = be_transform_node(pred);
4033 ir_graph *irg = current_ir_graph;
4034 dbg_info *dbgi = get_irn_dbg_info(node);
4035 ir_mode *mode = get_irn_mode(node);
4036 long proj = get_Proj_proj(node);
4040 if (is_ia32_xDiv(new_pred)) {
4041 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4042 } else if (is_ia32_vfdiv(new_pred)) {
4043 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4047 if (is_ia32_xDiv(new_pred)) {
4048 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4049 } else if (is_ia32_vfdiv(new_pred)) {
4050 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4058 return new_rd_Unknown(irg, mode);
4062 * Transform the Thread Local Storage Proj.
4064 static ir_node *gen_Proj_tls(ir_node *node) {
4065 ir_node *block = be_transform_node(get_nodes_block(node));
4066 ir_graph *irg = current_ir_graph;
4067 dbg_info *dbgi = NULL;
4068 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4074 * Transform the Projs from a be_Call.
4076 static ir_node *gen_Proj_be_Call(ir_node *node) {
4077 ir_node *block = be_transform_node(get_nodes_block(node));
4078 ir_node *call = get_Proj_pred(node);
4079 ir_node *new_call = be_transform_node(call);
4080 ir_graph *irg = current_ir_graph;
4081 dbg_info *dbgi = get_irn_dbg_info(node);
4082 long proj = get_Proj_proj(node);
4083 ir_mode *mode = get_irn_mode(node);
4085 const arch_register_class_t *cls;
4087 /* The following is kinda tricky: If we're using SSE, then we have to
4088 * move the result value of the call in floating point registers to an
4089 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4090 * after the call, we have to make sure to correctly make the
4091 * MemProj and the result Proj use these 2 nodes
4093 if (proj == pn_be_Call_M_regular) {
4094 // get new node for result, are we doing the sse load/store hack?
4095 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4096 ir_node *call_res_new;
4097 ir_node *call_res_pred = NULL;
4099 if (call_res != NULL) {
4100 call_res_new = be_transform_node(call_res);
4101 call_res_pred = get_Proj_pred(call_res_new);
4104 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4105 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4106 pn_be_Call_M_regular);
4108 assert(is_ia32_xLoad(call_res_pred));
4109 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4113 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
4115 ir_node *frame = get_irg_frame(irg);
4116 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4118 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4121 /* in case there is no memory output: create one to serialize the copy
4123 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4124 pn_be_Call_M_regular);
4125 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4126 pn_be_Call_first_res);
4128 /* store st(0) onto stack */
4129 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4131 set_ia32_op_type(fstp, ia32_AddrModeD);
4132 set_ia32_use_frame(fstp);
4133 set_ia32_am_flavour(fstp, ia32_am_B);
4135 /* load into SSE register */
4136 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
4137 set_ia32_ls_mode(sse_load, mode);
4138 set_ia32_op_type(sse_load, ia32_AddrModeS);
4139 set_ia32_use_frame(sse_load);
4140 set_ia32_am_flavour(sse_load, ia32_am_B);
4142 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4146 /* now: create new Keep whith all former ins and one additional in - the result Proj */
4148 /* get a Proj representing a caller save register */
4149 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
4150 assert(is_Proj(p) && "Proj expected.");
4152 /* user of the the proj is the Keep */
4153 p = get_edge_src_irn(get_irn_out_edge_first(p));
4154 assert(be_is_Keep(p) && "Keep expected.");
4160 /* transform call modes */
4161 if (mode_is_data(mode)) {
4162 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4166 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4170 * Transform the Projs from a Cmp.
4172 static ir_node *gen_Proj_Cmp(ir_node *node)
4174 /* normally Cmps are processed when looking at Cond nodes, but this case
4175 * can happen in complicated Psi conditions */
4177 ir_node *cmp = get_Proj_pred(node);
4178 long pnc = get_Proj_proj(node);
4179 ir_node *cmp_left = get_Cmp_left(cmp);
4180 ir_node *cmp_right = get_Cmp_right(cmp);
4181 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4182 dbg_info *dbgi = get_irn_dbg_info(cmp);
4183 ir_node *block = be_transform_node(get_nodes_block(node));
4186 assert(!mode_is_float(cmp_mode));
4188 if(!mode_is_signed(cmp_mode)) {
4189 pnc |= ia32_pn_Cmp_Unsigned;
4192 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
4193 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
4199 * Transform and potentially renumber Proj nodes.
4201 static ir_node *gen_Proj(ir_node *node) {
4202 ir_graph *irg = current_ir_graph;
4203 dbg_info *dbgi = get_irn_dbg_info(node);
4204 ir_node *pred = get_Proj_pred(node);
4205 long proj = get_Proj_proj(node);
4207 if (is_Store(pred) || be_is_FrameStore(pred)) {
4208 if (proj == pn_Store_M) {
4209 return be_transform_node(pred);
4212 return new_r_Bad(irg);
4214 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4215 return gen_Proj_Load(node);
4216 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4217 return gen_Proj_DivMod(node);
4218 } else if (is_CopyB(pred)) {
4219 return gen_Proj_CopyB(node);
4220 } else if (is_Quot(pred)) {
4221 return gen_Proj_Quot(node);
4222 } else if (is_ia32_l_vfdiv(pred)) {
4223 return gen_Proj_l_vfdiv(node);
4224 } else if (be_is_SubSP(pred)) {
4225 return gen_Proj_be_SubSP(node);
4226 } else if (be_is_AddSP(pred)) {
4227 return gen_Proj_be_AddSP(node);
4228 } else if (be_is_Call(pred)) {
4229 return gen_Proj_be_Call(node);
4230 } else if (is_Cmp(pred)) {
4231 return gen_Proj_Cmp(node);
4232 } else if (get_irn_op(pred) == op_Start) {
4233 if (proj == pn_Start_X_initial_exec) {
4234 ir_node *block = get_nodes_block(pred);
4237 /* we exchange the ProjX with a jump */
4238 block = be_transform_node(block);
4239 jump = new_rd_Jmp(dbgi, irg, block);
4242 if (node == be_get_old_anchor(anchor_tls)) {
4243 return gen_Proj_tls(node);
4246 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4250 ir_node *new_pred = be_transform_node(pred);
4251 ir_node *block = be_transform_node(get_nodes_block(node));
4252 ir_mode *mode = get_irn_mode(node);
4253 if (mode_needs_gp_reg(mode)) {
4254 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4255 get_Proj_proj(node));
4256 #ifdef DEBUG_libfirm
4257 new_proj->node_nr = node->node_nr;
4263 return be_duplicate_node(node);
4267 * Enters all transform functions into the generic pointer
4269 static void register_transformers(void)
4273 /* first clear the generic function pointer for all ops */
4274 clear_irp_opcodes_generic_func();
4276 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4277 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4314 /* transform ops from intrinsic lowering */
4337 GEN(ia32_l_X87toSSE);
4338 GEN(ia32_l_SSEtoX87);
4343 /* we should never see these nodes */
4358 /* handle generic backend nodes */
4369 /* set the register for all Unknown nodes */
4372 op_Mulh = get_op_Mulh();
4381 * Pre-transform all unknown and noreg nodes.
4383 static void ia32_pretransform_node(void *arch_cg) {
4384 ia32_code_gen_t *cg = arch_cg;
4386 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4387 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4388 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4389 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4390 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4391 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4396 * Walker, checks if all ia32 nodes producing more than one result have
4397 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4400 void add_missing_keep_walker(ir_node *node, void *data)
4403 unsigned found_projs = 0;
4404 const ir_edge_t *edge;
4405 ir_mode *mode = get_irn_mode(node);
4410 if(!is_ia32_irn(node))
4413 n_outs = get_ia32_n_res(node);
4416 if(is_ia32_SwitchJmp(node))
4419 assert(n_outs < (int) sizeof(unsigned) * 8);
4420 foreach_out_edge(node, edge) {
4421 ir_node *proj = get_edge_src_irn(edge);
4422 int pn = get_Proj_proj(proj);
4424 assert(pn < n_outs);
4425 found_projs |= 1 << pn;
4429 /* are keeps missing? */
4431 for(i = 0; i < n_outs; ++i) {
4434 const arch_register_req_t *req;
4435 const arch_register_class_t *class;
4437 if(found_projs & (1 << i)) {
4441 req = get_ia32_out_req(node, i);
4447 block = get_nodes_block(node);
4448 in[0] = new_r_Proj(current_ir_graph, block, node,
4449 arch_register_class_mode(class), i);
4450 if(last_keep != NULL) {
4451 be_Keep_add_node(last_keep, class, in[0]);
4453 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4459 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4463 void add_missing_keeps(ia32_code_gen_t *cg)
4465 ir_graph *irg = be_get_birg_irg(cg->birg);
4466 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4469 /* do the transformation */
4470 void ia32_transform_graph(ia32_code_gen_t *cg) {
4471 register_transformers();
4473 initial_fpcw = NULL;
4474 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4475 edges_verify(cg->irg);
4476 add_missing_keeps(cg);
4477 edges_verify(cg->irg);
4480 void ia32_init_transform(void)
4482 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");