2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_map_regs.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
67 #include "gen_ia32_regalloc_if.h"
69 #define SFP_SIGN "0x80000000"
70 #define DFP_SIGN "0x8000000000000000"
71 #define SFP_ABS "0x7FFFFFFF"
72 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
74 #define TP_SFP_SIGN "ia32_sfp_sign"
75 #define TP_DFP_SIGN "ia32_dfp_sign"
76 #define TP_SFP_ABS "ia32_sfp_abs"
77 #define TP_DFP_ABS "ia32_dfp_abs"
79 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
80 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
81 #define ENT_SFP_ABS "IA32_SFP_ABS"
82 #define ENT_DFP_ABS "IA32_DFP_ABS"
84 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
85 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
87 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 /** hold the current code generator during transformation */
90 static ia32_code_gen_t *env_cg = NULL;
91 static ir_node *initial_fpcw = NULL;
93 extern ir_op *get_op_Mulh(void);
95 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
96 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
97 ir_node *op2, ir_node *mem);
99 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
100 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
101 ir_node *op2, ir_node *mem, ir_node *fpcw);
103 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
104 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
107 /****************************************************************************************************
109 * | | | | / _| | | (_)
110 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
111 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
112 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
113 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
115 ****************************************************************************************************/
117 static ir_node *try_create_Immediate(ir_node *node,
118 char immediate_constraint_type);
120 static ir_node *create_immediate_or_transform(ir_node *node,
121 char immediate_constraint_type);
123 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
124 dbg_info *dbgi, ir_node *new_block,
128 * Return true if a mode can be stored in the GP register set
130 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
131 if(mode == mode_fpcw)
133 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
137 * Returns 1 if irn is a Const representing 0, 0 otherwise
139 static INLINE int is_ia32_Const_0(ir_node *irn) {
140 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
141 && tarval_is_null(get_ia32_Immop_tarval(irn));
145 * Returns 1 if irn is a Const representing 1, 0 otherwise
147 static INLINE int is_ia32_Const_1(ir_node *irn) {
148 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
149 && tarval_is_one(get_ia32_Immop_tarval(irn));
153 * Collects all Projs of a node into the node array. Index is the projnum.
154 * BEWARE: The caller has to assure the appropriate array size!
156 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
157 const ir_edge_t *edge;
158 assert(get_irn_mode(irn) == mode_T && "need mode_T");
160 memset(projs, 0, size * sizeof(projs[0]));
162 foreach_out_edge(irn, edge) {
163 ir_node *proj = get_edge_src_irn(edge);
164 int proj_proj = get_Proj_proj(proj);
165 assert(proj_proj < size);
166 projs[proj_proj] = proj;
171 * Renumbers the proj having pn_old in the array tp pn_new
172 * and removes the proj from the array.
174 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
175 fprintf(stderr, "Warning: renumber_Proj used!\n");
177 set_Proj_proj(projs[pn_old], pn_new);
178 projs[pn_old] = NULL;
183 * creates a unique ident by adding a number to a tag
185 * @param tag the tag string, must contain a %d if a number
188 static ident *unique_id(const char *tag)
190 static unsigned id = 0;
193 snprintf(str, sizeof(str), tag, ++id);
194 return new_id_from_str(str);
198 * Get a primitive type for a mode.
200 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
202 pmap_entry *e = pmap_find(types, mode);
207 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
208 res = new_type_primitive(new_id_from_str(buf), mode);
209 set_type_alignment_bytes(res, 16);
210 pmap_insert(types, mode, res);
218 * Get an entity that is initialized with a tarval
220 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
222 tarval *tv = get_Const_tarval(cnst);
223 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
228 ir_mode *mode = get_irn_mode(cnst);
229 ir_type *tp = get_Const_type(cnst);
230 if (tp == firm_unknown_type)
231 tp = get_prim_type(cg->isa->types, mode);
233 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
235 set_entity_ld_ident(res, get_entity_ident(res));
236 set_entity_visibility(res, visibility_local);
237 set_entity_variability(res, variability_constant);
238 set_entity_allocation(res, allocation_static);
240 /* we create a new entity here: It's initialization must resist on the
242 rem = current_ir_graph;
243 current_ir_graph = get_const_code_irg();
244 set_atomic_ent_value(res, new_Const_type(tv, tp));
245 current_ir_graph = rem;
247 pmap_insert(cg->isa->tv_ent, tv, res);
255 static int is_Const_0(ir_node *node) {
259 return classify_Const(node) == CNST_NULL;
262 static int is_Const_1(ir_node *node) {
266 return classify_Const(node) == CNST_ONE;
270 * Transforms a Const.
272 static ir_node *gen_Const(ir_node *node) {
273 ir_graph *irg = current_ir_graph;
274 ir_node *old_block = get_nodes_block(node);
275 ir_node *block = be_transform_node(old_block);
276 dbg_info *dbgi = get_irn_dbg_info(node);
277 ir_mode *mode = get_irn_mode(node);
279 if (mode_is_float(mode)) {
281 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
282 ir_node *nomem = new_NoMem();
286 if (! USE_SSE2(env_cg)) {
287 cnst_classify_t clss = classify_Const(node);
289 if (clss == CNST_NULL) {
290 load = new_rd_ia32_vfldz(dbgi, irg, block);
292 } else if (clss == CNST_ONE) {
293 load = new_rd_ia32_vfld1(dbgi, irg, block);
296 floatent = get_entity_for_tv(env_cg, node);
298 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
299 set_ia32_op_type(load, ia32_AddrModeS);
300 set_ia32_am_flavour(load, ia32_am_N);
301 set_ia32_am_sc(load, floatent);
302 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
303 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
305 set_ia32_ls_mode(load, mode);
307 floatent = get_entity_for_tv(env_cg, node);
309 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
310 set_ia32_op_type(load, ia32_AddrModeS);
311 set_ia32_am_flavour(load, ia32_am_N);
312 set_ia32_am_sc(load, floatent);
313 set_ia32_ls_mode(load, mode);
314 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
316 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
319 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
321 /* Const Nodes before the initial IncSP are a bad idea, because
322 * they could be spilled and we have no SP ready at that point yet.
323 * So add a dependency to the initial frame pointer calculation to
324 * avoid that situation.
326 if (get_irg_start_block(irg) == block) {
327 add_irn_dep(load, get_irg_frame(irg));
330 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
333 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
336 if (get_irg_start_block(irg) == block) {
337 add_irn_dep(cnst, get_irg_frame(irg));
340 set_ia32_Const_attr(cnst, node);
341 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
346 return new_r_Bad(irg);
350 * Transforms a SymConst.
352 static ir_node *gen_SymConst(ir_node *node) {
353 ir_graph *irg = current_ir_graph;
354 ir_node *old_block = get_nodes_block(node);
355 ir_node *block = be_transform_node(old_block);
356 dbg_info *dbgi = get_irn_dbg_info(node);
357 ir_mode *mode = get_irn_mode(node);
360 if (mode_is_float(mode)) {
361 if (USE_SSE2(env_cg))
362 cnst = new_rd_ia32_xConst(dbgi, irg, block);
364 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
365 //set_ia32_ls_mode(cnst, mode);
366 set_ia32_ls_mode(cnst, mode_E);
368 cnst = new_rd_ia32_Const(dbgi, irg, block);
371 /* Const Nodes before the initial IncSP are a bad idea, because
372 * they could be spilled and we have no SP ready at that point yet
374 if (get_irg_start_block(irg) == block) {
375 add_irn_dep(cnst, get_irg_frame(irg));
378 set_ia32_Const_attr(cnst, node);
379 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
384 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
385 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
386 static const struct {
388 const char *ent_name;
389 const char *cnst_str;
390 } names [ia32_known_const_max] = {
391 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
392 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
393 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
394 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
396 static ir_entity *ent_cache[ia32_known_const_max];
398 const char *tp_name, *ent_name, *cnst_str;
406 ent_name = names[kct].ent_name;
407 if (! ent_cache[kct]) {
408 tp_name = names[kct].tp_name;
409 cnst_str = names[kct].cnst_str;
411 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
413 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
414 tp = new_type_primitive(new_id_from_str(tp_name), mode);
415 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
417 set_entity_ld_ident(ent, get_entity_ident(ent));
418 set_entity_visibility(ent, visibility_local);
419 set_entity_variability(ent, variability_constant);
420 set_entity_allocation(ent, allocation_static);
422 /* we create a new entity here: It's initialization must resist on the
424 rem = current_ir_graph;
425 current_ir_graph = get_const_code_irg();
426 cnst = new_Const(mode, tv);
427 current_ir_graph = rem;
429 set_atomic_ent_value(ent, cnst);
431 /* cache the entry */
432 ent_cache[kct] = ent;
435 return ent_cache[kct];
440 * Prints the old node name on cg obst and returns a pointer to it.
442 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
443 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
445 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
446 obstack_1grow(isa->name_obst, 0);
447 return obstack_finish(isa->name_obst);
451 /* determine if one operator is an Imm */
452 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
454 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
456 return is_ia32_Cnst(op2) ? op2 : NULL;
460 /* determine if one operator is not an Imm */
461 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
462 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
465 static void fold_immediate(ir_node *node, int in1, int in2) {
469 if (!(env_cg->opt & IA32_OPT_IMMOPS))
472 left = get_irn_n(node, in1);
473 right = get_irn_n(node, in2);
474 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
475 /* we can only set right operand to immediate */
476 if(!is_ia32_commutative(node))
478 /* exchange left/right */
479 set_irn_n(node, in1, right);
480 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
481 copy_ia32_Immop_attr(node, left);
482 } else if(is_ia32_Cnst(right)) {
483 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
484 copy_ia32_Immop_attr(node, right);
489 clear_ia32_commutative(node);
490 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
491 get_ia32_am_arity(node));
495 * Construct a standard binary operation, set AM and immediate if required.
497 * @param op1 The first operand
498 * @param op2 The second operand
499 * @param func The node constructor function
500 * @return The constructed ia32 node.
502 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
503 construct_binop_func *func, int commutative)
505 ir_node *block = be_transform_node(get_nodes_block(node));
506 ir_graph *irg = current_ir_graph;
507 dbg_info *dbgi = get_irn_dbg_info(node);
508 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
509 ir_node *nomem = new_NoMem();
512 ir_node *new_op1 = be_transform_node(op1);
513 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
514 if (is_ia32_Immediate(new_op2)) {
518 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
519 if (func == new_rd_ia32_IMul) {
520 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
522 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
525 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
527 set_ia32_commutative(new_node);
534 * Construct a standard binary operation, set AM and immediate if required.
536 * @param op1 The first operand
537 * @param op2 The second operand
538 * @param func The node constructor function
539 * @return The constructed ia32 node.
541 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
542 construct_binop_func *func)
544 ir_node *block = be_transform_node(get_nodes_block(node));
545 ir_node *new_op1 = be_transform_node(op1);
546 ir_node *new_op2 = be_transform_node(op2);
547 ir_node *new_node = NULL;
548 dbg_info *dbgi = get_irn_dbg_info(node);
549 ir_graph *irg = current_ir_graph;
550 ir_mode *mode = get_irn_mode(node);
551 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
552 ir_node *nomem = new_NoMem();
554 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
556 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
557 if (is_op_commutative(get_irn_op(node))) {
558 set_ia32_commutative(new_node);
560 set_ia32_ls_mode(new_node, mode);
562 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
567 static ir_node *get_fpcw(void)
570 if(initial_fpcw != NULL)
573 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
574 &ia32_fp_cw_regs[REG_FPCW]);
575 initial_fpcw = be_transform_node(fpcw);
581 * Construct a standard binary operation, set AM and immediate if required.
583 * @param op1 The first operand
584 * @param op2 The second operand
585 * @param func The node constructor function
586 * @return The constructed ia32 node.
588 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
589 construct_binop_float_func *func)
591 ir_node *block = be_transform_node(get_nodes_block(node));
592 ir_node *new_op1 = be_transform_node(op1);
593 ir_node *new_op2 = be_transform_node(op2);
594 ir_node *new_node = NULL;
595 dbg_info *dbgi = get_irn_dbg_info(node);
596 ir_graph *irg = current_ir_graph;
597 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
598 ir_node *nomem = new_NoMem();
600 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
602 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
603 if (is_op_commutative(get_irn_op(node))) {
604 set_ia32_commutative(new_node);
607 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
613 * Construct a shift/rotate binary operation, sets AM and immediate if required.
615 * @param op1 The first operand
616 * @param op2 The second operand
617 * @param func The node constructor function
618 * @return The constructed ia32 node.
620 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
621 construct_binop_func *func)
623 ir_node *block = be_transform_node(get_nodes_block(node));
624 ir_node *new_op1 = be_transform_node(op1);
626 ir_node *new_op = NULL;
627 dbg_info *dbgi = get_irn_dbg_info(node);
628 ir_graph *irg = current_ir_graph;
629 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
630 ir_node *nomem = new_NoMem();
632 assert(! mode_is_float(get_irn_mode(node))
633 && "Shift/Rotate with float not supported");
635 new_op2 = create_immediate_or_transform(op2, 'N');
637 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
640 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
642 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
644 set_ia32_emit_cl(new_op);
651 * Construct a standard unary operation, set AM and immediate if required.
653 * @param op The operand
654 * @param func The node constructor function
655 * @return The constructed ia32 node.
657 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
659 ir_node *block = be_transform_node(get_nodes_block(node));
660 ir_node *new_op = be_transform_node(op);
661 ir_node *new_node = NULL;
662 ir_graph *irg = current_ir_graph;
663 dbg_info *dbgi = get_irn_dbg_info(node);
664 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
665 ir_node *nomem = new_NoMem();
667 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
668 DB((dbg, LEVEL_1, "INT unop ..."));
669 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
671 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
677 * Creates an ia32 Add.
679 * @return the created ia32 Add node
681 static ir_node *gen_Add(ir_node *node) {
682 ir_node *block = be_transform_node(get_nodes_block(node));
683 ir_node *op1 = get_Add_left(node);
684 ir_node *new_op1 = be_transform_node(op1);
685 ir_node *op2 = get_Add_right(node);
686 ir_node *new_op2 = be_transform_node(op2);
687 ir_node *new_op = NULL;
688 ir_graph *irg = current_ir_graph;
689 dbg_info *dbgi = get_irn_dbg_info(node);
690 ir_mode *mode = get_irn_mode(node);
691 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
692 ir_node *nomem = new_NoMem();
693 ir_node *expr_op, *imm_op;
695 /* Check if immediate optimization is on and */
696 /* if it's an operation with immediate. */
697 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
698 expr_op = get_expr_op(new_op1, new_op2);
700 assert((expr_op || imm_op) && "invalid operands");
702 if (mode_is_float(mode)) {
703 if (USE_SSE2(env_cg))
704 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
706 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
711 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
712 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
714 /* No expr_op means, that we have two const - one symconst and */
715 /* one tarval or another symconst - because this case is not */
716 /* covered by constant folding */
717 /* We need to check for: */
718 /* 1) symconst + const -> becomes a LEA */
719 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
720 /* linker doesn't support two symconsts */
722 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
723 /* this is the 2nd case */
724 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
725 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
726 set_ia32_am_flavour(new_op, ia32_am_B);
727 set_ia32_op_type(new_op, ia32_AddrModeS);
729 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
730 } else if (tp1 == ia32_ImmSymConst) {
731 tarval *tv = get_ia32_Immop_tarval(new_op2);
732 long offs = get_tarval_long(tv);
734 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
735 add_irn_dep(new_op, get_irg_frame(irg));
736 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
738 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
739 add_ia32_am_offs_int(new_op, offs);
740 set_ia32_am_flavour(new_op, ia32_am_OB);
741 set_ia32_op_type(new_op, ia32_AddrModeS);
742 } else if (tp2 == ia32_ImmSymConst) {
743 tarval *tv = get_ia32_Immop_tarval(new_op1);
744 long offs = get_tarval_long(tv);
746 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
747 add_irn_dep(new_op, get_irg_frame(irg));
748 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
750 add_ia32_am_offs_int(new_op, offs);
751 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
752 set_ia32_am_flavour(new_op, ia32_am_OB);
753 set_ia32_op_type(new_op, ia32_AddrModeS);
755 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
756 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
757 tarval *restv = tarval_add(tv1, tv2);
759 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
761 new_op = new_rd_ia32_Const(dbgi, irg, block);
762 set_ia32_Const_tarval(new_op, restv);
763 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
766 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
769 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
770 tarval_classification_t class_tv, class_negtv;
771 tarval *tv = get_ia32_Immop_tarval(imm_op);
773 /* optimize tarvals */
774 class_tv = classify_tarval(tv);
775 class_negtv = classify_tarval(tarval_neg(tv));
777 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
778 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
779 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
780 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
782 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
783 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
784 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
785 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
791 /* This is a normal add */
792 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
795 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
796 set_ia32_commutative(new_op);
798 fold_immediate(new_op, 2, 3);
800 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
806 * Creates an ia32 Mul.
808 * @return the created ia32 Mul node
810 static ir_node *gen_Mul(ir_node *node) {
811 ir_node *op1 = get_Mul_left(node);
812 ir_node *op2 = get_Mul_right(node);
813 ir_mode *mode = get_irn_mode(node);
815 if (mode_is_float(mode)) {
816 if (USE_SSE2(env_cg))
817 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
819 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
823 for the lower 32bit of the result it doesn't matter whether we use
824 signed or unsigned multiplication so we use IMul as it has fewer
827 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
831 * Creates an ia32 Mulh.
832 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
833 * this result while Mul returns the lower 32 bit.
835 * @return the created ia32 Mulh node
837 static ir_node *gen_Mulh(ir_node *node) {
838 ir_node *block = be_transform_node(get_nodes_block(node));
839 ir_node *op1 = get_irn_n(node, 0);
840 ir_node *new_op1 = be_transform_node(op1);
841 ir_node *op2 = get_irn_n(node, 1);
842 ir_node *new_op2 = be_transform_node(op2);
843 ir_graph *irg = current_ir_graph;
844 dbg_info *dbgi = get_irn_dbg_info(node);
845 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
846 ir_mode *mode = get_irn_mode(node);
847 ir_node *proj_EDX, *res;
849 assert(!mode_is_float(mode) && "Mulh with float not supported");
850 if (mode_is_signed(mode)) {
851 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
852 new_op2, new_NoMem());
854 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
858 set_ia32_commutative(res);
859 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
861 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
869 * Creates an ia32 And.
871 * @return The created ia32 And node
873 static ir_node *gen_And(ir_node *node) {
874 ir_node *op1 = get_And_left(node);
875 ir_node *op2 = get_And_right(node);
876 assert(! mode_is_float(get_irn_mode(node)));
878 /* check for zero extension first */
880 tarval *tv = get_Const_tarval(op2);
881 long v = get_tarval_long(tv);
883 if (v == 0xFF || v == 0xFFFF) {
884 dbg_info *dbgi = get_irn_dbg_info(node);
885 ir_node *block = be_transform_node(get_nodes_block(node));
886 ir_node *new_op = be_transform_node(op1);
896 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, new_op);
897 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
903 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
909 * Creates an ia32 Or.
911 * @return The created ia32 Or node
913 static ir_node *gen_Or(ir_node *node) {
914 ir_node *op1 = get_Or_left(node);
915 ir_node *op2 = get_Or_right(node);
917 assert (! mode_is_float(get_irn_mode(node)));
918 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
924 * Creates an ia32 Eor.
926 * @return The created ia32 Eor node
928 static ir_node *gen_Eor(ir_node *node) {
929 ir_node *op1 = get_Eor_left(node);
930 ir_node *op2 = get_Eor_right(node);
932 assert(! mode_is_float(get_irn_mode(node)));
933 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
938 * Creates an ia32 Sub.
940 * @return The created ia32 Sub node
942 static ir_node *gen_Sub(ir_node *node) {
943 ir_node *block = be_transform_node(get_nodes_block(node));
944 ir_node *op1 = get_Sub_left(node);
945 ir_node *new_op1 = be_transform_node(op1);
946 ir_node *op2 = get_Sub_right(node);
947 ir_node *new_op2 = be_transform_node(op2);
948 ir_node *new_op = NULL;
949 ir_graph *irg = current_ir_graph;
950 dbg_info *dbgi = get_irn_dbg_info(node);
951 ir_mode *mode = get_irn_mode(node);
952 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
953 ir_node *nomem = new_NoMem();
954 ir_node *expr_op, *imm_op;
956 /* Check if immediate optimization is on and */
957 /* if it's an operation with immediate. */
958 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
959 expr_op = get_expr_op(new_op1, new_op2);
961 assert((expr_op || imm_op) && "invalid operands");
963 if (mode_is_float(mode)) {
964 if (USE_SSE2(env_cg))
965 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
967 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
972 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
973 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
975 /* No expr_op means, that we have two const - one symconst and */
976 /* one tarval or another symconst - because this case is not */
977 /* covered by constant folding */
978 /* We need to check for: */
979 /* 1) symconst - const -> becomes a LEA */
980 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
981 /* linker doesn't support two symconsts */
982 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
983 /* this is the 2nd case */
984 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
985 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
986 set_ia32_am_sc_sign(new_op);
987 set_ia32_am_flavour(new_op, ia32_am_B);
989 DBG_OPT_LEA3(op1, op2, node, new_op);
990 } else if (tp1 == ia32_ImmSymConst) {
991 tarval *tv = get_ia32_Immop_tarval(new_op2);
992 long offs = get_tarval_long(tv);
994 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
995 add_irn_dep(new_op, get_irg_frame(irg));
996 DBG_OPT_LEA3(op1, op2, node, new_op);
998 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
999 add_ia32_am_offs_int(new_op, -offs);
1000 set_ia32_am_flavour(new_op, ia32_am_OB);
1001 set_ia32_op_type(new_op, ia32_AddrModeS);
1002 } else if (tp2 == ia32_ImmSymConst) {
1003 tarval *tv = get_ia32_Immop_tarval(new_op1);
1004 long offs = get_tarval_long(tv);
1006 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1007 add_irn_dep(new_op, get_irg_frame(irg));
1008 DBG_OPT_LEA3(op1, op2, node, new_op);
1010 add_ia32_am_offs_int(new_op, offs);
1011 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1012 set_ia32_am_sc_sign(new_op);
1013 set_ia32_am_flavour(new_op, ia32_am_OB);
1014 set_ia32_op_type(new_op, ia32_AddrModeS);
1016 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1017 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1018 tarval *restv = tarval_sub(tv1, tv2);
1020 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1022 new_op = new_rd_ia32_Const(dbgi, irg, block);
1023 set_ia32_Const_tarval(new_op, restv);
1024 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1027 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1029 } else if (imm_op) {
1030 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1031 tarval_classification_t class_tv, class_negtv;
1032 tarval *tv = get_ia32_Immop_tarval(imm_op);
1034 /* optimize tarvals */
1035 class_tv = classify_tarval(tv);
1036 class_negtv = classify_tarval(tarval_neg(tv));
1038 if (class_tv == TV_CLASSIFY_ONE) {
1039 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1040 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1041 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1043 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1044 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1045 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1046 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1052 /* This is a normal sub */
1053 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1055 /* set AM support */
1056 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1058 fold_immediate(new_op, 2, 3);
1060 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1068 * Generates an ia32 DivMod with additional infrastructure for the
1069 * register allocator if needed.
1071 * @param dividend -no comment- :)
1072 * @param divisor -no comment- :)
1073 * @param dm_flav flavour_Div/Mod/DivMod
1074 * @return The created ia32 DivMod node
1076 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1077 ir_node *divisor, ia32_op_flavour_t dm_flav)
1079 ir_node *block = be_transform_node(get_nodes_block(node));
1080 ir_node *new_dividend = be_transform_node(dividend);
1081 ir_node *new_divisor = be_transform_node(divisor);
1082 ir_graph *irg = current_ir_graph;
1083 dbg_info *dbgi = get_irn_dbg_info(node);
1084 ir_mode *mode = get_irn_mode(node);
1085 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1086 ir_node *res, *proj_div, *proj_mod;
1087 ir_node *sign_extension;
1088 ir_node *mem, *new_mem;
1089 ir_node *projs[pn_DivMod_max];
1092 ia32_collect_Projs(node, projs, pn_DivMod_max);
1094 proj_div = proj_mod = NULL;
1098 mem = get_Div_mem(node);
1099 mode = get_Div_resmode(node);
1100 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1101 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1104 mem = get_Mod_mem(node);
1105 mode = get_Mod_resmode(node);
1106 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1107 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1109 case flavour_DivMod:
1110 mem = get_DivMod_mem(node);
1111 mode = get_DivMod_resmode(node);
1112 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1113 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1114 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1117 panic("invalid divmod flavour!");
1119 new_mem = be_transform_node(mem);
1121 if (mode_is_signed(mode)) {
1122 /* in signed mode, we need to sign extend the dividend */
1123 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1124 add_irn_dep(produceval, get_irg_frame(irg));
1125 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1128 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1129 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1131 add_irn_dep(sign_extension, get_irg_frame(irg));
1134 if (mode_is_signed(mode)) {
1135 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1136 sign_extension, new_divisor, new_mem, dm_flav);
1138 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1139 sign_extension, new_divisor, new_mem, dm_flav);
1142 set_ia32_exc_label(res, has_exc);
1143 set_irn_pinned(res, get_irn_pinned(node));
1144 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1146 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1153 * Wrapper for generate_DivMod. Sets flavour_Mod.
1156 static ir_node *gen_Mod(ir_node *node) {
1157 return generate_DivMod(node, get_Mod_left(node),
1158 get_Mod_right(node), flavour_Mod);
1162 * Wrapper for generate_DivMod. Sets flavour_Div.
1165 static ir_node *gen_Div(ir_node *node) {
1166 return generate_DivMod(node, get_Div_left(node),
1167 get_Div_right(node), flavour_Div);
1171 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1173 static ir_node *gen_DivMod(ir_node *node) {
1174 return generate_DivMod(node, get_DivMod_left(node),
1175 get_DivMod_right(node), flavour_DivMod);
1181 * Creates an ia32 floating Div.
1183 * @return The created ia32 xDiv node
1185 static ir_node *gen_Quot(ir_node *node) {
1186 ir_node *block = be_transform_node(get_nodes_block(node));
1187 ir_node *op1 = get_Quot_left(node);
1188 ir_node *new_op1 = be_transform_node(op1);
1189 ir_node *op2 = get_Quot_right(node);
1190 ir_node *new_op2 = be_transform_node(op2);
1191 ir_graph *irg = current_ir_graph;
1192 dbg_info *dbgi = get_irn_dbg_info(node);
1193 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1194 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1197 if (USE_SSE2(env_cg)) {
1198 ir_mode *mode = get_irn_mode(op1);
1199 if (is_ia32_xConst(new_op2)) {
1200 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1201 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1202 copy_ia32_Immop_attr(new_op, new_op2);
1204 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1205 // Matze: disabled for now, spillslot coalescer fails
1206 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1208 set_ia32_ls_mode(new_op, mode);
1210 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1211 new_op2, nomem, get_fpcw());
1212 // Matze: disabled for now (spillslot coalescer fails)
1213 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1215 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1221 * Creates an ia32 Shl.
1223 * @return The created ia32 Shl node
1225 static ir_node *gen_Shl(ir_node *node) {
1226 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1233 * Creates an ia32 Shr.
1235 * @return The created ia32 Shr node
1237 static ir_node *gen_Shr(ir_node *node) {
1238 return gen_shift_binop(node, get_Shr_left(node),
1239 get_Shr_right(node), new_rd_ia32_Shr);
1245 * Creates an ia32 Sar.
1247 * @return The created ia32 Shrs node
1249 static ir_node *gen_Shrs(ir_node *node) {
1250 ir_node *left = get_Shrs_left(node);
1251 ir_node *right = get_Shrs_right(node);
1252 ir_mode *mode = get_irn_mode(node);
1253 if(is_Const(right) && mode == mode_Is) {
1254 tarval *tv = get_Const_tarval(right);
1255 long val = get_tarval_long(tv);
1257 /* this is a sign extension */
1258 ir_graph *irg = current_ir_graph;
1259 dbg_info *dbgi = get_irn_dbg_info(node);
1260 ir_node *block = be_transform_node(get_nodes_block(node));
1262 ir_node *new_op = be_transform_node(op);
1263 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1264 add_irn_dep(pval, get_irg_frame(irg));
1266 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1270 /* 8 or 16 bit sign extension? */
1271 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1272 ir_node *shl_left = get_Shl_left(left);
1273 ir_node *shl_right = get_Shl_right(left);
1274 if(is_Const(shl_right)) {
1275 tarval *tv1 = get_Const_tarval(right);
1276 tarval *tv2 = get_Const_tarval(shl_right);
1277 if(tv1 == tv2 && tarval_is_long(tv1)) {
1278 long val = get_tarval_long(tv1);
1279 if(val == 16 || val == 24) {
1280 dbg_info *dbgi = get_irn_dbg_info(node);
1281 ir_node *block = be_transform_node(get_nodes_block(node));
1282 ir_node *new_op = be_transform_node(shl_left);
1292 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1294 SET_IA32_ORIG_NODE(res,
1295 ia32_get_old_node_name(env_cg, node));
1304 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1310 * Creates an ia32 RotL.
1312 * @param op1 The first operator
1313 * @param op2 The second operator
1314 * @return The created ia32 RotL node
1316 static ir_node *gen_RotL(ir_node *node,
1317 ir_node *op1, ir_node *op2) {
1318 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1324 * Creates an ia32 RotR.
1325 * NOTE: There is no RotR with immediate because this would always be a RotL
1326 * "imm-mode_size_bits" which can be pre-calculated.
1328 * @param op1 The first operator
1329 * @param op2 The second operator
1330 * @return The created ia32 RotR node
1332 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1334 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1340 * Creates an ia32 RotR or RotL (depending on the found pattern).
1342 * @return The created ia32 RotL or RotR node
1344 static ir_node *gen_Rot(ir_node *node) {
1345 ir_node *rotate = NULL;
1346 ir_node *op1 = get_Rot_left(node);
1347 ir_node *op2 = get_Rot_right(node);
1349 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1350 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1351 that means we can create a RotR instead of an Add and a RotL */
1353 if (get_irn_op(op2) == op_Add) {
1355 ir_node *left = get_Add_left(add);
1356 ir_node *right = get_Add_right(add);
1357 if (is_Const(right)) {
1358 tarval *tv = get_Const_tarval(right);
1359 ir_mode *mode = get_irn_mode(node);
1360 long bits = get_mode_size_bits(mode);
1362 if (get_irn_op(left) == op_Minus &&
1363 tarval_is_long(tv) &&
1364 get_tarval_long(tv) == bits)
1366 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1367 rotate = gen_RotR(node, op1, get_Minus_op(left));
1372 if (rotate == NULL) {
1373 rotate = gen_RotL(node, op1, op2);
1382 * Transforms a Minus node.
1384 * @param op The Minus operand
1385 * @return The created ia32 Minus node
1387 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1388 ir_node *block = be_transform_node(get_nodes_block(node));
1389 ir_graph *irg = current_ir_graph;
1390 dbg_info *dbgi = get_irn_dbg_info(node);
1391 ir_mode *mode = get_irn_mode(node);
1396 if (mode_is_float(mode)) {
1397 ir_node *new_op = be_transform_node(op);
1398 if (USE_SSE2(env_cg)) {
1399 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1400 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1401 ir_node *nomem = new_rd_NoMem(irg);
1403 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1405 size = get_mode_size_bits(mode);
1406 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1408 set_ia32_am_sc(res, ent);
1409 set_ia32_op_type(res, ia32_AddrModeS);
1410 set_ia32_ls_mode(res, mode);
1412 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1415 res = gen_unop(node, op, new_rd_ia32_Neg);
1418 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1424 * Transforms a Minus node.
1426 * @return The created ia32 Minus node
1428 static ir_node *gen_Minus(ir_node *node) {
1429 return gen_Minus_ex(node, get_Minus_op(node));
1432 static ir_node *create_Immediate_from_int(int val)
1434 ir_graph *irg = current_ir_graph;
1435 ir_node *start_block = get_irg_start_block(irg);
1436 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, 0, val);
1437 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
1442 static ir_node *gen_bin_Not(ir_node *node)
1444 ir_graph *irg = current_ir_graph;
1445 dbg_info *dbgi = get_irn_dbg_info(node);
1446 ir_node *block = be_transform_node(get_nodes_block(node));
1447 ir_node *op = get_Not_op(node);
1448 ir_node *new_op = be_transform_node(op);
1449 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1450 ir_node *nomem = new_NoMem();
1451 ir_node *one = create_Immediate_from_int(1);
1453 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1457 * Transforms a Not node.
1459 * @return The created ia32 Not node
1461 static ir_node *gen_Not(ir_node *node) {
1462 ir_node *op = get_Not_op(node);
1463 ir_mode *mode = get_irn_mode(node);
1465 if(mode == mode_b) {
1466 return gen_bin_Not(node);
1469 assert (! mode_is_float(get_irn_mode(node)));
1470 return gen_unop(node, op, new_rd_ia32_Not);
1476 * Transforms an Abs node.
1478 * @return The created ia32 Abs node
1480 static ir_node *gen_Abs(ir_node *node) {
1481 ir_node *block = be_transform_node(get_nodes_block(node));
1482 ir_node *op = get_Abs_op(node);
1483 ir_node *new_op = be_transform_node(op);
1484 ir_graph *irg = current_ir_graph;
1485 dbg_info *dbgi = get_irn_dbg_info(node);
1486 ir_mode *mode = get_irn_mode(node);
1487 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1488 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1489 ir_node *nomem = new_NoMem();
1494 if (mode_is_float(mode)) {
1495 if (USE_SSE2(env_cg)) {
1496 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1498 size = get_mode_size_bits(mode);
1499 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1501 set_ia32_am_sc(res, ent);
1503 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1505 set_ia32_op_type(res, ia32_AddrModeS);
1506 set_ia32_ls_mode(res, mode);
1509 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1510 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1514 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1515 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1518 add_irn_dep(pval, get_irg_frame(irg));
1519 SET_IA32_ORIG_NODE(sign_extension,
1520 ia32_get_old_node_name(env_cg, node));
1522 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1523 sign_extension, nomem);
1524 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1526 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1527 sign_extension, nomem);
1528 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1537 * Transforms a Load.
1539 * @return the created ia32 Load node
1541 static ir_node *gen_Load(ir_node *node) {
1542 ir_node *old_block = get_nodes_block(node);
1543 ir_node *block = be_transform_node(old_block);
1544 ir_node *ptr = get_Load_ptr(node);
1545 ir_node *new_ptr = be_transform_node(ptr);
1546 ir_node *mem = get_Load_mem(node);
1547 ir_node *new_mem = be_transform_node(mem);
1548 ir_graph *irg = current_ir_graph;
1549 dbg_info *dbgi = get_irn_dbg_info(node);
1550 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1551 ir_mode *mode = get_Load_mode(node);
1553 ir_node *lptr = new_ptr;
1556 ia32_am_flavour_t am_flav = ia32_am_B;
1558 /* address might be a constant (symconst or absolute address) */
1559 if (is_ia32_Const(new_ptr)) {
1564 if (mode_is_float(mode)) {
1565 if (USE_SSE2(env_cg)) {
1566 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1567 res_mode = mode_xmm;
1569 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1570 res_mode = mode_vfp;
1576 /* create a conv node with address mode for smaller modes */
1577 if(get_mode_size_bits(mode) < 32) {
1578 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, lptr, noreg, noreg,
1581 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1586 /* base is a constant address */
1588 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1589 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1590 am_flav = ia32_am_N;
1592 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1593 long offs = get_tarval_long(tv);
1595 add_ia32_am_offs_int(new_op, offs);
1596 am_flav = ia32_am_O;
1600 set_irn_pinned(new_op, get_irn_pinned(node));
1601 set_ia32_op_type(new_op, ia32_AddrModeS);
1602 set_ia32_am_flavour(new_op, am_flav);
1603 set_ia32_ls_mode(new_op, mode);
1605 /* make sure we are scheduled behind the initial IncSP/Barrier
1606 * to avoid spills being placed before it
1608 if (block == get_irg_start_block(irg)) {
1609 add_irn_dep(new_op, get_irg_frame(irg));
1612 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1613 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1621 * Transforms a Store.
1623 * @return the created ia32 Store node
1625 static ir_node *gen_Store(ir_node *node) {
1626 ir_node *block = be_transform_node(get_nodes_block(node));
1627 ir_node *ptr = get_Store_ptr(node);
1628 ir_node *new_ptr = be_transform_node(ptr);
1629 ir_node *val = get_Store_value(node);
1631 ir_node *mem = get_Store_mem(node);
1632 ir_node *new_mem = be_transform_node(mem);
1633 ir_graph *irg = current_ir_graph;
1634 dbg_info *dbgi = get_irn_dbg_info(node);
1635 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1636 ir_node *sptr = new_ptr;
1637 ir_mode *mode = get_irn_mode(val);
1640 ia32_am_flavour_t am_flav = ia32_am_B;
1642 /* address might be a constant (symconst or absolute address) */
1643 if (is_ia32_Const(new_ptr)) {
1648 if (mode_is_float(mode)) {
1649 new_val = be_transform_node(val);
1650 if (USE_SSE2(env_cg)) {
1651 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1654 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1658 new_val = create_immediate_or_transform(val, 0);
1662 if (get_mode_size_bits(mode) == 8) {
1663 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1666 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1671 /* base is an constant address */
1673 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1674 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1675 am_flav = ia32_am_N;
1677 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1678 long offs = get_tarval_long(tv);
1680 add_ia32_am_offs_int(new_op, offs);
1681 am_flav = ia32_am_O;
1685 set_irn_pinned(new_op, get_irn_pinned(node));
1686 set_ia32_op_type(new_op, ia32_AddrModeD);
1687 set_ia32_am_flavour(new_op, am_flav);
1688 set_ia32_ls_mode(new_op, mode);
1690 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1691 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1696 static ir_node *maybe_scale_up(ir_node *new_op, ir_mode *mode, dbg_info *dbgi)
1701 if(get_mode_size_bits(mode) == 32)
1705 if(is_ia32_Immediate(new_op))
1708 if(mode_is_signed(mode))
1713 block = get_nodes_block(new_op);
1714 return create_I2I_Conv(mode, tgt_mode, dbgi, block, new_op);
1717 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1718 ir_node *cmp_left, ir_node *cmp_right)
1720 ir_node *new_cmp_left;
1721 ir_node *new_cmp_right;
1728 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1730 if(cmp_right != NULL && !is_Const_0(cmp_right))
1733 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1734 and_left = get_And_left(cmp_left);
1735 and_right = get_And_right(cmp_left);
1737 mode = get_irn_mode(and_left);
1738 new_cmp_left = be_transform_node(and_left);
1739 new_cmp_right = create_immediate_or_transform(and_right, 0);
1741 mode = get_irn_mode(cmp_left);
1742 new_cmp_left = be_transform_node(cmp_left);
1743 new_cmp_right = be_transform_node(cmp_left);
1746 assert(get_mode_size_bits(mode) <= 32);
1747 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1748 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1749 noreg = ia32_new_NoReg_gp(env_cg);
1750 nomem = new_NoMem();
1752 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1753 new_cmp_left, new_cmp_right, nomem, pnc);
1754 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1759 static ir_node *create_Switch(ir_node *node)
1761 ir_graph *irg = current_ir_graph;
1762 dbg_info *dbgi = get_irn_dbg_info(node);
1763 ir_node *block = be_transform_node(get_nodes_block(node));
1764 ir_node *sel = get_Cond_selector(node);
1765 ir_node *new_sel = be_transform_node(sel);
1767 int switch_min = INT_MAX;
1768 const ir_edge_t *edge;
1770 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1772 /* determine the smallest switch case value */
1773 foreach_out_edge(node, edge) {
1774 ir_node *proj = get_edge_src_irn(edge);
1775 int pn = get_Proj_proj(proj);
1780 if (switch_min != 0) {
1781 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1783 /* if smallest switch case is not 0 we need an additional sub */
1784 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1785 add_ia32_am_offs_int(new_sel, -switch_min);
1786 set_ia32_am_flavour(new_sel, ia32_am_OB);
1787 set_ia32_op_type(new_sel, ia32_AddrModeS);
1789 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1792 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1793 set_ia32_pncode(res, get_Cond_defaultProj(node));
1795 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1801 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1803 * @return The transformed node.
1805 static ir_node *gen_Cond(ir_node *node) {
1806 ir_node *block = be_transform_node(get_nodes_block(node));
1807 ir_graph *irg = current_ir_graph;
1808 dbg_info *dbgi = get_irn_dbg_info(node);
1809 ir_node *sel = get_Cond_selector(node);
1810 ir_mode *sel_mode = get_irn_mode(sel);
1811 ir_node *res = NULL;
1812 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1819 ir_node *nomem = new_NoMem();
1822 if (sel_mode != mode_b) {
1823 return create_Switch(node);
1826 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
1827 /* it's some mode_b value but not a direct comparison -> create a
1829 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
1830 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1834 cmp = get_Proj_pred(sel);
1835 cmp_a = get_Cmp_left(cmp);
1836 cmp_b = get_Cmp_right(cmp);
1837 cmp_mode = get_irn_mode(cmp_a);
1838 pnc = get_Proj_proj(sel);
1839 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1840 pnc |= ia32_pn_Cmp_Unsigned;
1843 if(mode_needs_gp_reg(cmp_mode)) {
1844 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b);
1846 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1851 new_cmp_a = be_transform_node(cmp_a);
1852 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1854 if (mode_is_float(cmp_mode)) {
1855 if (USE_SSE2(env_cg)) {
1856 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1858 set_ia32_commutative(res);
1859 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1860 set_ia32_ls_mode(res, cmp_mode);
1862 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1863 set_ia32_commutative(res);
1866 /** workaround smaller compare modes with converts...
1867 * We could easily support 16bit compares, for 8 bit we have to set
1868 * additional register constraints, which we don't do yet
1870 new_cmp_a = maybe_scale_up(new_cmp_a, cmp_mode, dbgi);
1871 new_cmp_b = maybe_scale_up(new_cmp_b, cmp_mode, dbgi);
1873 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1874 new_cmp_a, new_cmp_b, nomem, pnc);
1875 set_ia32_commutative(res);
1876 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1879 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1887 * Transforms a CopyB node.
1889 * @return The transformed node.
1891 static ir_node *gen_CopyB(ir_node *node) {
1892 ir_node *block = be_transform_node(get_nodes_block(node));
1893 ir_node *src = get_CopyB_src(node);
1894 ir_node *new_src = be_transform_node(src);
1895 ir_node *dst = get_CopyB_dst(node);
1896 ir_node *new_dst = be_transform_node(dst);
1897 ir_node *mem = get_CopyB_mem(node);
1898 ir_node *new_mem = be_transform_node(mem);
1899 ir_node *res = NULL;
1900 ir_graph *irg = current_ir_graph;
1901 dbg_info *dbgi = get_irn_dbg_info(node);
1902 int size = get_type_size_bytes(get_CopyB_type(node));
1905 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1906 /* then we need the size explicitly in ECX. */
1907 if (size >= 32 * 4) {
1908 rem = size & 0x3; /* size % 4 */
1911 res = new_rd_ia32_Const(dbgi, irg, block);
1912 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1913 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1915 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1916 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1918 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1919 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1922 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1928 ir_node *gen_be_Copy(ir_node *node)
1930 ir_node *result = be_duplicate_node(node);
1931 ir_mode *mode = get_irn_mode(result);
1933 if (mode_needs_gp_reg(mode)) {
1934 set_irn_mode(result, mode_Iu);
1941 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1942 dbg_info *dbgi, ir_node *block)
1944 ir_graph *irg = current_ir_graph;
1945 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1946 ir_node *nomem = new_rd_NoMem(irg);
1948 ir_node *new_cmp_left;
1949 ir_node *new_cmp_right;
1952 /* can we use a test instruction? */
1953 if(cmp_right == NULL || is_Const_0(cmp_right)) {
1954 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1955 if(is_And(cmp_left) &&
1956 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1957 ir_node *and_left = get_And_left(cmp_left);
1958 ir_node *and_right = get_And_right(cmp_left);
1960 mode = get_irn_mode(and_left);
1961 new_cmp_left = be_transform_node(and_left);
1962 new_cmp_right = create_immediate_or_transform(and_right, 0);
1964 mode = get_irn_mode(cmp_left);
1965 new_cmp_left = be_transform_node(cmp_left);
1966 new_cmp_right = be_transform_node(cmp_left);
1969 assert(get_mode_size_bits(mode) <= 32);
1970 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1971 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1973 res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
1974 new_cmp_left, new_cmp_right, nomem, pnc);
1975 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1980 mode = get_irn_mode(cmp_left);
1982 new_cmp_left = be_transform_node(cmp_left);
1983 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1985 assert(get_mode_size_bits(mode) <= 32);
1986 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1987 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1989 res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
1990 new_cmp_left, new_cmp_right, nomem, pnc);
1995 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1996 ir_node *val_true, ir_node *val_false,
1997 dbg_info *dbgi, ir_node *block)
1999 ir_graph *irg = current_ir_graph;
2000 ir_node *new_val_true = be_transform_node(val_true);
2001 ir_node *new_val_false = be_transform_node(val_false);
2002 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2003 ir_node *nomem = new_NoMem();
2004 ir_node *new_cmp_left;
2005 ir_node *new_cmp_right;
2008 /* cmovs with unknowns are pointless... */
2009 if(is_Unknown(val_true)) {
2010 #ifdef DEBUG_libfirm
2011 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2013 return new_val_false;
2015 if(is_Unknown(val_false)) {
2016 #ifdef DEBUG_libfirm
2017 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2019 return new_val_true;
2022 /* can we use a test instruction? */
2023 if(is_Const_0(cmp_right)) {
2024 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2025 if(is_And(cmp_left) &&
2026 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2027 ir_node *and_left = get_And_left(cmp_left);
2028 ir_node *and_right = get_And_right(cmp_left);
2030 new_cmp_left = be_transform_node(and_left);
2031 new_cmp_right = create_immediate_or_transform(and_right, 0);
2033 new_cmp_left = be_transform_node(cmp_left);
2034 new_cmp_right = be_transform_node(cmp_left);
2037 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, block, noreg, noreg,
2038 new_cmp_left, new_cmp_right, nomem,
2039 new_val_true, new_val_false, pnc);
2040 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
2045 new_cmp_left = be_transform_node(cmp_left);
2046 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
2048 res = new_rd_ia32_CmpCMov(dbgi, irg, block, noreg, noreg, new_cmp_left,
2049 new_cmp_right, nomem, new_val_true, new_val_false,
2051 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
2058 * Transforms a Psi node into CMov.
2060 * @return The transformed node.
2062 static ir_node *gen_Psi(ir_node *node) {
2063 ir_node *psi_true = get_Psi_val(node, 0);
2064 ir_node *psi_default = get_Psi_default(node);
2065 ia32_code_gen_t *cg = env_cg;
2066 ir_node *cond = get_Psi_cond(node, 0);
2067 ir_node *block = be_transform_node(get_nodes_block(node));
2068 dbg_info *dbgi = get_irn_dbg_info(node);
2075 assert(get_Psi_n_conds(node) == 1);
2076 assert(get_irn_mode(cond) == mode_b);
2077 assert(mode_needs_gp_reg(get_irn_mode(node)));
2079 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
2080 /* a mode_b value, we have to compare it against 0 */
2082 cmp_right = new_Const_long(mode_Iu, 0);
2086 ir_node *cmp = get_Proj_pred(cond);
2088 cmp_left = get_Cmp_left(cmp);
2089 cmp_right = get_Cmp_right(cmp);
2090 cmp_mode = get_irn_mode(cmp_left);
2091 pnc = get_Proj_proj(cond);
2093 assert(!mode_is_float(cmp_mode));
2095 if (!mode_is_signed(cmp_mode)) {
2096 pnc |= ia32_pn_Cmp_Unsigned;
2100 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2101 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2102 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2103 pnc = get_negated_pnc(pnc, cmp_mode);
2104 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2106 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
2109 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2115 * Following conversion rules apply:
2119 * 1) n bit -> m bit n > m (downscale)
2121 * 2) n bit -> m bit n == m (sign change)
2123 * 3) n bit -> m bit n < m (upscale)
2124 * a) source is signed: movsx
2125 * b) source is unsigned: and with lower bits sets
2129 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2133 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2137 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2138 * x87 is mode_E internally, conversions happen only at load and store
2139 * in non-strict semantic
2143 * Create a conversion from x87 state register to general purpose.
2145 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2146 ir_node *block = be_transform_node(get_nodes_block(node));
2147 ir_node *op = get_Conv_op(node);
2148 ir_node *new_op = be_transform_node(op);
2149 ia32_code_gen_t *cg = env_cg;
2150 ir_graph *irg = current_ir_graph;
2151 dbg_info *dbgi = get_irn_dbg_info(node);
2152 ir_node *noreg = ia32_new_NoReg_gp(cg);
2153 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2154 ir_mode *mode = get_irn_mode(node);
2155 ir_node *fist, *load;
2158 fist = new_rd_ia32_vfist(dbgi, irg, block,
2159 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2161 set_irn_pinned(fist, op_pin_state_floats);
2162 set_ia32_use_frame(fist);
2163 set_ia32_op_type(fist, ia32_AddrModeD);
2164 set_ia32_am_flavour(fist, ia32_am_B);
2166 assert(get_mode_size_bits(mode) <= 32);
2167 /* exception we can only store signed 32 bit integers, so for unsigned
2168 we store a 64bit (signed) integer and load the lower bits */
2169 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2170 set_ia32_ls_mode(fist, mode_Ls);
2172 set_ia32_ls_mode(fist, mode_Is);
2174 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2177 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2179 set_irn_pinned(load, op_pin_state_floats);
2180 set_ia32_use_frame(load);
2181 set_ia32_op_type(load, ia32_AddrModeS);
2182 set_ia32_am_flavour(load, ia32_am_B);
2183 set_ia32_ls_mode(load, mode_Is);
2184 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2186 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2189 static ir_node *create_strict_conv(ir_mode *tgt_mode, ir_node *node)
2191 ir_node *block = get_nodes_block(node);
2192 ir_graph *irg = current_ir_graph;
2193 dbg_info *dbgi = get_irn_dbg_info(node);
2194 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2195 ir_node *nomem = new_NoMem();
2196 ir_node *frame = get_irg_frame(irg);
2197 ir_node *store, *load;
2200 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2202 set_ia32_use_frame(store);
2203 set_ia32_op_type(store, ia32_AddrModeD);
2204 set_ia32_am_flavour(store, ia32_am_OB);
2205 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2207 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2209 set_ia32_use_frame(load);
2210 set_ia32_op_type(load, ia32_AddrModeS);
2211 set_ia32_am_flavour(load, ia32_am_OB);
2212 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2214 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2219 * Create a conversion from general purpose to x87 register
2221 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2222 ir_node *block = be_transform_node(get_nodes_block(node));
2223 ir_node *op = get_Conv_op(node);
2224 ir_node *new_op = be_transform_node(op);
2225 ir_graph *irg = current_ir_graph;
2226 dbg_info *dbgi = get_irn_dbg_info(node);
2227 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2228 ir_node *nomem = new_NoMem();
2229 ir_mode *mode = get_irn_mode(op);
2230 ir_mode *store_mode;
2231 ir_node *fild, *store;
2235 /* first convert to 32 bit signed if necessary */
2236 src_bits = get_mode_size_bits(src_mode);
2237 if (src_bits == 8) {
2238 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem,
2240 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2241 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2243 } else if (src_bits < 32) {
2244 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem, src_mode);
2245 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2246 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2250 assert(get_mode_size_bits(mode) == 32);
2253 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2255 set_ia32_use_frame(store);
2256 set_ia32_op_type(store, ia32_AddrModeD);
2257 set_ia32_am_flavour(store, ia32_am_OB);
2258 set_ia32_ls_mode(store, mode_Iu);
2260 /* exception for 32bit unsigned, do a 64bit spill+load */
2261 if(!mode_is_signed(mode)) {
2264 ir_node *zero_const = create_Immediate_from_int(0);
2266 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg,
2269 set_ia32_use_frame(zero_store);
2270 set_ia32_op_type(zero_store, ia32_AddrModeD);
2271 add_ia32_am_offs_int(zero_store, 4);
2272 set_ia32_ls_mode(zero_store, mode_Iu);
2277 store = new_rd_Sync(dbgi, irg, block, 2, in);
2278 store_mode = mode_Ls;
2280 store_mode = mode_Is;
2284 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2286 set_ia32_use_frame(fild);
2287 set_ia32_op_type(fild, ia32_AddrModeS);
2288 set_ia32_am_flavour(fild, ia32_am_OB);
2289 set_ia32_ls_mode(fild, store_mode);
2291 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2297 * Crete a conversion from one integer mode into another one
2299 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2300 dbg_info *dbgi, ir_node *new_block,
2303 ir_graph *irg = current_ir_graph;
2304 int src_bits = get_mode_size_bits(src_mode);
2305 int tgt_bits = get_mode_size_bits(tgt_mode);
2306 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2307 ir_node *nomem = new_rd_NoMem(irg);
2309 ir_mode *smaller_mode;
2312 if (src_bits < tgt_bits) {
2313 smaller_mode = src_mode;
2314 smaller_bits = src_bits;
2316 smaller_mode = tgt_mode;
2317 smaller_bits = tgt_bits;
2320 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2321 if (smaller_bits == 8) {
2322 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2323 new_op, nomem, smaller_mode);
2325 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, noreg, noreg, new_op,
2326 nomem, smaller_mode);
2328 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2334 * Transforms a Conv node.
2336 * @return The created ia32 Conv node
2338 static ir_node *gen_Conv(ir_node *node) {
2339 ir_node *block = be_transform_node(get_nodes_block(node));
2340 ir_node *op = get_Conv_op(node);
2341 ir_node *new_op = be_transform_node(op);
2342 ir_graph *irg = current_ir_graph;
2343 dbg_info *dbgi = get_irn_dbg_info(node);
2344 ir_mode *src_mode = get_irn_mode(op);
2345 ir_mode *tgt_mode = get_irn_mode(node);
2346 int src_bits = get_mode_size_bits(src_mode);
2347 int tgt_bits = get_mode_size_bits(tgt_mode);
2348 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2349 ir_node *nomem = new_rd_NoMem(irg);
2352 if (src_mode == mode_b) {
2353 assert(mode_is_int(tgt_mode));
2354 /* nothing to do, we already model bools as 0/1 ints */
2358 if (src_mode == tgt_mode) {
2359 if (get_Conv_strict(node)) {
2360 if (USE_SSE2(env_cg)) {
2361 /* when we are in SSE mode, we can kill all strict no-op conversion */
2365 /* this should be optimized already, but who knows... */
2366 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2367 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2372 if (mode_is_float(src_mode)) {
2373 /* we convert from float ... */
2374 if (mode_is_float(tgt_mode)) {
2375 if(src_mode == mode_E && tgt_mode == mode_D
2376 && !get_Conv_strict(node)) {
2377 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2382 if (USE_SSE2(env_cg)) {
2383 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2384 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2385 set_ia32_ls_mode(res, tgt_mode);
2387 if(get_Conv_strict(node)) {
2388 res = create_strict_conv(tgt_mode, new_op);
2389 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2392 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2397 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2398 if (USE_SSE2(env_cg)) {
2399 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2400 set_ia32_ls_mode(res, src_mode);
2402 return gen_x87_fp_to_gp(node);
2406 /* we convert from int ... */
2407 if (mode_is_float(tgt_mode)) {
2409 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2410 if (USE_SSE2(env_cg)) {
2411 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2412 set_ia32_ls_mode(res, tgt_mode);
2413 if(src_bits == 32) {
2414 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2417 res = gen_x87_gp_to_fp(node, src_mode);
2418 if(get_Conv_strict(node)) {
2419 res = create_strict_conv(tgt_mode, res);
2420 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2421 ia32_get_old_node_name(env_cg, node));
2425 } else if(tgt_mode == mode_b) {
2426 /* mode_b lowering already took care that we only have 0/1 values */
2427 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2428 src_mode, tgt_mode));
2432 if (src_bits == tgt_bits) {
2433 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2434 src_mode, tgt_mode));
2438 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, new_op);
2442 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2448 int check_immediate_constraint(long val, char immediate_constraint_type)
2450 switch (immediate_constraint_type) {
2454 return val >= 0 && val <= 32;
2456 return val >= 0 && val <= 63;
2458 return val >= -128 && val <= 127;
2460 return val == 0xff || val == 0xffff;
2462 return val >= 0 && val <= 3;
2464 return val >= 0 && val <= 255;
2466 return val >= 0 && val <= 127;
2470 panic("Invalid immediate constraint found");
2475 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2478 tarval *offset = NULL;
2479 int offset_sign = 0;
2481 ir_entity *symconst_ent = NULL;
2482 int symconst_sign = 0;
2484 ir_node *cnst = NULL;
2485 ir_node *symconst = NULL;
2491 mode = get_irn_mode(node);
2492 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2496 if(is_Minus(node)) {
2498 node = get_Minus_op(node);
2501 if(is_Const(node)) {
2504 offset_sign = minus;
2505 } else if(is_SymConst(node)) {
2508 symconst_sign = minus;
2509 } else if(is_Add(node)) {
2510 ir_node *left = get_Add_left(node);
2511 ir_node *right = get_Add_right(node);
2512 if(is_Const(left) && is_SymConst(right)) {
2515 symconst_sign = minus;
2516 offset_sign = minus;
2517 } else if(is_SymConst(left) && is_Const(right)) {
2520 symconst_sign = minus;
2521 offset_sign = minus;
2523 } else if(is_Sub(node)) {
2524 ir_node *left = get_Sub_left(node);
2525 ir_node *right = get_Sub_right(node);
2526 if(is_Const(left) && is_SymConst(right)) {
2529 symconst_sign = !minus;
2530 offset_sign = minus;
2531 } else if(is_SymConst(left) && is_Const(right)) {
2534 symconst_sign = minus;
2535 offset_sign = !minus;
2542 offset = get_Const_tarval(cnst);
2543 if(tarval_is_long(offset)) {
2544 val = get_tarval_long(offset);
2545 } else if(tarval_is_null(offset)) {
2548 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2553 if(!check_immediate_constraint(val, immediate_constraint_type))
2556 if(symconst != NULL) {
2557 if(immediate_constraint_type != 0) {
2558 /* we need full 32bits for symconsts */
2562 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2564 symconst_ent = get_SymConst_entity(symconst);
2566 if(cnst == NULL && symconst == NULL)
2569 if(offset_sign && offset != NULL) {
2570 offset = tarval_neg(offset);
2573 irg = current_ir_graph;
2574 dbgi = get_irn_dbg_info(node);
2575 block = get_irg_start_block(irg);
2576 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2577 symconst_sign, val);
2578 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2584 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2586 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2587 if (new_node == NULL) {
2588 new_node = be_transform_node(node);
2593 typedef struct constraint_t constraint_t;
2594 struct constraint_t {
2597 const arch_register_req_t **out_reqs;
2599 const arch_register_req_t *req;
2600 unsigned immediate_possible;
2601 char immediate_type;
2604 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2606 int immediate_possible = 0;
2607 char immediate_type = 0;
2608 unsigned limited = 0;
2609 const arch_register_class_t *cls = NULL;
2611 struct obstack *obst;
2612 arch_register_req_t *req;
2613 unsigned *limited_ptr;
2617 /* TODO: replace all the asserts with nice error messages */
2619 printf("Constraint: %s\n", c);
2629 assert(cls == NULL ||
2630 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2631 cls = &ia32_reg_classes[CLASS_ia32_gp];
2632 limited |= 1 << REG_EAX;
2635 assert(cls == NULL ||
2636 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2637 cls = &ia32_reg_classes[CLASS_ia32_gp];
2638 limited |= 1 << REG_EBX;
2641 assert(cls == NULL ||
2642 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2643 cls = &ia32_reg_classes[CLASS_ia32_gp];
2644 limited |= 1 << REG_ECX;
2647 assert(cls == NULL ||
2648 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2649 cls = &ia32_reg_classes[CLASS_ia32_gp];
2650 limited |= 1 << REG_EDX;
2653 assert(cls == NULL ||
2654 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2655 cls = &ia32_reg_classes[CLASS_ia32_gp];
2656 limited |= 1 << REG_EDI;
2659 assert(cls == NULL ||
2660 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2661 cls = &ia32_reg_classes[CLASS_ia32_gp];
2662 limited |= 1 << REG_ESI;
2665 case 'q': /* q means lower part of the regs only, this makes no
2666 * difference to Q for us (we only assigne whole registers) */
2667 assert(cls == NULL ||
2668 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2669 cls = &ia32_reg_classes[CLASS_ia32_gp];
2670 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2674 assert(cls == NULL ||
2675 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2676 cls = &ia32_reg_classes[CLASS_ia32_gp];
2677 limited |= 1 << REG_EAX | 1 << REG_EDX;
2680 assert(cls == NULL ||
2681 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2682 cls = &ia32_reg_classes[CLASS_ia32_gp];
2683 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2684 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2691 assert(cls == NULL);
2692 cls = &ia32_reg_classes[CLASS_ia32_gp];
2698 /* TODO: mark values so the x87 simulator knows about t and u */
2699 assert(cls == NULL);
2700 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2705 assert(cls == NULL);
2706 /* TODO: check that sse2 is supported */
2707 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2717 assert(!immediate_possible);
2718 immediate_possible = 1;
2719 immediate_type = *c;
2723 assert(!immediate_possible);
2724 immediate_possible = 1;
2728 assert(!immediate_possible && cls == NULL);
2729 immediate_possible = 1;
2730 cls = &ia32_reg_classes[CLASS_ia32_gp];
2743 assert(constraint->is_in && "can only specify same constraint "
2746 sscanf(c, "%d%n", &same_as, &p);
2753 case 'E': /* no float consts yet */
2754 case 'F': /* no float consts yet */
2755 case 's': /* makes no sense on x86 */
2756 case 'X': /* we can't support that in firm */
2760 case '<': /* no autodecrement on x86 */
2761 case '>': /* no autoincrement on x86 */
2762 case 'C': /* sse constant not supported yet */
2763 case 'G': /* 80387 constant not supported yet */
2764 case 'y': /* we don't support mmx registers yet */
2765 case 'Z': /* not available in 32 bit mode */
2766 case 'e': /* not available in 32 bit mode */
2767 assert(0 && "asm constraint not supported");
2770 assert(0 && "unknown asm constraint found");
2777 const arch_register_req_t *other_constr;
2779 assert(cls == NULL && "same as and register constraint not supported");
2780 assert(!immediate_possible && "same as and immediate constraint not "
2782 assert(same_as < constraint->n_outs && "wrong constraint number in "
2783 "same_as constraint");
2785 other_constr = constraint->out_reqs[same_as];
2787 req = obstack_alloc(obst, sizeof(req[0]));
2788 req->cls = other_constr->cls;
2789 req->type = arch_register_req_type_should_be_same;
2790 req->limited = NULL;
2791 req->other_same = pos;
2792 req->other_different = -1;
2794 /* switch constraints. This is because in firm we have same_as
2795 * constraints on the output constraints while in the gcc asm syntax
2796 * they are specified on the input constraints */
2797 constraint->req = other_constr;
2798 constraint->out_reqs[same_as] = req;
2799 constraint->immediate_possible = 0;
2803 if(immediate_possible && cls == NULL) {
2804 cls = &ia32_reg_classes[CLASS_ia32_gp];
2806 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2807 assert(cls != NULL);
2809 if(immediate_possible) {
2810 assert(constraint->is_in
2811 && "imeediates make no sense for output constraints");
2813 /* todo: check types (no float input on 'r' constrainted in and such... */
2815 irg = current_ir_graph;
2816 obst = get_irg_obstack(irg);
2819 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2820 limited_ptr = (unsigned*) (req+1);
2822 req = obstack_alloc(obst, sizeof(req[0]));
2824 memset(req, 0, sizeof(req[0]));
2827 req->type = arch_register_req_type_limited;
2828 *limited_ptr = limited;
2829 req->limited = limited_ptr;
2831 req->type = arch_register_req_type_normal;
2835 constraint->req = req;
2836 constraint->immediate_possible = immediate_possible;
2837 constraint->immediate_type = immediate_type;
2841 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2848 panic("Clobbers not supported yet");
2851 ir_node *gen_ASM(ir_node *node)
2854 ir_graph *irg = current_ir_graph;
2855 ir_node *block = be_transform_node(get_nodes_block(node));
2856 dbg_info *dbgi = get_irn_dbg_info(node);
2863 ia32_asm_attr_t *attr;
2864 const arch_register_req_t **out_reqs;
2865 const arch_register_req_t **in_reqs;
2866 struct obstack *obst;
2867 constraint_t parsed_constraint;
2869 /* transform inputs */
2870 arity = get_irn_arity(node);
2871 in = alloca(arity * sizeof(in[0]));
2872 memset(in, 0, arity * sizeof(in[0]));
2874 n_outs = get_ASM_n_output_constraints(node);
2875 n_clobbers = get_ASM_n_clobbers(node);
2876 out_arity = n_outs + n_clobbers;
2878 /* construct register constraints */
2879 obst = get_irg_obstack(irg);
2880 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2881 parsed_constraint.out_reqs = out_reqs;
2882 parsed_constraint.n_outs = n_outs;
2883 parsed_constraint.is_in = 0;
2884 for(i = 0; i < out_arity; ++i) {
2888 const ir_asm_constraint *constraint;
2889 constraint = & get_ASM_output_constraints(node) [i];
2890 c = get_id_str(constraint->constraint);
2891 parse_asm_constraint(i, &parsed_constraint, c);
2893 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2894 c = get_id_str(glob_id);
2895 parse_clobber(node, i, &parsed_constraint, c);
2897 out_reqs[i] = parsed_constraint.req;
2900 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2901 parsed_constraint.is_in = 1;
2902 for(i = 0; i < arity; ++i) {
2903 const ir_asm_constraint *constraint;
2907 constraint = & get_ASM_input_constraints(node) [i];
2908 constr_id = constraint->constraint;
2909 c = get_id_str(constr_id);
2910 parse_asm_constraint(i, &parsed_constraint, c);
2911 in_reqs[i] = parsed_constraint.req;
2913 if(parsed_constraint.immediate_possible) {
2914 ir_node *pred = get_irn_n(node, i);
2915 char imm_type = parsed_constraint.immediate_type;
2916 ir_node *immediate = try_create_Immediate(pred, imm_type);
2918 if(immediate != NULL) {
2924 /* transform inputs */
2925 for(i = 0; i < arity; ++i) {
2927 ir_node *transformed;
2932 pred = get_irn_n(node, i);
2933 transformed = be_transform_node(pred);
2934 in[i] = transformed;
2937 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2939 generic_attr = get_irn_generic_attr(res);
2940 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2941 attr->asm_text = get_ASM_text(node);
2942 set_ia32_out_req_all(res, out_reqs);
2943 set_ia32_in_req_all(res, in_reqs);
2945 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2950 /********************************************
2953 * | |__ ___ _ __ ___ __| | ___ ___
2954 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2955 * | |_) | __/ | | | (_) | (_| | __/\__ \
2956 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2958 ********************************************/
2960 static ir_node *gen_be_StackParam(ir_node *node) {
2961 ir_node *block = be_transform_node(get_nodes_block(node));
2962 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2963 ir_node *new_ptr = be_transform_node(ptr);
2964 ir_node *new_op = NULL;
2965 ir_graph *irg = current_ir_graph;
2966 dbg_info *dbgi = get_irn_dbg_info(node);
2967 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2968 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2969 ir_mode *load_mode = get_irn_mode(node);
2970 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2974 if (mode_is_float(load_mode)) {
2975 if (USE_SSE2(env_cg)) {
2976 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2977 pn_res = pn_ia32_xLoad_res;
2978 proj_mode = mode_xmm;
2980 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2981 pn_res = pn_ia32_vfld_res;
2982 proj_mode = mode_vfp;
2985 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2986 proj_mode = mode_Iu;
2987 pn_res = pn_ia32_Load_res;
2990 set_irn_pinned(new_op, op_pin_state_floats);
2991 set_ia32_frame_ent(new_op, ent);
2992 set_ia32_use_frame(new_op);
2994 set_ia32_op_type(new_op, ia32_AddrModeS);
2995 set_ia32_am_flavour(new_op, ia32_am_B);
2996 set_ia32_ls_mode(new_op, load_mode);
2997 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2999 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3001 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
3005 * Transforms a FrameAddr into an ia32 Add.
3007 static ir_node *gen_be_FrameAddr(ir_node *node) {
3008 ir_node *block = be_transform_node(get_nodes_block(node));
3009 ir_node *op = be_get_FrameAddr_frame(node);
3010 ir_node *new_op = be_transform_node(op);
3011 ir_graph *irg = current_ir_graph;
3012 dbg_info *dbgi = get_irn_dbg_info(node);
3013 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3016 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3017 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3018 set_ia32_use_frame(res);
3019 set_ia32_am_flavour(res, ia32_am_OB);
3021 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3027 * Transforms a FrameLoad into an ia32 Load.
3029 static ir_node *gen_be_FrameLoad(ir_node *node) {
3030 ir_node *block = be_transform_node(get_nodes_block(node));
3031 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
3032 ir_node *new_mem = be_transform_node(mem);
3033 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
3034 ir_node *new_ptr = be_transform_node(ptr);
3035 ir_node *new_op = NULL;
3036 ir_graph *irg = current_ir_graph;
3037 dbg_info *dbgi = get_irn_dbg_info(node);
3038 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3039 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
3040 ir_mode *mode = get_type_mode(get_entity_type(ent));
3041 ir_node *projs[pn_Load_max];
3043 ia32_collect_Projs(node, projs, pn_Load_max);
3045 if (mode_is_float(mode)) {
3046 if (USE_SSE2(env_cg)) {
3047 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
3050 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
3054 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
3057 set_irn_pinned(new_op, op_pin_state_floats);
3058 set_ia32_frame_ent(new_op, ent);
3059 set_ia32_use_frame(new_op);
3061 set_ia32_op_type(new_op, ia32_AddrModeS);
3062 set_ia32_am_flavour(new_op, ia32_am_B);
3063 set_ia32_ls_mode(new_op, mode);
3064 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
3066 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3073 * Transforms a FrameStore into an ia32 Store.
3075 static ir_node *gen_be_FrameStore(ir_node *node) {
3076 ir_node *block = be_transform_node(get_nodes_block(node));
3077 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
3078 ir_node *new_mem = be_transform_node(mem);
3079 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
3080 ir_node *new_ptr = be_transform_node(ptr);
3081 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
3082 ir_node *new_val = be_transform_node(val);
3083 ir_node *new_op = NULL;
3084 ir_graph *irg = current_ir_graph;
3085 dbg_info *dbgi = get_irn_dbg_info(node);
3086 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3087 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
3088 ir_mode *mode = get_irn_mode(val);
3090 if (mode_is_float(mode)) {
3091 if (USE_SSE2(env_cg)) {
3092 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3094 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
3096 } else if (get_mode_size_bits(mode) == 8) {
3097 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3099 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3102 set_ia32_frame_ent(new_op, ent);
3103 set_ia32_use_frame(new_op);
3105 set_ia32_op_type(new_op, ia32_AddrModeD);
3106 set_ia32_am_flavour(new_op, ia32_am_B);
3107 set_ia32_ls_mode(new_op, mode);
3109 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3115 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3117 static ir_node *gen_be_Return(ir_node *node) {
3118 ir_graph *irg = current_ir_graph;
3119 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3120 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3121 ir_entity *ent = get_irg_entity(irg);
3122 ir_type *tp = get_entity_type(ent);
3127 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3128 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3131 int pn_ret_val, pn_ret_mem, arity, i;
3133 assert(ret_val != NULL);
3134 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3135 return be_duplicate_node(node);
3138 res_type = get_method_res_type(tp, 0);
3140 if (! is_Primitive_type(res_type)) {
3141 return be_duplicate_node(node);
3144 mode = get_type_mode(res_type);
3145 if (! mode_is_float(mode)) {
3146 return be_duplicate_node(node);
3149 assert(get_method_n_ress(tp) == 1);
3151 pn_ret_val = get_Proj_proj(ret_val);
3152 pn_ret_mem = get_Proj_proj(ret_mem);
3154 /* get the Barrier */
3155 barrier = get_Proj_pred(ret_val);
3157 /* get result input of the Barrier */
3158 ret_val = get_irn_n(barrier, pn_ret_val);
3159 new_ret_val = be_transform_node(ret_val);
3161 /* get memory input of the Barrier */
3162 ret_mem = get_irn_n(barrier, pn_ret_mem);
3163 new_ret_mem = be_transform_node(ret_mem);
3165 frame = get_irg_frame(irg);
3167 dbgi = get_irn_dbg_info(barrier);
3168 block = be_transform_node(get_nodes_block(barrier));
3170 noreg = ia32_new_NoReg_gp(env_cg);
3172 /* store xmm0 onto stack */
3173 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3174 new_ret_val, new_ret_mem);
3175 set_ia32_ls_mode(sse_store, mode);
3176 set_ia32_op_type(sse_store, ia32_AddrModeD);
3177 set_ia32_use_frame(sse_store);
3178 set_ia32_am_flavour(sse_store, ia32_am_B);
3180 /* load into x87 register */
3181 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3182 set_ia32_op_type(fld, ia32_AddrModeS);
3183 set_ia32_use_frame(fld);
3184 set_ia32_am_flavour(fld, ia32_am_B);
3186 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3187 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3189 /* create a new barrier */
3190 arity = get_irn_arity(barrier);
3191 in = alloca(arity * sizeof(in[0]));
3192 for (i = 0; i < arity; ++i) {
3195 if (i == pn_ret_val) {
3197 } else if (i == pn_ret_mem) {
3200 ir_node *in = get_irn_n(barrier, i);
3201 new_in = be_transform_node(in);
3206 new_barrier = new_ir_node(dbgi, irg, block,
3207 get_irn_op(barrier), get_irn_mode(barrier),
3209 copy_node_attr(barrier, new_barrier);
3210 be_duplicate_deps(barrier, new_barrier);
3211 be_set_transformed_node(barrier, new_barrier);
3212 mark_irn_visited(barrier);
3214 /* transform normally */
3215 return be_duplicate_node(node);
3219 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3221 static ir_node *gen_be_AddSP(ir_node *node) {
3222 ir_node *block = be_transform_node(get_nodes_block(node));
3223 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3225 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3226 ir_node *new_sp = be_transform_node(sp);
3227 ir_graph *irg = current_ir_graph;
3228 dbg_info *dbgi = get_irn_dbg_info(node);
3229 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3230 ir_node *nomem = new_NoMem();
3233 new_sz = create_immediate_or_transform(sz, 0);
3235 /* ia32 stack grows in reverse direction, make a SubSP */
3236 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3238 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3239 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3245 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3247 static ir_node *gen_be_SubSP(ir_node *node) {
3248 ir_node *block = be_transform_node(get_nodes_block(node));
3249 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3251 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3252 ir_node *new_sp = be_transform_node(sp);
3253 ir_graph *irg = current_ir_graph;
3254 dbg_info *dbgi = get_irn_dbg_info(node);
3255 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3256 ir_node *nomem = new_NoMem();
3259 new_sz = create_immediate_or_transform(sz, 0);
3261 /* ia32 stack grows in reverse direction, make an AddSP */
3262 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3263 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3264 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3270 * This function just sets the register for the Unknown node
3271 * as this is not done during register allocation because Unknown
3272 * is an "ignore" node.
3274 static ir_node *gen_Unknown(ir_node *node) {
3275 ir_mode *mode = get_irn_mode(node);
3277 if (mode_is_float(mode)) {
3279 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3280 if (USE_SSE2(env_cg))
3281 return ia32_new_Unknown_xmm(env_cg);
3283 return ia32_new_Unknown_vfp(env_cg);
3285 ir_graph *irg = current_ir_graph;
3286 dbg_info *dbgi = get_irn_dbg_info(node);
3287 ir_node *block = get_irg_start_block(irg);
3288 return new_rd_ia32_vfldz(dbgi, irg, block);
3290 } else if (mode_needs_gp_reg(mode)) {
3291 return ia32_new_Unknown_gp(env_cg);
3293 assert(0 && "unsupported Unknown-Mode");
3300 * Change some phi modes
3302 static ir_node *gen_Phi(ir_node *node) {
3303 ir_node *block = be_transform_node(get_nodes_block(node));
3304 ir_graph *irg = current_ir_graph;
3305 dbg_info *dbgi = get_irn_dbg_info(node);
3306 ir_mode *mode = get_irn_mode(node);
3309 if(mode_needs_gp_reg(mode)) {
3310 /* we shouldn't have any 64bit stuff around anymore */
3311 assert(get_mode_size_bits(mode) <= 32);
3312 /* all integer operations are on 32bit registers now */
3314 } else if(mode_is_float(mode)) {
3315 if (USE_SSE2(env_cg)) {
3322 /* phi nodes allow loops, so we use the old arguments for now
3323 * and fix this later */
3324 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3325 copy_node_attr(node, phi);
3326 be_duplicate_deps(node, phi);
3328 be_set_transformed_node(node, phi);
3329 be_enqueue_preds(node);
3337 static ir_node *gen_IJmp(ir_node *node) {
3338 ir_node *block = be_transform_node(get_nodes_block(node));
3339 ir_graph *irg = current_ir_graph;
3340 dbg_info *dbgi = get_irn_dbg_info(node);
3341 ir_node *new_op = be_transform_node(get_IJmp_target(node));
3342 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3343 ir_node *nomem = new_NoMem();
3346 new_node = new_rd_ia32_IJmp(dbgi, irg, block, noreg, noreg, new_op, nomem);
3347 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_unary);
3349 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3355 /**********************************************************************
3358 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3359 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3360 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3361 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3363 **********************************************************************/
3365 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3367 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3370 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3371 ir_node *val, ir_node *mem);
3374 * Transforms a lowered Load into a "real" one.
3376 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3378 ir_node *block = be_transform_node(get_nodes_block(node));
3379 ir_node *ptr = get_irn_n(node, 0);
3380 ir_node *new_ptr = be_transform_node(ptr);
3381 ir_node *mem = get_irn_n(node, 1);
3382 ir_node *new_mem = be_transform_node(mem);
3383 ir_graph *irg = current_ir_graph;
3384 dbg_info *dbgi = get_irn_dbg_info(node);
3385 ir_mode *mode = get_ia32_ls_mode(node);
3386 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3389 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3391 set_ia32_op_type(new_op, ia32_AddrModeS);
3392 set_ia32_am_flavour(new_op, ia32_am_OB);
3393 set_ia32_am_offs_int(new_op, 0);
3394 set_ia32_am_scale(new_op, 1);
3395 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3396 if (is_ia32_am_sc_sign(node))
3397 set_ia32_am_sc_sign(new_op);
3398 set_ia32_ls_mode(new_op, mode);
3399 if (is_ia32_use_frame(node)) {
3400 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3401 set_ia32_use_frame(new_op);
3404 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3410 * Transforms a lowered Store into a "real" one.
3412 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3414 ir_node *block = be_transform_node(get_nodes_block(node));
3415 ir_node *ptr = get_irn_n(node, 0);
3416 ir_node *new_ptr = be_transform_node(ptr);
3417 ir_node *val = get_irn_n(node, 1);
3418 ir_node *new_val = be_transform_node(val);
3419 ir_node *mem = get_irn_n(node, 2);
3420 ir_node *new_mem = be_transform_node(mem);
3421 ir_graph *irg = current_ir_graph;
3422 dbg_info *dbgi = get_irn_dbg_info(node);
3423 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3424 ir_mode *mode = get_ia32_ls_mode(node);
3427 ia32_am_flavour_t am_flav = ia32_B;
3429 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3431 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3433 add_ia32_am_offs_int(new_op, am_offs);
3436 set_ia32_op_type(new_op, ia32_AddrModeD);
3437 set_ia32_am_flavour(new_op, am_flav);
3438 set_ia32_ls_mode(new_op, mode);
3439 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3440 set_ia32_use_frame(new_op);
3442 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3449 * Transforms an ia32_l_XXX into a "real" XXX node
3451 * @param env The transformation environment
3452 * @return the created ia32 XXX node
3454 #define GEN_LOWERED_OP(op) \
3455 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3456 return gen_binop(node, get_binop_left(node), \
3457 get_binop_right(node), new_rd_ia32_##op,0); \
3460 #define GEN_LOWERED_x87_OP(op) \
3461 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3463 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3464 get_binop_right(node), new_rd_ia32_##op); \
3468 #define GEN_LOWERED_UNOP(op) \
3469 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3470 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3473 #define GEN_LOWERED_SHIFT_OP(op) \
3474 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3475 return gen_shift_binop(node, get_binop_left(node), \
3476 get_binop_right(node), new_rd_ia32_##op); \
3479 #define GEN_LOWERED_LOAD(op) \
3480 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3481 return gen_lowered_Load(node, new_rd_ia32_##op); \
3484 #define GEN_LOWERED_STORE(op) \
3485 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3486 return gen_lowered_Store(node, new_rd_ia32_##op); \
3493 GEN_LOWERED_OP(IMul)
3495 GEN_LOWERED_x87_OP(vfprem)
3496 GEN_LOWERED_x87_OP(vfmul)
3497 GEN_LOWERED_x87_OP(vfsub)
3499 GEN_LOWERED_UNOP(Neg)
3501 GEN_LOWERED_LOAD(vfild)
3502 GEN_LOWERED_LOAD(Load)
3503 GEN_LOWERED_STORE(Store)
3506 * Transforms a l_vfist into a "real" vfist node.
3508 * @param env The transformation environment
3509 * @return the created ia32 vfist node
3511 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3512 ir_node *block = be_transform_node(get_nodes_block(node));
3513 ir_node *ptr = get_irn_n(node, 0);
3514 ir_node *new_ptr = be_transform_node(ptr);
3515 ir_node *val = get_irn_n(node, 1);
3516 ir_node *new_val = be_transform_node(val);
3517 ir_node *mem = get_irn_n(node, 2);
3518 ir_node *new_mem = be_transform_node(mem);
3519 ir_graph *irg = current_ir_graph;
3520 dbg_info *dbgi = get_irn_dbg_info(node);
3521 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3522 ir_mode *mode = get_ia32_ls_mode(node);
3523 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3526 ia32_am_flavour_t am_flav = ia32_B;
3528 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_val, trunc_mode, new_mem);
3530 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3532 add_ia32_am_offs_int(new_op, am_offs);
3535 set_ia32_op_type(new_op, ia32_AddrModeD);
3536 set_ia32_am_flavour(new_op, am_flav);
3537 set_ia32_ls_mode(new_op, mode);
3538 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3539 set_ia32_use_frame(new_op);
3541 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3547 * Transforms a l_vfdiv into a "real" vfdiv node.
3549 * @param env The transformation environment
3550 * @return the created ia32 vfdiv node
3552 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3553 ir_node *block = be_transform_node(get_nodes_block(node));
3554 ir_node *left = get_binop_left(node);
3555 ir_node *new_left = be_transform_node(left);
3556 ir_node *right = get_binop_right(node);
3557 ir_node *new_right = be_transform_node(right);
3558 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3559 ir_graph *irg = current_ir_graph;
3560 dbg_info *dbgi = get_irn_dbg_info(node);
3561 ir_node *fpcw = get_fpcw();
3564 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3565 new_right, new_NoMem(), fpcw);
3566 clear_ia32_commutative(vfdiv);
3567 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3569 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3575 * Transforms a l_MulS into a "real" MulS node.
3577 * @param env The transformation environment
3578 * @return the created ia32 Mul node
3580 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3581 ir_node *block = be_transform_node(get_nodes_block(node));
3582 ir_node *left = get_binop_left(node);
3583 ir_node *new_left = be_transform_node(left);
3584 ir_node *right = get_binop_right(node);
3585 ir_node *new_right = be_transform_node(right);
3586 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3587 ir_graph *irg = current_ir_graph;
3588 dbg_info *dbgi = get_irn_dbg_info(node);
3590 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3591 /* and then skip the result Proj, because all needed Projs are already there. */
3592 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3593 new_right, new_NoMem());
3594 clear_ia32_commutative(muls);
3595 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3597 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3602 GEN_LOWERED_SHIFT_OP(Shl)
3603 GEN_LOWERED_SHIFT_OP(Shr)
3604 GEN_LOWERED_SHIFT_OP(Sar)
3607 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3608 * op1 - target to be shifted
3609 * op2 - contains bits to be shifted into target
3611 * Only op3 can be an immediate.
3613 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3614 ir_node *op2, ir_node *count)
3616 ir_node *block = be_transform_node(get_nodes_block(node));
3617 ir_node *new_op1 = be_transform_node(op1);
3618 ir_node *new_op2 = be_transform_node(op2);
3619 ir_node *new_count = be_transform_node(count);
3620 ir_node *new_op = NULL;
3621 ir_graph *irg = current_ir_graph;
3622 dbg_info *dbgi = get_irn_dbg_info(node);
3623 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3624 ir_node *nomem = new_NoMem();
3628 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3630 /* Check if immediate optimization is on and */
3631 /* if it's an operation with immediate. */
3632 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3634 /* Limit imm_op within range imm8 */
3636 tv = get_ia32_Immop_tarval(imm_op);
3639 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3640 set_ia32_Immop_tarval(imm_op, tv);
3647 /* integer operations */
3649 /* This is ShiftD with const */
3650 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3652 if (is_ia32_l_ShlD(node))
3653 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3654 new_op1, new_op2, noreg, nomem);
3656 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3657 new_op1, new_op2, noreg, nomem);
3658 copy_ia32_Immop_attr(new_op, imm_op);
3661 /* This is a normal ShiftD */
3662 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3663 if (is_ia32_l_ShlD(node))
3664 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3665 new_op1, new_op2, new_count, nomem);
3667 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3668 new_op1, new_op2, new_count, nomem);
3671 /* set AM support */
3672 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3674 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3676 set_ia32_emit_cl(new_op);
3681 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3682 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3683 get_irn_n(node, 1), get_irn_n(node, 2));
3686 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3687 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3688 get_irn_n(node, 1), get_irn_n(node, 2));
3692 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3694 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3695 ir_node *block = be_transform_node(get_nodes_block(node));
3696 ir_node *val = get_irn_n(node, 1);
3697 ir_node *new_val = be_transform_node(val);
3698 ia32_code_gen_t *cg = env_cg;
3699 ir_node *res = NULL;
3700 ir_graph *irg = current_ir_graph;
3702 ir_node *noreg, *new_ptr, *new_mem;
3709 mem = get_irn_n(node, 2);
3710 new_mem = be_transform_node(mem);
3711 ptr = get_irn_n(node, 0);
3712 new_ptr = be_transform_node(ptr);
3713 noreg = ia32_new_NoReg_gp(cg);
3714 dbgi = get_irn_dbg_info(node);
3716 /* Store x87 -> MEM */
3717 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3718 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3719 set_ia32_use_frame(res);
3720 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3721 set_ia32_am_flavour(res, ia32_B);
3722 set_ia32_op_type(res, ia32_AddrModeD);
3724 /* Load MEM -> SSE */
3725 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3726 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3727 set_ia32_use_frame(res);
3728 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3729 set_ia32_am_flavour(res, ia32_B);
3730 set_ia32_op_type(res, ia32_AddrModeS);
3731 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3737 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3739 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3740 ir_node *block = be_transform_node(get_nodes_block(node));
3741 ir_node *val = get_irn_n(node, 1);
3742 ir_node *new_val = be_transform_node(val);
3743 ia32_code_gen_t *cg = env_cg;
3744 ir_graph *irg = current_ir_graph;
3745 ir_node *res = NULL;
3746 ir_entity *fent = get_ia32_frame_ent(node);
3747 ir_mode *lsmode = get_ia32_ls_mode(node);
3749 ir_node *noreg, *new_ptr, *new_mem;
3753 if (! USE_SSE2(cg)) {
3754 /* SSE unit is not used -> skip this node. */
3758 ptr = get_irn_n(node, 0);
3759 new_ptr = be_transform_node(ptr);
3760 mem = get_irn_n(node, 2);
3761 new_mem = be_transform_node(mem);
3762 noreg = ia32_new_NoReg_gp(cg);
3763 dbgi = get_irn_dbg_info(node);
3765 /* Store SSE -> MEM */
3766 if (is_ia32_xLoad(skip_Proj(new_val))) {
3767 ir_node *ld = skip_Proj(new_val);
3769 /* we can vfld the value directly into the fpu */
3770 fent = get_ia32_frame_ent(ld);
3771 ptr = get_irn_n(ld, 0);
3772 offs = get_ia32_am_offs_int(ld);
3774 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3775 set_ia32_frame_ent(res, fent);
3776 set_ia32_use_frame(res);
3777 set_ia32_ls_mode(res, lsmode);
3778 set_ia32_am_flavour(res, ia32_B);
3779 set_ia32_op_type(res, ia32_AddrModeD);
3783 /* Load MEM -> x87 */
3784 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3785 set_ia32_frame_ent(res, fent);
3786 set_ia32_use_frame(res);
3787 add_ia32_am_offs_int(res, offs);
3788 set_ia32_am_flavour(res, ia32_B);
3789 set_ia32_op_type(res, ia32_AddrModeS);
3790 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3795 /*********************************************************
3798 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3799 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3800 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3801 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3803 *********************************************************/
3806 * the BAD transformer.
3808 static ir_node *bad_transform(ir_node *node) {
3809 panic("No transform function for %+F available.\n", node);
3814 * Transform the Projs of an AddSP.
3816 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3817 ir_node *block = be_transform_node(get_nodes_block(node));
3818 ir_node *pred = get_Proj_pred(node);
3819 ir_node *new_pred = be_transform_node(pred);
3820 ir_graph *irg = current_ir_graph;
3821 dbg_info *dbgi = get_irn_dbg_info(node);
3822 long proj = get_Proj_proj(node);
3824 if (proj == pn_be_AddSP_sp) {
3825 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3826 pn_ia32_SubSP_stack);
3827 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3829 } else if(proj == pn_be_AddSP_res) {
3830 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3831 pn_ia32_SubSP_addr);
3832 } else if (proj == pn_be_AddSP_M) {
3833 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3837 return new_rd_Unknown(irg, get_irn_mode(node));
3841 * Transform the Projs of a SubSP.
3843 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3844 ir_node *block = be_transform_node(get_nodes_block(node));
3845 ir_node *pred = get_Proj_pred(node);
3846 ir_node *new_pred = be_transform_node(pred);
3847 ir_graph *irg = current_ir_graph;
3848 dbg_info *dbgi = get_irn_dbg_info(node);
3849 long proj = get_Proj_proj(node);
3851 if (proj == pn_be_SubSP_sp) {
3852 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3853 pn_ia32_AddSP_stack);
3854 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3856 } else if (proj == pn_be_SubSP_M) {
3857 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3861 return new_rd_Unknown(irg, get_irn_mode(node));
3865 * Transform and renumber the Projs from a Load.
3867 static ir_node *gen_Proj_Load(ir_node *node) {
3868 ir_node *block = be_transform_node(get_nodes_block(node));
3869 ir_node *pred = get_Proj_pred(node);
3870 ir_node *new_pred = be_transform_node(pred);
3871 ir_graph *irg = current_ir_graph;
3872 dbg_info *dbgi = get_irn_dbg_info(node);
3873 long proj = get_Proj_proj(node);
3875 /* renumber the proj */
3876 if (is_ia32_Load(new_pred)) {
3877 if (proj == pn_Load_res) {
3878 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3879 } else if (proj == pn_Load_M) {
3880 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3882 } else if(is_ia32_Conv_I2I(new_pred)) {
3883 set_irn_mode(new_pred, mode_T);
3884 if (proj == pn_Load_res) {
3885 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, 0);
3886 } else if (proj == pn_Load_M) {
3887 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
3889 } else if (is_ia32_xLoad(new_pred)) {
3890 if (proj == pn_Load_res) {
3891 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3892 } else if (proj == pn_Load_M) {
3893 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3895 } else if (is_ia32_vfld(new_pred)) {
3896 if (proj == pn_Load_res) {
3897 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3898 } else if (proj == pn_Load_M) {
3899 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3904 return new_rd_Unknown(irg, get_irn_mode(node));
3908 * Transform and renumber the Projs from a DivMod like instruction.
3910 static ir_node *gen_Proj_DivMod(ir_node *node) {
3911 ir_node *block = be_transform_node(get_nodes_block(node));
3912 ir_node *pred = get_Proj_pred(node);
3913 ir_node *new_pred = be_transform_node(pred);
3914 ir_graph *irg = current_ir_graph;
3915 dbg_info *dbgi = get_irn_dbg_info(node);
3916 ir_mode *mode = get_irn_mode(node);
3917 long proj = get_Proj_proj(node);
3919 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3921 switch (get_irn_opcode(pred)) {
3925 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3927 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3935 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3937 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3945 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3946 case pn_DivMod_res_div:
3947 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3948 case pn_DivMod_res_mod:
3949 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3959 return new_rd_Unknown(irg, mode);
3963 * Transform and renumber the Projs from a CopyB.
3965 static ir_node *gen_Proj_CopyB(ir_node *node) {
3966 ir_node *block = be_transform_node(get_nodes_block(node));
3967 ir_node *pred = get_Proj_pred(node);
3968 ir_node *new_pred = be_transform_node(pred);
3969 ir_graph *irg = current_ir_graph;
3970 dbg_info *dbgi = get_irn_dbg_info(node);
3971 ir_mode *mode = get_irn_mode(node);
3972 long proj = get_Proj_proj(node);
3975 case pn_CopyB_M_regular:
3976 if (is_ia32_CopyB_i(new_pred)) {
3977 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3978 } else if (is_ia32_CopyB(new_pred)) {
3979 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3987 return new_rd_Unknown(irg, mode);
3991 * Transform and renumber the Projs from a vfdiv.
3993 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3994 ir_node *block = be_transform_node(get_nodes_block(node));
3995 ir_node *pred = get_Proj_pred(node);
3996 ir_node *new_pred = be_transform_node(pred);
3997 ir_graph *irg = current_ir_graph;
3998 dbg_info *dbgi = get_irn_dbg_info(node);
3999 ir_mode *mode = get_irn_mode(node);
4000 long proj = get_Proj_proj(node);
4003 case pn_ia32_l_vfdiv_M:
4004 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4005 case pn_ia32_l_vfdiv_res:
4006 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4011 return new_rd_Unknown(irg, mode);
4015 * Transform and renumber the Projs from a Quot.
4017 static ir_node *gen_Proj_Quot(ir_node *node) {
4018 ir_node *block = be_transform_node(get_nodes_block(node));
4019 ir_node *pred = get_Proj_pred(node);
4020 ir_node *new_pred = be_transform_node(pred);
4021 ir_graph *irg = current_ir_graph;
4022 dbg_info *dbgi = get_irn_dbg_info(node);
4023 ir_mode *mode = get_irn_mode(node);
4024 long proj = get_Proj_proj(node);
4028 if (is_ia32_xDiv(new_pred)) {
4029 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4030 } else if (is_ia32_vfdiv(new_pred)) {
4031 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4035 if (is_ia32_xDiv(new_pred)) {
4036 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4037 } else if (is_ia32_vfdiv(new_pred)) {
4038 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4046 return new_rd_Unknown(irg, mode);
4050 * Transform the Thread Local Storage Proj.
4052 static ir_node *gen_Proj_tls(ir_node *node) {
4053 ir_node *block = be_transform_node(get_nodes_block(node));
4054 ir_graph *irg = current_ir_graph;
4055 dbg_info *dbgi = NULL;
4056 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4062 * Transform the Projs from a be_Call.
4064 static ir_node *gen_Proj_be_Call(ir_node *node) {
4065 ir_node *block = be_transform_node(get_nodes_block(node));
4066 ir_node *call = get_Proj_pred(node);
4067 ir_node *new_call = be_transform_node(call);
4068 ir_graph *irg = current_ir_graph;
4069 dbg_info *dbgi = get_irn_dbg_info(node);
4070 long proj = get_Proj_proj(node);
4071 ir_mode *mode = get_irn_mode(node);
4073 const arch_register_class_t *cls;
4075 /* The following is kinda tricky: If we're using SSE, then we have to
4076 * move the result value of the call in floating point registers to an
4077 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4078 * after the call, we have to make sure to correctly make the
4079 * MemProj and the result Proj use these 2 nodes
4081 if (proj == pn_be_Call_M_regular) {
4082 // get new node for result, are we doing the sse load/store hack?
4083 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4084 ir_node *call_res_new;
4085 ir_node *call_res_pred = NULL;
4087 if (call_res != NULL) {
4088 call_res_new = be_transform_node(call_res);
4089 call_res_pred = get_Proj_pred(call_res_new);
4092 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4093 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4094 pn_be_Call_M_regular);
4096 assert(is_ia32_xLoad(call_res_pred));
4097 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4101 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
4103 ir_node *frame = get_irg_frame(irg);
4104 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4106 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4109 /* in case there is no memory output: create one to serialize the copy
4111 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4112 pn_be_Call_M_regular);
4113 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4114 pn_be_Call_first_res);
4116 /* store st(0) onto stack */
4117 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4119 set_ia32_op_type(fstp, ia32_AddrModeD);
4120 set_ia32_use_frame(fstp);
4121 set_ia32_am_flavour(fstp, ia32_am_B);
4123 /* load into SSE register */
4124 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
4125 set_ia32_ls_mode(sse_load, mode);
4126 set_ia32_op_type(sse_load, ia32_AddrModeS);
4127 set_ia32_use_frame(sse_load);
4128 set_ia32_am_flavour(sse_load, ia32_am_B);
4130 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4134 /* now: create new Keep whith all former ins and one additional in - the result Proj */
4136 /* get a Proj representing a caller save register */
4137 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
4138 assert(is_Proj(p) && "Proj expected.");
4140 /* user of the the proj is the Keep */
4141 p = get_edge_src_irn(get_irn_out_edge_first(p));
4142 assert(be_is_Keep(p) && "Keep expected.");
4148 /* transform call modes */
4149 if (mode_is_data(mode)) {
4150 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4154 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4158 * Transform the Projs from a Cmp.
4160 static ir_node *gen_Proj_Cmp(ir_node *node)
4162 /* normally Cmps are processed when looking at Cond nodes, but this case
4163 * can happen in complicated Psi conditions */
4165 ir_node *cmp = get_Proj_pred(node);
4166 long pnc = get_Proj_proj(node);
4167 ir_node *cmp_left = get_Cmp_left(cmp);
4168 ir_node *cmp_right = get_Cmp_right(cmp);
4169 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4170 dbg_info *dbgi = get_irn_dbg_info(cmp);
4171 ir_node *block = be_transform_node(get_nodes_block(node));
4174 assert(!mode_is_float(cmp_mode));
4176 if(!mode_is_signed(cmp_mode)) {
4177 pnc |= ia32_pn_Cmp_Unsigned;
4180 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
4181 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
4187 * Transform and potentially renumber Proj nodes.
4189 static ir_node *gen_Proj(ir_node *node) {
4190 ir_graph *irg = current_ir_graph;
4191 dbg_info *dbgi = get_irn_dbg_info(node);
4192 ir_node *pred = get_Proj_pred(node);
4193 long proj = get_Proj_proj(node);
4195 if (is_Store(pred) || be_is_FrameStore(pred)) {
4196 if (proj == pn_Store_M) {
4197 return be_transform_node(pred);
4200 return new_r_Bad(irg);
4202 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4203 return gen_Proj_Load(node);
4204 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4205 return gen_Proj_DivMod(node);
4206 } else if (is_CopyB(pred)) {
4207 return gen_Proj_CopyB(node);
4208 } else if (is_Quot(pred)) {
4209 return gen_Proj_Quot(node);
4210 } else if (is_ia32_l_vfdiv(pred)) {
4211 return gen_Proj_l_vfdiv(node);
4212 } else if (be_is_SubSP(pred)) {
4213 return gen_Proj_be_SubSP(node);
4214 } else if (be_is_AddSP(pred)) {
4215 return gen_Proj_be_AddSP(node);
4216 } else if (be_is_Call(pred)) {
4217 return gen_Proj_be_Call(node);
4218 } else if (is_Cmp(pred)) {
4219 return gen_Proj_Cmp(node);
4220 } else if (get_irn_op(pred) == op_Start) {
4221 if (proj == pn_Start_X_initial_exec) {
4222 ir_node *block = get_nodes_block(pred);
4225 /* we exchange the ProjX with a jump */
4226 block = be_transform_node(block);
4227 jump = new_rd_Jmp(dbgi, irg, block);
4230 if (node == be_get_old_anchor(anchor_tls)) {
4231 return gen_Proj_tls(node);
4234 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4238 ir_node *new_pred = be_transform_node(pred);
4239 ir_node *block = be_transform_node(get_nodes_block(node));
4240 ir_mode *mode = get_irn_mode(node);
4241 if (mode_needs_gp_reg(mode)) {
4242 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4243 get_Proj_proj(node));
4244 #ifdef DEBUG_libfirm
4245 new_proj->node_nr = node->node_nr;
4251 return be_duplicate_node(node);
4255 * Enters all transform functions into the generic pointer
4257 static void register_transformers(void)
4261 /* first clear the generic function pointer for all ops */
4262 clear_irp_opcodes_generic_func();
4264 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4265 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4302 /* transform ops from intrinsic lowering */
4324 GEN(ia32_l_X87toSSE);
4325 GEN(ia32_l_SSEtoX87);
4330 /* we should never see these nodes */
4345 /* handle generic backend nodes */
4356 /* set the register for all Unknown nodes */
4359 op_Mulh = get_op_Mulh();
4368 * Pre-transform all unknown and noreg nodes.
4370 static void ia32_pretransform_node(void *arch_cg) {
4371 ia32_code_gen_t *cg = arch_cg;
4373 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4374 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4375 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4376 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4377 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4378 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4383 * Walker, checks if all ia32 nodes producing more than one result have
4384 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4387 void add_missing_keep_walker(ir_node *node, void *data)
4390 unsigned found_projs = 0;
4391 const ir_edge_t *edge;
4392 ir_mode *mode = get_irn_mode(node);
4397 if(!is_ia32_irn(node))
4400 n_outs = get_ia32_n_res(node);
4403 if(is_ia32_SwitchJmp(node))
4406 assert(n_outs < (int) sizeof(unsigned) * 8);
4407 foreach_out_edge(node, edge) {
4408 ir_node *proj = get_edge_src_irn(edge);
4409 int pn = get_Proj_proj(proj);
4411 assert(pn < n_outs);
4412 found_projs |= 1 << pn;
4416 /* are keeps missing? */
4418 for(i = 0; i < n_outs; ++i) {
4421 const arch_register_req_t *req;
4422 const arch_register_class_t *class;
4424 if(found_projs & (1 << i)) {
4428 req = get_ia32_out_req(node, i);
4434 block = get_nodes_block(node);
4435 in[0] = new_r_Proj(current_ir_graph, block, node,
4436 arch_register_class_mode(class), i);
4437 if(last_keep != NULL) {
4438 be_Keep_add_node(last_keep, class, in[0]);
4440 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4446 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4450 void add_missing_keeps(ia32_code_gen_t *cg)
4452 ir_graph *irg = be_get_birg_irg(cg->birg);
4453 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4456 /* do the transformation */
4457 void ia32_transform_graph(ia32_code_gen_t *cg) {
4458 register_transformers();
4460 initial_fpcw = NULL;
4461 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4462 edges_verify(cg->irg);
4463 add_missing_keeps(cg);
4464 edges_verify(cg->irg);
4467 void ia32_init_transform(void)
4469 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");