2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
60 #include "bearch_ia32_t.h"
61 #include "ia32_nodes_attr.h"
62 #include "ia32_transform.h"
63 #include "ia32_new_nodes.h"
64 #include "ia32_map_regs.h"
65 #include "ia32_dbg_stat.h"
66 #include "ia32_optimize.h"
67 #include "ia32_util.h"
68 #include "ia32_address_mode.h"
69 #include "ia32_architecture.h"
71 #include "gen_ia32_regalloc_if.h"
73 #define SFP_SIGN "0x80000000"
74 #define DFP_SIGN "0x8000000000000000"
75 #define SFP_ABS "0x7FFFFFFF"
76 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
77 #define DFP_INTMAX "9223372036854775807"
79 #define TP_SFP_SIGN "ia32_sfp_sign"
80 #define TP_DFP_SIGN "ia32_dfp_sign"
81 #define TP_SFP_ABS "ia32_sfp_abs"
82 #define TP_DFP_ABS "ia32_dfp_abs"
83 #define TP_INT_MAX "ia32_int_max"
85 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
86 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
87 #define ENT_SFP_ABS "IA32_SFP_ABS"
88 #define ENT_DFP_ABS "IA32_DFP_ABS"
89 #define ENT_INT_MAX "IA32_INT_MAX"
91 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
92 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
94 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
96 /** hold the current code generator during transformation */
97 static ia32_code_gen_t *env_cg = NULL;
98 static ir_node *initial_fpcw = NULL;
99 static heights_t *heights = NULL;
101 extern ir_op *get_op_Mulh(void);
103 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
104 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
105 ir_node *op1, ir_node *op2);
107 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
108 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
109 ir_node *op1, ir_node *op2, ir_node *flags);
111 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
112 ir_node *block, ir_node *op1, ir_node *op2);
114 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
115 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
118 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
119 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
121 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
122 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
123 ir_node *op1, ir_node *op2, ir_node *fpcw);
125 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
126 ir_node *block, ir_node *op);
128 static ir_node *try_create_Immediate(ir_node *node,
129 char immediate_constraint_type);
131 static ir_node *create_immediate_or_transform(ir_node *node,
132 char immediate_constraint_type);
134 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
135 dbg_info *dbgi, ir_node *block,
136 ir_node *op, ir_node *orig_node);
139 * Return true if a mode can be stored in the GP register set
141 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
142 if(mode == mode_fpcw)
144 if(get_mode_size_bits(mode) > 32)
146 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
150 * creates a unique ident by adding a number to a tag
152 * @param tag the tag string, must contain a %d if a number
155 static ident *unique_id(const char *tag)
157 static unsigned id = 0;
160 snprintf(str, sizeof(str), tag, ++id);
161 return new_id_from_str(str);
165 * Get a primitive type for a mode.
167 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
169 pmap_entry *e = pmap_find(types, mode);
174 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
175 res = new_type_primitive(new_id_from_str(buf), mode);
176 set_type_alignment_bytes(res, 16);
177 pmap_insert(types, mode, res);
185 * Get an atomic entity that is initialized with a tarval
187 static ir_entity *create_float_const_entity(ir_node *cnst)
189 ia32_isa_t *isa = env_cg->isa;
190 tarval *tv = get_Const_tarval(cnst);
191 pmap_entry *e = pmap_find(isa->tv_ent, tv);
196 ir_mode *mode = get_irn_mode(cnst);
197 ir_type *tp = get_Const_type(cnst);
198 if (tp == firm_unknown_type)
199 tp = get_prim_type(isa->types, mode);
201 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
203 set_entity_ld_ident(res, get_entity_ident(res));
204 set_entity_visibility(res, visibility_local);
205 set_entity_variability(res, variability_constant);
206 set_entity_allocation(res, allocation_static);
208 /* we create a new entity here: It's initialization must resist on the
210 rem = current_ir_graph;
211 current_ir_graph = get_const_code_irg();
212 set_atomic_ent_value(res, new_Const_type(tv, tp));
213 current_ir_graph = rem;
215 pmap_insert(isa->tv_ent, tv, res);
223 static int is_Const_0(ir_node *node) {
224 return is_Const(node) && is_Const_null(node);
227 static int is_Const_1(ir_node *node) {
228 return is_Const(node) && is_Const_one(node);
231 static int is_Const_Minus_1(ir_node *node) {
232 return is_Const(node) && is_Const_all_one(node);
236 * returns true if constant can be created with a simple float command
238 static int is_simple_x87_Const(ir_node *node)
240 tarval *tv = get_Const_tarval(node);
242 if(tarval_is_null(tv) || tarval_is_one(tv))
245 /* TODO: match all the other float constants */
250 * Transforms a Const.
252 static ir_node *gen_Const(ir_node *node) {
253 ir_graph *irg = current_ir_graph;
254 ir_node *old_block = get_nodes_block(node);
255 ir_node *block = be_transform_node(old_block);
256 dbg_info *dbgi = get_irn_dbg_info(node);
257 ir_mode *mode = get_irn_mode(node);
259 assert(is_Const(node));
261 if (mode_is_float(mode)) {
263 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
264 ir_node *nomem = new_NoMem();
268 if (ia32_cg_config.use_sse2) {
269 if (is_Const_null(node)) {
270 load = new_rd_ia32_xZero(dbgi, irg, block);
271 set_ia32_ls_mode(load, mode);
274 floatent = create_float_const_entity(node);
276 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
278 set_ia32_op_type(load, ia32_AddrModeS);
279 set_ia32_am_sc(load, floatent);
280 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
281 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
284 if (is_Const_null(node)) {
285 load = new_rd_ia32_vfldz(dbgi, irg, block);
287 } else if (is_Const_one(node)) {
288 load = new_rd_ia32_vfld1(dbgi, irg, block);
291 floatent = create_float_const_entity(node);
293 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
294 set_ia32_op_type(load, ia32_AddrModeS);
295 set_ia32_am_sc(load, floatent);
296 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
297 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
299 set_ia32_ls_mode(load, mode);
302 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
304 /* Const Nodes before the initial IncSP are a bad idea, because
305 * they could be spilled and we have no SP ready at that point yet.
306 * So add a dependency to the initial frame pointer calculation to
307 * avoid that situation.
309 if (get_irg_start_block(irg) == block) {
310 add_irn_dep(load, get_irg_frame(irg));
313 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
317 tarval *tv = get_Const_tarval(node);
320 tv = tarval_convert_to(tv, mode_Iu);
322 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
324 panic("couldn't convert constant tarval (%+F)", node);
326 val = get_tarval_long(tv);
328 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
329 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
332 if (get_irg_start_block(irg) == block) {
333 add_irn_dep(cnst, get_irg_frame(irg));
341 * Transforms a SymConst.
343 static ir_node *gen_SymConst(ir_node *node) {
344 ir_graph *irg = current_ir_graph;
345 ir_node *old_block = get_nodes_block(node);
346 ir_node *block = be_transform_node(old_block);
347 dbg_info *dbgi = get_irn_dbg_info(node);
348 ir_mode *mode = get_irn_mode(node);
351 if (mode_is_float(mode)) {
352 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
353 ir_node *nomem = new_NoMem();
355 if (ia32_cg_config.use_sse2)
356 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
358 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
359 set_ia32_am_sc(cnst, get_SymConst_entity(node));
360 set_ia32_use_frame(cnst);
364 if(get_SymConst_kind(node) != symconst_addr_ent) {
365 panic("backend only support symconst_addr_ent (at %+F)", node);
367 entity = get_SymConst_entity(node);
368 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
371 /* Const Nodes before the initial IncSP are a bad idea, because
372 * they could be spilled and we have no SP ready at that point yet
374 if (get_irg_start_block(irg) == block) {
375 add_irn_dep(cnst, get_irg_frame(irg));
378 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
383 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
384 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
385 static const struct {
387 const char *ent_name;
388 const char *cnst_str;
391 } names [ia32_known_const_max] = {
392 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
393 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
394 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
395 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
396 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
398 static ir_entity *ent_cache[ia32_known_const_max];
400 const char *tp_name, *ent_name, *cnst_str;
408 ent_name = names[kct].ent_name;
409 if (! ent_cache[kct]) {
410 tp_name = names[kct].tp_name;
411 cnst_str = names[kct].cnst_str;
413 switch (names[kct].mode) {
414 case 0: mode = mode_Iu; break;
415 case 1: mode = mode_Lu; break;
416 default: mode = mode_F; break;
418 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
419 tp = new_type_primitive(new_id_from_str(tp_name), mode);
420 /* set the specified alignment */
421 set_type_alignment_bytes(tp, names[kct].align);
423 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
425 set_entity_ld_ident(ent, get_entity_ident(ent));
426 set_entity_visibility(ent, visibility_local);
427 set_entity_variability(ent, variability_constant);
428 set_entity_allocation(ent, allocation_static);
430 /* we create a new entity here: It's initialization must resist on the
432 rem = current_ir_graph;
433 current_ir_graph = get_const_code_irg();
434 cnst = new_Const(mode, tv);
435 current_ir_graph = rem;
437 set_atomic_ent_value(ent, cnst);
439 /* cache the entry */
440 ent_cache[kct] = ent;
443 return ent_cache[kct];
448 * Prints the old node name on cg obst and returns a pointer to it.
450 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
451 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
453 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
454 obstack_1grow(isa->name_obst, 0);
455 return obstack_finish(isa->name_obst);
460 * return true if the node is a Proj(Load) and could be used in source address
461 * mode for another node. Will return only true if the @p other node is not
462 * dependent on the memory of the Load (for binary operations use the other
463 * input here, for unary operations use NULL).
465 static int ia32_use_source_address_mode(ir_node *block, ir_node *node,
466 ir_node *other, ir_node *other2)
468 ir_mode *mode = get_irn_mode(node);
472 /* float constants are always available */
473 if(is_Const(node) && mode_is_float(mode)) {
474 if(!is_simple_x87_Const(node))
476 if(get_irn_n_edges(node) > 1)
483 load = get_Proj_pred(node);
484 pn = get_Proj_proj(node);
485 if(!is_Load(load) || pn != pn_Load_res)
487 if(get_nodes_block(load) != block)
489 /* we only use address mode if we're the only user of the load */
490 if(get_irn_n_edges(node) > 1)
492 /* in some edge cases with address mode we might reach the load normally
493 * and through some AM sequence, if it is already materialized then we
494 * can't create an AM node from it */
495 if(be_is_transformed(node))
498 /* don't do AM if other node inputs depend on the load (via mem-proj) */
499 if(other != NULL && get_nodes_block(other) == block
500 && heights_reachable_in_block(heights, other, load))
502 if(other2 != NULL && get_nodes_block(other2) == block
503 && heights_reachable_in_block(heights, other2, load))
509 typedef struct ia32_address_mode_t ia32_address_mode_t;
510 struct ia32_address_mode_t {
514 ia32_op_type_t op_type;
518 unsigned commutative : 1;
519 unsigned ins_permuted : 1;
522 static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
524 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
526 /* construct load address */
527 memset(addr, 0, sizeof(addr[0]));
528 ia32_create_address_mode(addr, ptr, /*force=*/0);
530 addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
531 addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
532 addr->mem = be_transform_node(mem);
535 static void build_address(ia32_address_mode_t *am, ir_node *node)
537 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
538 ia32_address_t *addr = &am->addr;
545 ir_entity *entity = create_float_const_entity(node);
546 addr->base = noreg_gp;
547 addr->index = noreg_gp;
548 addr->mem = new_NoMem();
549 addr->symconst_ent = entity;
551 am->ls_mode = get_irn_mode(node);
552 am->pinned = op_pin_state_floats;
556 load = get_Proj_pred(node);
557 ptr = get_Load_ptr(load);
558 mem = get_Load_mem(load);
559 new_mem = be_transform_node(mem);
560 am->pinned = get_irn_pinned(load);
561 am->ls_mode = get_Load_mode(load);
562 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
564 /* construct load address */
565 ia32_create_address_mode(addr, ptr, /*force=*/0);
567 addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
568 addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
572 static void set_address(ir_node *node, const ia32_address_t *addr)
574 set_ia32_am_scale(node, addr->scale);
575 set_ia32_am_sc(node, addr->symconst_ent);
576 set_ia32_am_offs_int(node, addr->offset);
577 if(addr->symconst_sign)
578 set_ia32_am_sc_sign(node);
580 set_ia32_use_frame(node);
581 set_ia32_frame_ent(node, addr->frame_entity);
584 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
586 set_address(node, &am->addr);
588 set_ia32_op_type(node, am->op_type);
589 set_ia32_ls_mode(node, am->ls_mode);
590 if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) {
591 set_irn_pinned(node, am->pinned);
594 set_ia32_commutative(node);
598 * Check, if a given node is a Down-Conv, ie. a integer Conv
599 * from a mode with a mode with more bits to a mode with lesser bits.
600 * Moreover, we return only true if the node has not more than 1 user.
602 * @param node the node
603 * @return non-zero if node is a Down-Conv
605 static int is_downconv(const ir_node *node)
613 /* we only want to skip the conv when we're the only user
614 * (not optimal but for now...)
616 if(get_irn_n_edges(node) > 1)
619 src_mode = get_irn_mode(get_Conv_op(node));
620 dest_mode = get_irn_mode(node);
621 return mode_needs_gp_reg(src_mode)
622 && mode_needs_gp_reg(dest_mode)
623 && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode);
626 /* Skip all Down-Conv's on a given node and return the resulting node. */
627 ir_node *ia32_skip_downconv(ir_node *node) {
628 while (is_downconv(node))
629 node = get_Conv_op(node);
635 static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
637 ir_mode *mode = get_irn_mode(node);
642 if(mode_is_signed(mode)) {
647 block = get_nodes_block(node);
648 dbgi = get_irn_dbg_info(node);
650 return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
655 * matches operands of a node into ia32 addressing/operand modes. This covers
656 * usage of source address mode, immediates, operations with non 32-bit modes,
658 * The resulting data is filled into the @p am struct. block is the block
659 * of the node whose arguments are matched. op1, op2 are the first and second
660 * input that are matched (op1 may be NULL). other_op is another unrelated
661 * input that is not matched! but which is needed sometimes to check if AM
662 * for op1/op2 is legal.
663 * @p flags describes the supported modes of the operation in detail.
665 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
666 ir_node *op1, ir_node *op2, ir_node *other_op,
669 ia32_address_t *addr = &am->addr;
670 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
673 ir_mode *mode = get_irn_mode(op2);
675 unsigned commutative;
676 int use_am_and_immediates;
678 int mode_bits = get_mode_size_bits(mode);
680 memset(am, 0, sizeof(am[0]));
682 commutative = (flags & match_commutative) != 0;
683 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
684 use_am = (flags & match_am) != 0;
685 use_immediate = (flags & match_immediate) != 0;
686 assert(!use_am_and_immediates || use_immediate);
689 assert(!commutative || op1 != NULL);
690 assert(use_am || !(flags & match_8bit_am));
691 assert(use_am || !(flags & match_16bit_am));
694 if (! (flags & match_8bit_am))
696 /* we don't automatically add upconvs yet */
697 assert((flags & match_mode_neutral) || (flags & match_8bit));
698 } else if(mode_bits == 16) {
699 if(! (flags & match_16bit_am))
701 /* we don't automatically add upconvs yet */
702 assert((flags & match_mode_neutral) || (flags & match_16bit));
705 /* we can simply skip downconvs for mode neutral nodes: the upper bits
706 * can be random for these operations */
707 if(flags & match_mode_neutral) {
708 op2 = ia32_skip_downconv(op2);
710 op1 = ia32_skip_downconv(op1);
714 /* match immediates. firm nodes are normalized: constants are always on the
717 if(! (flags & match_try_am) && use_immediate) {
718 new_op2 = try_create_Immediate(op2, 0);
722 && use_am && ia32_use_source_address_mode(block, op2, op1, other_op)) {
723 build_address(am, op2);
724 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
725 if(mode_is_float(mode)) {
726 new_op2 = ia32_new_NoReg_vfp(env_cg);
730 am->op_type = ia32_AddrModeS;
731 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
733 && ia32_use_source_address_mode(block, op1, op2, other_op)) {
735 build_address(am, op1);
737 if(mode_is_float(mode)) {
738 noreg = ia32_new_NoReg_vfp(env_cg);
743 if(new_op2 != NULL) {
746 new_op1 = be_transform_node(op2);
748 am->ins_permuted = 1;
750 am->op_type = ia32_AddrModeS;
752 if(flags & match_try_am) {
755 am->op_type = ia32_Normal;
759 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
761 new_op2 = be_transform_node(op2);
762 am->op_type = ia32_Normal;
763 am->ls_mode = get_irn_mode(op2);
764 if(flags & match_mode_neutral)
765 am->ls_mode = mode_Iu;
767 if(addr->base == NULL)
768 addr->base = noreg_gp;
769 if(addr->index == NULL)
770 addr->index = noreg_gp;
771 if(addr->mem == NULL)
772 addr->mem = new_NoMem();
774 am->new_op1 = new_op1;
775 am->new_op2 = new_op2;
776 am->commutative = commutative;
779 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
781 ir_graph *irg = current_ir_graph;
785 if(am->mem_proj == NULL)
788 /* we have to create a mode_T so the old MemProj can attach to us */
789 mode = get_irn_mode(node);
790 load = get_Proj_pred(am->mem_proj);
792 mark_irn_visited(load);
793 be_set_transformed_node(load, node);
796 set_irn_mode(node, mode_T);
797 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
804 * Construct a standard binary operation, set AM and immediate if required.
806 * @param op1 The first operand
807 * @param op2 The second operand
808 * @param func The node constructor function
809 * @return The constructed ia32 node.
811 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
812 construct_binop_func *func, match_flags_t flags)
814 ir_node *block = get_nodes_block(node);
815 ir_node *new_block = be_transform_node(block);
816 ir_graph *irg = current_ir_graph;
817 dbg_info *dbgi = get_irn_dbg_info(node);
819 ia32_address_mode_t am;
820 ia32_address_t *addr = &am.addr;
822 match_arguments(&am, block, op1, op2, NULL, flags);
824 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
825 am.new_op1, am.new_op2);
826 set_am_attributes(new_node, &am);
827 /* we can't use source address mode anymore when using immediates */
828 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
829 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
830 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
832 new_node = fix_mem_proj(new_node, &am);
839 n_ia32_l_binop_right,
840 n_ia32_l_binop_eflags
842 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
843 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
844 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
845 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left)
846 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right)
847 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
850 * Construct a binary operation which also consumes the eflags.
852 * @param node The node to transform
853 * @param func The node constructor function
854 * @param flags The match flags
855 * @return The constructor ia32 node
857 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
860 ir_node *src_block = get_nodes_block(node);
861 ir_node *block = be_transform_node(src_block);
862 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
863 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
864 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
865 ir_node *new_eflags = be_transform_node(eflags);
866 ir_graph *irg = current_ir_graph;
867 dbg_info *dbgi = get_irn_dbg_info(node);
869 ia32_address_mode_t am;
870 ia32_address_t *addr = &am.addr;
872 match_arguments(&am, src_block, op1, op2, NULL, flags);
874 new_node = func(dbgi, irg, block, addr->base, addr->index,
875 addr->mem, am.new_op1, am.new_op2, new_eflags);
876 set_am_attributes(new_node, &am);
877 /* we can't use source address mode anymore when using immediates */
878 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
879 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
880 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
882 new_node = fix_mem_proj(new_node, &am);
887 static ir_node *get_fpcw(void)
890 if(initial_fpcw != NULL)
893 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
894 &ia32_fp_cw_regs[REG_FPCW]);
895 initial_fpcw = be_transform_node(fpcw);
901 * Construct a standard binary operation, set AM and immediate if required.
903 * @param op1 The first operand
904 * @param op2 The second operand
905 * @param func The node constructor function
906 * @return The constructed ia32 node.
908 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
909 construct_binop_float_func *func,
912 ir_graph *irg = current_ir_graph;
913 dbg_info *dbgi = get_irn_dbg_info(node);
914 ir_node *block = get_nodes_block(node);
915 ir_node *new_block = be_transform_node(block);
916 ir_mode *mode = get_irn_mode(node);
918 ia32_address_mode_t am;
919 ia32_address_t *addr = &am.addr;
921 /* cannot use addresmode with long double on x87 */
922 if (get_mode_size_bits(mode) > 64)
925 match_arguments(&am, block, op1, op2, NULL, flags);
927 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
928 am.new_op1, am.new_op2, get_fpcw());
929 set_am_attributes(new_node, &am);
931 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
933 new_node = fix_mem_proj(new_node, &am);
939 * Construct a shift/rotate binary operation, sets AM and immediate if required.
941 * @param op1 The first operand
942 * @param op2 The second operand
943 * @param func The node constructor function
944 * @return The constructed ia32 node.
946 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
947 construct_shift_func *func,
950 dbg_info *dbgi = get_irn_dbg_info(node);
951 ir_graph *irg = current_ir_graph;
952 ir_node *block = get_nodes_block(node);
953 ir_node *new_block = be_transform_node(block);
958 assert(! mode_is_float(get_irn_mode(node)));
959 assert(flags & match_immediate);
960 assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
962 if(flags & match_mode_neutral) {
963 op1 = ia32_skip_downconv(op1);
965 new_op1 = be_transform_node(op1);
967 /* the shift amount can be any mode that is bigger than 5 bits, since all
968 * other bits are ignored anyway */
969 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
970 op2 = get_Conv_op(op2);
971 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
973 new_op2 = create_immediate_or_transform(op2, 0);
975 new_node = func(dbgi, irg, new_block, new_op1, new_op2);
976 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
978 /* lowered shift instruction may have a dependency operand, handle it here */
979 if (get_irn_arity(node) == 3) {
980 /* we have a dependency */
981 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
982 add_irn_dep(new_node, new_dep);
990 * Construct a standard unary operation, set AM and immediate if required.
992 * @param op The operand
993 * @param func The node constructor function
994 * @return The constructed ia32 node.
996 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
999 ir_graph *irg = current_ir_graph;
1000 dbg_info *dbgi = get_irn_dbg_info(node);
1001 ir_node *block = get_nodes_block(node);
1002 ir_node *new_block = be_transform_node(block);
1006 assert(flags == 0 || flags == match_mode_neutral);
1007 if(flags & match_mode_neutral) {
1008 op = ia32_skip_downconv(op);
1011 new_op = be_transform_node(op);
1012 new_node = func(dbgi, irg, new_block, new_op);
1014 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1019 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
1020 ia32_address_t *addr)
1022 ir_graph *irg = current_ir_graph;
1023 ir_node *base = addr->base;
1024 ir_node *index = addr->index;
1028 base = ia32_new_NoReg_gp(env_cg);
1030 base = be_transform_node(base);
1034 index = ia32_new_NoReg_gp(env_cg);
1036 index = be_transform_node(index);
1039 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1040 set_address(res, addr);
1045 static int am_has_immediates(const ia32_address_t *addr)
1047 return addr->offset != 0 || addr->symconst_ent != NULL
1048 || addr->frame_entity || addr->use_frame;
1052 * Creates an ia32 Add.
1054 * @return the created ia32 Add node
1056 static ir_node *gen_Add(ir_node *node) {
1057 ir_graph *irg = current_ir_graph;
1058 dbg_info *dbgi = get_irn_dbg_info(node);
1059 ir_node *block = get_nodes_block(node);
1060 ir_node *new_block = be_transform_node(block);
1061 ir_node *op1 = get_Add_left(node);
1062 ir_node *op2 = get_Add_right(node);
1063 ir_mode *mode = get_irn_mode(node);
1065 ir_node *add_immediate_op;
1066 ia32_address_t addr;
1067 ia32_address_mode_t am;
1069 if (mode_is_float(mode)) {
1070 if (ia32_cg_config.use_sse2)
1071 return gen_binop(node, op1, op2, new_rd_ia32_xAdd,
1072 match_commutative | match_am);
1074 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd,
1075 match_commutative | match_am);
1078 ia32_mark_non_am(node);
1080 op2 = ia32_skip_downconv(op2);
1081 op1 = ia32_skip_downconv(op1);
1085 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1086 * 1. Add with immediate -> Lea
1087 * 2. Add with possible source address mode -> Add
1088 * 3. Otherwise -> Lea
1090 memset(&addr, 0, sizeof(addr));
1091 ia32_create_address_mode(&addr, node, /*force=*/1);
1092 add_immediate_op = NULL;
1094 if(addr.base == NULL && addr.index == NULL) {
1095 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
1096 addr.symconst_sign, addr.offset);
1097 add_irn_dep(new_node, get_irg_frame(irg));
1098 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1101 /* add with immediate? */
1102 if(addr.index == NULL) {
1103 add_immediate_op = addr.base;
1104 } else if(addr.base == NULL && addr.scale == 0) {
1105 add_immediate_op = addr.index;
1108 if(add_immediate_op != NULL) {
1109 if(!am_has_immediates(&addr)) {
1110 #ifdef DEBUG_libfirm
1111 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1114 return be_transform_node(add_immediate_op);
1117 new_node = create_lea_from_address(dbgi, new_block, &addr);
1118 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1122 /* test if we can use source address mode */
1123 match_arguments(&am, block, op1, op2, NULL, match_commutative
1124 | match_mode_neutral | match_am | match_immediate | match_try_am);
1126 /* construct an Add with source address mode */
1127 if (am.op_type == ia32_AddrModeS) {
1128 ia32_address_t *am_addr = &am.addr;
1129 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
1130 am_addr->index, am_addr->mem, am.new_op1,
1132 set_am_attributes(new_node, &am);
1133 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1135 new_node = fix_mem_proj(new_node, &am);
1140 /* otherwise construct a lea */
1141 new_node = create_lea_from_address(dbgi, new_block, &addr);
1142 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1147 * Creates an ia32 Mul.
1149 * @return the created ia32 Mul node
1151 static ir_node *gen_Mul(ir_node *node) {
1152 ir_node *op1 = get_Mul_left(node);
1153 ir_node *op2 = get_Mul_right(node);
1154 ir_mode *mode = get_irn_mode(node);
1156 if (mode_is_float(mode)) {
1157 if (ia32_cg_config.use_sse2)
1158 return gen_binop(node, op1, op2, new_rd_ia32_xMul,
1159 match_commutative | match_am);
1161 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul,
1162 match_commutative | match_am);
1165 /* for the lower 32bit of the result it doesn't matter whether we use
1166 * signed or unsigned multiplication so we use IMul as it has fewer
1168 return gen_binop(node, op1, op2, new_rd_ia32_IMul,
1169 match_commutative | match_am | match_mode_neutral |
1170 match_immediate | match_am_and_immediates);
1174 * Creates an ia32 Mulh.
1175 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1176 * this result while Mul returns the lower 32 bit.
1178 * @return the created ia32 Mulh node
1180 static ir_node *gen_Mulh(ir_node *node)
1182 ir_node *block = get_nodes_block(node);
1183 ir_node *new_block = be_transform_node(block);
1184 ir_graph *irg = current_ir_graph;
1185 dbg_info *dbgi = get_irn_dbg_info(node);
1186 ir_mode *mode = get_irn_mode(node);
1187 ir_node *op1 = get_Mulh_left(node);
1188 ir_node *op2 = get_Mulh_right(node);
1189 ir_node *proj_res_high;
1191 ia32_address_mode_t am;
1192 ia32_address_t *addr = &am.addr;
1194 assert(!mode_is_float(mode) && "Mulh with float not supported");
1195 assert(get_mode_size_bits(mode) == 32);
1197 match_arguments(&am, block, op1, op2, NULL, match_commutative | match_am);
1199 if (mode_is_signed(mode)) {
1200 new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base,
1201 addr->index, addr->mem, am.new_op1,
1204 new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base,
1205 addr->index, addr->mem, am.new_op1,
1209 set_am_attributes(new_node, &am);
1210 /* we can't use source address mode anymore when using immediates */
1211 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
1212 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
1213 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1215 assert(get_irn_mode(new_node) == mode_T);
1217 fix_mem_proj(new_node, &am);
1219 assert(pn_ia32_IMul1OP_res_high == pn_ia32_Mul_res_high);
1220 proj_res_high = new_rd_Proj(dbgi, irg, block, new_node,
1221 mode_Iu, pn_ia32_IMul1OP_res_high);
1223 return proj_res_high;
1229 * Creates an ia32 And.
1231 * @return The created ia32 And node
1233 static ir_node *gen_And(ir_node *node) {
1234 ir_node *op1 = get_And_left(node);
1235 ir_node *op2 = get_And_right(node);
1236 assert(! mode_is_float(get_irn_mode(node)));
1238 /* is it a zero extension? */
1239 if (is_Const(op2)) {
1240 tarval *tv = get_Const_tarval(op2);
1241 long v = get_tarval_long(tv);
1243 if (v == 0xFF || v == 0xFFFF) {
1244 dbg_info *dbgi = get_irn_dbg_info(node);
1245 ir_node *block = get_nodes_block(node);
1252 assert(v == 0xFFFF);
1255 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1261 return gen_binop(node, op1, op2, new_rd_ia32_And,
1262 match_commutative | match_mode_neutral | match_am
1269 * Creates an ia32 Or.
1271 * @return The created ia32 Or node
1273 static ir_node *gen_Or(ir_node *node) {
1274 ir_node *op1 = get_Or_left(node);
1275 ir_node *op2 = get_Or_right(node);
1277 assert (! mode_is_float(get_irn_mode(node)));
1278 return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative
1279 | match_mode_neutral | match_am | match_immediate);
1285 * Creates an ia32 Eor.
1287 * @return The created ia32 Eor node
1289 static ir_node *gen_Eor(ir_node *node) {
1290 ir_node *op1 = get_Eor_left(node);
1291 ir_node *op2 = get_Eor_right(node);
1293 assert(! mode_is_float(get_irn_mode(node)));
1294 return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative
1295 | match_mode_neutral | match_am | match_immediate);
1300 * Creates an ia32 Sub.
1302 * @return The created ia32 Sub node
1304 static ir_node *gen_Sub(ir_node *node) {
1305 ir_node *op1 = get_Sub_left(node);
1306 ir_node *op2 = get_Sub_right(node);
1307 ir_mode *mode = get_irn_mode(node);
1309 if (mode_is_float(mode)) {
1310 if (ia32_cg_config.use_sse2)
1311 return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am);
1313 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub,
1318 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1322 return gen_binop(node, op1, op2, new_rd_ia32_Sub, match_mode_neutral
1323 | match_am | match_immediate);
1327 * Generates an ia32 DivMod with additional infrastructure for the
1328 * register allocator if needed.
1330 static ir_node *create_Div(ir_node *node)
1332 ir_graph *irg = current_ir_graph;
1333 dbg_info *dbgi = get_irn_dbg_info(node);
1334 ir_node *block = get_nodes_block(node);
1335 ir_node *new_block = be_transform_node(block);
1342 ir_node *sign_extension;
1343 ia32_address_mode_t am;
1344 ia32_address_t *addr = &am.addr;
1346 /* the upper bits have random contents for smaller modes */
1347 switch (get_irn_opcode(node)) {
1349 op1 = get_Div_left(node);
1350 op2 = get_Div_right(node);
1351 mem = get_Div_mem(node);
1352 mode = get_Div_resmode(node);
1355 op1 = get_Mod_left(node);
1356 op2 = get_Mod_right(node);
1357 mem = get_Mod_mem(node);
1358 mode = get_Mod_resmode(node);
1361 op1 = get_DivMod_left(node);
1362 op2 = get_DivMod_right(node);
1363 mem = get_DivMod_mem(node);
1364 mode = get_DivMod_resmode(node);
1367 panic("invalid divmod node %+F", node);
1370 match_arguments(&am, block, op1, op2, NULL, match_am);
1372 if(!is_NoMem(mem)) {
1373 new_mem = be_transform_node(mem);
1374 if(!is_NoMem(addr->mem)) {
1378 new_mem = new_rd_Sync(dbgi, irg, new_block, 2, in);
1381 new_mem = addr->mem;
1384 if (mode_is_signed(mode)) {
1385 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1386 add_irn_dep(produceval, get_irg_frame(irg));
1387 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1,
1390 new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base,
1391 addr->index, new_mem, am.new_op1,
1392 sign_extension, am.new_op2);
1394 sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0);
1395 add_irn_dep(sign_extension, get_irg_frame(irg));
1397 new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base,
1398 addr->index, new_mem, am.new_op1,
1399 sign_extension, am.new_op2);
1402 set_irn_pinned(new_node, get_irn_pinned(node));
1404 set_am_attributes(new_node, &am);
1405 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1407 new_node = fix_mem_proj(new_node, &am);
1413 static ir_node *gen_Mod(ir_node *node) {
1414 return create_Div(node);
1417 static ir_node *gen_Div(ir_node *node) {
1418 return create_Div(node);
1421 static ir_node *gen_DivMod(ir_node *node) {
1422 return create_Div(node);
1428 * Creates an ia32 floating Div.
1430 * @return The created ia32 xDiv node
1432 static ir_node *gen_Quot(ir_node *node)
1434 ir_node *op1 = get_Quot_left(node);
1435 ir_node *op2 = get_Quot_right(node);
1437 if (ia32_cg_config.use_sse2) {
1438 return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am);
1440 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, match_am);
1446 * Creates an ia32 Shl.
1448 * @return The created ia32 Shl node
1450 static ir_node *gen_Shl(ir_node *node) {
1451 ir_node *left = get_Shl_left(node);
1452 ir_node *right = get_Shl_right(node);
1454 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
1455 match_mode_neutral | match_immediate);
1459 * Creates an ia32 Shr.
1461 * @return The created ia32 Shr node
1463 static ir_node *gen_Shr(ir_node *node) {
1464 ir_node *left = get_Shr_left(node);
1465 ir_node *right = get_Shr_right(node);
1467 return gen_shift_binop(node, left, right, new_rd_ia32_Shr, match_immediate);
1473 * Creates an ia32 Sar.
1475 * @return The created ia32 Shrs node
1477 static ir_node *gen_Shrs(ir_node *node) {
1478 ir_node *left = get_Shrs_left(node);
1479 ir_node *right = get_Shrs_right(node);
1480 ir_mode *mode = get_irn_mode(node);
1482 if(is_Const(right) && mode == mode_Is) {
1483 tarval *tv = get_Const_tarval(right);
1484 long val = get_tarval_long(tv);
1486 /* this is a sign extension */
1487 ir_graph *irg = current_ir_graph;
1488 dbg_info *dbgi = get_irn_dbg_info(node);
1489 ir_node *block = be_transform_node(get_nodes_block(node));
1491 ir_node *new_op = be_transform_node(op);
1492 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1493 add_irn_dep(pval, get_irg_frame(irg));
1495 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1499 /* 8 or 16 bit sign extension? */
1500 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1501 ir_node *shl_left = get_Shl_left(left);
1502 ir_node *shl_right = get_Shl_right(left);
1503 if(is_Const(shl_right)) {
1504 tarval *tv1 = get_Const_tarval(right);
1505 tarval *tv2 = get_Const_tarval(shl_right);
1506 if(tv1 == tv2 && tarval_is_long(tv1)) {
1507 long val = get_tarval_long(tv1);
1508 if(val == 16 || val == 24) {
1509 dbg_info *dbgi = get_irn_dbg_info(node);
1510 ir_node *block = get_nodes_block(node);
1520 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1529 return gen_shift_binop(node, left, right, new_rd_ia32_Sar, match_immediate);
1535 * Creates an ia32 RotL.
1537 * @param op1 The first operator
1538 * @param op2 The second operator
1539 * @return The created ia32 RotL node
1541 static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) {
1542 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate);
1548 * Creates an ia32 RotR.
1549 * NOTE: There is no RotR with immediate because this would always be a RotL
1550 * "imm-mode_size_bits" which can be pre-calculated.
1552 * @param op1 The first operator
1553 * @param op2 The second operator
1554 * @return The created ia32 RotR node
1556 static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) {
1557 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate);
1563 * Creates an ia32 RotR or RotL (depending on the found pattern).
1565 * @return The created ia32 RotL or RotR node
1567 static ir_node *gen_Rot(ir_node *node) {
1568 ir_node *rotate = NULL;
1569 ir_node *op1 = get_Rot_left(node);
1570 ir_node *op2 = get_Rot_right(node);
1572 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1573 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1574 that means we can create a RotR instead of an Add and a RotL */
1576 if (get_irn_op(op2) == op_Add) {
1578 ir_node *left = get_Add_left(add);
1579 ir_node *right = get_Add_right(add);
1580 if (is_Const(right)) {
1581 tarval *tv = get_Const_tarval(right);
1582 ir_mode *mode = get_irn_mode(node);
1583 long bits = get_mode_size_bits(mode);
1585 if (get_irn_op(left) == op_Minus &&
1586 tarval_is_long(tv) &&
1587 get_tarval_long(tv) == bits &&
1590 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1591 rotate = gen_RotR(node, op1, get_Minus_op(left));
1596 if (rotate == NULL) {
1597 rotate = gen_RotL(node, op1, op2);
1606 * Transforms a Minus node.
1608 * @return The created ia32 Minus node
1610 static ir_node *gen_Minus(ir_node *node)
1612 ir_node *op = get_Minus_op(node);
1613 ir_node *block = be_transform_node(get_nodes_block(node));
1614 ir_graph *irg = current_ir_graph;
1615 dbg_info *dbgi = get_irn_dbg_info(node);
1616 ir_mode *mode = get_irn_mode(node);
1621 if (mode_is_float(mode)) {
1622 ir_node *new_op = be_transform_node(op);
1623 if (ia32_cg_config.use_sse2) {
1624 /* TODO: non-optimal... if we have many xXors, then we should
1625 * rather create a load for the const and use that instead of
1626 * several AM nodes... */
1627 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1628 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1629 ir_node *nomem = new_rd_NoMem(irg);
1631 new_node = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp,
1632 nomem, new_op, noreg_xmm);
1634 size = get_mode_size_bits(mode);
1635 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1637 set_ia32_am_sc(new_node, ent);
1638 set_ia32_op_type(new_node, ia32_AddrModeS);
1639 set_ia32_ls_mode(new_node, mode);
1641 new_node = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1644 new_node = gen_unop(node, op, new_rd_ia32_Neg, match_mode_neutral);
1647 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1653 * Transforms a Not node.
1655 * @return The created ia32 Not node
1657 static ir_node *gen_Not(ir_node *node) {
1658 ir_node *op = get_Not_op(node);
1660 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1661 assert (! mode_is_float(get_irn_mode(node)));
1663 return gen_unop(node, op, new_rd_ia32_Not, match_mode_neutral);
1669 * Transforms an Abs node.
1671 * @return The created ia32 Abs node
1673 static ir_node *gen_Abs(ir_node *node)
1675 ir_node *block = get_nodes_block(node);
1676 ir_node *new_block = be_transform_node(block);
1677 ir_node *op = get_Abs_op(node);
1678 ir_graph *irg = current_ir_graph;
1679 dbg_info *dbgi = get_irn_dbg_info(node);
1680 ir_mode *mode = get_irn_mode(node);
1681 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1682 ir_node *nomem = new_NoMem();
1688 if (mode_is_float(mode)) {
1689 new_op = be_transform_node(op);
1691 if (ia32_cg_config.use_sse2) {
1692 ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg);
1693 new_node = new_rd_ia32_xAnd(dbgi,irg, new_block, noreg_gp, noreg_gp,
1694 nomem, new_op, noreg_fp);
1696 size = get_mode_size_bits(mode);
1697 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1699 set_ia32_am_sc(new_node, ent);
1701 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1703 set_ia32_op_type(new_node, ia32_AddrModeS);
1704 set_ia32_ls_mode(new_node, mode);
1706 new_node = new_rd_ia32_vfabs(dbgi, irg, new_block, new_op);
1707 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1710 ir_node *xor, *pval, *sign_extension;
1712 if (get_mode_size_bits(mode) == 32) {
1713 new_op = be_transform_node(op);
1715 new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node);
1718 pval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1719 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block,
1722 add_irn_dep(pval, get_irg_frame(irg));
1723 SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node));
1725 xor = new_rd_ia32_Xor(dbgi, irg, new_block, noreg_gp, noreg_gp,
1726 nomem, new_op, sign_extension);
1727 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1729 new_node = new_rd_ia32_Sub(dbgi, irg, new_block, noreg_gp, noreg_gp,
1730 nomem, xor, sign_extension);
1731 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1737 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
1739 ir_graph *irg = current_ir_graph;
1747 /* we have a Cmp as input */
1749 ir_node *pred = get_Proj_pred(node);
1751 flags = be_transform_node(pred);
1752 *pnc_out = get_Proj_proj(node);
1757 /* a mode_b value, we have to compare it against 0 */
1758 dbgi = get_irn_dbg_info(node);
1759 new_block = be_transform_node(get_nodes_block(node));
1760 new_op = be_transform_node(node);
1761 noreg = ia32_new_NoReg_gp(env_cg);
1762 nomem = new_NoMem();
1763 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
1764 new_op, new_op, 0, 0);
1765 *pnc_out = pn_Cmp_Lg;
1770 * Transforms a Load.
1772 * @return the created ia32 Load node
1774 static ir_node *gen_Load(ir_node *node) {
1775 ir_node *old_block = get_nodes_block(node);
1776 ir_node *block = be_transform_node(old_block);
1777 ir_node *ptr = get_Load_ptr(node);
1778 ir_node *mem = get_Load_mem(node);
1779 ir_node *new_mem = be_transform_node(mem);
1782 ir_graph *irg = current_ir_graph;
1783 dbg_info *dbgi = get_irn_dbg_info(node);
1784 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1785 ir_mode *mode = get_Load_mode(node);
1788 ia32_address_t addr;
1790 /* construct load address */
1791 memset(&addr, 0, sizeof(addr));
1792 ia32_create_address_mode(&addr, ptr, /*force=*/0);
1799 base = be_transform_node(base);
1805 index = be_transform_node(index);
1808 if (mode_is_float(mode)) {
1809 if (ia32_cg_config.use_sse2) {
1810 new_node = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1812 res_mode = mode_xmm;
1814 new_node = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1816 res_mode = mode_vfp;
1819 assert(mode != mode_b);
1821 /* create a conv node with address mode for smaller modes */
1822 if(get_mode_size_bits(mode) < 32) {
1823 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1824 new_mem, noreg, mode);
1826 new_node = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1831 set_irn_pinned(new_node, get_irn_pinned(node));
1832 set_ia32_op_type(new_node, ia32_AddrModeS);
1833 set_ia32_ls_mode(new_node, mode);
1834 set_address(new_node, &addr);
1836 if(get_irn_pinned(node) == op_pin_state_floats) {
1837 add_ia32_flags(new_node, arch_irn_flags_rematerializable);
1840 /* make sure we are scheduled behind the initial IncSP/Barrier
1841 * to avoid spills being placed before it
1843 if (block == get_irg_start_block(irg)) {
1844 add_irn_dep(new_node, get_irg_frame(irg));
1847 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1852 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1853 ir_node *ptr, ir_node *other)
1860 /* we only use address mode if we're the only user of the load */
1861 if(get_irn_n_edges(node) > 1)
1864 load = get_Proj_pred(node);
1867 if(get_nodes_block(load) != block)
1870 /* Store should be attached to the load */
1871 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1873 /* store should have the same pointer as the load */
1874 if(get_Load_ptr(load) != ptr)
1877 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1878 if(other != NULL && get_nodes_block(other) == block
1879 && heights_reachable_in_block(heights, other, load))
1885 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1886 ir_node *mem, ir_node *ptr, ir_mode *mode,
1887 construct_binop_dest_func *func,
1888 construct_binop_dest_func *func8bit,
1889 match_flags_t flags)
1891 ir_node *src_block = get_nodes_block(node);
1893 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1894 ir_graph *irg = current_ir_graph;
1899 ia32_address_mode_t am;
1900 ia32_address_t *addr = &am.addr;
1901 memset(&am, 0, sizeof(am));
1903 assert(flags & match_dest_am);
1904 assert(flags & match_immediate); /* there is no destam node without... */
1905 commutative = (flags & match_commutative) != 0;
1907 if(use_dest_am(src_block, op1, mem, ptr, op2)) {
1908 build_address(&am, op1);
1909 new_op = create_immediate_or_transform(op2, 0);
1910 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
1911 build_address(&am, op2);
1912 new_op = create_immediate_or_transform(op1, 0);
1917 if(addr->base == NULL)
1918 addr->base = noreg_gp;
1919 if(addr->index == NULL)
1920 addr->index = noreg_gp;
1921 if(addr->mem == NULL)
1922 addr->mem = new_NoMem();
1924 dbgi = get_irn_dbg_info(node);
1925 block = be_transform_node(src_block);
1926 if(get_mode_size_bits(mode) == 8) {
1927 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1930 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1933 set_address(new_node, addr);
1934 set_ia32_op_type(new_node, ia32_AddrModeD);
1935 set_ia32_ls_mode(new_node, mode);
1936 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1941 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1942 ir_node *ptr, ir_mode *mode,
1943 construct_unop_dest_func *func)
1945 ir_graph *irg = current_ir_graph;
1946 ir_node *src_block = get_nodes_block(node);
1950 ia32_address_mode_t am;
1951 ia32_address_t *addr = &am.addr;
1952 memset(&am, 0, sizeof(am));
1954 if(!use_dest_am(src_block, op, mem, ptr, NULL))
1957 build_address(&am, op);
1959 dbgi = get_irn_dbg_info(node);
1960 block = be_transform_node(src_block);
1961 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1962 set_address(new_node, addr);
1963 set_ia32_op_type(new_node, ia32_AddrModeD);
1964 set_ia32_ls_mode(new_node, mode);
1965 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1970 static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) {
1971 ir_mode *mode = get_irn_mode(node);
1972 ir_node *psi_true = get_Psi_val(node, 0);
1973 ir_node *psi_default = get_Psi_default(node);
1984 ia32_address_t addr;
1986 if(get_mode_size_bits(mode) != 8)
1989 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
1991 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
1997 build_address_ptr(&addr, ptr, mem);
1999 irg = current_ir_graph;
2000 dbgi = get_irn_dbg_info(node);
2001 block = get_nodes_block(node);
2002 new_block = be_transform_node(block);
2003 cond = get_Psi_cond(node, 0);
2004 flags = get_flags_node(cond, &pnc);
2005 new_mem = be_transform_node(mem);
2006 new_node = new_rd_ia32_SetMem(dbgi, irg, new_block, addr.base,
2007 addr.index, addr.mem, flags, pnc, negated);
2008 set_address(new_node, &addr);
2009 set_ia32_op_type(new_node, ia32_AddrModeD);
2010 set_ia32_ls_mode(new_node, mode);
2011 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2016 static ir_node *try_create_dest_am(ir_node *node) {
2017 ir_node *val = get_Store_value(node);
2018 ir_node *mem = get_Store_mem(node);
2019 ir_node *ptr = get_Store_ptr(node);
2020 ir_mode *mode = get_irn_mode(val);
2021 unsigned bits = get_mode_size_bits(mode);
2026 /* handle only GP modes for now... */
2027 if(!mode_needs_gp_reg(mode))
2031 /* store must be the only user of the val node */
2032 if(get_irn_n_edges(val) > 1)
2034 /* skip pointless convs */
2036 ir_node *conv_op = get_Conv_op(val);
2037 ir_mode *pred_mode = get_irn_mode(conv_op);
2038 if(pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
2046 /* value must be in the same block */
2047 if(get_nodes_block(node) != get_nodes_block(val))
2050 switch(get_irn_opcode(val)) {
2052 op1 = get_Add_left(val);
2053 op2 = get_Add_right(val);
2054 if(is_Const_1(op2)) {
2055 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2056 new_rd_ia32_IncMem);
2058 } else if(is_Const_Minus_1(op2)) {
2059 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2060 new_rd_ia32_DecMem);
2063 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2064 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit,
2065 match_dest_am | match_commutative |
2069 op1 = get_Sub_left(val);
2070 op2 = get_Sub_right(val);
2072 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
2075 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2076 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit,
2077 match_dest_am | match_immediate |
2081 op1 = get_And_left(val);
2082 op2 = get_And_right(val);
2083 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2084 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit,
2085 match_dest_am | match_commutative |
2089 op1 = get_Or_left(val);
2090 op2 = get_Or_right(val);
2091 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2092 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit,
2093 match_dest_am | match_commutative |
2097 op1 = get_Eor_left(val);
2098 op2 = get_Eor_right(val);
2099 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2100 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit,
2101 match_dest_am | match_commutative |
2105 op1 = get_Shl_left(val);
2106 op2 = get_Shl_right(val);
2107 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2108 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem,
2109 match_dest_am | match_immediate);
2112 op1 = get_Shr_left(val);
2113 op2 = get_Shr_right(val);
2114 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2115 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem,
2116 match_dest_am | match_immediate);
2119 op1 = get_Shrs_left(val);
2120 op2 = get_Shrs_right(val);
2121 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2122 new_rd_ia32_SarMem, new_rd_ia32_SarMem,
2123 match_dest_am | match_immediate);
2126 op1 = get_Rot_left(val);
2127 op2 = get_Rot_right(val);
2128 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2129 new_rd_ia32_RolMem, new_rd_ia32_RolMem,
2130 match_dest_am | match_immediate);
2132 /* TODO: match ROR patterns... */
2134 new_node = try_create_SetMem(val, ptr, mem);
2137 op1 = get_Minus_op(val);
2138 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
2141 /* should be lowered already */
2142 assert(mode != mode_b);
2143 op1 = get_Not_op(val);
2144 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
2150 if(new_node != NULL) {
2151 if(get_irn_pinned(new_node) != op_pin_state_pinned &&
2152 get_irn_pinned(node) == op_pin_state_pinned) {
2153 set_irn_pinned(new_node, op_pin_state_pinned);
2160 static int is_float_to_int32_conv(const ir_node *node)
2162 ir_mode *mode = get_irn_mode(node);
2166 if(get_mode_size_bits(mode) != 32 || !mode_needs_gp_reg(mode))
2171 conv_op = get_Conv_op(node);
2172 conv_mode = get_irn_mode(conv_op);
2174 if(!mode_is_float(conv_mode))
2181 * Transforms a Store.
2183 * @return the created ia32 Store node
2185 static ir_node *gen_Store(ir_node *node)
2187 ir_node *block = get_nodes_block(node);
2188 ir_node *new_block = be_transform_node(block);
2189 ir_node *ptr = get_Store_ptr(node);
2190 ir_node *val = get_Store_value(node);
2191 ir_node *mem = get_Store_mem(node);
2192 ir_graph *irg = current_ir_graph;
2193 dbg_info *dbgi = get_irn_dbg_info(node);
2194 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2195 ir_mode *mode = get_irn_mode(val);
2198 ia32_address_t addr;
2200 /* check for destination address mode */
2201 new_node = try_create_dest_am(node);
2202 if(new_node != NULL)
2205 /* construct store address */
2206 memset(&addr, 0, sizeof(addr));
2207 ia32_create_address_mode(&addr, ptr, /*force=*/0);
2209 if(addr.base == NULL) {
2212 addr.base = be_transform_node(addr.base);
2215 if(addr.index == NULL) {
2218 addr.index = be_transform_node(addr.index);
2220 addr.mem = be_transform_node(mem);
2222 if (mode_is_float(mode)) {
2223 /* convs (and strict-convs) before stores are unnecessary if the mode
2225 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2226 val = get_Conv_op(val);
2228 new_val = be_transform_node(val);
2229 if (ia32_cg_config.use_sse2) {
2230 new_node = new_rd_ia32_xStore(dbgi, irg, new_block, addr.base,
2231 addr.index, addr.mem, new_val);
2233 new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base,
2234 addr.index, addr.mem, new_val, mode);
2236 } else if(is_float_to_int32_conv(val)) {
2237 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
2238 val = get_Conv_op(val);
2240 /* convs (and strict-convs) before stores are unnecessary if the mode
2242 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2243 val = get_Conv_op(val);
2245 new_val = be_transform_node(val);
2247 new_node = new_rd_ia32_vfist(dbgi, irg, new_block, addr.base,
2248 addr.index, addr.mem, new_val, trunc_mode);
2250 new_val = create_immediate_or_transform(val, 0);
2251 assert(mode != mode_b);
2253 if (get_mode_size_bits(mode) == 8) {
2254 new_node = new_rd_ia32_Store8Bit(dbgi, irg, new_block, addr.base,
2255 addr.index, addr.mem, new_val);
2257 new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
2258 addr.index, addr.mem, new_val);
2262 set_irn_pinned(new_node, get_irn_pinned(node));
2263 set_ia32_op_type(new_node, ia32_AddrModeD);
2264 set_ia32_ls_mode(new_node, mode);
2266 set_address(new_node, &addr);
2267 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2272 static ir_node *create_Switch(ir_node *node)
2274 ir_graph *irg = current_ir_graph;
2275 dbg_info *dbgi = get_irn_dbg_info(node);
2276 ir_node *block = be_transform_node(get_nodes_block(node));
2277 ir_node *sel = get_Cond_selector(node);
2278 ir_node *new_sel = be_transform_node(sel);
2279 int switch_min = INT_MAX;
2280 int switch_max = INT_MIN;
2281 long default_pn = get_Cond_defaultProj(node);
2283 const ir_edge_t *edge;
2285 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2287 /* determine the smallest switch case value */
2288 foreach_out_edge(node, edge) {
2289 ir_node *proj = get_edge_src_irn(edge);
2290 long pn = get_Proj_proj(proj);
2291 if(pn == default_pn)
2300 if((unsigned) (switch_max - switch_min) > 256000) {
2301 panic("Size of switch %+F bigger than 256000", node);
2304 if (switch_min != 0) {
2305 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2307 /* if smallest switch case is not 0 we need an additional sub */
2308 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2309 add_ia32_am_offs_int(new_sel, -switch_min);
2310 set_ia32_op_type(new_sel, ia32_AddrModeS);
2312 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2315 new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel, default_pn);
2316 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2321 static ir_node *gen_Cond(ir_node *node) {
2322 ir_node *block = get_nodes_block(node);
2323 ir_node *new_block = be_transform_node(block);
2324 ir_graph *irg = current_ir_graph;
2325 dbg_info *dbgi = get_irn_dbg_info(node);
2326 ir_node *sel = get_Cond_selector(node);
2327 ir_mode *sel_mode = get_irn_mode(sel);
2328 ir_node *flags = NULL;
2332 if (sel_mode != mode_b) {
2333 return create_Switch(node);
2336 /* we get flags from a cmp */
2337 flags = get_flags_node(sel, &pnc);
2339 new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2340 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2348 * Transforms a CopyB node.
2350 * @return The transformed node.
2352 static ir_node *gen_CopyB(ir_node *node) {
2353 ir_node *block = be_transform_node(get_nodes_block(node));
2354 ir_node *src = get_CopyB_src(node);
2355 ir_node *new_src = be_transform_node(src);
2356 ir_node *dst = get_CopyB_dst(node);
2357 ir_node *new_dst = be_transform_node(dst);
2358 ir_node *mem = get_CopyB_mem(node);
2359 ir_node *new_mem = be_transform_node(mem);
2360 ir_node *res = NULL;
2361 ir_graph *irg = current_ir_graph;
2362 dbg_info *dbgi = get_irn_dbg_info(node);
2363 int size = get_type_size_bytes(get_CopyB_type(node));
2366 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2367 /* then we need the size explicitly in ECX. */
2368 if (size >= 32 * 4) {
2369 rem = size & 0x3; /* size % 4 */
2372 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2373 add_irn_dep(res, get_irg_frame(irg));
2375 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
2378 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2381 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
2384 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2389 static ir_node *gen_be_Copy(ir_node *node)
2391 ir_node *new_node = be_duplicate_node(node);
2392 ir_mode *mode = get_irn_mode(new_node);
2394 if (mode_needs_gp_reg(mode)) {
2395 set_irn_mode(new_node, mode_Iu);
2401 static ir_node *create_Fucom(ir_node *node)
2403 ir_graph *irg = current_ir_graph;
2404 dbg_info *dbgi = get_irn_dbg_info(node);
2405 ir_node *block = get_nodes_block(node);
2406 ir_node *new_block = be_transform_node(block);
2407 ir_node *left = get_Cmp_left(node);
2408 ir_node *new_left = be_transform_node(left);
2409 ir_node *right = get_Cmp_right(node);
2413 if(ia32_cg_config.use_fucomi) {
2414 new_right = be_transform_node(right);
2415 new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left,
2417 set_ia32_commutative(new_node);
2418 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2420 if(ia32_cg_config.use_ftst && is_Const_0(right)) {
2421 new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left,
2424 new_right = be_transform_node(right);
2425 new_node = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2429 set_ia32_commutative(new_node);
2431 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2433 new_node = new_rd_ia32_Sahf(dbgi, irg, new_block, new_node);
2434 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2440 static ir_node *create_Ucomi(ir_node *node)
2442 ir_graph *irg = current_ir_graph;
2443 dbg_info *dbgi = get_irn_dbg_info(node);
2444 ir_node *src_block = get_nodes_block(node);
2445 ir_node *new_block = be_transform_node(src_block);
2446 ir_node *left = get_Cmp_left(node);
2447 ir_node *right = get_Cmp_right(node);
2449 ia32_address_mode_t am;
2450 ia32_address_t *addr = &am.addr;
2452 match_arguments(&am, src_block, left, right, NULL,
2453 match_commutative | match_am);
2455 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2456 addr->mem, am.new_op1, am.new_op2,
2458 set_am_attributes(new_node, &am);
2460 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2462 new_node = fix_mem_proj(new_node, &am);
2468 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2469 * to fold an and into a test node
2471 static int can_fold_test_and(ir_node *node)
2473 const ir_edge_t *edge;
2475 /** we can only have eq and lg projs */
2476 foreach_out_edge(node, edge) {
2477 ir_node *proj = get_edge_src_irn(edge);
2478 pn_Cmp pnc = get_Proj_proj(proj);
2479 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2486 static ir_node *gen_Cmp(ir_node *node)
2488 ir_graph *irg = current_ir_graph;
2489 dbg_info *dbgi = get_irn_dbg_info(node);
2490 ir_node *block = get_nodes_block(node);
2491 ir_node *new_block = be_transform_node(block);
2492 ir_node *left = get_Cmp_left(node);
2493 ir_node *right = get_Cmp_right(node);
2494 ir_mode *cmp_mode = get_irn_mode(left);
2496 ia32_address_mode_t am;
2497 ia32_address_t *addr = &am.addr;
2500 if(mode_is_float(cmp_mode)) {
2501 if (ia32_cg_config.use_sse2) {
2502 return create_Ucomi(node);
2504 return create_Fucom(node);
2508 assert(mode_needs_gp_reg(cmp_mode));
2510 /* we prefer the Test instruction where possible except cases where
2511 * we can use SourceAM */
2512 cmp_unsigned = !mode_is_signed(cmp_mode);
2513 if (is_Const_0(right)) {
2515 get_irn_n_edges(left) == 1 &&
2516 can_fold_test_and(node)) {
2517 /* Test(and_left, and_right) */
2518 ir_node *and_left = get_And_left(left);
2519 ir_node *and_right = get_And_right(left);
2520 ir_mode *mode = get_irn_mode(and_left);
2522 match_arguments(&am, block, and_left, and_right, NULL,
2524 match_am | match_8bit_am | match_16bit_am |
2525 match_am_and_immediates | match_immediate |
2526 match_8bit | match_16bit);
2527 if (get_mode_size_bits(mode) == 8) {
2528 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2529 addr->index, addr->mem, am.new_op1,
2530 am.new_op2, am.ins_permuted,
2533 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2534 addr->index, addr->mem, am.new_op1,
2535 am.new_op2, am.ins_permuted, cmp_unsigned);
2538 match_arguments(&am, block, NULL, left, NULL,
2539 match_am | match_8bit_am | match_16bit_am |
2540 match_8bit | match_16bit);
2541 if (am.op_type == ia32_AddrModeS) {
2543 ir_node *imm_zero = try_create_Immediate(right, 0);
2544 if (get_mode_size_bits(cmp_mode) == 8) {
2545 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2546 addr->index, addr->mem, am.new_op2,
2547 imm_zero, am.ins_permuted,
2550 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2551 addr->index, addr->mem, am.new_op2,
2552 imm_zero, am.ins_permuted, cmp_unsigned);
2555 /* Test(left, left) */
2556 if (get_mode_size_bits(cmp_mode) == 8) {
2557 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2558 addr->index, addr->mem, am.new_op2,
2559 am.new_op2, am.ins_permuted,
2562 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2563 addr->index, addr->mem, am.new_op2,
2564 am.new_op2, am.ins_permuted,
2570 /* Cmp(left, right) */
2571 match_arguments(&am, block, left, right, NULL,
2572 match_commutative | match_am | match_8bit_am |
2573 match_16bit_am | match_am_and_immediates |
2574 match_immediate | match_8bit | match_16bit);
2575 if (get_mode_size_bits(cmp_mode) == 8) {
2576 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2577 addr->index, addr->mem, am.new_op1,
2578 am.new_op2, am.ins_permuted,
2581 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2582 addr->index, addr->mem, am.new_op1,
2583 am.new_op2, am.ins_permuted, cmp_unsigned);
2586 set_am_attributes(new_node, &am);
2587 assert(cmp_mode != NULL);
2588 set_ia32_ls_mode(new_node, cmp_mode);
2590 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2592 new_node = fix_mem_proj(new_node, &am);
2597 static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags,
2600 ir_graph *irg = current_ir_graph;
2601 dbg_info *dbgi = get_irn_dbg_info(node);
2602 ir_node *block = get_nodes_block(node);
2603 ir_node *new_block = be_transform_node(block);
2604 ir_node *val_true = get_Psi_val(node, 0);
2605 ir_node *val_false = get_Psi_default(node);
2607 match_flags_t match_flags;
2608 ia32_address_mode_t am;
2609 ia32_address_t *addr;
2611 assert(ia32_cg_config.use_cmov);
2612 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2616 match_flags = match_commutative | match_am | match_16bit_am |
2619 match_arguments(&am, block, val_false, val_true, flags, match_flags);
2621 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2622 addr->mem, am.new_op1, am.new_op2, new_flags,
2623 am.ins_permuted, pnc);
2624 set_am_attributes(new_node, &am);
2626 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2628 new_node = fix_mem_proj(new_node, &am);
2635 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2636 ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
2639 ir_graph *irg = current_ir_graph;
2640 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2641 ir_node *nomem = new_NoMem();
2642 ir_mode *mode = get_irn_mode(orig_node);
2645 new_node = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
2646 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2648 /* we might need to conv the result up */
2649 if(get_mode_size_bits(mode) > 8) {
2650 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2651 nomem, new_node, mode_Bu);
2652 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2659 * Transforms a Psi node into CMov.
2661 * @return The transformed node.
2663 static ir_node *gen_Psi(ir_node *node)
2665 dbg_info *dbgi = get_irn_dbg_info(node);
2666 ir_node *block = get_nodes_block(node);
2667 ir_node *new_block = be_transform_node(block);
2668 ir_node *psi_true = get_Psi_val(node, 0);
2669 ir_node *psi_default = get_Psi_default(node);
2670 ir_node *cond = get_Psi_cond(node, 0);
2671 ir_node *flags = NULL;
2675 assert(get_Psi_n_conds(node) == 1);
2676 assert(get_irn_mode(cond) == mode_b);
2677 assert(mode_needs_gp_reg(get_irn_mode(node)));
2679 flags = get_flags_node(cond, &pnc);
2681 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2682 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
2683 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2684 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
2686 new_node = create_CMov(node, cond, flags, pnc);
2693 * Create a conversion from x87 state register to general purpose.
2695 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2696 ir_node *block = be_transform_node(get_nodes_block(node));
2697 ir_node *op = get_Conv_op(node);
2698 ir_node *new_op = be_transform_node(op);
2699 ia32_code_gen_t *cg = env_cg;
2700 ir_graph *irg = current_ir_graph;
2701 dbg_info *dbgi = get_irn_dbg_info(node);
2702 ir_node *noreg = ia32_new_NoReg_gp(cg);
2703 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2704 ir_mode *mode = get_irn_mode(node);
2705 ir_node *fist, *load;
2708 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2709 new_NoMem(), new_op, trunc_mode);
2711 set_irn_pinned(fist, op_pin_state_floats);
2712 set_ia32_use_frame(fist);
2713 set_ia32_op_type(fist, ia32_AddrModeD);
2715 assert(get_mode_size_bits(mode) <= 32);
2716 /* exception we can only store signed 32 bit integers, so for unsigned
2717 we store a 64bit (signed) integer and load the lower bits */
2718 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2719 set_ia32_ls_mode(fist, mode_Ls);
2721 set_ia32_ls_mode(fist, mode_Is);
2723 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2726 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2728 set_irn_pinned(load, op_pin_state_floats);
2729 set_ia32_use_frame(load);
2730 set_ia32_op_type(load, ia32_AddrModeS);
2731 set_ia32_ls_mode(load, mode_Is);
2732 if(get_ia32_ls_mode(fist) == mode_Ls) {
2733 ia32_attr_t *attr = get_ia32_attr(load);
2734 attr->data.need_64bit_stackent = 1;
2736 ia32_attr_t *attr = get_ia32_attr(load);
2737 attr->data.need_32bit_stackent = 1;
2739 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2741 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2745 * Creates a x87 strict Conv by placing a Sore and a Load
2747 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2749 ir_node *block = get_nodes_block(node);
2750 ir_graph *irg = current_ir_graph;
2751 dbg_info *dbgi = get_irn_dbg_info(node);
2752 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2753 ir_node *nomem = new_NoMem();
2754 ir_node *frame = get_irg_frame(irg);
2755 ir_node *store, *load;
2758 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2760 set_ia32_use_frame(store);
2761 set_ia32_op_type(store, ia32_AddrModeD);
2762 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2764 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2766 set_ia32_use_frame(load);
2767 set_ia32_op_type(load, ia32_AddrModeS);
2768 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2770 new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2774 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2776 ir_graph *irg = current_ir_graph;
2777 ir_node *start_block = get_irg_start_block(irg);
2778 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2779 symconst, symconst_sign, val);
2780 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2786 * Create a conversion from general purpose to x87 register
2788 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2789 ir_node *src_block = get_nodes_block(node);
2790 ir_node *block = be_transform_node(src_block);
2791 ir_graph *irg = current_ir_graph;
2792 dbg_info *dbgi = get_irn_dbg_info(node);
2793 ir_node *op = get_Conv_op(node);
2794 ir_node *new_op = NULL;
2798 ir_mode *store_mode;
2804 /* fild can use source AM if the operand is a signed 32bit integer */
2805 if (src_mode == mode_Is) {
2806 ia32_address_mode_t am;
2808 match_arguments(&am, src_block, NULL, op, NULL,
2809 match_am | match_try_am);
2810 if (am.op_type == ia32_AddrModeS) {
2811 ia32_address_t *addr = &am.addr;
2813 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base,
2814 addr->index, addr->mem);
2815 new_node = new_r_Proj(irg, block, fild, mode_vfp,
2818 set_am_attributes(fild, &am);
2819 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2821 fix_mem_proj(fild, &am);
2826 if(new_op == NULL) {
2827 new_op = be_transform_node(op);
2830 noreg = ia32_new_NoReg_gp(env_cg);
2831 nomem = new_NoMem();
2832 mode = get_irn_mode(op);
2834 /* first convert to 32 bit signed if necessary */
2835 src_bits = get_mode_size_bits(src_mode);
2836 if (src_bits == 8) {
2837 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2839 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2841 } else if (src_bits < 32) {
2842 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2844 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2848 assert(get_mode_size_bits(mode) == 32);
2851 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2854 set_ia32_use_frame(store);
2855 set_ia32_op_type(store, ia32_AddrModeD);
2856 set_ia32_ls_mode(store, mode_Iu);
2858 /* exception for 32bit unsigned, do a 64bit spill+load */
2859 if(!mode_is_signed(mode)) {
2862 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2864 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2865 get_irg_frame(irg), noreg, nomem,
2868 set_ia32_use_frame(zero_store);
2869 set_ia32_op_type(zero_store, ia32_AddrModeD);
2870 add_ia32_am_offs_int(zero_store, 4);
2871 set_ia32_ls_mode(zero_store, mode_Iu);
2876 store = new_rd_Sync(dbgi, irg, block, 2, in);
2877 store_mode = mode_Ls;
2879 store_mode = mode_Is;
2883 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2885 set_ia32_use_frame(fild);
2886 set_ia32_op_type(fild, ia32_AddrModeS);
2887 set_ia32_ls_mode(fild, store_mode);
2889 new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2895 * Create a conversion from one integer mode into another one
2897 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2898 dbg_info *dbgi, ir_node *block, ir_node *op,
2901 ir_graph *irg = current_ir_graph;
2902 int src_bits = get_mode_size_bits(src_mode);
2903 int tgt_bits = get_mode_size_bits(tgt_mode);
2904 ir_node *new_block = be_transform_node(block);
2906 ir_mode *smaller_mode;
2908 ia32_address_mode_t am;
2909 ia32_address_t *addr = &am.addr;
2912 if (src_bits < tgt_bits) {
2913 smaller_mode = src_mode;
2914 smaller_bits = src_bits;
2916 smaller_mode = tgt_mode;
2917 smaller_bits = tgt_bits;
2920 #ifdef DEBUG_libfirm
2922 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
2927 match_arguments(&am, block, NULL, op, NULL,
2928 match_8bit | match_16bit |
2929 match_am | match_8bit_am | match_16bit_am);
2930 if (smaller_bits == 8) {
2931 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2932 addr->index, addr->mem, am.new_op2,
2935 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2936 addr->index, addr->mem, am.new_op2,
2939 set_am_attributes(new_node, &am);
2940 /* match_arguments assume that out-mode = in-mode, this isn't true here
2942 set_ia32_ls_mode(new_node, smaller_mode);
2943 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2944 new_node = fix_mem_proj(new_node, &am);
2949 * Transforms a Conv node.
2951 * @return The created ia32 Conv node
2953 static ir_node *gen_Conv(ir_node *node) {
2954 ir_node *block = get_nodes_block(node);
2955 ir_node *new_block = be_transform_node(block);
2956 ir_node *op = get_Conv_op(node);
2957 ir_node *new_op = NULL;
2958 ir_graph *irg = current_ir_graph;
2959 dbg_info *dbgi = get_irn_dbg_info(node);
2960 ir_mode *src_mode = get_irn_mode(op);
2961 ir_mode *tgt_mode = get_irn_mode(node);
2962 int src_bits = get_mode_size_bits(src_mode);
2963 int tgt_bits = get_mode_size_bits(tgt_mode);
2964 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2965 ir_node *nomem = new_rd_NoMem(irg);
2966 ir_node *res = NULL;
2968 if (src_mode == mode_b) {
2969 assert(mode_is_int(tgt_mode));
2970 /* nothing to do, we already model bools as 0/1 ints */
2971 return be_transform_node(op);
2974 if (src_mode == tgt_mode) {
2975 if (get_Conv_strict(node)) {
2976 if (ia32_cg_config.use_sse2) {
2977 /* when we are in SSE mode, we can kill all strict no-op conversion */
2978 return be_transform_node(op);
2981 /* this should be optimized already, but who knows... */
2982 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2983 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2984 return be_transform_node(op);
2988 if (mode_is_float(src_mode)) {
2989 new_op = be_transform_node(op);
2990 /* we convert from float ... */
2991 if (mode_is_float(tgt_mode)) {
2992 if(src_mode == mode_E && tgt_mode == mode_D
2993 && !get_Conv_strict(node)) {
2994 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2999 if (ia32_cg_config.use_sse2) {
3000 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
3001 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
3003 set_ia32_ls_mode(res, tgt_mode);
3005 if(get_Conv_strict(node)) {
3006 res = gen_x87_strict_conv(tgt_mode, new_op);
3007 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
3010 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3015 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
3016 if (ia32_cg_config.use_sse2) {
3017 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
3019 set_ia32_ls_mode(res, src_mode);
3021 return gen_x87_fp_to_gp(node);
3025 /* we convert from int ... */
3026 if (mode_is_float(tgt_mode)) {
3028 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
3029 if (ia32_cg_config.use_sse2) {
3030 new_op = be_transform_node(op);
3031 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
3033 set_ia32_ls_mode(res, tgt_mode);
3035 res = gen_x87_gp_to_fp(node, src_mode);
3036 if(get_Conv_strict(node)) {
3037 res = gen_x87_strict_conv(tgt_mode, res);
3038 SET_IA32_ORIG_NODE(get_Proj_pred(res),
3039 ia32_get_old_node_name(env_cg, node));
3043 } else if(tgt_mode == mode_b) {
3044 /* mode_b lowering already took care that we only have 0/1 values */
3045 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3046 src_mode, tgt_mode));
3047 return be_transform_node(op);
3050 if (src_bits == tgt_bits) {
3051 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3052 src_mode, tgt_mode));
3053 return be_transform_node(op);
3056 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
3064 static int check_immediate_constraint(long val, char immediate_constraint_type)
3066 switch (immediate_constraint_type) {
3070 return val >= 0 && val <= 32;
3072 return val >= 0 && val <= 63;
3074 return val >= -128 && val <= 127;
3076 return val == 0xff || val == 0xffff;
3078 return val >= 0 && val <= 3;
3080 return val >= 0 && val <= 255;
3082 return val >= 0 && val <= 127;
3086 panic("Invalid immediate constraint found");
3090 static ir_node *try_create_Immediate(ir_node *node,
3091 char immediate_constraint_type)
3094 tarval *offset = NULL;
3095 int offset_sign = 0;
3097 ir_entity *symconst_ent = NULL;
3098 int symconst_sign = 0;
3100 ir_node *cnst = NULL;
3101 ir_node *symconst = NULL;
3104 mode = get_irn_mode(node);
3105 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
3109 if(is_Minus(node)) {
3111 node = get_Minus_op(node);
3114 if(is_Const(node)) {
3117 offset_sign = minus;
3118 } else if(is_SymConst(node)) {
3121 symconst_sign = minus;
3122 } else if(is_Add(node)) {
3123 ir_node *left = get_Add_left(node);
3124 ir_node *right = get_Add_right(node);
3125 if(is_Const(left) && is_SymConst(right)) {
3128 symconst_sign = minus;
3129 offset_sign = minus;
3130 } else if(is_SymConst(left) && is_Const(right)) {
3133 symconst_sign = minus;
3134 offset_sign = minus;
3136 } else if(is_Sub(node)) {
3137 ir_node *left = get_Sub_left(node);
3138 ir_node *right = get_Sub_right(node);
3139 if(is_Const(left) && is_SymConst(right)) {
3142 symconst_sign = !minus;
3143 offset_sign = minus;
3144 } else if(is_SymConst(left) && is_Const(right)) {
3147 symconst_sign = minus;
3148 offset_sign = !minus;
3155 offset = get_Const_tarval(cnst);
3156 if(tarval_is_long(offset)) {
3157 val = get_tarval_long(offset);
3159 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
3164 if(!check_immediate_constraint(val, immediate_constraint_type))
3167 if(symconst != NULL) {
3168 if(immediate_constraint_type != 0) {
3169 /* we need full 32bits for symconsts */
3173 /* unfortunately the assembler/linker doesn't support -symconst */
3177 if(get_SymConst_kind(symconst) != symconst_addr_ent)
3179 symconst_ent = get_SymConst_entity(symconst);
3181 if(cnst == NULL && symconst == NULL)
3184 if(offset_sign && offset != NULL) {
3185 offset = tarval_neg(offset);
3188 new_node = create_Immediate(symconst_ent, symconst_sign, val);
3193 static ir_node *create_immediate_or_transform(ir_node *node,
3194 char immediate_constraint_type)
3196 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
3197 if (new_node == NULL) {
3198 new_node = be_transform_node(node);
3203 static const arch_register_req_t no_register_req = {
3204 arch_register_req_type_none,
3205 NULL, /* regclass */
3206 NULL, /* limit bitset */
3208 0 /* different pos */
3212 * An assembler constraint.
3214 typedef struct constraint_t constraint_t;
3215 struct constraint_t {
3218 const arch_register_req_t **out_reqs;
3220 const arch_register_req_t *req;
3221 unsigned immediate_possible;
3222 char immediate_type;
3225 static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
3227 int immediate_possible = 0;
3228 char immediate_type = 0;
3229 unsigned limited = 0;
3230 const arch_register_class_t *cls = NULL;
3231 ir_graph *irg = current_ir_graph;
3232 struct obstack *obst = get_irg_obstack(irg);
3233 arch_register_req_t *req;
3234 unsigned *limited_ptr = NULL;
3238 /* TODO: replace all the asserts with nice error messages */
3241 /* a memory constraint: no need to do anything in backend about it
3242 * (the dependencies are already respected by the memory edge of
3244 constraint->req = &no_register_req;
3256 assert(cls == NULL ||
3257 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3258 cls = &ia32_reg_classes[CLASS_ia32_gp];
3259 limited |= 1 << REG_EAX;
3262 assert(cls == NULL ||
3263 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3264 cls = &ia32_reg_classes[CLASS_ia32_gp];
3265 limited |= 1 << REG_EBX;
3268 assert(cls == NULL ||
3269 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3270 cls = &ia32_reg_classes[CLASS_ia32_gp];
3271 limited |= 1 << REG_ECX;
3274 assert(cls == NULL ||
3275 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3276 cls = &ia32_reg_classes[CLASS_ia32_gp];
3277 limited |= 1 << REG_EDX;
3280 assert(cls == NULL ||
3281 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3282 cls = &ia32_reg_classes[CLASS_ia32_gp];
3283 limited |= 1 << REG_EDI;
3286 assert(cls == NULL ||
3287 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3288 cls = &ia32_reg_classes[CLASS_ia32_gp];
3289 limited |= 1 << REG_ESI;
3292 case 'q': /* q means lower part of the regs only, this makes no
3293 * difference to Q for us (we only assigne whole registers) */
3294 assert(cls == NULL ||
3295 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3296 cls = &ia32_reg_classes[CLASS_ia32_gp];
3297 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3301 assert(cls == NULL ||
3302 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3303 cls = &ia32_reg_classes[CLASS_ia32_gp];
3304 limited |= 1 << REG_EAX | 1 << REG_EDX;
3307 assert(cls == NULL ||
3308 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3309 cls = &ia32_reg_classes[CLASS_ia32_gp];
3310 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3311 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3318 assert(cls == NULL);
3319 cls = &ia32_reg_classes[CLASS_ia32_gp];
3325 /* TODO: mark values so the x87 simulator knows about t and u */
3326 assert(cls == NULL);
3327 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3332 assert(cls == NULL);
3333 /* TODO: check that sse2 is supported */
3334 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3344 assert(!immediate_possible);
3345 immediate_possible = 1;
3346 immediate_type = *c;
3350 assert(!immediate_possible);
3351 immediate_possible = 1;
3355 assert(!immediate_possible && cls == NULL);
3356 immediate_possible = 1;
3357 cls = &ia32_reg_classes[CLASS_ia32_gp];
3370 assert(constraint->is_in && "can only specify same constraint "
3373 sscanf(c, "%d%n", &same_as, &p);
3381 /* memory constraint no need to do anything in backend about it
3382 * (the dependencies are already respected by the memory edge of
3384 constraint->req = &no_register_req;
3387 case 'E': /* no float consts yet */
3388 case 'F': /* no float consts yet */
3389 case 's': /* makes no sense on x86 */
3390 case 'X': /* we can't support that in firm */
3393 case '<': /* no autodecrement on x86 */
3394 case '>': /* no autoincrement on x86 */
3395 case 'C': /* sse constant not supported yet */
3396 case 'G': /* 80387 constant not supported yet */
3397 case 'y': /* we don't support mmx registers yet */
3398 case 'Z': /* not available in 32 bit mode */
3399 case 'e': /* not available in 32 bit mode */
3400 panic("unsupported asm constraint '%c' found in (%+F)",
3401 *c, current_ir_graph);
3404 panic("unknown asm constraint '%c' found in (%+F)", *c,
3412 const arch_register_req_t *other_constr;
3414 assert(cls == NULL && "same as and register constraint not supported");
3415 assert(!immediate_possible && "same as and immediate constraint not "
3417 assert(same_as < constraint->n_outs && "wrong constraint number in "
3418 "same_as constraint");
3420 other_constr = constraint->out_reqs[same_as];
3422 req = obstack_alloc(obst, sizeof(req[0]));
3423 req->cls = other_constr->cls;
3424 req->type = arch_register_req_type_should_be_same;
3425 req->limited = NULL;
3426 req->other_same = 1U << pos;
3427 req->other_different = 0;
3429 /* switch constraints. This is because in firm we have same_as
3430 * constraints on the output constraints while in the gcc asm syntax
3431 * they are specified on the input constraints */
3432 constraint->req = other_constr;
3433 constraint->out_reqs[same_as] = req;
3434 constraint->immediate_possible = 0;
3438 if(immediate_possible && cls == NULL) {
3439 cls = &ia32_reg_classes[CLASS_ia32_gp];
3441 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3442 assert(cls != NULL);
3444 if(immediate_possible) {
3445 assert(constraint->is_in
3446 && "immediate make no sense for output constraints");
3448 /* todo: check types (no float input on 'r' constrained in and such... */
3451 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3452 limited_ptr = (unsigned*) (req+1);
3454 req = obstack_alloc(obst, sizeof(req[0]));
3456 memset(req, 0, sizeof(req[0]));
3459 req->type = arch_register_req_type_limited;
3460 *limited_ptr = limited;
3461 req->limited = limited_ptr;
3463 req->type = arch_register_req_type_normal;
3467 constraint->req = req;
3468 constraint->immediate_possible = immediate_possible;
3469 constraint->immediate_type = immediate_type;
3472 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3473 const char *clobber)
3475 ir_graph *irg = get_irn_irg(node);
3476 struct obstack *obst = get_irg_obstack(irg);
3477 const arch_register_t *reg = NULL;
3480 arch_register_req_t *req;
3481 const arch_register_class_t *cls;
3485 fprintf(stderr, "Clobber: %s\n", clobber);
3487 /* TODO: construct a hashmap instead of doing linear search for clobber
3489 for(c = 0; c < N_CLASSES; ++c) {
3490 cls = & ia32_reg_classes[c];
3491 for(r = 0; r < cls->n_regs; ++r) {
3492 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
3493 if(strcmp(temp_reg->name, clobber) == 0
3494 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
3503 panic("Register '%s' mentioned in asm clobber is unknown\n", clobber);
3507 assert(reg->index < 32);
3509 unsigned *limited = obstack_alloc(obst, sizeof(limited[0]));
3510 *limited = 1 << reg->index;
3512 req = obstack_alloc(obst, sizeof(req[0]));
3513 memset(req, 0, sizeof(req[0]));
3514 req->type = arch_register_req_type_limited;
3516 req->limited = limited;
3518 constraint->req = req;
3519 constraint->immediate_possible = 0;
3520 constraint->immediate_type = 0;
3523 static int is_memory_op(const ir_asm_constraint *constraint)
3525 ident *id = constraint->constraint;
3526 const char *str = get_id_str(id);
3529 for(c = str; *c != '\0'; ++c) {
3538 * generates code for a ASM node
3540 static ir_node *gen_ASM(ir_node *node)
3543 ir_graph *irg = current_ir_graph;
3544 ir_node *block = get_nodes_block(node);
3545 ir_node *new_block = be_transform_node(block);
3546 dbg_info *dbgi = get_irn_dbg_info(node);
3550 int n_out_constraints;
3552 const arch_register_req_t **out_reg_reqs;
3553 const arch_register_req_t **in_reg_reqs;
3554 ia32_asm_reg_t *register_map;
3555 unsigned reg_map_size = 0;
3556 struct obstack *obst;
3557 const ir_asm_constraint *in_constraints;
3558 const ir_asm_constraint *out_constraints;
3560 constraint_t parsed_constraint;
3562 arity = get_irn_arity(node);
3563 in = alloca(arity * sizeof(in[0]));
3564 memset(in, 0, arity * sizeof(in[0]));
3566 n_out_constraints = get_ASM_n_output_constraints(node);
3567 n_clobbers = get_ASM_n_clobbers(node);
3568 out_arity = n_out_constraints + n_clobbers;
3569 /* hack to keep space for mem proj */
3573 in_constraints = get_ASM_input_constraints(node);
3574 out_constraints = get_ASM_output_constraints(node);
3575 clobbers = get_ASM_clobbers(node);
3577 /* construct output constraints */
3578 obst = get_irg_obstack(irg);
3579 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
3580 parsed_constraint.out_reqs = out_reg_reqs;
3581 parsed_constraint.n_outs = n_out_constraints;
3582 parsed_constraint.is_in = 0;
3584 for(i = 0; i < out_arity; ++i) {
3587 if(i < n_out_constraints) {
3588 const ir_asm_constraint *constraint = &out_constraints[i];
3589 c = get_id_str(constraint->constraint);
3590 parse_asm_constraint(i, &parsed_constraint, c);
3592 if(constraint->pos > reg_map_size)
3593 reg_map_size = constraint->pos;
3595 out_reg_reqs[i] = parsed_constraint.req;
3596 } else if(i < out_arity - 1) {
3597 ident *glob_id = clobbers [i - n_out_constraints];
3598 assert(glob_id != NULL);
3599 c = get_id_str(glob_id);
3600 parse_clobber(node, i, &parsed_constraint, c);
3602 out_reg_reqs[i+1] = parsed_constraint.req;
3606 out_reg_reqs[n_out_constraints] = &no_register_req;
3608 /* construct input constraints */
3609 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
3610 parsed_constraint.is_in = 1;
3611 for(i = 0; i < arity; ++i) {
3612 const ir_asm_constraint *constraint = &in_constraints[i];
3613 ident *constr_id = constraint->constraint;
3614 const char *c = get_id_str(constr_id);
3616 parse_asm_constraint(i, &parsed_constraint, c);
3617 in_reg_reqs[i] = parsed_constraint.req;
3619 if(constraint->pos > reg_map_size)
3620 reg_map_size = constraint->pos;
3622 if(parsed_constraint.immediate_possible) {
3623 ir_node *pred = get_irn_n(node, i);
3624 char imm_type = parsed_constraint.immediate_type;
3625 ir_node *immediate = try_create_Immediate(pred, imm_type);
3627 if(immediate != NULL) {
3634 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
3635 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
3637 for(i = 0; i < n_out_constraints; ++i) {
3638 const ir_asm_constraint *constraint = &out_constraints[i];
3639 unsigned pos = constraint->pos;
3641 assert(pos < reg_map_size);
3642 register_map[pos].use_input = 0;
3643 register_map[pos].valid = 1;
3644 register_map[pos].memory = is_memory_op(constraint);
3645 register_map[pos].inout_pos = i;
3646 register_map[pos].mode = constraint->mode;
3649 /* transform inputs */
3650 for(i = 0; i < arity; ++i) {
3651 const ir_asm_constraint *constraint = &in_constraints[i];
3652 unsigned pos = constraint->pos;
3653 ir_node *pred = get_irn_n(node, i);
3654 ir_node *transformed;
3656 assert(pos < reg_map_size);
3657 register_map[pos].use_input = 1;
3658 register_map[pos].valid = 1;
3659 register_map[pos].memory = is_memory_op(constraint);
3660 register_map[pos].inout_pos = i;
3661 register_map[pos].mode = constraint->mode;
3666 transformed = be_transform_node(pred);
3667 in[i] = transformed;
3670 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
3671 get_ASM_text(node), register_map);
3673 set_ia32_out_req_all(new_node, out_reg_reqs);
3674 set_ia32_in_req_all(new_node, in_reg_reqs);
3676 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3682 * Transforms a FrameAddr into an ia32 Add.
3684 static ir_node *gen_be_FrameAddr(ir_node *node) {
3685 ir_node *block = be_transform_node(get_nodes_block(node));
3686 ir_node *op = be_get_FrameAddr_frame(node);
3687 ir_node *new_op = be_transform_node(op);
3688 ir_graph *irg = current_ir_graph;
3689 dbg_info *dbgi = get_irn_dbg_info(node);
3690 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3693 new_node = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3694 set_ia32_frame_ent(new_node, arch_get_frame_entity(env_cg->arch_env, node));
3695 set_ia32_use_frame(new_node);
3697 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3703 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3705 static ir_node *gen_be_Return(ir_node *node) {
3706 ir_graph *irg = current_ir_graph;
3707 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3708 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3709 ir_entity *ent = get_irg_entity(irg);
3710 ir_type *tp = get_entity_type(ent);
3715 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3716 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3719 int pn_ret_val, pn_ret_mem, arity, i;
3721 assert(ret_val != NULL);
3722 if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) {
3723 return be_duplicate_node(node);
3726 res_type = get_method_res_type(tp, 0);
3728 if (! is_Primitive_type(res_type)) {
3729 return be_duplicate_node(node);
3732 mode = get_type_mode(res_type);
3733 if (! mode_is_float(mode)) {
3734 return be_duplicate_node(node);
3737 assert(get_method_n_ress(tp) == 1);
3739 pn_ret_val = get_Proj_proj(ret_val);
3740 pn_ret_mem = get_Proj_proj(ret_mem);
3742 /* get the Barrier */
3743 barrier = get_Proj_pred(ret_val);
3745 /* get result input of the Barrier */
3746 ret_val = get_irn_n(barrier, pn_ret_val);
3747 new_ret_val = be_transform_node(ret_val);
3749 /* get memory input of the Barrier */
3750 ret_mem = get_irn_n(barrier, pn_ret_mem);
3751 new_ret_mem = be_transform_node(ret_mem);
3753 frame = get_irg_frame(irg);
3755 dbgi = get_irn_dbg_info(barrier);
3756 block = be_transform_node(get_nodes_block(barrier));
3758 noreg = ia32_new_NoReg_gp(env_cg);
3760 /* store xmm0 onto stack */
3761 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3762 new_ret_mem, new_ret_val);
3763 set_ia32_ls_mode(sse_store, mode);
3764 set_ia32_op_type(sse_store, ia32_AddrModeD);
3765 set_ia32_use_frame(sse_store);
3767 /* load into x87 register */
3768 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3769 set_ia32_op_type(fld, ia32_AddrModeS);
3770 set_ia32_use_frame(fld);
3772 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3773 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3775 /* create a new barrier */
3776 arity = get_irn_arity(barrier);
3777 in = alloca(arity * sizeof(in[0]));
3778 for (i = 0; i < arity; ++i) {
3781 if (i == pn_ret_val) {
3783 } else if (i == pn_ret_mem) {
3786 ir_node *in = get_irn_n(barrier, i);
3787 new_in = be_transform_node(in);
3792 new_barrier = new_ir_node(dbgi, irg, block,
3793 get_irn_op(barrier), get_irn_mode(barrier),
3795 copy_node_attr(barrier, new_barrier);
3796 be_duplicate_deps(barrier, new_barrier);
3797 be_set_transformed_node(barrier, new_barrier);
3798 mark_irn_visited(barrier);
3800 /* transform normally */
3801 return be_duplicate_node(node);
3805 * Transform a be_AddSP into an ia32_SubSP.
3807 static ir_node *gen_be_AddSP(ir_node *node)
3809 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3810 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3812 return gen_binop(node, sp, sz, new_rd_ia32_SubSP, match_am);
3816 * Transform a be_SubSP into an ia32_AddSP
3818 static ir_node *gen_be_SubSP(ir_node *node)
3820 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3821 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3823 return gen_binop(node, sp, sz, new_rd_ia32_AddSP, match_am);
3827 * This function just sets the register for the Unknown node
3828 * as this is not done during register allocation because Unknown
3829 * is an "ignore" node.
3831 static ir_node *gen_Unknown(ir_node *node) {
3832 ir_mode *mode = get_irn_mode(node);
3834 if (mode_is_float(mode)) {
3835 if (ia32_cg_config.use_sse2) {
3836 return ia32_new_Unknown_xmm(env_cg);
3838 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3839 ir_graph *irg = current_ir_graph;
3840 dbg_info *dbgi = get_irn_dbg_info(node);
3841 ir_node *block = get_irg_start_block(irg);
3842 return new_rd_ia32_vfldz(dbgi, irg, block);
3844 } else if (mode_needs_gp_reg(mode)) {
3845 return ia32_new_Unknown_gp(env_cg);
3847 panic("unsupported Unknown-Mode");
3853 * Change some phi modes
3855 static ir_node *gen_Phi(ir_node *node) {
3856 ir_node *block = be_transform_node(get_nodes_block(node));
3857 ir_graph *irg = current_ir_graph;
3858 dbg_info *dbgi = get_irn_dbg_info(node);
3859 ir_mode *mode = get_irn_mode(node);
3862 if(mode_needs_gp_reg(mode)) {
3863 /* we shouldn't have any 64bit stuff around anymore */
3864 assert(get_mode_size_bits(mode) <= 32);
3865 /* all integer operations are on 32bit registers now */
3867 } else if(mode_is_float(mode)) {
3868 if (ia32_cg_config.use_sse2) {
3875 /* phi nodes allow loops, so we use the old arguments for now
3876 * and fix this later */
3877 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3878 get_irn_in(node) + 1);
3879 copy_node_attr(node, phi);
3880 be_duplicate_deps(node, phi);
3882 be_set_transformed_node(node, phi);
3883 be_enqueue_preds(node);
3891 static ir_node *gen_IJmp(ir_node *node)
3893 ir_node *block = get_nodes_block(node);
3894 ir_node *new_block = be_transform_node(block);
3895 ir_graph *irg = current_ir_graph;
3896 dbg_info *dbgi = get_irn_dbg_info(node);
3897 ir_node *op = get_IJmp_target(node);
3899 ia32_address_mode_t am;
3900 ia32_address_t *addr = &am.addr;
3902 assert(get_irn_mode(op) == mode_P);
3904 match_arguments(&am, block, NULL, op, NULL,
3905 match_am | match_8bit_am | match_16bit_am |
3906 match_immediate | match_8bit | match_16bit);
3908 new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index,
3909 addr->mem, am.new_op2);
3910 set_am_attributes(new_node, &am);
3911 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3913 new_node = fix_mem_proj(new_node, &am);
3918 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3921 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3922 ir_node *val, ir_node *mem);
3925 * Transforms a lowered Load into a "real" one.
3927 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3929 ir_node *block = be_transform_node(get_nodes_block(node));
3930 ir_node *ptr = get_irn_n(node, 0);
3931 ir_node *new_ptr = be_transform_node(ptr);
3932 ir_node *mem = get_irn_n(node, 1);
3933 ir_node *new_mem = be_transform_node(mem);
3934 ir_graph *irg = current_ir_graph;
3935 dbg_info *dbgi = get_irn_dbg_info(node);
3936 ir_mode *mode = get_ia32_ls_mode(node);
3937 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3940 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3942 set_ia32_op_type(new_op, ia32_AddrModeS);
3943 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3944 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3945 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3946 if (is_ia32_am_sc_sign(node))
3947 set_ia32_am_sc_sign(new_op);
3948 set_ia32_ls_mode(new_op, mode);
3949 if (is_ia32_use_frame(node)) {
3950 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3951 set_ia32_use_frame(new_op);
3954 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3960 * Transforms a lowered Store into a "real" one.
3962 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3964 ir_node *block = be_transform_node(get_nodes_block(node));
3965 ir_node *ptr = get_irn_n(node, 0);
3966 ir_node *new_ptr = be_transform_node(ptr);
3967 ir_node *val = get_irn_n(node, 1);
3968 ir_node *new_val = be_transform_node(val);
3969 ir_node *mem = get_irn_n(node, 2);
3970 ir_node *new_mem = be_transform_node(mem);
3971 ir_graph *irg = current_ir_graph;
3972 dbg_info *dbgi = get_irn_dbg_info(node);
3973 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3974 ir_mode *mode = get_ia32_ls_mode(node);
3978 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3980 am_offs = get_ia32_am_offs_int(node);
3981 add_ia32_am_offs_int(new_op, am_offs);
3983 set_ia32_op_type(new_op, ia32_AddrModeD);
3984 set_ia32_ls_mode(new_op, mode);
3985 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3986 set_ia32_use_frame(new_op);
3988 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3993 static ir_node *gen_ia32_l_ShlDep(ir_node *node)
3995 ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val);
3996 ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_count);
3998 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
3999 match_immediate | match_mode_neutral);
4002 static ir_node *gen_ia32_l_ShrDep(ir_node *node)
4004 ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_val);
4005 ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_count);
4006 return gen_shift_binop(node, left, right, new_rd_ia32_Shr,
4010 static ir_node *gen_ia32_l_SarDep(ir_node *node)
4012 ir_node *left = get_irn_n(node, n_ia32_l_SarDep_val);
4013 ir_node *right = get_irn_n(node, n_ia32_l_SarDep_count);
4014 return gen_shift_binop(node, left, right, new_rd_ia32_Sar,
4018 static ir_node *gen_ia32_l_Add(ir_node *node) {
4019 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
4020 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
4021 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add,
4022 match_commutative | match_am | match_immediate |
4023 match_mode_neutral);
4025 if(is_Proj(lowered)) {
4026 lowered = get_Proj_pred(lowered);
4028 assert(is_ia32_Add(lowered));
4029 set_irn_mode(lowered, mode_T);
4035 static ir_node *gen_ia32_l_Adc(ir_node *node)
4037 return gen_binop_flags(node, new_rd_ia32_Adc,
4038 match_commutative | match_am | match_immediate |
4039 match_mode_neutral);
4043 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
4045 * @param node The node to transform
4046 * @return the created ia32 vfild node
4048 static ir_node *gen_ia32_l_vfild(ir_node *node) {
4049 return gen_lowered_Load(node, new_rd_ia32_vfild);
4053 * Transforms an ia32_l_Load into a "real" ia32_Load node
4055 * @param node The node to transform
4056 * @return the created ia32 Load node
4058 static ir_node *gen_ia32_l_Load(ir_node *node) {
4059 return gen_lowered_Load(node, new_rd_ia32_Load);
4063 * Transforms an ia32_l_Store into a "real" ia32_Store node
4065 * @param node The node to transform
4066 * @return the created ia32 Store node
4068 static ir_node *gen_ia32_l_Store(ir_node *node) {
4069 return gen_lowered_Store(node, new_rd_ia32_Store);
4073 * Transforms a l_vfist into a "real" vfist node.
4075 * @param node The node to transform
4076 * @return the created ia32 vfist node
4078 static ir_node *gen_ia32_l_vfist(ir_node *node) {
4079 ir_node *block = be_transform_node(get_nodes_block(node));
4080 ir_node *ptr = get_irn_n(node, 0);
4081 ir_node *new_ptr = be_transform_node(ptr);
4082 ir_node *val = get_irn_n(node, 1);
4083 ir_node *new_val = be_transform_node(val);
4084 ir_node *mem = get_irn_n(node, 2);
4085 ir_node *new_mem = be_transform_node(mem);
4086 ir_graph *irg = current_ir_graph;
4087 dbg_info *dbgi = get_irn_dbg_info(node);
4088 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4089 ir_mode *mode = get_ia32_ls_mode(node);
4090 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
4094 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
4095 new_val, trunc_mode);
4097 am_offs = get_ia32_am_offs_int(node);
4098 add_ia32_am_offs_int(new_op, am_offs);
4100 set_ia32_op_type(new_op, ia32_AddrModeD);
4101 set_ia32_ls_mode(new_op, mode);
4102 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
4103 set_ia32_use_frame(new_op);
4105 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
4111 * Transforms a l_MulS into a "real" MulS node.
4113 * @return the created ia32 Mul node
4115 static ir_node *gen_ia32_l_Mul(ir_node *node) {
4116 ir_node *left = get_binop_left(node);
4117 ir_node *right = get_binop_right(node);
4119 return gen_binop(node, left, right, new_rd_ia32_Mul,
4120 match_commutative | match_am | match_mode_neutral);
4124 * Transforms a l_IMulS into a "real" IMul1OPS node.
4126 * @return the created ia32 IMul1OP node
4128 static ir_node *gen_ia32_l_IMul(ir_node *node) {
4129 ir_node *left = get_binop_left(node);
4130 ir_node *right = get_binop_right(node);
4132 return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
4133 match_commutative | match_am | match_mode_neutral);
4136 static ir_node *gen_ia32_l_Sub(ir_node *node) {
4137 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
4138 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
4139 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub,
4140 match_am | match_immediate | match_mode_neutral);
4142 if(is_Proj(lowered)) {
4143 lowered = get_Proj_pred(lowered);
4145 assert(is_ia32_Sub(lowered));
4146 set_irn_mode(lowered, mode_T);
4152 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
4153 return gen_binop_flags(node, new_rd_ia32_Sbb,
4154 match_am | match_immediate | match_mode_neutral);
4158 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
4159 * op1 - target to be shifted
4160 * op2 - contains bits to be shifted into target
4162 * Only op3 can be an immediate.
4164 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
4165 ir_node *low, ir_node *count)
4167 ir_node *block = get_nodes_block(node);
4168 ir_node *new_block = be_transform_node(block);
4169 ir_graph *irg = current_ir_graph;
4170 dbg_info *dbgi = get_irn_dbg_info(node);
4171 ir_node *new_high = be_transform_node(high);
4172 ir_node *new_low = be_transform_node(low);
4176 /* the shift amount can be any mode that is bigger than 5 bits, since all
4177 * other bits are ignored anyway */
4178 while (is_Conv(count) && get_irn_n_edges(count) == 1) {
4179 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
4180 count = get_Conv_op(count);
4182 new_count = create_immediate_or_transform(count, 0);
4184 if (is_ia32_l_ShlD(node)) {
4185 new_node = new_rd_ia32_ShlD(dbgi, irg, new_block, new_high, new_low,
4188 new_node = new_rd_ia32_ShrD(dbgi, irg, new_block, new_high, new_low,
4191 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
4196 static ir_node *gen_ia32_l_ShlD(ir_node *node)
4198 ir_node *high = get_irn_n(node, n_ia32_l_ShlD_val_high);
4199 ir_node *low = get_irn_n(node, n_ia32_l_ShlD_val_low);
4200 ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
4201 return gen_lowered_64bit_shifts(node, high, low, count);
4204 static ir_node *gen_ia32_l_ShrD(ir_node *node)
4206 ir_node *high = get_irn_n(node, n_ia32_l_ShrD_val_high);
4207 ir_node *low = get_irn_n(node, n_ia32_l_ShrD_val_low);
4208 ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
4209 return gen_lowered_64bit_shifts(node, high, low, count);
4212 static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) {
4213 ir_node *src_block = get_nodes_block(node);
4214 ir_node *block = be_transform_node(src_block);
4215 ir_graph *irg = current_ir_graph;
4216 dbg_info *dbgi = get_irn_dbg_info(node);
4217 ir_node *frame = get_irg_frame(irg);
4218 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4219 ir_node *nomem = new_NoMem();
4220 ir_node *val_low = get_irn_n(node, n_ia32_l_LLtoFloat_val_low);
4221 ir_node *val_high = get_irn_n(node, n_ia32_l_LLtoFloat_val_high);
4222 ir_node *new_val_low = be_transform_node(val_low);
4223 ir_node *new_val_high = be_transform_node(val_high);
4228 ir_node *store_high;
4230 if(!mode_is_signed(get_irn_mode(val_high))) {
4231 panic("unsigned long long -> float not supported yet (%+F)", node);
4235 store_low = new_rd_ia32_Store(dbgi, irg, block, frame, noreg, nomem,
4237 store_high = new_rd_ia32_Store(dbgi, irg, block, frame, noreg, nomem,
4239 SET_IA32_ORIG_NODE(store_low, ia32_get_old_node_name(env_cg, node));
4240 SET_IA32_ORIG_NODE(store_high, ia32_get_old_node_name(env_cg, node));
4242 set_ia32_use_frame(store_low);
4243 set_ia32_use_frame(store_high);
4244 set_ia32_op_type(store_low, ia32_AddrModeD);
4245 set_ia32_op_type(store_high, ia32_AddrModeD);
4246 set_ia32_ls_mode(store_low, mode_Iu);
4247 set_ia32_ls_mode(store_high, mode_Is);
4248 add_ia32_am_offs_int(store_high, 4);
4252 sync = new_rd_Sync(dbgi, irg, block, 2, in);
4255 fild = new_rd_ia32_vfild(dbgi, irg, block, frame, noreg, sync);
4257 set_ia32_use_frame(fild);
4258 set_ia32_op_type(fild, ia32_AddrModeS);
4259 set_ia32_ls_mode(fild, mode_Ls);
4261 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
4263 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
4266 static ir_node *gen_ia32_l_FloattoLL(ir_node *node) {
4268 panic("LLtoFloat NIY");
4272 * the BAD transformer.
4274 static ir_node *bad_transform(ir_node *node) {
4275 panic("No transform function for %+F available.\n", node);
4280 * Transform the Projs of an AddSP.
4282 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4283 ir_node *block = be_transform_node(get_nodes_block(node));
4284 ir_node *pred = get_Proj_pred(node);
4285 ir_node *new_pred = be_transform_node(pred);
4286 ir_graph *irg = current_ir_graph;
4287 dbg_info *dbgi = get_irn_dbg_info(node);
4288 long proj = get_Proj_proj(node);
4290 if (proj == pn_be_AddSP_sp) {
4291 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4292 pn_ia32_SubSP_stack);
4293 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4295 } else if(proj == pn_be_AddSP_res) {
4296 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4297 pn_ia32_SubSP_addr);
4298 } else if (proj == pn_be_AddSP_M) {
4299 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4303 return new_rd_Unknown(irg, get_irn_mode(node));
4307 * Transform the Projs of a SubSP.
4309 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4310 ir_node *block = be_transform_node(get_nodes_block(node));
4311 ir_node *pred = get_Proj_pred(node);
4312 ir_node *new_pred = be_transform_node(pred);
4313 ir_graph *irg = current_ir_graph;
4314 dbg_info *dbgi = get_irn_dbg_info(node);
4315 long proj = get_Proj_proj(node);
4317 if (proj == pn_be_SubSP_sp) {
4318 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4319 pn_ia32_AddSP_stack);
4320 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4322 } else if (proj == pn_be_SubSP_M) {
4323 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4327 return new_rd_Unknown(irg, get_irn_mode(node));
4331 * Transform and renumber the Projs from a Load.
4333 static ir_node *gen_Proj_Load(ir_node *node) {
4335 ir_node *block = be_transform_node(get_nodes_block(node));
4336 ir_node *pred = get_Proj_pred(node);
4337 ir_graph *irg = current_ir_graph;
4338 dbg_info *dbgi = get_irn_dbg_info(node);
4339 long proj = get_Proj_proj(node);
4342 /* loads might be part of source address mode matches, so we don't
4343 transform the ProjMs yet (with the exception of loads whose result is
4346 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4349 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4351 /* this is needed, because sometimes we have loops that are only
4352 reachable through the ProjM */
4353 be_enqueue_preds(node);
4354 /* do it in 2 steps, to silence firm verifier */
4355 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4356 set_Proj_proj(res, pn_ia32_Load_M);
4360 /* renumber the proj */
4361 new_pred = be_transform_node(pred);
4362 if (is_ia32_Load(new_pred)) {
4365 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
4367 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
4368 case pn_Load_X_regular:
4369 return new_rd_Jmp(dbgi, irg, block);
4370 case pn_Load_X_except:
4371 /* This Load might raise an exception. Mark it. */
4372 set_ia32_exc_label(new_pred, 1);
4373 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Load_X_exc);
4377 } else if (is_ia32_Conv_I2I(new_pred) ||
4378 is_ia32_Conv_I2I8Bit(new_pred)) {
4379 set_irn_mode(new_pred, mode_T);
4380 if (proj == pn_Load_res) {
4381 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4382 } else if (proj == pn_Load_M) {
4383 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4385 } else if (is_ia32_xLoad(new_pred)) {
4388 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
4390 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
4391 case pn_Load_X_regular:
4392 return new_rd_Jmp(dbgi, irg, block);
4393 case pn_Load_X_except:
4394 /* This Load might raise an exception. Mark it. */
4395 set_ia32_exc_label(new_pred, 1);
4396 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_xLoad_X_exc);
4400 } else if (is_ia32_vfld(new_pred)) {
4403 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
4405 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
4406 case pn_Load_X_regular:
4407 return new_rd_Jmp(dbgi, irg, block);
4408 case pn_Load_X_except:
4409 /* This Load might raise an exception. Mark it. */
4410 set_ia32_exc_label(new_pred, 1);
4411 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_xLoad_X_exc);
4416 /* can happen for ProJMs when source address mode happened for the
4419 /* however it should not be the result proj, as that would mean the
4420 load had multiple users and should not have been used for
4422 if (proj != pn_Load_M) {
4423 panic("internal error: transformed node not a Load");
4425 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4429 return new_rd_Unknown(irg, get_irn_mode(node));
4433 * Transform and renumber the Projs from a DivMod like instruction.
4435 static ir_node *gen_Proj_DivMod(ir_node *node) {
4436 ir_node *block = be_transform_node(get_nodes_block(node));
4437 ir_node *pred = get_Proj_pred(node);
4438 ir_node *new_pred = be_transform_node(pred);
4439 ir_graph *irg = current_ir_graph;
4440 dbg_info *dbgi = get_irn_dbg_info(node);
4441 ir_mode *mode = get_irn_mode(node);
4442 long proj = get_Proj_proj(node);
4444 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4446 switch (get_irn_opcode(pred)) {
4450 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4452 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4453 case pn_Div_X_regular:
4454 return new_rd_Jmp(dbgi, irg, block);
4455 case pn_Div_X_except:
4456 set_ia32_exc_label(new_pred, 1);
4457 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc);
4465 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4467 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4468 case pn_Mod_X_except:
4469 set_ia32_exc_label(new_pred, 1);
4470 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc);
4478 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4479 case pn_DivMod_res_div:
4480 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4481 case pn_DivMod_res_mod:
4482 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4483 case pn_DivMod_X_regular:
4484 return new_rd_Jmp(dbgi, irg, block);
4485 case pn_DivMod_X_except:
4486 set_ia32_exc_label(new_pred, 1);
4487 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc);
4497 return new_rd_Unknown(irg, mode);
4501 * Transform and renumber the Projs from a CopyB.
4503 static ir_node *gen_Proj_CopyB(ir_node *node) {
4504 ir_node *block = be_transform_node(get_nodes_block(node));
4505 ir_node *pred = get_Proj_pred(node);
4506 ir_node *new_pred = be_transform_node(pred);
4507 ir_graph *irg = current_ir_graph;
4508 dbg_info *dbgi = get_irn_dbg_info(node);
4509 ir_mode *mode = get_irn_mode(node);
4510 long proj = get_Proj_proj(node);
4513 case pn_CopyB_M_regular:
4514 if (is_ia32_CopyB_i(new_pred)) {
4515 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4516 } else if (is_ia32_CopyB(new_pred)) {
4517 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4525 return new_rd_Unknown(irg, mode);
4529 * Transform and renumber the Projs from a Quot.
4531 static ir_node *gen_Proj_Quot(ir_node *node) {
4532 ir_node *block = be_transform_node(get_nodes_block(node));
4533 ir_node *pred = get_Proj_pred(node);
4534 ir_node *new_pred = be_transform_node(pred);
4535 ir_graph *irg = current_ir_graph;
4536 dbg_info *dbgi = get_irn_dbg_info(node);
4537 ir_mode *mode = get_irn_mode(node);
4538 long proj = get_Proj_proj(node);
4542 if (is_ia32_xDiv(new_pred)) {
4543 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4544 } else if (is_ia32_vfdiv(new_pred)) {
4545 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4549 if (is_ia32_xDiv(new_pred)) {
4550 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4551 } else if (is_ia32_vfdiv(new_pred)) {
4552 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4560 return new_rd_Unknown(irg, mode);
4564 * Transform the Thread Local Storage Proj.
4566 static ir_node *gen_Proj_tls(ir_node *node) {
4567 ir_node *block = be_transform_node(get_nodes_block(node));
4568 ir_graph *irg = current_ir_graph;
4569 dbg_info *dbgi = NULL;
4570 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4575 static ir_node *gen_be_Call(ir_node *node) {
4576 ir_node *res = be_duplicate_node(node);
4577 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4582 static ir_node *gen_be_IncSP(ir_node *node) {
4583 ir_node *res = be_duplicate_node(node);
4584 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4590 * Transform the Projs from a be_Call.
4592 static ir_node *gen_Proj_be_Call(ir_node *node) {
4593 ir_node *block = be_transform_node(get_nodes_block(node));
4594 ir_node *call = get_Proj_pred(node);
4595 ir_node *new_call = be_transform_node(call);
4596 ir_graph *irg = current_ir_graph;
4597 dbg_info *dbgi = get_irn_dbg_info(node);
4598 ir_type *method_type = be_Call_get_type(call);
4599 int n_res = get_method_n_ress(method_type);
4600 long proj = get_Proj_proj(node);
4601 ir_mode *mode = get_irn_mode(node);
4603 const arch_register_class_t *cls;
4605 /* The following is kinda tricky: If we're using SSE, then we have to
4606 * move the result value of the call in floating point registers to an
4607 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4608 * after the call, we have to make sure to correctly make the
4609 * MemProj and the result Proj use these 2 nodes
4611 if (proj == pn_be_Call_M_regular) {
4612 // get new node for result, are we doing the sse load/store hack?
4613 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4614 ir_node *call_res_new;
4615 ir_node *call_res_pred = NULL;
4617 if (call_res != NULL) {
4618 call_res_new = be_transform_node(call_res);
4619 call_res_pred = get_Proj_pred(call_res_new);
4622 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4623 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4624 pn_be_Call_M_regular);
4626 assert(is_ia32_xLoad(call_res_pred));
4627 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4631 if (ia32_cg_config.use_sse2 && proj >= pn_be_Call_first_res
4632 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)) {
4634 ir_node *frame = get_irg_frame(irg);
4635 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4637 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4640 /* in case there is no memory output: create one to serialize the copy
4642 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4643 pn_be_Call_M_regular);
4644 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4645 pn_be_Call_first_res);
4647 /* store st(0) onto stack */
4648 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4650 set_ia32_op_type(fstp, ia32_AddrModeD);
4651 set_ia32_use_frame(fstp);
4653 /* load into SSE register */
4654 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4656 set_ia32_op_type(sse_load, ia32_AddrModeS);
4657 set_ia32_use_frame(sse_load);
4659 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4665 /* transform call modes */
4666 if (mode_is_data(mode)) {
4667 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4671 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4675 * Transform the Projs from a Cmp.
4677 static ir_node *gen_Proj_Cmp(ir_node *node)
4679 /* this probably means not all mode_b nodes were lowered... */
4680 panic("trying to directly transform Proj_Cmp %+F (mode_b not lowered?)",
4685 * Transform and potentially renumber Proj nodes.
4687 static ir_node *gen_Proj(ir_node *node) {
4688 ir_graph *irg = current_ir_graph;
4689 dbg_info *dbgi = get_irn_dbg_info(node);
4690 ir_node *pred = get_Proj_pred(node);
4691 long proj = get_Proj_proj(node);
4693 if (is_Store(pred)) {
4694 if (proj == pn_Store_M) {
4695 return be_transform_node(pred);
4698 return new_r_Bad(irg);
4700 } else if (is_Load(pred)) {
4701 return gen_Proj_Load(node);
4702 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4703 return gen_Proj_DivMod(node);
4704 } else if (is_CopyB(pred)) {
4705 return gen_Proj_CopyB(node);
4706 } else if (is_Quot(pred)) {
4707 return gen_Proj_Quot(node);
4708 } else if (be_is_SubSP(pred)) {
4709 return gen_Proj_be_SubSP(node);
4710 } else if (be_is_AddSP(pred)) {
4711 return gen_Proj_be_AddSP(node);
4712 } else if (be_is_Call(pred)) {
4713 return gen_Proj_be_Call(node);
4714 } else if (is_Cmp(pred)) {
4715 return gen_Proj_Cmp(node);
4716 } else if (get_irn_op(pred) == op_Start) {
4717 if (proj == pn_Start_X_initial_exec) {
4718 ir_node *block = get_nodes_block(pred);
4721 /* we exchange the ProjX with a jump */
4722 block = be_transform_node(block);
4723 jump = new_rd_Jmp(dbgi, irg, block);
4726 if (node == be_get_old_anchor(anchor_tls)) {
4727 return gen_Proj_tls(node);
4730 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4734 ir_node *new_pred = be_transform_node(pred);
4735 ir_node *block = be_transform_node(get_nodes_block(node));
4736 ir_mode *mode = get_irn_mode(node);
4737 if (mode_needs_gp_reg(mode)) {
4738 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4739 get_Proj_proj(node));
4740 #ifdef DEBUG_libfirm
4741 new_proj->node_nr = node->node_nr;
4747 return be_duplicate_node(node);
4751 * Enters all transform functions into the generic pointer
4753 static void register_transformers(void)
4757 /* first clear the generic function pointer for all ops */
4758 clear_irp_opcodes_generic_func();
4760 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4761 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4799 /* transform ops from intrinsic lowering */
4815 GEN(ia32_l_LLtoFloat);
4816 GEN(ia32_l_FloattoLL);
4822 /* we should never see these nodes */
4837 /* handle generic backend nodes */
4846 op_Mulh = get_op_Mulh();
4855 * Pre-transform all unknown and noreg nodes.
4857 static void ia32_pretransform_node(void *arch_cg) {
4858 ia32_code_gen_t *cg = arch_cg;
4860 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4861 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4862 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4863 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4864 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4865 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4870 * Walker, checks if all ia32 nodes producing more than one result have
4871 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4873 static void add_missing_keep_walker(ir_node *node, void *data)
4876 unsigned found_projs = 0;
4877 const ir_edge_t *edge;
4878 ir_mode *mode = get_irn_mode(node);
4883 if(!is_ia32_irn(node))
4886 n_outs = get_ia32_n_res(node);
4889 if(is_ia32_SwitchJmp(node))
4892 assert(n_outs < (int) sizeof(unsigned) * 8);
4893 foreach_out_edge(node, edge) {
4894 ir_node *proj = get_edge_src_irn(edge);
4895 int pn = get_Proj_proj(proj);
4897 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4898 found_projs |= 1 << pn;
4902 /* are keeps missing? */
4904 for(i = 0; i < n_outs; ++i) {
4907 const arch_register_req_t *req;
4908 const arch_register_class_t *class;
4910 if(found_projs & (1 << i)) {
4914 req = get_ia32_out_req(node, i);
4919 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4923 block = get_nodes_block(node);
4924 in[0] = new_r_Proj(current_ir_graph, block, node,
4925 arch_register_class_mode(class), i);
4926 if(last_keep != NULL) {
4927 be_Keep_add_node(last_keep, class, in[0]);
4929 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4930 if(sched_is_scheduled(node)) {
4931 sched_add_after(node, last_keep);
4938 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4941 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4943 ir_graph *irg = be_get_birg_irg(cg->birg);
4944 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4947 /* do the transformation */
4948 void ia32_transform_graph(ia32_code_gen_t *cg) {
4950 ir_graph *irg = cg->irg;
4952 register_transformers();
4954 initial_fpcw = NULL;
4956 BE_TIMER_PUSH(t_heights);
4957 heights = heights_new(irg);
4958 BE_TIMER_POP(t_heights);
4959 ia32_calculate_non_address_mode_nodes(cg->birg);
4961 /* the transform phase is not safe for CSE (yet) because several nodes get
4962 * attributes set after their creation */
4963 cse_last = get_opt_cse();
4966 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4968 set_opt_cse(cse_last);
4970 ia32_free_non_address_mode_nodes();
4971 heights_free(heights);
4975 void ia32_init_transform(void)
4977 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");