2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode.h"
52 #include "../besched.h"
54 #include "../beutil.h"
56 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_common_transform.h"
61 #include "ia32_nodes_attr.h"
62 #include "ia32_transform.h"
63 #include "ia32_new_nodes.h"
64 #include "ia32_map_regs.h"
65 #include "ia32_dbg_stat.h"
66 #include "ia32_optimize.h"
67 #include "ia32_util.h"
68 #include "ia32_address_mode.h"
69 #include "ia32_architecture.h"
71 #include "gen_ia32_regalloc_if.h"
73 /* define this to construct SSE constants instead of load them */
74 #undef CONSTRUCT_SSE_CONST
77 #define SFP_SIGN "0x80000000"
78 #define DFP_SIGN "0x8000000000000000"
79 #define SFP_ABS "0x7FFFFFFF"
80 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
81 #define DFP_INTMAX "9223372036854775807"
82 #define ULL_BIAS "18446744073709551616"
84 #define ENT_SFP_SIGN ".LC_ia32_sfp_sign"
85 #define ENT_DFP_SIGN ".LC_ia32_dfp_sign"
86 #define ENT_SFP_ABS ".LC_ia32_sfp_abs"
87 #define ENT_DFP_ABS ".LC_ia32_dfp_abs"
88 #define ENT_ULL_BIAS ".LC_ia32_ull_bias"
90 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
91 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
93 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
95 static ir_node *initial_fpcw = NULL;
98 typedef ir_node *construct_binop_func(dbg_info *db, ir_node *block,
99 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1,
102 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_node *block,
103 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2,
106 typedef ir_node *construct_shift_func(dbg_info *db, ir_node *block,
107 ir_node *op1, ir_node *op2);
109 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_node *block,
110 ir_node *base, ir_node *index, ir_node *mem, ir_node *op);
112 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_node *block,
113 ir_node *base, ir_node *index, ir_node *mem);
115 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_node *block,
116 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2,
119 typedef ir_node *construct_unop_func(dbg_info *db, ir_node *block, ir_node *op);
121 static ir_node *create_immediate_or_transform(ir_node *node,
122 char immediate_constraint_type);
124 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
125 dbg_info *dbgi, ir_node *block,
126 ir_node *op, ir_node *orig_node);
128 /* its enough to have those once */
129 static ir_node *nomem, *noreg_GP;
131 /** a list to postprocess all calls */
132 static ir_node **call_list;
133 static ir_type **call_types;
135 /** Return non-zero is a node represents the 0 constant. */
136 static bool is_Const_0(ir_node *node)
138 return is_Const(node) && is_Const_null(node);
141 /** Return non-zero is a node represents the 1 constant. */
142 static bool is_Const_1(ir_node *node)
144 return is_Const(node) && is_Const_one(node);
147 /** Return non-zero is a node represents the -1 constant. */
148 static bool is_Const_Minus_1(ir_node *node)
150 return is_Const(node) && is_Const_all_one(node);
154 * returns true if constant can be created with a simple float command
156 static bool is_simple_x87_Const(ir_node *node)
158 tarval *tv = get_Const_tarval(node);
159 if (tarval_is_null(tv) || tarval_is_one(tv))
162 /* TODO: match all the other float constants */
167 * returns true if constant can be created with a simple float command
169 static bool is_simple_sse_Const(ir_node *node)
171 tarval *tv = get_Const_tarval(node);
172 ir_mode *mode = get_tarval_mode(tv);
177 if (tarval_is_null(tv)
178 #ifdef CONSTRUCT_SSE_CONST
183 #ifdef CONSTRUCT_SSE_CONST
184 if (mode == mode_D) {
185 unsigned val = get_tarval_sub_bits(tv, 0) |
186 (get_tarval_sub_bits(tv, 1) << 8) |
187 (get_tarval_sub_bits(tv, 2) << 16) |
188 (get_tarval_sub_bits(tv, 3) << 24);
190 /* lower 32bit are zero, really a 32bit constant */
193 #endif /* CONSTRUCT_SSE_CONST */
194 /* TODO: match all the other float constants */
199 * Transforms a Const.
201 static ir_node *gen_Const(ir_node *node)
203 ir_node *old_block = get_nodes_block(node);
204 ir_node *block = be_transform_node(old_block);
205 dbg_info *dbgi = get_irn_dbg_info(node);
206 ir_mode *mode = get_irn_mode(node);
208 assert(is_Const(node));
210 if (mode_is_float(mode)) {
215 if (ia32_cg_config.use_sse2) {
216 tarval *tv = get_Const_tarval(node);
217 if (tarval_is_null(tv)) {
218 load = new_bd_ia32_xZero(dbgi, block);
219 set_ia32_ls_mode(load, mode);
221 #ifdef CONSTRUCT_SSE_CONST
222 } else if (tarval_is_one(tv)) {
223 int cnst = mode == mode_F ? 26 : 55;
224 ir_node *imm1 = ia32_create_Immediate(NULL, 0, cnst);
225 ir_node *imm2 = ia32_create_Immediate(NULL, 0, 2);
226 ir_node *pslld, *psrld;
228 load = new_bd_ia32_xAllOnes(dbgi, block);
229 set_ia32_ls_mode(load, mode);
230 pslld = new_bd_ia32_xPslld(dbgi, block, load, imm1);
231 set_ia32_ls_mode(pslld, mode);
232 psrld = new_bd_ia32_xPsrld(dbgi, block, pslld, imm2);
233 set_ia32_ls_mode(psrld, mode);
235 #endif /* CONSTRUCT_SSE_CONST */
236 } else if (mode == mode_F) {
237 /* we can place any 32bit constant by using a movd gp, sse */
238 unsigned val = get_tarval_sub_bits(tv, 0) |
239 (get_tarval_sub_bits(tv, 1) << 8) |
240 (get_tarval_sub_bits(tv, 2) << 16) |
241 (get_tarval_sub_bits(tv, 3) << 24);
242 ir_node *cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
243 load = new_bd_ia32_xMovd(dbgi, block, cnst);
244 set_ia32_ls_mode(load, mode);
247 #ifdef CONSTRUCT_SSE_CONST
248 if (mode == mode_D) {
249 unsigned val = get_tarval_sub_bits(tv, 0) |
250 (get_tarval_sub_bits(tv, 1) << 8) |
251 (get_tarval_sub_bits(tv, 2) << 16) |
252 (get_tarval_sub_bits(tv, 3) << 24);
254 ir_node *imm32 = ia32_create_Immediate(NULL, 0, 32);
255 ir_node *cnst, *psllq;
257 /* fine, lower 32bit are zero, produce 32bit value */
258 val = get_tarval_sub_bits(tv, 4) |
259 (get_tarval_sub_bits(tv, 5) << 8) |
260 (get_tarval_sub_bits(tv, 6) << 16) |
261 (get_tarval_sub_bits(tv, 7) << 24);
262 cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
263 load = new_bd_ia32_xMovd(dbgi, block, cnst);
264 set_ia32_ls_mode(load, mode);
265 psllq = new_bd_ia32_xPsllq(dbgi, block, load, imm32);
266 set_ia32_ls_mode(psllq, mode);
271 #endif /* CONSTRUCT_SSE_CONST */
272 floatent = create_float_const_entity(node);
274 load = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode);
275 set_ia32_op_type(load, ia32_AddrModeS);
276 set_ia32_am_sc(load, floatent);
277 arch_irn_add_flags(load, arch_irn_flags_rematerializable);
278 res = new_r_Proj(block, load, mode_xmm, pn_ia32_xLoad_res);
281 if (is_Const_null(node)) {
282 load = new_bd_ia32_vfldz(dbgi, block);
284 set_ia32_ls_mode(load, mode);
285 } else if (is_Const_one(node)) {
286 load = new_bd_ia32_vfld1(dbgi, block);
288 set_ia32_ls_mode(load, mode);
292 floatent = create_float_const_entity(node);
293 /* create_float_const_ent is smart and sometimes creates
295 ls_mode = get_type_mode(get_entity_type(floatent));
297 load = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem,
299 set_ia32_op_type(load, ia32_AddrModeS);
300 set_ia32_am_sc(load, floatent);
301 arch_irn_add_flags(load, arch_irn_flags_rematerializable);
302 res = new_r_Proj(block, load, mode_vfp, pn_ia32_vfld_res);
305 #ifdef CONSTRUCT_SSE_CONST
307 #endif /* CONSTRUCT_SSE_CONST */
308 SET_IA32_ORIG_NODE(load, node);
310 be_dep_on_frame(load);
312 } else { /* non-float mode */
314 tarval *tv = get_Const_tarval(node);
317 tv = tarval_convert_to(tv, mode_Iu);
319 if (tv == get_tarval_bad() || tv == get_tarval_undefined() ||
321 panic("couldn't convert constant tarval (%+F)", node);
323 val = get_tarval_long(tv);
325 cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
326 SET_IA32_ORIG_NODE(cnst, node);
328 be_dep_on_frame(cnst);
334 * Transforms a SymConst.
336 static ir_node *gen_SymConst(ir_node *node)
338 ir_node *old_block = get_nodes_block(node);
339 ir_node *block = be_transform_node(old_block);
340 dbg_info *dbgi = get_irn_dbg_info(node);
341 ir_mode *mode = get_irn_mode(node);
344 if (mode_is_float(mode)) {
345 if (ia32_cg_config.use_sse2)
346 cnst = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E);
348 cnst = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E);
349 set_ia32_am_sc(cnst, get_SymConst_entity(node));
350 set_ia32_use_frame(cnst);
354 if (get_SymConst_kind(node) != symconst_addr_ent) {
355 panic("backend only support symconst_addr_ent (at %+F)", node);
357 entity = get_SymConst_entity(node);
358 cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0, 0);
361 SET_IA32_ORIG_NODE(cnst, node);
363 be_dep_on_frame(cnst);
368 * Create a float type for the given mode and cache it.
370 * @param mode the mode for the float type (might be integer mode for SSE2 types)
371 * @param align alignment
373 static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align)
379 if (mode == mode_Iu) {
380 static ir_type *int_Iu[16] = {NULL, };
382 if (int_Iu[align] == NULL) {
383 int_Iu[align] = tp = new_type_primitive(mode);
384 /* set the specified alignment */
385 set_type_alignment_bytes(tp, align);
387 return int_Iu[align];
388 } else if (mode == mode_Lu) {
389 static ir_type *int_Lu[16] = {NULL, };
391 if (int_Lu[align] == NULL) {
392 int_Lu[align] = tp = new_type_primitive(mode);
393 /* set the specified alignment */
394 set_type_alignment_bytes(tp, align);
396 return int_Lu[align];
397 } else if (mode == mode_F) {
398 static ir_type *float_F[16] = {NULL, };
400 if (float_F[align] == NULL) {
401 float_F[align] = tp = new_type_primitive(mode);
402 /* set the specified alignment */
403 set_type_alignment_bytes(tp, align);
405 return float_F[align];
406 } else if (mode == mode_D) {
407 static ir_type *float_D[16] = {NULL, };
409 if (float_D[align] == NULL) {
410 float_D[align] = tp = new_type_primitive(mode);
411 /* set the specified alignment */
412 set_type_alignment_bytes(tp, align);
414 return float_D[align];
416 static ir_type *float_E[16] = {NULL, };
418 if (float_E[align] == NULL) {
419 float_E[align] = tp = new_type_primitive(mode);
420 /* set the specified alignment */
421 set_type_alignment_bytes(tp, align);
423 return float_E[align];
428 * Create a float[2] array type for the given atomic type.
430 * @param tp the atomic type
432 static ir_type *ia32_create_float_array(ir_type *tp)
434 ir_mode *mode = get_type_mode(tp);
435 unsigned align = get_type_alignment_bytes(tp);
440 if (mode == mode_F) {
441 static ir_type *float_F[16] = {NULL, };
443 if (float_F[align] != NULL)
444 return float_F[align];
445 arr = float_F[align] = new_type_array(1, tp);
446 } else if (mode == mode_D) {
447 static ir_type *float_D[16] = {NULL, };
449 if (float_D[align] != NULL)
450 return float_D[align];
451 arr = float_D[align] = new_type_array(1, tp);
453 static ir_type *float_E[16] = {NULL, };
455 if (float_E[align] != NULL)
456 return float_E[align];
457 arr = float_E[align] = new_type_array(1, tp);
459 set_type_alignment_bytes(arr, align);
460 set_type_size_bytes(arr, 2 * get_type_size_bytes(tp));
461 set_type_state(arr, layout_fixed);
465 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
466 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct)
468 static const struct {
469 const char *ent_name;
470 const char *cnst_str;
473 } names [ia32_known_const_max] = {
474 { ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
475 { ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
476 { ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
477 { ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
478 { ENT_ULL_BIAS, ULL_BIAS, 2, 4 } /* ia32_ULLBIAS */
480 static ir_entity *ent_cache[ia32_known_const_max];
482 const char *ent_name, *cnst_str;
488 ent_name = names[kct].ent_name;
489 if (! ent_cache[kct]) {
490 cnst_str = names[kct].cnst_str;
492 switch (names[kct].mode) {
493 case 0: mode = mode_Iu; break;
494 case 1: mode = mode_Lu; break;
495 default: mode = mode_F; break;
497 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
498 tp = ia32_create_float_type(mode, names[kct].align);
500 if (kct == ia32_ULLBIAS)
501 tp = ia32_create_float_array(tp);
502 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
504 set_entity_ld_ident(ent, get_entity_ident(ent));
505 set_entity_visibility(ent, visibility_local);
506 set_entity_variability(ent, variability_constant);
507 set_entity_allocation(ent, allocation_static);
509 if (kct == ia32_ULLBIAS) {
510 ir_initializer_t *initializer = create_initializer_compound(2);
512 set_initializer_compound_value(initializer, 0,
513 create_initializer_tarval(get_tarval_null(mode)));
514 set_initializer_compound_value(initializer, 1,
515 create_initializer_tarval(tv));
517 set_entity_initializer(ent, initializer);
519 set_entity_initializer(ent, create_initializer_tarval(tv));
522 /* cache the entry */
523 ent_cache[kct] = ent;
526 return ent_cache[kct];
530 * return true if the node is a Proj(Load) and could be used in source address
531 * mode for another node. Will return only true if the @p other node is not
532 * dependent on the memory of the Load (for binary operations use the other
533 * input here, for unary operations use NULL).
535 static int ia32_use_source_address_mode(ir_node *block, ir_node *node,
536 ir_node *other, ir_node *other2, match_flags_t flags)
541 /* float constants are always available */
542 if (is_Const(node)) {
543 ir_mode *mode = get_irn_mode(node);
544 if (mode_is_float(mode)) {
545 if (ia32_cg_config.use_sse2) {
546 if (is_simple_sse_Const(node))
549 if (is_simple_x87_Const(node))
552 if (get_irn_n_edges(node) > 1)
560 load = get_Proj_pred(node);
561 pn = get_Proj_proj(node);
562 if (!is_Load(load) || pn != pn_Load_res)
564 if (get_nodes_block(load) != block)
566 /* we only use address mode if we're the only user of the load */
567 if (get_irn_n_edges(node) != (flags & match_two_users ? 2 : 1))
569 /* in some edge cases with address mode we might reach the load normally
570 * and through some AM sequence, if it is already materialized then we
571 * can't create an AM node from it */
572 if (be_is_transformed(node))
575 /* don't do AM if other node inputs depend on the load (via mem-proj) */
576 if (other != NULL && prevents_AM(block, load, other))
579 if (other2 != NULL && prevents_AM(block, load, other2))
585 typedef struct ia32_address_mode_t ia32_address_mode_t;
586 struct ia32_address_mode_t {
591 ia32_op_type_t op_type;
595 unsigned commutative : 1;
596 unsigned ins_permuted : 1;
599 static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
601 /* construct load address */
602 memset(addr, 0, sizeof(addr[0]));
603 ia32_create_address_mode(addr, ptr, 0);
605 addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP;
606 addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP;
607 addr->mem = be_transform_node(mem);
610 static void build_address(ia32_address_mode_t *am, ir_node *node,
611 ia32_create_am_flags_t flags)
613 ia32_address_t *addr = &am->addr;
619 if (is_Const(node)) {
620 ir_entity *entity = create_float_const_entity(node);
621 addr->base = noreg_GP;
622 addr->index = noreg_GP;
624 addr->symconst_ent = entity;
626 am->ls_mode = get_type_mode(get_entity_type(entity));
627 am->pinned = op_pin_state_floats;
631 load = get_Proj_pred(node);
632 ptr = get_Load_ptr(load);
633 mem = get_Load_mem(load);
634 new_mem = be_transform_node(mem);
635 am->pinned = get_irn_pinned(load);
636 am->ls_mode = get_Load_mode(load);
637 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
640 /* construct load address */
641 ia32_create_address_mode(addr, ptr, flags);
643 addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP;
644 addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP;
648 static void set_address(ir_node *node, const ia32_address_t *addr)
650 set_ia32_am_scale(node, addr->scale);
651 set_ia32_am_sc(node, addr->symconst_ent);
652 set_ia32_am_offs_int(node, addr->offset);
653 if (addr->symconst_sign)
654 set_ia32_am_sc_sign(node);
656 set_ia32_use_frame(node);
657 set_ia32_frame_ent(node, addr->frame_entity);
661 * Apply attributes of a given address mode to a node.
663 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
665 set_address(node, &am->addr);
667 set_ia32_op_type(node, am->op_type);
668 set_ia32_ls_mode(node, am->ls_mode);
669 if (am->pinned == op_pin_state_pinned) {
670 /* beware: some nodes are already pinned and did not allow to change the state */
671 if (get_irn_pinned(node) != op_pin_state_pinned)
672 set_irn_pinned(node, op_pin_state_pinned);
675 set_ia32_commutative(node);
679 * Check, if a given node is a Down-Conv, ie. a integer Conv
680 * from a mode with a mode with more bits to a mode with lesser bits.
681 * Moreover, we return only true if the node has not more than 1 user.
683 * @param node the node
684 * @return non-zero if node is a Down-Conv
686 static int is_downconv(const ir_node *node)
694 /* we only want to skip the conv when we're the only user
695 * (not optimal but for now...)
697 if (get_irn_n_edges(node) > 1)
700 src_mode = get_irn_mode(get_Conv_op(node));
701 dest_mode = get_irn_mode(node);
703 ia32_mode_needs_gp_reg(src_mode) &&
704 ia32_mode_needs_gp_reg(dest_mode) &&
705 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
708 /* Skip all Down-Conv's on a given node and return the resulting node. */
709 ir_node *ia32_skip_downconv(ir_node *node)
711 while (is_downconv(node))
712 node = get_Conv_op(node);
717 static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
719 ir_mode *mode = get_irn_mode(node);
724 if (mode_is_signed(mode)) {
729 block = get_nodes_block(node);
730 dbgi = get_irn_dbg_info(node);
732 return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
736 * matches operands of a node into ia32 addressing/operand modes. This covers
737 * usage of source address mode, immediates, operations with non 32-bit modes,
739 * The resulting data is filled into the @p am struct. block is the block
740 * of the node whose arguments are matched. op1, op2 are the first and second
741 * input that are matched (op1 may be NULL). other_op is another unrelated
742 * input that is not matched! but which is needed sometimes to check if AM
743 * for op1/op2 is legal.
744 * @p flags describes the supported modes of the operation in detail.
746 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
747 ir_node *op1, ir_node *op2, ir_node *other_op,
750 ia32_address_t *addr = &am->addr;
751 ir_mode *mode = get_irn_mode(op2);
752 int mode_bits = get_mode_size_bits(mode);
753 ir_node *new_op1, *new_op2;
755 unsigned commutative;
756 int use_am_and_immediates;
759 memset(am, 0, sizeof(am[0]));
761 commutative = (flags & match_commutative) != 0;
762 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
763 use_am = (flags & match_am) != 0;
764 use_immediate = (flags & match_immediate) != 0;
765 assert(!use_am_and_immediates || use_immediate);
768 assert(!commutative || op1 != NULL);
769 assert(use_am || !(flags & match_8bit_am));
770 assert(use_am || !(flags & match_16bit_am));
772 if ((mode_bits == 8 && !(flags & match_8bit_am)) ||
773 (mode_bits == 16 && !(flags & match_16bit_am))) {
777 /* we can simply skip downconvs for mode neutral nodes: the upper bits
778 * can be random for these operations */
779 if (flags & match_mode_neutral) {
780 op2 = ia32_skip_downconv(op2);
782 op1 = ia32_skip_downconv(op1);
786 /* match immediates. firm nodes are normalized: constants are always on the
789 if (!(flags & match_try_am) && use_immediate) {
790 new_op2 = try_create_Immediate(op2, 0);
793 if (new_op2 == NULL &&
794 use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) {
795 build_address(am, op2, 0);
796 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
797 if (mode_is_float(mode)) {
798 new_op2 = ia32_new_NoReg_vfp(env_cg);
802 am->op_type = ia32_AddrModeS;
803 } else if (commutative && (new_op2 == NULL || use_am_and_immediates) &&
805 ia32_use_source_address_mode(block, op1, op2, other_op, flags)) {
807 build_address(am, op1, 0);
809 if (mode_is_float(mode)) {
810 noreg = ia32_new_NoReg_vfp(env_cg);
815 if (new_op2 != NULL) {
818 new_op1 = be_transform_node(op2);
820 am->ins_permuted = 1;
822 am->op_type = ia32_AddrModeS;
825 am->op_type = ia32_Normal;
827 if (flags & match_try_am) {
833 mode = get_irn_mode(op2);
834 if (flags & match_upconv_32 && get_mode_size_bits(mode) != 32) {
835 new_op1 = (op1 == NULL ? NULL : create_upconv(op1, NULL));
837 new_op2 = create_upconv(op2, NULL);
838 am->ls_mode = mode_Iu;
840 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
842 new_op2 = be_transform_node(op2);
843 am->ls_mode = (flags & match_mode_neutral) ? mode_Iu : mode;
846 if (addr->base == NULL)
847 addr->base = noreg_GP;
848 if (addr->index == NULL)
849 addr->index = noreg_GP;
850 if (addr->mem == NULL)
853 am->new_op1 = new_op1;
854 am->new_op2 = new_op2;
855 am->commutative = commutative;
859 * "Fixes" a node that uses address mode by turning it into mode_T
860 * and returning a pn_ia32_res Proj.
862 * @param node the node
863 * @param am its address mode
865 * @return a Proj(pn_ia32_res) if a memory address mode is used,
868 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
873 if (am->mem_proj == NULL)
876 /* we have to create a mode_T so the old MemProj can attach to us */
877 mode = get_irn_mode(node);
878 load = get_Proj_pred(am->mem_proj);
880 be_set_transformed_node(load, node);
882 if (mode != mode_T) {
883 set_irn_mode(node, mode_T);
884 return new_rd_Proj(NULL, get_nodes_block(node), node, mode, pn_ia32_res);
891 * Construct a standard binary operation, set AM and immediate if required.
893 * @param node The original node for which the binop is created
894 * @param op1 The first operand
895 * @param op2 The second operand
896 * @param func The node constructor function
897 * @return The constructed ia32 node.
899 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
900 construct_binop_func *func, match_flags_t flags)
903 ir_node *block, *new_block, *new_node;
904 ia32_address_mode_t am;
905 ia32_address_t *addr = &am.addr;
907 block = get_nodes_block(node);
908 match_arguments(&am, block, op1, op2, NULL, flags);
910 dbgi = get_irn_dbg_info(node);
911 new_block = be_transform_node(block);
912 new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem,
913 am.new_op1, am.new_op2);
914 set_am_attributes(new_node, &am);
915 /* we can't use source address mode anymore when using immediates */
916 if (!(flags & match_am_and_immediates) &&
917 (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)))
918 set_ia32_am_support(new_node, ia32_am_none);
919 SET_IA32_ORIG_NODE(new_node, node);
921 new_node = fix_mem_proj(new_node, &am);
927 * Generic names for the inputs of an ia32 binary op.
930 n_ia32_l_binop_left, /**< ia32 left input */
931 n_ia32_l_binop_right, /**< ia32 right input */
932 n_ia32_l_binop_eflags /**< ia32 eflags input */
934 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
935 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
936 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
937 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_minuend, n_Sbb_minuend)
938 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend)
939 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
942 * Construct a binary operation which also consumes the eflags.
944 * @param node The node to transform
945 * @param func The node constructor function
946 * @param flags The match flags
947 * @return The constructor ia32 node
949 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
952 ir_node *src_block = get_nodes_block(node);
953 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
954 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
955 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
957 ir_node *block, *new_node, *new_eflags;
958 ia32_address_mode_t am;
959 ia32_address_t *addr = &am.addr;
961 match_arguments(&am, src_block, op1, op2, eflags, flags);
963 dbgi = get_irn_dbg_info(node);
964 block = be_transform_node(src_block);
965 new_eflags = be_transform_node(eflags);
966 new_node = func(dbgi, block, addr->base, addr->index, addr->mem,
967 am.new_op1, am.new_op2, new_eflags);
968 set_am_attributes(new_node, &am);
969 /* we can't use source address mode anymore when using immediates */
970 if (!(flags & match_am_and_immediates) &&
971 (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)))
972 set_ia32_am_support(new_node, ia32_am_none);
973 SET_IA32_ORIG_NODE(new_node, node);
975 new_node = fix_mem_proj(new_node, &am);
980 static ir_node *get_fpcw(void)
983 if (initial_fpcw != NULL)
986 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
987 &ia32_fp_cw_regs[REG_FPCW]);
988 initial_fpcw = be_transform_node(fpcw);
994 * Construct a standard binary operation, set AM and immediate if required.
996 * @param op1 The first operand
997 * @param op2 The second operand
998 * @param func The node constructor function
999 * @return The constructed ia32 node.
1001 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
1002 construct_binop_float_func *func)
1004 ir_mode *mode = get_irn_mode(node);
1006 ir_node *block, *new_block, *new_node;
1007 ia32_address_mode_t am;
1008 ia32_address_t *addr = &am.addr;
1009 ia32_x87_attr_t *attr;
1010 /* All operations are considered commutative, because there are reverse
1012 match_flags_t flags = match_commutative;
1014 /* happens for div nodes... */
1016 mode = get_divop_resmod(node);
1018 /* cannot use address mode with long double on x87 */
1019 if (get_mode_size_bits(mode) <= 64)
1022 block = get_nodes_block(node);
1023 match_arguments(&am, block, op1, op2, NULL, flags);
1025 dbgi = get_irn_dbg_info(node);
1026 new_block = be_transform_node(block);
1027 new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem,
1028 am.new_op1, am.new_op2, get_fpcw());
1029 set_am_attributes(new_node, &am);
1031 attr = get_ia32_x87_attr(new_node);
1032 attr->attr.data.ins_permuted = am.ins_permuted;
1034 SET_IA32_ORIG_NODE(new_node, node);
1036 new_node = fix_mem_proj(new_node, &am);
1042 * Construct a shift/rotate binary operation, sets AM and immediate if required.
1044 * @param op1 The first operand
1045 * @param op2 The second operand
1046 * @param func The node constructor function
1047 * @return The constructed ia32 node.
1049 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
1050 construct_shift_func *func,
1051 match_flags_t flags)
1054 ir_node *block, *new_block, *new_op1, *new_op2, *new_node;
1056 assert(! mode_is_float(get_irn_mode(node)));
1057 assert(flags & match_immediate);
1058 assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
1060 if (flags & match_mode_neutral) {
1061 op1 = ia32_skip_downconv(op1);
1062 new_op1 = be_transform_node(op1);
1063 } else if (get_mode_size_bits(get_irn_mode(node)) != 32) {
1064 new_op1 = create_upconv(op1, node);
1066 new_op1 = be_transform_node(op1);
1069 /* the shift amount can be any mode that is bigger than 5 bits, since all
1070 * other bits are ignored anyway */
1071 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
1072 ir_node *const op = get_Conv_op(op2);
1073 if (mode_is_float(get_irn_mode(op)))
1076 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
1078 new_op2 = create_immediate_or_transform(op2, 0);
1080 dbgi = get_irn_dbg_info(node);
1081 block = get_nodes_block(node);
1082 new_block = be_transform_node(block);
1083 new_node = func(dbgi, new_block, new_op1, new_op2);
1084 SET_IA32_ORIG_NODE(new_node, node);
1086 /* lowered shift instruction may have a dependency operand, handle it here */
1087 if (get_irn_arity(node) == 3) {
1088 /* we have a dependency */
1089 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
1090 add_irn_dep(new_node, new_dep);
1098 * Construct a standard unary operation, set AM and immediate if required.
1100 * @param op The operand
1101 * @param func The node constructor function
1102 * @return The constructed ia32 node.
1104 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
1105 match_flags_t flags)
1108 ir_node *block, *new_block, *new_op, *new_node;
1110 assert(flags == 0 || flags == match_mode_neutral);
1111 if (flags & match_mode_neutral) {
1112 op = ia32_skip_downconv(op);
1115 new_op = be_transform_node(op);
1116 dbgi = get_irn_dbg_info(node);
1117 block = get_nodes_block(node);
1118 new_block = be_transform_node(block);
1119 new_node = func(dbgi, new_block, new_op);
1121 SET_IA32_ORIG_NODE(new_node, node);
1126 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
1127 ia32_address_t *addr)
1129 ir_node *base, *index, *res;
1135 base = be_transform_node(base);
1138 index = addr->index;
1139 if (index == NULL) {
1142 index = be_transform_node(index);
1145 res = new_bd_ia32_Lea(dbgi, block, base, index);
1146 set_address(res, addr);
1152 * Returns non-zero if a given address mode has a symbolic or
1153 * numerical offset != 0.
1155 static int am_has_immediates(const ia32_address_t *addr)
1157 return addr->offset != 0 || addr->symconst_ent != NULL
1158 || addr->frame_entity || addr->use_frame;
1162 * Creates an ia32 Add.
1164 * @return the created ia32 Add node
1166 static ir_node *gen_Add(ir_node *node)
1168 ir_mode *mode = get_irn_mode(node);
1169 ir_node *op1 = get_Add_left(node);
1170 ir_node *op2 = get_Add_right(node);
1172 ir_node *block, *new_block, *new_node, *add_immediate_op;
1173 ia32_address_t addr;
1174 ia32_address_mode_t am;
1176 if (mode_is_float(mode)) {
1177 if (ia32_cg_config.use_sse2)
1178 return gen_binop(node, op1, op2, new_bd_ia32_xAdd,
1179 match_commutative | match_am);
1181 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfadd);
1184 ia32_mark_non_am(node);
1186 op2 = ia32_skip_downconv(op2);
1187 op1 = ia32_skip_downconv(op1);
1191 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1192 * 1. Add with immediate -> Lea
1193 * 2. Add with possible source address mode -> Add
1194 * 3. Otherwise -> Lea
1196 memset(&addr, 0, sizeof(addr));
1197 ia32_create_address_mode(&addr, node, ia32_create_am_force);
1198 add_immediate_op = NULL;
1200 dbgi = get_irn_dbg_info(node);
1201 block = get_nodes_block(node);
1202 new_block = be_transform_node(block);
1205 if (addr.base == NULL && addr.index == NULL) {
1206 new_node = new_bd_ia32_Const(dbgi, new_block, addr.symconst_ent,
1207 addr.symconst_sign, 0, addr.offset);
1208 be_dep_on_frame(new_node);
1209 SET_IA32_ORIG_NODE(new_node, node);
1212 /* add with immediate? */
1213 if (addr.index == NULL) {
1214 add_immediate_op = addr.base;
1215 } else if (addr.base == NULL && addr.scale == 0) {
1216 add_immediate_op = addr.index;
1219 if (add_immediate_op != NULL) {
1220 if (!am_has_immediates(&addr)) {
1221 #ifdef DEBUG_libfirm
1222 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1225 return be_transform_node(add_immediate_op);
1228 new_node = create_lea_from_address(dbgi, new_block, &addr);
1229 SET_IA32_ORIG_NODE(new_node, node);
1233 /* test if we can use source address mode */
1234 match_arguments(&am, block, op1, op2, NULL, match_commutative
1235 | match_mode_neutral | match_am | match_immediate | match_try_am);
1237 /* construct an Add with source address mode */
1238 if (am.op_type == ia32_AddrModeS) {
1239 ia32_address_t *am_addr = &am.addr;
1240 new_node = new_bd_ia32_Add(dbgi, new_block, am_addr->base,
1241 am_addr->index, am_addr->mem, am.new_op1,
1243 set_am_attributes(new_node, &am);
1244 SET_IA32_ORIG_NODE(new_node, node);
1246 new_node = fix_mem_proj(new_node, &am);
1251 /* otherwise construct a lea */
1252 new_node = create_lea_from_address(dbgi, new_block, &addr);
1253 SET_IA32_ORIG_NODE(new_node, node);
1258 * Creates an ia32 Mul.
1260 * @return the created ia32 Mul node
1262 static ir_node *gen_Mul(ir_node *node)
1264 ir_node *op1 = get_Mul_left(node);
1265 ir_node *op2 = get_Mul_right(node);
1266 ir_mode *mode = get_irn_mode(node);
1268 if (mode_is_float(mode)) {
1269 if (ia32_cg_config.use_sse2)
1270 return gen_binop(node, op1, op2, new_bd_ia32_xMul,
1271 match_commutative | match_am);
1273 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfmul);
1275 return gen_binop(node, op1, op2, new_bd_ia32_IMul,
1276 match_commutative | match_am | match_mode_neutral |
1277 match_immediate | match_am_and_immediates);
1281 * Creates an ia32 Mulh.
1282 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1283 * this result while Mul returns the lower 32 bit.
1285 * @return the created ia32 Mulh node
1287 static ir_node *gen_Mulh(ir_node *node)
1289 ir_node *block = get_nodes_block(node);
1290 ir_node *new_block = be_transform_node(block);
1291 dbg_info *dbgi = get_irn_dbg_info(node);
1292 ir_node *op1 = get_Mulh_left(node);
1293 ir_node *op2 = get_Mulh_right(node);
1294 ir_mode *mode = get_irn_mode(node);
1296 ir_node *proj_res_high;
1298 if (get_mode_size_bits(mode) != 32) {
1299 panic("Mulh without 32bit size not supported in ia32 backend (%+F)", node);
1302 if (mode_is_signed(mode)) {
1303 new_node = gen_binop(node, op1, op2, new_bd_ia32_IMul1OP, match_commutative | match_am);
1304 proj_res_high = new_rd_Proj(dbgi, new_block, new_node, mode_Iu, pn_ia32_IMul1OP_res_high);
1306 new_node = gen_binop(node, op1, op2, new_bd_ia32_Mul, match_commutative | match_am);
1307 proj_res_high = new_rd_Proj(dbgi, new_block, new_node, mode_Iu, pn_ia32_Mul_res_high);
1309 return proj_res_high;
1313 * Creates an ia32 And.
1315 * @return The created ia32 And node
1317 static ir_node *gen_And(ir_node *node)
1319 ir_node *op1 = get_And_left(node);
1320 ir_node *op2 = get_And_right(node);
1321 assert(! mode_is_float(get_irn_mode(node)));
1323 /* is it a zero extension? */
1324 if (is_Const(op2)) {
1325 tarval *tv = get_Const_tarval(op2);
1326 long v = get_tarval_long(tv);
1328 if (v == 0xFF || v == 0xFFFF) {
1329 dbg_info *dbgi = get_irn_dbg_info(node);
1330 ir_node *block = get_nodes_block(node);
1337 assert(v == 0xFFFF);
1340 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1345 return gen_binop(node, op1, op2, new_bd_ia32_And,
1346 match_commutative | match_mode_neutral | match_am | match_immediate);
1352 * Creates an ia32 Or.
1354 * @return The created ia32 Or node
1356 static ir_node *gen_Or(ir_node *node)
1358 ir_node *op1 = get_Or_left(node);
1359 ir_node *op2 = get_Or_right(node);
1361 assert (! mode_is_float(get_irn_mode(node)));
1362 return gen_binop(node, op1, op2, new_bd_ia32_Or, match_commutative
1363 | match_mode_neutral | match_am | match_immediate);
1369 * Creates an ia32 Eor.
1371 * @return The created ia32 Eor node
1373 static ir_node *gen_Eor(ir_node *node)
1375 ir_node *op1 = get_Eor_left(node);
1376 ir_node *op2 = get_Eor_right(node);
1378 assert(! mode_is_float(get_irn_mode(node)));
1379 return gen_binop(node, op1, op2, new_bd_ia32_Xor, match_commutative
1380 | match_mode_neutral | match_am | match_immediate);
1385 * Creates an ia32 Sub.
1387 * @return The created ia32 Sub node
1389 static ir_node *gen_Sub(ir_node *node)
1391 ir_node *op1 = get_Sub_left(node);
1392 ir_node *op2 = get_Sub_right(node);
1393 ir_mode *mode = get_irn_mode(node);
1395 if (mode_is_float(mode)) {
1396 if (ia32_cg_config.use_sse2)
1397 return gen_binop(node, op1, op2, new_bd_ia32_xSub, match_am);
1399 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfsub);
1402 if (is_Const(op2)) {
1403 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1407 return gen_binop(node, op1, op2, new_bd_ia32_Sub, match_mode_neutral
1408 | match_am | match_immediate);
1411 static ir_node *transform_AM_mem(ir_node *const block,
1412 ir_node *const src_val,
1413 ir_node *const src_mem,
1414 ir_node *const am_mem)
1416 if (is_NoMem(am_mem)) {
1417 return be_transform_node(src_mem);
1418 } else if (is_Proj(src_val) &&
1420 get_Proj_pred(src_val) == get_Proj_pred(src_mem)) {
1421 /* avoid memory loop */
1423 } else if (is_Proj(src_val) && is_Sync(src_mem)) {
1424 ir_node *const ptr_pred = get_Proj_pred(src_val);
1425 int const arity = get_Sync_n_preds(src_mem);
1430 NEW_ARR_A(ir_node*, ins, arity + 1);
1432 /* NOTE: This sometimes produces dead-code because the old sync in
1433 * src_mem might not be used anymore, we should detect this case
1434 * and kill the sync... */
1435 for (i = arity - 1; i >= 0; --i) {
1436 ir_node *const pred = get_Sync_pred(src_mem, i);
1438 /* avoid memory loop */
1439 if (is_Proj(pred) && get_Proj_pred(pred) == ptr_pred)
1442 ins[n++] = be_transform_node(pred);
1447 return new_r_Sync(block, n, ins);
1451 ins[0] = be_transform_node(src_mem);
1453 return new_r_Sync(block, 2, ins);
1458 * Create a 32bit to 64bit signed extension.
1460 * @param dbgi debug info
1461 * @param block the block where node nodes should be placed
1462 * @param val the value to extend
1463 * @param orig the original node
1465 static ir_node *create_sex_32_64(dbg_info *dbgi, ir_node *block,
1466 ir_node *val, const ir_node *orig)
1471 if (ia32_cg_config.use_short_sex_eax) {
1472 ir_node *pval = new_bd_ia32_ProduceVal(dbgi, block);
1473 be_dep_on_frame(pval);
1474 res = new_bd_ia32_Cltd(dbgi, block, val, pval);
1476 ir_node *imm31 = ia32_create_Immediate(NULL, 0, 31);
1477 res = new_bd_ia32_Sar(dbgi, block, val, imm31);
1479 SET_IA32_ORIG_NODE(res, orig);
1484 * Generates an ia32 DivMod with additional infrastructure for the
1485 * register allocator if needed.
1487 static ir_node *create_Div(ir_node *node)
1489 dbg_info *dbgi = get_irn_dbg_info(node);
1490 ir_node *block = get_nodes_block(node);
1491 ir_node *new_block = be_transform_node(block);
1498 ir_node *sign_extension;
1499 ia32_address_mode_t am;
1500 ia32_address_t *addr = &am.addr;
1502 /* the upper bits have random contents for smaller modes */
1503 switch (get_irn_opcode(node)) {
1505 op1 = get_Div_left(node);
1506 op2 = get_Div_right(node);
1507 mem = get_Div_mem(node);
1508 mode = get_Div_resmode(node);
1511 op1 = get_Mod_left(node);
1512 op2 = get_Mod_right(node);
1513 mem = get_Mod_mem(node);
1514 mode = get_Mod_resmode(node);
1517 op1 = get_DivMod_left(node);
1518 op2 = get_DivMod_right(node);
1519 mem = get_DivMod_mem(node);
1520 mode = get_DivMod_resmode(node);
1523 panic("invalid divmod node %+F", node);
1526 match_arguments(&am, block, op1, op2, NULL, match_am | match_upconv_32);
1528 /* Beware: We don't need a Sync, if the memory predecessor of the Div node
1529 is the memory of the consumed address. We can have only the second op as address
1530 in Div nodes, so check only op2. */
1531 new_mem = transform_AM_mem(block, op2, mem, addr->mem);
1533 if (mode_is_signed(mode)) {
1534 sign_extension = create_sex_32_64(dbgi, new_block, am.new_op1, node);
1535 new_node = new_bd_ia32_IDiv(dbgi, new_block, addr->base,
1536 addr->index, new_mem, am.new_op2, am.new_op1, sign_extension);
1538 sign_extension = new_bd_ia32_Const(dbgi, new_block, NULL, 0, 0, 0);
1539 be_dep_on_frame(sign_extension);
1541 new_node = new_bd_ia32_Div(dbgi, new_block, addr->base,
1542 addr->index, new_mem, am.new_op2,
1543 am.new_op1, sign_extension);
1546 set_irn_pinned(new_node, get_irn_pinned(node));
1548 set_am_attributes(new_node, &am);
1549 SET_IA32_ORIG_NODE(new_node, node);
1551 new_node = fix_mem_proj(new_node, &am);
1557 * Generates an ia32 Mod.
1559 static ir_node *gen_Mod(ir_node *node)
1561 return create_Div(node);
1565 * Generates an ia32 Div.
1567 static ir_node *gen_Div(ir_node *node)
1569 return create_Div(node);
1573 * Generates an ia32 DivMod.
1575 static ir_node *gen_DivMod(ir_node *node)
1577 return create_Div(node);
1583 * Creates an ia32 floating Div.
1585 * @return The created ia32 xDiv node
1587 static ir_node *gen_Quot(ir_node *node)
1589 ir_node *op1 = get_Quot_left(node);
1590 ir_node *op2 = get_Quot_right(node);
1592 if (ia32_cg_config.use_sse2) {
1593 return gen_binop(node, op1, op2, new_bd_ia32_xDiv, match_am);
1595 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfdiv);
1601 * Creates an ia32 Shl.
1603 * @return The created ia32 Shl node
1605 static ir_node *gen_Shl(ir_node *node)
1607 ir_node *left = get_Shl_left(node);
1608 ir_node *right = get_Shl_right(node);
1610 return gen_shift_binop(node, left, right, new_bd_ia32_Shl,
1611 match_mode_neutral | match_immediate);
1615 * Creates an ia32 Shr.
1617 * @return The created ia32 Shr node
1619 static ir_node *gen_Shr(ir_node *node)
1621 ir_node *left = get_Shr_left(node);
1622 ir_node *right = get_Shr_right(node);
1624 return gen_shift_binop(node, left, right, new_bd_ia32_Shr, match_immediate);
1630 * Creates an ia32 Sar.
1632 * @return The created ia32 Shrs node
1634 static ir_node *gen_Shrs(ir_node *node)
1636 ir_node *left = get_Shrs_left(node);
1637 ir_node *right = get_Shrs_right(node);
1639 if (is_Const(right)) {
1640 tarval *tv = get_Const_tarval(right);
1641 long val = get_tarval_long(tv);
1643 /* this is a sign extension */
1644 dbg_info *dbgi = get_irn_dbg_info(node);
1645 ir_node *block = be_transform_node(get_nodes_block(node));
1646 ir_node *new_op = be_transform_node(left);
1648 return create_sex_32_64(dbgi, block, new_op, node);
1652 /* 8 or 16 bit sign extension? */
1653 if (is_Const(right) && is_Shl(left)) {
1654 ir_node *shl_left = get_Shl_left(left);
1655 ir_node *shl_right = get_Shl_right(left);
1656 if (is_Const(shl_right)) {
1657 tarval *tv1 = get_Const_tarval(right);
1658 tarval *tv2 = get_Const_tarval(shl_right);
1659 if (tv1 == tv2 && tarval_is_long(tv1)) {
1660 long val = get_tarval_long(tv1);
1661 if (val == 16 || val == 24) {
1662 dbg_info *dbgi = get_irn_dbg_info(node);
1663 ir_node *block = get_nodes_block(node);
1673 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1682 return gen_shift_binop(node, left, right, new_bd_ia32_Sar, match_immediate);
1688 * Creates an ia32 Rol.
1690 * @param op1 The first operator
1691 * @param op2 The second operator
1692 * @return The created ia32 RotL node
1694 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
1696 return gen_shift_binop(node, op1, op2, new_bd_ia32_Rol, match_immediate);
1702 * Creates an ia32 Ror.
1703 * NOTE: There is no RotR with immediate because this would always be a RotL
1704 * "imm-mode_size_bits" which can be pre-calculated.
1706 * @param op1 The first operator
1707 * @param op2 The second operator
1708 * @return The created ia32 RotR node
1710 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
1712 return gen_shift_binop(node, op1, op2, new_bd_ia32_Ror, match_immediate);
1718 * Creates an ia32 RotR or RotL (depending on the found pattern).
1720 * @return The created ia32 RotL or RotR node
1722 static ir_node *gen_Rotl(ir_node *node)
1724 ir_node *rotate = NULL;
1725 ir_node *op1 = get_Rotl_left(node);
1726 ir_node *op2 = get_Rotl_right(node);
1728 /* Firm has only RotL, so we are looking for a right (op2)
1729 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1730 that means we can create a RotR instead of an Add and a RotL */
1734 ir_node *left = get_Add_left(add);
1735 ir_node *right = get_Add_right(add);
1736 if (is_Const(right)) {
1737 tarval *tv = get_Const_tarval(right);
1738 ir_mode *mode = get_irn_mode(node);
1739 long bits = get_mode_size_bits(mode);
1741 if (is_Minus(left) &&
1742 tarval_is_long(tv) &&
1743 get_tarval_long(tv) == bits &&
1746 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1747 rotate = gen_Ror(node, op1, get_Minus_op(left));
1752 if (rotate == NULL) {
1753 rotate = gen_Rol(node, op1, op2);
1762 * Transforms a Minus node.
1764 * @return The created ia32 Minus node
1766 static ir_node *gen_Minus(ir_node *node)
1768 ir_node *op = get_Minus_op(node);
1769 ir_node *block = be_transform_node(get_nodes_block(node));
1770 dbg_info *dbgi = get_irn_dbg_info(node);
1771 ir_mode *mode = get_irn_mode(node);
1776 if (mode_is_float(mode)) {
1777 ir_node *new_op = be_transform_node(op);
1778 if (ia32_cg_config.use_sse2) {
1779 /* TODO: non-optimal... if we have many xXors, then we should
1780 * rather create a load for the const and use that instead of
1781 * several AM nodes... */
1782 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1784 new_node = new_bd_ia32_xXor(dbgi, block, noreg_GP, noreg_GP,
1785 nomem, new_op, noreg_xmm);
1787 size = get_mode_size_bits(mode);
1788 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1790 set_ia32_am_sc(new_node, ent);
1791 set_ia32_op_type(new_node, ia32_AddrModeS);
1792 set_ia32_ls_mode(new_node, mode);
1794 new_node = new_bd_ia32_vfchs(dbgi, block, new_op);
1797 new_node = gen_unop(node, op, new_bd_ia32_Neg, match_mode_neutral);
1800 SET_IA32_ORIG_NODE(new_node, node);
1806 * Transforms a Not node.
1808 * @return The created ia32 Not node
1810 static ir_node *gen_Not(ir_node *node)
1812 ir_node *op = get_Not_op(node);
1814 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1815 assert (! mode_is_float(get_irn_mode(node)));
1817 return gen_unop(node, op, new_bd_ia32_Not, match_mode_neutral);
1823 * Transforms an Abs node.
1825 * @return The created ia32 Abs node
1827 static ir_node *gen_Abs(ir_node *node)
1829 ir_node *block = get_nodes_block(node);
1830 ir_node *new_block = be_transform_node(block);
1831 ir_node *op = get_Abs_op(node);
1832 dbg_info *dbgi = get_irn_dbg_info(node);
1833 ir_mode *mode = get_irn_mode(node);
1839 if (mode_is_float(mode)) {
1840 new_op = be_transform_node(op);
1842 if (ia32_cg_config.use_sse2) {
1843 ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg);
1844 new_node = new_bd_ia32_xAnd(dbgi, new_block, noreg_GP, noreg_GP,
1845 nomem, new_op, noreg_fp);
1847 size = get_mode_size_bits(mode);
1848 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1850 set_ia32_am_sc(new_node, ent);
1852 SET_IA32_ORIG_NODE(new_node, node);
1854 set_ia32_op_type(new_node, ia32_AddrModeS);
1855 set_ia32_ls_mode(new_node, mode);
1857 new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op);
1858 SET_IA32_ORIG_NODE(new_node, node);
1861 ir_node *xor, *sign_extension;
1863 if (get_mode_size_bits(mode) == 32) {
1864 new_op = be_transform_node(op);
1866 new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node);
1869 sign_extension = create_sex_32_64(dbgi, new_block, new_op, node);
1871 xor = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP,
1872 nomem, new_op, sign_extension);
1873 SET_IA32_ORIG_NODE(xor, node);
1875 new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP,
1876 nomem, xor, sign_extension);
1877 SET_IA32_ORIG_NODE(new_node, node);
1884 * Create a bt instruction for x & (1 << n) and place it into the block of cmp.
1886 static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n)
1888 dbg_info *dbgi = get_irn_dbg_info(cmp);
1889 ir_node *block = get_nodes_block(cmp);
1890 ir_node *new_block = be_transform_node(block);
1891 ir_node *op1 = be_transform_node(x);
1892 ir_node *op2 = be_transform_node(n);
1894 return new_bd_ia32_Bt(dbgi, new_block, op1, op2);
1898 * Transform a node returning a "flag" result.
1900 * @param node the node to transform
1901 * @param pnc_out the compare mode to use
1903 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
1910 /* we have a Cmp as input */
1911 if (is_Proj(node)) {
1912 ir_node *pred = get_Proj_pred(node);
1914 pn_Cmp pnc = get_Proj_proj(node);
1915 if (ia32_cg_config.use_bt && (pnc == pn_Cmp_Lg || pnc == pn_Cmp_Eq)) {
1916 ir_node *l = get_Cmp_left(pred);
1917 ir_node *r = get_Cmp_right(pred);
1919 ir_node *la = get_And_left(l);
1920 ir_node *ra = get_And_right(l);
1922 ir_node *c = get_Shl_left(la);
1923 if (is_Const_1(c) && (is_Const_0(r) || r == la)) {
1924 /* (1 << n) & ra) */
1925 ir_node *n = get_Shl_right(la);
1926 flags = gen_bt(pred, ra, n);
1927 /* we must generate a Jc/Jnc jump */
1928 pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge;
1931 *pnc_out = ia32_pn_Cmp_unsigned | pnc;
1936 ir_node *c = get_Shl_left(ra);
1937 if (is_Const_1(c) && (is_Const_0(r) || r == ra)) {
1938 /* la & (1 << n)) */
1939 ir_node *n = get_Shl_right(ra);
1940 flags = gen_bt(pred, la, n);
1941 /* we must generate a Jc/Jnc jump */
1942 pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge;
1945 *pnc_out = ia32_pn_Cmp_unsigned | pnc;
1951 flags = be_transform_node(pred);
1953 if (mode_is_float(get_irn_mode(get_Cmp_left(pred))))
1954 *pnc_out |= ia32_pn_Cmp_float;
1959 /* a mode_b value, we have to compare it against 0 */
1960 dbgi = get_irn_dbg_info(node);
1961 new_block = be_transform_node(get_nodes_block(node));
1962 new_op = be_transform_node(node);
1963 flags = new_bd_ia32_Test(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op,
1964 new_op, /*is_permuted=*/0, /*cmp_unsigned=*/0);
1965 *pnc_out = pn_Cmp_Lg;
1970 * Transforms a Load.
1972 * @return the created ia32 Load node
1974 static ir_node *gen_Load(ir_node *node)
1976 ir_node *old_block = get_nodes_block(node);
1977 ir_node *block = be_transform_node(old_block);
1978 ir_node *ptr = get_Load_ptr(node);
1979 ir_node *mem = get_Load_mem(node);
1980 ir_node *new_mem = be_transform_node(mem);
1983 dbg_info *dbgi = get_irn_dbg_info(node);
1984 ir_mode *mode = get_Load_mode(node);
1987 ia32_address_t addr;
1989 /* construct load address */
1990 memset(&addr, 0, sizeof(addr));
1991 ia32_create_address_mode(&addr, ptr, 0);
1998 base = be_transform_node(base);
2001 if (index == NULL) {
2004 index = be_transform_node(index);
2007 if (mode_is_float(mode)) {
2008 if (ia32_cg_config.use_sse2) {
2009 new_node = new_bd_ia32_xLoad(dbgi, block, base, index, new_mem,
2011 res_mode = mode_xmm;
2013 new_node = new_bd_ia32_vfld(dbgi, block, base, index, new_mem,
2015 res_mode = mode_vfp;
2018 assert(mode != mode_b);
2020 /* create a conv node with address mode for smaller modes */
2021 if (get_mode_size_bits(mode) < 32) {
2022 new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, index,
2023 new_mem, noreg_GP, mode);
2025 new_node = new_bd_ia32_Load(dbgi, block, base, index, new_mem);
2030 set_irn_pinned(new_node, get_irn_pinned(node));
2031 set_ia32_op_type(new_node, ia32_AddrModeS);
2032 set_ia32_ls_mode(new_node, mode);
2033 set_address(new_node, &addr);
2035 if (get_irn_pinned(node) == op_pin_state_floats) {
2036 assert(pn_ia32_xLoad_res == pn_ia32_vfld_res
2037 && pn_ia32_vfld_res == pn_ia32_Load_res
2038 && pn_ia32_Load_res == pn_ia32_res);
2039 arch_irn_add_flags(new_node, arch_irn_flags_rematerializable);
2042 SET_IA32_ORIG_NODE(new_node, node);
2044 be_dep_on_frame(new_node);
2048 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
2049 ir_node *ptr, ir_node *other)
2056 /* we only use address mode if we're the only user of the load */
2057 if (get_irn_n_edges(node) > 1)
2060 load = get_Proj_pred(node);
2063 if (get_nodes_block(load) != block)
2066 /* store should have the same pointer as the load */
2067 if (get_Load_ptr(load) != ptr)
2070 /* don't do AM if other node inputs depend on the load (via mem-proj) */
2071 if (other != NULL &&
2072 get_nodes_block(other) == block &&
2073 heights_reachable_in_block(heights, other, load)) {
2077 if (prevents_AM(block, load, mem))
2079 /* Store should be attached to the load via mem */
2080 assert(heights_reachable_in_block(heights, mem, load));
2085 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
2086 ir_node *mem, ir_node *ptr, ir_mode *mode,
2087 construct_binop_dest_func *func,
2088 construct_binop_dest_func *func8bit,
2089 match_flags_t flags)
2091 ir_node *src_block = get_nodes_block(node);
2099 ia32_address_mode_t am;
2100 ia32_address_t *addr = &am.addr;
2101 memset(&am, 0, sizeof(am));
2103 assert(flags & match_immediate); /* there is no destam node without... */
2104 commutative = (flags & match_commutative) != 0;
2106 if (use_dest_am(src_block, op1, mem, ptr, op2)) {
2107 build_address(&am, op1, ia32_create_am_double_use);
2108 new_op = create_immediate_or_transform(op2, 0);
2109 } else if (commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
2110 build_address(&am, op2, ia32_create_am_double_use);
2111 new_op = create_immediate_or_transform(op1, 0);
2116 if (addr->base == NULL)
2117 addr->base = noreg_GP;
2118 if (addr->index == NULL)
2119 addr->index = noreg_GP;
2120 if (addr->mem == NULL)
2123 dbgi = get_irn_dbg_info(node);
2124 block = be_transform_node(src_block);
2125 new_mem = transform_AM_mem(block, am.am_node, mem, addr->mem);
2127 if (get_mode_size_bits(mode) == 8) {
2128 new_node = func8bit(dbgi, block, addr->base, addr->index, new_mem, new_op);
2130 new_node = func(dbgi, block, addr->base, addr->index, new_mem, new_op);
2132 set_address(new_node, addr);
2133 set_ia32_op_type(new_node, ia32_AddrModeD);
2134 set_ia32_ls_mode(new_node, mode);
2135 SET_IA32_ORIG_NODE(new_node, node);
2137 be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
2138 mem_proj = be_transform_node(am.mem_proj);
2139 be_set_transformed_node(mem_proj ? mem_proj : am.mem_proj, new_node);
2144 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
2145 ir_node *ptr, ir_mode *mode,
2146 construct_unop_dest_func *func)
2148 ir_node *src_block = get_nodes_block(node);
2154 ia32_address_mode_t am;
2155 ia32_address_t *addr = &am.addr;
2157 if (!use_dest_am(src_block, op, mem, ptr, NULL))
2160 memset(&am, 0, sizeof(am));
2161 build_address(&am, op, ia32_create_am_double_use);
2163 dbgi = get_irn_dbg_info(node);
2164 block = be_transform_node(src_block);
2165 new_mem = transform_AM_mem(block, am.am_node, mem, addr->mem);
2166 new_node = func(dbgi, block, addr->base, addr->index, new_mem);
2167 set_address(new_node, addr);
2168 set_ia32_op_type(new_node, ia32_AddrModeD);
2169 set_ia32_ls_mode(new_node, mode);
2170 SET_IA32_ORIG_NODE(new_node, node);
2172 be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
2173 mem_proj = be_transform_node(am.mem_proj);
2174 be_set_transformed_node(mem_proj ? mem_proj : am.mem_proj, new_node);
2179 static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
2181 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
2182 return get_negated_pnc(pnc, mode);
2185 static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem)
2187 ir_mode *mode = get_irn_mode(node);
2188 ir_node *mux_true = get_Mux_true(node);
2189 ir_node *mux_false = get_Mux_false(node);
2199 ia32_address_t addr;
2201 if (get_mode_size_bits(mode) != 8)
2204 if (is_Const_1(mux_true) && is_Const_0(mux_false)) {
2206 } else if (is_Const_0(mux_true) && is_Const_1(mux_false)) {
2212 cond = get_Mux_sel(node);
2213 flags = get_flags_node(cond, &pnc);
2214 /* we can't handle the float special cases with SetM */
2215 if (pnc & ia32_pn_Cmp_float)
2218 pnc = ia32_get_negated_pnc(pnc);
2220 build_address_ptr(&addr, ptr, mem);
2222 dbgi = get_irn_dbg_info(node);
2223 block = get_nodes_block(node);
2224 new_block = be_transform_node(block);
2225 new_mem = be_transform_node(mem);
2226 new_node = new_bd_ia32_SetccMem(dbgi, new_block, addr.base,
2227 addr.index, addr.mem, flags, pnc);
2228 set_address(new_node, &addr);
2229 set_ia32_op_type(new_node, ia32_AddrModeD);
2230 set_ia32_ls_mode(new_node, mode);
2231 SET_IA32_ORIG_NODE(new_node, node);
2236 static ir_node *try_create_dest_am(ir_node *node)
2238 ir_node *val = get_Store_value(node);
2239 ir_node *mem = get_Store_mem(node);
2240 ir_node *ptr = get_Store_ptr(node);
2241 ir_mode *mode = get_irn_mode(val);
2242 unsigned bits = get_mode_size_bits(mode);
2247 /* handle only GP modes for now... */
2248 if (!ia32_mode_needs_gp_reg(mode))
2252 /* store must be the only user of the val node */
2253 if (get_irn_n_edges(val) > 1)
2255 /* skip pointless convs */
2257 ir_node *conv_op = get_Conv_op(val);
2258 ir_mode *pred_mode = get_irn_mode(conv_op);
2259 if (!ia32_mode_needs_gp_reg(pred_mode))
2261 if (pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
2269 /* value must be in the same block */
2270 if (get_nodes_block(node) != get_nodes_block(val))
2273 switch (get_irn_opcode(val)) {
2275 op1 = get_Add_left(val);
2276 op2 = get_Add_right(val);
2277 if (ia32_cg_config.use_incdec) {
2278 if (is_Const_1(op2)) {
2279 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_IncMem);
2281 } else if (is_Const_Minus_1(op2)) {
2282 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_DecMem);
2286 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2287 new_bd_ia32_AddMem, new_bd_ia32_AddMem8Bit,
2288 match_commutative | match_immediate);
2291 op1 = get_Sub_left(val);
2292 op2 = get_Sub_right(val);
2293 if (is_Const(op2)) {
2294 ir_fprintf(stderr, "Optimisation warning: not-normalized sub ,C found\n");
2296 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2297 new_bd_ia32_SubMem, new_bd_ia32_SubMem8Bit,
2301 op1 = get_And_left(val);
2302 op2 = get_And_right(val);
2303 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2304 new_bd_ia32_AndMem, new_bd_ia32_AndMem8Bit,
2305 match_commutative | match_immediate);
2308 op1 = get_Or_left(val);
2309 op2 = get_Or_right(val);
2310 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2311 new_bd_ia32_OrMem, new_bd_ia32_OrMem8Bit,
2312 match_commutative | match_immediate);
2315 op1 = get_Eor_left(val);
2316 op2 = get_Eor_right(val);
2317 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2318 new_bd_ia32_XorMem, new_bd_ia32_XorMem8Bit,
2319 match_commutative | match_immediate);
2322 op1 = get_Shl_left(val);
2323 op2 = get_Shl_right(val);
2324 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2325 new_bd_ia32_ShlMem, new_bd_ia32_ShlMem,
2329 op1 = get_Shr_left(val);
2330 op2 = get_Shr_right(val);
2331 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2332 new_bd_ia32_ShrMem, new_bd_ia32_ShrMem,
2336 op1 = get_Shrs_left(val);
2337 op2 = get_Shrs_right(val);
2338 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2339 new_bd_ia32_SarMem, new_bd_ia32_SarMem,
2343 op1 = get_Rotl_left(val);
2344 op2 = get_Rotl_right(val);
2345 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2346 new_bd_ia32_RolMem, new_bd_ia32_RolMem,
2349 /* TODO: match ROR patterns... */
2351 new_node = try_create_SetMem(val, ptr, mem);
2355 op1 = get_Minus_op(val);
2356 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NegMem);
2359 /* should be lowered already */
2360 assert(mode != mode_b);
2361 op1 = get_Not_op(val);
2362 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NotMem);
2368 if (new_node != NULL) {
2369 if (get_irn_pinned(new_node) != op_pin_state_pinned &&
2370 get_irn_pinned(node) == op_pin_state_pinned) {
2371 set_irn_pinned(new_node, op_pin_state_pinned);
2378 static bool possible_int_mode_for_fp(ir_mode *mode)
2382 if (!mode_is_signed(mode))
2384 size = get_mode_size_bits(mode);
2385 if (size != 16 && size != 32)
2390 static int is_float_to_int_conv(const ir_node *node)
2392 ir_mode *mode = get_irn_mode(node);
2396 if (!possible_int_mode_for_fp(mode))
2401 conv_op = get_Conv_op(node);
2402 conv_mode = get_irn_mode(conv_op);
2404 if (!mode_is_float(conv_mode))
2411 * Transform a Store(floatConst) into a sequence of
2414 * @return the created ia32 Store node
2416 static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns)
2418 ir_mode *mode = get_irn_mode(cns);
2419 unsigned size = get_mode_size_bytes(mode);
2420 tarval *tv = get_Const_tarval(cns);
2421 ir_node *block = get_nodes_block(node);
2422 ir_node *new_block = be_transform_node(block);
2423 ir_node *ptr = get_Store_ptr(node);
2424 ir_node *mem = get_Store_mem(node);
2425 dbg_info *dbgi = get_irn_dbg_info(node);
2429 ia32_address_t addr;
2431 assert(size % 4 == 0);
2434 build_address_ptr(&addr, ptr, mem);
2438 get_tarval_sub_bits(tv, ofs) |
2439 (get_tarval_sub_bits(tv, ofs + 1) << 8) |
2440 (get_tarval_sub_bits(tv, ofs + 2) << 16) |
2441 (get_tarval_sub_bits(tv, ofs + 3) << 24);
2442 ir_node *imm = ia32_create_Immediate(NULL, 0, val);
2444 ir_node *new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
2445 addr.index, addr.mem, imm);
2447 set_irn_pinned(new_node, get_irn_pinned(node));
2448 set_ia32_op_type(new_node, ia32_AddrModeD);
2449 set_ia32_ls_mode(new_node, mode_Iu);
2450 set_address(new_node, &addr);
2451 SET_IA32_ORIG_NODE(new_node, node);
2454 ins[i++] = new_node;
2459 } while (size != 0);
2462 return new_rd_Sync(dbgi, new_block, i, ins);
2469 * Generate a vfist or vfisttp instruction.
2471 static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index,
2472 ir_node *mem, ir_node *val, ir_node **fist)
2476 if (ia32_cg_config.use_fisttp) {
2477 /* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied
2478 if other users exists */
2479 ir_node *vfisttp = new_bd_ia32_vfisttp(dbgi, block, base, index, mem, val);
2480 ir_node *value = new_r_Proj(block, vfisttp, mode_E, pn_ia32_vfisttp_res);
2481 be_new_Keep(block, 1, &value);
2483 new_node = new_r_Proj(block, vfisttp, mode_M, pn_ia32_vfisttp_M);
2486 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
2489 new_node = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode);
2495 * Transforms a general (no special case) Store.
2497 * @return the created ia32 Store node
2499 static ir_node *gen_general_Store(ir_node *node)
2501 ir_node *val = get_Store_value(node);
2502 ir_mode *mode = get_irn_mode(val);
2503 ir_node *block = get_nodes_block(node);
2504 ir_node *new_block = be_transform_node(block);
2505 ir_node *ptr = get_Store_ptr(node);
2506 ir_node *mem = get_Store_mem(node);
2507 dbg_info *dbgi = get_irn_dbg_info(node);
2508 ir_node *new_val, *new_node, *store;
2509 ia32_address_t addr;
2511 /* check for destination address mode */
2512 new_node = try_create_dest_am(node);
2513 if (new_node != NULL)
2516 /* construct store address */
2517 memset(&addr, 0, sizeof(addr));
2518 ia32_create_address_mode(&addr, ptr, 0);
2520 if (addr.base == NULL) {
2521 addr.base = noreg_GP;
2523 addr.base = be_transform_node(addr.base);
2526 if (addr.index == NULL) {
2527 addr.index = noreg_GP;
2529 addr.index = be_transform_node(addr.index);
2531 addr.mem = be_transform_node(mem);
2533 if (mode_is_float(mode)) {
2534 /* Convs (and strict-Convs) before stores are unnecessary if the mode
2536 while (is_Conv(val) && mode == get_irn_mode(val)) {
2537 ir_node *op = get_Conv_op(val);
2538 if (!mode_is_float(get_irn_mode(op)))
2542 new_val = be_transform_node(val);
2543 if (ia32_cg_config.use_sse2) {
2544 new_node = new_bd_ia32_xStore(dbgi, new_block, addr.base,
2545 addr.index, addr.mem, new_val);
2547 new_node = new_bd_ia32_vfst(dbgi, new_block, addr.base,
2548 addr.index, addr.mem, new_val, mode);
2551 } else if (!ia32_cg_config.use_sse2 && is_float_to_int_conv(val)) {
2552 val = get_Conv_op(val);
2554 /* TODO: is this optimisation still necessary at all (middleend)? */
2555 /* We can skip ALL float->float up-Convs (and strict-up-Convs) before stores. */
2556 while (is_Conv(val)) {
2557 ir_node *op = get_Conv_op(val);
2558 if (!mode_is_float(get_irn_mode(op)))
2560 if (get_mode_size_bits(get_irn_mode(op)) > get_mode_size_bits(get_irn_mode(val)))
2564 new_val = be_transform_node(val);
2565 new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val, &store);
2567 new_val = create_immediate_or_transform(val, 0);
2568 assert(mode != mode_b);
2570 if (get_mode_size_bits(mode) == 8) {
2571 new_node = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
2572 addr.index, addr.mem, new_val);
2574 new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
2575 addr.index, addr.mem, new_val);
2580 set_irn_pinned(store, get_irn_pinned(node));
2581 set_ia32_op_type(store, ia32_AddrModeD);
2582 set_ia32_ls_mode(store, mode);
2584 set_address(store, &addr);
2585 SET_IA32_ORIG_NODE(store, node);
2591 * Transforms a Store.
2593 * @return the created ia32 Store node
2595 static ir_node *gen_Store(ir_node *node)
2597 ir_node *val = get_Store_value(node);
2598 ir_mode *mode = get_irn_mode(val);
2600 if (mode_is_float(mode) && is_Const(val)) {
2601 /* We can transform every floating const store
2602 into a sequence of integer stores.
2603 If the constant is already in a register,
2604 it would be better to use it, but we don't
2605 have this information here. */
2606 return gen_float_const_Store(node, val);
2608 return gen_general_Store(node);
2612 * Transforms a Switch.
2614 * @return the created ia32 SwitchJmp node
2616 static ir_node *create_Switch(ir_node *node)
2618 dbg_info *dbgi = get_irn_dbg_info(node);
2619 ir_node *block = be_transform_node(get_nodes_block(node));
2620 ir_node *sel = get_Cond_selector(node);
2621 ir_node *new_sel = be_transform_node(sel);
2622 long switch_min = LONG_MAX;
2623 long switch_max = LONG_MIN;
2624 long default_pn = get_Cond_default_proj(node);
2626 const ir_edge_t *edge;
2628 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2630 /* determine the smallest switch case value */
2631 foreach_out_edge(node, edge) {
2632 ir_node *proj = get_edge_src_irn(edge);
2633 long pn = get_Proj_proj(proj);
2634 if (pn == default_pn)
2637 if (pn < switch_min)
2639 if (pn > switch_max)
2643 if ((unsigned long) (switch_max - switch_min) > 128000) {
2644 panic("Size of switch %+F bigger than 128000", node);
2647 if (switch_min != 0) {
2648 /* if smallest switch case is not 0 we need an additional sub */
2649 new_sel = new_bd_ia32_Lea(dbgi, block, new_sel, noreg_GP);
2650 add_ia32_am_offs_int(new_sel, -switch_min);
2651 set_ia32_op_type(new_sel, ia32_AddrModeS);
2653 SET_IA32_ORIG_NODE(new_sel, node);
2656 new_node = new_bd_ia32_SwitchJmp(dbgi, block, new_sel, default_pn);
2657 SET_IA32_ORIG_NODE(new_node, node);
2663 * Transform a Cond node.
2665 static ir_node *gen_Cond(ir_node *node)
2667 ir_node *block = get_nodes_block(node);
2668 ir_node *new_block = be_transform_node(block);
2669 dbg_info *dbgi = get_irn_dbg_info(node);
2670 ir_node *sel = get_Cond_selector(node);
2671 ir_mode *sel_mode = get_irn_mode(sel);
2672 ir_node *flags = NULL;
2676 if (sel_mode != mode_b) {
2677 return create_Switch(node);
2680 /* we get flags from a Cmp */
2681 flags = get_flags_node(sel, &pnc);
2683 new_node = new_bd_ia32_Jcc(dbgi, new_block, flags, pnc);
2684 SET_IA32_ORIG_NODE(new_node, node);
2690 * Transform a be_Copy.
2692 static ir_node *gen_be_Copy(ir_node *node)
2694 ir_node *new_node = be_duplicate_node(node);
2695 ir_mode *mode = get_irn_mode(new_node);
2697 if (ia32_mode_needs_gp_reg(mode)) {
2698 set_irn_mode(new_node, mode_Iu);
2704 static ir_node *create_Fucom(ir_node *node)
2706 dbg_info *dbgi = get_irn_dbg_info(node);
2707 ir_node *block = get_nodes_block(node);
2708 ir_node *new_block = be_transform_node(block);
2709 ir_node *left = get_Cmp_left(node);
2710 ir_node *new_left = be_transform_node(left);
2711 ir_node *right = get_Cmp_right(node);
2715 if (ia32_cg_config.use_fucomi) {
2716 new_right = be_transform_node(right);
2717 new_node = new_bd_ia32_vFucomi(dbgi, new_block, new_left,
2719 set_ia32_commutative(new_node);
2720 SET_IA32_ORIG_NODE(new_node, node);
2722 if (ia32_cg_config.use_ftst && is_Const_0(right)) {
2723 new_node = new_bd_ia32_vFtstFnstsw(dbgi, new_block, new_left, 0);
2725 new_right = be_transform_node(right);
2726 new_node = new_bd_ia32_vFucomFnstsw(dbgi, new_block, new_left, new_right, 0);
2729 set_ia32_commutative(new_node);
2731 SET_IA32_ORIG_NODE(new_node, node);
2733 new_node = new_bd_ia32_Sahf(dbgi, new_block, new_node);
2734 SET_IA32_ORIG_NODE(new_node, node);
2740 static ir_node *create_Ucomi(ir_node *node)
2742 dbg_info *dbgi = get_irn_dbg_info(node);
2743 ir_node *src_block = get_nodes_block(node);
2744 ir_node *new_block = be_transform_node(src_block);
2745 ir_node *left = get_Cmp_left(node);
2746 ir_node *right = get_Cmp_right(node);
2748 ia32_address_mode_t am;
2749 ia32_address_t *addr = &am.addr;
2751 match_arguments(&am, src_block, left, right, NULL,
2752 match_commutative | match_am);
2754 new_node = new_bd_ia32_Ucomi(dbgi, new_block, addr->base, addr->index,
2755 addr->mem, am.new_op1, am.new_op2,
2757 set_am_attributes(new_node, &am);
2759 SET_IA32_ORIG_NODE(new_node, node);
2761 new_node = fix_mem_proj(new_node, &am);
2767 * helper function: checks whether all Cmp projs are Lg or Eq which is needed
2768 * to fold an and into a test node
2770 static bool can_fold_test_and(ir_node *node)
2772 const ir_edge_t *edge;
2774 /** we can only have eq and lg projs */
2775 foreach_out_edge(node, edge) {
2776 ir_node *proj = get_edge_src_irn(edge);
2777 pn_Cmp pnc = get_Proj_proj(proj);
2778 if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2786 * returns true if it is assured, that the upper bits of a node are "clean"
2787 * which means for a 16 or 8 bit value, that the upper bits in the register
2788 * are 0 for unsigned and a copy of the last significant bit for signed
2791 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
2793 assert(ia32_mode_needs_gp_reg(mode));
2794 if (get_mode_size_bits(mode) >= 32)
2797 if (is_Proj(transformed_node))
2798 return upper_bits_clean(get_Proj_pred(transformed_node), mode);
2800 switch (get_ia32_irn_opcode(transformed_node)) {
2801 case iro_ia32_Conv_I2I:
2802 case iro_ia32_Conv_I2I8Bit: {
2803 ir_mode *smaller_mode = get_ia32_ls_mode(transformed_node);
2804 if (mode_is_signed(smaller_mode) != mode_is_signed(mode))
2806 if (get_mode_size_bits(smaller_mode) > get_mode_size_bits(mode))
2813 if (mode_is_signed(mode)) {
2814 return false; /* TODO handle signed modes */
2816 ir_node *right = get_irn_n(transformed_node, n_ia32_Shr_count);
2817 if (is_ia32_Immediate(right) || is_ia32_Const(right)) {
2818 const ia32_immediate_attr_t *attr
2819 = get_ia32_immediate_attr_const(right);
2820 if (attr->symconst == 0 &&
2821 (unsigned)attr->offset >= 32 - get_mode_size_bits(mode)) {
2825 return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Shr_val), mode);
2829 /* TODO too conservative if shift amount is constant */
2830 return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Sar_val), mode);
2833 if (!mode_is_signed(mode)) {
2835 upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_right), mode) ||
2836 upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_left), mode);
2838 /* TODO if one is known to be zero extended, then || is sufficient */
2843 upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_right), mode) &&
2844 upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_left), mode);
2846 case iro_ia32_Const:
2847 case iro_ia32_Immediate: {
2848 const ia32_immediate_attr_t *attr =
2849 get_ia32_immediate_attr_const(transformed_node);
2850 if (mode_is_signed(mode)) {
2851 long shifted = attr->offset >> (get_mode_size_bits(mode) - 1);
2852 return shifted == 0 || shifted == -1;
2854 unsigned long shifted = (unsigned long)attr->offset;
2855 shifted >>= get_mode_size_bits(mode);
2856 return shifted == 0;
2866 * Generate code for a Cmp.
2868 static ir_node *gen_Cmp(ir_node *node)
2870 dbg_info *dbgi = get_irn_dbg_info(node);
2871 ir_node *block = get_nodes_block(node);
2872 ir_node *new_block = be_transform_node(block);
2873 ir_node *left = get_Cmp_left(node);
2874 ir_node *right = get_Cmp_right(node);
2875 ir_mode *cmp_mode = get_irn_mode(left);
2877 ia32_address_mode_t am;
2878 ia32_address_t *addr = &am.addr;
2881 if (mode_is_float(cmp_mode)) {
2882 if (ia32_cg_config.use_sse2) {
2883 return create_Ucomi(node);
2885 return create_Fucom(node);
2889 assert(ia32_mode_needs_gp_reg(cmp_mode));
2891 /* Prefer the Test instruction, when encountering (x & y) ==/!= 0 */
2892 cmp_unsigned = !mode_is_signed(cmp_mode);
2893 if (is_Const_0(right) &&
2895 get_irn_n_edges(left) == 1 &&
2896 can_fold_test_and(node)) {
2897 /* Test(and_left, and_right) */
2898 ir_node *and_left = get_And_left(left);
2899 ir_node *and_right = get_And_right(left);
2901 /* matze: code here used mode instead of cmd_mode, I think it is always
2902 * the same as cmp_mode, but I leave this here to see if this is really
2905 assert(get_irn_mode(and_left) == cmp_mode);
2907 match_arguments(&am, block, and_left, and_right, NULL,
2909 match_am | match_8bit_am | match_16bit_am |
2910 match_am_and_immediates | match_immediate);
2912 /* use 32bit compare mode if possible since the opcode is smaller */
2913 if (upper_bits_clean(am.new_op1, cmp_mode) &&
2914 upper_bits_clean(am.new_op2, cmp_mode)) {
2915 cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
2918 if (get_mode_size_bits(cmp_mode) == 8) {
2919 new_node = new_bd_ia32_Test8Bit(dbgi, new_block, addr->base,
2920 addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted,
2923 new_node = new_bd_ia32_Test(dbgi, new_block, addr->base, addr->index,
2924 addr->mem, am.new_op1, am.new_op2, am.ins_permuted, cmp_unsigned);
2927 /* Cmp(left, right) */
2928 match_arguments(&am, block, left, right, NULL,
2929 match_commutative | match_am | match_8bit_am |
2930 match_16bit_am | match_am_and_immediates |
2932 /* use 32bit compare mode if possible since the opcode is smaller */
2933 if (upper_bits_clean(am.new_op1, cmp_mode) &&
2934 upper_bits_clean(am.new_op2, cmp_mode)) {
2935 cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
2938 if (get_mode_size_bits(cmp_mode) == 8) {
2939 new_node = new_bd_ia32_Cmp8Bit(dbgi, new_block, addr->base,
2940 addr->index, addr->mem, am.new_op1,
2941 am.new_op2, am.ins_permuted,
2944 new_node = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index,
2945 addr->mem, am.new_op1, am.new_op2, am.ins_permuted, cmp_unsigned);
2948 set_am_attributes(new_node, &am);
2949 set_ia32_ls_mode(new_node, cmp_mode);
2951 SET_IA32_ORIG_NODE(new_node, node);
2953 new_node = fix_mem_proj(new_node, &am);
2958 static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags,
2961 dbg_info *dbgi = get_irn_dbg_info(node);
2962 ir_node *block = get_nodes_block(node);
2963 ir_node *new_block = be_transform_node(block);
2964 ir_node *val_true = get_Mux_true(node);
2965 ir_node *val_false = get_Mux_false(node);
2967 ia32_address_mode_t am;
2968 ia32_address_t *addr;
2970 assert(ia32_cg_config.use_cmov);
2971 assert(ia32_mode_needs_gp_reg(get_irn_mode(val_true)));
2975 match_arguments(&am, block, val_false, val_true, flags,
2976 match_commutative | match_am | match_16bit_am | match_mode_neutral);
2978 if (am.ins_permuted)
2979 pnc = ia32_get_negated_pnc(pnc);
2981 new_node = new_bd_ia32_CMovcc(dbgi, new_block, addr->base, addr->index,
2982 addr->mem, am.new_op1, am.new_op2, new_flags,
2984 set_am_attributes(new_node, &am);
2986 SET_IA32_ORIG_NODE(new_node, node);
2988 new_node = fix_mem_proj(new_node, &am);
2994 * Creates a ia32 Setcc instruction.
2996 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2997 ir_node *flags, pn_Cmp pnc,
3000 ir_mode *mode = get_irn_mode(orig_node);
3003 new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, pnc);
3004 SET_IA32_ORIG_NODE(new_node, orig_node);
3006 /* we might need to conv the result up */
3007 if (get_mode_size_bits(mode) > 8) {
3008 new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP,
3009 nomem, new_node, mode_Bu);
3010 SET_IA32_ORIG_NODE(new_node, orig_node);
3017 * Create instruction for an unsigned Difference or Zero.
3019 static ir_node *create_doz(ir_node *psi, ir_node *a, ir_node *b)
3021 ir_mode *mode = get_irn_mode(psi);
3031 new_node = gen_binop(psi, a, b, new_bd_ia32_Sub,
3032 match_mode_neutral | match_am | match_immediate | match_two_users);
3034 block = get_nodes_block(new_node);
3036 if (is_Proj(new_node)) {
3037 sub = get_Proj_pred(new_node);
3038 assert(is_ia32_Sub(sub));
3041 set_irn_mode(sub, mode_T);
3042 new_node = new_rd_Proj(NULL, block, sub, mode, pn_ia32_res);
3044 eflags = new_rd_Proj(NULL, block, sub, mode_Iu, pn_ia32_Sub_flags);
3046 dbgi = get_irn_dbg_info(psi);
3047 sbb = new_bd_ia32_Sbb0(dbgi, block, eflags);
3048 not = new_bd_ia32_Not(dbgi, block, sbb);
3050 new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, not);
3051 set_ia32_commutative(new_node);
3056 * Create an const array of two float consts.
3058 * @param c0 the first constant
3059 * @param c1 the second constant
3060 * @param new_mode IN/OUT for the mode of the constants, if NULL
3061 * smallest possible mode will be used
3063 static ir_entity *ia32_create_const_array(ir_node *c0, ir_node *c1, ir_mode **new_mode) {
3065 ir_mode *mode = *new_mode;
3067 ir_initializer_t *initializer;
3068 tarval *tv0 = get_Const_tarval(c0);
3069 tarval *tv1 = get_Const_tarval(c1);
3072 /* detect the best mode for the constants */
3073 mode = get_tarval_mode(tv0);
3075 if (mode != mode_F) {
3076 if (tarval_ieee754_can_conv_lossless(tv0, mode_F) &&
3077 tarval_ieee754_can_conv_lossless(tv1, mode_F)) {
3079 tv0 = tarval_convert_to(tv0, mode);
3080 tv1 = tarval_convert_to(tv1, mode);
3081 } else if (mode != mode_D) {
3082 if (tarval_ieee754_can_conv_lossless(tv0, mode_D) &&
3083 tarval_ieee754_can_conv_lossless(tv1, mode_D)) {
3085 tv0 = tarval_convert_to(tv0, mode);
3086 tv1 = tarval_convert_to(tv1, mode);
3093 tp = ia32_create_float_type(mode, 4);
3094 tp = ia32_create_float_array(tp);
3096 ent = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp);
3098 set_entity_ld_ident(ent, get_entity_ident(ent));
3099 set_entity_visibility(ent, visibility_local);
3100 set_entity_variability(ent, variability_constant);
3101 set_entity_allocation(ent, allocation_static);
3103 initializer = create_initializer_compound(2);
3105 set_initializer_compound_value(initializer, 0, create_initializer_tarval(tv0));
3106 set_initializer_compound_value(initializer, 1, create_initializer_tarval(tv1));
3108 set_entity_initializer(ent, initializer);
3115 * Transforms a Mux node into some code sequence.
3117 * @return The transformed node.
3119 static ir_node *gen_Mux(ir_node *node)
3121 dbg_info *dbgi = get_irn_dbg_info(node);
3122 ir_node *block = get_nodes_block(node);
3123 ir_node *new_block = be_transform_node(block);
3124 ir_node *mux_true = get_Mux_true(node);
3125 ir_node *mux_false = get_Mux_false(node);
3126 ir_node *cond = get_Mux_sel(node);
3127 ir_mode *mode = get_irn_mode(node);
3132 assert(get_irn_mode(cond) == mode_b);
3134 /* Note: a Mux node uses a Load two times IFF it's used in the compare AND in the result */
3135 if (mode_is_float(mode)) {
3136 ir_node *cmp = get_Proj_pred(cond);
3137 ir_node *cmp_left = get_Cmp_left(cmp);
3138 ir_node *cmp_right = get_Cmp_right(cmp);
3139 pn_Cmp pnc = get_Proj_proj(cond);
3141 if (ia32_cg_config.use_sse2) {
3142 if (pnc == pn_Cmp_Lt || pnc == pn_Cmp_Le) {
3143 if (cmp_left == mux_true && cmp_right == mux_false) {
3144 /* Mux(a <= b, a, b) => MIN */
3145 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
3146 match_commutative | match_am | match_two_users);
3147 } else if (cmp_left == mux_false && cmp_right == mux_true) {
3148 /* Mux(a <= b, b, a) => MAX */
3149 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
3150 match_commutative | match_am | match_two_users);
3152 } else if (pnc == pn_Cmp_Gt || pnc == pn_Cmp_Ge) {
3153 if (cmp_left == mux_true && cmp_right == mux_false) {
3154 /* Mux(a >= b, a, b) => MAX */
3155 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
3156 match_commutative | match_am | match_two_users);
3157 } else if (cmp_left == mux_false && cmp_right == mux_true) {
3158 /* Mux(a >= b, b, a) => MIN */
3159 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
3160 match_commutative | match_am | match_two_users);
3165 if (is_Const(mux_true) && is_Const(mux_false)) {
3166 ia32_address_mode_t am;
3171 flags = get_flags_node(cond, &pnc);
3172 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node);
3174 if (ia32_cg_config.use_sse2) {
3175 /* cannot load from different mode on SSE */
3178 /* x87 can load any mode */
3182 am.addr.symconst_ent = ia32_create_const_array(mux_false, mux_true, &new_mode);
3184 switch (get_mode_size_bytes(new_mode)) {
3194 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3195 set_ia32_am_scale(new_node, 2);
3200 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3201 set_ia32_am_scale(new_node, 1);
3204 /* arg, shift 16 NOT supported */
3206 new_node = new_bd_ia32_Add(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, new_node);
3209 panic("Unsupported constant size");
3212 am.ls_mode = new_mode;
3213 am.addr.base = noreg_GP;
3214 am.addr.index = new_node;
3215 am.addr.mem = nomem;
3217 am.addr.scale = scale;
3218 am.addr.use_frame = 0;
3219 am.addr.frame_entity = NULL;
3220 am.addr.symconst_sign = 0;
3221 am.mem_proj = am.addr.mem;
3222 am.op_type = ia32_AddrModeS;
3225 am.pinned = op_pin_state_floats;
3227 am.ins_permuted = 0;
3229 if (ia32_cg_config.use_sse2)
3230 load = new_bd_ia32_xLoad(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
3232 load = new_bd_ia32_vfld(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
3233 set_am_attributes(load, &am);
3235 return new_rd_Proj(NULL, block, load, mode_vfp, pn_ia32_res);
3237 panic("cannot transform floating point Mux");
3240 assert(ia32_mode_needs_gp_reg(mode));
3242 if (is_Proj(cond)) {
3243 ir_node *cmp = get_Proj_pred(cond);
3245 ir_node *cmp_left = get_Cmp_left(cmp);
3246 ir_node *cmp_right = get_Cmp_right(cmp);
3247 pn_Cmp pnc = get_Proj_proj(cond);
3249 /* check for unsigned Doz first */
3250 if ((pnc & pn_Cmp_Gt) && !mode_is_signed(mode) &&
3251 is_Const_0(mux_false) && is_Sub(mux_true) &&
3252 get_Sub_left(mux_true) == cmp_left && get_Sub_right(mux_true) == cmp_right) {
3253 /* Mux(a >=u b, a - b, 0) unsigned Doz */
3254 return create_doz(node, cmp_left, cmp_right);
3255 } else if ((pnc & pn_Cmp_Lt) && !mode_is_signed(mode) &&
3256 is_Const_0(mux_true) && is_Sub(mux_false) &&
3257 get_Sub_left(mux_false) == cmp_left && get_Sub_right(mux_false) == cmp_right) {
3258 /* Mux(a <=u b, 0, a - b) unsigned Doz */
3259 return create_doz(node, cmp_left, cmp_right);
3264 flags = get_flags_node(cond, &pnc);
3266 if (is_Const(mux_true) && is_Const(mux_false)) {
3267 /* both are const, good */
3268 if (is_Const_1(mux_true) && is_Const_0(mux_false)) {
3269 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node);
3270 } else if (is_Const_0(mux_true) && is_Const_1(mux_false)) {
3271 pnc = ia32_get_negated_pnc(pnc);
3272 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node);
3274 /* Not that simple. */
3279 new_node = create_CMov(node, cond, flags, pnc);
3287 * Create a conversion from x87 state register to general purpose.
3289 static ir_node *gen_x87_fp_to_gp(ir_node *node)
3291 ir_node *block = be_transform_node(get_nodes_block(node));
3292 ir_node *op = get_Conv_op(node);
3293 ir_node *new_op = be_transform_node(op);
3294 ir_graph *irg = current_ir_graph;
3295 dbg_info *dbgi = get_irn_dbg_info(node);
3296 ir_mode *mode = get_irn_mode(node);
3297 ir_node *fist, *load, *mem;
3299 mem = gen_vfist(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, new_op, &fist);
3300 set_irn_pinned(fist, op_pin_state_floats);
3301 set_ia32_use_frame(fist);
3302 set_ia32_op_type(fist, ia32_AddrModeD);
3304 assert(get_mode_size_bits(mode) <= 32);
3305 /* exception we can only store signed 32 bit integers, so for unsigned
3306 we store a 64bit (signed) integer and load the lower bits */
3307 if (get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
3308 set_ia32_ls_mode(fist, mode_Ls);
3310 set_ia32_ls_mode(fist, mode_Is);
3312 SET_IA32_ORIG_NODE(fist, node);
3315 load = new_bd_ia32_Load(dbgi, block, get_irg_frame(irg), noreg_GP, mem);
3317 set_irn_pinned(load, op_pin_state_floats);
3318 set_ia32_use_frame(load);
3319 set_ia32_op_type(load, ia32_AddrModeS);
3320 set_ia32_ls_mode(load, mode_Is);
3321 if (get_ia32_ls_mode(fist) == mode_Ls) {
3322 ia32_attr_t *attr = get_ia32_attr(load);
3323 attr->data.need_64bit_stackent = 1;
3325 ia32_attr_t *attr = get_ia32_attr(load);
3326 attr->data.need_32bit_stackent = 1;
3328 SET_IA32_ORIG_NODE(load, node);
3330 return new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res);
3334 * Creates a x87 strict Conv by placing a Store and a Load
3336 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
3338 ir_node *block = get_nodes_block(node);
3339 ir_graph *irg = get_Block_irg(block);
3340 dbg_info *dbgi = get_irn_dbg_info(node);
3341 ir_node *frame = get_irg_frame(irg);
3342 ir_node *store, *load;
3345 store = new_bd_ia32_vfst(dbgi, block, frame, noreg_GP, nomem, node, tgt_mode);
3346 set_ia32_use_frame(store);
3347 set_ia32_op_type(store, ia32_AddrModeD);
3348 SET_IA32_ORIG_NODE(store, node);
3350 load = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store, tgt_mode);
3351 set_ia32_use_frame(load);
3352 set_ia32_op_type(load, ia32_AddrModeS);
3353 SET_IA32_ORIG_NODE(load, node);
3355 new_node = new_r_Proj(block, load, mode_E, pn_ia32_vfld_res);
3359 static ir_node *create_Conv_I2I(dbg_info *dbgi, ir_node *block, ir_node *base,
3360 ir_node *index, ir_node *mem, ir_node *val, ir_mode *mode)
3362 ir_node *(*func)(dbg_info*, ir_node*, ir_node*, ir_node*, ir_node*, ir_node*, ir_mode*);
3364 func = get_mode_size_bits(mode) == 8 ?
3365 new_bd_ia32_Conv_I2I8Bit : new_bd_ia32_Conv_I2I;
3366 return func(dbgi, block, base, index, mem, val, mode);
3370 * Create a conversion from general purpose to x87 register
3372 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode)
3374 ir_node *src_block = get_nodes_block(node);
3375 ir_node *block = be_transform_node(src_block);
3376 ir_graph *irg = get_Block_irg(block);
3377 dbg_info *dbgi = get_irn_dbg_info(node);
3378 ir_node *op = get_Conv_op(node);
3379 ir_node *new_op = NULL;
3381 ir_mode *store_mode;
3386 /* fild can use source AM if the operand is a signed 16bit or 32bit integer */
3387 if (possible_int_mode_for_fp(src_mode)) {
3388 ia32_address_mode_t am;
3390 match_arguments(&am, src_block, NULL, op, NULL, match_am | match_try_am | match_16bit_am);
3391 if (am.op_type == ia32_AddrModeS) {
3392 ia32_address_t *addr = &am.addr;
3394 fild = new_bd_ia32_vfild(dbgi, block, addr->base, addr->index, addr->mem);
3395 new_node = new_r_Proj(block, fild, mode_vfp, pn_ia32_vfild_res);
3397 set_am_attributes(fild, &am);
3398 SET_IA32_ORIG_NODE(fild, node);
3400 fix_mem_proj(fild, &am);
3405 if (new_op == NULL) {
3406 new_op = be_transform_node(op);
3409 mode = get_irn_mode(op);
3411 /* first convert to 32 bit signed if necessary */
3412 if (get_mode_size_bits(src_mode) < 32) {
3413 if (!upper_bits_clean(new_op, src_mode)) {
3414 new_op = create_Conv_I2I(dbgi, block, noreg_GP, noreg_GP, nomem, new_op, src_mode);
3415 SET_IA32_ORIG_NODE(new_op, node);
3420 assert(get_mode_size_bits(mode) == 32);
3423 store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, new_op);
3425 set_ia32_use_frame(store);
3426 set_ia32_op_type(store, ia32_AddrModeD);
3427 set_ia32_ls_mode(store, mode_Iu);
3429 /* exception for 32bit unsigned, do a 64bit spill+load */
3430 if (!mode_is_signed(mode)) {
3433 ir_node *zero_const = ia32_create_Immediate(NULL, 0, 0);
3435 ir_node *zero_store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg),
3436 noreg_GP, nomem, zero_const);
3438 set_ia32_use_frame(zero_store);
3439 set_ia32_op_type(zero_store, ia32_AddrModeD);
3440 add_ia32_am_offs_int(zero_store, 4);
3441 set_ia32_ls_mode(zero_store, mode_Iu);
3446 store = new_rd_Sync(dbgi, block, 2, in);
3447 store_mode = mode_Ls;
3449 store_mode = mode_Is;
3453 fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg_GP, store);
3455 set_ia32_use_frame(fild);
3456 set_ia32_op_type(fild, ia32_AddrModeS);
3457 set_ia32_ls_mode(fild, store_mode);
3459 new_node = new_r_Proj(block, fild, mode_vfp, pn_ia32_vfild_res);
3465 * Create a conversion from one integer mode into another one
3467 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
3468 dbg_info *dbgi, ir_node *block, ir_node *op,
3471 ir_node *new_block = be_transform_node(block);
3473 ir_mode *smaller_mode;
3474 ia32_address_mode_t am;
3475 ia32_address_t *addr = &am.addr;
3478 if (get_mode_size_bits(src_mode) < get_mode_size_bits(tgt_mode)) {
3479 smaller_mode = src_mode;
3481 smaller_mode = tgt_mode;
3484 #ifdef DEBUG_libfirm
3486 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
3491 match_arguments(&am, block, NULL, op, NULL,
3492 match_am | match_8bit_am | match_16bit_am);
3494 if (upper_bits_clean(am.new_op2, smaller_mode)) {
3495 /* unnecessary conv. in theory it shouldn't have been AM */
3496 assert(is_ia32_NoReg_GP(addr->base));
3497 assert(is_ia32_NoReg_GP(addr->index));
3498 assert(is_NoMem(addr->mem));
3499 assert(am.addr.offset == 0);
3500 assert(am.addr.symconst_ent == NULL);
3504 new_node = create_Conv_I2I(dbgi, new_block, addr->base, addr->index,
3505 addr->mem, am.new_op2, smaller_mode);
3506 set_am_attributes(new_node, &am);
3507 /* match_arguments assume that out-mode = in-mode, this isn't true here
3509 set_ia32_ls_mode(new_node, smaller_mode);
3510 SET_IA32_ORIG_NODE(new_node, node);
3511 new_node = fix_mem_proj(new_node, &am);
3516 * Transforms a Conv node.
3518 * @return The created ia32 Conv node
3520 static ir_node *gen_Conv(ir_node *node)
3522 ir_node *block = get_nodes_block(node);
3523 ir_node *new_block = be_transform_node(block);
3524 ir_node *op = get_Conv_op(node);
3525 ir_node *new_op = NULL;
3526 dbg_info *dbgi = get_irn_dbg_info(node);
3527 ir_mode *src_mode = get_irn_mode(op);
3528 ir_mode *tgt_mode = get_irn_mode(node);
3529 int src_bits = get_mode_size_bits(src_mode);
3530 int tgt_bits = get_mode_size_bits(tgt_mode);
3531 ir_node *res = NULL;
3533 assert(!mode_is_int(src_mode) || src_bits <= 32);
3534 assert(!mode_is_int(tgt_mode) || tgt_bits <= 32);
3536 /* modeB -> X should already be lowered by the lower_mode_b pass */
3537 if (src_mode == mode_b) {
3538 panic("ConvB not lowered %+F", node);
3541 if (src_mode == tgt_mode) {
3542 if (get_Conv_strict(node)) {
3543 if (ia32_cg_config.use_sse2) {
3544 /* when we are in SSE mode, we can kill all strict no-op conversion */
3545 return be_transform_node(op);
3548 /* this should be optimized already, but who knows... */
3549 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
3550 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
3551 return be_transform_node(op);
3555 if (mode_is_float(src_mode)) {
3556 new_op = be_transform_node(op);
3557 /* we convert from float ... */
3558 if (mode_is_float(tgt_mode)) {
3560 if (ia32_cg_config.use_sse2) {
3561 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
3562 res = new_bd_ia32_Conv_FP2FP(dbgi, new_block, noreg_GP, noreg_GP,
3564 set_ia32_ls_mode(res, tgt_mode);
3566 if (get_Conv_strict(node)) {
3567 /* if fp_no_float_fold is not set then we assume that we
3568 * don't have any float operations in a non
3569 * mode_float_arithmetic mode and can skip strict upconvs */
3570 if (src_bits < tgt_bits
3571 && !(get_irg_fp_model(current_ir_graph) & fp_no_float_fold)) {
3572 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3575 res = gen_x87_strict_conv(tgt_mode, new_op);
3576 SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
3580 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3585 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
3586 if (ia32_cg_config.use_sse2) {
3587 res = new_bd_ia32_Conv_FP2I(dbgi, new_block, noreg_GP, noreg_GP,
3589 set_ia32_ls_mode(res, src_mode);
3591 return gen_x87_fp_to_gp(node);
3595 /* we convert from int ... */
3596 if (mode_is_float(tgt_mode)) {
3598 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
3599 if (ia32_cg_config.use_sse2) {
3600 new_op = be_transform_node(op);
3601 res = new_bd_ia32_Conv_I2FP(dbgi, new_block, noreg_GP, noreg_GP,
3603 set_ia32_ls_mode(res, tgt_mode);
3605 unsigned int_mantissa = get_mode_size_bits(src_mode) - (mode_is_signed(src_mode) ? 1 : 0);
3606 unsigned float_mantissa = tarval_ieee754_get_mantissa_size(tgt_mode);
3607 res = gen_x87_gp_to_fp(node, src_mode);
3609 /* we need a strict-Conv, if the int mode has more bits than the
3611 if (float_mantissa < int_mantissa) {
3612 res = gen_x87_strict_conv(tgt_mode, res);
3613 SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
3617 } else if (tgt_mode == mode_b) {
3618 /* mode_b lowering already took care that we only have 0/1 values */
3619 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3620 src_mode, tgt_mode));
3621 return be_transform_node(op);
3624 if (src_bits == tgt_bits) {
3625 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3626 src_mode, tgt_mode));
3627 return be_transform_node(op);
3630 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
3638 static ir_node *create_immediate_or_transform(ir_node *node,
3639 char immediate_constraint_type)
3641 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
3642 if (new_node == NULL) {
3643 new_node = be_transform_node(node);
3649 * Transforms a FrameAddr into an ia32 Add.
3651 static ir_node *gen_be_FrameAddr(ir_node *node)
3653 ir_node *block = be_transform_node(get_nodes_block(node));
3654 ir_node *op = be_get_FrameAddr_frame(node);
3655 ir_node *new_op = be_transform_node(op);
3656 dbg_info *dbgi = get_irn_dbg_info(node);
3659 new_node = new_bd_ia32_Lea(dbgi, block, new_op, noreg_GP);
3660 set_ia32_frame_ent(new_node, arch_get_frame_entity(node));
3661 set_ia32_use_frame(new_node);
3663 SET_IA32_ORIG_NODE(new_node, node);
3669 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3671 static ir_node *gen_be_Return(ir_node *node)
3673 ir_graph *irg = current_ir_graph;
3674 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3675 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3676 ir_entity *ent = get_irg_entity(irg);
3677 ir_type *tp = get_entity_type(ent);
3682 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3683 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3685 int pn_ret_val, pn_ret_mem, arity, i;
3687 assert(ret_val != NULL);
3688 if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) {
3689 return be_duplicate_node(node);
3692 res_type = get_method_res_type(tp, 0);
3694 if (! is_Primitive_type(res_type)) {
3695 return be_duplicate_node(node);
3698 mode = get_type_mode(res_type);
3699 if (! mode_is_float(mode)) {
3700 return be_duplicate_node(node);
3703 assert(get_method_n_ress(tp) == 1);
3705 pn_ret_val = get_Proj_proj(ret_val);
3706 pn_ret_mem = get_Proj_proj(ret_mem);
3708 /* get the Barrier */
3709 barrier = get_Proj_pred(ret_val);
3711 /* get result input of the Barrier */
3712 ret_val = get_irn_n(barrier, pn_ret_val);
3713 new_ret_val = be_transform_node(ret_val);
3715 /* get memory input of the Barrier */
3716 ret_mem = get_irn_n(barrier, pn_ret_mem);
3717 new_ret_mem = be_transform_node(ret_mem);
3719 frame = get_irg_frame(irg);
3721 dbgi = get_irn_dbg_info(barrier);
3722 block = be_transform_node(get_nodes_block(barrier));
3724 /* store xmm0 onto stack */
3725 sse_store = new_bd_ia32_xStoreSimple(dbgi, block, frame, noreg_GP,
3726 new_ret_mem, new_ret_val);
3727 set_ia32_ls_mode(sse_store, mode);
3728 set_ia32_op_type(sse_store, ia32_AddrModeD);
3729 set_ia32_use_frame(sse_store);
3731 /* load into x87 register */
3732 fld = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, sse_store, mode);
3733 set_ia32_op_type(fld, ia32_AddrModeS);
3734 set_ia32_use_frame(fld);
3736 mproj = new_r_Proj(block, fld, mode_M, pn_ia32_vfld_M);
3737 fld = new_r_Proj(block, fld, mode_vfp, pn_ia32_vfld_res);
3739 /* create a new barrier */
3740 arity = get_irn_arity(barrier);
3741 in = ALLOCAN(ir_node*, arity);
3742 for (i = 0; i < arity; ++i) {
3745 if (i == pn_ret_val) {
3747 } else if (i == pn_ret_mem) {
3750 ir_node *in = get_irn_n(barrier, i);
3751 new_in = be_transform_node(in);
3756 new_barrier = new_ir_node(dbgi, irg, block,
3757 get_irn_op(barrier), get_irn_mode(barrier),
3759 copy_node_attr(barrier, new_barrier);
3760 be_duplicate_deps(barrier, new_barrier);
3761 be_set_transformed_node(barrier, new_barrier);
3763 /* transform normally */
3764 return be_duplicate_node(node);
3768 * Transform a be_AddSP into an ia32_SubSP.
3770 static ir_node *gen_be_AddSP(ir_node *node)
3772 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3773 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3775 return gen_binop(node, sp, sz, new_bd_ia32_SubSP,
3776 match_am | match_immediate);
3780 * Transform a be_SubSP into an ia32_AddSP
3782 static ir_node *gen_be_SubSP(ir_node *node)
3784 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3785 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3787 return gen_binop(node, sp, sz, new_bd_ia32_AddSP,
3788 match_am | match_immediate);
3792 * Change some phi modes
3794 static ir_node *gen_Phi(ir_node *node)
3796 const arch_register_req_t *req;
3797 ir_node *block = be_transform_node(get_nodes_block(node));
3798 ir_graph *irg = current_ir_graph;
3799 dbg_info *dbgi = get_irn_dbg_info(node);
3800 ir_mode *mode = get_irn_mode(node);
3803 if (ia32_mode_needs_gp_reg(mode)) {
3804 /* we shouldn't have any 64bit stuff around anymore */
3805 assert(get_mode_size_bits(mode) <= 32);
3806 /* all integer operations are on 32bit registers now */
3808 req = ia32_reg_classes[CLASS_ia32_gp].class_req;
3809 } else if (mode_is_float(mode)) {
3810 if (ia32_cg_config.use_sse2) {
3812 req = ia32_reg_classes[CLASS_ia32_xmm].class_req;
3815 req = ia32_reg_classes[CLASS_ia32_vfp].class_req;
3818 req = arch_no_register_req;
3821 /* phi nodes allow loops, so we use the old arguments for now
3822 * and fix this later */
3823 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3824 get_irn_in(node) + 1);
3825 copy_node_attr(node, phi);
3826 be_duplicate_deps(node, phi);
3828 arch_set_out_register_req(phi, 0, req);
3830 be_enqueue_preds(node);
3835 static ir_node *gen_Jmp(ir_node *node)
3837 ir_node *block = get_nodes_block(node);
3838 ir_node *new_block = be_transform_node(block);
3839 dbg_info *dbgi = get_irn_dbg_info(node);
3842 new_node = new_bd_ia32_Jmp(dbgi, new_block);
3843 SET_IA32_ORIG_NODE(new_node, node);
3851 static ir_node *gen_IJmp(ir_node *node)
3853 ir_node *block = get_nodes_block(node);
3854 ir_node *new_block = be_transform_node(block);
3855 dbg_info *dbgi = get_irn_dbg_info(node);
3856 ir_node *op = get_IJmp_target(node);
3858 ia32_address_mode_t am;
3859 ia32_address_t *addr = &am.addr;
3861 assert(get_irn_mode(op) == mode_P);
3863 match_arguments(&am, block, NULL, op, NULL, match_am | match_immediate);
3865 new_node = new_bd_ia32_IJmp(dbgi, new_block, addr->base, addr->index,
3866 addr->mem, am.new_op2);
3867 set_am_attributes(new_node, &am);
3868 SET_IA32_ORIG_NODE(new_node, node);
3870 new_node = fix_mem_proj(new_node, &am);
3876 * Transform a Bound node.
3878 static ir_node *gen_Bound(ir_node *node)
3881 ir_node *lower = get_Bound_lower(node);
3882 dbg_info *dbgi = get_irn_dbg_info(node);
3884 if (is_Const_0(lower)) {
3885 /* typical case for Java */
3886 ir_node *sub, *res, *flags, *block;
3888 res = gen_binop(node, get_Bound_index(node), get_Bound_upper(node),
3889 new_bd_ia32_Sub, match_mode_neutral | match_am | match_immediate);
3891 block = get_nodes_block(res);
3892 if (! is_Proj(res)) {
3894 set_irn_mode(sub, mode_T);
3895 res = new_rd_Proj(NULL, block, sub, mode_Iu, pn_ia32_res);
3897 sub = get_Proj_pred(res);
3899 flags = new_rd_Proj(NULL, block, sub, mode_Iu, pn_ia32_Sub_flags);
3900 new_node = new_bd_ia32_Jcc(dbgi, block, flags, pn_Cmp_Lt | ia32_pn_Cmp_unsigned);
3901 SET_IA32_ORIG_NODE(new_node, node);
3903 panic("generic Bound not supported in ia32 Backend");
3909 static ir_node *gen_ia32_l_ShlDep(ir_node *node)
3911 ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val);
3912 ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_count);
3914 return gen_shift_binop(node, left, right, new_bd_ia32_Shl,
3915 match_immediate | match_mode_neutral);
3918 static ir_node *gen_ia32_l_ShrDep(ir_node *node)
3920 ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_val);
3921 ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_count);
3922 return gen_shift_binop(node, left, right, new_bd_ia32_Shr,
3926 static ir_node *gen_ia32_l_SarDep(ir_node *node)
3928 ir_node *left = get_irn_n(node, n_ia32_l_SarDep_val);
3929 ir_node *right = get_irn_n(node, n_ia32_l_SarDep_count);
3930 return gen_shift_binop(node, left, right, new_bd_ia32_Sar,
3934 static ir_node *gen_ia32_l_Add(ir_node *node)
3936 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3937 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3938 ir_node *lowered = gen_binop(node, left, right, new_bd_ia32_Add,
3939 match_commutative | match_am | match_immediate |
3940 match_mode_neutral);
3942 if (is_Proj(lowered)) {
3943 lowered = get_Proj_pred(lowered);
3945 assert(is_ia32_Add(lowered));
3946 set_irn_mode(lowered, mode_T);
3952 static ir_node *gen_ia32_l_Adc(ir_node *node)
3954 return gen_binop_flags(node, new_bd_ia32_Adc,
3955 match_commutative | match_am | match_immediate |
3956 match_mode_neutral);
3960 * Transforms a l_MulS into a "real" MulS node.
3962 * @return the created ia32 Mul node
3964 static ir_node *gen_ia32_l_Mul(ir_node *node)
3966 ir_node *left = get_binop_left(node);
3967 ir_node *right = get_binop_right(node);
3969 return gen_binop(node, left, right, new_bd_ia32_Mul,
3970 match_commutative | match_am | match_mode_neutral);
3974 * Transforms a l_IMulS into a "real" IMul1OPS node.
3976 * @return the created ia32 IMul1OP node
3978 static ir_node *gen_ia32_l_IMul(ir_node *node)
3980 ir_node *left = get_binop_left(node);
3981 ir_node *right = get_binop_right(node);
3983 return gen_binop(node, left, right, new_bd_ia32_IMul1OP,
3984 match_commutative | match_am | match_mode_neutral);
3987 static ir_node *gen_ia32_l_Sub(ir_node *node)
3989 ir_node *left = get_irn_n(node, n_ia32_l_Sub_minuend);
3990 ir_node *right = get_irn_n(node, n_ia32_l_Sub_subtrahend);
3991 ir_node *lowered = gen_binop(node, left, right, new_bd_ia32_Sub,
3992 match_am | match_immediate | match_mode_neutral);
3994 if (is_Proj(lowered)) {
3995 lowered = get_Proj_pred(lowered);
3997 assert(is_ia32_Sub(lowered));
3998 set_irn_mode(lowered, mode_T);
4004 static ir_node *gen_ia32_l_Sbb(ir_node *node)
4006 return gen_binop_flags(node, new_bd_ia32_Sbb,
4007 match_am | match_immediate | match_mode_neutral);
4011 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
4012 * op1 - target to be shifted
4013 * op2 - contains bits to be shifted into target
4015 * Only op3 can be an immediate.
4017 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
4018 ir_node *low, ir_node *count)
4020 ir_node *block = get_nodes_block(node);
4021 ir_node *new_block = be_transform_node(block);
4022 dbg_info *dbgi = get_irn_dbg_info(node);
4023 ir_node *new_high = be_transform_node(high);
4024 ir_node *new_low = be_transform_node(low);
4028 /* the shift amount can be any mode that is bigger than 5 bits, since all
4029 * other bits are ignored anyway */
4030 while (is_Conv(count) &&
4031 get_irn_n_edges(count) == 1 &&
4032 mode_is_int(get_irn_mode(count))) {
4033 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
4034 count = get_Conv_op(count);
4036 new_count = create_immediate_or_transform(count, 0);
4038 if (is_ia32_l_ShlD(node)) {
4039 new_node = new_bd_ia32_ShlD(dbgi, new_block, new_high, new_low,
4042 new_node = new_bd_ia32_ShrD(dbgi, new_block, new_high, new_low,
4045 SET_IA32_ORIG_NODE(new_node, node);
4050 static ir_node *gen_ia32_l_ShlD(ir_node *node)
4052 ir_node *high = get_irn_n(node, n_ia32_l_ShlD_val_high);
4053 ir_node *low = get_irn_n(node, n_ia32_l_ShlD_val_low);
4054 ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
4055 return gen_lowered_64bit_shifts(node, high, low, count);
4058 static ir_node *gen_ia32_l_ShrD(ir_node *node)
4060 ir_node *high = get_irn_n(node, n_ia32_l_ShrD_val_high);
4061 ir_node *low = get_irn_n(node, n_ia32_l_ShrD_val_low);
4062 ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
4063 return gen_lowered_64bit_shifts(node, high, low, count);
4066 static ir_node *gen_ia32_l_LLtoFloat(ir_node *node)
4068 ir_node *src_block = get_nodes_block(node);
4069 ir_node *block = be_transform_node(src_block);
4070 ir_graph *irg = current_ir_graph;
4071 dbg_info *dbgi = get_irn_dbg_info(node);
4072 ir_node *frame = get_irg_frame(irg);
4073 ir_node *val_low = get_irn_n(node, n_ia32_l_LLtoFloat_val_low);
4074 ir_node *val_high = get_irn_n(node, n_ia32_l_LLtoFloat_val_high);
4075 ir_node *new_val_low = be_transform_node(val_low);
4076 ir_node *new_val_high = be_transform_node(val_high);
4078 ir_node *sync, *fild, *res;
4079 ir_node *store_low, *store_high;
4081 if (ia32_cg_config.use_sse2) {
4082 panic("ia32_l_LLtoFloat not implemented for SSE2");
4086 store_low = new_bd_ia32_Store(dbgi, block, frame, noreg_GP, nomem,
4088 store_high = new_bd_ia32_Store(dbgi, block, frame, noreg_GP, nomem,
4090 SET_IA32_ORIG_NODE(store_low, node);
4091 SET_IA32_ORIG_NODE(store_high, node);
4093 set_ia32_use_frame(store_low);
4094 set_ia32_use_frame(store_high);
4095 set_ia32_op_type(store_low, ia32_AddrModeD);
4096 set_ia32_op_type(store_high, ia32_AddrModeD);
4097 set_ia32_ls_mode(store_low, mode_Iu);
4098 set_ia32_ls_mode(store_high, mode_Is);
4099 add_ia32_am_offs_int(store_high, 4);
4103 sync = new_rd_Sync(dbgi, block, 2, in);
4106 fild = new_bd_ia32_vfild(dbgi, block, frame, noreg_GP, sync);
4108 set_ia32_use_frame(fild);
4109 set_ia32_op_type(fild, ia32_AddrModeS);
4110 set_ia32_ls_mode(fild, mode_Ls);
4112 SET_IA32_ORIG_NODE(fild, node);
4114 res = new_r_Proj(block, fild, mode_vfp, pn_ia32_vfild_res);
4116 if (! mode_is_signed(get_irn_mode(val_high))) {
4117 ia32_address_mode_t am;
4119 ir_node *count = ia32_create_Immediate(NULL, 0, 31);
4122 am.addr.base = noreg_GP;
4123 am.addr.index = new_bd_ia32_Shr(dbgi, block, new_val_high, count);
4124 am.addr.mem = nomem;
4127 am.addr.symconst_ent = ia32_gen_fp_known_const(ia32_ULLBIAS);
4128 am.addr.use_frame = 0;
4129 am.addr.frame_entity = NULL;
4130 am.addr.symconst_sign = 0;
4131 am.ls_mode = mode_F;
4132 am.mem_proj = nomem;
4133 am.op_type = ia32_AddrModeS;
4135 am.new_op2 = ia32_new_NoReg_vfp(env_cg);
4136 am.pinned = op_pin_state_floats;
4138 am.ins_permuted = 0;
4140 fadd = new_bd_ia32_vfadd(dbgi, block, am.addr.base, am.addr.index, am.addr.mem,
4141 am.new_op1, am.new_op2, get_fpcw());
4142 set_am_attributes(fadd, &am);
4144 set_irn_mode(fadd, mode_T);
4145 res = new_rd_Proj(NULL, block, fadd, mode_vfp, pn_ia32_res);
4150 static ir_node *gen_ia32_l_FloattoLL(ir_node *node)
4152 ir_node *src_block = get_nodes_block(node);
4153 ir_node *block = be_transform_node(src_block);
4154 ir_graph *irg = get_Block_irg(block);
4155 dbg_info *dbgi = get_irn_dbg_info(node);
4156 ir_node *frame = get_irg_frame(irg);
4157 ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val);
4158 ir_node *new_val = be_transform_node(val);
4159 ir_node *fist, *mem;
4161 mem = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_val, &fist);
4162 SET_IA32_ORIG_NODE(fist, node);
4163 set_ia32_use_frame(fist);
4164 set_ia32_op_type(fist, ia32_AddrModeD);
4165 set_ia32_ls_mode(fist, mode_Ls);
4171 * the BAD transformer.
4173 static ir_node *bad_transform(ir_node *node)
4175 panic("No transform function for %+F available.", node);
4179 static ir_node *gen_Proj_l_FloattoLL(ir_node *node)
4181 ir_node *block = be_transform_node(get_nodes_block(node));
4182 ir_graph *irg = get_Block_irg(block);
4183 ir_node *pred = get_Proj_pred(node);
4184 ir_node *new_pred = be_transform_node(pred);
4185 ir_node *frame = get_irg_frame(irg);
4186 dbg_info *dbgi = get_irn_dbg_info(node);
4187 long pn = get_Proj_proj(node);
4192 load = new_bd_ia32_Load(dbgi, block, frame, noreg_GP, new_pred);
4193 SET_IA32_ORIG_NODE(load, node);
4194 set_ia32_use_frame(load);
4195 set_ia32_op_type(load, ia32_AddrModeS);
4196 set_ia32_ls_mode(load, mode_Iu);
4197 /* we need a 64bit stackslot (fist stores 64bit) even though we only load
4198 * 32 bit from it with this particular load */
4199 attr = get_ia32_attr(load);
4200 attr->data.need_64bit_stackent = 1;
4202 if (pn == pn_ia32_l_FloattoLL_res_high) {
4203 add_ia32_am_offs_int(load, 4);
4205 assert(pn == pn_ia32_l_FloattoLL_res_low);
4208 proj = new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res);
4214 * Transform the Projs of an AddSP.
4216 static ir_node *gen_Proj_be_AddSP(ir_node *node)
4218 ir_node *block = be_transform_node(get_nodes_block(node));
4219 ir_node *pred = get_Proj_pred(node);
4220 ir_node *new_pred = be_transform_node(pred);
4221 dbg_info *dbgi = get_irn_dbg_info(node);
4222 long proj = get_Proj_proj(node);
4224 if (proj == pn_be_AddSP_sp) {
4225 ir_node *res = new_rd_Proj(dbgi, block, new_pred, mode_Iu,
4226 pn_ia32_SubSP_stack);
4227 arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]);
4229 } else if (proj == pn_be_AddSP_res) {
4230 return new_rd_Proj(dbgi, block, new_pred, mode_Iu,
4231 pn_ia32_SubSP_addr);
4232 } else if (proj == pn_be_AddSP_M) {
4233 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_SubSP_M);
4236 panic("No idea how to transform proj->AddSP");
4240 * Transform the Projs of a SubSP.
4242 static ir_node *gen_Proj_be_SubSP(ir_node *node)
4244 ir_node *block = be_transform_node(get_nodes_block(node));
4245 ir_node *pred = get_Proj_pred(node);
4246 ir_node *new_pred = be_transform_node(pred);
4247 dbg_info *dbgi = get_irn_dbg_info(node);
4248 long proj = get_Proj_proj(node);
4250 if (proj == pn_be_SubSP_sp) {
4251 ir_node *res = new_rd_Proj(dbgi, block, new_pred, mode_Iu,
4252 pn_ia32_AddSP_stack);
4253 arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]);
4255 } else if (proj == pn_be_SubSP_M) {
4256 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_AddSP_M);
4259 panic("No idea how to transform proj->SubSP");
4263 * Transform and renumber the Projs from a Load.
4265 static ir_node *gen_Proj_Load(ir_node *node)
4268 ir_node *block = be_transform_node(get_nodes_block(node));
4269 ir_node *pred = get_Proj_pred(node);
4270 dbg_info *dbgi = get_irn_dbg_info(node);
4271 long proj = get_Proj_proj(node);
4273 /* loads might be part of source address mode matches, so we don't
4274 * transform the ProjMs yet (with the exception of loads whose result is
4277 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4279 ir_node *old_block = get_nodes_block(node);
4281 /* this is needed, because sometimes we have loops that are only
4282 reachable through the ProjM */
4283 be_enqueue_preds(node);
4284 /* do it in 2 steps, to silence firm verifier */
4285 res = new_rd_Proj(dbgi, old_block, pred, mode_M, pn_Load_M);
4286 set_Proj_proj(res, pn_ia32_mem);
4290 /* renumber the proj */
4291 new_pred = be_transform_node(pred);
4292 if (is_ia32_Load(new_pred)) {
4295 return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Load_res);
4297 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Load_M);
4298 case pn_Load_X_regular:
4299 return new_rd_Jmp(dbgi, block);
4300 case pn_Load_X_except:
4301 /* This Load might raise an exception. Mark it. */
4302 set_ia32_exc_label(new_pred, 1);
4303 return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Load_X_exc);
4307 } else if (is_ia32_Conv_I2I(new_pred) ||
4308 is_ia32_Conv_I2I8Bit(new_pred)) {
4309 set_irn_mode(new_pred, mode_T);
4310 if (proj == pn_Load_res) {
4311 return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_res);
4312 } else if (proj == pn_Load_M) {
4313 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_mem);
4315 } else if (is_ia32_xLoad(new_pred)) {
4318 return new_rd_Proj(dbgi, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
4320 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_xLoad_M);
4321 case pn_Load_X_regular:
4322 return new_rd_Jmp(dbgi, block);
4323 case pn_Load_X_except:
4324 /* This Load might raise an exception. Mark it. */
4325 set_ia32_exc_label(new_pred, 1);
4326 return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_xLoad_X_exc);
4330 } else if (is_ia32_vfld(new_pred)) {
4333 return new_rd_Proj(dbgi, block, new_pred, mode_vfp, pn_ia32_vfld_res);
4335 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_vfld_M);
4336 case pn_Load_X_regular:
4337 return new_rd_Jmp(dbgi, block);
4338 case pn_Load_X_except:
4339 /* This Load might raise an exception. Mark it. */
4340 set_ia32_exc_label(new_pred, 1);
4341 return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_vfld_X_exc);
4346 /* can happen for ProJMs when source address mode happened for the
4349 /* however it should not be the result proj, as that would mean the
4350 load had multiple users and should not have been used for
4352 if (proj != pn_Load_M) {
4353 panic("internal error: transformed node not a Load");
4355 return new_rd_Proj(dbgi, block, new_pred, mode_M, 1);
4358 panic("No idea how to transform proj");
4362 * Transform and renumber the Projs from a DivMod like instruction.
4364 static ir_node *gen_Proj_DivMod(ir_node *node)
4366 ir_node *block = be_transform_node(get_nodes_block(node));
4367 ir_node *pred = get_Proj_pred(node);
4368 ir_node *new_pred = be_transform_node(pred);
4369 dbg_info *dbgi = get_irn_dbg_info(node);
4370 long proj = get_Proj_proj(node);
4372 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4374 switch (get_irn_opcode(pred)) {
4378 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Div_M);
4380 return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4381 case pn_Div_X_regular:
4382 return new_rd_Jmp(dbgi, block);
4383 case pn_Div_X_except:
4384 set_ia32_exc_label(new_pred, 1);
4385 return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Div_X_exc);
4393 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Div_M);
4395 return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4396 case pn_Mod_X_except:
4397 set_ia32_exc_label(new_pred, 1);
4398 return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Div_X_exc);
4406 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Div_M);
4407 case pn_DivMod_res_div:
4408 return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4409 case pn_DivMod_res_mod:
4410 return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4411 case pn_DivMod_X_regular:
4412 return new_rd_Jmp(dbgi, block);
4413 case pn_DivMod_X_except:
4414 set_ia32_exc_label(new_pred, 1);
4415 return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Div_X_exc);
4424 panic("No idea how to transform proj->DivMod");
4428 * Transform and renumber the Projs from a CopyB.
4430 static ir_node *gen_Proj_CopyB(ir_node *node)
4432 ir_node *block = be_transform_node(get_nodes_block(node));
4433 ir_node *pred = get_Proj_pred(node);
4434 ir_node *new_pred = be_transform_node(pred);
4435 dbg_info *dbgi = get_irn_dbg_info(node);
4436 long proj = get_Proj_proj(node);
4439 case pn_CopyB_M_regular:
4440 if (is_ia32_CopyB_i(new_pred)) {
4441 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4442 } else if (is_ia32_CopyB(new_pred)) {
4443 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_CopyB_M);
4450 panic("No idea how to transform proj->CopyB");
4454 * Transform and renumber the Projs from a Quot.
4456 static ir_node *gen_Proj_Quot(ir_node *node)
4458 ir_node *block = be_transform_node(get_nodes_block(node));
4459 ir_node *pred = get_Proj_pred(node);
4460 ir_node *new_pred = be_transform_node(pred);
4461 dbg_info *dbgi = get_irn_dbg_info(node);
4462 long proj = get_Proj_proj(node);
4466 if (is_ia32_xDiv(new_pred)) {
4467 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_xDiv_M);
4468 } else if (is_ia32_vfdiv(new_pred)) {
4469 return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4473 if (is_ia32_xDiv(new_pred)) {
4474 return new_rd_Proj(dbgi, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4475 } else if (is_ia32_vfdiv(new_pred)) {
4476 return new_rd_Proj(dbgi, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4479 case pn_Quot_X_regular:
4480 case pn_Quot_X_except:
4485 panic("No idea how to transform proj->Quot");
4488 static ir_node *gen_be_Call(ir_node *node)
4490 dbg_info *const dbgi = get_irn_dbg_info(node);
4491 ir_node *const src_block = get_nodes_block(node);
4492 ir_node *const block = be_transform_node(src_block);
4493 ir_node *const src_mem = get_irn_n(node, be_pos_Call_mem);
4494 ir_node *const src_sp = get_irn_n(node, be_pos_Call_sp);
4495 ir_node *const sp = be_transform_node(src_sp);
4496 ir_node *const src_ptr = get_irn_n(node, be_pos_Call_ptr);
4497 ia32_address_mode_t am;
4498 ia32_address_t *const addr = &am.addr;
4503 ir_node * eax = noreg_GP;
4504 ir_node * ecx = noreg_GP;
4505 ir_node * edx = noreg_GP;
4506 unsigned const pop = be_Call_get_pop(node);
4507 ir_type *const call_tp = be_Call_get_type(node);
4508 int old_no_pic_adjust;
4510 /* Run the x87 simulator if the call returns a float value */
4511 if (get_method_n_ress(call_tp) > 0) {
4512 ir_type *const res_type = get_method_res_type(call_tp, 0);
4513 ir_mode *const res_mode = get_type_mode(res_type);
4515 if (res_mode != NULL && mode_is_float(res_mode)) {
4516 env_cg->do_x87_sim = 1;
4520 /* We do not want be_Call direct calls */
4521 assert(be_Call_get_entity(node) == NULL);
4523 /* special case for PIC trampoline calls */
4524 old_no_pic_adjust = no_pic_adjust;
4525 no_pic_adjust = env_cg->birg->main_env->options->pic;
4527 match_arguments(&am, src_block, NULL, src_ptr, src_mem,
4528 match_am | match_immediate);
4530 no_pic_adjust = old_no_pic_adjust;
4532 i = get_irn_arity(node) - 1;
4533 fpcw = be_transform_node(get_irn_n(node, i--));
4534 for (; i >= be_pos_Call_first_arg; --i) {
4535 arch_register_req_t const *const req = arch_get_register_req(node, i);
4536 ir_node *const reg_parm = be_transform_node(get_irn_n(node, i));
4538 assert(req->type == arch_register_req_type_limited);
4539 assert(req->cls == &ia32_reg_classes[CLASS_ia32_gp]);
4541 switch (*req->limited) {
4542 case 1 << REG_EAX: assert(eax == noreg_GP); eax = reg_parm; break;
4543 case 1 << REG_ECX: assert(ecx == noreg_GP); ecx = reg_parm; break;
4544 case 1 << REG_EDX: assert(edx == noreg_GP); edx = reg_parm; break;
4545 default: panic("Invalid GP register for register parameter");
4549 mem = transform_AM_mem(block, src_ptr, src_mem, addr->mem);
4550 call = new_bd_ia32_Call(dbgi, block, addr->base, addr->index, mem,
4551 am.new_op2, sp, fpcw, eax, ecx, edx, pop, call_tp);
4552 set_am_attributes(call, &am);
4553 call = fix_mem_proj(call, &am);
4555 if (get_irn_pinned(node) == op_pin_state_pinned)
4556 set_irn_pinned(call, op_pin_state_pinned);
4558 SET_IA32_ORIG_NODE(call, node);
4560 if (ia32_cg_config.use_sse2) {
4561 /* remember this call for post-processing */
4562 ARR_APP1(ir_node *, call_list, call);
4563 ARR_APP1(ir_type *, call_types, be_Call_get_type(node));
4570 * Transform Builtin trap
4572 static ir_node *gen_trap(ir_node *node) {
4573 dbg_info *dbgi = get_irn_dbg_info(node);
4574 ir_node *block = be_transform_node(get_nodes_block(node));
4575 ir_node *mem = be_transform_node(get_Builtin_mem(node));
4577 return new_bd_ia32_UD2(dbgi, block, mem);
4581 * Transform Builtin debugbreak
4583 static ir_node *gen_debugbreak(ir_node *node) {
4584 dbg_info *dbgi = get_irn_dbg_info(node);
4585 ir_node *block = be_transform_node(get_nodes_block(node));
4586 ir_node *mem = be_transform_node(get_Builtin_mem(node));
4588 return new_bd_ia32_Breakpoint(dbgi, block, mem);
4592 * Transform Builtin return_address
4594 static ir_node *gen_return_address(ir_node *node) {
4595 ir_node *param = get_Builtin_param(node, 0);
4596 ir_node *frame = get_Builtin_param(node, 1);
4597 dbg_info *dbgi = get_irn_dbg_info(node);
4598 tarval *tv = get_Const_tarval(param);
4599 unsigned long value = get_tarval_long(tv);
4601 ir_node *block = be_transform_node(get_nodes_block(node));
4602 ir_node *ptr = be_transform_node(frame);
4606 ir_node *cnt = new_bd_ia32_ProduceVal(dbgi, block);
4607 ir_node *res = new_bd_ia32_ProduceVal(dbgi, block);
4608 ptr = new_bd_ia32_ClimbFrame(dbgi, block, ptr, cnt, res, value);
4611 /* load the return address from this frame */
4612 load = new_bd_ia32_Load(dbgi, block, ptr, noreg_GP, nomem);
4614 set_irn_pinned(load, get_irn_pinned(node));
4615 set_ia32_op_type(load, ia32_AddrModeS);
4616 set_ia32_ls_mode(load, mode_Iu);
4618 set_ia32_am_offs_int(load, 0);
4619 set_ia32_use_frame(load);
4620 set_ia32_frame_ent(load, ia32_get_return_address_entity());
4622 if (get_irn_pinned(node) == op_pin_state_floats) {
4623 assert(pn_ia32_xLoad_res == pn_ia32_vfld_res
4624 && pn_ia32_vfld_res == pn_ia32_Load_res
4625 && pn_ia32_Load_res == pn_ia32_res);
4626 arch_irn_add_flags(load, arch_irn_flags_rematerializable);
4629 SET_IA32_ORIG_NODE(load, node);
4630 return new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res);
4634 * Transform Builtin frame_address
4636 static ir_node *gen_frame_address(ir_node *node) {
4637 ir_node *param = get_Builtin_param(node, 0);
4638 ir_node *frame = get_Builtin_param(node, 1);
4639 dbg_info *dbgi = get_irn_dbg_info(node);
4640 tarval *tv = get_Const_tarval(param);
4641 unsigned long value = get_tarval_long(tv);
4643 ir_node *block = be_transform_node(get_nodes_block(node));
4644 ir_node *ptr = be_transform_node(frame);
4649 ir_node *cnt = new_bd_ia32_ProduceVal(dbgi, block);
4650 ir_node *res = new_bd_ia32_ProduceVal(dbgi, block);
4651 ptr = new_bd_ia32_ClimbFrame(dbgi, block, ptr, cnt, res, value);
4654 /* load the frame address from this frame */
4655 load = new_bd_ia32_Load(dbgi, block, ptr, noreg_GP, nomem);
4657 set_irn_pinned(load, get_irn_pinned(node));
4658 set_ia32_op_type(load, ia32_AddrModeS);
4659 set_ia32_ls_mode(load, mode_Iu);
4661 ent = ia32_get_frame_address_entity();
4663 set_ia32_am_offs_int(load, 0);
4664 set_ia32_use_frame(load);
4665 set_ia32_frame_ent(load, ent);
4667 /* will fail anyway, but gcc does this: */
4668 set_ia32_am_offs_int(load, 0);
4671 if (get_irn_pinned(node) == op_pin_state_floats) {
4672 assert(pn_ia32_xLoad_res == pn_ia32_vfld_res
4673 && pn_ia32_vfld_res == pn_ia32_Load_res
4674 && pn_ia32_Load_res == pn_ia32_res);
4675 arch_irn_add_flags(load, arch_irn_flags_rematerializable);
4678 SET_IA32_ORIG_NODE(load, node);
4679 return new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res);
4683 * Transform Builtin frame_address
4685 static ir_node *gen_prefetch(ir_node *node) {
4687 ir_node *ptr, *block, *mem, *base, *index;
4688 ir_node *param, *new_node;
4691 ia32_address_t addr;
4693 if (!ia32_cg_config.use_sse_prefetch && !ia32_cg_config.use_3dnow_prefetch) {
4694 /* no prefetch at all, route memory */
4695 return be_transform_node(get_Builtin_mem(node));
4698 param = get_Builtin_param(node, 1);
4699 tv = get_Const_tarval(param);
4700 rw = get_tarval_long(tv);
4702 /* construct load address */
4703 memset(&addr, 0, sizeof(addr));
4704 ptr = get_Builtin_param(node, 0);
4705 ia32_create_address_mode(&addr, ptr, 0);
4712 base = be_transform_node(base);
4715 if (index == NULL) {
4718 index = be_transform_node(index);
4721 dbgi = get_irn_dbg_info(node);
4722 block = be_transform_node(get_nodes_block(node));
4723 mem = be_transform_node(get_Builtin_mem(node));
4725 if (rw == 1 && ia32_cg_config.use_3dnow_prefetch) {
4726 /* we have 3DNow!, this was already checked above */
4727 new_node = new_bd_ia32_PrefetchW(dbgi, block, base, index, mem);
4728 } else if (ia32_cg_config.use_sse_prefetch) {
4729 /* note: rw == 1 is IGNORED in that case */
4730 param = get_Builtin_param(node, 2);
4731 tv = get_Const_tarval(param);
4732 locality = get_tarval_long(tv);
4734 /* SSE style prefetch */
4737 new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, index, mem);
4740 new_node = new_bd_ia32_Prefetch2(dbgi, block, base, index, mem);
4743 new_node = new_bd_ia32_Prefetch1(dbgi, block, base, index, mem);
4746 new_node = new_bd_ia32_Prefetch0(dbgi, block, base, index, mem);
4750 assert(ia32_cg_config.use_3dnow_prefetch);
4751 /* 3DNow! style prefetch */
4752 new_node = new_bd_ia32_Prefetch(dbgi, block, base, index, mem);
4755 set_irn_pinned(new_node, get_irn_pinned(node));
4756 set_ia32_op_type(new_node, ia32_AddrModeS);
4757 set_ia32_ls_mode(new_node, mode_Bu);
4758 set_address(new_node, &addr);
4760 SET_IA32_ORIG_NODE(new_node, node);
4762 be_dep_on_frame(new_node);
4763 return new_r_Proj(block, new_node, mode_M, pn_ia32_Prefetch_M);
4767 * Transform bsf like node
4769 static ir_node *gen_unop_AM(ir_node *node, construct_binop_dest_func *func)
4771 ir_node *param = get_Builtin_param(node, 0);
4772 dbg_info *dbgi = get_irn_dbg_info(node);
4774 ir_node *block = get_nodes_block(node);
4775 ir_node *new_block = be_transform_node(block);
4777 ia32_address_mode_t am;
4778 ia32_address_t *addr = &am.addr;
4781 match_arguments(&am, block, NULL, param, NULL, match_am);
4783 cnt = func(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2);
4784 set_am_attributes(cnt, &am);
4785 set_ia32_ls_mode(cnt, get_irn_mode(param));
4787 SET_IA32_ORIG_NODE(cnt, node);
4788 return fix_mem_proj(cnt, &am);
4792 * Transform builtin ffs.
4794 static ir_node *gen_ffs(ir_node *node)
4796 ir_node *bsf = gen_unop_AM(node, new_bd_ia32_Bsf);
4797 ir_node *real = skip_Proj(bsf);
4798 dbg_info *dbgi = get_irn_dbg_info(real);
4799 ir_node *block = get_nodes_block(real);
4800 ir_node *flag, *set, *conv, *neg, *or;
4803 if (get_irn_mode(real) != mode_T) {
4804 set_irn_mode(real, mode_T);
4805 bsf = new_r_Proj(block, real, mode_Iu, pn_ia32_res);
4808 flag = new_r_Proj(block, real, mode_b, pn_ia32_flags);
4811 set = new_bd_ia32_Setcc(dbgi, block, flag, pn_Cmp_Eq);
4812 SET_IA32_ORIG_NODE(set, node);
4815 conv = new_bd_ia32_Conv_I2I8Bit(dbgi, block, noreg_GP, noreg_GP, nomem, set, mode_Bu);
4816 SET_IA32_ORIG_NODE(conv, node);
4819 neg = new_bd_ia32_Neg(dbgi, block, conv);
4822 or = new_bd_ia32_Or(dbgi, block, noreg_GP, noreg_GP, nomem, bsf, neg);
4823 set_ia32_commutative(or);
4826 return new_bd_ia32_Add(dbgi, block, noreg_GP, noreg_GP, nomem, or, ia32_create_Immediate(NULL, 0, 1));
4830 * Transform builtin clz.
4832 static ir_node *gen_clz(ir_node *node)
4834 ir_node *bsr = gen_unop_AM(node, new_bd_ia32_Bsr);
4835 ir_node *real = skip_Proj(bsr);
4836 dbg_info *dbgi = get_irn_dbg_info(real);
4837 ir_node *block = get_nodes_block(real);
4838 ir_node *imm = ia32_create_Immediate(NULL, 0, 31);
4840 return new_bd_ia32_Xor(dbgi, block, noreg_GP, noreg_GP, nomem, bsr, imm);
4844 * Transform builtin ctz.
4846 static ir_node *gen_ctz(ir_node *node)
4848 return gen_unop_AM(node, new_bd_ia32_Bsf);
4852 * Transform builtin parity.
4854 static ir_node *gen_parity(ir_node *node)
4856 ir_node *param = get_Builtin_param(node, 0);
4857 dbg_info *dbgi = get_irn_dbg_info(node);
4859 ir_node *block = get_nodes_block(node);
4861 ir_node *new_block = be_transform_node(block);
4862 ir_node *imm, *cmp, *new_node;
4864 ia32_address_mode_t am;
4865 ia32_address_t *addr = &am.addr;
4869 match_arguments(&am, block, NULL, param, NULL, match_am);
4870 imm = ia32_create_Immediate(NULL, 0, 0);
4871 cmp = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index,
4872 addr->mem, imm, am.new_op2, am.ins_permuted, 0);
4873 set_am_attributes(cmp, &am);
4874 set_ia32_ls_mode(cmp, mode_Iu);
4876 SET_IA32_ORIG_NODE(cmp, node);
4878 cmp = fix_mem_proj(cmp, &am);
4881 new_node = new_bd_ia32_Setcc(dbgi, new_block, cmp, ia32_pn_Cmp_parity);
4882 SET_IA32_ORIG_NODE(new_node, node);
4885 new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP,
4886 nomem, new_node, mode_Bu);
4887 SET_IA32_ORIG_NODE(new_node, node);
4892 * Transform builtin popcount
4894 static ir_node *gen_popcount(ir_node *node) {
4895 ir_node *param = get_Builtin_param(node, 0);
4896 dbg_info *dbgi = get_irn_dbg_info(node);
4898 ir_node *block = get_nodes_block(node);
4899 ir_node *new_block = be_transform_node(block);
4902 ir_node *imm, *simm, *m1, *s1, *s2, *s3, *s4, *s5, *m2, *m3, *m4, *m5, *m6, *m7, *m8, *m9, *m10, *m11, *m12, *m13;
4904 /* check for SSE4.2 or SSE4a and use the popcnt instruction */
4905 if (ia32_cg_config.use_popcnt) {
4906 ia32_address_mode_t am;
4907 ia32_address_t *addr = &am.addr;
4910 match_arguments(&am, block, NULL, param, NULL, match_am | match_16bit_am);
4912 cnt = new_bd_ia32_Popcnt(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2);
4913 set_am_attributes(cnt, &am);
4914 set_ia32_ls_mode(cnt, get_irn_mode(param));
4916 SET_IA32_ORIG_NODE(cnt, node);
4917 return fix_mem_proj(cnt, &am);
4920 new_param = be_transform_node(param);
4922 /* do the standard popcount algo */
4924 /* m1 = x & 0x55555555 */
4925 imm = ia32_create_Immediate(NULL, 0, 0x55555555);
4926 m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_param, imm);
4929 simm = ia32_create_Immediate(NULL, 0, 1);
4930 s1 = new_bd_ia32_Shl(dbgi, new_block, new_param, simm);
4932 /* m2 = s1 & 0x55555555 */
4933 m2 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s1, imm);
4936 m3 = new_bd_ia32_Lea(dbgi, new_block, m2, m1);
4938 /* m4 = m3 & 0x33333333 */
4939 imm = ia32_create_Immediate(NULL, 0, 0x33333333);
4940 m4 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m3, imm);
4943 simm = ia32_create_Immediate(NULL, 0, 2);
4944 s2 = new_bd_ia32_Shl(dbgi, new_block, m3, simm);
4946 /* m5 = s2 & 0x33333333 */
4947 m5 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, imm);
4950 m6 = new_bd_ia32_Lea(dbgi, new_block, m4, m5);
4952 /* m7 = m6 & 0x0F0F0F0F */
4953 imm = ia32_create_Immediate(NULL, 0, 0x0F0F0F0F);
4954 m7 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m6, imm);
4957 simm = ia32_create_Immediate(NULL, 0, 4);
4958 s3 = new_bd_ia32_Shl(dbgi, new_block, m6, simm);
4960 /* m8 = s3 & 0x0F0F0F0F */
4961 m8 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, imm);
4964 m9 = new_bd_ia32_Lea(dbgi, new_block, m7, m8);
4966 /* m10 = m9 & 0x00FF00FF */
4967 imm = ia32_create_Immediate(NULL, 0, 0x00FF00FF);
4968 m10 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m9, imm);
4971 simm = ia32_create_Immediate(NULL, 0, 8);
4972 s4 = new_bd_ia32_Shl(dbgi, new_block, m9, simm);
4974 /* m11 = s4 & 0x00FF00FF */
4975 m11 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s4, imm);
4977 /* m12 = m10 + m11 */
4978 m12 = new_bd_ia32_Lea(dbgi, new_block, m10, m11);
4980 /* m13 = m12 & 0x0000FFFF */
4981 imm = ia32_create_Immediate(NULL, 0, 0x0000FFFF);
4982 m13 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m12, imm);
4984 /* s5 = m12 >> 16 */
4985 simm = ia32_create_Immediate(NULL, 0, 16);
4986 s5 = new_bd_ia32_Shl(dbgi, new_block, m12, simm);
4988 /* res = m13 + s5 */
4989 return new_bd_ia32_Lea(dbgi, new_block, m13, s5);
4993 * Transform builtin byte swap.
4995 static ir_node *gen_bswap(ir_node *node) {
4996 ir_node *param = be_transform_node(get_Builtin_param(node, 0));
4997 dbg_info *dbgi = get_irn_dbg_info(node);
4999 ir_node *block = get_nodes_block(node);
5000 ir_node *new_block = be_transform_node(block);
5001 ir_mode *mode = get_irn_mode(param);
5002 unsigned size = get_mode_size_bits(mode);
5003 ir_node *m1, *m2, *m3, *m4, *s1, *s2, *s3, *s4;
5007 if (ia32_cg_config.use_i486) {
5008 /* swap available */
5009 return new_bd_ia32_Bswap(dbgi, new_block, param);
5011 s1 = new_bd_ia32_Shl(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 24));
5012 s2 = new_bd_ia32_Shl(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 8));
5014 m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, ia32_create_Immediate(NULL, 0, 0xFF00));
5015 m2 = new_bd_ia32_Lea(dbgi, new_block, s1, m1);
5017 s3 = new_bd_ia32_Shr(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 8));
5019 m3 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, ia32_create_Immediate(NULL, 0, 0xFF0000));
5020 m4 = new_bd_ia32_Lea(dbgi, new_block, m2, m3);
5022 s4 = new_bd_ia32_Shr(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 24));
5023 return new_bd_ia32_Lea(dbgi, new_block, m4, s4);
5026 /* swap16 always available */
5027 return new_bd_ia32_Bswap16(dbgi, new_block, param);
5030 panic("Invalid bswap size (%d)", size);
5035 * Transform builtin outport.
5037 static ir_node *gen_outport(ir_node *node) {
5038 ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0);
5039 ir_node *oldv = get_Builtin_param(node, 1);
5040 ir_mode *mode = get_irn_mode(oldv);
5041 ir_node *value = be_transform_node(oldv);
5042 ir_node *block = be_transform_node(get_nodes_block(node));
5043 ir_node *mem = be_transform_node(get_Builtin_mem(node));
5044 dbg_info *dbgi = get_irn_dbg_info(node);
5046 ir_node *res = new_bd_ia32_Outport(dbgi, block, port, value, mem);
5047 set_ia32_ls_mode(res, mode);
5052 * Transform builtin inport.
5054 static ir_node *gen_inport(ir_node *node) {
5055 ir_type *tp = get_Builtin_type(node);
5056 ir_type *rstp = get_method_res_type(tp, 0);
5057 ir_mode *mode = get_type_mode(rstp);
5058 ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0);
5059 ir_node *block = be_transform_node(get_nodes_block(node));
5060 ir_node *mem = be_transform_node(get_Builtin_mem(node));
5061 dbg_info *dbgi = get_irn_dbg_info(node);
5063 ir_node *res = new_bd_ia32_Inport(dbgi, block, port, mem);
5064 set_ia32_ls_mode(res, mode);
5066 /* check for missing Result Proj */
5071 * Transform a builtin inner trampoline
5073 static ir_node *gen_inner_trampoline(ir_node *node) {
5074 ir_node *ptr = get_Builtin_param(node, 0);
5075 ir_node *callee = get_Builtin_param(node, 1);
5076 ir_node *env = be_transform_node(get_Builtin_param(node, 2));
5077 ir_node *mem = get_Builtin_mem(node);
5078 ir_node *block = get_nodes_block(node);
5079 ir_node *new_block = be_transform_node(block);
5083 ir_node *trampoline;
5085 dbg_info *dbgi = get_irn_dbg_info(node);
5086 ia32_address_t addr;
5088 /* construct store address */
5089 memset(&addr, 0, sizeof(addr));
5090 ia32_create_address_mode(&addr, ptr, 0);
5092 if (addr.base == NULL) {
5093 addr.base = noreg_GP;
5095 addr.base = be_transform_node(addr.base);
5098 if (addr.index == NULL) {
5099 addr.index = noreg_GP;
5101 addr.index = be_transform_node(addr.index);
5103 addr.mem = be_transform_node(mem);
5105 /* mov ecx, <env> */
5106 val = ia32_create_Immediate(NULL, 0, 0xB9);
5107 store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
5108 addr.index, addr.mem, val);
5109 set_irn_pinned(store, get_irn_pinned(node));
5110 set_ia32_op_type(store, ia32_AddrModeD);
5111 set_ia32_ls_mode(store, mode_Bu);
5112 set_address(store, &addr);
5116 store = new_bd_ia32_Store(dbgi, new_block, addr.base,
5117 addr.index, addr.mem, env);
5118 set_irn_pinned(store, get_irn_pinned(node));
5119 set_ia32_op_type(store, ia32_AddrModeD);
5120 set_ia32_ls_mode(store, mode_Iu);
5121 set_address(store, &addr);
5125 /* jmp rel <callee> */
5126 val = ia32_create_Immediate(NULL, 0, 0xE9);
5127 store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
5128 addr.index, addr.mem, val);
5129 set_irn_pinned(store, get_irn_pinned(node));
5130 set_ia32_op_type(store, ia32_AddrModeD);
5131 set_ia32_ls_mode(store, mode_Bu);
5132 set_address(store, &addr);
5136 trampoline = be_transform_node(ptr);
5138 /* the callee is typically an immediate */
5139 if (is_SymConst(callee)) {
5140 rel = new_bd_ia32_Const(dbgi, new_block, get_SymConst_entity(callee), 0, 0, -10);
5142 rel = new_bd_ia32_Lea(dbgi, new_block, be_transform_node(callee), ia32_create_Immediate(NULL, 0, -10));
5144 rel = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, nomem, rel, trampoline);
5146 store = new_bd_ia32_Store(dbgi, new_block, addr.base,
5147 addr.index, addr.mem, rel);
5148 set_irn_pinned(store, get_irn_pinned(node));
5149 set_ia32_op_type(store, ia32_AddrModeD);
5150 set_ia32_ls_mode(store, mode_Iu);
5151 set_address(store, &addr);
5156 return new_r_Tuple(new_block, 2, in);
5160 * Transform Builtin node.
5162 static ir_node *gen_Builtin(ir_node *node) {
5163 ir_builtin_kind kind = get_Builtin_kind(node);
5167 return gen_trap(node);
5168 case ir_bk_debugbreak:
5169 return gen_debugbreak(node);
5170 case ir_bk_return_address:
5171 return gen_return_address(node);
5172 case ir_bk_frame_address:
5173 return gen_frame_address(node);
5174 case ir_bk_prefetch:
5175 return gen_prefetch(node);
5177 return gen_ffs(node);
5179 return gen_clz(node);
5181 return gen_ctz(node);
5183 return gen_parity(node);
5184 case ir_bk_popcount:
5185 return gen_popcount(node);
5187 return gen_bswap(node);
5189 return gen_outport(node);
5191 return gen_inport(node);
5192 case ir_bk_inner_trampoline:
5193 return gen_inner_trampoline(node);
5195 panic("Builtin %s not implemented in IA32", get_builtin_kind_name(kind));
5199 * Transform Proj(Builtin) node.
5201 static ir_node *gen_Proj_Builtin(ir_node *proj) {
5202 ir_node *node = get_Proj_pred(proj);
5203 ir_node *new_node = be_transform_node(node);
5204 ir_builtin_kind kind = get_Builtin_kind(node);
5207 case ir_bk_return_address:
5208 case ir_bk_frame_address:
5213 case ir_bk_popcount:
5215 assert(get_Proj_proj(proj) == pn_Builtin_1_result);
5218 case ir_bk_debugbreak:
5219 case ir_bk_prefetch:
5221 assert(get_Proj_proj(proj) == pn_Builtin_M);
5224 if (get_Proj_proj(proj) == pn_Builtin_1_result) {
5225 return new_r_Proj(get_nodes_block(new_node),
5226 new_node, get_irn_mode(proj), pn_ia32_Inport_res);
5228 assert(get_Proj_proj(proj) == pn_Builtin_M);
5229 return new_r_Proj(get_nodes_block(new_node),
5230 new_node, mode_M, pn_ia32_Inport_M);
5232 case ir_bk_inner_trampoline:
5233 if (get_Proj_proj(proj) == pn_Builtin_1_result) {
5234 return get_Tuple_pred(new_node, 1);
5236 assert(get_Proj_proj(proj) == pn_Builtin_M);
5237 return get_Tuple_pred(new_node, 0);
5240 panic("Builtin %s not implemented in IA32", get_builtin_kind_name(kind));
5243 static ir_node *gen_be_IncSP(ir_node *node)
5245 ir_node *res = be_duplicate_node(node);
5246 arch_irn_add_flags(res, arch_irn_flags_modify_flags);
5252 * Transform the Projs from a be_Call.
5254 static ir_node *gen_Proj_be_Call(ir_node *node)
5256 ir_node *block = be_transform_node(get_nodes_block(node));
5257 ir_node *call = get_Proj_pred(node);
5258 ir_node *new_call = be_transform_node(call);
5259 dbg_info *dbgi = get_irn_dbg_info(node);
5260 long proj = get_Proj_proj(node);
5261 ir_mode *mode = get_irn_mode(node);
5264 if (proj == pn_be_Call_M_regular) {
5265 return new_rd_Proj(dbgi, block, new_call, mode_M, n_ia32_Call_mem);
5267 /* transform call modes */
5268 if (mode_is_data(mode)) {
5269 const arch_register_class_t *cls = arch_get_irn_reg_class_out(node);
5273 /* Map from be_Call to ia32_Call proj number */
5274 if (proj == pn_be_Call_sp) {
5275 proj = pn_ia32_Call_stack;
5276 } else if (proj == pn_be_Call_M_regular) {
5277 proj = pn_ia32_Call_M;
5279 arch_register_req_t const *const req = arch_get_register_req_out(node);
5280 int const n_outs = arch_irn_get_n_outs(new_call);
5283 assert(proj >= pn_be_Call_first_res);
5284 assert(req->type & arch_register_req_type_limited);
5286 for (i = 0; i < n_outs; ++i) {
5287 arch_register_req_t const *const new_req
5288 = arch_get_out_register_req(new_call, i);
5290 if (!(new_req->type & arch_register_req_type_limited) ||
5291 new_req->cls != req->cls ||
5292 *new_req->limited != *req->limited)
5301 res = new_rd_Proj(dbgi, block, new_call, mode, proj);
5303 /* TODO arch_set_irn_register() only operates on Projs, need variant with index */
5305 case pn_ia32_Call_stack:
5306 arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]);
5309 case pn_ia32_Call_fpcw:
5310 arch_set_irn_register(res, &ia32_fp_cw_regs[REG_FPCW]);
5318 * Transform the Projs from a Cmp.
5320 static ir_node *gen_Proj_Cmp(ir_node *node)
5322 /* this probably means not all mode_b nodes were lowered... */
5323 panic("trying to directly transform Proj_Cmp %+F (mode_b not lowered?)",
5328 * Transform the Projs from a Bound.
5330 static ir_node *gen_Proj_Bound(ir_node *node)
5332 ir_node *new_node, *block;
5333 ir_node *pred = get_Proj_pred(node);
5335 switch (get_Proj_proj(node)) {
5337 return be_transform_node(get_Bound_mem(pred));
5338 case pn_Bound_X_regular:
5339 new_node = be_transform_node(pred);
5340 block = get_nodes_block(new_node);
5341 return new_r_Proj(block, new_node, mode_X, pn_ia32_Jcc_true);
5342 case pn_Bound_X_except:
5343 new_node = be_transform_node(pred);
5344 block = get_nodes_block(new_node);
5345 return new_r_Proj(block, new_node, mode_X, pn_ia32_Jcc_false);
5347 return be_transform_node(get_Bound_index(pred));
5349 panic("unsupported Proj from Bound");
5353 static ir_node *gen_Proj_ASM(ir_node *node)
5355 ir_mode *mode = get_irn_mode(node);
5356 ir_node *pred = get_Proj_pred(node);
5357 ir_node *new_pred = be_transform_node(pred);
5358 ir_node *block = get_nodes_block(new_pred);
5359 long pos = get_Proj_proj(node);
5361 if (mode == mode_M) {
5362 pos = arch_irn_get_n_outs(new_pred)-1;
5363 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
5365 } else if (mode_is_float(mode)) {
5368 panic("unexpected proj mode at ASM");
5371 return new_r_Proj(block, new_pred, mode, pos);
5375 * Transform and potentially renumber Proj nodes.
5377 static ir_node *gen_Proj(ir_node *node)
5379 ir_node *pred = get_Proj_pred(node);
5382 switch (get_irn_opcode(pred)) {
5384 proj = get_Proj_proj(node);
5385 if (proj == pn_Store_M) {
5386 return be_transform_node(pred);
5388 panic("No idea how to transform proj->Store");
5391 return gen_Proj_Load(node);
5393 return gen_Proj_ASM(node);
5395 return gen_Proj_Builtin(node);
5399 return gen_Proj_DivMod(node);
5401 return gen_Proj_CopyB(node);
5403 return gen_Proj_Quot(node);
5405 return gen_Proj_be_SubSP(node);
5407 return gen_Proj_be_AddSP(node);
5409 return gen_Proj_be_Call(node);
5411 return gen_Proj_Cmp(node);
5413 return gen_Proj_Bound(node);
5415 proj = get_Proj_proj(node);
5417 case pn_Start_X_initial_exec: {
5418 ir_node *block = get_nodes_block(pred);
5419 ir_node *new_block = be_transform_node(block);
5420 dbg_info *dbgi = get_irn_dbg_info(node);
5421 /* we exchange the ProjX with a jump */
5422 ir_node *jump = new_rd_Jmp(dbgi, new_block);
5427 case pn_Start_P_tls:
5428 return gen_Proj_tls(node);
5433 if (is_ia32_l_FloattoLL(pred)) {
5434 return gen_Proj_l_FloattoLL(node);
5436 } else if (!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
5440 ir_mode *mode = get_irn_mode(node);
5441 if (ia32_mode_needs_gp_reg(mode)) {
5442 ir_node *new_pred = be_transform_node(pred);
5443 ir_node *block = be_transform_node(get_nodes_block(node));
5444 ir_node *new_proj = new_r_Proj(block, new_pred,
5445 mode_Iu, get_Proj_proj(node));
5446 new_proj->node_nr = node->node_nr;
5451 return be_duplicate_node(node);
5455 * Enters all transform functions into the generic pointer
5457 static void register_transformers(void)
5459 /* first clear the generic function pointer for all ops */
5460 clear_irp_opcodes_generic_func();
5462 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
5463 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
5503 /* transform ops from intrinsic lowering */
5515 GEN(ia32_l_LLtoFloat);
5516 GEN(ia32_l_FloattoLL);
5522 /* we should never see these nodes */
5537 /* handle builtins */
5540 /* handle generic backend nodes */
5554 * Pre-transform all unknown and noreg nodes.
5556 static void ia32_pretransform_node(void)
5558 ia32_code_gen_t *cg = env_cg;
5560 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
5561 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
5562 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
5563 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
5564 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
5565 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
5567 nomem = get_irg_no_mem(current_ir_graph);
5568 noreg_GP = ia32_new_NoReg_gp(cg);
5574 * Walker, checks if all ia32 nodes producing more than one result have their
5575 * Projs, otherwise creates new Projs and keeps them using a be_Keep node.
5577 static void add_missing_keep_walker(ir_node *node, void *data)
5580 unsigned found_projs = 0;
5581 const ir_edge_t *edge;
5582 ir_mode *mode = get_irn_mode(node);
5587 if (!is_ia32_irn(node))
5590 n_outs = arch_irn_get_n_outs(node);
5593 if (is_ia32_SwitchJmp(node))
5596 assert(n_outs < (int) sizeof(unsigned) * 8);
5597 foreach_out_edge(node, edge) {
5598 ir_node *proj = get_edge_src_irn(edge);
5601 /* The node could be kept */
5605 if (get_irn_mode(proj) == mode_M)
5608 pn = get_Proj_proj(proj);
5609 assert(pn < n_outs);
5610 found_projs |= 1 << pn;
5614 /* are keeps missing? */
5616 for (i = 0; i < n_outs; ++i) {
5619 const arch_register_req_t *req;
5620 const arch_register_class_t *cls;
5622 if (found_projs & (1 << i)) {
5626 req = arch_get_out_register_req(node, i);
5631 if (cls == &ia32_reg_classes[CLASS_ia32_flags]) {
5635 block = get_nodes_block(node);
5636 in[0] = new_r_Proj(block, node, arch_register_class_mode(cls), i);
5637 if (last_keep != NULL) {
5638 be_Keep_add_node(last_keep, cls, in[0]);
5640 last_keep = be_new_Keep(block, 1, in);
5641 if (sched_is_scheduled(node)) {
5642 sched_add_after(node, last_keep);
5649 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
5652 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
5654 ir_graph *irg = be_get_birg_irg(cg->birg);
5655 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
5659 * Post-process all calls if we are in SSE mode.
5660 * The ABI requires that the results are in st0, copy them
5661 * to a xmm register.
5663 static void postprocess_fp_call_results(void) {
5666 for (i = ARR_LEN(call_list) - 1; i >= 0; --i) {
5667 ir_node *call = call_list[i];
5668 ir_type *mtp = call_types[i];
5671 for (j = get_method_n_ress(mtp) - 1; j >= 0; --j) {
5672 ir_type *res_tp = get_method_res_type(mtp, j);
5673 ir_node *res, *new_res;
5674 const ir_edge_t *edge, *next;
5677 if (! is_atomic_type(res_tp)) {
5678 /* no floating point return */
5681 mode = get_type_mode(res_tp);
5682 if (! mode_is_float(mode)) {
5683 /* no floating point return */
5687 res = be_get_Proj_for_pn(call, pn_ia32_Call_vf0 + j);
5690 /* now patch the users */
5691 foreach_out_edge_safe(res, edge, next) {
5692 ir_node *succ = get_edge_src_irn(edge);
5695 if (be_is_Keep(succ))
5698 if (is_ia32_xStore(succ)) {
5699 /* an xStore can be patched into an vfst */
5700 dbg_info *db = get_irn_dbg_info(succ);
5701 ir_node *block = get_nodes_block(succ);
5702 ir_node *base = get_irn_n(succ, n_ia32_xStore_base);
5703 ir_node *index = get_irn_n(succ, n_ia32_xStore_index);
5704 ir_node *mem = get_irn_n(succ, n_ia32_xStore_mem);
5705 ir_node *value = get_irn_n(succ, n_ia32_xStore_val);
5706 ir_mode *mode = get_ia32_ls_mode(succ);
5708 ir_node *st = new_bd_ia32_vfst(db, block, base, index, mem, value, mode);
5709 set_ia32_am_offs_int(st, get_ia32_am_offs_int(succ));
5710 if (is_ia32_use_frame(succ))
5711 set_ia32_use_frame(st);
5712 set_ia32_frame_ent(st, get_ia32_frame_ent(succ));
5713 set_irn_pinned(st, get_irn_pinned(succ));
5714 set_ia32_op_type(st, ia32_AddrModeD);
5718 if (new_res == NULL) {
5719 dbg_info *db = get_irn_dbg_info(call);
5720 ir_node *block = get_nodes_block(call);
5721 ir_node *frame = get_irg_frame(current_ir_graph);
5722 ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M);
5723 ir_node *call_mem = new_r_Proj(block, call, mode_M, pn_ia32_Call_M);
5724 ir_node *vfst, *xld, *new_mem;
5726 /* store st(0) on stack */
5727 vfst = new_bd_ia32_vfst(db, block, frame, noreg_GP, call_mem, res, mode);
5728 set_ia32_op_type(vfst, ia32_AddrModeD);
5729 set_ia32_use_frame(vfst);
5731 /* load into SSE register */
5732 xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst, mode);
5733 set_ia32_op_type(xld, ia32_AddrModeS);
5734 set_ia32_use_frame(xld);
5736 new_res = new_r_Proj(block, xld, mode, pn_ia32_xLoad_res);
5737 new_mem = new_r_Proj(block, xld, mode_M, pn_ia32_xLoad_M);
5739 if (old_mem != NULL) {
5740 edges_reroute(old_mem, new_mem, current_ir_graph);
5744 set_irn_n(succ, get_edge_src_pos(edge), new_res);
5751 /* do the transformation */
5752 void ia32_transform_graph(ia32_code_gen_t *cg)
5756 register_transformers();
5758 initial_fpcw = NULL;
5761 be_timer_push(T_HEIGHTS);
5762 heights = heights_new(cg->irg);
5763 be_timer_pop(T_HEIGHTS);
5764 ia32_calculate_non_address_mode_nodes(cg->birg);
5766 /* the transform phase is not safe for CSE (yet) because several nodes get
5767 * attributes set after their creation */
5768 cse_last = get_opt_cse();
5771 call_list = NEW_ARR_F(ir_node *, 0);
5772 call_types = NEW_ARR_F(ir_type *, 0);
5773 be_transform_graph(cg->birg, ia32_pretransform_node);
5775 if (ia32_cg_config.use_sse2)
5776 postprocess_fp_call_results();
5777 DEL_ARR_F(call_types);
5778 DEL_ARR_F(call_list);
5780 set_opt_cse(cse_last);
5782 ia32_free_non_address_mode_nodes();
5783 heights_free(heights);
5787 void ia32_init_transform(void)
5789 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");