2 * This file implements the IR transformation from firm into
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
26 #include "../benode_t.h"
27 #include "bearch_ia32_t.h"
29 #include "ia32_nodes_attr.h"
30 #include "../arch/archop.h" /* we need this for Min and Max nodes */
31 #include "ia32_transform.h"
32 #include "ia32_new_nodes.h"
34 #include "gen_ia32_regalloc_if.h"
36 #define SFP_SIGN "0x80000000"
37 #define DFP_SIGN "0x8000000000000000"
38 #define SFP_ABS "0x7FFFFFFF"
39 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
41 #define TP_SFP_SIGN "ia32_sfp_sign"
42 #define TP_DFP_SIGN "ia32_dfp_sign"
43 #define TP_SFP_ABS "ia32_sfp_abs"
44 #define TP_DFP_ABS "ia32_dfp_abs"
46 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
47 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
48 #define ENT_SFP_ABS "IA32_SFP_ABS"
49 #define ENT_DFP_ABS "IA32_DFP_ABS"
51 extern ir_op *get_op_Mulh(void);
53 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
54 ir_node *op1, ir_node *op2, ir_node *mem, ir_mode *mode);
56 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
57 ir_node *op, ir_node *mem, ir_mode *mode);
60 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS
63 /****************************************************************************************************
65 * | | | | / _| | | (_)
66 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
67 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
68 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
69 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
71 ****************************************************************************************************/
78 /* Compares two (entity, tarval) combinations */
79 static int cmp_tv_ent(const void *a, const void *b, size_t len) {
80 const struct tv_ent *e1 = a;
81 const struct tv_ent *e2 = b;
83 return !(e1->tv == e2->tv);
86 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
87 static char *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
88 static set *const_set = NULL;
100 const_set = new_set(cmp_tv_ent, 10);
105 tp_name = TP_SFP_SIGN;
106 ent_name = ENT_SFP_SIGN;
110 tp_name = TP_DFP_SIGN;
111 ent_name = ENT_DFP_SIGN;
115 tp_name = TP_SFP_ABS;
116 ent_name = ENT_SFP_ABS;
120 tp_name = TP_DFP_ABS;
121 ent_name = ENT_DFP_ABS;
127 key.tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
130 entry = set_insert(const_set, &key, sizeof(key), HASH_PTR(key.tv));
133 tp = new_type_primitive(new_id_from_str(tp_name), mode);
134 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
136 set_entity_ld_ident(ent, get_entity_ident(ent));
137 set_entity_visibility(ent, visibility_local);
138 set_entity_variability(ent, variability_constant);
139 set_entity_allocation(ent, allocation_static);
141 /* we create a new entity here: It's initialization must resist on the
143 rem = current_ir_graph;
144 current_ir_graph = get_const_code_irg();
145 cnst = new_Const(mode, key.tv);
146 current_ir_graph = rem;
148 set_atomic_ent_value(ent, cnst);
150 /* set the entry for hashmap */
159 * Prints the old node name on cg obst and returns a pointer to it.
161 const char *get_old_node_name(ia32_transform_env_t *env) {
162 static int name_cnt = 0;
163 ia32_isa_t *isa = (ia32_isa_t *)env->cg->arch_env->isa;
165 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", env->irn);
166 obstack_1grow(isa->name_obst, 0);
167 isa->name_obst_size += obstack_object_size(isa->name_obst);
169 if (name_cnt % 1024 == 0) {
170 printf("name obst size reached %d bytes after %d nodes\n", isa->name_obst_size, name_cnt);
172 return obstack_finish(isa->name_obst);
176 /* determine if one operator is an Imm */
177 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
179 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
180 else return is_ia32_Cnst(op2) ? op2 : NULL;
183 /* determine if one operator is not an Imm */
184 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
185 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
190 * Construct a standard binary operation, set AM and immediate if required.
192 * @param env The transformation environment
193 * @param op1 The first operand
194 * @param op2 The second operand
195 * @param func The node constructor function
196 * @return The constructed ia32 node.
198 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
199 ir_node *new_op = NULL;
200 ir_mode *mode = env->mode;
201 dbg_info *dbg = env->dbg;
202 ir_graph *irg = env->irg;
203 ir_node *block = env->block;
204 firm_dbg_module_t *mod = env->mod;
205 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
206 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
207 ir_node *nomem = new_NoMem();
208 ir_node *expr_op, *imm_op;
210 /* Check if immediate optimization is on and */
211 /* if it's an operation with immediate. */
212 if (! env->cg->opt.immops) {
216 else if (is_op_commutative(get_irn_op(env->irn))) {
217 imm_op = get_immediate_op(op1, op2);
218 expr_op = get_expr_op(op1, op2);
221 imm_op = get_immediate_op(NULL, op2);
222 expr_op = get_expr_op(op1, op2);
225 assert((expr_op || imm_op) && "invalid operands");
228 /* We have two consts here: not yet supported */
232 if (mode_is_float(mode)) {
233 /* floating point operations */
235 DB((mod, LEVEL_1, "FP with immediate ..."));
236 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem, mode_T);
237 set_ia32_Immop_attr(new_op, imm_op);
238 set_ia32_am_support(new_op, ia32_am_None);
241 DB((mod, LEVEL_1, "FP binop ..."));
242 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
243 set_ia32_am_support(new_op, ia32_am_Source);
247 /* integer operations */
249 /* This is expr + const */
250 DB((mod, LEVEL_1, "INT with immediate ..."));
251 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem, mode_T);
252 set_ia32_Immop_attr(new_op, imm_op);
255 set_ia32_am_support(new_op, ia32_am_Dest);
258 DB((mod, LEVEL_1, "INT binop ..."));
259 /* This is a normal operation */
260 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
263 set_ia32_am_support(new_op, ia32_am_Full);
268 set_ia32_orig_node(new_op, get_old_node_name(env));
271 set_ia32_res_mode(new_op, mode);
273 if (is_op_commutative(get_irn_op(env->irn))) {
274 set_ia32_commutative(new_op);
277 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
283 * Construct a shift/rotate binary operation, sets AM and immediate if required.
285 * @param env The transformation environment
286 * @param op1 The first operand
287 * @param op2 The second operand
288 * @param func The node constructor function
289 * @return The constructed ia32 node.
291 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
292 ir_node *new_op = NULL;
293 ir_mode *mode = env->mode;
294 dbg_info *dbg = env->dbg;
295 ir_graph *irg = env->irg;
296 ir_node *block = env->block;
297 firm_dbg_module_t *mod = env->mod;
298 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
299 ir_node *nomem = new_NoMem();
300 ir_node *expr_op, *imm_op;
303 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
305 /* Check if immediate optimization is on and */
306 /* if it's an operation with immediate. */
307 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
308 expr_op = get_expr_op(op1, op2);
310 assert((expr_op || imm_op) && "invalid operands");
313 /* We have two consts here: not yet supported */
317 /* Limit imm_op within range imm8 */
319 tv = get_ia32_Immop_tarval(imm_op);
322 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
329 /* integer operations */
331 /* This is shift/rot with const */
332 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
334 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
335 set_ia32_Immop_attr(new_op, imm_op);
338 /* This is a normal shift/rot */
339 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
340 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
344 set_ia32_am_support(new_op, ia32_am_Dest);
347 set_ia32_orig_node(new_op, get_old_node_name(env));
350 set_ia32_res_mode(new_op, mode);
352 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
357 * Construct a standard unary operation, set AM and immediate if required.
359 * @param env The transformation environment
360 * @param op The operand
361 * @param func The node constructor function
362 * @return The constructed ia32 node.
364 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
365 ir_node *new_op = NULL;
366 ir_mode *mode = env->mode;
367 dbg_info *dbg = env->dbg;
368 firm_dbg_module_t *mod = env->mod;
369 ir_graph *irg = env->irg;
370 ir_node *block = env->block;
371 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
372 ir_node *nomem = new_NoMem();
374 new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
376 if (mode_is_float(mode)) {
377 DB((mod, LEVEL_1, "FP unop ..."));
378 /* floating point operations don't support implicit store */
379 set_ia32_am_support(new_op, ia32_am_None);
382 DB((mod, LEVEL_1, "INT unop ..."));
383 set_ia32_am_support(new_op, ia32_am_Dest);
387 set_ia32_orig_node(new_op, get_old_node_name(env));
390 set_ia32_res_mode(new_op, mode);
392 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
398 * Creates an ia32 Add with immediate.
400 * @param env The transformation environment
401 * @param expr_op The expression operator
402 * @param const_op The constant
403 * @return the created ia32 Add node
405 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
406 ir_node *new_op = NULL;
407 tarval *tv = get_ia32_Immop_tarval(const_op);
408 firm_dbg_module_t *mod = env->mod;
409 dbg_info *dbg = env->dbg;
410 ir_graph *irg = env->irg;
411 ir_node *block = env->block;
412 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
413 ir_node *nomem = new_NoMem();
415 tarval_classification_t class_tv, class_negtv;
417 /* try to optimize to inc/dec */
418 if (env->cg->opt.incdec && tv) {
419 /* optimize tarvals */
420 class_tv = classify_tarval(tv);
421 class_negtv = classify_tarval(tarval_neg(tv));
423 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
424 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
425 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
428 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
429 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
430 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
436 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
437 set_ia32_Immop_attr(new_op, const_op);
444 * Creates an ia32 Add.
446 * @param dbg firm node dbg
447 * @param block the block the new node should belong to
448 * @param op1 first operator
449 * @param op2 second operator
450 * @param mode node mode
451 * @return the created ia32 Add node
453 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
454 ir_node *new_op = NULL;
455 dbg_info *dbg = env->dbg;
456 ir_mode *mode = env->mode;
457 ir_graph *irg = env->irg;
458 ir_node *block = env->block;
459 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
460 ir_node *nomem = new_NoMem();
461 ir_node *expr_op, *imm_op;
463 /* Check if immediate optimization is on and */
464 /* if it's an operation with immediate. */
465 imm_op = env->cg->opt.immops ? get_immediate_op(op1, op2) : NULL;
466 expr_op = get_expr_op(op1, op2);
468 assert((expr_op || imm_op) && "invalid operands");
470 if (mode_is_float(mode)) {
471 return gen_binop(env, op1, op2, new_rd_ia32_fAdd);
476 /* No expr_op means, that we have two const - one symconst and */
477 /* one tarval or another symconst - because this case is not */
478 /* covered by constant folding */
480 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
481 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
482 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
485 set_ia32_am_support(new_op, ia32_am_Source);
486 set_ia32_op_type(new_op, ia32_AddrModeS);
487 set_ia32_am_flavour(new_op, ia32_am_O);
489 /* Lea doesn't need a Proj */
493 /* This is expr + const */
494 new_op = gen_imm_Add(env, expr_op, imm_op);
497 set_ia32_am_support(new_op, ia32_am_Dest);
500 /* This is a normal add */
501 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
504 set_ia32_am_support(new_op, ia32_am_Full);
509 set_ia32_orig_node(new_op, get_old_node_name(env));
512 set_ia32_res_mode(new_op, mode);
514 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
520 * Creates an ia32 Mul.
522 * @param dbg firm node dbg
523 * @param block the block the new node should belong to
524 * @param op1 first operator
525 * @param op2 second operator
526 * @param mode node mode
527 * @return the created ia32 Mul node
529 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
532 if (mode_is_float(env->mode)) {
533 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul);
536 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
545 * Creates an ia32 Mulh.
546 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
547 * this result while Mul returns the lower 32 bit.
549 * @param env The transformation environment
550 * @param op1 The first operator
551 * @param op2 The second operator
552 * @return the created ia32 Mulh node
554 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
555 ir_node *proj_EAX, *proj_EDX, *mulh;
558 assert(mode_is_float(env->mode) && "Mulh with float not supported");
559 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
560 mulh = get_Proj_pred(proj_EAX);
561 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
563 /* to be on the save side */
564 set_Proj_proj(proj_EAX, pn_EAX);
566 if (get_ia32_cnst(mulh)) {
567 /* Mulh with const cannot have AM */
568 set_ia32_am_support(mulh, ia32_am_None);
571 /* Mulh cannot have AM for destination */
572 set_ia32_am_support(mulh, ia32_am_Source);
578 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
586 * Creates an ia32 And.
588 * @param env The transformation environment
589 * @param op1 The first operator
590 * @param op2 The second operator
591 * @return The created ia32 And node
593 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
594 if (mode_is_float(env->mode)) {
595 return gen_binop(env, op1, op2, new_rd_ia32_fAnd);
598 return gen_binop(env, op1, op2, new_rd_ia32_And);
605 * Creates an ia32 Or.
607 * @param env The transformation environment
608 * @param op1 The first operator
609 * @param op2 The second operator
610 * @return The created ia32 Or node
612 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
613 if (mode_is_float(env->mode)) {
614 return gen_binop(env, op1, op2, new_rd_ia32_fOr);
617 return gen_binop(env, op1, op2, new_rd_ia32_Or);
624 * Creates an ia32 Eor.
626 * @param env The transformation environment
627 * @param op1 The first operator
628 * @param op2 The second operator
629 * @return The created ia32 Eor node
631 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
632 if (mode_is_float(env->mode)) {
633 return gen_binop(env, op1, op2, new_rd_ia32_fEor);
636 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
643 * Creates an ia32 Max.
645 * @param env The transformation environment
646 * @param op1 The first operator
647 * @param op2 The second operator
648 * @return the created ia32 Max node
650 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
653 if (mode_is_float(env->mode)) {
654 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
657 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
658 set_ia32_am_support(new_op, ia32_am_None);
660 set_ia32_orig_node(new_op, get_old_node_name(env));
670 * Creates an ia32 Min.
672 * @param env The transformation environment
673 * @param op1 The first operator
674 * @param op2 The second operator
675 * @return the created ia32 Min node
677 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
680 if (mode_is_float(env->mode)) {
681 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
684 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
685 set_ia32_am_support(new_op, ia32_am_None);
687 set_ia32_orig_node(new_op, get_old_node_name(env));
697 * Creates an ia32 Sub with immediate.
699 * @param env The transformation environment
700 * @param op1 The first operator
701 * @param op2 The second operator
702 * @return The created ia32 Sub node
704 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
705 ir_node *new_op = NULL;
706 tarval *tv = get_ia32_Immop_tarval(const_op);
707 firm_dbg_module_t *mod = env->mod;
708 dbg_info *dbg = env->dbg;
709 ir_graph *irg = env->irg;
710 ir_node *block = env->block;
711 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
712 ir_node *nomem = new_NoMem();
714 tarval_classification_t class_tv, class_negtv;
716 /* try to optimize to inc/dec */
717 if (env->cg->opt.incdec && tv) {
718 /* optimize tarvals */
719 class_tv = classify_tarval(tv);
720 class_negtv = classify_tarval(tarval_neg(tv));
722 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
723 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
724 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
727 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
728 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
729 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
735 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
736 set_ia32_Immop_attr(new_op, const_op);
743 * Creates an ia32 Sub.
745 * @param env The transformation environment
746 * @param op1 The first operator
747 * @param op2 The second operator
748 * @return The created ia32 Sub node
750 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
751 ir_node *new_op = NULL;
752 dbg_info *dbg = env->dbg;
753 ir_mode *mode = env->mode;
754 ir_graph *irg = env->irg;
755 ir_node *block = env->block;
756 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
757 ir_node *nomem = new_NoMem();
758 ir_node *expr_op, *imm_op;
760 /* Check if immediate optimization is on and */
761 /* if it's an operation with immediate. */
762 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
763 expr_op = get_expr_op(op1, op2);
765 assert((expr_op || imm_op) && "invalid operands");
767 if (mode_is_float(mode)) {
768 return gen_binop(env, op1, op2, new_rd_ia32_fSub);
773 /* No expr_op means, that we have two const - one symconst and */
774 /* one tarval or another symconst - because this case is not */
775 /* covered by constant folding */
777 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
778 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
779 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
782 set_ia32_am_support(new_op, ia32_am_Source);
783 set_ia32_op_type(new_op, ia32_AddrModeS);
784 set_ia32_am_flavour(new_op, ia32_am_O);
786 /* Lea doesn't need a Proj */
790 /* This is expr - const */
791 new_op = gen_imm_Sub(env, expr_op, imm_op);
794 set_ia32_am_support(new_op, ia32_am_Dest);
797 /* This is a normal sub */
798 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
801 set_ia32_am_support(new_op, ia32_am_Full);
806 set_ia32_orig_node(new_op, get_old_node_name(env));
809 set_ia32_res_mode(new_op, mode);
811 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
817 * Generates an ia32 DivMod with additional infrastructure for the
818 * register allocator if needed.
820 * @param env The transformation environment
821 * @param dividend -no comment- :)
822 * @param divisor -no comment- :)
823 * @param dm_flav flavour_Div/Mod/DivMod
824 * @return The created ia32 DivMod node
826 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
828 ir_node *edx_node, *cltd;
830 dbg_info *dbg = env->dbg;
831 ir_graph *irg = env->irg;
832 ir_node *block = env->block;
833 ir_mode *mode = env->mode;
834 ir_node *irn = env->irn;
839 mem = get_Div_mem(irn);
842 mem = get_Mod_mem(irn);
845 mem = get_DivMod_mem(irn);
851 if (mode_is_signed(mode)) {
852 /* in signed mode, we need to sign extend the dividend */
853 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend, mode_T);
854 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EAX);
855 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EDX);
858 edx_node = new_rd_ia32_Const(dbg, irg, block, mode_Iu);
859 set_ia32_Const_type(edx_node, ia32_Const);
860 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
863 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode_T);
865 set_ia32_flavour(res, dm_flav);
866 set_ia32_n_res(res, 2);
868 /* Only one proj is used -> We must add a second proj and */
869 /* connect this one to a Keep node to eat up the second */
870 /* destroyed register. */
871 if (get_irn_n_edges(irn) == 1) {
872 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
873 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
875 if (get_Proj_proj(proj) == pn_DivMod_res_div) {
876 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
879 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
882 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
886 set_ia32_orig_node(res, get_old_node_name(env));
889 set_ia32_res_mode(res, mode_Is);
896 * Wrapper for generate_DivMod. Sets flavour_Mod.
898 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
899 return generate_DivMod(env, op1, op2, flavour_Mod);
905 * Wrapper for generate_DivMod. Sets flavour_Div.
907 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
908 return generate_DivMod(env, op1, op2, flavour_Div);
914 * Wrapper for generate_DivMod. Sets flavour_DivMod.
916 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
917 return generate_DivMod(env, op1, op2, flavour_DivMod);
923 * Creates an ia32 floating Div.
925 * @param env The transformation environment
926 * @param op1 The first operator
927 * @param op2 The second operator
928 * @return The created ia32 fDiv node
930 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
931 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
932 ir_node *nomem = new_rd_NoMem(env->irg);
935 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, env->mode);
936 set_ia32_am_support(new_op, ia32_am_Source);
939 set_ia32_orig_node(new_op, get_old_node_name(env));
948 * Creates an ia32 Shl.
950 * @param env The transformation environment
951 * @param op1 The first operator
952 * @param op2 The second operator
953 * @return The created ia32 Shl node
955 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
956 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shl);
962 * Creates an ia32 Shr.
964 * @param env The transformation environment
965 * @param op1 The first operator
966 * @param op2 The second operator
967 * @return The created ia32 Shr node
969 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
970 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shr);
976 * Creates an ia32 Shrs.
978 * @param env The transformation environment
979 * @param op1 The first operator
980 * @param op2 The second operator
981 * @return The created ia32 Shrs node
983 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
984 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shrs);
990 * Creates an ia32 RotL.
992 * @param env The transformation environment
993 * @param op1 The first operator
994 * @param op2 The second operator
995 * @return The created ia32 RotL node
997 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
998 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1004 * Creates an ia32 RotR.
1005 * NOTE: There is no RotR with immediate because this would always be a RotL
1006 * "imm-mode_size_bits" which can be pre-calculated.
1008 * @param env The transformation environment
1009 * @param op1 The first operator
1010 * @param op2 The second operator
1011 * @return The created ia32 RotR node
1013 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1014 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1020 * Creates an ia32 RotR or RotL (depending on the found pattern).
1022 * @param env The transformation environment
1023 * @param op1 The first operator
1024 * @param op2 The second operator
1025 * @return The created ia32 RotL or RotR node
1027 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1028 ir_node *rotate = NULL;
1030 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1031 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1032 that means we can create a RotR instead of an Add and a RotL */
1035 ir_node *pred = get_Proj_pred(op2);
1037 if (is_ia32_Add(pred)) {
1038 ir_node *pred_pred = get_irn_n(pred, 2);
1039 tarval *tv = get_ia32_Immop_tarval(pred);
1040 long bits = get_mode_size_bits(env->mode);
1042 if (is_Proj(pred_pred)) {
1043 pred_pred = get_Proj_pred(pred_pred);
1046 if (is_ia32_Minus(pred_pred) &&
1047 tarval_is_long(tv) &&
1048 get_tarval_long(tv) == bits)
1050 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1051 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1058 rotate = gen_RotL(env, op1, op2);
1067 * Transforms a Minus node.
1069 * @param env The transformation environment
1070 * @param op The operator
1071 * @return The created ia32 Minus node
1073 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
1076 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1077 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1078 ir_node *nomem = new_rd_NoMem(env->irg);
1081 if (mode_is_float(env->mode)) {
1082 new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1084 size = get_mode_size_bits(env->mode);
1085 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1087 set_ia32_sc(new_op, name);
1090 set_ia32_orig_node(new_op, get_old_node_name(env));
1093 set_ia32_res_mode(new_op, env->mode);
1095 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1098 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1107 * Transforms a Not node.
1109 * @param env The transformation environment
1110 * @param op The operator
1111 * @return The created ia32 Not node
1113 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) {
1116 if (mode_is_float(env->mode)) {
1120 new_op = gen_unop(env, op, new_rd_ia32_Not);
1129 * Transforms an Abs node.
1131 * @param env The transformation environment
1132 * @param op The operator
1133 * @return The created ia32 Abs node
1135 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
1136 ir_node *res, *p_eax, *p_edx;
1137 dbg_info *dbg = env->dbg;
1138 ir_mode *mode = env->mode;
1139 ir_graph *irg = env->irg;
1140 ir_node *block = env->block;
1141 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1142 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1143 ir_node *nomem = new_NoMem();
1147 if (mode_is_float(mode)) {
1148 res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1150 size = get_mode_size_bits(mode);
1151 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1153 set_ia32_sc(res, name);
1156 set_ia32_orig_node(res, get_old_node_name(env));
1159 set_ia32_res_mode(res, mode);
1161 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1164 res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T);
1166 set_ia32_orig_node(res, get_old_node_name(env));
1168 set_ia32_res_mode(res, mode);
1170 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
1171 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
1173 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T);
1175 set_ia32_orig_node(res, get_old_node_name(env));
1177 set_ia32_res_mode(res, mode);
1179 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1181 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T);
1183 set_ia32_orig_node(res, get_old_node_name(env));
1185 set_ia32_res_mode(res, mode);
1187 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1196 * Transforms a Load.
1198 * @param mod the debug module
1199 * @param block the block the new node should belong to
1200 * @param node the ir Load node
1201 * @param mode node mode
1202 * @return the created ia32 Load node
1204 static ir_node *gen_Load(ia32_transform_env_t *env) {
1205 ir_node *node = env->irn;
1206 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1209 if (mode_is_float(env->mode)) {
1210 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1213 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1216 set_ia32_am_support(new_op, ia32_am_Source);
1217 set_ia32_op_type(new_op, ia32_AddrModeS);
1218 set_ia32_am_flavour(new_op, ia32_B);
1219 set_ia32_ls_mode(new_op, get_Load_mode(node));
1222 set_ia32_orig_node(new_op, get_old_node_name(env));
1231 * Transforms a Store.
1233 * @param mod the debug module
1234 * @param block the block the new node should belong to
1235 * @param node the ir Store node
1236 * @param mode node mode
1237 * @return the created ia32 Store node
1239 static ir_node *gen_Store(ia32_transform_env_t *env) {
1240 ir_node *node = env->irn;
1241 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1242 ir_node *val = get_Store_value(node);
1243 ir_node *ptr = get_Store_ptr(node);
1244 ir_node *mem = get_Store_mem(node);
1245 ir_node *sval = val;
1248 /* in case of storing a const -> make it an attribute */
1249 if (is_ia32_Cnst(val)) {
1253 if (mode_is_float(env->mode)) {
1254 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode);
1257 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode);
1260 /* stored const is an attribute (saves a register) */
1261 if (is_ia32_Cnst(val)) {
1262 set_ia32_Immop_attr(new_op, val);
1265 set_ia32_am_support(new_op, ia32_am_Dest);
1266 set_ia32_op_type(new_op, ia32_AddrModeD);
1267 set_ia32_am_flavour(new_op, ia32_B);
1268 set_ia32_ls_mode(new_op, get_irn_mode(val));
1271 set_ia32_orig_node(new_op, get_old_node_name(env));
1280 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp or CondJmp_i
1282 * @param env The transformation environment
1283 * @return The transformed node.
1285 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1286 dbg_info *dbg = env->dbg;
1287 ir_graph *irg = env->irg;
1288 ir_node *block = env->block;
1289 ir_node *node = env->irn;
1290 ir_node *sel = get_Cond_selector(node);
1291 ir_mode *sel_mode = get_irn_mode(sel);
1292 ir_node *res = NULL;
1293 ir_node *pred = NULL;
1294 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1295 ir_node *nomem = new_NoMem();
1296 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1298 if (is_Proj(sel) && sel_mode == mode_b) {
1299 pred = get_Proj_pred(sel);
1301 /* get both compare operators */
1302 cmp_a = get_Cmp_left(pred);
1303 cmp_b = get_Cmp_right(pred);
1305 /* check if we can use a CondJmp with immediate */
1306 cnst = env->cg->opt.immops ? get_immediate_op(cmp_a, cmp_b) : NULL;
1307 expr = get_expr_op(cmp_a, cmp_b);
1310 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1311 set_ia32_Immop_attr(res, cnst);
1314 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1317 set_ia32_pncode(res, get_Proj_proj(sel));
1318 set_ia32_am_support(res, ia32_am_Source);
1321 res = new_rd_ia32_SwitchJmp(dbg, irg, block, sel, mode_T);
1322 set_ia32_pncode(res, get_Cond_defaultProj(node));
1326 set_ia32_orig_node(res, get_old_node_name(env));
1335 * Transforms a CopyB node.
1337 * @param env The transformation environment
1338 * @return The transformed node.
1340 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1341 ir_node *res = NULL;
1342 dbg_info *dbg = env->dbg;
1343 ir_graph *irg = env->irg;
1344 ir_mode *mode = env->mode;
1345 ir_node *block = env->block;
1346 ir_node *node = env->irn;
1347 ir_node *src = get_CopyB_src(node);
1348 ir_node *dst = get_CopyB_dst(node);
1349 ir_node *mem = get_CopyB_mem(node);
1350 int size = get_type_size_bytes(get_CopyB_type(node));
1353 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1354 /* then we need the size explicitly in ECX. */
1355 if (size >= 16 * 4) {
1356 rem = size & 0x3; /* size % 4 */
1359 res = new_rd_ia32_Const(dbg, irg, block, mode_Is);
1360 set_ia32_op_type(res, ia32_Const);
1361 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1363 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1364 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1367 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1368 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1372 set_ia32_orig_node(res, get_old_node_name(env));
1381 * Transforms a Mux node into CMov.
1383 * @param env The transformation environment
1384 * @return The transformed node.
1386 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1387 ir_node *node = env->irn;
1388 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1389 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1392 set_ia32_orig_node(new_op, get_old_node_name(env));
1401 * Transforms a Conv node.
1403 * @param env The transformation environment
1404 * @param op The operator
1405 * @return The created ia32 Conv node
1407 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
1408 dbg_info *dbg = env->dbg;
1409 ir_graph *irg = env->irg;
1410 ir_mode *src_mode = get_irn_mode(op);
1411 ir_mode *tgt_mode = env->mode;
1412 ir_node *block = env->block;
1413 ir_node *new_op = NULL;
1414 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1415 ir_node *nomem = new_rd_NoMem(irg);
1416 firm_dbg_module_t *mod = env->mod;
1418 if (src_mode == tgt_mode) {
1419 /* this can happen when changing mode_P to mode_Is */
1420 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1421 edges_reroute(env->irn, op, irg);
1423 else if (mode_is_float(src_mode)) {
1424 /* we convert from float ... */
1425 if (mode_is_float(tgt_mode)) {
1427 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1428 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1432 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1433 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1437 /* we convert from int ... */
1438 if (mode_is_float(tgt_mode)) {
1440 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1441 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1445 DB((mod, LEVEL_1, "omitting Conv(Int, Int) ..."));
1446 edges_reroute(env->irn, op, irg);
1452 set_ia32_orig_node(new_op, get_old_node_name(env));
1454 set_ia32_res_mode(new_op, tgt_mode);
1456 set_ia32_am_support(new_op, ia32_am_Source);
1458 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
1466 /********************************************
1469 * | |__ ___ _ __ ___ __| | ___ ___
1470 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1471 * | |_) | __/ | | | (_) | (_| | __/\__ \
1472 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1474 ********************************************/
1477 * Transforms a FrameAddr into an ia32 Add.
1479 static ir_node *gen_FrameAddr(ia32_transform_env_t *env) {
1480 ir_node *new_op = NULL;
1481 ir_node *node = env->irn;
1482 ir_node *op = get_irn_n(node, 0);
1483 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1484 ir_node *nomem = new_rd_NoMem(env->irg);
1486 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem, mode_T);
1487 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1488 set_ia32_am_support(new_op, ia32_am_Full);
1489 set_ia32_use_frame(new_op);
1492 set_ia32_orig_node(new_op, get_old_node_name(env));
1495 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1499 * Transforms a FrameLoad into an ia32 Load.
1501 static ir_node *gen_FrameLoad(ia32_transform_env_t *env) {
1502 ir_node *new_op = NULL;
1503 ir_node *node = env->irn;
1504 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1505 ir_node *mem = get_irn_n(node, 0);
1506 ir_node *ptr = get_irn_n(node, 1);
1507 entity *ent = be_get_frame_entity(node);
1508 ir_mode *mode = get_type_mode(get_entity_type(ent));
1510 if (mode_is_float(mode)) {
1511 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1514 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1517 set_ia32_frame_ent(new_op, ent);
1519 set_ia32_am_support(new_op, ia32_am_Source);
1520 set_ia32_op_type(new_op, ia32_AddrModeS);
1521 set_ia32_am_flavour(new_op, ia32_B);
1522 set_ia32_ls_mode(new_op, mode);
1525 set_ia32_orig_node(new_op, get_old_node_name(env));
1533 * Transforms a FrameStore into an ia32 Store.
1535 static ir_node *gen_FrameStore(ia32_transform_env_t *env) {
1536 ir_node *new_op = NULL;
1537 ir_node *node = env->irn;
1538 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1539 ir_node *mem = get_irn_n(node, 0);
1540 ir_node *ptr = get_irn_n(node, 1);
1541 ir_node *val = get_irn_n(node, 2);
1542 entity *ent = be_get_frame_entity(node);
1543 ir_mode *mode = get_irn_mode(val);
1545 if (mode_is_float(mode)) {
1546 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1549 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1551 set_ia32_frame_ent(new_op, ent);
1553 set_ia32_am_support(new_op, ia32_am_Dest);
1554 set_ia32_op_type(new_op, ia32_AddrModeD);
1555 set_ia32_am_flavour(new_op, ia32_B);
1556 set_ia32_ls_mode(new_op, mode);
1559 set_ia32_orig_node(new_op, get_old_node_name(env));
1567 /*********************************************************
1570 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1571 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1572 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1573 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1575 *********************************************************/
1578 * Transforms the given firm node (and maybe some other related nodes)
1579 * into one or more assembler nodes.
1581 * @param node the firm node
1582 * @param env the debug module
1584 void ia32_transform_node(ir_node *node, void *env) {
1585 ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env;
1586 opcode code = get_irn_opcode(node);
1587 ir_node *asm_node = NULL;
1588 ia32_transform_env_t tenv;
1593 tenv.block = get_nodes_block(node);
1594 tenv.dbg = get_irn_dbg_info(node);
1595 tenv.irg = current_ir_graph;
1597 tenv.mod = cgenv->mod;
1598 tenv.mode = get_irn_mode(node);
1601 #define UNOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_op(node)); break
1602 #define BINOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_left(node), get_##a##_right(node)); break
1603 #define GEN(a) case iro_##a: asm_node = gen_##a(&tenv); break
1604 #define IGN(a) case iro_##a: break
1605 #define BAD(a) case iro_##a: goto bad
1606 #define OTHER_BIN(a) \
1607 if (get_irn_op(node) == get_op_##a()) { \
1608 asm_node = gen_##a(&tenv, get_irn_n(node, 0), get_irn_n(node, 1)); \
1612 if (be_is_##a(node)) { \
1613 asm_node = gen_##a(&tenv); \
1617 DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
1664 /* constant transformation happens earlier */
1693 fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
1697 /* exchange nodes if a new one was generated */
1699 exchange(node, asm_node);
1700 DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
1703 DB((tenv.mod, LEVEL_1, "ignored\n"));