2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
99 extern ir_op *get_op_Mulh(void);
101 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
102 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
103 ir_node *op1, ir_node *op2);
105 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
106 ir_node *block, ir_node *op1, ir_node *op2);
108 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
109 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
112 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
113 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
115 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
116 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 ir_node *op1, ir_node *op2, ir_node *fpcw);
119 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
120 ir_node *block, ir_node *op);
122 /****************************************************************************************************
124 * | | | | / _| | | (_)
125 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
126 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
127 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
128 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
130 ****************************************************************************************************/
132 static ir_node *try_create_Immediate(ir_node *node,
133 char immediate_constraint_type);
135 static ir_node *create_immediate_or_transform(ir_node *node,
136 char immediate_constraint_type);
138 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
139 dbg_info *dbgi, ir_node *block,
140 ir_node *op, ir_node *orig_node);
143 * Return true if a mode can be stored in the GP register set
145 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
146 if(mode == mode_fpcw)
148 if(get_mode_size_bits(mode) > 32)
150 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
154 * creates a unique ident by adding a number to a tag
156 * @param tag the tag string, must contain a %d if a number
159 static ident *unique_id(const char *tag)
161 static unsigned id = 0;
164 snprintf(str, sizeof(str), tag, ++id);
165 return new_id_from_str(str);
169 * Get a primitive type for a mode.
171 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
173 pmap_entry *e = pmap_find(types, mode);
178 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
179 res = new_type_primitive(new_id_from_str(buf), mode);
180 set_type_alignment_bytes(res, 16);
181 pmap_insert(types, mode, res);
189 * Get an atomic entity that is initialized with a tarval
191 static ir_entity *ia32_get_entity_for_tv(ia32_isa_t *isa, ir_node *cnst)
193 tarval *tv = get_Const_tarval(cnst);
194 pmap_entry *e = pmap_find(isa->tv_ent, tv);
199 ir_mode *mode = get_irn_mode(cnst);
200 ir_type *tp = get_Const_type(cnst);
201 if (tp == firm_unknown_type)
202 tp = get_prim_type(isa->types, mode);
204 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
206 set_entity_ld_ident(res, get_entity_ident(res));
207 set_entity_visibility(res, visibility_local);
208 set_entity_variability(res, variability_constant);
209 set_entity_allocation(res, allocation_static);
211 /* we create a new entity here: It's initialization must resist on the
213 rem = current_ir_graph;
214 current_ir_graph = get_const_code_irg();
215 set_atomic_ent_value(res, new_Const_type(tv, tp));
216 current_ir_graph = rem;
218 pmap_insert(isa->tv_ent, tv, res);
226 static int is_Const_0(ir_node *node) {
227 return is_Const(node) && is_Const_null(node);
230 static int is_Const_1(ir_node *node) {
231 return is_Const(node) && is_Const_one(node);
234 static int is_Const_Minus_1(ir_node *node) {
235 return is_Const(node) && is_Const_all_one(node);
239 * Transforms a Const.
241 static ir_node *gen_Const(ir_node *node) {
242 ir_graph *irg = current_ir_graph;
243 ir_node *old_block = get_nodes_block(node);
244 ir_node *block = be_transform_node(old_block);
245 dbg_info *dbgi = get_irn_dbg_info(node);
246 ir_mode *mode = get_irn_mode(node);
248 if (mode_is_float(mode)) {
250 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
251 ir_node *nomem = new_NoMem();
255 if (USE_SSE2(env_cg)) {
256 if (is_Const_null(node)) {
257 load = new_rd_ia32_xZero(dbgi, irg, block);
258 set_ia32_ls_mode(load, mode);
261 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
263 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
265 set_ia32_op_type(load, ia32_AddrModeS);
266 set_ia32_am_sc(load, floatent);
267 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
268 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
271 if (is_Const_null(node)) {
272 load = new_rd_ia32_vfldz(dbgi, irg, block);
274 } else if (is_Const_one(node)) {
275 load = new_rd_ia32_vfld1(dbgi, irg, block);
278 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
280 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
281 set_ia32_op_type(load, ia32_AddrModeS);
282 set_ia32_am_sc(load, floatent);
283 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
284 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
286 set_ia32_ls_mode(load, mode);
289 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
291 /* Const Nodes before the initial IncSP are a bad idea, because
292 * they could be spilled and we have no SP ready at that point yet.
293 * So add a dependency to the initial frame pointer calculation to
294 * avoid that situation.
296 if (get_irg_start_block(irg) == block) {
297 add_irn_dep(load, get_irg_frame(irg));
300 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
304 tarval *tv = get_Const_tarval(node);
307 tv = tarval_convert_to(tv, mode_Iu);
309 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
311 panic("couldn't convert constant tarval (%+F)", node);
313 val = get_tarval_long(tv);
315 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
316 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
319 get_ia32_flags(cnst) | arch_irn_flags_modify_flags);
323 if (get_irg_start_block(irg) == block) {
324 add_irn_dep(cnst, get_irg_frame(irg));
332 * Transforms a SymConst.
334 static ir_node *gen_SymConst(ir_node *node) {
335 ir_graph *irg = current_ir_graph;
336 ir_node *old_block = get_nodes_block(node);
337 ir_node *block = be_transform_node(old_block);
338 dbg_info *dbgi = get_irn_dbg_info(node);
339 ir_mode *mode = get_irn_mode(node);
342 if (mode_is_float(mode)) {
343 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
344 ir_node *nomem = new_NoMem();
346 if (USE_SSE2(env_cg))
347 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
349 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
350 set_ia32_am_sc(cnst, get_SymConst_entity(node));
351 set_ia32_use_frame(cnst);
355 if(get_SymConst_kind(node) != symconst_addr_ent) {
356 panic("backend only support symconst_addr_ent (at %+F)", node);
358 entity = get_SymConst_entity(node);
359 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
362 /* Const Nodes before the initial IncSP are a bad idea, because
363 * they could be spilled and we have no SP ready at that point yet
365 if (get_irg_start_block(irg) == block) {
366 add_irn_dep(cnst, get_irg_frame(irg));
369 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
374 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
375 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
376 static const struct {
378 const char *ent_name;
379 const char *cnst_str;
382 } names [ia32_known_const_max] = {
383 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
384 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
385 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
386 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
387 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
389 static ir_entity *ent_cache[ia32_known_const_max];
391 const char *tp_name, *ent_name, *cnst_str;
399 ent_name = names[kct].ent_name;
400 if (! ent_cache[kct]) {
401 tp_name = names[kct].tp_name;
402 cnst_str = names[kct].cnst_str;
404 switch (names[kct].mode) {
405 case 0: mode = mode_Iu; break;
406 case 1: mode = mode_Lu; break;
407 default: mode = mode_F; break;
409 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
410 tp = new_type_primitive(new_id_from_str(tp_name), mode);
411 /* set the specified alignment */
412 set_type_alignment_bytes(tp, names[kct].align);
414 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
416 set_entity_ld_ident(ent, get_entity_ident(ent));
417 set_entity_visibility(ent, visibility_local);
418 set_entity_variability(ent, variability_constant);
419 set_entity_allocation(ent, allocation_static);
421 /* we create a new entity here: It's initialization must resist on the
423 rem = current_ir_graph;
424 current_ir_graph = get_const_code_irg();
425 cnst = new_Const(mode, tv);
426 current_ir_graph = rem;
428 set_atomic_ent_value(ent, cnst);
430 /* cache the entry */
431 ent_cache[kct] = ent;
434 return ent_cache[kct];
439 * Prints the old node name on cg obst and returns a pointer to it.
441 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
442 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
444 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
445 obstack_1grow(isa->name_obst, 0);
446 return obstack_finish(isa->name_obst);
450 int use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
458 load = get_Proj_pred(node);
459 pn = get_Proj_proj(node);
460 if(!is_Load(load) || pn != pn_Load_res)
462 if(get_nodes_block(load) != block)
464 /* we only use address mode if we're the only user of the load */
465 if(get_irn_n_edges(node) > 1)
468 mode = get_irn_mode(node);
469 if(!mode_needs_gp_reg(mode))
471 if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
474 /* don't do AM if other node inputs depend on the load (via mem-proj) */
475 if(other != NULL && get_nodes_block(other) == block
476 && heights_reachable_in_block(heights, other, load))
482 typedef struct ia32_address_mode_t ia32_address_mode_t;
483 struct ia32_address_mode_t {
487 ia32_op_type_t op_type;
494 static void build_address(ia32_address_mode_t *am, ir_node *node)
496 ia32_address_t *addr = &am->addr;
497 ir_node *load = get_Proj_pred(node);
498 ir_node *ptr = get_Load_ptr(load);
499 ir_node *mem = get_Load_mem(load);
500 ir_node *new_mem = be_transform_node(mem);
504 am->ls_mode = get_Load_mode(load);
505 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
507 /* construct load address */
508 ia32_create_address_mode(addr, ptr, 0);
513 base = ia32_new_NoReg_gp(env_cg);
515 base = be_transform_node(base);
519 index = ia32_new_NoReg_gp(env_cg);
521 index = be_transform_node(index);
529 static void set_address(ir_node *node, ia32_address_t *addr)
531 set_ia32_am_scale(node, addr->scale);
532 set_ia32_am_sc(node, addr->symconst_ent);
533 set_ia32_am_offs_int(node, addr->offset);
534 if(addr->symconst_sign)
535 set_ia32_am_sc_sign(node);
537 set_ia32_use_frame(node);
538 set_ia32_frame_ent(node, addr->frame_entity);
541 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
543 set_address(node, &am->addr);
545 set_ia32_op_type(node, am->op_type);
546 set_ia32_ls_mode(node, am->ls_mode);
548 set_ia32_commutative(node);
552 match_commutative = 1 << 0,
553 match_am_and_immediates = 1 << 1,
554 match_no_am = 1 << 2,
555 match_8_16_bit_am = 1 << 3,
556 match_no_immediate = 1 << 4
559 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
560 ir_node *op1, ir_node *op2, match_flags_t flags)
562 ia32_address_t *addr = &am->addr;
563 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
568 int use_am_and_immediates;
571 memset(am, 0, sizeof(am[0]));
573 commutative = (flags & match_commutative) != 0;
574 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
575 use_am = ! (flags & match_no_am);
576 use_immediate = !(flags & match_no_immediate);
579 assert(!commutative || op1 != NULL);
581 if(!(flags & match_8_16_bit_am)
583 && get_mode_size_bits(get_irn_mode(op1)) < 32)
586 new_op2 = (use_immediate ? try_create_Immediate(op2, 0) : NULL);
587 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
588 build_address(am, op2);
589 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
591 am->op_type = ia32_AddrModeS;
592 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
593 use_am && use_source_address_mode(block, op1, op2)) {
594 build_address(am, op1);
595 if(new_op2 != NULL) {
598 new_op1 = be_transform_node(op2);
602 am->op_type = ia32_AddrModeS;
604 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
606 new_op2 = be_transform_node(op2);
607 am->op_type = ia32_Normal;
609 if(addr->base == NULL)
610 addr->base = noreg_gp;
611 if(addr->index == NULL)
612 addr->index = noreg_gp;
613 if(addr->mem == NULL)
614 addr->mem = new_NoMem();
616 am->new_op1 = new_op1;
617 am->new_op2 = new_op2;
618 am->commutative = commutative;
621 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
623 ir_graph *irg = current_ir_graph;
627 if(am->mem_proj == NULL)
630 /* we have to create a mode_T so the old MemProj can attach to us */
631 mode = get_irn_mode(node);
632 load = get_Proj_pred(am->mem_proj);
634 mark_irn_visited(load);
635 be_set_transformed_node(load, node);
638 set_irn_mode(node, mode_T);
639 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
646 * Construct a standard binary operation, set AM and immediate if required.
648 * @param op1 The first operand
649 * @param op2 The second operand
650 * @param func The node constructor function
651 * @return The constructed ia32 node.
653 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
654 construct_binop_func *func, int commutative)
656 ir_node *src_block = get_nodes_block(node);
657 ir_node *block = be_transform_node(src_block);
658 ir_graph *irg = current_ir_graph;
659 dbg_info *dbgi = get_irn_dbg_info(node);
661 ia32_address_mode_t am;
662 ia32_address_t *addr = &am.addr;
663 match_flags_t flags = 0;
666 flags |= match_commutative;
668 match_arguments(&am, src_block, op1, op2, flags);
670 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
671 am.new_op1, am.new_op2);
672 set_am_attributes(new_node, &am);
673 /* we can't use source address mode anymore when using immediates */
674 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
675 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
676 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
678 new_node = fix_mem_proj(new_node, &am);
684 * Construct a standard binary operation, set AM and immediate if required.
686 * @param op1 The first operand
687 * @param op2 The second operand
688 * @param func The node constructor function
689 * @return The constructed ia32 node.
691 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
692 construct_binop_func *func)
694 ir_node *block = be_transform_node(get_nodes_block(node));
695 ir_node *new_op1 = be_transform_node(op1);
696 ir_node *new_op2 = be_transform_node(op2);
697 ir_node *new_node = NULL;
698 dbg_info *dbgi = get_irn_dbg_info(node);
699 ir_graph *irg = current_ir_graph;
700 ir_mode *mode = get_irn_mode(node);
701 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
702 ir_node *nomem = new_NoMem();
704 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1,
706 if (is_op_commutative(get_irn_op(node))) {
707 set_ia32_commutative(new_node);
709 set_ia32_ls_mode(new_node, mode);
711 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
716 static ir_node *get_fpcw(void)
719 if(initial_fpcw != NULL)
722 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
723 &ia32_fp_cw_regs[REG_FPCW]);
724 initial_fpcw = be_transform_node(fpcw);
730 * Construct a standard binary operation, set AM and immediate if required.
732 * @param op1 The first operand
733 * @param op2 The second operand
734 * @param func The node constructor function
735 * @return The constructed ia32 node.
737 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
738 construct_binop_float_func *func)
740 ir_node *block = be_transform_node(get_nodes_block(node));
741 ir_node *new_op1 = be_transform_node(op1);
742 ir_node *new_op2 = be_transform_node(op2);
743 ir_node *new_node = NULL;
744 dbg_info *dbgi = get_irn_dbg_info(node);
745 ir_graph *irg = current_ir_graph;
746 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
747 ir_node *nomem = new_NoMem();
749 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1, new_op2,
751 if (is_op_commutative(get_irn_op(node))) {
752 set_ia32_commutative(new_node);
755 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
761 * Construct a shift/rotate binary operation, sets AM and immediate if required.
763 * @param op1 The first operand
764 * @param op2 The second operand
765 * @param func The node constructor function
766 * @return The constructed ia32 node.
768 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
769 construct_shift_func *func)
771 dbg_info *dbgi = get_irn_dbg_info(node);
772 ir_graph *irg = current_ir_graph;
773 ir_node *block = get_nodes_block(node);
774 ir_node *new_block = be_transform_node(block);
775 ir_node *new_op1 = be_transform_node(op1);
776 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
779 assert(! mode_is_float(get_irn_mode(node))
780 && "Shift/Rotate with float not supported");
782 res = func(dbgi, irg, new_block, new_op1, new_op2);
783 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
785 /* lowered shift instruction may have a dependency operand, handle it here */
786 if (get_irn_arity(node) == 3) {
787 /* we have a dependency */
788 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
789 add_irn_dep(res, new_dep);
797 * Construct a standard unary operation, set AM and immediate if required.
799 * @param op The operand
800 * @param func The node constructor function
801 * @return The constructed ia32 node.
803 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
805 ir_node *block = be_transform_node(get_nodes_block(node));
806 ir_node *new_op = be_transform_node(op);
807 ir_node *new_node = NULL;
808 ir_graph *irg = current_ir_graph;
809 dbg_info *dbgi = get_irn_dbg_info(node);
811 new_node = func(dbgi, irg, block, new_op);
813 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
818 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
819 ia32_address_t *addr)
821 ir_graph *irg = current_ir_graph;
822 ir_node *base = addr->base;
823 ir_node *index = addr->index;
827 base = ia32_new_NoReg_gp(env_cg);
829 base = be_transform_node(base);
833 index = ia32_new_NoReg_gp(env_cg);
835 index = be_transform_node(index);
838 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
839 set_address(res, addr);
844 static int am_has_immediates(const ia32_address_t *addr)
846 return addr->offset != 0 || addr->symconst_ent != NULL
847 || addr->frame_entity || addr->use_frame;
851 * Creates an ia32 Add.
853 * @return the created ia32 Add node
855 static ir_node *gen_Add(ir_node *node) {
856 ir_node *block = be_transform_node(get_nodes_block(node));
857 ir_node *op1 = get_Add_left(node);
858 ir_node *op2 = get_Add_right(node);
861 ir_graph *irg = current_ir_graph;
862 dbg_info *dbgi = get_irn_dbg_info(node);
863 ir_mode *mode = get_irn_mode(node);
864 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
865 ir_node *src_block = get_nodes_block(node);
866 ir_node *add_immediate_op;
868 ia32_address_mode_t am;
870 if (mode_is_float(mode)) {
871 if (USE_SSE2(env_cg))
872 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
874 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
879 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
880 * 1. Add with immediate -> Lea
881 * 2. Add with possible source address mode -> Add
882 * 3. Otherwise -> Lea
884 memset(&addr, 0, sizeof(addr));
885 ia32_create_address_mode(&addr, node, 1);
886 add_immediate_op = NULL;
888 if(addr.base == NULL && addr.index == NULL) {
889 new_op = new_rd_ia32_Const(dbgi, irg, block, addr.symconst_ent,
890 addr.symconst_sign, addr.offset);
891 add_irn_dep(new_op, get_irg_frame(irg));
892 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
895 /* add with immediate? */
896 if(addr.index == NULL) {
897 add_immediate_op = addr.base;
898 } else if(addr.base == NULL && addr.scale == 0) {
899 add_immediate_op = addr.index;
902 if(add_immediate_op != NULL) {
903 if(!am_has_immediates(&addr)) {
905 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
908 return be_transform_node(add_immediate_op);
911 new_op = create_lea_from_address(dbgi, block, &addr);
912 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
916 /* test if we can use source address mode */
917 memset(&am, 0, sizeof(am));
919 if(use_source_address_mode(src_block, op2, op1)) {
920 build_address(&am, op2);
921 new_op1 = be_transform_node(op1);
922 } else if(use_source_address_mode(src_block, op1, op2)) {
923 build_address(&am, op1);
924 new_op1 = be_transform_node(op2);
926 /* construct an Add with source address mode */
927 if(new_op1 != NULL) {
928 ia32_address_t *am_addr = &am.addr;
929 new_op = new_rd_ia32_Add(dbgi, irg, block, am_addr->base, am_addr->index,
930 am_addr->mem, new_op1, noreg);
931 set_address(new_op, am_addr);
932 set_ia32_op_type(new_op, ia32_AddrModeS);
933 set_ia32_ls_mode(new_op, am.ls_mode);
934 set_ia32_commutative(new_op);
935 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
937 new_op = fix_mem_proj(new_op, &am);
942 /* otherwise construct a lea */
943 new_op = create_lea_from_address(dbgi, block, &addr);
944 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
949 * Creates an ia32 Mul.
951 * @return the created ia32 Mul node
953 static ir_node *gen_Mul(ir_node *node) {
954 ir_node *op1 = get_Mul_left(node);
955 ir_node *op2 = get_Mul_right(node);
956 ir_mode *mode = get_irn_mode(node);
958 if (mode_is_float(mode)) {
959 if (USE_SSE2(env_cg))
960 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
962 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
966 for the lower 32bit of the result it doesn't matter whether we use
967 signed or unsigned multiplication so we use IMul as it has fewer
970 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
974 * Creates an ia32 Mulh.
975 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
976 * this result while Mul returns the lower 32 bit.
978 * @return the created ia32 Mulh node
980 static ir_node *gen_Mulh(ir_node *node) {
981 ir_node *block = be_transform_node(get_nodes_block(node));
982 ir_node *op1 = get_irn_n(node, 0);
983 ir_node *new_op1 = be_transform_node(op1);
984 ir_node *op2 = get_irn_n(node, 1);
985 ir_node *new_op2 = be_transform_node(op2);
986 ir_graph *irg = current_ir_graph;
987 dbg_info *dbgi = get_irn_dbg_info(node);
988 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
989 ir_mode *mode = get_irn_mode(node);
990 ir_node *proj_EDX, *res;
992 assert(!mode_is_float(mode) && "Mulh with float not supported");
993 if (mode_is_signed(mode)) {
994 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_NoMem(),
997 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(), new_op1,
1001 set_ia32_commutative(res);
1003 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1011 * Creates an ia32 And.
1013 * @return The created ia32 And node
1015 static ir_node *gen_And(ir_node *node) {
1016 ir_node *op1 = get_And_left(node);
1017 ir_node *op2 = get_And_right(node);
1018 assert(! mode_is_float(get_irn_mode(node)));
1020 /* is it a zero extension? */
1021 if (is_Const(op2)) {
1022 tarval *tv = get_Const_tarval(op2);
1023 long v = get_tarval_long(tv);
1025 if (v == 0xFF || v == 0xFFFF) {
1026 dbg_info *dbgi = get_irn_dbg_info(node);
1027 ir_node *block = get_nodes_block(node);
1034 assert(v == 0xFFFF);
1037 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1043 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
1049 * Creates an ia32 Or.
1051 * @return The created ia32 Or node
1053 static ir_node *gen_Or(ir_node *node) {
1054 ir_node *op1 = get_Or_left(node);
1055 ir_node *op2 = get_Or_right(node);
1057 assert (! mode_is_float(get_irn_mode(node)));
1058 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
1064 * Creates an ia32 Eor.
1066 * @return The created ia32 Eor node
1068 static ir_node *gen_Eor(ir_node *node) {
1069 ir_node *op1 = get_Eor_left(node);
1070 ir_node *op2 = get_Eor_right(node);
1072 assert(! mode_is_float(get_irn_mode(node)));
1073 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
1078 * Creates an ia32 Sub.
1080 * @return The created ia32 Sub node
1082 static ir_node *gen_Sub(ir_node *node) {
1083 ir_node *op1 = get_Sub_left(node);
1084 ir_node *op2 = get_Sub_right(node);
1085 ir_mode *mode = get_irn_mode(node);
1087 if (mode_is_float(mode)) {
1088 if (USE_SSE2(env_cg))
1089 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1091 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1095 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1099 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1105 * Generates an ia32 DivMod with additional infrastructure for the
1106 * register allocator if needed.
1108 * @param dividend -no comment- :)
1109 * @param divisor -no comment- :)
1110 * @param dm_flav flavour_Div/Mod/DivMod
1111 * @return The created ia32 DivMod node
1113 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1114 ir_node *divisor, ia32_op_flavour_t dm_flav)
1116 ir_node *block = be_transform_node(get_nodes_block(node));
1117 ir_node *new_dividend = be_transform_node(dividend);
1118 ir_node *new_divisor = be_transform_node(divisor);
1119 ir_graph *irg = current_ir_graph;
1120 dbg_info *dbgi = get_irn_dbg_info(node);
1121 ir_mode *mode = get_irn_mode(node);
1122 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1123 ir_node *res, *proj_div, *proj_mod;
1124 ir_node *sign_extension;
1125 ir_node *mem, *new_mem;
1128 proj_div = proj_mod = NULL;
1132 mem = get_Div_mem(node);
1133 mode = get_Div_resmode(node);
1134 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1135 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1138 mem = get_Mod_mem(node);
1139 mode = get_Mod_resmode(node);
1140 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1141 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1143 case flavour_DivMod:
1144 mem = get_DivMod_mem(node);
1145 mode = get_DivMod_resmode(node);
1146 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1147 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1148 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1151 panic("invalid divmod flavour!");
1153 new_mem = be_transform_node(mem);
1155 if (mode_is_signed(mode)) {
1156 /* in signed mode, we need to sign extend the dividend */
1157 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1158 add_irn_dep(produceval, get_irg_frame(irg));
1159 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1162 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1163 set_ia32_flags(sign_extension, get_ia32_flags(sign_extension) | arch_irn_flags_modify_flags);
1164 add_irn_dep(sign_extension, get_irg_frame(irg));
1167 if (mode_is_signed(mode)) {
1168 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
1169 new_dividend, sign_extension, new_divisor, dm_flav);
1171 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem, new_dividend,
1172 sign_extension, new_divisor, dm_flav);
1175 set_ia32_exc_label(res, has_exc);
1176 set_irn_pinned(res, get_irn_pinned(node));
1178 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1185 * Wrapper for generate_DivMod. Sets flavour_Mod.
1188 static ir_node *gen_Mod(ir_node *node) {
1189 return generate_DivMod(node, get_Mod_left(node),
1190 get_Mod_right(node), flavour_Mod);
1194 * Wrapper for generate_DivMod. Sets flavour_Div.
1197 static ir_node *gen_Div(ir_node *node) {
1198 return generate_DivMod(node, get_Div_left(node),
1199 get_Div_right(node), flavour_Div);
1203 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1205 static ir_node *gen_DivMod(ir_node *node) {
1206 return generate_DivMod(node, get_DivMod_left(node),
1207 get_DivMod_right(node), flavour_DivMod);
1213 * Creates an ia32 floating Div.
1215 * @return The created ia32 xDiv node
1217 static ir_node *gen_Quot(ir_node *node) {
1218 ir_node *block = be_transform_node(get_nodes_block(node));
1219 ir_node *op1 = get_Quot_left(node);
1220 ir_node *new_op1 = be_transform_node(op1);
1221 ir_node *op2 = get_Quot_right(node);
1222 ir_node *new_op2 = be_transform_node(op2);
1223 ir_graph *irg = current_ir_graph;
1224 dbg_info *dbgi = get_irn_dbg_info(node);
1225 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1226 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1229 if (USE_SSE2(env_cg)) {
1230 ir_mode *mode = get_irn_mode(op1);
1231 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, nomem, new_op1,
1233 set_ia32_ls_mode(new_op, mode);
1235 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, nomem, new_op1,
1236 new_op2, get_fpcw());
1238 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1244 * Creates an ia32 Shl.
1246 * @return The created ia32 Shl node
1248 static ir_node *gen_Shl(ir_node *node) {
1249 ir_node *right = get_Shl_right(node);
1251 /* test whether we can build a lea */
1252 if(is_Const(right)) {
1253 tarval *tv = get_Const_tarval(right);
1254 if(tarval_is_long(tv)) {
1255 long val = get_tarval_long(tv);
1256 if(val >= 0 && val <= 3) {
1257 ir_graph *irg = current_ir_graph;
1258 dbg_info *dbgi = get_irn_dbg_info(node);
1259 ir_node *block = be_transform_node(get_nodes_block(node));
1260 ir_node *base = ia32_new_NoReg_gp(env_cg);
1261 ir_node *index = be_transform_node(get_Shl_left(node));
1262 ir_node *res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1263 set_ia32_am_scale(res, val);
1264 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1270 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1277 * Creates an ia32 Shr.
1279 * @return The created ia32 Shr node
1281 static ir_node *gen_Shr(ir_node *node) {
1282 return gen_shift_binop(node, get_Shr_left(node),
1283 get_Shr_right(node), new_rd_ia32_Shr);
1289 * Creates an ia32 Sar.
1291 * @return The created ia32 Shrs node
1293 static ir_node *gen_Shrs(ir_node *node) {
1294 ir_node *left = get_Shrs_left(node);
1295 ir_node *right = get_Shrs_right(node);
1296 ir_mode *mode = get_irn_mode(node);
1297 if(is_Const(right) && mode == mode_Is) {
1298 tarval *tv = get_Const_tarval(right);
1299 long val = get_tarval_long(tv);
1301 /* this is a sign extension */
1302 ir_graph *irg = current_ir_graph;
1303 dbg_info *dbgi = get_irn_dbg_info(node);
1304 ir_node *block = be_transform_node(get_nodes_block(node));
1306 ir_node *new_op = be_transform_node(op);
1307 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1308 add_irn_dep(pval, get_irg_frame(irg));
1310 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1314 /* 8 or 16 bit sign extension? */
1315 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1316 ir_node *shl_left = get_Shl_left(left);
1317 ir_node *shl_right = get_Shl_right(left);
1318 if(is_Const(shl_right)) {
1319 tarval *tv1 = get_Const_tarval(right);
1320 tarval *tv2 = get_Const_tarval(shl_right);
1321 if(tv1 == tv2 && tarval_is_long(tv1)) {
1322 long val = get_tarval_long(tv1);
1323 if(val == 16 || val == 24) {
1324 dbg_info *dbgi = get_irn_dbg_info(node);
1325 ir_node *block = get_nodes_block(node);
1335 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1344 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1350 * Creates an ia32 RotL.
1352 * @param op1 The first operator
1353 * @param op2 The second operator
1354 * @return The created ia32 RotL node
1356 static ir_node *gen_RotL(ir_node *node,
1357 ir_node *op1, ir_node *op2) {
1358 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1364 * Creates an ia32 RotR.
1365 * NOTE: There is no RotR with immediate because this would always be a RotL
1366 * "imm-mode_size_bits" which can be pre-calculated.
1368 * @param op1 The first operator
1369 * @param op2 The second operator
1370 * @return The created ia32 RotR node
1372 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1374 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1380 * Creates an ia32 RotR or RotL (depending on the found pattern).
1382 * @return The created ia32 RotL or RotR node
1384 static ir_node *gen_Rot(ir_node *node) {
1385 ir_node *rotate = NULL;
1386 ir_node *op1 = get_Rot_left(node);
1387 ir_node *op2 = get_Rot_right(node);
1389 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1390 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1391 that means we can create a RotR instead of an Add and a RotL */
1393 if (get_irn_op(op2) == op_Add) {
1395 ir_node *left = get_Add_left(add);
1396 ir_node *right = get_Add_right(add);
1397 if (is_Const(right)) {
1398 tarval *tv = get_Const_tarval(right);
1399 ir_mode *mode = get_irn_mode(node);
1400 long bits = get_mode_size_bits(mode);
1402 if (get_irn_op(left) == op_Minus &&
1403 tarval_is_long(tv) &&
1404 get_tarval_long(tv) == bits)
1406 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1407 rotate = gen_RotR(node, op1, get_Minus_op(left));
1412 if (rotate == NULL) {
1413 rotate = gen_RotL(node, op1, op2);
1422 * Transforms a Minus node.
1424 * @return The created ia32 Minus node
1426 static ir_node *gen_Minus(ir_node *node)
1428 ir_node *op = get_Minus_op(node);
1429 ir_node *block = be_transform_node(get_nodes_block(node));
1430 ir_graph *irg = current_ir_graph;
1431 dbg_info *dbgi = get_irn_dbg_info(node);
1432 ir_mode *mode = get_irn_mode(node);
1437 if (mode_is_float(mode)) {
1438 ir_node *new_op = be_transform_node(op);
1439 if (USE_SSE2(env_cg)) {
1440 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1441 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1442 ir_node *nomem = new_rd_NoMem(irg);
1444 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1447 size = get_mode_size_bits(mode);
1448 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1450 set_ia32_am_sc(res, ent);
1451 set_ia32_op_type(res, ia32_AddrModeS);
1452 set_ia32_ls_mode(res, mode);
1454 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1457 res = gen_unop(node, op, new_rd_ia32_Neg);
1460 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1465 static ir_node *create_Immediate_from_int(int val)
1467 ir_graph *irg = current_ir_graph;
1468 ir_node *start_block = get_irg_start_block(irg);
1469 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, 0, val);
1470 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
1475 static ir_node *gen_bin_Not(ir_node *node)
1477 ir_graph *irg = current_ir_graph;
1478 dbg_info *dbgi = get_irn_dbg_info(node);
1479 ir_node *block = be_transform_node(get_nodes_block(node));
1480 ir_node *op = get_Not_op(node);
1481 ir_node *new_op = be_transform_node(op);
1482 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1483 ir_node *nomem = new_NoMem();
1484 ir_node *one = create_Immediate_from_int(1);
1486 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, nomem, new_op, one);
1490 * Transforms a Not node.
1492 * @return The created ia32 Not node
1494 static ir_node *gen_Not(ir_node *node) {
1495 ir_node *op = get_Not_op(node);
1496 ir_mode *mode = get_irn_mode(node);
1498 if(mode == mode_b) {
1499 return gen_bin_Not(node);
1502 assert (! mode_is_float(get_irn_mode(node)));
1503 return gen_unop(node, op, new_rd_ia32_Not);
1509 * Transforms an Abs node.
1511 * @return The created ia32 Abs node
1513 static ir_node *gen_Abs(ir_node *node) {
1514 ir_node *block = be_transform_node(get_nodes_block(node));
1515 ir_node *op = get_Abs_op(node);
1516 ir_node *new_op = be_transform_node(op);
1517 ir_graph *irg = current_ir_graph;
1518 dbg_info *dbgi = get_irn_dbg_info(node);
1519 ir_mode *mode = get_irn_mode(node);
1520 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1521 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1522 ir_node *nomem = new_NoMem();
1527 if (mode_is_float(mode)) {
1528 if (USE_SSE2(env_cg)) {
1529 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
1531 size = get_mode_size_bits(mode);
1532 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1534 set_ia32_am_sc(res, ent);
1536 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1538 set_ia32_op_type(res, ia32_AddrModeS);
1539 set_ia32_ls_mode(res, mode);
1542 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1543 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1547 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1548 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1551 add_irn_dep(pval, get_irg_frame(irg));
1552 SET_IA32_ORIG_NODE(sign_extension,
1553 ia32_get_old_node_name(env_cg, node));
1555 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
1557 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1559 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
1561 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1568 * Transforms a Load.
1570 * @return the created ia32 Load node
1572 static ir_node *gen_Load(ir_node *node) {
1573 ir_node *old_block = get_nodes_block(node);
1574 ir_node *block = be_transform_node(old_block);
1575 ir_node *ptr = get_Load_ptr(node);
1576 ir_node *mem = get_Load_mem(node);
1577 ir_node *new_mem = be_transform_node(mem);
1580 ir_graph *irg = current_ir_graph;
1581 dbg_info *dbgi = get_irn_dbg_info(node);
1582 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1583 ir_mode *mode = get_Load_mode(node);
1586 ia32_address_t addr;
1588 /* construct load address */
1589 memset(&addr, 0, sizeof(addr));
1590 ia32_create_address_mode(&addr, ptr, 0);
1597 base = be_transform_node(base);
1603 index = be_transform_node(index);
1606 if (mode_is_float(mode)) {
1607 if (USE_SSE2(env_cg)) {
1608 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1610 res_mode = mode_xmm;
1612 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1614 res_mode = mode_vfp;
1620 /* create a conv node with address mode for smaller modes */
1621 if(get_mode_size_bits(mode) < 32) {
1622 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1623 new_mem, noreg, mode);
1625 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1630 set_irn_pinned(new_op, get_irn_pinned(node));
1631 set_ia32_op_type(new_op, ia32_AddrModeS);
1632 set_ia32_ls_mode(new_op, mode);
1633 set_address(new_op, &addr);
1635 /* make sure we are scheduled behind the initial IncSP/Barrier
1636 * to avoid spills being placed before it
1638 if (block == get_irg_start_block(irg)) {
1639 add_irn_dep(new_op, get_irg_frame(irg));
1642 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1643 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1648 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1649 ir_node *ptr, ir_mode *mode, ir_node *other)
1656 /* we only use address mode if we're the only user of the load */
1657 if(get_irn_n_edges(node) > 1)
1660 load = get_Proj_pred(node);
1663 if(get_nodes_block(load) != block)
1666 /* Store should be attached to the load */
1667 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1669 /* store should have the same pointer as the load */
1670 if(get_Load_ptr(load) != ptr)
1673 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1674 if(other != NULL && get_nodes_block(other) == block
1675 && heights_reachable_in_block(heights, other, load))
1678 assert(get_Load_mode(load) == mode);
1683 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1684 ir_node *mem, ir_node *ptr, ir_mode *mode,
1685 construct_binop_dest_func *func,
1686 construct_binop_dest_func *func8bit,
1689 ir_node *src_block = get_nodes_block(node);
1691 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1692 ir_graph *irg = current_ir_graph;
1696 ia32_address_mode_t am;
1697 ia32_address_t *addr = &am.addr;
1698 memset(&am, 0, sizeof(am));
1700 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1701 build_address(&am, op1);
1702 new_op = create_immediate_or_transform(op2, 0);
1703 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1704 build_address(&am, op2);
1705 new_op = create_immediate_or_transform(op1, 0);
1710 if(addr->base == NULL)
1711 addr->base = noreg_gp;
1712 if(addr->index == NULL)
1713 addr->index = noreg_gp;
1714 if(addr->mem == NULL)
1715 addr->mem = new_NoMem();
1717 dbgi = get_irn_dbg_info(node);
1718 block = be_transform_node(src_block);
1719 if(get_mode_size_bits(mode) == 8) {
1720 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1723 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1726 set_address(new_node, addr);
1727 set_ia32_op_type(new_node, ia32_AddrModeD);
1728 set_ia32_ls_mode(new_node, mode);
1729 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1734 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1735 ir_node *ptr, ir_mode *mode,
1736 construct_unop_dest_func *func)
1738 ir_node *src_block = get_nodes_block(node);
1740 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1741 ir_graph *irg = current_ir_graph;
1744 ia32_address_mode_t am;
1745 ia32_address_t *addr = &am.addr;
1746 memset(&am, 0, sizeof(am));
1748 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1751 build_address(&am, op);
1753 if(addr->base == NULL)
1754 addr->base = noreg_gp;
1755 if(addr->index == NULL)
1756 addr->index = noreg_gp;
1757 if(addr->mem == NULL)
1758 addr->mem = new_NoMem();
1760 dbgi = get_irn_dbg_info(node);
1761 block = be_transform_node(src_block);
1762 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1763 set_address(new_node, addr);
1764 set_ia32_op_type(new_node, ia32_AddrModeD);
1765 set_ia32_ls_mode(new_node, mode);
1766 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1771 static ir_node *try_create_dest_am(ir_node *node) {
1772 ir_node *val = get_Store_value(node);
1773 ir_node *mem = get_Store_mem(node);
1774 ir_node *ptr = get_Store_ptr(node);
1775 ir_mode *mode = get_irn_mode(val);
1780 /* handle only GP modes for now... */
1781 if(!mode_needs_gp_reg(mode))
1784 /* store must be the only user of the val node */
1785 if(get_irn_n_edges(val) > 1)
1788 switch(get_irn_opcode(val)) {
1790 op1 = get_Add_left(val);
1791 op2 = get_Add_right(val);
1792 if(is_Const_1(op2)) {
1793 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1794 new_rd_ia32_IncMem);
1796 } else if(is_Const_Minus_1(op2)) {
1797 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1798 new_rd_ia32_DecMem);
1801 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1802 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, 1);
1805 op1 = get_Sub_left(val);
1806 op2 = get_Sub_right(val);
1808 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
1811 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1812 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, 0);
1815 op1 = get_And_left(val);
1816 op2 = get_And_right(val);
1817 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1818 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, 1);
1821 op1 = get_Or_left(val);
1822 op2 = get_Or_right(val);
1823 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1824 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, 1);
1827 op1 = get_Eor_left(val);
1828 op2 = get_Eor_right(val);
1829 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1830 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, 1);
1833 op1 = get_Shl_left(val);
1834 op2 = get_Shl_right(val);
1835 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1836 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, 0);
1839 op1 = get_Shr_left(val);
1840 op2 = get_Shr_right(val);
1841 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1842 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, 0);
1845 op1 = get_Shrs_left(val);
1846 op2 = get_Shrs_right(val);
1847 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1848 new_rd_ia32_SarMem, new_rd_ia32_SarMem, 0);
1851 op1 = get_Rot_left(val);
1852 op2 = get_Rot_right(val);
1853 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1854 new_rd_ia32_RolMem, new_rd_ia32_RolMem, 0);
1856 /* TODO: match ROR patterns... */
1858 op1 = get_Minus_op(val);
1859 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1862 /* should be lowered already */
1863 assert(mode != mode_b);
1864 op1 = get_Not_op(val);
1865 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1875 * Transforms a Store.
1877 * @return the created ia32 Store node
1879 static ir_node *gen_Store(ir_node *node) {
1880 ir_node *block = be_transform_node(get_nodes_block(node));
1881 ir_node *ptr = get_Store_ptr(node);
1884 ir_node *val = get_Store_value(node);
1886 ir_node *mem = get_Store_mem(node);
1887 ir_node *new_mem = be_transform_node(mem);
1888 ir_graph *irg = current_ir_graph;
1889 dbg_info *dbgi = get_irn_dbg_info(node);
1890 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1891 ir_mode *mode = get_irn_mode(val);
1893 ia32_address_t addr;
1895 /* check for destination address mode */
1896 new_op = try_create_dest_am(node);
1900 /* construct store address */
1901 memset(&addr, 0, sizeof(addr));
1902 ia32_create_address_mode(&addr, ptr, 0);
1909 base = be_transform_node(base);
1915 index = be_transform_node(index);
1918 if (mode_is_float(mode)) {
1919 new_val = be_transform_node(val);
1920 if (USE_SSE2(env_cg)) {
1921 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
1924 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
1928 new_val = create_immediate_or_transform(val, 0);
1932 if (get_mode_size_bits(mode) == 8) {
1933 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
1936 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
1941 set_irn_pinned(new_op, get_irn_pinned(node));
1942 set_ia32_op_type(new_op, ia32_AddrModeD);
1943 set_ia32_ls_mode(new_op, mode);
1945 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1946 set_address(new_op, &addr);
1947 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1952 static ir_node *create_Switch(ir_node *node)
1954 ir_graph *irg = current_ir_graph;
1955 dbg_info *dbgi = get_irn_dbg_info(node);
1956 ir_node *block = be_transform_node(get_nodes_block(node));
1957 ir_node *sel = get_Cond_selector(node);
1958 ir_node *new_sel = be_transform_node(sel);
1960 int switch_min = INT_MAX;
1961 const ir_edge_t *edge;
1963 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1965 /* determine the smallest switch case value */
1966 foreach_out_edge(node, edge) {
1967 ir_node *proj = get_edge_src_irn(edge);
1968 int pn = get_Proj_proj(proj);
1973 if (switch_min != 0) {
1974 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1976 /* if smallest switch case is not 0 we need an additional sub */
1977 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1978 add_ia32_am_offs_int(new_sel, -switch_min);
1979 set_ia32_op_type(new_sel, ia32_AddrModeS);
1981 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1984 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1985 set_ia32_pncode(res, get_Cond_defaultProj(node));
1987 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1992 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
1994 ir_graph *irg = current_ir_graph;
2002 /* we have a Cmp as input */
2004 ir_node *pred = get_Proj_pred(node);
2006 flags = be_transform_node(pred);
2007 *pnc_out = get_Proj_proj(node);
2012 /* a mode_b value, we have to compare it against 0 */
2013 dbgi = get_irn_dbg_info(node);
2014 new_block = be_transform_node(get_nodes_block(node));
2015 new_op = be_transform_node(node);
2016 noreg = ia32_new_NoReg_gp(env_cg);
2017 nomem = new_NoMem();
2018 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
2019 new_op, new_op, 0, 0);
2020 *pnc_out = pn_Cmp_Lg;
2024 static ir_node *gen_Cond(ir_node *node) {
2025 ir_node *block = get_nodes_block(node);
2026 ir_node *new_block = be_transform_node(block);
2027 ir_graph *irg = current_ir_graph;
2028 dbg_info *dbgi = get_irn_dbg_info(node);
2029 ir_node *sel = get_Cond_selector(node);
2030 ir_mode *sel_mode = get_irn_mode(sel);
2032 ir_node *flags = NULL;
2035 if (sel_mode != mode_b) {
2036 return create_Switch(node);
2039 /* we get flags from a cmp */
2040 flags = get_flags_node(sel, &pnc);
2042 res = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2043 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2051 * Transforms a CopyB node.
2053 * @return The transformed node.
2055 static ir_node *gen_CopyB(ir_node *node) {
2056 ir_node *block = be_transform_node(get_nodes_block(node));
2057 ir_node *src = get_CopyB_src(node);
2058 ir_node *new_src = be_transform_node(src);
2059 ir_node *dst = get_CopyB_dst(node);
2060 ir_node *new_dst = be_transform_node(dst);
2061 ir_node *mem = get_CopyB_mem(node);
2062 ir_node *new_mem = be_transform_node(mem);
2063 ir_node *res = NULL;
2064 ir_graph *irg = current_ir_graph;
2065 dbg_info *dbgi = get_irn_dbg_info(node);
2066 int size = get_type_size_bytes(get_CopyB_type(node));
2069 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2070 /* then we need the size explicitly in ECX. */
2071 if (size >= 32 * 4) {
2072 rem = size & 0x3; /* size % 4 */
2075 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2077 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2079 set_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);
2081 add_irn_dep(res, get_irg_frame(irg));
2083 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2084 /* we misuse the pncode field for the copyb size */
2085 set_ia32_pncode(res, rem);
2087 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2088 set_ia32_pncode(res, size);
2091 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2096 static ir_node *gen_be_Copy(ir_node *node)
2098 ir_node *result = be_duplicate_node(node);
2099 ir_mode *mode = get_irn_mode(result);
2101 if (mode_needs_gp_reg(mode)) {
2102 set_irn_mode(result, mode_Iu);
2109 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2110 * to fold an and into a test node
2112 static int can_fold_test_and(ir_node *node)
2114 const ir_edge_t *edge;
2116 /** we can only have eq and lg projs */
2117 foreach_out_edge(node, edge) {
2118 ir_node *proj = get_edge_src_irn(edge);
2119 pn_Cmp pnc = get_Proj_proj(proj);
2120 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2127 static ir_node *try_create_Test(ir_node *node)
2129 ir_graph *irg = current_ir_graph;
2130 dbg_info *dbgi = get_irn_dbg_info(node);
2131 ir_node *block = get_nodes_block(node);
2132 ir_node *new_block = be_transform_node(block);
2133 ir_node *cmp_left = get_Cmp_left(node);
2134 ir_node *cmp_right = get_Cmp_right(node);
2139 ia32_address_mode_t am;
2140 ia32_address_t *addr = &am.addr;
2143 /* can we use a test instruction? */
2144 if(!is_Const_0(cmp_right))
2147 if(is_And(cmp_left) && get_irn_n_edges(cmp_left) == 1 &&
2148 can_fold_test_and(node)) {
2149 ir_node *and_left = get_And_left(cmp_left);
2150 ir_node *and_right = get_And_right(cmp_left);
2152 mode = get_irn_mode(and_left);
2156 mode = get_irn_mode(cmp_left);
2161 assert(get_mode_size_bits(mode) <= 32);
2163 match_arguments(&am, block, left, right, match_commutative |
2164 match_8_16_bit_am | match_am_and_immediates);
2166 cmp_unsigned = !mode_is_signed(mode);
2167 if(get_mode_size_bits(mode) == 8) {
2168 res = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2169 addr->index, addr->mem, am.new_op1,
2170 am.new_op2, am.flipped, cmp_unsigned);
2172 res = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, addr->index,
2173 addr->mem, am.new_op1, am.new_op2, am.flipped,
2176 set_am_attributes(res, &am);
2177 assert(mode != NULL);
2178 set_ia32_ls_mode(res, mode);
2180 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2182 res = fix_mem_proj(res, &am);
2186 static ir_node *create_Fucom(ir_node *node)
2188 ir_graph *irg = current_ir_graph;
2189 dbg_info *dbgi = get_irn_dbg_info(node);
2190 ir_node *block = get_nodes_block(node);
2191 ir_node *new_block = be_transform_node(block);
2192 ir_node *left = get_Cmp_left(node);
2193 ir_node *new_left = be_transform_node(left);
2194 ir_node *right = get_Cmp_right(node);
2195 ir_node *new_right = be_transform_node(right);
2198 res = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left, new_right,
2200 set_ia32_commutative(res);
2202 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2204 res = new_rd_ia32_Sahf(dbgi, irg, new_block, res);
2205 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2210 static ir_node *create_Ucomi(ir_node *node)
2212 ir_graph *irg = current_ir_graph;
2213 dbg_info *dbgi = get_irn_dbg_info(node);
2214 ir_node *block = get_nodes_block(node);
2215 ir_node *new_block = be_transform_node(block);
2216 ir_node *left = get_Cmp_left(node);
2217 ir_node *new_left = be_transform_node(left);
2218 ir_node *right = get_Cmp_right(node);
2219 ir_node *new_right = be_transform_node(right);
2220 ir_mode *mode = get_irn_mode(left);
2221 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2222 ir_node *nomem = new_NoMem();
2225 res = new_rd_ia32_Ucomi(dbgi, irg, new_block, noreg, noreg, nomem, new_left,
2227 set_ia32_commutative(res);
2228 set_ia32_ls_mode(res, mode);
2230 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2235 static ir_node *gen_Cmp(ir_node *node)
2237 ir_graph *irg = current_ir_graph;
2238 dbg_info *dbgi = get_irn_dbg_info(node);
2239 ir_node *block = get_nodes_block(node);
2240 ir_node *new_block = be_transform_node(block);
2241 ir_node *left = get_Cmp_left(node);
2242 ir_node *right = get_Cmp_right(node);
2243 ir_mode *cmp_mode = get_irn_mode(left);
2245 ia32_address_mode_t am;
2246 ia32_address_t *addr = &am.addr;
2249 if(mode_is_float(cmp_mode)) {
2250 if (USE_SSE2(env_cg)) {
2251 return create_Ucomi(node);
2253 return create_Fucom(node);
2257 assert(mode_needs_gp_reg(cmp_mode));
2259 /* we prefer the Test instruction where possible except cases where
2260 * we can use SourceAM */
2261 if(!use_source_address_mode(block, left, right) &&
2262 !use_source_address_mode(block, right, left)) {
2263 res = try_create_Test(node);
2268 match_arguments(&am, block, left, right,
2269 match_commutative | match_8_16_bit_am |
2270 match_am_and_immediates);
2272 cmp_unsigned = !mode_is_signed(get_irn_mode(left));
2273 if(get_mode_size_bits(cmp_mode) == 8) {
2274 res = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, addr->index,
2275 addr->mem, am.new_op1, am.new_op2,
2276 am.flipped, cmp_unsigned);
2278 res = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, addr->index,
2279 addr->mem, am.new_op1, am.new_op2, am.flipped,
2282 set_am_attributes(res, &am);
2283 assert(cmp_mode != NULL);
2284 set_ia32_ls_mode(res, cmp_mode);
2286 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2288 res = fix_mem_proj(res, &am);
2293 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2295 ir_graph *irg = current_ir_graph;
2296 dbg_info *dbgi = get_irn_dbg_info(node);
2297 ir_node *block = get_nodes_block(node);
2298 ir_node *new_block = be_transform_node(block);
2299 ir_node *val_true = get_Psi_val(node, 0);
2300 ir_node *new_val_true = be_transform_node(val_true);
2301 ir_node *val_false = get_Psi_default(node);
2302 ir_node *new_val_false = be_transform_node(val_false);
2303 ir_mode *mode = get_irn_mode(node);
2304 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2305 ir_node *nomem = new_NoMem();
2308 assert(mode_needs_gp_reg(mode));
2310 res = new_rd_ia32_CMov(dbgi, irg, new_block, noreg, noreg, nomem,
2311 new_val_false, new_val_true, new_flags, pnc);
2312 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2319 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2320 ir_node *flags, pn_Cmp pnc, ir_node *orig_node)
2322 ir_graph *irg = current_ir_graph;
2323 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2324 ir_node *nomem = new_NoMem();
2327 res = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc);
2328 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2329 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2330 nomem, res, mode_Bu);
2331 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2337 * Transforms a Psi node into CMov.
2339 * @return The transformed node.
2341 static ir_node *gen_Psi(ir_node *node)
2343 dbg_info *dbgi = get_irn_dbg_info(node);
2344 ir_node *block = get_nodes_block(node);
2345 ir_node *new_block = be_transform_node(block);
2346 ir_node *psi_true = get_Psi_val(node, 0);
2347 ir_node *psi_default = get_Psi_default(node);
2348 ir_node *cond = get_Psi_cond(node, 0);
2349 ir_node *flags = NULL;
2354 assert(get_Psi_n_conds(node) == 1);
2355 assert(get_irn_mode(cond) == mode_b);
2356 assert(mode_needs_gp_reg(get_irn_mode(node)));
2358 flags = get_flags_node(cond, &pnc);
2360 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2361 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2362 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2363 pnc = get_negated_pnc(pnc, cmp_mode);
2364 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2366 res = create_CMov(node, flags, pnc);
2373 * Create a conversion from x87 state register to general purpose.
2375 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2376 ir_node *block = be_transform_node(get_nodes_block(node));
2377 ir_node *op = get_Conv_op(node);
2378 ir_node *new_op = be_transform_node(op);
2379 ia32_code_gen_t *cg = env_cg;
2380 ir_graph *irg = current_ir_graph;
2381 dbg_info *dbgi = get_irn_dbg_info(node);
2382 ir_node *noreg = ia32_new_NoReg_gp(cg);
2383 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2384 ir_mode *mode = get_irn_mode(node);
2385 ir_node *fist, *load;
2388 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2389 new_NoMem(), new_op, trunc_mode);
2391 set_irn_pinned(fist, op_pin_state_floats);
2392 set_ia32_use_frame(fist);
2393 set_ia32_op_type(fist, ia32_AddrModeD);
2395 assert(get_mode_size_bits(mode) <= 32);
2396 /* exception we can only store signed 32 bit integers, so for unsigned
2397 we store a 64bit (signed) integer and load the lower bits */
2398 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2399 set_ia32_ls_mode(fist, mode_Ls);
2401 set_ia32_ls_mode(fist, mode_Is);
2403 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2406 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2408 set_irn_pinned(load, op_pin_state_floats);
2409 set_ia32_use_frame(load);
2410 set_ia32_op_type(load, ia32_AddrModeS);
2411 set_ia32_ls_mode(load, mode_Is);
2412 if(get_ia32_ls_mode(fist) == mode_Ls) {
2413 ia32_attr_t *attr = get_ia32_attr(load);
2414 attr->data.need_64bit_stackent = 1;
2416 ia32_attr_t *attr = get_ia32_attr(load);
2417 attr->data.need_32bit_stackent = 1;
2419 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2421 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2425 * Creates a x87 strict Conv by placing a Sore and a Load
2427 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2429 ir_node *block = get_nodes_block(node);
2430 ir_graph *irg = current_ir_graph;
2431 dbg_info *dbgi = get_irn_dbg_info(node);
2432 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2433 ir_node *nomem = new_NoMem();
2434 ir_node *frame = get_irg_frame(irg);
2435 ir_node *store, *load;
2438 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2440 set_ia32_use_frame(store);
2441 set_ia32_op_type(store, ia32_AddrModeD);
2442 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2444 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2446 set_ia32_use_frame(load);
2447 set_ia32_op_type(load, ia32_AddrModeS);
2448 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2450 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2455 * Create a conversion from general purpose to x87 register
2457 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2458 ir_node *src_block = get_nodes_block(node);
2459 ir_node *block = be_transform_node(src_block);
2460 ir_graph *irg = current_ir_graph;
2461 dbg_info *dbgi = get_irn_dbg_info(node);
2462 ir_node *op = get_Conv_op(node);
2467 ir_mode *store_mode;
2473 /* fild can use source AM if the operand is a signed 32bit integer */
2474 if (src_mode == mode_Is) {
2475 ia32_address_mode_t am;
2477 match_arguments(&am, src_block, NULL, op, match_no_immediate);
2478 if (am.op_type == ia32_AddrModeS) {
2479 ia32_address_t *addr = &am.addr;
2481 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base, addr->index, addr->mem);
2482 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2484 set_am_attributes(fild, &am);
2485 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2487 fix_mem_proj(fild, &am);
2491 new_op = am.new_op2;
2493 new_op = be_transform_node(op);
2496 noreg = ia32_new_NoReg_gp(env_cg);
2497 nomem = new_NoMem();
2498 mode = get_irn_mode(op);
2500 /* first convert to 32 bit signed if necessary */
2501 src_bits = get_mode_size_bits(src_mode);
2502 if (src_bits == 8) {
2503 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2505 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2507 } else if (src_bits < 32) {
2508 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2510 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2514 assert(get_mode_size_bits(mode) == 32);
2517 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2520 set_ia32_use_frame(store);
2521 set_ia32_op_type(store, ia32_AddrModeD);
2522 set_ia32_ls_mode(store, mode_Iu);
2524 /* exception for 32bit unsigned, do a 64bit spill+load */
2525 if(!mode_is_signed(mode)) {
2528 ir_node *zero_const = create_Immediate_from_int(0);
2530 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2531 get_irg_frame(irg), noreg, nomem,
2534 set_ia32_use_frame(zero_store);
2535 set_ia32_op_type(zero_store, ia32_AddrModeD);
2536 add_ia32_am_offs_int(zero_store, 4);
2537 set_ia32_ls_mode(zero_store, mode_Iu);
2542 store = new_rd_Sync(dbgi, irg, block, 2, in);
2543 store_mode = mode_Ls;
2545 store_mode = mode_Is;
2549 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2551 set_ia32_use_frame(fild);
2552 set_ia32_op_type(fild, ia32_AddrModeS);
2553 set_ia32_ls_mode(fild, store_mode);
2555 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2561 * Crete a conversion from one integer mode into another one
2563 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2564 dbg_info *dbgi, ir_node *block, ir_node *op,
2567 ir_graph *irg = current_ir_graph;
2568 int src_bits = get_mode_size_bits(src_mode);
2569 int tgt_bits = get_mode_size_bits(tgt_mode);
2570 ir_node *new_block = be_transform_node(block);
2571 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2574 ir_mode *smaller_mode;
2576 ia32_address_mode_t am;
2577 ia32_address_t *addr = &am.addr;
2579 if (src_bits < tgt_bits) {
2580 smaller_mode = src_mode;
2581 smaller_bits = src_bits;
2583 smaller_mode = tgt_mode;
2584 smaller_bits = tgt_bits;
2587 memset(&am, 0, sizeof(am));
2588 if(use_source_address_mode(block, op, NULL)) {
2589 build_address(&am, op);
2591 am.op_type = ia32_AddrModeS;
2593 new_op = be_transform_node(op);
2594 am.op_type = ia32_Normal;
2596 if(addr->base == NULL)
2598 if(addr->index == NULL)
2599 addr->index = noreg;
2600 if(addr->mem == NULL)
2601 addr->mem = new_NoMem();
2603 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2604 if (smaller_bits == 8) {
2605 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2606 addr->index, addr->mem, new_op,
2609 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2610 addr->index, addr->mem, new_op,
2614 set_am_attributes(res, &am);
2615 set_ia32_ls_mode(res, smaller_mode);
2616 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2617 res = fix_mem_proj(res, &am);
2623 * Transforms a Conv node.
2625 * @return The created ia32 Conv node
2627 static ir_node *gen_Conv(ir_node *node) {
2628 ir_node *block = get_nodes_block(node);
2629 ir_node *new_block = be_transform_node(block);
2630 ir_node *op = get_Conv_op(node);
2631 ir_node *new_op = NULL;
2632 ir_graph *irg = current_ir_graph;
2633 dbg_info *dbgi = get_irn_dbg_info(node);
2634 ir_mode *src_mode = get_irn_mode(op);
2635 ir_mode *tgt_mode = get_irn_mode(node);
2636 int src_bits = get_mode_size_bits(src_mode);
2637 int tgt_bits = get_mode_size_bits(tgt_mode);
2638 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2639 ir_node *nomem = new_rd_NoMem(irg);
2640 ir_node *res = NULL;
2642 if (src_mode == mode_b) {
2643 assert(mode_is_int(tgt_mode));
2644 /* nothing to do, we already model bools as 0/1 ints */
2645 return be_transform_node(op);
2648 if (src_mode == tgt_mode) {
2649 if (get_Conv_strict(node)) {
2650 if (USE_SSE2(env_cg)) {
2651 /* when we are in SSE mode, we can kill all strict no-op conversion */
2652 return be_transform_node(op);
2655 /* this should be optimized already, but who knows... */
2656 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2657 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2658 return be_transform_node(op);
2662 if (mode_is_float(src_mode)) {
2663 new_op = be_transform_node(op);
2664 /* we convert from float ... */
2665 if (mode_is_float(tgt_mode)) {
2666 if(src_mode == mode_E && tgt_mode == mode_D
2667 && !get_Conv_strict(node)) {
2668 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2673 if (USE_SSE2(env_cg)) {
2674 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2675 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2677 set_ia32_ls_mode(res, tgt_mode);
2679 if(get_Conv_strict(node)) {
2680 res = gen_x87_strict_conv(tgt_mode, new_op);
2681 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2684 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2689 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2690 if (USE_SSE2(env_cg)) {
2691 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2693 set_ia32_ls_mode(res, src_mode);
2695 return gen_x87_fp_to_gp(node);
2699 /* we convert from int ... */
2700 if (mode_is_float(tgt_mode)) {
2702 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2703 if (USE_SSE2(env_cg)) {
2704 new_op = be_transform_node(op);
2705 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2707 set_ia32_ls_mode(res, tgt_mode);
2709 res = gen_x87_gp_to_fp(node, src_mode);
2710 if(get_Conv_strict(node)) {
2711 res = gen_x87_strict_conv(tgt_mode, res);
2712 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2713 ia32_get_old_node_name(env_cg, node));
2717 } else if(tgt_mode == mode_b) {
2718 /* mode_b lowering already took care that we only have 0/1 values */
2719 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2720 src_mode, tgt_mode));
2721 return be_transform_node(op);
2724 if (src_bits == tgt_bits) {
2725 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2726 src_mode, tgt_mode));
2727 return be_transform_node(op);
2730 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2738 static int check_immediate_constraint(long val, char immediate_constraint_type)
2740 switch (immediate_constraint_type) {
2744 return val >= 0 && val <= 32;
2746 return val >= 0 && val <= 63;
2748 return val >= -128 && val <= 127;
2750 return val == 0xff || val == 0xffff;
2752 return val >= 0 && val <= 3;
2754 return val >= 0 && val <= 255;
2756 return val >= 0 && val <= 127;
2760 panic("Invalid immediate constraint found");
2764 static ir_node *try_create_Immediate(ir_node *node,
2765 char immediate_constraint_type)
2768 tarval *offset = NULL;
2769 int offset_sign = 0;
2771 ir_entity *symconst_ent = NULL;
2772 int symconst_sign = 0;
2774 ir_node *cnst = NULL;
2775 ir_node *symconst = NULL;
2781 mode = get_irn_mode(node);
2782 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2786 if(is_Minus(node)) {
2788 node = get_Minus_op(node);
2791 if(is_Const(node)) {
2794 offset_sign = minus;
2795 } else if(is_SymConst(node)) {
2798 symconst_sign = minus;
2799 } else if(is_Add(node)) {
2800 ir_node *left = get_Add_left(node);
2801 ir_node *right = get_Add_right(node);
2802 if(is_Const(left) && is_SymConst(right)) {
2805 symconst_sign = minus;
2806 offset_sign = minus;
2807 } else if(is_SymConst(left) && is_Const(right)) {
2810 symconst_sign = minus;
2811 offset_sign = minus;
2813 } else if(is_Sub(node)) {
2814 ir_node *left = get_Sub_left(node);
2815 ir_node *right = get_Sub_right(node);
2816 if(is_Const(left) && is_SymConst(right)) {
2819 symconst_sign = !minus;
2820 offset_sign = minus;
2821 } else if(is_SymConst(left) && is_Const(right)) {
2824 symconst_sign = minus;
2825 offset_sign = !minus;
2832 offset = get_Const_tarval(cnst);
2833 if(tarval_is_long(offset)) {
2834 val = get_tarval_long(offset);
2836 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2841 if(!check_immediate_constraint(val, immediate_constraint_type))
2844 if(symconst != NULL) {
2845 if(immediate_constraint_type != 0) {
2846 /* we need full 32bits for symconsts */
2850 /* unfortunately the assembler/linker doesn't support -symconst */
2854 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2856 symconst_ent = get_SymConst_entity(symconst);
2858 if(cnst == NULL && symconst == NULL)
2861 if(offset_sign && offset != NULL) {
2862 offset = tarval_neg(offset);
2865 irg = current_ir_graph;
2866 dbgi = get_irn_dbg_info(node);
2867 block = get_irg_start_block(irg);
2868 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2869 symconst_sign, val);
2870 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2875 static ir_node *create_immediate_or_transform(ir_node *node,
2876 char immediate_constraint_type)
2878 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2879 if (new_node == NULL) {
2880 new_node = be_transform_node(node);
2885 typedef struct constraint_t constraint_t;
2886 struct constraint_t {
2889 const arch_register_req_t **out_reqs;
2891 const arch_register_req_t *req;
2892 unsigned immediate_possible;
2893 char immediate_type;
2896 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2898 int immediate_possible = 0;
2899 char immediate_type = 0;
2900 unsigned limited = 0;
2901 const arch_register_class_t *cls = NULL;
2902 ir_graph *irg = current_ir_graph;
2903 struct obstack *obst = get_irg_obstack(irg);
2904 arch_register_req_t *req;
2905 unsigned *limited_ptr;
2909 /* TODO: replace all the asserts with nice error messages */
2911 printf("Constraint: %s\n", c);
2921 assert(cls == NULL ||
2922 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2923 cls = &ia32_reg_classes[CLASS_ia32_gp];
2924 limited |= 1 << REG_EAX;
2927 assert(cls == NULL ||
2928 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2929 cls = &ia32_reg_classes[CLASS_ia32_gp];
2930 limited |= 1 << REG_EBX;
2933 assert(cls == NULL ||
2934 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2935 cls = &ia32_reg_classes[CLASS_ia32_gp];
2936 limited |= 1 << REG_ECX;
2939 assert(cls == NULL ||
2940 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2941 cls = &ia32_reg_classes[CLASS_ia32_gp];
2942 limited |= 1 << REG_EDX;
2945 assert(cls == NULL ||
2946 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2947 cls = &ia32_reg_classes[CLASS_ia32_gp];
2948 limited |= 1 << REG_EDI;
2951 assert(cls == NULL ||
2952 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2953 cls = &ia32_reg_classes[CLASS_ia32_gp];
2954 limited |= 1 << REG_ESI;
2957 case 'q': /* q means lower part of the regs only, this makes no
2958 * difference to Q for us (we only assigne whole registers) */
2959 assert(cls == NULL ||
2960 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2961 cls = &ia32_reg_classes[CLASS_ia32_gp];
2962 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2966 assert(cls == NULL ||
2967 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2968 cls = &ia32_reg_classes[CLASS_ia32_gp];
2969 limited |= 1 << REG_EAX | 1 << REG_EDX;
2972 assert(cls == NULL ||
2973 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2974 cls = &ia32_reg_classes[CLASS_ia32_gp];
2975 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2976 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2983 assert(cls == NULL);
2984 cls = &ia32_reg_classes[CLASS_ia32_gp];
2990 /* TODO: mark values so the x87 simulator knows about t and u */
2991 assert(cls == NULL);
2992 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2997 assert(cls == NULL);
2998 /* TODO: check that sse2 is supported */
2999 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3009 assert(!immediate_possible);
3010 immediate_possible = 1;
3011 immediate_type = *c;
3015 assert(!immediate_possible);
3016 immediate_possible = 1;
3020 assert(!immediate_possible && cls == NULL);
3021 immediate_possible = 1;
3022 cls = &ia32_reg_classes[CLASS_ia32_gp];
3035 assert(constraint->is_in && "can only specify same constraint "
3038 sscanf(c, "%d%n", &same_as, &p);
3045 case 'E': /* no float consts yet */
3046 case 'F': /* no float consts yet */
3047 case 's': /* makes no sense on x86 */
3048 case 'X': /* we can't support that in firm */
3052 case '<': /* no autodecrement on x86 */
3053 case '>': /* no autoincrement on x86 */
3054 case 'C': /* sse constant not supported yet */
3055 case 'G': /* 80387 constant not supported yet */
3056 case 'y': /* we don't support mmx registers yet */
3057 case 'Z': /* not available in 32 bit mode */
3058 case 'e': /* not available in 32 bit mode */
3059 panic("unsupported asm constraint '%c' found in (%+F)",
3060 *c, current_ir_graph);
3063 panic("unknown asm constraint '%c' found in (%+F)", *c,
3071 const arch_register_req_t *other_constr;
3073 assert(cls == NULL && "same as and register constraint not supported");
3074 assert(!immediate_possible && "same as and immediate constraint not "
3076 assert(same_as < constraint->n_outs && "wrong constraint number in "
3077 "same_as constraint");
3079 other_constr = constraint->out_reqs[same_as];
3081 req = obstack_alloc(obst, sizeof(req[0]));
3082 req->cls = other_constr->cls;
3083 req->type = arch_register_req_type_should_be_same;
3084 req->limited = NULL;
3085 req->other_same[0] = pos;
3086 req->other_same[1] = -1;
3087 req->other_different = -1;
3089 /* switch constraints. This is because in firm we have same_as
3090 * constraints on the output constraints while in the gcc asm syntax
3091 * they are specified on the input constraints */
3092 constraint->req = other_constr;
3093 constraint->out_reqs[same_as] = req;
3094 constraint->immediate_possible = 0;
3098 if(immediate_possible && cls == NULL) {
3099 cls = &ia32_reg_classes[CLASS_ia32_gp];
3101 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3102 assert(cls != NULL);
3104 if(immediate_possible) {
3105 assert(constraint->is_in
3106 && "imeediates make no sense for output constraints");
3108 /* todo: check types (no float input on 'r' constrained in and such... */
3111 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3112 limited_ptr = (unsigned*) (req+1);
3114 req = obstack_alloc(obst, sizeof(req[0]));
3116 memset(req, 0, sizeof(req[0]));
3119 req->type = arch_register_req_type_limited;
3120 *limited_ptr = limited;
3121 req->limited = limited_ptr;
3123 req->type = arch_register_req_type_normal;
3127 constraint->req = req;
3128 constraint->immediate_possible = immediate_possible;
3129 constraint->immediate_type = immediate_type;
3132 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3139 panic("Clobbers not supported yet");
3143 * generates code for a ASM node
3145 static ir_node *gen_ASM(ir_node *node)
3148 ir_graph *irg = current_ir_graph;
3149 ir_node *block = be_transform_node(get_nodes_block(node));
3150 dbg_info *dbgi = get_irn_dbg_info(node);
3157 ia32_asm_attr_t *attr;
3158 const arch_register_req_t **out_reqs;
3159 const arch_register_req_t **in_reqs;
3160 struct obstack *obst;
3161 constraint_t parsed_constraint;
3163 /* transform inputs */
3164 arity = get_irn_arity(node);
3165 in = alloca(arity * sizeof(in[0]));
3166 memset(in, 0, arity * sizeof(in[0]));
3168 n_outs = get_ASM_n_output_constraints(node);
3169 n_clobbers = get_ASM_n_clobbers(node);
3170 out_arity = n_outs + n_clobbers;
3172 /* construct register constraints */
3173 obst = get_irg_obstack(irg);
3174 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
3175 parsed_constraint.out_reqs = out_reqs;
3176 parsed_constraint.n_outs = n_outs;
3177 parsed_constraint.is_in = 0;
3178 for(i = 0; i < out_arity; ++i) {
3182 const ir_asm_constraint *constraint;
3183 constraint = & get_ASM_output_constraints(node) [i];
3184 c = get_id_str(constraint->constraint);
3185 parse_asm_constraint(i, &parsed_constraint, c);
3187 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
3188 c = get_id_str(glob_id);
3189 parse_clobber(node, i, &parsed_constraint, c);
3191 out_reqs[i] = parsed_constraint.req;
3194 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
3195 parsed_constraint.is_in = 1;
3196 for(i = 0; i < arity; ++i) {
3197 const ir_asm_constraint *constraint;
3201 constraint = & get_ASM_input_constraints(node) [i];
3202 constr_id = constraint->constraint;
3203 c = get_id_str(constr_id);
3204 parse_asm_constraint(i, &parsed_constraint, c);
3205 in_reqs[i] = parsed_constraint.req;
3207 if(parsed_constraint.immediate_possible) {
3208 ir_node *pred = get_irn_n(node, i);
3209 char imm_type = parsed_constraint.immediate_type;
3210 ir_node *immediate = try_create_Immediate(pred, imm_type);
3212 if(immediate != NULL) {
3218 /* transform inputs */
3219 for(i = 0; i < arity; ++i) {
3221 ir_node *transformed;
3226 pred = get_irn_n(node, i);
3227 transformed = be_transform_node(pred);
3228 in[i] = transformed;
3231 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
3233 generic_attr = get_irn_generic_attr(res);
3234 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
3235 attr->asm_text = get_ASM_text(node);
3236 set_ia32_out_req_all(res, out_reqs);
3237 set_ia32_in_req_all(res, in_reqs);
3239 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3244 /********************************************
3247 * | |__ ___ _ __ ___ __| | ___ ___
3248 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3249 * | |_) | __/ | | | (_) | (_| | __/\__ \
3250 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3252 ********************************************/
3255 * Transforms a FrameAddr into an ia32 Add.
3257 static ir_node *gen_be_FrameAddr(ir_node *node) {
3258 ir_node *block = be_transform_node(get_nodes_block(node));
3259 ir_node *op = be_get_FrameAddr_frame(node);
3260 ir_node *new_op = be_transform_node(op);
3261 ir_graph *irg = current_ir_graph;
3262 dbg_info *dbgi = get_irn_dbg_info(node);
3263 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3266 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3267 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3268 set_ia32_use_frame(res);
3270 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3276 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3278 static ir_node *gen_be_Return(ir_node *node) {
3279 ir_graph *irg = current_ir_graph;
3280 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3281 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3282 ir_entity *ent = get_irg_entity(irg);
3283 ir_type *tp = get_entity_type(ent);
3288 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3289 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3292 int pn_ret_val, pn_ret_mem, arity, i;
3294 assert(ret_val != NULL);
3295 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3296 return be_duplicate_node(node);
3299 res_type = get_method_res_type(tp, 0);
3301 if (! is_Primitive_type(res_type)) {
3302 return be_duplicate_node(node);
3305 mode = get_type_mode(res_type);
3306 if (! mode_is_float(mode)) {
3307 return be_duplicate_node(node);
3310 assert(get_method_n_ress(tp) == 1);
3312 pn_ret_val = get_Proj_proj(ret_val);
3313 pn_ret_mem = get_Proj_proj(ret_mem);
3315 /* get the Barrier */
3316 barrier = get_Proj_pred(ret_val);
3318 /* get result input of the Barrier */
3319 ret_val = get_irn_n(barrier, pn_ret_val);
3320 new_ret_val = be_transform_node(ret_val);
3322 /* get memory input of the Barrier */
3323 ret_mem = get_irn_n(barrier, pn_ret_mem);
3324 new_ret_mem = be_transform_node(ret_mem);
3326 frame = get_irg_frame(irg);
3328 dbgi = get_irn_dbg_info(barrier);
3329 block = be_transform_node(get_nodes_block(barrier));
3331 noreg = ia32_new_NoReg_gp(env_cg);
3333 /* store xmm0 onto stack */
3334 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3335 new_ret_mem, new_ret_val);
3336 set_ia32_ls_mode(sse_store, mode);
3337 set_ia32_op_type(sse_store, ia32_AddrModeD);
3338 set_ia32_use_frame(sse_store);
3340 /* load into x87 register */
3341 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3342 set_ia32_op_type(fld, ia32_AddrModeS);
3343 set_ia32_use_frame(fld);
3345 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3346 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3348 /* create a new barrier */
3349 arity = get_irn_arity(barrier);
3350 in = alloca(arity * sizeof(in[0]));
3351 for (i = 0; i < arity; ++i) {
3354 if (i == pn_ret_val) {
3356 } else if (i == pn_ret_mem) {
3359 ir_node *in = get_irn_n(barrier, i);
3360 new_in = be_transform_node(in);
3365 new_barrier = new_ir_node(dbgi, irg, block,
3366 get_irn_op(barrier), get_irn_mode(barrier),
3368 copy_node_attr(barrier, new_barrier);
3369 be_duplicate_deps(barrier, new_barrier);
3370 be_set_transformed_node(barrier, new_barrier);
3371 mark_irn_visited(barrier);
3373 /* transform normally */
3374 return be_duplicate_node(node);
3378 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3380 static ir_node *gen_be_AddSP(ir_node *node) {
3381 ir_node *block = be_transform_node(get_nodes_block(node));
3382 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3384 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3385 ir_node *new_sp = be_transform_node(sp);
3386 ir_graph *irg = current_ir_graph;
3387 dbg_info *dbgi = get_irn_dbg_info(node);
3388 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3389 ir_node *nomem = new_NoMem();
3392 new_sz = create_immediate_or_transform(sz, 0);
3394 /* ia32 stack grows in reverse direction, make a SubSP */
3395 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
3397 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3403 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3405 static ir_node *gen_be_SubSP(ir_node *node) {
3406 ir_node *block = be_transform_node(get_nodes_block(node));
3407 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3409 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3410 ir_node *new_sp = be_transform_node(sp);
3411 ir_graph *irg = current_ir_graph;
3412 dbg_info *dbgi = get_irn_dbg_info(node);
3413 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3414 ir_node *nomem = new_NoMem();
3417 new_sz = create_immediate_or_transform(sz, 0);
3419 /* ia32 stack grows in reverse direction, make an AddSP */
3420 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
3422 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3428 * This function just sets the register for the Unknown node
3429 * as this is not done during register allocation because Unknown
3430 * is an "ignore" node.
3432 static ir_node *gen_Unknown(ir_node *node) {
3433 ir_mode *mode = get_irn_mode(node);
3435 if (mode_is_float(mode)) {
3436 if (USE_SSE2(env_cg)) {
3437 return ia32_new_Unknown_xmm(env_cg);
3439 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3440 ir_graph *irg = current_ir_graph;
3441 dbg_info *dbgi = get_irn_dbg_info(node);
3442 ir_node *block = get_irg_start_block(irg);
3443 return new_rd_ia32_vfldz(dbgi, irg, block);
3445 } else if (mode_needs_gp_reg(mode)) {
3446 return ia32_new_Unknown_gp(env_cg);
3448 assert(0 && "unsupported Unknown-Mode");
3455 * Change some phi modes
3457 static ir_node *gen_Phi(ir_node *node) {
3458 ir_node *block = be_transform_node(get_nodes_block(node));
3459 ir_graph *irg = current_ir_graph;
3460 dbg_info *dbgi = get_irn_dbg_info(node);
3461 ir_mode *mode = get_irn_mode(node);
3464 if(mode_needs_gp_reg(mode)) {
3465 /* we shouldn't have any 64bit stuff around anymore */
3466 assert(get_mode_size_bits(mode) <= 32);
3467 /* all integer operations are on 32bit registers now */
3469 } else if(mode_is_float(mode)) {
3470 if (USE_SSE2(env_cg)) {
3477 /* phi nodes allow loops, so we use the old arguments for now
3478 * and fix this later */
3479 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3480 get_irn_in(node) + 1);
3481 copy_node_attr(node, phi);
3482 be_duplicate_deps(node, phi);
3484 be_set_transformed_node(node, phi);
3485 be_enqueue_preds(node);
3493 static ir_node *gen_IJmp(ir_node *node) {
3494 /* TODO: support AM */
3495 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3499 /**********************************************************************
3502 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3503 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3504 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3505 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3507 **********************************************************************/
3509 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3511 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3514 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3515 ir_node *val, ir_node *mem);
3518 * Transforms a lowered Load into a "real" one.
3520 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3522 ir_node *block = be_transform_node(get_nodes_block(node));
3523 ir_node *ptr = get_irn_n(node, 0);
3524 ir_node *new_ptr = be_transform_node(ptr);
3525 ir_node *mem = get_irn_n(node, 1);
3526 ir_node *new_mem = be_transform_node(mem);
3527 ir_graph *irg = current_ir_graph;
3528 dbg_info *dbgi = get_irn_dbg_info(node);
3529 ir_mode *mode = get_ia32_ls_mode(node);
3530 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3533 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3535 set_ia32_op_type(new_op, ia32_AddrModeS);
3536 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3537 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3538 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3539 if (is_ia32_am_sc_sign(node))
3540 set_ia32_am_sc_sign(new_op);
3541 set_ia32_ls_mode(new_op, mode);
3542 if (is_ia32_use_frame(node)) {
3543 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3544 set_ia32_use_frame(new_op);
3547 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3553 * Transforms a lowered Store into a "real" one.
3555 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3557 ir_node *block = be_transform_node(get_nodes_block(node));
3558 ir_node *ptr = get_irn_n(node, 0);
3559 ir_node *new_ptr = be_transform_node(ptr);
3560 ir_node *val = get_irn_n(node, 1);
3561 ir_node *new_val = be_transform_node(val);
3562 ir_node *mem = get_irn_n(node, 2);
3563 ir_node *new_mem = be_transform_node(mem);
3564 ir_graph *irg = current_ir_graph;
3565 dbg_info *dbgi = get_irn_dbg_info(node);
3566 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3567 ir_mode *mode = get_ia32_ls_mode(node);
3571 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3573 am_offs = get_ia32_am_offs_int(node);
3574 add_ia32_am_offs_int(new_op, am_offs);
3576 set_ia32_op_type(new_op, ia32_AddrModeD);
3577 set_ia32_ls_mode(new_op, mode);
3578 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3579 set_ia32_use_frame(new_op);
3581 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3588 * Transforms an ia32_l_XXX into a "real" XXX node
3590 * @param node The node to transform
3591 * @return the created ia32 XXX node
3593 #define GEN_LOWERED_OP(op) \
3594 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3595 return gen_binop(node, get_binop_left(node), \
3596 get_binop_right(node), new_rd_ia32_##op,0); \
3599 #define GEN_LOWERED_x87_OP(op) \
3600 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3602 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3603 get_binop_right(node), new_rd_ia32_##op); \
3607 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3608 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3609 return gen_shift_binop(node, get_irn_n(node, 0), \
3610 get_irn_n(node, 1), new_rd_ia32_##op); \
3613 GEN_LOWERED_x87_OP(vfprem)
3614 GEN_LOWERED_x87_OP(vfmul)
3615 GEN_LOWERED_x87_OP(vfsub)
3616 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3617 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3618 GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
3619 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3621 static ir_node *gen_ia32_l_Add(ir_node *node) {
3622 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3623 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3624 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, 1);
3626 if(is_Proj(lowered)) {
3627 lowered = get_Proj_pred(lowered);
3629 assert(is_ia32_Add(lowered));
3630 set_irn_mode(lowered, mode_T);
3636 static ir_node *gen_ia32_l_Adc(ir_node *node) {
3637 ir_node *src_block = get_nodes_block(node);
3638 ir_node *block = be_transform_node(src_block);
3639 ir_node *op1 = get_irn_n(node, n_ia32_l_Adc_left);
3640 ir_node *op2 = get_irn_n(node, n_ia32_l_Adc_right);
3641 ir_node *flags = get_irn_n(node, n_ia32_l_Adc_eflags);
3642 ir_node *new_flags = be_transform_node(flags);
3643 ir_graph *irg = current_ir_graph;
3644 dbg_info *dbgi = get_irn_dbg_info(node);
3646 ia32_address_mode_t am;
3647 ia32_address_t *addr = &am.addr;
3649 match_arguments(&am, src_block, op1, op2, match_commutative);
3651 new_node = new_rd_ia32_Adc(dbgi, irg, block, addr->base, addr->index,
3652 addr->mem, am.new_op1, am.new_op2, new_flags);
3653 set_am_attributes(new_node, &am);
3654 /* we can't use source address mode anymore when using immediates */
3655 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3656 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3657 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3659 new_node = fix_mem_proj(new_node, &am);
3665 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3667 * @param node The node to transform
3668 * @return the created ia32 Neg node
3670 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3671 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3675 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3677 * @param node The node to transform
3678 * @return the created ia32 vfild node
3680 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3681 return gen_lowered_Load(node, new_rd_ia32_vfild);
3685 * Transforms an ia32_l_Load into a "real" ia32_Load node
3687 * @param node The node to transform
3688 * @return the created ia32 Load node
3690 static ir_node *gen_ia32_l_Load(ir_node *node) {
3691 return gen_lowered_Load(node, new_rd_ia32_Load);
3695 * Transforms an ia32_l_Store into a "real" ia32_Store node
3697 * @param node The node to transform
3698 * @return the created ia32 Store node
3700 static ir_node *gen_ia32_l_Store(ir_node *node) {
3701 return gen_lowered_Store(node, new_rd_ia32_Store);
3705 * Transforms a l_vfist into a "real" vfist node.
3707 * @param node The node to transform
3708 * @return the created ia32 vfist node
3710 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3711 ir_node *block = be_transform_node(get_nodes_block(node));
3712 ir_node *ptr = get_irn_n(node, 0);
3713 ir_node *new_ptr = be_transform_node(ptr);
3714 ir_node *val = get_irn_n(node, 1);
3715 ir_node *new_val = be_transform_node(val);
3716 ir_node *mem = get_irn_n(node, 2);
3717 ir_node *new_mem = be_transform_node(mem);
3718 ir_graph *irg = current_ir_graph;
3719 dbg_info *dbgi = get_irn_dbg_info(node);
3720 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3721 ir_mode *mode = get_ia32_ls_mode(node);
3722 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3726 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3727 new_val, trunc_mode);
3729 am_offs = get_ia32_am_offs_int(node);
3730 add_ia32_am_offs_int(new_op, am_offs);
3732 set_ia32_op_type(new_op, ia32_AddrModeD);
3733 set_ia32_ls_mode(new_op, mode);
3734 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3735 set_ia32_use_frame(new_op);
3737 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3743 * Transforms a l_vfdiv into a "real" vfdiv node.
3745 * @param env The transformation environment
3746 * @return the created ia32 vfdiv node
3748 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3749 ir_node *block = be_transform_node(get_nodes_block(node));
3750 ir_node *left = get_binop_left(node);
3751 ir_node *new_left = be_transform_node(left);
3752 ir_node *right = get_binop_right(node);
3753 ir_node *new_right = be_transform_node(right);
3754 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3755 ir_graph *irg = current_ir_graph;
3756 dbg_info *dbgi = get_irn_dbg_info(node);
3757 ir_node *fpcw = get_fpcw();
3760 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_NoMem(),
3761 new_left, new_right, fpcw);
3762 clear_ia32_commutative(vfdiv);
3764 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3770 * Transforms a l_MulS into a "real" MulS node.
3772 * @param env The transformation environment
3773 * @return the created ia32 Mul node
3775 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3776 ir_node *block = be_transform_node(get_nodes_block(node));
3777 ir_node *left = get_binop_left(node);
3778 ir_node *new_left = be_transform_node(left);
3779 ir_node *right = get_binop_right(node);
3780 ir_node *new_right = be_transform_node(right);
3781 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3782 ir_graph *irg = current_ir_graph;
3783 dbg_info *dbgi = get_irn_dbg_info(node);
3785 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3786 /* and then skip the result Proj, because all needed Projs are already there. */
3787 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(),
3788 new_left, new_right);
3789 clear_ia32_commutative(muls);
3791 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3797 * Transforms a l_IMulS into a "real" IMul1OPS node.
3799 * @param env The transformation environment
3800 * @return the created ia32 IMul1OP node
3802 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3803 ir_node *block = be_transform_node(get_nodes_block(node));
3804 ir_node *left = get_binop_left(node);
3805 ir_node *new_left = be_transform_node(left);
3806 ir_node *right = get_binop_right(node);
3807 ir_node *new_right = be_transform_node(right);
3808 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3809 ir_graph *irg = current_ir_graph;
3810 dbg_info *dbgi = get_irn_dbg_info(node);
3812 /* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */
3813 /* and then skip the result Proj, because all needed Projs are already there. */
3814 ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg,
3815 new_NoMem(), new_left, new_right);
3816 clear_ia32_commutative(muls);
3818 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3823 static ir_node *gen_ia32_l_Sub(ir_node *node) {
3824 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
3825 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
3826 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, 0);
3828 if(is_Proj(lowered)) {
3829 lowered = get_Proj_pred(lowered);
3831 assert(is_ia32_Sub(lowered));
3832 set_irn_mode(lowered, mode_T);
3838 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
3839 ir_node *src_block = get_nodes_block(node);
3840 ir_node *block = be_transform_node(src_block);
3841 ir_node *op1 = get_irn_n(node, n_ia32_l_Sbb_left);
3842 ir_node *op2 = get_irn_n(node, n_ia32_l_Sbb_right);
3843 ir_node *flags = get_irn_n(node, n_ia32_l_Sbb_eflags);
3844 ir_node *new_flags = be_transform_node(flags);
3845 ir_graph *irg = current_ir_graph;
3846 dbg_info *dbgi = get_irn_dbg_info(node);
3848 ia32_address_mode_t am;
3849 ia32_address_t *addr = &am.addr;
3851 match_arguments(&am, src_block, op1, op2, match_commutative);
3853 new_node = new_rd_ia32_Sbb(dbgi, irg, block, addr->base, addr->index,
3854 addr->mem, am.new_op1, am.new_op2, new_flags);
3855 set_am_attributes(new_node, &am);
3856 /* we can't use source address mode anymore when using immediates */
3857 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3858 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3859 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3861 new_node = fix_mem_proj(new_node, &am);
3867 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3868 * op1 - target to be shifted
3869 * op2 - contains bits to be shifted into target
3871 * Only op3 can be an immediate.
3873 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3874 ir_node *op2, ir_node *count)
3876 ir_node *block = be_transform_node(get_nodes_block(node));
3877 ir_node *new_op = NULL;
3878 ir_graph *irg = current_ir_graph;
3879 dbg_info *dbgi = get_irn_dbg_info(node);
3880 ir_node *new_op1 = be_transform_node(op1);
3881 ir_node *new_op2 = be_transform_node(op2);
3882 ir_node *new_count = create_immediate_or_transform(count, 'I');
3884 /* TODO proper AM support */
3886 if (is_ia32_l_ShlD(node))
3887 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3889 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3891 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3896 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3897 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3898 get_irn_n(node, 1), get_irn_n(node, 2));
3901 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3902 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3903 get_irn_n(node, 1), get_irn_n(node, 2));
3907 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3909 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3910 ir_node *block = be_transform_node(get_nodes_block(node));
3911 ir_node *val = get_irn_n(node, 1);
3912 ir_node *new_val = be_transform_node(val);
3913 ia32_code_gen_t *cg = env_cg;
3914 ir_node *res = NULL;
3915 ir_graph *irg = current_ir_graph;
3917 ir_node *noreg, *new_ptr, *new_mem;
3924 mem = get_irn_n(node, 2);
3925 new_mem = be_transform_node(mem);
3926 ptr = get_irn_n(node, 0);
3927 new_ptr = be_transform_node(ptr);
3928 noreg = ia32_new_NoReg_gp(cg);
3929 dbgi = get_irn_dbg_info(node);
3931 /* Store x87 -> MEM */
3932 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
3933 get_ia32_ls_mode(node));
3934 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3935 set_ia32_use_frame(res);
3936 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3937 set_ia32_op_type(res, ia32_AddrModeD);
3939 /* Load MEM -> SSE */
3940 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
3941 get_ia32_ls_mode(node));
3942 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3943 set_ia32_use_frame(res);
3944 set_ia32_op_type(res, ia32_AddrModeS);
3945 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3951 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3953 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3954 ir_node *block = be_transform_node(get_nodes_block(node));
3955 ir_node *val = get_irn_n(node, 1);
3956 ir_node *new_val = be_transform_node(val);
3957 ia32_code_gen_t *cg = env_cg;
3958 ir_graph *irg = current_ir_graph;
3959 ir_node *res = NULL;
3960 ir_entity *fent = get_ia32_frame_ent(node);
3961 ir_mode *lsmode = get_ia32_ls_mode(node);
3963 ir_node *noreg, *new_ptr, *new_mem;
3967 if (! USE_SSE2(cg)) {
3968 /* SSE unit is not used -> skip this node. */
3972 ptr = get_irn_n(node, 0);
3973 new_ptr = be_transform_node(ptr);
3974 mem = get_irn_n(node, 2);
3975 new_mem = be_transform_node(mem);
3976 noreg = ia32_new_NoReg_gp(cg);
3977 dbgi = get_irn_dbg_info(node);
3979 /* Store SSE -> MEM */
3980 if (is_ia32_xLoad(skip_Proj(new_val))) {
3981 ir_node *ld = skip_Proj(new_val);
3983 /* we can vfld the value directly into the fpu */
3984 fent = get_ia32_frame_ent(ld);
3985 ptr = get_irn_n(ld, 0);
3986 offs = get_ia32_am_offs_int(ld);
3988 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
3990 set_ia32_frame_ent(res, fent);
3991 set_ia32_use_frame(res);
3992 set_ia32_ls_mode(res, lsmode);
3993 set_ia32_op_type(res, ia32_AddrModeD);
3997 /* Load MEM -> x87 */
3998 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3999 set_ia32_frame_ent(res, fent);
4000 set_ia32_use_frame(res);
4001 add_ia32_am_offs_int(res, offs);
4002 set_ia32_op_type(res, ia32_AddrModeS);
4003 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4008 /*********************************************************
4011 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
4012 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
4013 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4014 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4016 *********************************************************/
4019 * the BAD transformer.
4021 static ir_node *bad_transform(ir_node *node) {
4022 panic("No transform function for %+F available.\n", node);
4027 * Transform the Projs of an AddSP.
4029 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4030 ir_node *block = be_transform_node(get_nodes_block(node));
4031 ir_node *pred = get_Proj_pred(node);
4032 ir_node *new_pred = be_transform_node(pred);
4033 ir_graph *irg = current_ir_graph;
4034 dbg_info *dbgi = get_irn_dbg_info(node);
4035 long proj = get_Proj_proj(node);
4037 if (proj == pn_be_AddSP_sp) {
4038 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4039 pn_ia32_SubSP_stack);
4040 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4042 } else if(proj == pn_be_AddSP_res) {
4043 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4044 pn_ia32_SubSP_addr);
4045 } else if (proj == pn_be_AddSP_M) {
4046 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4050 return new_rd_Unknown(irg, get_irn_mode(node));
4054 * Transform the Projs of a SubSP.
4056 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4057 ir_node *block = be_transform_node(get_nodes_block(node));
4058 ir_node *pred = get_Proj_pred(node);
4059 ir_node *new_pred = be_transform_node(pred);
4060 ir_graph *irg = current_ir_graph;
4061 dbg_info *dbgi = get_irn_dbg_info(node);
4062 long proj = get_Proj_proj(node);
4064 if (proj == pn_be_SubSP_sp) {
4065 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4066 pn_ia32_AddSP_stack);
4067 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4069 } else if (proj == pn_be_SubSP_M) {
4070 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4074 return new_rd_Unknown(irg, get_irn_mode(node));
4078 * Transform and renumber the Projs from a Load.
4080 static ir_node *gen_Proj_Load(ir_node *node) {
4082 ir_node *block = be_transform_node(get_nodes_block(node));
4083 ir_node *pred = get_Proj_pred(node);
4084 ir_graph *irg = current_ir_graph;
4085 dbg_info *dbgi = get_irn_dbg_info(node);
4086 long proj = get_Proj_proj(node);
4089 /* loads might be part of source address mode matches, so we don't
4090 transform the ProjMs yet (with the exception of loads whose result is
4093 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4096 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4098 /* this is needed, because sometimes we have loops that are only
4099 reachable through the ProjM */
4100 be_enqueue_preds(node);
4101 /* do it in 2 steps, to silence firm verifier */
4102 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4103 set_Proj_proj(res, pn_ia32_Load_M);
4107 /* renumber the proj */
4108 new_pred = be_transform_node(pred);
4109 if (is_ia32_Load(new_pred)) {
4110 if (proj == pn_Load_res) {
4111 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4113 } else if (proj == pn_Load_M) {
4114 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4117 } else if(is_ia32_Conv_I2I(new_pred)) {
4118 set_irn_mode(new_pred, mode_T);
4119 if (proj == pn_Load_res) {
4120 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4121 } else if (proj == pn_Load_M) {
4122 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4124 } else if (is_ia32_xLoad(new_pred)) {
4125 if (proj == pn_Load_res) {
4126 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4128 } else if (proj == pn_Load_M) {
4129 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4132 } else if (is_ia32_vfld(new_pred)) {
4133 if (proj == pn_Load_res) {
4134 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4136 } else if (proj == pn_Load_M) {
4137 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4141 /* can happen for ProJMs when source address mode happened for the
4144 /* however it should not be the result proj, as that would mean the
4145 load had multiple users and should not have been used for
4147 if(proj != pn_Load_M) {
4148 panic("internal error: transformed node not a Load");
4150 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4154 return new_rd_Unknown(irg, get_irn_mode(node));
4158 * Transform and renumber the Projs from a DivMod like instruction.
4160 static ir_node *gen_Proj_DivMod(ir_node *node) {
4161 ir_node *block = be_transform_node(get_nodes_block(node));
4162 ir_node *pred = get_Proj_pred(node);
4163 ir_node *new_pred = be_transform_node(pred);
4164 ir_graph *irg = current_ir_graph;
4165 dbg_info *dbgi = get_irn_dbg_info(node);
4166 ir_mode *mode = get_irn_mode(node);
4167 long proj = get_Proj_proj(node);
4169 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4171 switch (get_irn_opcode(pred)) {
4175 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4177 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4185 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4187 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4195 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4196 case pn_DivMod_res_div:
4197 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4198 case pn_DivMod_res_mod:
4199 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4209 return new_rd_Unknown(irg, mode);
4213 * Transform and renumber the Projs from a CopyB.
4215 static ir_node *gen_Proj_CopyB(ir_node *node) {
4216 ir_node *block = be_transform_node(get_nodes_block(node));
4217 ir_node *pred = get_Proj_pred(node);
4218 ir_node *new_pred = be_transform_node(pred);
4219 ir_graph *irg = current_ir_graph;
4220 dbg_info *dbgi = get_irn_dbg_info(node);
4221 ir_mode *mode = get_irn_mode(node);
4222 long proj = get_Proj_proj(node);
4225 case pn_CopyB_M_regular:
4226 if (is_ia32_CopyB_i(new_pred)) {
4227 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4228 } else if (is_ia32_CopyB(new_pred)) {
4229 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4237 return new_rd_Unknown(irg, mode);
4241 * Transform and renumber the Projs from a vfdiv.
4243 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
4244 ir_node *block = be_transform_node(get_nodes_block(node));
4245 ir_node *pred = get_Proj_pred(node);
4246 ir_node *new_pred = be_transform_node(pred);
4247 ir_graph *irg = current_ir_graph;
4248 dbg_info *dbgi = get_irn_dbg_info(node);
4249 ir_mode *mode = get_irn_mode(node);
4250 long proj = get_Proj_proj(node);
4253 case pn_ia32_l_vfdiv_M:
4254 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4255 case pn_ia32_l_vfdiv_res:
4256 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4261 return new_rd_Unknown(irg, mode);
4265 * Transform and renumber the Projs from a Quot.
4267 static ir_node *gen_Proj_Quot(ir_node *node) {
4268 ir_node *block = be_transform_node(get_nodes_block(node));
4269 ir_node *pred = get_Proj_pred(node);
4270 ir_node *new_pred = be_transform_node(pred);
4271 ir_graph *irg = current_ir_graph;
4272 dbg_info *dbgi = get_irn_dbg_info(node);
4273 ir_mode *mode = get_irn_mode(node);
4274 long proj = get_Proj_proj(node);
4278 if (is_ia32_xDiv(new_pred)) {
4279 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4280 } else if (is_ia32_vfdiv(new_pred)) {
4281 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4285 if (is_ia32_xDiv(new_pred)) {
4286 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4287 } else if (is_ia32_vfdiv(new_pred)) {
4288 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4296 return new_rd_Unknown(irg, mode);
4300 * Transform the Thread Local Storage Proj.
4302 static ir_node *gen_Proj_tls(ir_node *node) {
4303 ir_node *block = be_transform_node(get_nodes_block(node));
4304 ir_graph *irg = current_ir_graph;
4305 dbg_info *dbgi = NULL;
4306 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4311 static ir_node *gen_be_Call(ir_node *node) {
4312 ir_node *res = be_duplicate_node(node);
4313 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4318 static ir_node *gen_be_IncSP(ir_node *node) {
4319 ir_node *res = be_duplicate_node(node);
4320 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4326 * Transform the Projs from a be_Call.
4328 static ir_node *gen_Proj_be_Call(ir_node *node) {
4329 ir_node *block = be_transform_node(get_nodes_block(node));
4330 ir_node *call = get_Proj_pred(node);
4331 ir_node *new_call = be_transform_node(call);
4332 ir_graph *irg = current_ir_graph;
4333 dbg_info *dbgi = get_irn_dbg_info(node);
4334 ir_type *method_type = be_Call_get_type(call);
4335 int n_res = get_method_n_ress(method_type);
4336 long proj = get_Proj_proj(node);
4337 ir_mode *mode = get_irn_mode(node);
4339 const arch_register_class_t *cls;
4341 /* The following is kinda tricky: If we're using SSE, then we have to
4342 * move the result value of the call in floating point registers to an
4343 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4344 * after the call, we have to make sure to correctly make the
4345 * MemProj and the result Proj use these 2 nodes
4347 if (proj == pn_be_Call_M_regular) {
4348 // get new node for result, are we doing the sse load/store hack?
4349 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4350 ir_node *call_res_new;
4351 ir_node *call_res_pred = NULL;
4353 if (call_res != NULL) {
4354 call_res_new = be_transform_node(call_res);
4355 call_res_pred = get_Proj_pred(call_res_new);
4358 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4359 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4360 pn_be_Call_M_regular);
4362 assert(is_ia32_xLoad(call_res_pred));
4363 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4367 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4368 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4369 && USE_SSE2(env_cg)) {
4371 ir_node *frame = get_irg_frame(irg);
4372 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4374 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4377 /* in case there is no memory output: create one to serialize the copy
4379 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4380 pn_be_Call_M_regular);
4381 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4382 pn_be_Call_first_res);
4384 /* store st(0) onto stack */
4385 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4387 set_ia32_op_type(fstp, ia32_AddrModeD);
4388 set_ia32_use_frame(fstp);
4390 /* load into SSE register */
4391 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4393 set_ia32_op_type(sse_load, ia32_AddrModeS);
4394 set_ia32_use_frame(sse_load);
4396 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4402 /* transform call modes */
4403 if (mode_is_data(mode)) {
4404 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4408 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4412 * Transform the Projs from a Cmp.
4414 static ir_node *gen_Proj_Cmp(ir_node *node)
4416 /* normally Cmps are processed when looking at Cond nodes, but this case
4417 * can happen in complicated Psi conditions */
4418 dbg_info *dbgi = get_irn_dbg_info(node);
4419 ir_node *block = get_nodes_block(node);
4420 ir_node *new_block = be_transform_node(block);
4421 ir_node *cmp = get_Proj_pred(node);
4422 ir_node *new_cmp = be_transform_node(cmp);
4423 long pnc = get_Proj_proj(node);
4426 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node);
4432 * Transform and potentially renumber Proj nodes.
4434 static ir_node *gen_Proj(ir_node *node) {
4435 ir_graph *irg = current_ir_graph;
4436 dbg_info *dbgi = get_irn_dbg_info(node);
4437 ir_node *pred = get_Proj_pred(node);
4438 long proj = get_Proj_proj(node);
4440 if (is_Store(pred)) {
4441 if (proj == pn_Store_M) {
4442 return be_transform_node(pred);
4445 return new_r_Bad(irg);
4447 } else if (is_Load(pred)) {
4448 return gen_Proj_Load(node);
4449 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4450 return gen_Proj_DivMod(node);
4451 } else if (is_CopyB(pred)) {
4452 return gen_Proj_CopyB(node);
4453 } else if (is_Quot(pred)) {
4454 return gen_Proj_Quot(node);
4455 } else if (is_ia32_l_vfdiv(pred)) {
4456 return gen_Proj_l_vfdiv(node);
4457 } else if (be_is_SubSP(pred)) {
4458 return gen_Proj_be_SubSP(node);
4459 } else if (be_is_AddSP(pred)) {
4460 return gen_Proj_be_AddSP(node);
4461 } else if (be_is_Call(pred)) {
4462 return gen_Proj_be_Call(node);
4463 } else if (is_Cmp(pred)) {
4464 return gen_Proj_Cmp(node);
4465 } else if (get_irn_op(pred) == op_Start) {
4466 if (proj == pn_Start_X_initial_exec) {
4467 ir_node *block = get_nodes_block(pred);
4470 /* we exchange the ProjX with a jump */
4471 block = be_transform_node(block);
4472 jump = new_rd_Jmp(dbgi, irg, block);
4475 if (node == be_get_old_anchor(anchor_tls)) {
4476 return gen_Proj_tls(node);
4479 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4483 ir_node *new_pred = be_transform_node(pred);
4484 ir_node *block = be_transform_node(get_nodes_block(node));
4485 ir_mode *mode = get_irn_mode(node);
4486 if (mode_needs_gp_reg(mode)) {
4487 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4488 get_Proj_proj(node));
4489 #ifdef DEBUG_libfirm
4490 new_proj->node_nr = node->node_nr;
4496 return be_duplicate_node(node);
4500 * Enters all transform functions into the generic pointer
4502 static void register_transformers(void)
4506 /* first clear the generic function pointer for all ops */
4507 clear_irp_opcodes_generic_func();
4509 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4510 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4548 /* transform ops from intrinsic lowering */
4570 GEN(ia32_l_X87toSSE);
4571 GEN(ia32_l_SSEtoX87);
4577 /* we should never see these nodes */
4592 /* handle generic backend nodes */
4601 op_Mulh = get_op_Mulh();
4610 * Pre-transform all unknown and noreg nodes.
4612 static void ia32_pretransform_node(void *arch_cg) {
4613 ia32_code_gen_t *cg = arch_cg;
4615 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4616 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4617 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4618 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4619 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4620 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4625 * Walker, checks if all ia32 nodes producing more than one result have
4626 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4628 static void add_missing_keep_walker(ir_node *node, void *data)
4631 unsigned found_projs = 0;
4632 const ir_edge_t *edge;
4633 ir_mode *mode = get_irn_mode(node);
4638 if(!is_ia32_irn(node))
4641 n_outs = get_ia32_n_res(node);
4644 if(is_ia32_SwitchJmp(node))
4647 assert(n_outs < (int) sizeof(unsigned) * 8);
4648 foreach_out_edge(node, edge) {
4649 ir_node *proj = get_edge_src_irn(edge);
4650 int pn = get_Proj_proj(proj);
4652 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4653 found_projs |= 1 << pn;
4657 /* are keeps missing? */
4659 for(i = 0; i < n_outs; ++i) {
4662 const arch_register_req_t *req;
4663 const arch_register_class_t *class;
4665 if(found_projs & (1 << i)) {
4669 req = get_ia32_out_req(node, i);
4674 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4678 block = get_nodes_block(node);
4679 in[0] = new_r_Proj(current_ir_graph, block, node,
4680 arch_register_class_mode(class), i);
4681 if(last_keep != NULL) {
4682 be_Keep_add_node(last_keep, class, in[0]);
4684 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4685 if(sched_is_scheduled(node)) {
4686 sched_add_after(node, last_keep);
4693 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4696 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4698 ir_graph *irg = be_get_birg_irg(cg->birg);
4699 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4702 /* do the transformation */
4703 void ia32_transform_graph(ia32_code_gen_t *cg) {
4704 ir_graph *irg = cg->irg;
4706 register_transformers();
4708 initial_fpcw = NULL;
4710 heights = heights_new(irg);
4711 calculate_non_address_mode_nodes(irg);
4713 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4715 free_non_address_mode_nodes();
4716 heights_free(heights);
4720 void ia32_init_transform(void)
4722 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");