2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
15 #include "irgraph_t.h"
20 #include "iredges_t.h"
29 #include "../benode_t.h"
30 #include "../besched.h"
33 #include "../arch/archop.h" /* we need this for Min and Max nodes */
35 #include "bearch_ia32_t.h"
36 #include "ia32_nodes_attr.h"
37 #include "ia32_transform.h"
38 #include "ia32_new_nodes.h"
39 #include "ia32_map_regs.h"
40 #include "ia32_dbg_stat.h"
41 #include "ia32_optimize.h"
43 #include "gen_ia32_regalloc_if.h"
45 #define SFP_SIGN "0x80000000"
46 #define DFP_SIGN "0x8000000000000000"
47 #define SFP_ABS "0x7FFFFFFF"
48 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
50 #define TP_SFP_SIGN "ia32_sfp_sign"
51 #define TP_DFP_SIGN "ia32_dfp_sign"
52 #define TP_SFP_ABS "ia32_sfp_abs"
53 #define TP_DFP_ABS "ia32_dfp_abs"
55 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
56 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
57 #define ENT_SFP_ABS "IA32_SFP_ABS"
58 #define ENT_DFP_ABS "IA32_DFP_ABS"
60 extern ir_op *get_op_Mulh(void);
62 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
63 ir_node *op1, ir_node *op2, ir_node *mem);
65 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
66 ir_node *op, ir_node *mem);
69 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
72 /****************************************************************************************************
74 * | | | | / _| | | (_)
75 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
76 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
77 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
78 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
80 ****************************************************************************************************/
83 * Returns 1 if irn is a Const representing 0, 0 otherwise
85 static INLINE int is_ia32_Const_0(ir_node *irn) {
86 return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
90 * Returns 1 if irn is a Const representing 1, 0 otherwise
92 static INLINE int is_ia32_Const_1(ir_node *irn) {
93 return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
97 * Returns the Proj representing the UNKNOWN register for given mode.
99 static ir_node *be_get_unknown_for_mode(ia32_code_gen_t *cg, ir_mode *mode) {
100 be_abi_irg_t *babi = cg->birg->abi;
101 const arch_register_t *unknwn_reg = NULL;
103 if (mode_is_float(mode)) {
104 unknwn_reg = USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_UKNWN] : &ia32_vfp_regs[REG_VFP_UKNWN];
107 unknwn_reg = &ia32_gp_regs[REG_GP_UKNWN];
110 return be_abi_get_callee_save_irn(babi, unknwn_reg);
114 * Gets the Proj with number pn from irn.
116 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
117 const ir_edge_t *edge;
119 assert(get_irn_mode(irn) == mode_T && "need mode_T");
121 foreach_out_edge(irn, edge) {
122 proj = get_edge_src_irn(edge);
124 if (get_Proj_proj(proj) == pn)
132 * SSE convert of an integer node into a floating point node.
134 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block,
135 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
137 ir_node *noreg = ia32_new_NoReg_gp(cg);
138 ir_node *nomem = new_rd_NoMem(irg);
140 ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
141 set_ia32_src_mode(conv, get_irn_mode(in));
142 set_ia32_tgt_mode(conv, tgt_mode);
143 set_ia32_am_support(conv, ia32_am_Source);
144 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
146 return new_rd_Proj(dbg, irg, block, conv, tgt_mode, pn_ia32_Conv_I2FP_res);
149 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
150 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
151 static const struct {
153 const char *ent_name;
154 const char *cnst_str;
155 } names [ia32_known_const_max] = {
156 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
157 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
158 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
159 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
161 static struct entity *ent_cache[ia32_known_const_max];
163 const char *tp_name, *ent_name, *cnst_str;
170 ent_name = names[kct].ent_name;
171 if (! ent_cache[kct]) {
172 tp_name = names[kct].tp_name;
173 cnst_str = names[kct].cnst_str;
175 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
176 tp = new_type_primitive(new_id_from_str(tp_name), mode);
177 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
179 set_entity_ld_ident(ent, get_entity_ident(ent));
180 set_entity_visibility(ent, visibility_local);
181 set_entity_variability(ent, variability_constant);
182 set_entity_allocation(ent, allocation_static);
184 /* we create a new entity here: It's initialization must resist on the
186 rem = current_ir_graph;
187 current_ir_graph = get_const_code_irg();
188 cnst = new_Const(mode, tv);
189 current_ir_graph = rem;
191 set_atomic_ent_value(ent, cnst);
193 /* cache the entry */
194 ent_cache[kct] = ent;
197 return get_entity_ident(ent_cache[kct]);
202 * Prints the old node name on cg obst and returns a pointer to it.
204 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
205 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
207 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
208 obstack_1grow(isa->name_obst, 0);
209 isa->name_obst_size += obstack_object_size(isa->name_obst);
210 return obstack_finish(isa->name_obst);
214 /* determine if one operator is an Imm */
215 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
217 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
218 else return is_ia32_Cnst(op2) ? op2 : NULL;
221 /* determine if one operator is not an Imm */
222 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
223 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
228 * Construct a standard binary operation, set AM and immediate if required.
230 * @param env The transformation environment
231 * @param op1 The first operand
232 * @param op2 The second operand
233 * @param func The node constructor function
234 * @return The constructed ia32 node.
236 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
237 ir_node *new_op = NULL;
238 ir_mode *mode = env->mode;
239 dbg_info *dbg = env->dbg;
240 ir_graph *irg = env->irg;
241 ir_node *block = env->block;
242 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
243 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
244 ir_node *nomem = new_NoMem();
245 ir_node *expr_op, *imm_op;
246 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
248 /* Check if immediate optimization is on and */
249 /* if it's an operation with immediate. */
250 if (! (env->cg->opt & IA32_OPT_IMMOPS)) {
254 else if (is_op_commutative(get_irn_op(env->irn))) {
255 imm_op = get_immediate_op(op1, op2);
256 expr_op = get_expr_op(op1, op2);
259 imm_op = get_immediate_op(NULL, op2);
260 expr_op = get_expr_op(op1, op2);
263 assert((expr_op || imm_op) && "invalid operands");
266 /* We have two consts here: not yet supported */
270 if (mode_is_float(mode)) {
271 /* floating point operations */
273 DB((mod, LEVEL_1, "FP with immediate ..."));
274 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
275 set_ia32_Immop_attr(new_op, imm_op);
276 set_ia32_am_support(new_op, ia32_am_None);
279 DB((mod, LEVEL_1, "FP binop ..."));
280 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
281 set_ia32_am_support(new_op, ia32_am_Source);
283 set_ia32_ls_mode(new_op, mode);
286 /* integer operations */
288 /* This is expr + const */
289 DB((mod, LEVEL_1, "INT with immediate ..."));
290 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
291 set_ia32_Immop_attr(new_op, imm_op);
294 set_ia32_am_support(new_op, ia32_am_Dest);
297 DB((mod, LEVEL_1, "INT binop ..."));
298 /* This is a normal operation */
299 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
302 set_ia32_am_support(new_op, ia32_am_Full);
306 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
308 set_ia32_res_mode(new_op, mode);
310 if (is_op_commutative(get_irn_op(env->irn))) {
311 set_ia32_commutative(new_op);
314 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
320 * Construct a shift/rotate binary operation, sets AM and immediate if required.
322 * @param env The transformation environment
323 * @param op1 The first operand
324 * @param op2 The second operand
325 * @param func The node constructor function
326 * @return The constructed ia32 node.
328 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
329 ir_node *new_op = NULL;
330 ir_mode *mode = env->mode;
331 dbg_info *dbg = env->dbg;
332 ir_graph *irg = env->irg;
333 ir_node *block = env->block;
334 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
335 ir_node *nomem = new_NoMem();
336 ir_node *expr_op, *imm_op;
338 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
340 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
342 /* Check if immediate optimization is on and */
343 /* if it's an operation with immediate. */
344 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
345 expr_op = get_expr_op(op1, op2);
347 assert((expr_op || imm_op) && "invalid operands");
350 /* We have two consts here: not yet supported */
354 /* Limit imm_op within range imm8 */
356 tv = get_ia32_Immop_tarval(imm_op);
359 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
366 /* integer operations */
368 /* This is shift/rot with const */
369 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
371 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
372 set_ia32_Immop_attr(new_op, imm_op);
375 /* This is a normal shift/rot */
376 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
377 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
381 set_ia32_am_support(new_op, ia32_am_Dest);
383 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
385 set_ia32_res_mode(new_op, mode);
386 set_ia32_emit_cl(new_op);
388 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
393 * Construct a standard unary operation, set AM and immediate if required.
395 * @param env The transformation environment
396 * @param op The operand
397 * @param func The node constructor function
398 * @return The constructed ia32 node.
400 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
401 ir_node *new_op = NULL;
402 ir_mode *mode = env->mode;
403 dbg_info *dbg = env->dbg;
404 ir_graph *irg = env->irg;
405 ir_node *block = env->block;
406 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
407 ir_node *nomem = new_NoMem();
408 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
410 new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
412 if (mode_is_float(mode)) {
413 DB((mod, LEVEL_1, "FP unop ..."));
414 /* floating point operations don't support implicit store */
415 set_ia32_am_support(new_op, ia32_am_None);
418 DB((mod, LEVEL_1, "INT unop ..."));
419 set_ia32_am_support(new_op, ia32_am_Dest);
422 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
424 set_ia32_res_mode(new_op, mode);
426 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
432 * Creates an ia32 Add with immediate.
434 * @param env The transformation environment
435 * @param expr_op The expression operator
436 * @param const_op The constant
437 * @return the created ia32 Add node
439 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
440 ir_node *new_op = NULL;
441 tarval *tv = get_ia32_Immop_tarval(const_op);
442 dbg_info *dbg = env->dbg;
443 ir_graph *irg = env->irg;
444 ir_node *block = env->block;
445 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
446 ir_node *nomem = new_NoMem();
448 tarval_classification_t class_tv, class_negtv;
449 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
451 /* try to optimize to inc/dec */
452 if ((env->cg->opt & IA32_OPT_INCDEC) && (get_ia32_op_type(const_op) == ia32_Const)) {
453 /* optimize tarvals */
454 class_tv = classify_tarval(tv);
455 class_negtv = classify_tarval(tarval_neg(tv));
457 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
458 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
459 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
462 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
463 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
464 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
470 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
471 set_ia32_Immop_attr(new_op, const_op);
472 set_ia32_commutative(new_op);
479 * Creates an ia32 Add.
481 * @param env The transformation environment
482 * @return the created ia32 Add node
484 static ir_node *gen_Add(ia32_transform_env_t *env) {
485 ir_node *new_op = NULL;
486 dbg_info *dbg = env->dbg;
487 ir_mode *mode = env->mode;
488 ir_graph *irg = env->irg;
489 ir_node *block = env->block;
490 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
491 ir_node *nomem = new_NoMem();
492 ir_node *expr_op, *imm_op;
493 ir_node *op1 = get_Add_left(env->irn);
494 ir_node *op2 = get_Add_right(env->irn);
496 /* Check if immediate optimization is on and */
497 /* if it's an operation with immediate. */
498 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
499 expr_op = get_expr_op(op1, op2);
501 assert((expr_op || imm_op) && "invalid operands");
503 if (mode_is_float(mode)) {
505 if (USE_SSE2(env->cg))
506 return gen_binop(env, op1, op2, new_rd_ia32_xAdd);
508 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
513 /* No expr_op means, that we have two const - one symconst and */
514 /* one tarval or another symconst - because this case is not */
515 /* covered by constant folding */
516 /* We need to check for: */
517 /* 1) symconst + const -> becomes a LEA */
518 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
519 /* linker doesn't support two symconsts */
521 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
522 /* this is the 2nd case */
523 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
524 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
525 set_ia32_am_flavour(new_op, ia32_am_OB);
527 DBG_OPT_LEA1(op2, new_op);
530 /* this is the 1st case */
531 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
533 DBG_OPT_LEA2(op1, op2, new_op);
535 if (get_ia32_op_type(op1) == ia32_SymConst) {
536 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
537 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
540 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
541 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
543 set_ia32_am_flavour(new_op, ia32_am_O);
547 set_ia32_am_support(new_op, ia32_am_Source);
548 set_ia32_op_type(new_op, ia32_AddrModeS);
550 /* Lea doesn't need a Proj */
554 /* This is expr + const */
555 new_op = gen_imm_Add(env, expr_op, imm_op);
558 set_ia32_am_support(new_op, ia32_am_Dest);
561 /* This is a normal add */
562 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
565 set_ia32_am_support(new_op, ia32_am_Full);
566 set_ia32_commutative(new_op);
570 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
572 set_ia32_res_mode(new_op, mode);
574 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Add_res);
578 * Transforms an ia32_l_AddC (created in intrinsic lowering) into a "real" AddC
580 * @param env The transformation environment
581 * @return the created ia32 Add node
583 static ir_node *gen_ia32_l_AddC(ia32_transform_env_t *env) {
584 return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_AddC);
588 * Transforms an ia32_l_Add (created in intrinsic lowering) into a "real" Add
590 * @param env The transformation environment
591 * @return the created ia32 Add node
593 static ir_node *gen_ia32_l_Add(ia32_transform_env_t *env) {
594 return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_Add);
600 * Creates an ia32 Mul.
602 * @param env The transformation environment
603 * @return the created ia32 Mul node
605 static ir_node *gen_Mul(ia32_transform_env_t *env) {
606 ir_node *op1 = get_Mul_left(env->irn);
607 ir_node *op2 = get_Mul_right(env->irn);
610 if (mode_is_float(env->mode)) {
612 if (USE_SSE2(env->cg))
613 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMul);
615 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
618 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
627 * Creates an ia32 Mulh.
628 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
629 * this result while Mul returns the lower 32 bit.
631 * @param env The transformation environment
632 * @return the created ia32 Mulh node
634 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
635 ir_node *op1 = get_irn_n(env->irn, 0);
636 ir_node *op2 = get_irn_n(env->irn, 1);
637 ir_node *proj_EAX, *proj_EDX, *mulh;
640 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
641 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
642 mulh = get_Proj_pred(proj_EAX);
643 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
645 /* to be on the save side */
646 set_Proj_proj(proj_EAX, pn_EAX);
648 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
649 /* Mulh with const cannot have AM */
650 set_ia32_am_support(mulh, ia32_am_None);
653 /* Mulh cannot have AM for destination */
654 set_ia32_am_support(mulh, ia32_am_Source);
660 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
668 * Creates an ia32 And.
670 * @param env The transformation environment
671 * @return The created ia32 And node
673 static ir_node *gen_And(ia32_transform_env_t *env) {
674 ir_node *op1 = get_And_left(env->irn);
675 ir_node *op2 = get_And_right(env->irn);
677 assert (! mode_is_float(env->mode));
678 return gen_binop(env, op1, op2, new_rd_ia32_And);
684 * Creates an ia32 Or.
686 * @param env The transformation environment
687 * @return The created ia32 Or node
689 static ir_node *gen_Or(ia32_transform_env_t *env) {
690 ir_node *op1 = get_Or_left(env->irn);
691 ir_node *op2 = get_Or_right(env->irn);
693 assert (! mode_is_float(env->mode));
694 return gen_binop(env, op1, op2, new_rd_ia32_Or);
700 * Creates an ia32 Eor.
702 * @param env The transformation environment
703 * @return The created ia32 Eor node
705 static ir_node *gen_Eor(ia32_transform_env_t *env) {
706 ir_node *op1 = get_Eor_left(env->irn);
707 ir_node *op2 = get_Eor_right(env->irn);
709 assert(! mode_is_float(env->mode));
710 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
716 * Creates an ia32 Max.
718 * @param env The transformation environment
719 * @return the created ia32 Max node
721 static ir_node *gen_Max(ia32_transform_env_t *env) {
722 ir_node *op1 = get_irn_n(env->irn, 0);
723 ir_node *op2 = get_irn_n(env->irn, 1);
726 if (mode_is_float(env->mode)) {
728 if (USE_SSE2(env->cg))
729 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMax);
735 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
736 set_ia32_am_support(new_op, ia32_am_None);
737 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
746 * Creates an ia32 Min.
748 * @param env The transformation environment
749 * @return the created ia32 Min node
751 static ir_node *gen_Min(ia32_transform_env_t *env) {
752 ir_node *op1 = get_irn_n(env->irn, 0);
753 ir_node *op2 = get_irn_n(env->irn, 1);
756 if (mode_is_float(env->mode)) {
758 if (USE_SSE2(env->cg))
759 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMin);
765 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
766 set_ia32_am_support(new_op, ia32_am_None);
767 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
776 * Creates an ia32 Sub with immediate.
778 * @param env The transformation environment
779 * @param expr_op The first operator
780 * @param const_op The constant operator
781 * @return The created ia32 Sub node
783 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
784 ir_node *new_op = NULL;
785 tarval *tv = get_ia32_Immop_tarval(const_op);
786 dbg_info *dbg = env->dbg;
787 ir_graph *irg = env->irg;
788 ir_node *block = env->block;
789 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
790 ir_node *nomem = new_NoMem();
792 tarval_classification_t class_tv, class_negtv;
793 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
795 /* try to optimize to inc/dec */
796 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
797 /* optimize tarvals */
798 class_tv = classify_tarval(tv);
799 class_negtv = classify_tarval(tarval_neg(tv));
801 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
802 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
803 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
806 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
807 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
808 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
814 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
815 set_ia32_Immop_attr(new_op, const_op);
822 * Creates an ia32 Sub.
824 * @param env The transformation environment
825 * @return The created ia32 Sub node
827 static ir_node *gen_Sub(ia32_transform_env_t *env) {
828 ir_node *new_op = NULL;
829 dbg_info *dbg = env->dbg;
830 ir_mode *mode = env->mode;
831 ir_graph *irg = env->irg;
832 ir_node *block = env->block;
833 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
834 ir_node *nomem = new_NoMem();
835 ir_node *op1 = get_Sub_left(env->irn);
836 ir_node *op2 = get_Sub_right(env->irn);
837 ir_node *expr_op, *imm_op;
839 /* Check if immediate optimization is on and */
840 /* if it's an operation with immediate. */
841 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
842 expr_op = get_expr_op(op1, op2);
844 assert((expr_op || imm_op) && "invalid operands");
846 if (mode_is_float(mode)) {
848 if (USE_SSE2(env->cg))
849 return gen_binop(env, op1, op2, new_rd_ia32_xSub);
851 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
856 /* No expr_op means, that we have two const - one symconst and */
857 /* one tarval or another symconst - because this case is not */
858 /* covered by constant folding */
859 /* We need to check for: */
860 /* 1) symconst + const -> becomes a LEA */
861 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
862 /* linker doesn't support two symconsts */
864 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
865 /* this is the 2nd case */
866 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
867 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
868 set_ia32_am_sc_sign(new_op);
869 set_ia32_am_flavour(new_op, ia32_am_OB);
871 DBG_OPT_LEA1(op2, new_op);
874 /* this is the 1st case */
875 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
877 DBG_OPT_LEA2(op1, op2, new_op);
879 if (get_ia32_op_type(op1) == ia32_SymConst) {
880 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
881 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
884 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
885 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
886 set_ia32_am_sc_sign(new_op);
888 set_ia32_am_flavour(new_op, ia32_am_O);
892 set_ia32_am_support(new_op, ia32_am_Source);
893 set_ia32_op_type(new_op, ia32_AddrModeS);
895 /* Lea doesn't need a Proj */
899 /* This is expr - const */
900 new_op = gen_imm_Sub(env, expr_op, imm_op);
903 set_ia32_am_support(new_op, ia32_am_Dest);
906 /* This is a normal sub */
907 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
910 set_ia32_am_support(new_op, ia32_am_Full);
914 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
916 set_ia32_res_mode(new_op, mode);
918 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Sub_res);
922 * Transforms an ia32_l_SubC (created in intrinsic lowering) into a "real" SubC
924 * @param env The transformation environment
925 * @return the created ia32 SubC node
927 static ir_node *gen_ia32_l_SubC(ia32_transform_env_t *env) {
928 return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_SubC);
932 * Transforms an ia32_l_Sub (created in intrinsic lowering) into a "real" Sub
934 * @param env The transformation environment
935 * @return the created ia32 Sub node
937 static ir_node *gen_ia32_l_Sub(ia32_transform_env_t *env) {
938 return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_Sub);
944 * Generates an ia32 DivMod with additional infrastructure for the
945 * register allocator if needed.
947 * @param env The transformation environment
948 * @param dividend -no comment- :)
949 * @param divisor -no comment- :)
950 * @param dm_flav flavour_Div/Mod/DivMod
951 * @return The created ia32 DivMod node
953 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
955 ir_node *edx_node, *cltd;
957 dbg_info *dbg = env->dbg;
958 ir_graph *irg = env->irg;
959 ir_node *block = env->block;
960 ir_mode *mode = env->mode;
961 ir_node *irn = env->irn;
966 mem = get_Div_mem(irn);
967 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
970 mem = get_Mod_mem(irn);
971 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
974 mem = get_DivMod_mem(irn);
975 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
981 if (mode_is_signed(mode)) {
982 /* in signed mode, we need to sign extend the dividend */
983 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
984 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
985 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
988 edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
989 set_ia32_Const_type(edx_node, ia32_Const);
990 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
993 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
995 set_ia32_n_res(res, 2);
997 /* Only one proj is used -> We must add a second proj and */
998 /* connect this one to a Keep node to eat up the second */
999 /* destroyed register. */
1000 if (get_irn_n_edges(irn) == 1) {
1001 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
1002 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
1004 if (get_irn_op(irn) == op_Div) {
1005 set_Proj_proj(proj, pn_DivMod_res_div);
1006 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
1009 set_Proj_proj(proj, pn_DivMod_res_mod);
1010 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
1013 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1016 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1018 set_ia32_res_mode(res, mode_Is);
1025 * Wrapper for generate_DivMod. Sets flavour_Mod.
1027 * @param env The transformation environment
1029 static ir_node *gen_Mod(ia32_transform_env_t *env) {
1030 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
1034 * Wrapper for generate_DivMod. Sets flavour_Div.
1036 * @param env The transformation environment
1038 static ir_node *gen_Div(ia32_transform_env_t *env) {
1039 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
1043 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1045 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
1046 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
1052 * Creates an ia32 floating Div.
1054 * @param env The transformation environment
1055 * @return The created ia32 xDiv node
1057 static ir_node *gen_Quot(ia32_transform_env_t *env) {
1058 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1060 ir_node *nomem = new_rd_NoMem(env->irg);
1061 ir_node *op1 = get_Quot_left(env->irn);
1062 ir_node *op2 = get_Quot_right(env->irn);
1065 if (USE_SSE2(env->cg)) {
1066 if (is_ia32_xConst(op2)) {
1067 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
1068 set_ia32_am_support(new_op, ia32_am_None);
1069 set_ia32_Immop_attr(new_op, op2);
1072 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1073 set_ia32_am_support(new_op, ia32_am_Source);
1077 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1078 set_ia32_am_support(new_op, ia32_am_Source);
1080 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
1081 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1089 * Creates an ia32 Shl.
1091 * @param env The transformation environment
1092 * @return The created ia32 Shl node
1094 static ir_node *gen_Shl(ia32_transform_env_t *env) {
1095 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
1101 * Creates an ia32 Shr.
1103 * @param env The transformation environment
1104 * @return The created ia32 Shr node
1106 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1107 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1113 * Creates an ia32 Shrs.
1115 * @param env The transformation environment
1116 * @return The created ia32 Shrs node
1118 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1119 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1125 * Creates an ia32 RotL.
1127 * @param env The transformation environment
1128 * @param op1 The first operator
1129 * @param op2 The second operator
1130 * @return The created ia32 RotL node
1132 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1133 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1139 * Creates an ia32 RotR.
1140 * NOTE: There is no RotR with immediate because this would always be a RotL
1141 * "imm-mode_size_bits" which can be pre-calculated.
1143 * @param env The transformation environment
1144 * @param op1 The first operator
1145 * @param op2 The second operator
1146 * @return The created ia32 RotR node
1148 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1149 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1155 * Creates an ia32 RotR or RotL (depending on the found pattern).
1157 * @param env The transformation environment
1158 * @return The created ia32 RotL or RotR node
1160 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1161 ir_node *rotate = NULL;
1162 ir_node *op1 = get_Rot_left(env->irn);
1163 ir_node *op2 = get_Rot_right(env->irn);
1165 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1166 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1167 that means we can create a RotR instead of an Add and a RotL */
1170 ir_node *pred = get_Proj_pred(op2);
1172 if (is_ia32_Add(pred)) {
1173 ir_node *pred_pred = get_irn_n(pred, 2);
1174 tarval *tv = get_ia32_Immop_tarval(pred);
1175 long bits = get_mode_size_bits(env->mode);
1177 if (is_Proj(pred_pred)) {
1178 pred_pred = get_Proj_pred(pred_pred);
1181 if (is_ia32_Minus(pred_pred) &&
1182 tarval_is_long(tv) &&
1183 get_tarval_long(tv) == bits)
1185 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1186 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1193 rotate = gen_RotL(env, op1, op2);
1202 * Transforms a Minus node.
1204 * @param env The transformation environment
1205 * @param op The Minus operand
1206 * @return The created ia32 Minus node
1208 static ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1213 if (mode_is_float(env->mode)) {
1215 if (USE_SSE2(env->cg)) {
1216 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1217 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1218 ir_node *nomem = new_rd_NoMem(env->irg);
1220 new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1222 size = get_mode_size_bits(env->mode);
1223 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1225 set_ia32_sc(new_op, name);
1227 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1229 set_ia32_res_mode(new_op, env->mode);
1230 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1232 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
1235 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1236 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1240 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1247 * Transforms a Minus node.
1249 * @param env The transformation environment
1250 * @return The created ia32 Minus node
1252 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1253 return gen_Minus_ex(env, get_Minus_op(env->irn));
1258 * Transforms a Not node.
1260 * @param env The transformation environment
1261 * @return The created ia32 Not node
1263 static ir_node *gen_Not(ia32_transform_env_t *env) {
1264 assert (! mode_is_float(env->mode));
1265 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1271 * Transforms an Abs node.
1273 * @param env The transformation environment
1274 * @return The created ia32 Abs node
1276 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1277 ir_node *res, *p_eax, *p_edx;
1278 dbg_info *dbg = env->dbg;
1279 ir_mode *mode = env->mode;
1280 ir_graph *irg = env->irg;
1281 ir_node *block = env->block;
1282 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1283 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1284 ir_node *nomem = new_NoMem();
1285 ir_node *op = get_Abs_op(env->irn);
1289 if (mode_is_float(mode)) {
1291 if (USE_SSE2(env->cg)) {
1292 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1294 size = get_mode_size_bits(mode);
1295 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1297 set_ia32_sc(res, name);
1299 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1301 set_ia32_res_mode(res, mode);
1302 set_ia32_immop_type(res, ia32_ImmSymConst);
1304 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
1307 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1308 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1312 res = new_rd_ia32_Cdq(dbg, irg, block, op);
1313 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1314 set_ia32_res_mode(res, mode);
1316 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
1317 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
1319 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1320 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1321 set_ia32_res_mode(res, mode);
1323 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
1325 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1326 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1327 set_ia32_res_mode(res, mode);
1329 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
1338 * Transforms a Load.
1340 * @param env The transformation environment
1341 * @return the created ia32 Load node
1343 static ir_node *gen_Load(ia32_transform_env_t *env) {
1344 ir_node *node = env->irn;
1345 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1346 ir_node *ptr = get_Load_ptr(node);
1347 ir_node *lptr = ptr;
1348 ir_mode *mode = get_Load_mode(node);
1351 ia32_am_flavour_t am_flav = ia32_B;
1353 /* address might be a constant (symconst or absolute address) */
1354 if (is_ia32_Const(ptr)) {
1359 if (mode_is_float(mode)) {
1361 if (USE_SSE2(env->cg))
1362 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1364 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1367 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1370 /* base is an constant address */
1372 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1373 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1376 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1382 set_ia32_am_support(new_op, ia32_am_Source);
1383 set_ia32_op_type(new_op, ia32_AddrModeS);
1384 set_ia32_am_flavour(new_op, am_flav);
1385 set_ia32_ls_mode(new_op, mode);
1387 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1395 * Transforms a Store.
1397 * @param env The transformation environment
1398 * @return the created ia32 Store node
1400 static ir_node *gen_Store(ia32_transform_env_t *env) {
1401 ir_node *node = env->irn;
1402 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1403 ir_node *val = get_Store_value(node);
1404 ir_node *ptr = get_Store_ptr(node);
1405 ir_node *sptr = ptr;
1406 ir_node *mem = get_Store_mem(node);
1407 ir_mode *mode = get_irn_mode(val);
1408 ir_node *sval = val;
1411 ia32_am_flavour_t am_flav = ia32_B;
1412 ia32_immop_type_t immop = ia32_ImmNone;
1414 if (! mode_is_float(mode)) {
1415 /* in case of storing a const (but not a symconst) -> make it an attribute */
1416 if (is_ia32_Cnst(val)) {
1417 switch (get_ia32_op_type(val)) {
1419 immop = ia32_ImmConst;
1422 immop = ia32_ImmSymConst;
1425 assert(0 && "unsupported Const type");
1431 /* address might be a constant (symconst or absolute address) */
1432 if (is_ia32_Const(ptr)) {
1437 if (mode_is_float(mode)) {
1439 if (USE_SSE2(env->cg))
1440 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1442 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1444 else if (get_mode_size_bits(mode) == 8) {
1445 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1448 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1451 /* stored const is an attribute (saves a register) */
1452 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1453 set_ia32_Immop_attr(new_op, val);
1456 /* base is an constant address */
1458 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1459 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1462 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1468 set_ia32_am_support(new_op, ia32_am_Dest);
1469 set_ia32_op_type(new_op, ia32_AddrModeD);
1470 set_ia32_am_flavour(new_op, am_flav);
1471 set_ia32_ls_mode(new_op, get_irn_mode(val));
1472 set_ia32_immop_type(new_op, immop);
1474 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1482 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1484 * @param env The transformation environment
1485 * @return The transformed node.
1487 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1488 dbg_info *dbg = env->dbg;
1489 ir_graph *irg = env->irg;
1490 ir_node *block = env->block;
1491 ir_node *node = env->irn;
1492 ir_node *sel = get_Cond_selector(node);
1493 ir_mode *sel_mode = get_irn_mode(sel);
1494 ir_node *res = NULL;
1495 ir_node *pred = NULL;
1496 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1497 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1499 if (is_Proj(sel) && sel_mode == mode_b) {
1500 ir_node *nomem = new_NoMem();
1502 pred = get_Proj_pred(sel);
1504 /* get both compare operators */
1505 cmp_a = get_Cmp_left(pred);
1506 cmp_b = get_Cmp_right(pred);
1508 /* check if we can use a CondJmp with immediate */
1509 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1510 expr = get_expr_op(cmp_a, cmp_b);
1513 pn_Cmp pnc = get_Proj_proj(sel);
1515 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1516 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1517 /* a Cmp A =/!= 0 */
1518 ir_node *op1 = expr;
1519 ir_node *op2 = expr;
1520 ir_node *and = skip_Proj(expr);
1521 const char *cnst = NULL;
1523 /* check, if expr is an only once used And operation */
1524 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1525 op1 = get_irn_n(and, 2);
1526 op2 = get_irn_n(and, 3);
1528 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1530 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1531 set_ia32_pncode(res, get_Proj_proj(sel));
1532 set_ia32_res_mode(res, get_irn_mode(op1));
1535 copy_ia32_Immop_attr(res, and);
1538 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1543 if (mode_is_float(get_irn_mode(expr))) {
1545 if (USE_SSE2(env->cg))
1546 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1552 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1554 set_ia32_Immop_attr(res, cnst);
1555 set_ia32_res_mode(res, get_irn_mode(expr));
1558 if (mode_is_float(get_irn_mode(cmp_a))) {
1560 if (USE_SSE2(env->cg))
1561 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1564 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1565 proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
1566 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1570 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1571 set_ia32_commutative(res);
1573 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1576 set_ia32_pncode(res, get_Proj_proj(sel));
1577 //set_ia32_am_support(res, ia32_am_Source);
1580 /* determine the smallest switch case value */
1581 int switch_min = INT_MAX;
1582 const ir_edge_t *edge;
1585 foreach_out_edge(node, edge) {
1586 int pn = get_Proj_proj(get_edge_src_irn(edge));
1587 switch_min = pn < switch_min ? pn : switch_min;
1591 /* if smallest switch case is not 0 we need an additional sub */
1592 snprintf(buf, sizeof(buf), "%d", switch_min);
1593 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1594 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1595 sub_ia32_am_offs(res, buf);
1596 set_ia32_am_flavour(res, ia32_am_OB);
1597 set_ia32_am_support(res, ia32_am_Source);
1598 set_ia32_op_type(res, ia32_AddrModeS);
1601 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1602 set_ia32_pncode(res, get_Cond_defaultProj(node));
1603 set_ia32_res_mode(res, get_irn_mode(sel));
1606 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1613 * Transforms a CopyB node.
1615 * @param env The transformation environment
1616 * @return The transformed node.
1618 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1619 ir_node *res = NULL;
1620 dbg_info *dbg = env->dbg;
1621 ir_graph *irg = env->irg;
1622 ir_mode *mode = env->mode;
1623 ir_node *block = env->block;
1624 ir_node *node = env->irn;
1625 ir_node *src = get_CopyB_src(node);
1626 ir_node *dst = get_CopyB_dst(node);
1627 ir_node *mem = get_CopyB_mem(node);
1628 int size = get_type_size_bytes(get_CopyB_type(node));
1631 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1632 /* then we need the size explicitly in ECX. */
1633 if (size >= 16 * 4) {
1634 rem = size & 0x3; /* size % 4 */
1637 res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
1638 set_ia32_op_type(res, ia32_Const);
1639 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1641 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1642 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1645 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1646 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1647 set_ia32_immop_type(res, ia32_ImmConst);
1650 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1658 * Transforms a Mux node into CMov.
1660 * @param env The transformation environment
1661 * @return The transformed node.
1663 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1665 ir_node *node = env->irn;
1666 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1667 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1669 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1676 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *cmp_a, ir_node *cmp_b, \
1677 ir_node *psi_true, ir_node *psi_default, ir_mode *mode);
1680 * Transforms a Psi node into CMov.
1682 * @param env The transformation environment
1683 * @return The transformed node.
1685 static ir_node *gen_Psi(ia32_transform_env_t *env) {
1686 ia32_code_gen_t *cg = env->cg;
1687 dbg_info *dbg = env->dbg;
1688 ir_graph *irg = env->irg;
1689 ir_mode *mode = env->mode;
1690 ir_node *block = env->block;
1691 ir_node *node = env->irn;
1692 ir_node *cmp_proj = get_Mux_sel(node);
1693 ir_node *psi_true = get_Psi_val(node, 0);
1694 ir_node *psi_default = get_Psi_default(node);
1695 ir_node *noreg = ia32_new_NoReg_gp(cg);
1696 ir_node *nomem = new_rd_NoMem(irg);
1697 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
1700 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
1702 cmp = get_Proj_pred(cmp_proj);
1703 cmp_a = get_Cmp_left(cmp);
1704 cmp_b = get_Cmp_right(cmp);
1705 pnc = get_Proj_proj(cmp_proj);
1707 if (mode_is_float(mode)) {
1708 /* floating point psi */
1711 /* 1st case: compare operands are float too */
1713 /* psi(cmp(a, b), t, f) can be done as: */
1714 /* tmp = cmp a, b */
1715 /* tmp2 = t and tmp */
1716 /* tmp3 = f and not tmp */
1717 /* res = tmp2 or tmp3 */
1719 /* in case the compare operands are int, we move them into xmm register */
1720 if (! mode_is_float(get_irn_mode(cmp_a))) {
1721 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, node, mode_D);
1722 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, node, mode_D);
1724 pnc |= 8; /* transform integer compare to fp compare */
1727 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1728 set_ia32_pncode(new_op, pnc);
1729 set_ia32_am_support(new_op, ia32_am_Source);
1730 set_ia32_res_mode(new_op, mode);
1731 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1732 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xCmp_res);
1734 and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, psi_true, new_op, nomem);
1735 set_ia32_am_support(and1, ia32_am_Source);
1736 set_ia32_res_mode(and1, mode);
1737 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
1738 and1 = new_rd_Proj(dbg, irg, block, and1, mode, pn_ia32_xAnd_res);
1740 and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, psi_default, nomem);
1741 set_ia32_am_support(and2, ia32_am_Source);
1742 set_ia32_res_mode(and2, mode);
1743 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
1744 and2 = new_rd_Proj(dbg, irg, block, and2, mode, pn_ia32_xAndNot_res);
1746 new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
1747 set_ia32_am_support(new_op, ia32_am_Source);
1748 set_ia32_res_mode(new_op, mode);
1749 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1750 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xOr_res);
1754 new_op = new_rd_ia32_vfCMov(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1755 set_ia32_pncode(new_op, pnc);
1756 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1761 construct_binop_func *set_func = NULL;
1762 cmov_func_t *cmov_func = NULL;
1764 if (mode_is_float(get_irn_mode(cmp_a))) {
1765 /* 1st case: compare operands are floats */
1770 set_func = new_rd_ia32_xCmpSet;
1771 cmov_func = new_rd_ia32_xCmpCMov;
1775 set_func = new_rd_ia32_vfCmpSet;
1776 cmov_func = new_rd_ia32_vfCmpCMov;
1779 pnc &= 7; /* fp compare -> int compare */
1782 /* 2nd case: compare operand are integer too */
1783 set_func = new_rd_ia32_CmpSet;
1784 cmov_func = new_rd_ia32_CmpCMov;
1787 /* create the nodes */
1789 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
1790 if (is_ia32_Const_0(cmp_b) && is_Proj(cmp_a) && (is_ia32_And(get_Proj_pred(cmp_a)) || is_ia32_Or(get_Proj_pred(cmp_a)))) {
1791 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1792 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1793 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1794 set_ia32_pncode(new_op, pnc);
1796 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1797 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1798 /* we invert condition and set default to 0 */
1799 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1800 set_ia32_pncode(new_op, get_negated_pnc(pnc, mode));
1803 /* otherwise: use CMOVcc */
1804 new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, cmp_a, psi_true, psi_default, mode);
1805 set_ia32_pncode(new_op, pnc);
1808 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1812 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1813 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1814 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1815 set_ia32_pncode(get_Proj_pred(new_op), pnc);
1816 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1818 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1819 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1820 /* we invert condition and set default to 0 */
1821 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1822 set_ia32_pncode(get_Proj_pred(new_op), get_negated_pnc(pnc, mode));
1823 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1826 /* otherwise: use CMOVcc */
1827 new_op = cmov_func(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1828 set_ia32_pncode(new_op, pnc);
1829 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1839 * Following conversion rules apply:
1843 * 1) n bit -> m bit n > m (downscale)
1844 * a) target is signed: movsx
1845 * b) target is unsigned: and with lower bits sets
1846 * 2) n bit -> m bit n == m (sign change)
1848 * 3) n bit -> m bit n < m (upscale)
1849 * a) source is signed: movsx
1850 * b) source is unsigned: and with lower bits sets
1854 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1858 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1859 * if target mode < 32bit: additional INT -> INT conversion (see above)
1863 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1864 * x87 is mode_E internally, conversions happen only at load and store
1865 * in non-strict semantic
1869 * Create a conversion from x87 state register to general purpose.
1871 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1872 ia32_code_gen_t *cg = env->cg;
1873 entity *ent = cg->fp_to_gp;
1874 ir_graph *irg = env->irg;
1875 ir_node *block = env->block;
1876 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1877 ir_node *op = get_Conv_op(env->irn);
1878 ir_node *fist, *mem, *load;
1881 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1882 ent = cg->fp_to_gp =
1883 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1887 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
1889 set_ia32_frame_ent(fist, ent);
1890 set_ia32_use_frame(fist);
1891 set_ia32_am_support(fist, ia32_am_Dest);
1892 set_ia32_op_type(fist, ia32_AddrModeD);
1893 set_ia32_am_flavour(fist, ia32_B);
1894 set_ia32_ls_mode(fist, mode_E);
1896 mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
1899 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1901 set_ia32_frame_ent(load, ent);
1902 set_ia32_use_frame(load);
1903 set_ia32_am_support(load, ia32_am_Source);
1904 set_ia32_op_type(load, ia32_AddrModeS);
1905 set_ia32_am_flavour(load, ia32_B);
1906 set_ia32_ls_mode(load, tgt_mode);
1908 return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
1912 * Create a conversion from x87 state register to general purpose.
1914 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1915 ia32_code_gen_t *cg = env->cg;
1916 entity *ent = cg->gp_to_fp;
1917 ir_graph *irg = env->irg;
1918 ir_node *block = env->block;
1919 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1920 ir_node *nomem = get_irg_no_mem(irg);
1921 ir_node *op = get_Conv_op(env->irn);
1922 ir_node *fild, *store, *mem;
1926 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
1927 ent = cg->gp_to_fp =
1928 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
1931 /* first convert to 32 bit */
1932 src_bits = get_mode_size_bits(src_mode);
1933 if (src_bits == 8) {
1934 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
1935 op = new_r_Proj(irg, block, op, mode_Is, 0);
1937 else if (src_bits < 32) {
1938 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
1939 op = new_r_Proj(irg, block, op, mode_Is, 0);
1943 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
1945 set_ia32_frame_ent(store, ent);
1946 set_ia32_use_frame(store);
1948 set_ia32_am_support(store, ia32_am_Dest);
1949 set_ia32_op_type(store, ia32_AddrModeD);
1950 set_ia32_am_flavour(store, ia32_B);
1951 set_ia32_ls_mode(store, mode_Is);
1953 mem = new_r_Proj(irg, block, store, mode_M, 0);
1956 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1958 set_ia32_frame_ent(fild, ent);
1959 set_ia32_use_frame(fild);
1960 set_ia32_am_support(fild, ia32_am_Source);
1961 set_ia32_op_type(fild, ia32_AddrModeS);
1962 set_ia32_am_flavour(fild, ia32_B);
1963 set_ia32_ls_mode(fild, mode_E);
1965 return new_r_Proj(irg, block, fild, mode_E, 0);
1969 * Transforms a Conv node.
1971 * @param env The transformation environment
1972 * @return The created ia32 Conv node
1974 static ir_node *gen_Conv(ia32_transform_env_t *env) {
1975 dbg_info *dbg = env->dbg;
1976 ir_graph *irg = env->irg;
1977 ir_node *op = get_Conv_op(env->irn);
1978 ir_mode *src_mode = get_irn_mode(op);
1979 ir_mode *tgt_mode = env->mode;
1980 int src_bits = get_mode_size_bits(src_mode);
1981 int tgt_bits = get_mode_size_bits(tgt_mode);
1983 ir_node *block = env->block;
1984 ir_node *new_op = NULL;
1985 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1986 ir_node *nomem = new_rd_NoMem(irg);
1988 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1990 if (src_mode == tgt_mode) {
1991 /* this can happen when changing mode_P to mode_Is */
1992 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1993 edges_reroute(env->irn, op, irg);
1995 else if (mode_is_float(src_mode)) {
1996 /* we convert from float ... */
1997 if (mode_is_float(tgt_mode)) {
1999 if (USE_SSE2(env->cg)) {
2000 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
2001 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
2002 pn = pn_ia32_Conv_FP2FP_res;
2005 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
2006 edges_reroute(env->irn, op, irg);
2011 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
2012 if (USE_SSE2(env->cg)) {
2013 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
2014 pn = pn_ia32_Conv_FP2I_res;
2017 return gen_x87_fp_to_gp(env, tgt_mode);
2019 /* if target mode is not int: add an additional downscale convert */
2020 if (tgt_bits < 32) {
2021 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2022 set_ia32_am_support(new_op, ia32_am_Source);
2023 set_ia32_tgt_mode(new_op, tgt_mode);
2024 set_ia32_src_mode(new_op, src_mode);
2026 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, pn_ia32_Conv_FP2I_res);
2028 if (tgt_bits == 8 || src_bits == 8) {
2029 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
2030 pn = pn_ia32_Conv_I2I8Bit_res;
2033 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
2034 pn = pn_ia32_Conv_I2I_res;
2040 /* we convert from int ... */
2041 if (mode_is_float(tgt_mode)) {
2044 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
2045 if (USE_SSE2(env->cg)) {
2046 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
2047 pn = pn_ia32_Conv_I2FP_res;
2050 return gen_x87_gp_to_fp(env, src_mode);
2054 if (get_mode_size_bits(src_mode) == tgt_bits) {
2055 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
2056 edges_reroute(env->irn, op, irg);
2059 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2060 if (tgt_bits == 8 || src_bits == 8) {
2061 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
2062 pn = pn_ia32_Conv_I2I8Bit_res;
2065 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
2066 pn = pn_ia32_Conv_I2I_res;
2073 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2074 set_ia32_tgt_mode(new_op, tgt_mode);
2075 set_ia32_src_mode(new_op, src_mode);
2077 set_ia32_am_support(new_op, ia32_am_Source);
2079 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, pn);
2087 /********************************************
2090 * | |__ ___ _ __ ___ __| | ___ ___
2091 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2092 * | |_) | __/ | | | (_) | (_| | __/\__ \
2093 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2095 ********************************************/
2098 * Decides in which block the transformed StackParam should be placed.
2099 * If the StackParam has more than one user, the dominator block of
2100 * the users will be returned. In case of only one user, this is either
2101 * the user block or, in case of a Phi, the predecessor block of the Phi.
2103 static ir_node *get_block_transformed_stack_param(ir_node *irn) {
2104 ir_node *dom_bl = NULL;
2106 if (get_irn_n_edges(irn) == 1) {
2107 ir_node *src = get_edge_src_irn(get_irn_out_edge_first(irn));
2109 if (! is_Phi(src)) {
2110 dom_bl = get_nodes_block(src);
2113 /* Determine on which in position of the Phi the irn is */
2114 /* and get the corresponding cfg predecessor block. */
2116 int i = get_irn_pred_pos(src, irn);
2117 assert(i >= 0 && "kaputt");
2118 dom_bl = get_Block_cfgpred_block(get_nodes_block(src), i);
2122 dom_bl = node_users_smallest_common_dominator(irn, 1);
2125 assert(dom_bl && "dominator block not found");
2130 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
2131 ir_node *new_op = NULL;
2132 ir_node *node = env->irn;
2133 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2134 ir_node *mem = new_rd_NoMem(env->irg);
2135 ir_node *ptr = get_irn_n(node, 0);
2136 entity *ent = be_get_frame_entity(node);
2137 ir_mode *mode = env->mode;
2139 /* choose the block where to place the load */
2140 env->block = get_block_transformed_stack_param(node);
2142 if (mode_is_float(mode)) {
2144 if (USE_SSE2(env->cg))
2145 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2147 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2150 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2153 set_ia32_frame_ent(new_op, ent);
2154 set_ia32_use_frame(new_op);
2156 set_ia32_am_support(new_op, ia32_am_Source);
2157 set_ia32_op_type(new_op, ia32_AddrModeS);
2158 set_ia32_am_flavour(new_op, ia32_B);
2159 set_ia32_ls_mode(new_op, mode);
2161 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2163 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
2167 * Transforms a FrameAddr into an ia32 Add.
2169 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
2170 ir_node *new_op = NULL;
2171 ir_node *node = env->irn;
2172 ir_node *op = get_irn_n(node, 0);
2173 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2174 ir_node *nomem = new_rd_NoMem(env->irg);
2176 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
2177 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
2178 set_ia32_am_support(new_op, ia32_am_Full);
2179 set_ia32_use_frame(new_op);
2180 set_ia32_immop_type(new_op, ia32_ImmConst);
2181 set_ia32_commutative(new_op);
2183 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2185 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
2189 * Transforms a FrameLoad into an ia32 Load.
2191 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
2192 ir_node *new_op = NULL;
2193 ir_node *node = env->irn;
2194 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2195 ir_node *mem = get_irn_n(node, 0);
2196 ir_node *ptr = get_irn_n(node, 1);
2197 entity *ent = be_get_frame_entity(node);
2198 ir_mode *mode = get_type_mode(get_entity_type(ent));
2200 if (mode_is_float(mode)) {
2202 if (USE_SSE2(env->cg))
2203 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2205 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2208 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2210 set_ia32_frame_ent(new_op, ent);
2211 set_ia32_use_frame(new_op);
2213 set_ia32_am_support(new_op, ia32_am_Source);
2214 set_ia32_op_type(new_op, ia32_AddrModeS);
2215 set_ia32_am_flavour(new_op, ia32_B);
2216 set_ia32_ls_mode(new_op, mode);
2218 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2225 * Transforms a FrameStore into an ia32 Store.
2227 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
2228 ir_node *new_op = NULL;
2229 ir_node *node = env->irn;
2230 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2231 ir_node *mem = get_irn_n(node, 0);
2232 ir_node *ptr = get_irn_n(node, 1);
2233 ir_node *val = get_irn_n(node, 2);
2234 entity *ent = be_get_frame_entity(node);
2235 ir_mode *mode = get_irn_mode(val);
2237 if (mode_is_float(mode)) {
2239 if (USE_SSE2(env->cg))
2240 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2242 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2244 else if (get_mode_size_bits(mode) == 8) {
2245 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2248 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2251 set_ia32_frame_ent(new_op, ent);
2252 set_ia32_use_frame(new_op);
2254 set_ia32_am_support(new_op, ia32_am_Dest);
2255 set_ia32_op_type(new_op, ia32_AddrModeD);
2256 set_ia32_am_flavour(new_op, ia32_B);
2257 set_ia32_ls_mode(new_op, mode);
2259 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2265 * This function just sets the register for the Unknown node
2266 * as this is not done during register allocation because Unknown
2267 * is an "ignore" node.
2269 static ir_node *gen_Unknown(ia32_transform_env_t *env) {
2270 ir_mode *mode = env->mode;
2271 ir_node *irn = env->irn;
2273 if (mode_is_float(mode)) {
2274 if (USE_SSE2(env->cg))
2275 arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
2277 arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
2279 else if (mode_is_int(mode) || mode_is_reference(mode)) {
2280 arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
2283 assert(0 && "unsupported Unknown-Mode");
2290 /*********************************************************
2293 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
2294 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
2295 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
2296 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
2298 *********************************************************/
2301 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
2302 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2304 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
2305 ia32_transform_env_t tenv;
2306 ir_node *in1, *in2, *noreg, *nomem, *res;
2307 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
2309 /* Return if AM node or not a Sub or xSub */
2310 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_xSub(irn)))
2313 noreg = ia32_new_NoReg_gp(cg);
2314 nomem = new_rd_NoMem(cg->irg);
2315 in1 = get_irn_n(irn, 2);
2316 in2 = get_irn_n(irn, 3);
2317 in1_reg = arch_get_irn_register(cg->arch_env, in1);
2318 in2_reg = arch_get_irn_register(cg->arch_env, in2);
2319 out_reg = get_ia32_out_reg(irn, 0);
2321 tenv.block = get_nodes_block(irn);
2322 tenv.dbg = get_irn_dbg_info(irn);
2325 tenv.mode = get_ia32_res_mode(irn);
2327 DEBUG_ONLY(tenv.mod = cg->mod;)
2329 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
2330 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
2331 /* generate the neg src2 */
2332 res = gen_Minus_ex(&tenv, in2);
2333 arch_set_irn_register(cg->arch_env, res, in2_reg);
2335 /* add to schedule */
2336 sched_add_before(irn, res);
2338 /* generate the add */
2339 if (mode_is_float(tenv.mode)) {
2340 res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2341 set_ia32_am_support(res, ia32_am_Source);
2344 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2345 set_ia32_am_support(res, ia32_am_Full);
2346 set_ia32_commutative(res);
2348 set_ia32_res_mode(res, tenv.mode);
2350 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
2352 slots = get_ia32_slots(res);
2355 /* add to schedule */
2356 sched_add_before(irn, res);
2358 /* remove the old sub */
2361 DBG_OPT_SUB2NEGADD(irn, res);
2363 /* exchange the add and the sub */
2369 * Transforms a LEA into an Add if possible
2370 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2372 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
2373 ia32_am_flavour_t am_flav;
2375 ir_node *res = NULL;
2376 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
2378 ia32_transform_env_t tenv;
2379 const arch_register_t *out_reg, *base_reg, *index_reg;
2382 if (! is_ia32_Lea(irn))
2385 am_flav = get_ia32_am_flavour(irn);
2387 /* only some LEAs can be transformed to an Add */
2388 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
2391 noreg = ia32_new_NoReg_gp(cg);
2392 nomem = new_rd_NoMem(cg->irg);
2395 base = get_irn_n(irn, 0);
2396 index = get_irn_n(irn,1);
2398 offs = get_ia32_am_offs(irn);
2400 /* offset has a explicit sign -> we need to skip + */
2401 if (offs && offs[0] == '+')
2404 out_reg = arch_get_irn_register(cg->arch_env, irn);
2405 base_reg = arch_get_irn_register(cg->arch_env, base);
2406 index_reg = arch_get_irn_register(cg->arch_env, index);
2408 tenv.block = get_nodes_block(irn);
2409 tenv.dbg = get_irn_dbg_info(irn);
2412 DEBUG_ONLY(tenv.mod = cg->mod;)
2413 tenv.mode = get_irn_mode(irn);
2416 switch(get_ia32_am_flavour(irn)) {
2418 /* out register must be same as base register */
2419 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2425 /* out register must be same as base register */
2426 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2433 /* out register must be same as index register */
2434 if (! REGS_ARE_EQUAL(out_reg, index_reg))
2441 /* out register must be same as one in register */
2442 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
2446 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
2451 /* in registers a different from out -> no Add possible */
2458 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
2459 arch_set_irn_register(cg->arch_env, res, out_reg);
2460 set_ia32_op_type(res, ia32_Normal);
2461 set_ia32_commutative(res);
2462 set_ia32_res_mode(res, tenv.mode);
2465 set_ia32_cnst(res, offs);
2466 set_ia32_immop_type(res, ia32_ImmConst);
2469 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
2471 /* add Add to schedule */
2472 sched_add_before(irn, res);
2474 DBG_OPT_LEA2ADD(irn, res);
2476 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, pn_ia32_Add_res);
2478 /* add result Proj to schedule */
2479 sched_add_before(irn, res);
2481 /* remove the old LEA */
2484 /* exchange the Add and the LEA */
2489 * the BAD transformer.
2491 static ir_node *bad_transform(ia32_transform_env_t *env) {
2492 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2498 * Enters all transform functions into the generic pointer
2500 void ia32_register_transformers(void) {
2501 ir_op *op_Max, *op_Min, *op_Mulh;
2503 /* first clear the generic function pointer for all ops */
2504 clear_irp_opcodes_generic_func();
2506 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2507 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
2558 /* constant transformation happens earlier */
2582 /* set the register for all Unknown nodes */
2585 op_Max = get_op_Max();
2588 op_Min = get_op_Min();
2591 op_Mulh = get_op_Mulh();
2600 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
2603 * Transforms the given firm node (and maybe some other related nodes)
2604 * into one or more assembler nodes.
2606 * @param node the firm node
2607 * @param env the debug module
2609 void ia32_transform_node(ir_node *node, void *env) {
2610 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2611 ir_op *op = get_irn_op(node);
2612 ir_node *asm_node = NULL;
2618 /* link arguments pointing to Unknown to the UNKNOWN Proj */
2619 for (i = get_irn_arity(node) - 1; i >= 0; i--) {
2620 if (is_Unknown(get_irn_n(node, i)))
2621 set_irn_n(node, i, be_get_unknown_for_mode(cg, get_irn_mode(get_irn_n(node, i))));
2624 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
2625 if (op->ops.generic) {
2626 ia32_transform_env_t tenv;
2627 transform_func *transform = (transform_func *)op->ops.generic;
2629 tenv.block = get_nodes_block(node);
2630 tenv.dbg = get_irn_dbg_info(node);
2631 tenv.irg = current_ir_graph;
2633 tenv.mode = get_irn_mode(node);
2635 DEBUG_ONLY(tenv.mod = cg->mod;)
2637 asm_node = (*transform)(&tenv);
2640 /* exchange nodes if a new one was generated */
2642 exchange(node, asm_node);
2643 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2646 DB((cg->mod, LEVEL_1, "ignored\n"));
2651 * Transforms a psi condition.
2653 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
2656 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
2657 set_irn_mode(cond, mode);
2659 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
2660 ir_node *in = get_irn_n(cond, i);
2662 /* if in is a compare: transform into Set/xCmp */
2664 ir_node *new_op = NULL;
2665 ir_node *cmp = get_Proj_pred(in);
2666 ir_node *cmp_a = get_Cmp_left(cmp);
2667 ir_node *cmp_b = get_Cmp_right(cmp);
2668 dbg_info *dbg = get_irn_dbg_info(cmp);
2669 ir_graph *irg = get_irn_irg(cmp);
2670 ir_node *block = get_nodes_block(cmp);
2671 ir_node *noreg = ia32_new_NoReg_gp(cg);
2672 ir_node *nomem = new_rd_NoMem(irg);
2673 int pnc = get_Proj_proj(in);
2675 /* this is a compare */
2676 if (mode_is_float(mode)) {
2677 /* Psi is float, we need a floating point compare */
2681 if (! mode_is_float(get_irn_mode(cmp_a))) {
2682 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
2683 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
2687 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
2688 set_ia32_pncode(new_op, pnc);
2689 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
2698 ia32_transform_env_t tenv;
2699 construct_binop_func *set_func = NULL;
2701 if (mode_is_float(get_irn_mode(cmp_a))) {
2702 /* 1st case: compare operands are floats */
2707 set_func = new_rd_ia32_xCmpSet;
2711 set_func = new_rd_ia32_vfCmpSet;
2714 pnc &= 7; /* fp compare -> int compare */
2717 /* 2nd case: compare operand are integer too */
2718 set_func = new_rd_ia32_CmpSet;
2729 new_op = gen_binop(&tenv, cmp_a, cmp_b, set_func);
2730 set_ia32_pncode(get_Proj_pred(new_op), pnc);
2731 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
2734 /* exchange with old compare */
2735 exchange(in, new_op);
2738 /* another complex condition */
2739 transform_psi_cond(in, mode, cg);
2745 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
2746 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
2747 * compare, which causes the compare result to be stores in a register. The
2748 * "And"s and "Or"s are transformed later, we just have to set their mode right.
2750 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
2751 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2752 ir_node *psi_sel, *new_cmp, *block;
2757 if (get_irn_opcode(node) != iro_Psi)
2760 psi_sel = get_Psi_cond(node, 0);
2762 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
2763 if (is_Proj(psi_sel))
2766 mode = get_irn_mode(node);
2768 transform_psi_cond(psi_sel, mode, cg);
2770 irg = get_irn_irg(node);
2771 block = get_nodes_block(node);
2773 /* we need to compare the evaluated condition tree with 0 */
2775 /* BEWARE: new_r_Const_long works for floating point as well */
2776 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
2777 /* transform the const */
2778 ia32_place_consts_set_modes(new_cmp, cg);
2779 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne + (mode_is_float(mode) ? pn_Cmp_Uo : 0));
2781 set_Psi_cond(node, 0, new_cmp);