2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
15 #include "irgraph_t.h"
20 #include "iredges_t.h"
28 #include "archop.h" /* we need this for Min and Max nodes */
30 #include "../benode_t.h"
31 #include "../besched.h"
34 #include "bearch_ia32_t.h"
35 #include "ia32_nodes_attr.h"
36 #include "ia32_transform.h"
37 #include "ia32_new_nodes.h"
38 #include "ia32_map_regs.h"
39 #include "ia32_dbg_stat.h"
40 #include "ia32_optimize.h"
42 #include "gen_ia32_regalloc_if.h"
44 #define SFP_SIGN "0x80000000"
45 #define DFP_SIGN "0x8000000000000000"
46 #define SFP_ABS "0x7FFFFFFF"
47 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
49 #define TP_SFP_SIGN "ia32_sfp_sign"
50 #define TP_DFP_SIGN "ia32_dfp_sign"
51 #define TP_SFP_ABS "ia32_sfp_abs"
52 #define TP_DFP_ABS "ia32_dfp_abs"
54 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
55 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
56 #define ENT_SFP_ABS "IA32_SFP_ABS"
57 #define ENT_DFP_ABS "IA32_DFP_ABS"
59 extern ir_op *get_op_Mulh(void);
61 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
62 ir_node *op1, ir_node *op2, ir_node *mem);
64 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
65 ir_node *op, ir_node *mem);
68 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
71 /****************************************************************************************************
73 * | | | | / _| | | (_)
74 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
75 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
76 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
77 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
79 ****************************************************************************************************/
82 * Returns 1 if irn is a Const representing 0, 0 otherwise
84 static INLINE int is_ia32_Const_0(ir_node *irn) {
85 return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
89 * Returns 1 if irn is a Const representing 1, 0 otherwise
91 static INLINE int is_ia32_Const_1(ir_node *irn) {
92 return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
96 * Returns the Proj representing the UNKNOWN register for given mode.
98 static ir_node *be_get_unknown_for_mode(ia32_code_gen_t *cg, ir_mode *mode) {
99 be_abi_irg_t *babi = cg->birg->abi;
100 const arch_register_t *unknwn_reg = NULL;
102 if (mode_is_float(mode)) {
103 unknwn_reg = USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_UKNWN] : &ia32_vfp_regs[REG_VFP_UKNWN];
106 unknwn_reg = &ia32_gp_regs[REG_GP_UKNWN];
109 return be_abi_get_callee_save_irn(babi, unknwn_reg);
113 * Gets the Proj with number pn from irn.
115 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
116 const ir_edge_t *edge;
118 assert(get_irn_mode(irn) == mode_T && "need mode_T");
120 foreach_out_edge(irn, edge) {
121 proj = get_edge_src_irn(edge);
123 if (get_Proj_proj(proj) == pn)
131 * SSE convert of an integer node into a floating point node.
133 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block,
134 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
136 ir_node *noreg = ia32_new_NoReg_gp(cg);
137 ir_node *nomem = new_rd_NoMem(irg);
139 ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
140 set_ia32_src_mode(conv, get_irn_mode(in));
141 set_ia32_tgt_mode(conv, tgt_mode);
142 set_ia32_am_support(conv, ia32_am_Source);
143 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
145 return new_rd_Proj(dbg, irg, block, conv, tgt_mode, pn_ia32_Conv_I2FP_res);
148 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
149 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
150 static const struct {
152 const char *ent_name;
153 const char *cnst_str;
154 } names [ia32_known_const_max] = {
155 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
156 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
157 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
158 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
160 static struct entity *ent_cache[ia32_known_const_max];
162 const char *tp_name, *ent_name, *cnst_str;
169 ent_name = names[kct].ent_name;
170 if (! ent_cache[kct]) {
171 tp_name = names[kct].tp_name;
172 cnst_str = names[kct].cnst_str;
174 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
175 tp = new_type_primitive(new_id_from_str(tp_name), mode);
176 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
178 set_entity_ld_ident(ent, get_entity_ident(ent));
179 set_entity_visibility(ent, visibility_local);
180 set_entity_variability(ent, variability_constant);
181 set_entity_allocation(ent, allocation_static);
183 /* we create a new entity here: It's initialization must resist on the
185 rem = current_ir_graph;
186 current_ir_graph = get_const_code_irg();
187 cnst = new_Const(mode, tv);
188 current_ir_graph = rem;
190 set_atomic_ent_value(ent, cnst);
192 /* cache the entry */
193 ent_cache[kct] = ent;
196 return get_entity_ident(ent_cache[kct]);
201 * Prints the old node name on cg obst and returns a pointer to it.
203 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
204 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
206 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
207 obstack_1grow(isa->name_obst, 0);
208 isa->name_obst_size += obstack_object_size(isa->name_obst);
209 return obstack_finish(isa->name_obst);
213 /* determine if one operator is an Imm */
214 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
216 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
217 else return is_ia32_Cnst(op2) ? op2 : NULL;
220 /* determine if one operator is not an Imm */
221 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
222 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
227 * Construct a standard binary operation, set AM and immediate if required.
229 * @param env The transformation environment
230 * @param op1 The first operand
231 * @param op2 The second operand
232 * @param func The node constructor function
233 * @return The constructed ia32 node.
235 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
236 ir_node *new_op = NULL;
237 ir_mode *mode = env->mode;
238 dbg_info *dbg = env->dbg;
239 ir_graph *irg = env->irg;
240 ir_node *block = env->block;
241 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
242 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
243 ir_node *nomem = new_NoMem();
244 ir_node *expr_op, *imm_op;
245 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
247 /* Check if immediate optimization is on and */
248 /* if it's an operation with immediate. */
249 if (! (env->cg->opt & IA32_OPT_IMMOPS)) {
253 else if (is_op_commutative(get_irn_op(env->irn))) {
254 imm_op = get_immediate_op(op1, op2);
255 expr_op = get_expr_op(op1, op2);
258 imm_op = get_immediate_op(NULL, op2);
259 expr_op = get_expr_op(op1, op2);
262 assert((expr_op || imm_op) && "invalid operands");
265 /* We have two consts here: not yet supported */
269 if (mode_is_float(mode)) {
270 /* floating point operations */
272 DB((mod, LEVEL_1, "FP with immediate ..."));
273 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
274 set_ia32_Immop_attr(new_op, imm_op);
275 set_ia32_am_support(new_op, ia32_am_None);
278 DB((mod, LEVEL_1, "FP binop ..."));
279 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
280 set_ia32_am_support(new_op, ia32_am_Source);
282 set_ia32_ls_mode(new_op, mode);
285 /* integer operations */
287 /* This is expr + const */
288 DB((mod, LEVEL_1, "INT with immediate ..."));
289 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
290 set_ia32_Immop_attr(new_op, imm_op);
293 set_ia32_am_support(new_op, ia32_am_Dest);
296 DB((mod, LEVEL_1, "INT binop ..."));
297 /* This is a normal operation */
298 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
301 set_ia32_am_support(new_op, ia32_am_Full);
305 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
307 set_ia32_res_mode(new_op, mode);
309 if (is_op_commutative(get_irn_op(env->irn))) {
310 set_ia32_commutative(new_op);
313 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
319 * Construct a shift/rotate binary operation, sets AM and immediate if required.
321 * @param env The transformation environment
322 * @param op1 The first operand
323 * @param op2 The second operand
324 * @param func The node constructor function
325 * @return The constructed ia32 node.
327 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
328 ir_node *new_op = NULL;
329 ir_mode *mode = env->mode;
330 dbg_info *dbg = env->dbg;
331 ir_graph *irg = env->irg;
332 ir_node *block = env->block;
333 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
334 ir_node *nomem = new_NoMem();
335 ir_node *expr_op, *imm_op;
337 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
339 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
341 /* Check if immediate optimization is on and */
342 /* if it's an operation with immediate. */
343 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
344 expr_op = get_expr_op(op1, op2);
346 assert((expr_op || imm_op) && "invalid operands");
349 /* We have two consts here: not yet supported */
353 /* Limit imm_op within range imm8 */
355 tv = get_ia32_Immop_tarval(imm_op);
358 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
365 /* integer operations */
367 /* This is shift/rot with const */
368 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
370 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
371 set_ia32_Immop_attr(new_op, imm_op);
374 /* This is a normal shift/rot */
375 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
376 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
380 set_ia32_am_support(new_op, ia32_am_Dest);
382 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
384 set_ia32_res_mode(new_op, mode);
385 set_ia32_emit_cl(new_op);
387 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
392 * Construct a standard unary operation, set AM and immediate if required.
394 * @param env The transformation environment
395 * @param op The operand
396 * @param func The node constructor function
397 * @return The constructed ia32 node.
399 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
400 ir_node *new_op = NULL;
401 ir_mode *mode = env->mode;
402 dbg_info *dbg = env->dbg;
403 ir_graph *irg = env->irg;
404 ir_node *block = env->block;
405 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
406 ir_node *nomem = new_NoMem();
407 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
409 new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
411 if (mode_is_float(mode)) {
412 DB((mod, LEVEL_1, "FP unop ..."));
413 /* floating point operations don't support implicit store */
414 set_ia32_am_support(new_op, ia32_am_None);
417 DB((mod, LEVEL_1, "INT unop ..."));
418 set_ia32_am_support(new_op, ia32_am_Dest);
421 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
423 set_ia32_res_mode(new_op, mode);
425 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
431 * Creates an ia32 Add with immediate.
433 * @param env The transformation environment
434 * @param expr_op The expression operator
435 * @param const_op The constant
436 * @return the created ia32 Add node
438 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
439 ir_node *new_op = NULL;
440 tarval *tv = get_ia32_Immop_tarval(const_op);
441 dbg_info *dbg = env->dbg;
442 ir_graph *irg = env->irg;
443 ir_node *block = env->block;
444 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
445 ir_node *nomem = new_NoMem();
447 tarval_classification_t class_tv, class_negtv;
448 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
450 /* try to optimize to inc/dec */
451 if ((env->cg->opt & IA32_OPT_INCDEC) && (get_ia32_op_type(const_op) == ia32_Const)) {
452 /* optimize tarvals */
453 class_tv = classify_tarval(tv);
454 class_negtv = classify_tarval(tarval_neg(tv));
456 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
457 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
458 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
461 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
462 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
463 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
469 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
470 set_ia32_Immop_attr(new_op, const_op);
471 set_ia32_commutative(new_op);
478 * Creates an ia32 Add.
480 * @param env The transformation environment
481 * @return the created ia32 Add node
483 static ir_node *gen_Add(ia32_transform_env_t *env) {
484 ir_node *new_op = NULL;
485 dbg_info *dbg = env->dbg;
486 ir_mode *mode = env->mode;
487 ir_graph *irg = env->irg;
488 ir_node *block = env->block;
489 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
490 ir_node *nomem = new_NoMem();
491 ir_node *expr_op, *imm_op;
492 ir_node *op1 = get_Add_left(env->irn);
493 ir_node *op2 = get_Add_right(env->irn);
495 /* Check if immediate optimization is on and */
496 /* if it's an operation with immediate. */
497 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
498 expr_op = get_expr_op(op1, op2);
500 assert((expr_op || imm_op) && "invalid operands");
502 if (mode_is_float(mode)) {
504 if (USE_SSE2(env->cg))
505 return gen_binop(env, op1, op2, new_rd_ia32_xAdd);
507 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
512 /* No expr_op means, that we have two const - one symconst and */
513 /* one tarval or another symconst - because this case is not */
514 /* covered by constant folding */
515 /* We need to check for: */
516 /* 1) symconst + const -> becomes a LEA */
517 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
518 /* linker doesn't support two symconsts */
520 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
521 /* this is the 2nd case */
522 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
523 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
524 set_ia32_am_flavour(new_op, ia32_am_OB);
526 DBG_OPT_LEA1(op2, new_op);
529 /* this is the 1st case */
530 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
532 DBG_OPT_LEA2(op1, op2, new_op);
534 if (get_ia32_op_type(op1) == ia32_SymConst) {
535 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
536 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
539 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
540 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
542 set_ia32_am_flavour(new_op, ia32_am_O);
546 set_ia32_am_support(new_op, ia32_am_Source);
547 set_ia32_op_type(new_op, ia32_AddrModeS);
549 /* Lea doesn't need a Proj */
553 /* This is expr + const */
554 new_op = gen_imm_Add(env, expr_op, imm_op);
557 set_ia32_am_support(new_op, ia32_am_Dest);
560 /* This is a normal add */
561 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
564 set_ia32_am_support(new_op, ia32_am_Full);
565 set_ia32_commutative(new_op);
569 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
571 set_ia32_res_mode(new_op, mode);
573 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Add_res);
577 * Transforms an ia32_l_AddC (created in intrinsic lowering) into a "real" AddC
579 * @param env The transformation environment
580 * @return the created ia32 Add node
582 static ir_node *gen_ia32_l_AddC(ia32_transform_env_t *env) {
583 return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_AddC);
587 * Transforms an ia32_l_Add (created in intrinsic lowering) into a "real" Add
589 * @param env The transformation environment
590 * @return the created ia32 Add node
592 static ir_node *gen_ia32_l_Add(ia32_transform_env_t *env) {
593 return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_Add);
599 * Creates an ia32 Mul.
601 * @param env The transformation environment
602 * @return the created ia32 Mul node
604 static ir_node *gen_Mul(ia32_transform_env_t *env) {
605 ir_node *op1 = get_Mul_left(env->irn);
606 ir_node *op2 = get_Mul_right(env->irn);
609 if (mode_is_float(env->mode)) {
611 if (USE_SSE2(env->cg))
612 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMul);
614 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
617 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
626 * Creates an ia32 Mulh.
627 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
628 * this result while Mul returns the lower 32 bit.
630 * @param env The transformation environment
631 * @return the created ia32 Mulh node
633 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
634 ir_node *op1 = get_irn_n(env->irn, 0);
635 ir_node *op2 = get_irn_n(env->irn, 1);
636 ir_node *proj_EAX, *proj_EDX, *mulh;
639 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
640 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
641 mulh = get_Proj_pred(proj_EAX);
642 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
644 /* to be on the save side */
645 set_Proj_proj(proj_EAX, pn_EAX);
647 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
648 /* Mulh with const cannot have AM */
649 set_ia32_am_support(mulh, ia32_am_None);
652 /* Mulh cannot have AM for destination */
653 set_ia32_am_support(mulh, ia32_am_Source);
659 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
667 * Creates an ia32 And.
669 * @param env The transformation environment
670 * @return The created ia32 And node
672 static ir_node *gen_And(ia32_transform_env_t *env) {
673 ir_node *op1 = get_And_left(env->irn);
674 ir_node *op2 = get_And_right(env->irn);
676 assert (! mode_is_float(env->mode));
677 return gen_binop(env, op1, op2, new_rd_ia32_And);
683 * Creates an ia32 Or.
685 * @param env The transformation environment
686 * @return The created ia32 Or node
688 static ir_node *gen_Or(ia32_transform_env_t *env) {
689 ir_node *op1 = get_Or_left(env->irn);
690 ir_node *op2 = get_Or_right(env->irn);
692 assert (! mode_is_float(env->mode));
693 return gen_binop(env, op1, op2, new_rd_ia32_Or);
699 * Creates an ia32 Eor.
701 * @param env The transformation environment
702 * @return The created ia32 Eor node
704 static ir_node *gen_Eor(ia32_transform_env_t *env) {
705 ir_node *op1 = get_Eor_left(env->irn);
706 ir_node *op2 = get_Eor_right(env->irn);
708 assert(! mode_is_float(env->mode));
709 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
715 * Creates an ia32 Max.
717 * @param env The transformation environment
718 * @return the created ia32 Max node
720 static ir_node *gen_Max(ia32_transform_env_t *env) {
721 ir_node *op1 = get_irn_n(env->irn, 0);
722 ir_node *op2 = get_irn_n(env->irn, 1);
725 if (mode_is_float(env->mode)) {
727 if (USE_SSE2(env->cg))
728 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMax);
734 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
735 set_ia32_am_support(new_op, ia32_am_None);
736 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
745 * Creates an ia32 Min.
747 * @param env The transformation environment
748 * @return the created ia32 Min node
750 static ir_node *gen_Min(ia32_transform_env_t *env) {
751 ir_node *op1 = get_irn_n(env->irn, 0);
752 ir_node *op2 = get_irn_n(env->irn, 1);
755 if (mode_is_float(env->mode)) {
757 if (USE_SSE2(env->cg))
758 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMin);
764 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
765 set_ia32_am_support(new_op, ia32_am_None);
766 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
775 * Creates an ia32 Sub with immediate.
777 * @param env The transformation environment
778 * @param expr_op The first operator
779 * @param const_op The constant operator
780 * @return The created ia32 Sub node
782 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
783 ir_node *new_op = NULL;
784 tarval *tv = get_ia32_Immop_tarval(const_op);
785 dbg_info *dbg = env->dbg;
786 ir_graph *irg = env->irg;
787 ir_node *block = env->block;
788 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
789 ir_node *nomem = new_NoMem();
791 tarval_classification_t class_tv, class_negtv;
792 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
794 /* try to optimize to inc/dec */
795 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
796 /* optimize tarvals */
797 class_tv = classify_tarval(tv);
798 class_negtv = classify_tarval(tarval_neg(tv));
800 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
801 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
802 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
805 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
806 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
807 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
813 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
814 set_ia32_Immop_attr(new_op, const_op);
821 * Creates an ia32 Sub.
823 * @param env The transformation environment
824 * @return The created ia32 Sub node
826 static ir_node *gen_Sub(ia32_transform_env_t *env) {
827 ir_node *new_op = NULL;
828 dbg_info *dbg = env->dbg;
829 ir_mode *mode = env->mode;
830 ir_graph *irg = env->irg;
831 ir_node *block = env->block;
832 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
833 ir_node *nomem = new_NoMem();
834 ir_node *op1 = get_Sub_left(env->irn);
835 ir_node *op2 = get_Sub_right(env->irn);
836 ir_node *expr_op, *imm_op;
838 /* Check if immediate optimization is on and */
839 /* if it's an operation with immediate. */
840 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
841 expr_op = get_expr_op(op1, op2);
843 assert((expr_op || imm_op) && "invalid operands");
845 if (mode_is_float(mode)) {
847 if (USE_SSE2(env->cg))
848 return gen_binop(env, op1, op2, new_rd_ia32_xSub);
850 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
855 /* No expr_op means, that we have two const - one symconst and */
856 /* one tarval or another symconst - because this case is not */
857 /* covered by constant folding */
858 /* We need to check for: */
859 /* 1) symconst + const -> becomes a LEA */
860 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
861 /* linker doesn't support two symconsts */
863 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
864 /* this is the 2nd case */
865 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
866 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
867 set_ia32_am_sc_sign(new_op);
868 set_ia32_am_flavour(new_op, ia32_am_OB);
870 DBG_OPT_LEA1(op2, new_op);
873 /* this is the 1st case */
874 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
876 DBG_OPT_LEA2(op1, op2, new_op);
878 if (get_ia32_op_type(op1) == ia32_SymConst) {
879 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
880 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
883 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
884 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
885 set_ia32_am_sc_sign(new_op);
887 set_ia32_am_flavour(new_op, ia32_am_O);
891 set_ia32_am_support(new_op, ia32_am_Source);
892 set_ia32_op_type(new_op, ia32_AddrModeS);
894 /* Lea doesn't need a Proj */
898 /* This is expr - const */
899 new_op = gen_imm_Sub(env, expr_op, imm_op);
902 set_ia32_am_support(new_op, ia32_am_Dest);
905 /* This is a normal sub */
906 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
909 set_ia32_am_support(new_op, ia32_am_Full);
913 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
915 set_ia32_res_mode(new_op, mode);
917 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Sub_res);
921 * Transforms an ia32_l_SubC (created in intrinsic lowering) into a "real" SubC
923 * @param env The transformation environment
924 * @return the created ia32 SubC node
926 static ir_node *gen_ia32_l_SubC(ia32_transform_env_t *env) {
927 return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_SubC);
931 * Transforms an ia32_l_Sub (created in intrinsic lowering) into a "real" Sub
933 * @param env The transformation environment
934 * @return the created ia32 Sub node
936 static ir_node *gen_ia32_l_Sub(ia32_transform_env_t *env) {
937 return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_Sub);
943 * Generates an ia32 DivMod with additional infrastructure for the
944 * register allocator if needed.
946 * @param env The transformation environment
947 * @param dividend -no comment- :)
948 * @param divisor -no comment- :)
949 * @param dm_flav flavour_Div/Mod/DivMod
950 * @return The created ia32 DivMod node
952 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
954 ir_node *edx_node, *cltd;
956 dbg_info *dbg = env->dbg;
957 ir_graph *irg = env->irg;
958 ir_node *block = env->block;
959 ir_mode *mode = env->mode;
960 ir_node *irn = env->irn;
965 mem = get_Div_mem(irn);
966 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
969 mem = get_Mod_mem(irn);
970 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
973 mem = get_DivMod_mem(irn);
974 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
980 if (mode_is_signed(mode)) {
981 /* in signed mode, we need to sign extend the dividend */
982 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
983 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
984 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
987 edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
988 set_ia32_Const_type(edx_node, ia32_Const);
989 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
992 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
994 set_ia32_n_res(res, 2);
996 /* Only one proj is used -> We must add a second proj and */
997 /* connect this one to a Keep node to eat up the second */
998 /* destroyed register. */
999 if (get_irn_n_edges(irn) == 1) {
1000 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
1001 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
1003 if (get_irn_op(irn) == op_Div) {
1004 set_Proj_proj(proj, pn_DivMod_res_div);
1005 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
1008 set_Proj_proj(proj, pn_DivMod_res_mod);
1009 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
1012 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1015 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1017 set_ia32_res_mode(res, mode_Is);
1024 * Wrapper for generate_DivMod. Sets flavour_Mod.
1026 * @param env The transformation environment
1028 static ir_node *gen_Mod(ia32_transform_env_t *env) {
1029 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
1033 * Wrapper for generate_DivMod. Sets flavour_Div.
1035 * @param env The transformation environment
1037 static ir_node *gen_Div(ia32_transform_env_t *env) {
1038 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
1042 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1044 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
1045 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
1051 * Creates an ia32 floating Div.
1053 * @param env The transformation environment
1054 * @return The created ia32 xDiv node
1056 static ir_node *gen_Quot(ia32_transform_env_t *env) {
1057 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1059 ir_node *nomem = new_rd_NoMem(env->irg);
1060 ir_node *op1 = get_Quot_left(env->irn);
1061 ir_node *op2 = get_Quot_right(env->irn);
1064 if (USE_SSE2(env->cg)) {
1065 if (is_ia32_xConst(op2)) {
1066 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
1067 set_ia32_am_support(new_op, ia32_am_None);
1068 set_ia32_Immop_attr(new_op, op2);
1071 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1072 set_ia32_am_support(new_op, ia32_am_Source);
1076 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1077 set_ia32_am_support(new_op, ia32_am_Source);
1079 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
1080 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1088 * Creates an ia32 Shl.
1090 * @param env The transformation environment
1091 * @return The created ia32 Shl node
1093 static ir_node *gen_Shl(ia32_transform_env_t *env) {
1094 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
1100 * Creates an ia32 Shr.
1102 * @param env The transformation environment
1103 * @return The created ia32 Shr node
1105 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1106 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1112 * Creates an ia32 Shrs.
1114 * @param env The transformation environment
1115 * @return The created ia32 Shrs node
1117 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1118 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1124 * Creates an ia32 RotL.
1126 * @param env The transformation environment
1127 * @param op1 The first operator
1128 * @param op2 The second operator
1129 * @return The created ia32 RotL node
1131 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1132 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1138 * Creates an ia32 RotR.
1139 * NOTE: There is no RotR with immediate because this would always be a RotL
1140 * "imm-mode_size_bits" which can be pre-calculated.
1142 * @param env The transformation environment
1143 * @param op1 The first operator
1144 * @param op2 The second operator
1145 * @return The created ia32 RotR node
1147 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1148 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1154 * Creates an ia32 RotR or RotL (depending on the found pattern).
1156 * @param env The transformation environment
1157 * @return The created ia32 RotL or RotR node
1159 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1160 ir_node *rotate = NULL;
1161 ir_node *op1 = get_Rot_left(env->irn);
1162 ir_node *op2 = get_Rot_right(env->irn);
1164 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1165 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1166 that means we can create a RotR instead of an Add and a RotL */
1169 ir_node *pred = get_Proj_pred(op2);
1171 if (is_ia32_Add(pred)) {
1172 ir_node *pred_pred = get_irn_n(pred, 2);
1173 tarval *tv = get_ia32_Immop_tarval(pred);
1174 long bits = get_mode_size_bits(env->mode);
1176 if (is_Proj(pred_pred)) {
1177 pred_pred = get_Proj_pred(pred_pred);
1180 if (is_ia32_Minus(pred_pred) &&
1181 tarval_is_long(tv) &&
1182 get_tarval_long(tv) == bits)
1184 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1185 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1192 rotate = gen_RotL(env, op1, op2);
1201 * Transforms a Minus node.
1203 * @param env The transformation environment
1204 * @param op The Minus operand
1205 * @return The created ia32 Minus node
1207 static ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1212 if (mode_is_float(env->mode)) {
1214 if (USE_SSE2(env->cg)) {
1215 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1216 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1217 ir_node *nomem = new_rd_NoMem(env->irg);
1219 new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1221 size = get_mode_size_bits(env->mode);
1222 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1224 set_ia32_sc(new_op, name);
1226 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1228 set_ia32_res_mode(new_op, env->mode);
1229 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1231 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
1234 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1235 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1239 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1246 * Transforms a Minus node.
1248 * @param env The transformation environment
1249 * @return The created ia32 Minus node
1251 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1252 return gen_Minus_ex(env, get_Minus_op(env->irn));
1257 * Transforms a Not node.
1259 * @param env The transformation environment
1260 * @return The created ia32 Not node
1262 static ir_node *gen_Not(ia32_transform_env_t *env) {
1263 assert (! mode_is_float(env->mode));
1264 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1270 * Transforms an Abs node.
1272 * @param env The transformation environment
1273 * @return The created ia32 Abs node
1275 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1276 ir_node *res, *p_eax, *p_edx;
1277 dbg_info *dbg = env->dbg;
1278 ir_mode *mode = env->mode;
1279 ir_graph *irg = env->irg;
1280 ir_node *block = env->block;
1281 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1282 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1283 ir_node *nomem = new_NoMem();
1284 ir_node *op = get_Abs_op(env->irn);
1288 if (mode_is_float(mode)) {
1290 if (USE_SSE2(env->cg)) {
1291 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1293 size = get_mode_size_bits(mode);
1294 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1296 set_ia32_sc(res, name);
1298 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1300 set_ia32_res_mode(res, mode);
1301 set_ia32_immop_type(res, ia32_ImmSymConst);
1303 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
1306 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1307 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1311 res = new_rd_ia32_Cdq(dbg, irg, block, op);
1312 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1313 set_ia32_res_mode(res, mode);
1315 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
1316 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
1318 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1319 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1320 set_ia32_res_mode(res, mode);
1322 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
1324 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1325 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1326 set_ia32_res_mode(res, mode);
1328 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
1337 * Transforms a Load.
1339 * @param env The transformation environment
1340 * @return the created ia32 Load node
1342 static ir_node *gen_Load(ia32_transform_env_t *env) {
1343 ir_node *node = env->irn;
1344 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1345 ir_node *ptr = get_Load_ptr(node);
1346 ir_node *lptr = ptr;
1347 ir_mode *mode = get_Load_mode(node);
1350 ia32_am_flavour_t am_flav = ia32_B;
1352 /* address might be a constant (symconst or absolute address) */
1353 if (is_ia32_Const(ptr)) {
1358 if (mode_is_float(mode)) {
1360 if (USE_SSE2(env->cg))
1361 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1363 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1366 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1369 /* base is an constant address */
1371 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1372 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1375 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1381 set_ia32_am_support(new_op, ia32_am_Source);
1382 set_ia32_op_type(new_op, ia32_AddrModeS);
1383 set_ia32_am_flavour(new_op, am_flav);
1384 set_ia32_ls_mode(new_op, mode);
1386 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1394 * Transforms a Store.
1396 * @param env The transformation environment
1397 * @return the created ia32 Store node
1399 static ir_node *gen_Store(ia32_transform_env_t *env) {
1400 ir_node *node = env->irn;
1401 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1402 ir_node *val = get_Store_value(node);
1403 ir_node *ptr = get_Store_ptr(node);
1404 ir_node *sptr = ptr;
1405 ir_node *mem = get_Store_mem(node);
1406 ir_mode *mode = get_irn_mode(val);
1407 ir_node *sval = val;
1410 ia32_am_flavour_t am_flav = ia32_B;
1411 ia32_immop_type_t immop = ia32_ImmNone;
1413 if (! mode_is_float(mode)) {
1414 /* in case of storing a const (but not a symconst) -> make it an attribute */
1415 if (is_ia32_Cnst(val)) {
1416 switch (get_ia32_op_type(val)) {
1418 immop = ia32_ImmConst;
1421 immop = ia32_ImmSymConst;
1424 assert(0 && "unsupported Const type");
1430 /* address might be a constant (symconst or absolute address) */
1431 if (is_ia32_Const(ptr)) {
1436 if (mode_is_float(mode)) {
1438 if (USE_SSE2(env->cg))
1439 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1441 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1443 else if (get_mode_size_bits(mode) == 8) {
1444 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1447 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1450 /* stored const is an attribute (saves a register) */
1451 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1452 set_ia32_Immop_attr(new_op, val);
1455 /* base is an constant address */
1457 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1458 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1461 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1467 set_ia32_am_support(new_op, ia32_am_Dest);
1468 set_ia32_op_type(new_op, ia32_AddrModeD);
1469 set_ia32_am_flavour(new_op, am_flav);
1470 set_ia32_ls_mode(new_op, get_irn_mode(val));
1471 set_ia32_immop_type(new_op, immop);
1473 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1481 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1483 * @param env The transformation environment
1484 * @return The transformed node.
1486 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1487 dbg_info *dbg = env->dbg;
1488 ir_graph *irg = env->irg;
1489 ir_node *block = env->block;
1490 ir_node *node = env->irn;
1491 ir_node *sel = get_Cond_selector(node);
1492 ir_mode *sel_mode = get_irn_mode(sel);
1493 ir_node *res = NULL;
1494 ir_node *pred = NULL;
1495 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1496 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1498 if (is_Proj(sel) && sel_mode == mode_b) {
1499 ir_node *nomem = new_NoMem();
1501 pred = get_Proj_pred(sel);
1503 /* get both compare operators */
1504 cmp_a = get_Cmp_left(pred);
1505 cmp_b = get_Cmp_right(pred);
1507 /* check if we can use a CondJmp with immediate */
1508 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1509 expr = get_expr_op(cmp_a, cmp_b);
1512 pn_Cmp pnc = get_Proj_proj(sel);
1514 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1515 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1516 /* a Cmp A =/!= 0 */
1517 ir_node *op1 = expr;
1518 ir_node *op2 = expr;
1519 ir_node *and = skip_Proj(expr);
1520 const char *cnst = NULL;
1522 /* check, if expr is an only once used And operation */
1523 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1524 op1 = get_irn_n(and, 2);
1525 op2 = get_irn_n(and, 3);
1527 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1529 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1530 set_ia32_pncode(res, get_Proj_proj(sel));
1531 set_ia32_res_mode(res, get_irn_mode(op1));
1534 copy_ia32_Immop_attr(res, and);
1537 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1542 if (mode_is_float(get_irn_mode(expr))) {
1544 if (USE_SSE2(env->cg))
1545 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1551 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1553 set_ia32_Immop_attr(res, cnst);
1554 set_ia32_res_mode(res, get_irn_mode(expr));
1557 if (mode_is_float(get_irn_mode(cmp_a))) {
1559 if (USE_SSE2(env->cg))
1560 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1563 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1564 proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
1565 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1569 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1570 set_ia32_commutative(res);
1572 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1575 set_ia32_pncode(res, get_Proj_proj(sel));
1576 //set_ia32_am_support(res, ia32_am_Source);
1579 /* determine the smallest switch case value */
1580 int switch_min = INT_MAX;
1581 const ir_edge_t *edge;
1584 foreach_out_edge(node, edge) {
1585 int pn = get_Proj_proj(get_edge_src_irn(edge));
1586 switch_min = pn < switch_min ? pn : switch_min;
1590 /* if smallest switch case is not 0 we need an additional sub */
1591 snprintf(buf, sizeof(buf), "%d", switch_min);
1592 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1593 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1594 sub_ia32_am_offs(res, buf);
1595 set_ia32_am_flavour(res, ia32_am_OB);
1596 set_ia32_am_support(res, ia32_am_Source);
1597 set_ia32_op_type(res, ia32_AddrModeS);
1600 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1601 set_ia32_pncode(res, get_Cond_defaultProj(node));
1602 set_ia32_res_mode(res, get_irn_mode(sel));
1605 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1612 * Transforms a CopyB node.
1614 * @param env The transformation environment
1615 * @return The transformed node.
1617 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1618 ir_node *res = NULL;
1619 dbg_info *dbg = env->dbg;
1620 ir_graph *irg = env->irg;
1621 ir_mode *mode = env->mode;
1622 ir_node *block = env->block;
1623 ir_node *node = env->irn;
1624 ir_node *src = get_CopyB_src(node);
1625 ir_node *dst = get_CopyB_dst(node);
1626 ir_node *mem = get_CopyB_mem(node);
1627 int size = get_type_size_bytes(get_CopyB_type(node));
1630 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1631 /* then we need the size explicitly in ECX. */
1632 if (size >= 16 * 4) {
1633 rem = size & 0x3; /* size % 4 */
1636 res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
1637 set_ia32_op_type(res, ia32_Const);
1638 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1640 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1641 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1644 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1645 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1646 set_ia32_immop_type(res, ia32_ImmConst);
1649 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1657 * Transforms a Mux node into CMov.
1659 * @param env The transformation environment
1660 * @return The transformed node.
1662 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1664 ir_node *node = env->irn;
1665 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1666 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1668 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1675 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *cmp_a, ir_node *cmp_b, \
1676 ir_node *psi_true, ir_node *psi_default, ir_mode *mode);
1679 * Transforms a Psi node into CMov.
1681 * @param env The transformation environment
1682 * @return The transformed node.
1684 static ir_node *gen_Psi(ia32_transform_env_t *env) {
1685 ia32_code_gen_t *cg = env->cg;
1686 dbg_info *dbg = env->dbg;
1687 ir_graph *irg = env->irg;
1688 ir_mode *mode = env->mode;
1689 ir_node *block = env->block;
1690 ir_node *node = env->irn;
1691 ir_node *cmp_proj = get_Mux_sel(node);
1692 ir_node *psi_true = get_Psi_val(node, 0);
1693 ir_node *psi_default = get_Psi_default(node);
1694 ir_node *noreg = ia32_new_NoReg_gp(cg);
1695 ir_node *nomem = new_rd_NoMem(irg);
1696 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
1699 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
1701 cmp = get_Proj_pred(cmp_proj);
1702 cmp_a = get_Cmp_left(cmp);
1703 cmp_b = get_Cmp_right(cmp);
1704 pnc = get_Proj_proj(cmp_proj);
1706 if (mode_is_float(mode)) {
1707 /* floating point psi */
1710 /* 1st case: compare operands are float too */
1712 /* psi(cmp(a, b), t, f) can be done as: */
1713 /* tmp = cmp a, b */
1714 /* tmp2 = t and tmp */
1715 /* tmp3 = f and not tmp */
1716 /* res = tmp2 or tmp3 */
1718 /* in case the compare operands are int, we move them into xmm register */
1719 if (! mode_is_float(get_irn_mode(cmp_a))) {
1720 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, node, mode_D);
1721 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, node, mode_D);
1723 pnc |= 8; /* transform integer compare to fp compare */
1726 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1727 set_ia32_pncode(new_op, pnc);
1728 set_ia32_am_support(new_op, ia32_am_Source);
1729 set_ia32_res_mode(new_op, mode);
1730 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1731 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xCmp_res);
1733 and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, psi_true, new_op, nomem);
1734 set_ia32_am_support(and1, ia32_am_Source);
1735 set_ia32_res_mode(and1, mode);
1736 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
1737 and1 = new_rd_Proj(dbg, irg, block, and1, mode, pn_ia32_xAnd_res);
1739 and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, psi_default, nomem);
1740 set_ia32_am_support(and2, ia32_am_Source);
1741 set_ia32_res_mode(and2, mode);
1742 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
1743 and2 = new_rd_Proj(dbg, irg, block, and2, mode, pn_ia32_xAndNot_res);
1745 new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
1746 set_ia32_am_support(new_op, ia32_am_Source);
1747 set_ia32_res_mode(new_op, mode);
1748 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1749 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xOr_res);
1753 new_op = new_rd_ia32_vfCMov(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1754 set_ia32_pncode(new_op, pnc);
1755 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1760 construct_binop_func *set_func = NULL;
1761 cmov_func_t *cmov_func = NULL;
1763 if (mode_is_float(get_irn_mode(cmp_a))) {
1764 /* 1st case: compare operands are floats */
1769 set_func = new_rd_ia32_xCmpSet;
1770 cmov_func = new_rd_ia32_xCmpCMov;
1774 set_func = new_rd_ia32_vfCmpSet;
1775 cmov_func = new_rd_ia32_vfCmpCMov;
1778 pnc &= 7; /* fp compare -> int compare */
1781 /* 2nd case: compare operand are integer too */
1782 set_func = new_rd_ia32_CmpSet;
1783 cmov_func = new_rd_ia32_CmpCMov;
1786 /* create the nodes */
1788 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
1789 if (is_ia32_Const_0(cmp_b) && is_Proj(cmp_a) && (is_ia32_And(get_Proj_pred(cmp_a)) || is_ia32_Or(get_Proj_pred(cmp_a)))) {
1790 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1791 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1792 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1793 set_ia32_pncode(new_op, pnc);
1795 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1796 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1797 /* we invert condition and set default to 0 */
1798 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1799 set_ia32_pncode(new_op, get_negated_pnc(pnc, mode));
1802 /* otherwise: use CMOVcc */
1803 new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, cmp_a, psi_true, psi_default, mode);
1804 set_ia32_pncode(new_op, pnc);
1807 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1811 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1812 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1813 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1814 set_ia32_pncode(get_Proj_pred(new_op), pnc);
1815 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1817 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1818 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1819 /* we invert condition and set default to 0 */
1820 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1821 set_ia32_pncode(get_Proj_pred(new_op), get_negated_pnc(pnc, mode));
1822 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1825 /* otherwise: use CMOVcc */
1826 new_op = cmov_func(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1827 set_ia32_pncode(new_op, pnc);
1828 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1838 * Following conversion rules apply:
1842 * 1) n bit -> m bit n > m (downscale)
1843 * a) target is signed: movsx
1844 * b) target is unsigned: and with lower bits sets
1845 * 2) n bit -> m bit n == m (sign change)
1847 * 3) n bit -> m bit n < m (upscale)
1848 * a) source is signed: movsx
1849 * b) source is unsigned: and with lower bits sets
1853 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1857 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1858 * if target mode < 32bit: additional INT -> INT conversion (see above)
1862 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1863 * x87 is mode_E internally, conversions happen only at load and store
1864 * in non-strict semantic
1868 * Create a conversion from x87 state register to general purpose.
1870 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1871 ia32_code_gen_t *cg = env->cg;
1872 entity *ent = cg->fp_to_gp;
1873 ir_graph *irg = env->irg;
1874 ir_node *block = env->block;
1875 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1876 ir_node *op = get_Conv_op(env->irn);
1877 ir_node *fist, *mem, *load;
1880 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1881 ent = cg->fp_to_gp =
1882 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1886 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
1888 set_ia32_frame_ent(fist, ent);
1889 set_ia32_use_frame(fist);
1890 set_ia32_am_support(fist, ia32_am_Dest);
1891 set_ia32_op_type(fist, ia32_AddrModeD);
1892 set_ia32_am_flavour(fist, ia32_B);
1893 set_ia32_ls_mode(fist, mode_E);
1895 mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
1898 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1900 set_ia32_frame_ent(load, ent);
1901 set_ia32_use_frame(load);
1902 set_ia32_am_support(load, ia32_am_Source);
1903 set_ia32_op_type(load, ia32_AddrModeS);
1904 set_ia32_am_flavour(load, ia32_B);
1905 set_ia32_ls_mode(load, tgt_mode);
1907 return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
1911 * Create a conversion from x87 state register to general purpose.
1913 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1914 ia32_code_gen_t *cg = env->cg;
1915 entity *ent = cg->gp_to_fp;
1916 ir_graph *irg = env->irg;
1917 ir_node *block = env->block;
1918 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1919 ir_node *nomem = get_irg_no_mem(irg);
1920 ir_node *op = get_Conv_op(env->irn);
1921 ir_node *fild, *store, *mem;
1925 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
1926 ent = cg->gp_to_fp =
1927 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
1930 /* first convert to 32 bit */
1931 src_bits = get_mode_size_bits(src_mode);
1932 if (src_bits == 8) {
1933 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
1934 op = new_r_Proj(irg, block, op, mode_Is, 0);
1936 else if (src_bits < 32) {
1937 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
1938 op = new_r_Proj(irg, block, op, mode_Is, 0);
1942 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
1944 set_ia32_frame_ent(store, ent);
1945 set_ia32_use_frame(store);
1947 set_ia32_am_support(store, ia32_am_Dest);
1948 set_ia32_op_type(store, ia32_AddrModeD);
1949 set_ia32_am_flavour(store, ia32_B);
1950 set_ia32_ls_mode(store, mode_Is);
1952 mem = new_r_Proj(irg, block, store, mode_M, 0);
1955 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1957 set_ia32_frame_ent(fild, ent);
1958 set_ia32_use_frame(fild);
1959 set_ia32_am_support(fild, ia32_am_Source);
1960 set_ia32_op_type(fild, ia32_AddrModeS);
1961 set_ia32_am_flavour(fild, ia32_B);
1962 set_ia32_ls_mode(fild, mode_E);
1964 return new_r_Proj(irg, block, fild, mode_E, 0);
1968 * Transforms a Conv node.
1970 * @param env The transformation environment
1971 * @return The created ia32 Conv node
1973 static ir_node *gen_Conv(ia32_transform_env_t *env) {
1974 dbg_info *dbg = env->dbg;
1975 ir_graph *irg = env->irg;
1976 ir_node *op = get_Conv_op(env->irn);
1977 ir_mode *src_mode = get_irn_mode(op);
1978 ir_mode *tgt_mode = env->mode;
1979 int src_bits = get_mode_size_bits(src_mode);
1980 int tgt_bits = get_mode_size_bits(tgt_mode);
1982 ir_node *block = env->block;
1983 ir_node *new_op = NULL;
1984 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1985 ir_node *nomem = new_rd_NoMem(irg);
1987 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1989 if (src_mode == tgt_mode) {
1990 /* this can happen when changing mode_P to mode_Is */
1991 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1992 edges_reroute(env->irn, op, irg);
1994 else if (mode_is_float(src_mode)) {
1995 /* we convert from float ... */
1996 if (mode_is_float(tgt_mode)) {
1998 if (USE_SSE2(env->cg)) {
1999 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
2000 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
2001 pn = pn_ia32_Conv_FP2FP_res;
2004 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
2005 edges_reroute(env->irn, op, irg);
2010 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
2011 if (USE_SSE2(env->cg)) {
2012 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
2013 pn = pn_ia32_Conv_FP2I_res;
2016 return gen_x87_fp_to_gp(env, tgt_mode);
2018 /* if target mode is not int: add an additional downscale convert */
2019 if (tgt_bits < 32) {
2020 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2021 set_ia32_am_support(new_op, ia32_am_Source);
2022 set_ia32_tgt_mode(new_op, tgt_mode);
2023 set_ia32_src_mode(new_op, src_mode);
2025 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, pn_ia32_Conv_FP2I_res);
2027 if (tgt_bits == 8 || src_bits == 8) {
2028 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
2029 pn = pn_ia32_Conv_I2I8Bit_res;
2032 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
2033 pn = pn_ia32_Conv_I2I_res;
2039 /* we convert from int ... */
2040 if (mode_is_float(tgt_mode)) {
2043 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
2044 if (USE_SSE2(env->cg)) {
2045 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
2046 pn = pn_ia32_Conv_I2FP_res;
2049 return gen_x87_gp_to_fp(env, src_mode);
2053 if (get_mode_size_bits(src_mode) == tgt_bits) {
2054 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
2055 edges_reroute(env->irn, op, irg);
2058 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2059 if (tgt_bits == 8 || src_bits == 8) {
2060 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
2061 pn = pn_ia32_Conv_I2I8Bit_res;
2064 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
2065 pn = pn_ia32_Conv_I2I_res;
2072 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2073 set_ia32_tgt_mode(new_op, tgt_mode);
2074 set_ia32_src_mode(new_op, src_mode);
2076 set_ia32_am_support(new_op, ia32_am_Source);
2078 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, pn);
2086 /********************************************
2089 * | |__ ___ _ __ ___ __| | ___ ___
2090 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2091 * | |_) | __/ | | | (_) | (_| | __/\__ \
2092 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2094 ********************************************/
2097 * Decides in which block the transformed StackParam should be placed.
2098 * If the StackParam has more than one user, the dominator block of
2099 * the users will be returned. In case of only one user, this is either
2100 * the user block or, in case of a Phi, the predecessor block of the Phi.
2102 static ir_node *get_block_transformed_stack_param(ir_node *irn) {
2103 ir_node *dom_bl = NULL;
2105 if (get_irn_n_edges(irn) == 1) {
2106 ir_node *src = get_edge_src_irn(get_irn_out_edge_first(irn));
2108 if (! is_Phi(src)) {
2109 dom_bl = get_nodes_block(src);
2112 /* Determine on which in position of the Phi the irn is */
2113 /* and get the corresponding cfg predecessor block. */
2115 int i = get_irn_pred_pos(src, irn);
2116 assert(i >= 0 && "kaputt");
2117 dom_bl = get_Block_cfgpred_block(get_nodes_block(src), i);
2121 dom_bl = node_users_smallest_common_dominator(irn, 1);
2124 assert(dom_bl && "dominator block not found");
2129 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
2130 ir_node *new_op = NULL;
2131 ir_node *node = env->irn;
2132 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2133 ir_node *mem = new_rd_NoMem(env->irg);
2134 ir_node *ptr = get_irn_n(node, 0);
2135 entity *ent = be_get_frame_entity(node);
2136 ir_mode *mode = env->mode;
2138 /* choose the block where to place the load */
2139 env->block = get_block_transformed_stack_param(node);
2141 if (mode_is_float(mode)) {
2143 if (USE_SSE2(env->cg))
2144 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2146 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2149 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2152 set_ia32_frame_ent(new_op, ent);
2153 set_ia32_use_frame(new_op);
2155 set_ia32_am_support(new_op, ia32_am_Source);
2156 set_ia32_op_type(new_op, ia32_AddrModeS);
2157 set_ia32_am_flavour(new_op, ia32_B);
2158 set_ia32_ls_mode(new_op, mode);
2160 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2162 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
2166 * Transforms a FrameAddr into an ia32 Add.
2168 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
2169 ir_node *new_op = NULL;
2170 ir_node *node = env->irn;
2171 ir_node *op = get_irn_n(node, 0);
2172 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2173 ir_node *nomem = new_rd_NoMem(env->irg);
2175 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
2176 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
2177 set_ia32_am_support(new_op, ia32_am_Full);
2178 set_ia32_use_frame(new_op);
2179 set_ia32_immop_type(new_op, ia32_ImmConst);
2180 set_ia32_commutative(new_op);
2182 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2184 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
2188 * Transforms a FrameLoad into an ia32 Load.
2190 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
2191 ir_node *new_op = NULL;
2192 ir_node *node = env->irn;
2193 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2194 ir_node *mem = get_irn_n(node, 0);
2195 ir_node *ptr = get_irn_n(node, 1);
2196 entity *ent = be_get_frame_entity(node);
2197 ir_mode *mode = get_type_mode(get_entity_type(ent));
2199 if (mode_is_float(mode)) {
2201 if (USE_SSE2(env->cg))
2202 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2204 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2207 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2209 set_ia32_frame_ent(new_op, ent);
2210 set_ia32_use_frame(new_op);
2212 set_ia32_am_support(new_op, ia32_am_Source);
2213 set_ia32_op_type(new_op, ia32_AddrModeS);
2214 set_ia32_am_flavour(new_op, ia32_B);
2215 set_ia32_ls_mode(new_op, mode);
2217 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2224 * Transforms a FrameStore into an ia32 Store.
2226 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
2227 ir_node *new_op = NULL;
2228 ir_node *node = env->irn;
2229 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2230 ir_node *mem = get_irn_n(node, 0);
2231 ir_node *ptr = get_irn_n(node, 1);
2232 ir_node *val = get_irn_n(node, 2);
2233 entity *ent = be_get_frame_entity(node);
2234 ir_mode *mode = get_irn_mode(val);
2236 if (mode_is_float(mode)) {
2238 if (USE_SSE2(env->cg))
2239 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2241 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2243 else if (get_mode_size_bits(mode) == 8) {
2244 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2247 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2250 set_ia32_frame_ent(new_op, ent);
2251 set_ia32_use_frame(new_op);
2253 set_ia32_am_support(new_op, ia32_am_Dest);
2254 set_ia32_op_type(new_op, ia32_AddrModeD);
2255 set_ia32_am_flavour(new_op, ia32_B);
2256 set_ia32_ls_mode(new_op, mode);
2258 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2264 * This function just sets the register for the Unknown node
2265 * as this is not done during register allocation because Unknown
2266 * is an "ignore" node.
2268 static ir_node *gen_Unknown(ia32_transform_env_t *env) {
2269 ir_mode *mode = env->mode;
2270 ir_node *irn = env->irn;
2272 if (mode_is_float(mode)) {
2273 if (USE_SSE2(env->cg))
2274 arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
2276 arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
2278 else if (mode_is_int(mode) || mode_is_reference(mode)) {
2279 arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
2282 assert(0 && "unsupported Unknown-Mode");
2289 /*********************************************************
2292 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
2293 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
2294 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
2295 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
2297 *********************************************************/
2300 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
2301 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2303 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
2304 ia32_transform_env_t tenv;
2305 ir_node *in1, *in2, *noreg, *nomem, *res;
2306 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
2308 /* Return if AM node or not a Sub or xSub */
2309 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_xSub(irn)))
2312 noreg = ia32_new_NoReg_gp(cg);
2313 nomem = new_rd_NoMem(cg->irg);
2314 in1 = get_irn_n(irn, 2);
2315 in2 = get_irn_n(irn, 3);
2316 in1_reg = arch_get_irn_register(cg->arch_env, in1);
2317 in2_reg = arch_get_irn_register(cg->arch_env, in2);
2318 out_reg = get_ia32_out_reg(irn, 0);
2320 tenv.block = get_nodes_block(irn);
2321 tenv.dbg = get_irn_dbg_info(irn);
2324 tenv.mode = get_ia32_res_mode(irn);
2326 DEBUG_ONLY(tenv.mod = cg->mod;)
2328 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
2329 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
2330 /* generate the neg src2 */
2331 res = gen_Minus_ex(&tenv, in2);
2332 arch_set_irn_register(cg->arch_env, res, in2_reg);
2334 /* add to schedule */
2335 sched_add_before(irn, res);
2337 /* generate the add */
2338 if (mode_is_float(tenv.mode)) {
2339 res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2340 set_ia32_am_support(res, ia32_am_Source);
2343 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2344 set_ia32_am_support(res, ia32_am_Full);
2345 set_ia32_commutative(res);
2347 set_ia32_res_mode(res, tenv.mode);
2349 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
2351 slots = get_ia32_slots(res);
2354 /* add to schedule */
2355 sched_add_before(irn, res);
2357 /* remove the old sub */
2360 DBG_OPT_SUB2NEGADD(irn, res);
2362 /* exchange the add and the sub */
2368 * Transforms a LEA into an Add if possible
2369 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2371 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
2372 ia32_am_flavour_t am_flav;
2374 ir_node *res = NULL;
2375 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
2377 ia32_transform_env_t tenv;
2378 const arch_register_t *out_reg, *base_reg, *index_reg;
2381 if (! is_ia32_Lea(irn))
2384 am_flav = get_ia32_am_flavour(irn);
2386 /* only some LEAs can be transformed to an Add */
2387 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
2390 noreg = ia32_new_NoReg_gp(cg);
2391 nomem = new_rd_NoMem(cg->irg);
2394 base = get_irn_n(irn, 0);
2395 index = get_irn_n(irn,1);
2397 offs = get_ia32_am_offs(irn);
2399 /* offset has a explicit sign -> we need to skip + */
2400 if (offs && offs[0] == '+')
2403 out_reg = arch_get_irn_register(cg->arch_env, irn);
2404 base_reg = arch_get_irn_register(cg->arch_env, base);
2405 index_reg = arch_get_irn_register(cg->arch_env, index);
2407 tenv.block = get_nodes_block(irn);
2408 tenv.dbg = get_irn_dbg_info(irn);
2411 DEBUG_ONLY(tenv.mod = cg->mod;)
2412 tenv.mode = get_irn_mode(irn);
2415 switch(get_ia32_am_flavour(irn)) {
2417 /* out register must be same as base register */
2418 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2424 /* out register must be same as base register */
2425 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2432 /* out register must be same as index register */
2433 if (! REGS_ARE_EQUAL(out_reg, index_reg))
2440 /* out register must be same as one in register */
2441 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
2445 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
2450 /* in registers a different from out -> no Add possible */
2457 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
2458 arch_set_irn_register(cg->arch_env, res, out_reg);
2459 set_ia32_op_type(res, ia32_Normal);
2460 set_ia32_commutative(res);
2461 set_ia32_res_mode(res, tenv.mode);
2464 set_ia32_cnst(res, offs);
2465 set_ia32_immop_type(res, ia32_ImmConst);
2468 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
2470 /* add Add to schedule */
2471 sched_add_before(irn, res);
2473 DBG_OPT_LEA2ADD(irn, res);
2475 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, pn_ia32_Add_res);
2477 /* add result Proj to schedule */
2478 sched_add_before(irn, res);
2480 /* remove the old LEA */
2483 /* exchange the Add and the LEA */
2488 * the BAD transformer.
2490 static ir_node *bad_transform(ia32_transform_env_t *env) {
2491 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2497 * Enters all transform functions into the generic pointer
2499 void ia32_register_transformers(void) {
2500 ir_op *op_Max, *op_Min, *op_Mulh;
2502 /* first clear the generic function pointer for all ops */
2503 clear_irp_opcodes_generic_func();
2505 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2506 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
2557 /* constant transformation happens earlier */
2581 /* set the register for all Unknown nodes */
2584 op_Max = get_op_Max();
2587 op_Min = get_op_Min();
2590 op_Mulh = get_op_Mulh();
2599 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
2602 * Transforms the given firm node (and maybe some other related nodes)
2603 * into one or more assembler nodes.
2605 * @param node the firm node
2606 * @param env the debug module
2608 void ia32_transform_node(ir_node *node, void *env) {
2609 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2610 ir_op *op = get_irn_op(node);
2611 ir_node *asm_node = NULL;
2617 /* link arguments pointing to Unknown to the UNKNOWN Proj */
2618 for (i = get_irn_arity(node) - 1; i >= 0; i--) {
2619 if (is_Unknown(get_irn_n(node, i)))
2620 set_irn_n(node, i, be_get_unknown_for_mode(cg, get_irn_mode(get_irn_n(node, i))));
2623 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
2624 if (op->ops.generic) {
2625 ia32_transform_env_t tenv;
2626 transform_func *transform = (transform_func *)op->ops.generic;
2628 tenv.block = get_nodes_block(node);
2629 tenv.dbg = get_irn_dbg_info(node);
2630 tenv.irg = current_ir_graph;
2632 tenv.mode = get_irn_mode(node);
2634 DEBUG_ONLY(tenv.mod = cg->mod;)
2636 asm_node = (*transform)(&tenv);
2639 /* exchange nodes if a new one was generated */
2641 exchange(node, asm_node);
2642 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2645 DB((cg->mod, LEVEL_1, "ignored\n"));
2650 * Transforms a psi condition.
2652 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
2655 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
2656 set_irn_mode(cond, mode);
2658 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
2659 ir_node *in = get_irn_n(cond, i);
2661 /* if in is a compare: transform into Set/xCmp */
2663 ir_node *new_op = NULL;
2664 ir_node *cmp = get_Proj_pred(in);
2665 ir_node *cmp_a = get_Cmp_left(cmp);
2666 ir_node *cmp_b = get_Cmp_right(cmp);
2667 dbg_info *dbg = get_irn_dbg_info(cmp);
2668 ir_graph *irg = get_irn_irg(cmp);
2669 ir_node *block = get_nodes_block(cmp);
2670 ir_node *noreg = ia32_new_NoReg_gp(cg);
2671 ir_node *nomem = new_rd_NoMem(irg);
2672 int pnc = get_Proj_proj(in);
2674 /* this is a compare */
2675 if (mode_is_float(mode)) {
2676 /* Psi is float, we need a floating point compare */
2680 if (! mode_is_float(get_irn_mode(cmp_a))) {
2681 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
2682 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
2686 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
2687 set_ia32_pncode(new_op, pnc);
2688 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
2697 ia32_transform_env_t tenv;
2698 construct_binop_func *set_func = NULL;
2700 if (mode_is_float(get_irn_mode(cmp_a))) {
2701 /* 1st case: compare operands are floats */
2706 set_func = new_rd_ia32_xCmpSet;
2710 set_func = new_rd_ia32_vfCmpSet;
2713 pnc &= 7; /* fp compare -> int compare */
2716 /* 2nd case: compare operand are integer too */
2717 set_func = new_rd_ia32_CmpSet;
2728 new_op = gen_binop(&tenv, cmp_a, cmp_b, set_func);
2729 set_ia32_pncode(get_Proj_pred(new_op), pnc);
2730 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
2733 /* exchange with old compare */
2734 exchange(in, new_op);
2737 /* another complex condition */
2738 transform_psi_cond(in, mode, cg);
2744 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
2745 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
2746 * compare, which causes the compare result to be stores in a register. The
2747 * "And"s and "Or"s are transformed later, we just have to set their mode right.
2749 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
2750 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2751 ir_node *psi_sel, *new_cmp, *block;
2756 if (get_irn_opcode(node) != iro_Psi)
2759 psi_sel = get_Psi_cond(node, 0);
2761 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
2762 if (is_Proj(psi_sel))
2765 mode = get_irn_mode(node);
2767 transform_psi_cond(psi_sel, mode, cg);
2769 irg = get_irn_irg(node);
2770 block = get_nodes_block(node);
2772 /* we need to compare the evaluated condition tree with 0 */
2774 /* BEWARE: new_r_Const_long works for floating point as well */
2775 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
2776 /* transform the const */
2777 ia32_place_consts_set_modes(new_cmp, cg);
2778 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne + (mode_is_float(mode) ? pn_Cmp_Uo : 0));
2780 set_Psi_cond(node, 0, new_cmp);