2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
15 #include "irgraph_t.h"
20 #include "iredges_t.h"
28 #include "archop.h" /* we need this for Min and Max nodes */
30 #include "../benode_t.h"
31 #include "../besched.h"
34 #include "bearch_ia32_t.h"
35 #include "ia32_nodes_attr.h"
36 #include "ia32_transform.h"
37 #include "ia32_new_nodes.h"
38 #include "ia32_map_regs.h"
39 #include "ia32_dbg_stat.h"
40 #include "ia32_optimize.h"
41 #include "ia32_util.h"
43 #include "gen_ia32_regalloc_if.h"
45 #define SFP_SIGN "0x80000000"
46 #define DFP_SIGN "0x8000000000000000"
47 #define SFP_ABS "0x7FFFFFFF"
48 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
50 #define TP_SFP_SIGN "ia32_sfp_sign"
51 #define TP_DFP_SIGN "ia32_dfp_sign"
52 #define TP_SFP_ABS "ia32_sfp_abs"
53 #define TP_DFP_ABS "ia32_dfp_abs"
55 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
56 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
57 #define ENT_SFP_ABS "IA32_SFP_ABS"
58 #define ENT_DFP_ABS "IA32_DFP_ABS"
60 extern ir_op *get_op_Mulh(void);
62 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
63 ir_node *op1, ir_node *op2, ir_node *mem);
65 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
66 ir_node *op, ir_node *mem);
69 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
72 /****************************************************************************************************
74 * | | | | / _| | | (_)
75 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
76 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
77 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
78 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
80 ****************************************************************************************************/
83 * Returns 1 if irn is a Const representing 0, 0 otherwise
85 static INLINE int is_ia32_Const_0(ir_node *irn) {
86 return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
87 classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
91 * Returns 1 if irn is a Const representing 1, 0 otherwise
93 static INLINE int is_ia32_Const_1(ir_node *irn) {
94 return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
95 classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
99 * Returns the Proj representing the UNKNOWN register for given mode.
101 static ir_node *be_get_unknown_for_mode(ia32_code_gen_t *cg, ir_mode *mode) {
102 be_abi_irg_t *babi = cg->birg->abi;
103 const arch_register_t *unknwn_reg = NULL;
105 if (mode_is_float(mode)) {
106 unknwn_reg = USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_UKNWN] : &ia32_vfp_regs[REG_VFP_UKNWN];
109 unknwn_reg = &ia32_gp_regs[REG_GP_UKNWN];
112 return be_abi_get_callee_save_irn(babi, unknwn_reg);
116 * Gets the Proj with number pn from irn.
118 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
119 const ir_edge_t *edge;
121 assert(get_irn_mode(irn) == mode_T && "need mode_T");
123 foreach_out_edge(irn, edge) {
124 proj = get_edge_src_irn(edge);
126 if (get_Proj_proj(proj) == pn)
134 * SSE convert of an integer node into a floating point node.
136 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block,
137 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
139 ir_node *noreg = ia32_new_NoReg_gp(cg);
140 ir_node *nomem = new_rd_NoMem(irg);
142 ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
143 set_ia32_src_mode(conv, get_irn_mode(in));
144 set_ia32_tgt_mode(conv, tgt_mode);
145 set_ia32_am_support(conv, ia32_am_Source);
146 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
148 return new_rd_Proj(dbg, irg, block, conv, tgt_mode, pn_ia32_Conv_I2FP_res);
151 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
152 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
153 static const struct {
155 const char *ent_name;
156 const char *cnst_str;
157 } names [ia32_known_const_max] = {
158 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
159 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
160 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
161 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
163 static struct entity *ent_cache[ia32_known_const_max];
165 const char *tp_name, *ent_name, *cnst_str;
172 ent_name = names[kct].ent_name;
173 if (! ent_cache[kct]) {
174 tp_name = names[kct].tp_name;
175 cnst_str = names[kct].cnst_str;
177 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
178 tp = new_type_primitive(new_id_from_str(tp_name), mode);
179 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
181 set_entity_ld_ident(ent, get_entity_ident(ent));
182 set_entity_visibility(ent, visibility_local);
183 set_entity_variability(ent, variability_constant);
184 set_entity_allocation(ent, allocation_static);
186 /* we create a new entity here: It's initialization must resist on the
188 rem = current_ir_graph;
189 current_ir_graph = get_const_code_irg();
190 cnst = new_Const(mode, tv);
191 current_ir_graph = rem;
193 set_atomic_ent_value(ent, cnst);
195 /* cache the entry */
196 ent_cache[kct] = ent;
199 return get_entity_ident(ent_cache[kct]);
204 * Prints the old node name on cg obst and returns a pointer to it.
206 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
207 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
209 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
210 obstack_1grow(isa->name_obst, 0);
211 isa->name_obst_size += obstack_object_size(isa->name_obst);
212 return obstack_finish(isa->name_obst);
216 /* determine if one operator is an Imm */
217 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
219 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
220 else return is_ia32_Cnst(op2) ? op2 : NULL;
223 /* determine if one operator is not an Imm */
224 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
225 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
230 * Construct a standard binary operation, set AM and immediate if required.
232 * @param env The transformation environment
233 * @param op1 The first operand
234 * @param op2 The second operand
235 * @param func The node constructor function
236 * @return The constructed ia32 node.
238 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
239 ir_node *new_op = NULL;
240 ir_mode *mode = env->mode;
241 dbg_info *dbg = env->dbg;
242 ir_graph *irg = env->irg;
243 ir_node *block = env->block;
244 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
245 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
246 ir_node *nomem = new_NoMem();
247 ir_node *expr_op, *imm_op;
248 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
250 /* Check if immediate optimization is on and */
251 /* if it's an operation with immediate. */
252 /* MulS and Mulh don't support immediates */
253 if (! (env->cg->opt & IA32_OPT_IMMOPS) ||
254 func == new_rd_ia32_Mulh ||
255 func == new_rd_ia32_MulS)
260 else if (is_op_commutative(get_irn_op(env->irn))) {
261 imm_op = get_immediate_op(op1, op2);
262 expr_op = get_expr_op(op1, op2);
265 imm_op = get_immediate_op(NULL, op2);
266 expr_op = get_expr_op(op1, op2);
269 assert((expr_op || imm_op) && "invalid operands");
272 /* We have two consts here: not yet supported */
276 if (mode_is_float(mode)) {
277 /* floating point operations */
279 DB((mod, LEVEL_1, "FP with immediate ..."));
280 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
281 set_ia32_Immop_attr(new_op, imm_op);
282 set_ia32_am_support(new_op, ia32_am_None);
285 DB((mod, LEVEL_1, "FP binop ..."));
286 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
287 set_ia32_am_support(new_op, ia32_am_Source);
289 set_ia32_ls_mode(new_op, mode);
292 /* integer operations */
294 /* This is expr + const */
295 DB((mod, LEVEL_1, "INT with immediate ..."));
296 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
297 set_ia32_Immop_attr(new_op, imm_op);
300 set_ia32_am_support(new_op, ia32_am_Dest);
303 DB((mod, LEVEL_1, "INT binop ..."));
304 /* This is a normal operation */
305 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
308 set_ia32_am_support(new_op, ia32_am_Full);
312 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
314 set_ia32_res_mode(new_op, mode);
316 if (is_op_commutative(get_irn_op(env->irn))) {
317 set_ia32_commutative(new_op);
320 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
326 * Construct a shift/rotate binary operation, sets AM and immediate if required.
328 * @param env The transformation environment
329 * @param op1 The first operand
330 * @param op2 The second operand
331 * @param func The node constructor function
332 * @return The constructed ia32 node.
334 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
335 ir_node *new_op = NULL;
336 ir_mode *mode = env->mode;
337 dbg_info *dbg = env->dbg;
338 ir_graph *irg = env->irg;
339 ir_node *block = env->block;
340 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
341 ir_node *nomem = new_NoMem();
342 ir_node *expr_op, *imm_op;
344 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
346 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
348 /* Check if immediate optimization is on and */
349 /* if it's an operation with immediate. */
350 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
351 expr_op = get_expr_op(op1, op2);
353 assert((expr_op || imm_op) && "invalid operands");
356 /* We have two consts here: not yet supported */
360 /* Limit imm_op within range imm8 */
362 tv = get_ia32_Immop_tarval(imm_op);
365 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
366 set_ia32_Immop_tarval(imm_op, tv);
373 /* integer operations */
375 /* This is shift/rot with const */
376 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
378 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
379 set_ia32_Immop_attr(new_op, imm_op);
382 /* This is a normal shift/rot */
383 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
384 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
388 set_ia32_am_support(new_op, ia32_am_Dest);
390 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
392 set_ia32_res_mode(new_op, mode);
393 set_ia32_emit_cl(new_op);
395 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
400 * Construct a standard unary operation, set AM and immediate if required.
402 * @param env The transformation environment
403 * @param op The operand
404 * @param func The node constructor function
405 * @return The constructed ia32 node.
407 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
408 ir_node *new_op = NULL;
409 ir_mode *mode = env->mode;
410 dbg_info *dbg = env->dbg;
411 ir_graph *irg = env->irg;
412 ir_node *block = env->block;
413 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
414 ir_node *nomem = new_NoMem();
415 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
417 new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
419 if (mode_is_float(mode)) {
420 DB((mod, LEVEL_1, "FP unop ..."));
421 /* floating point operations don't support implicit store */
422 set_ia32_am_support(new_op, ia32_am_None);
425 DB((mod, LEVEL_1, "INT unop ..."));
426 set_ia32_am_support(new_op, ia32_am_Dest);
429 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
431 set_ia32_res_mode(new_op, mode);
433 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
439 * Creates an ia32 Add with immediate.
441 * @param env The transformation environment
442 * @param expr_op The expression operator
443 * @param const_op The constant
444 * @return the created ia32 Add node
446 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
447 ir_node *new_op = NULL;
448 tarval *tv = get_ia32_Immop_tarval(const_op);
449 dbg_info *dbg = env->dbg;
450 ir_graph *irg = env->irg;
451 ir_node *block = env->block;
452 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
453 ir_node *nomem = new_NoMem();
455 tarval_classification_t class_tv, class_negtv;
456 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
458 /* try to optimize to inc/dec */
459 if ((env->cg->opt & IA32_OPT_INCDEC) && (get_ia32_op_type(const_op) == ia32_Const)) {
460 /* optimize tarvals */
461 class_tv = classify_tarval(tv);
462 class_negtv = classify_tarval(tarval_neg(tv));
464 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
465 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
466 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
469 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
470 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
471 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
477 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
478 set_ia32_Immop_attr(new_op, const_op);
479 set_ia32_commutative(new_op);
486 * Creates an ia32 Add.
488 * @param env The transformation environment
489 * @return the created ia32 Add node
491 static ir_node *gen_Add(ia32_transform_env_t *env) {
492 ir_node *new_op = NULL;
493 dbg_info *dbg = env->dbg;
494 ir_mode *mode = env->mode;
495 ir_graph *irg = env->irg;
496 ir_node *block = env->block;
497 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
498 ir_node *nomem = new_NoMem();
499 ir_node *expr_op, *imm_op;
500 ir_node *op1 = get_Add_left(env->irn);
501 ir_node *op2 = get_Add_right(env->irn);
503 /* Check if immediate optimization is on and */
504 /* if it's an operation with immediate. */
505 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
506 expr_op = get_expr_op(op1, op2);
508 assert((expr_op || imm_op) && "invalid operands");
510 if (mode_is_float(mode)) {
512 if (USE_SSE2(env->cg))
513 return gen_binop(env, op1, op2, new_rd_ia32_xAdd);
515 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
520 /* No expr_op means, that we have two const - one symconst and */
521 /* one tarval or another symconst - because this case is not */
522 /* covered by constant folding */
523 /* We need to check for: */
524 /* 1) symconst + const -> becomes a LEA */
525 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
526 /* linker doesn't support two symconsts */
528 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
529 /* this is the 2nd case */
530 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
531 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
532 set_ia32_am_flavour(new_op, ia32_am_OB);
534 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
537 /* this is the 1st case */
538 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
540 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
542 if (get_ia32_op_type(op1) == ia32_SymConst) {
543 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
544 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
547 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
548 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
550 set_ia32_am_flavour(new_op, ia32_am_O);
554 set_ia32_am_support(new_op, ia32_am_Source);
555 set_ia32_op_type(new_op, ia32_AddrModeS);
557 /* Lea doesn't need a Proj */
561 /* This is expr + const */
562 new_op = gen_imm_Add(env, expr_op, imm_op);
565 set_ia32_am_support(new_op, ia32_am_Dest);
568 /* This is a normal add */
569 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
572 set_ia32_am_support(new_op, ia32_am_Full);
573 set_ia32_commutative(new_op);
577 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
579 set_ia32_res_mode(new_op, mode);
581 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Add_res);
587 * Creates an ia32 Mul.
589 * @param env The transformation environment
590 * @return the created ia32 Mul node
592 static ir_node *gen_Mul(ia32_transform_env_t *env) {
593 ir_node *op1 = get_Mul_left(env->irn);
594 ir_node *op2 = get_Mul_right(env->irn);
597 if (mode_is_float(env->mode)) {
599 if (USE_SSE2(env->cg))
600 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMul);
602 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
605 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
614 * Creates an ia32 Mulh.
615 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
616 * this result while Mul returns the lower 32 bit.
618 * @param env The transformation environment
619 * @return the created ia32 Mulh node
621 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
622 ir_node *op1 = get_irn_n(env->irn, 0);
623 ir_node *op2 = get_irn_n(env->irn, 1);
624 ir_node *proj_EAX, *proj_EDX, *mulh;
627 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
628 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
629 mulh = get_Proj_pred(proj_EAX);
630 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
632 /* to be on the save side */
633 set_Proj_proj(proj_EAX, pn_EAX);
635 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
636 /* Mulh with const cannot have AM */
637 set_ia32_am_support(mulh, ia32_am_None);
640 /* Mulh cannot have AM for destination */
641 set_ia32_am_support(mulh, ia32_am_Source);
647 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
655 * Creates an ia32 And.
657 * @param env The transformation environment
658 * @return The created ia32 And node
660 static ir_node *gen_And(ia32_transform_env_t *env) {
661 ir_node *op1 = get_And_left(env->irn);
662 ir_node *op2 = get_And_right(env->irn);
664 assert (! mode_is_float(env->mode));
665 return gen_binop(env, op1, op2, new_rd_ia32_And);
671 * Creates an ia32 Or.
673 * @param env The transformation environment
674 * @return The created ia32 Or node
676 static ir_node *gen_Or(ia32_transform_env_t *env) {
677 ir_node *op1 = get_Or_left(env->irn);
678 ir_node *op2 = get_Or_right(env->irn);
680 assert (! mode_is_float(env->mode));
681 return gen_binop(env, op1, op2, new_rd_ia32_Or);
687 * Creates an ia32 Eor.
689 * @param env The transformation environment
690 * @return The created ia32 Eor node
692 static ir_node *gen_Eor(ia32_transform_env_t *env) {
693 ir_node *op1 = get_Eor_left(env->irn);
694 ir_node *op2 = get_Eor_right(env->irn);
696 assert(! mode_is_float(env->mode));
697 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
703 * Creates an ia32 Max.
705 * @param env The transformation environment
706 * @return the created ia32 Max node
708 static ir_node *gen_Max(ia32_transform_env_t *env) {
709 ir_node *op1 = get_irn_n(env->irn, 0);
710 ir_node *op2 = get_irn_n(env->irn, 1);
713 if (mode_is_float(env->mode)) {
715 if (USE_SSE2(env->cg))
716 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMax);
722 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
723 set_ia32_am_support(new_op, ia32_am_None);
724 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
733 * Creates an ia32 Min.
735 * @param env The transformation environment
736 * @return the created ia32 Min node
738 static ir_node *gen_Min(ia32_transform_env_t *env) {
739 ir_node *op1 = get_irn_n(env->irn, 0);
740 ir_node *op2 = get_irn_n(env->irn, 1);
743 if (mode_is_float(env->mode)) {
745 if (USE_SSE2(env->cg))
746 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMin);
752 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
753 set_ia32_am_support(new_op, ia32_am_None);
754 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
763 * Creates an ia32 Sub with immediate.
765 * @param env The transformation environment
766 * @param expr_op The first operator
767 * @param const_op The constant operator
768 * @return The created ia32 Sub node
770 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
771 ir_node *new_op = NULL;
772 tarval *tv = get_ia32_Immop_tarval(const_op);
773 dbg_info *dbg = env->dbg;
774 ir_graph *irg = env->irg;
775 ir_node *block = env->block;
776 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
777 ir_node *nomem = new_NoMem();
779 tarval_classification_t class_tv, class_negtv;
780 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
782 /* try to optimize to inc/dec */
783 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
784 /* optimize tarvals */
785 class_tv = classify_tarval(tv);
786 class_negtv = classify_tarval(tarval_neg(tv));
788 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
789 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
790 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
793 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
794 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
795 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
801 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
802 set_ia32_Immop_attr(new_op, const_op);
809 * Creates an ia32 Sub.
811 * @param env The transformation environment
812 * @return The created ia32 Sub node
814 static ir_node *gen_Sub(ia32_transform_env_t *env) {
815 ir_node *new_op = NULL;
816 dbg_info *dbg = env->dbg;
817 ir_mode *mode = env->mode;
818 ir_graph *irg = env->irg;
819 ir_node *block = env->block;
820 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
821 ir_node *nomem = new_NoMem();
822 ir_node *op1 = get_Sub_left(env->irn);
823 ir_node *op2 = get_Sub_right(env->irn);
824 ir_node *expr_op, *imm_op;
826 /* Check if immediate optimization is on and */
827 /* if it's an operation with immediate. */
828 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
829 expr_op = get_expr_op(op1, op2);
831 assert((expr_op || imm_op) && "invalid operands");
833 if (mode_is_float(mode)) {
835 if (USE_SSE2(env->cg))
836 return gen_binop(env, op1, op2, new_rd_ia32_xSub);
838 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
843 /* No expr_op means, that we have two const - one symconst and */
844 /* one tarval or another symconst - because this case is not */
845 /* covered by constant folding */
846 /* We need to check for: */
847 /* 1) symconst - const -> becomes a LEA */
848 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
849 /* linker doesn't support two symconsts */
851 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
852 /* this is the 2nd case */
853 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
854 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
855 set_ia32_am_sc_sign(new_op);
856 set_ia32_am_flavour(new_op, ia32_am_OB);
858 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
861 /* this is the 1st case */
862 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
864 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
866 if (get_ia32_op_type(op1) == ia32_SymConst) {
867 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
868 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
871 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
872 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
873 set_ia32_am_sc_sign(new_op);
875 set_ia32_am_flavour(new_op, ia32_am_O);
879 set_ia32_am_support(new_op, ia32_am_Source);
880 set_ia32_op_type(new_op, ia32_AddrModeS);
882 /* Lea doesn't need a Proj */
886 /* This is expr - const */
887 new_op = gen_imm_Sub(env, expr_op, imm_op);
890 set_ia32_am_support(new_op, ia32_am_Dest);
893 /* This is a normal sub */
894 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
897 set_ia32_am_support(new_op, ia32_am_Full);
901 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
903 set_ia32_res_mode(new_op, mode);
905 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Sub_res);
911 * Generates an ia32 DivMod with additional infrastructure for the
912 * register allocator if needed.
914 * @param env The transformation environment
915 * @param dividend -no comment- :)
916 * @param divisor -no comment- :)
917 * @param dm_flav flavour_Div/Mod/DivMod
918 * @return The created ia32 DivMod node
920 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
922 ir_node *edx_node, *cltd;
924 dbg_info *dbg = env->dbg;
925 ir_graph *irg = env->irg;
926 ir_node *block = env->block;
927 ir_mode *mode = env->mode;
928 ir_node *irn = env->irn;
934 mem = get_Div_mem(irn);
935 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
938 mem = get_Mod_mem(irn);
939 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
942 mem = get_DivMod_mem(irn);
943 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
949 if (mode_is_signed(mode)) {
950 /* in signed mode, we need to sign extend the dividend */
951 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
952 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
953 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
956 edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
957 set_ia32_Const_type(edx_node, ia32_Const);
958 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
961 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
963 set_ia32_n_res(res, 2);
965 /* Only one proj is used -> We must add a second proj and */
966 /* connect this one to a Keep node to eat up the second */
967 /* destroyed register. */
968 n = get_irn_n_edges(irn);
971 proj = ia32_get_proj_for_mode(irn, mode_M);
973 /* in case of two projs, one must be the memory proj */
974 if (n == 1 || (n == 2 && proj)) {
975 proj = ia32_get_res_proj(irn);
976 assert(proj && "Result proj expected");
978 if (get_irn_op(irn) == op_Div) {
979 set_Proj_proj(proj, pn_DivMod_res_div);
980 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_mod);
983 set_Proj_proj(proj, pn_DivMod_res_mod);
984 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_div);
987 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
990 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
992 set_ia32_res_mode(res, mode);
999 * Wrapper for generate_DivMod. Sets flavour_Mod.
1001 * @param env The transformation environment
1003 static ir_node *gen_Mod(ia32_transform_env_t *env) {
1004 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
1008 * Wrapper for generate_DivMod. Sets flavour_Div.
1010 * @param env The transformation environment
1012 static ir_node *gen_Div(ia32_transform_env_t *env) {
1013 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
1017 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1019 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
1020 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
1026 * Creates an ia32 floating Div.
1028 * @param env The transformation environment
1029 * @return The created ia32 xDiv node
1031 static ir_node *gen_Quot(ia32_transform_env_t *env) {
1032 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1034 ir_node *nomem = new_rd_NoMem(env->irg);
1035 ir_node *op1 = get_Quot_left(env->irn);
1036 ir_node *op2 = get_Quot_right(env->irn);
1039 if (USE_SSE2(env->cg)) {
1040 if (is_ia32_xConst(op2)) {
1041 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
1042 set_ia32_am_support(new_op, ia32_am_None);
1043 set_ia32_Immop_attr(new_op, op2);
1046 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1047 set_ia32_am_support(new_op, ia32_am_Source);
1051 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1052 set_ia32_am_support(new_op, ia32_am_Source);
1054 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
1055 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1063 * Creates an ia32 Shl.
1065 * @param env The transformation environment
1066 * @return The created ia32 Shl node
1068 static ir_node *gen_Shl(ia32_transform_env_t *env) {
1069 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
1075 * Creates an ia32 Shr.
1077 * @param env The transformation environment
1078 * @return The created ia32 Shr node
1080 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1081 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1087 * Creates an ia32 Shrs.
1089 * @param env The transformation environment
1090 * @return The created ia32 Shrs node
1092 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1093 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1099 * Creates an ia32 RotL.
1101 * @param env The transformation environment
1102 * @param op1 The first operator
1103 * @param op2 The second operator
1104 * @return The created ia32 RotL node
1106 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1107 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1113 * Creates an ia32 RotR.
1114 * NOTE: There is no RotR with immediate because this would always be a RotL
1115 * "imm-mode_size_bits" which can be pre-calculated.
1117 * @param env The transformation environment
1118 * @param op1 The first operator
1119 * @param op2 The second operator
1120 * @return The created ia32 RotR node
1122 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1123 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1129 * Creates an ia32 RotR or RotL (depending on the found pattern).
1131 * @param env The transformation environment
1132 * @return The created ia32 RotL or RotR node
1134 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1135 ir_node *rotate = NULL;
1136 ir_node *op1 = get_Rot_left(env->irn);
1137 ir_node *op2 = get_Rot_right(env->irn);
1139 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1140 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1141 that means we can create a RotR instead of an Add and a RotL */
1144 ir_node *pred = get_Proj_pred(op2);
1146 if (is_ia32_Add(pred)) {
1147 ir_node *pred_pred = get_irn_n(pred, 2);
1148 tarval *tv = get_ia32_Immop_tarval(pred);
1149 long bits = get_mode_size_bits(env->mode);
1151 if (is_Proj(pred_pred)) {
1152 pred_pred = get_Proj_pred(pred_pred);
1155 if (is_ia32_Minus(pred_pred) &&
1156 tarval_is_long(tv) &&
1157 get_tarval_long(tv) == bits)
1159 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1160 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1167 rotate = gen_RotL(env, op1, op2);
1176 * Transforms a Minus node.
1178 * @param env The transformation environment
1179 * @param op The Minus operand
1180 * @return The created ia32 Minus node
1182 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1187 if (mode_is_float(env->mode)) {
1189 if (USE_SSE2(env->cg)) {
1190 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1191 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1192 ir_node *nomem = new_rd_NoMem(env->irg);
1194 new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1196 size = get_mode_size_bits(env->mode);
1197 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1199 set_ia32_sc(new_op, name);
1201 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1203 set_ia32_res_mode(new_op, env->mode);
1204 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1206 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
1209 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1210 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1214 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1221 * Transforms a Minus node.
1223 * @param env The transformation environment
1224 * @return The created ia32 Minus node
1226 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1227 return gen_Minus_ex(env, get_Minus_op(env->irn));
1232 * Transforms a Not node.
1234 * @param env The transformation environment
1235 * @return The created ia32 Not node
1237 static ir_node *gen_Not(ia32_transform_env_t *env) {
1238 assert (! mode_is_float(env->mode));
1239 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1245 * Transforms an Abs node.
1247 * @param env The transformation environment
1248 * @return The created ia32 Abs node
1250 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1251 ir_node *res, *p_eax, *p_edx;
1252 dbg_info *dbg = env->dbg;
1253 ir_mode *mode = env->mode;
1254 ir_graph *irg = env->irg;
1255 ir_node *block = env->block;
1256 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1257 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1258 ir_node *nomem = new_NoMem();
1259 ir_node *op = get_Abs_op(env->irn);
1263 if (mode_is_float(mode)) {
1265 if (USE_SSE2(env->cg)) {
1266 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1268 size = get_mode_size_bits(mode);
1269 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1271 set_ia32_sc(res, name);
1273 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1275 set_ia32_res_mode(res, mode);
1276 set_ia32_immop_type(res, ia32_ImmSymConst);
1278 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
1281 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1282 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1286 res = new_rd_ia32_Cdq(dbg, irg, block, op);
1287 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1288 set_ia32_res_mode(res, mode);
1290 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
1291 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
1293 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1294 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1295 set_ia32_res_mode(res, mode);
1297 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
1299 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1300 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1301 set_ia32_res_mode(res, mode);
1303 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
1312 * Transforms a Load.
1314 * @param env The transformation environment
1315 * @return the created ia32 Load node
1317 static ir_node *gen_Load(ia32_transform_env_t *env) {
1318 ir_node *node = env->irn;
1319 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1320 ir_node *ptr = get_Load_ptr(node);
1321 ir_node *lptr = ptr;
1322 ir_mode *mode = get_Load_mode(node);
1325 ia32_am_flavour_t am_flav = ia32_am_B;
1327 /* address might be a constant (symconst or absolute address) */
1328 if (is_ia32_Const(ptr)) {
1333 if (mode_is_float(mode)) {
1335 if (USE_SSE2(env->cg))
1336 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1338 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1341 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1344 /* base is an constant address */
1346 if (get_ia32_op_type(ptr) == ia32_SymConst) {
1347 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1348 am_flav = ia32_am_N;
1351 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1352 am_flav = ia32_am_O;
1356 set_ia32_am_support(new_op, ia32_am_Source);
1357 set_ia32_op_type(new_op, ia32_AddrModeS);
1358 set_ia32_am_flavour(new_op, am_flav);
1359 set_ia32_ls_mode(new_op, mode);
1362 check for special case: the loaded value might not be used (optimized, volatile, ...)
1363 we add a Proj + Keep for volatile loads and ignore all other cases
1365 if (! get_proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1366 /* add a result proj and a Keep to produce a pseudo use */
1367 ir_node *proj = new_r_Proj(env->irg, env->block, new_op, mode, pn_ia32_Load_res);
1368 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), env->irg, env->block, 1, &proj);
1371 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1379 * Transforms a Store.
1381 * @param env The transformation environment
1382 * @return the created ia32 Store node
1384 static ir_node *gen_Store(ia32_transform_env_t *env) {
1385 ir_node *node = env->irn;
1386 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1387 ir_node *val = get_Store_value(node);
1388 ir_node *ptr = get_Store_ptr(node);
1389 ir_node *sptr = ptr;
1390 ir_node *mem = get_Store_mem(node);
1391 ir_mode *mode = get_irn_link(node);
1392 ir_node *sval = val;
1395 ia32_am_flavour_t am_flav = ia32_am_B;
1396 ia32_immop_type_t immop = ia32_ImmNone;
1398 if (! mode_is_float(mode)) {
1399 /* in case of storing a const (but not a symconst) -> make it an attribute */
1400 if (is_ia32_Cnst(val)) {
1401 switch (get_ia32_op_type(val)) {
1403 immop = ia32_ImmConst;
1406 immop = ia32_ImmSymConst;
1409 assert(0 && "unsupported Const type");
1415 /* address might be a constant (symconst or absolute address) */
1416 if (is_ia32_Const(ptr)) {
1421 if (mode_is_float(mode)) {
1423 if (USE_SSE2(env->cg))
1424 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1426 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1428 else if (get_mode_size_bits(mode) == 8) {
1429 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1432 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1435 /* stored const is an attribute (saves a register) */
1436 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1437 set_ia32_Immop_attr(new_op, val);
1440 /* base is an constant address */
1442 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1443 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1444 am_flav = ia32_am_N;
1447 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1448 am_flav = ia32_am_O;
1452 set_ia32_am_support(new_op, ia32_am_Dest);
1453 set_ia32_op_type(new_op, ia32_AddrModeD);
1454 set_ia32_am_flavour(new_op, am_flav);
1455 set_ia32_ls_mode(new_op, mode);
1456 set_ia32_immop_type(new_op, immop);
1458 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1466 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1468 * @param env The transformation environment
1469 * @return The transformed node.
1471 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1472 dbg_info *dbg = env->dbg;
1473 ir_graph *irg = env->irg;
1474 ir_node *block = env->block;
1475 ir_node *node = env->irn;
1476 ir_node *sel = get_Cond_selector(node);
1477 ir_mode *sel_mode = get_irn_mode(sel);
1478 ir_node *res = NULL;
1479 ir_node *pred = NULL;
1480 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1481 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1483 if (is_Proj(sel) && sel_mode == mode_b) {
1484 ir_node *nomem = new_NoMem();
1486 pred = get_Proj_pred(sel);
1488 /* get both compare operators */
1489 cmp_a = get_Cmp_left(pred);
1490 cmp_b = get_Cmp_right(pred);
1492 /* check if we can use a CondJmp with immediate */
1493 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1494 expr = get_expr_op(cmp_a, cmp_b);
1497 pn_Cmp pnc = get_Proj_proj(sel);
1499 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1500 if (get_ia32_op_type(cnst) == ia32_Const &&
1501 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1503 /* a Cmp A =/!= 0 */
1504 ir_node *op1 = expr;
1505 ir_node *op2 = expr;
1506 ir_node *and = skip_Proj(expr);
1507 const char *cnst = NULL;
1509 /* check, if expr is an only once used And operation */
1510 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1511 op1 = get_irn_n(and, 2);
1512 op2 = get_irn_n(and, 3);
1514 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1516 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1517 set_ia32_pncode(res, get_Proj_proj(sel));
1518 set_ia32_res_mode(res, get_irn_mode(op1));
1521 copy_ia32_Immop_attr(res, and);
1524 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1529 if (mode_is_float(get_irn_mode(expr))) {
1531 if (USE_SSE2(env->cg))
1532 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1538 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1540 set_ia32_Immop_attr(res, cnst);
1541 set_ia32_res_mode(res, get_irn_mode(expr));
1544 if (mode_is_float(get_irn_mode(cmp_a))) {
1546 if (USE_SSE2(env->cg))
1547 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1550 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1551 proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
1552 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1556 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1557 set_ia32_commutative(res);
1559 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1562 set_ia32_pncode(res, get_Proj_proj(sel));
1563 //set_ia32_am_support(res, ia32_am_Source);
1566 /* determine the smallest switch case value */
1567 int switch_min = INT_MAX;
1568 const ir_edge_t *edge;
1571 foreach_out_edge(node, edge) {
1572 int pn = get_Proj_proj(get_edge_src_irn(edge));
1573 switch_min = pn < switch_min ? pn : switch_min;
1577 /* if smallest switch case is not 0 we need an additional sub */
1578 snprintf(buf, sizeof(buf), "%d", switch_min);
1579 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1580 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1581 sub_ia32_am_offs(res, buf);
1582 set_ia32_am_flavour(res, ia32_am_OB);
1583 set_ia32_am_support(res, ia32_am_Source);
1584 set_ia32_op_type(res, ia32_AddrModeS);
1587 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1588 set_ia32_pncode(res, get_Cond_defaultProj(node));
1589 set_ia32_res_mode(res, get_irn_mode(sel));
1592 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1599 * Transforms a CopyB node.
1601 * @param env The transformation environment
1602 * @return The transformed node.
1604 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1605 ir_node *res = NULL;
1606 dbg_info *dbg = env->dbg;
1607 ir_graph *irg = env->irg;
1608 ir_mode *mode = env->mode;
1609 ir_node *block = env->block;
1610 ir_node *node = env->irn;
1611 ir_node *src = get_CopyB_src(node);
1612 ir_node *dst = get_CopyB_dst(node);
1613 ir_node *mem = get_CopyB_mem(node);
1614 int size = get_type_size_bytes(get_CopyB_type(node));
1617 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1618 /* then we need the size explicitly in ECX. */
1619 if (size >= 16 * 4) {
1620 rem = size & 0x3; /* size % 4 */
1623 res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
1624 set_ia32_op_type(res, ia32_Const);
1625 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1627 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1628 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1631 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1632 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1633 set_ia32_immop_type(res, ia32_ImmConst);
1636 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1644 * Transforms a Mux node into CMov.
1646 * @param env The transformation environment
1647 * @return The transformed node.
1649 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1651 ir_node *node = env->irn;
1652 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1653 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1655 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1662 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *cmp_a, ir_node *cmp_b, \
1663 ir_node *psi_true, ir_node *psi_default, ir_mode *mode);
1666 * Transforms a Psi node into CMov.
1668 * @param env The transformation environment
1669 * @return The transformed node.
1671 static ir_node *gen_Psi(ia32_transform_env_t *env) {
1672 ia32_code_gen_t *cg = env->cg;
1673 dbg_info *dbg = env->dbg;
1674 ir_graph *irg = env->irg;
1675 ir_mode *mode = env->mode;
1676 ir_node *block = env->block;
1677 ir_node *node = env->irn;
1678 ir_node *cmp_proj = get_Mux_sel(node);
1679 ir_node *psi_true = get_Psi_val(node, 0);
1680 ir_node *psi_default = get_Psi_default(node);
1681 ir_node *noreg = ia32_new_NoReg_gp(cg);
1682 ir_node *nomem = new_rd_NoMem(irg);
1683 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
1686 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
1688 cmp = get_Proj_pred(cmp_proj);
1689 cmp_a = get_Cmp_left(cmp);
1690 cmp_b = get_Cmp_right(cmp);
1691 pnc = get_Proj_proj(cmp_proj);
1693 if (mode_is_float(mode)) {
1694 /* floating point psi */
1697 /* 1st case: compare operands are float too */
1699 /* psi(cmp(a, b), t, f) can be done as: */
1700 /* tmp = cmp a, b */
1701 /* tmp2 = t and tmp */
1702 /* tmp3 = f and not tmp */
1703 /* res = tmp2 or tmp3 */
1705 /* in case the compare operands are int, we move them into xmm register */
1706 if (! mode_is_float(get_irn_mode(cmp_a))) {
1707 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, node, mode_D);
1708 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, node, mode_D);
1710 pnc |= 8; /* transform integer compare to fp compare */
1713 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1714 set_ia32_pncode(new_op, pnc);
1715 set_ia32_am_support(new_op, ia32_am_Source);
1716 set_ia32_res_mode(new_op, mode);
1717 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1718 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xCmp_res);
1720 and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, psi_true, new_op, nomem);
1721 set_ia32_am_support(and1, ia32_am_None);
1722 set_ia32_res_mode(and1, mode);
1723 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
1724 and1 = new_rd_Proj(dbg, irg, block, and1, mode, pn_ia32_xAnd_res);
1726 and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, psi_default, nomem);
1727 set_ia32_am_support(and2, ia32_am_None);
1728 set_ia32_res_mode(and2, mode);
1729 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
1730 and2 = new_rd_Proj(dbg, irg, block, and2, mode, pn_ia32_xAndNot_res);
1732 new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
1733 set_ia32_am_support(new_op, ia32_am_None);
1734 set_ia32_res_mode(new_op, mode);
1735 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1736 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xOr_res);
1740 new_op = new_rd_ia32_vfCMov(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1741 set_ia32_pncode(new_op, pnc);
1742 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1747 construct_binop_func *set_func = NULL;
1748 cmov_func_t *cmov_func = NULL;
1750 if (mode_is_float(get_irn_mode(cmp_a))) {
1751 /* 1st case: compare operands are floats */
1756 set_func = new_rd_ia32_xCmpSet;
1757 cmov_func = new_rd_ia32_xCmpCMov;
1761 set_func = new_rd_ia32_vfCmpSet;
1762 cmov_func = new_rd_ia32_vfCmpCMov;
1765 pnc &= 7; /* fp compare -> int compare */
1768 /* 2nd case: compare operand are integer too */
1769 set_func = new_rd_ia32_CmpSet;
1770 cmov_func = new_rd_ia32_CmpCMov;
1773 /* create the nodes */
1775 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
1776 if (is_ia32_Const_0(cmp_b) && is_Proj(cmp_a) && (is_ia32_And(get_Proj_pred(cmp_a)) || is_ia32_Or(get_Proj_pred(cmp_a)))) {
1777 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1778 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1779 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1780 set_ia32_pncode(new_op, pnc);
1782 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1783 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1784 /* we invert condition and set default to 0 */
1785 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1786 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
1789 /* otherwise: use CMOVcc */
1790 new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, cmp_a, psi_true, psi_default, mode);
1791 set_ia32_pncode(new_op, pnc);
1794 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1798 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1799 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1800 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1801 set_ia32_pncode(get_Proj_pred(new_op), pnc);
1802 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1804 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1805 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1806 /* we invert condition and set default to 0 */
1807 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1808 set_ia32_pncode(get_Proj_pred(new_op), get_inversed_pnc(pnc));
1809 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1812 /* otherwise: use CMOVcc */
1813 new_op = cmov_func(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1814 set_ia32_pncode(new_op, pnc);
1815 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1825 * Following conversion rules apply:
1829 * 1) n bit -> m bit n > m (downscale)
1830 * a) target is signed: movsx
1831 * b) target is unsigned: and with lower bits sets
1832 * 2) n bit -> m bit n == m (sign change)
1834 * 3) n bit -> m bit n < m (upscale)
1835 * a) source is signed: movsx
1836 * b) source is unsigned: and with lower bits sets
1840 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1844 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1845 * if target mode < 32bit: additional INT -> INT conversion (see above)
1849 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1850 * x87 is mode_E internally, conversions happen only at load and store
1851 * in non-strict semantic
1855 * Create a conversion from x87 state register to general purpose.
1857 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1858 ia32_code_gen_t *cg = env->cg;
1859 entity *ent = cg->fp_to_gp;
1860 ir_graph *irg = env->irg;
1861 ir_node *block = env->block;
1862 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1863 ir_node *op = get_Conv_op(env->irn);
1864 ir_node *fist, *mem, *load;
1867 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1868 ent = cg->fp_to_gp =
1869 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1873 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
1875 set_ia32_frame_ent(fist, ent);
1876 set_ia32_use_frame(fist);
1877 set_ia32_am_support(fist, ia32_am_Dest);
1878 set_ia32_op_type(fist, ia32_AddrModeD);
1879 set_ia32_am_flavour(fist, ia32_B);
1880 set_ia32_ls_mode(fist, mode_F);
1882 mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
1885 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1887 set_ia32_frame_ent(load, ent);
1888 set_ia32_use_frame(load);
1889 set_ia32_am_support(load, ia32_am_Source);
1890 set_ia32_op_type(load, ia32_AddrModeS);
1891 set_ia32_am_flavour(load, ia32_B);
1892 set_ia32_ls_mode(load, tgt_mode);
1894 return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
1898 * Create a conversion from x87 state register to general purpose.
1900 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1901 ia32_code_gen_t *cg = env->cg;
1902 entity *ent = cg->gp_to_fp;
1903 ir_graph *irg = env->irg;
1904 ir_node *block = env->block;
1905 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1906 ir_node *nomem = get_irg_no_mem(irg);
1907 ir_node *op = get_Conv_op(env->irn);
1908 ir_node *fild, *store, *mem;
1912 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
1913 ent = cg->gp_to_fp =
1914 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
1917 /* first convert to 32 bit */
1918 src_bits = get_mode_size_bits(src_mode);
1919 if (src_bits == 8) {
1920 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
1921 op = new_r_Proj(irg, block, op, mode_Is, 0);
1923 else if (src_bits < 32) {
1924 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
1925 op = new_r_Proj(irg, block, op, mode_Is, 0);
1929 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
1931 set_ia32_frame_ent(store, ent);
1932 set_ia32_use_frame(store);
1934 set_ia32_am_support(store, ia32_am_Dest);
1935 set_ia32_op_type(store, ia32_AddrModeD);
1936 set_ia32_am_flavour(store, ia32_B);
1937 set_ia32_ls_mode(store, mode_Is);
1939 mem = new_r_Proj(irg, block, store, mode_M, 0);
1942 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1944 set_ia32_frame_ent(fild, ent);
1945 set_ia32_use_frame(fild);
1946 set_ia32_am_support(fild, ia32_am_Source);
1947 set_ia32_op_type(fild, ia32_AddrModeS);
1948 set_ia32_am_flavour(fild, ia32_B);
1949 set_ia32_ls_mode(fild, mode_F);
1951 return new_r_Proj(irg, block, fild, mode_F, 0);
1955 * Transforms a Conv node.
1957 * @param env The transformation environment
1958 * @return The created ia32 Conv node
1960 static ir_node *gen_Conv(ia32_transform_env_t *env) {
1961 dbg_info *dbg = env->dbg;
1962 ir_graph *irg = env->irg;
1963 ir_node *op = get_Conv_op(env->irn);
1964 ir_mode *src_mode = get_irn_mode(op);
1965 ir_mode *tgt_mode = env->mode;
1966 int src_bits = get_mode_size_bits(src_mode);
1967 int tgt_bits = get_mode_size_bits(tgt_mode);
1969 ir_node *block = env->block;
1970 ir_node *new_op = NULL;
1971 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1972 ir_node *nomem = new_rd_NoMem(irg);
1974 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1976 if (src_mode == tgt_mode) {
1977 /* this can happen when changing mode_P to mode_Is */
1978 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1979 edges_reroute(env->irn, op, irg);
1981 else if (mode_is_float(src_mode)) {
1982 /* we convert from float ... */
1983 if (mode_is_float(tgt_mode)) {
1985 if (USE_SSE2(env->cg)) {
1986 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1987 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
1988 pn = pn_ia32_Conv_FP2FP_res;
1991 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
1992 edges_reroute(env->irn, op, irg);
1997 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1998 if (USE_SSE2(env->cg)) {
1999 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
2000 pn = pn_ia32_Conv_FP2I_res;
2003 return gen_x87_fp_to_gp(env, tgt_mode);
2005 /* if target mode is not int: add an additional downscale convert */
2006 if (tgt_bits < 32) {
2007 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2008 set_ia32_am_support(new_op, ia32_am_Source);
2009 set_ia32_tgt_mode(new_op, tgt_mode);
2010 set_ia32_src_mode(new_op, src_mode);
2012 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, pn_ia32_Conv_FP2I_res);
2014 if (tgt_bits == 8 || src_bits == 8) {
2015 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
2016 pn = pn_ia32_Conv_I2I8Bit_res;
2019 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
2020 pn = pn_ia32_Conv_I2I_res;
2026 /* we convert from int ... */
2027 if (mode_is_float(tgt_mode)) {
2030 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
2031 if (USE_SSE2(env->cg)) {
2032 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
2033 pn = pn_ia32_Conv_I2FP_res;
2036 return gen_x87_gp_to_fp(env, src_mode);
2040 if (get_mode_size_bits(src_mode) == tgt_bits) {
2041 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
2042 edges_reroute(env->irn, op, irg);
2045 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2046 if (tgt_bits == 8 || src_bits == 8) {
2047 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
2048 pn = pn_ia32_Conv_I2I8Bit_res;
2051 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
2052 pn = pn_ia32_Conv_I2I_res;
2059 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2060 set_ia32_tgt_mode(new_op, tgt_mode);
2061 set_ia32_src_mode(new_op, src_mode);
2063 set_ia32_am_support(new_op, ia32_am_Source);
2065 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, pn);
2073 /********************************************
2076 * | |__ ___ _ __ ___ __| | ___ ___
2077 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2078 * | |_) | __/ | | | (_) | (_| | __/\__ \
2079 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2081 ********************************************/
2084 * Decides in which block the transformed StackParam should be placed.
2085 * If the StackParam has more than one user, the dominator block of
2086 * the users will be returned. In case of only one user, this is either
2087 * the user block or, in case of a Phi, the predecessor block of the Phi.
2089 static ir_node *get_block_transformed_stack_param(ir_node *irn) {
2090 ir_node *dom_bl = NULL;
2092 if (get_irn_n_edges(irn) == 1) {
2093 ir_node *src = get_edge_src_irn(get_irn_out_edge_first(irn));
2095 if (! is_Phi(src)) {
2096 dom_bl = get_nodes_block(src);
2099 /* Determine on which in position of the Phi the irn is */
2100 /* and get the corresponding cfg predecessor block. */
2102 int i = get_irn_pred_pos(src, irn);
2103 assert(i >= 0 && "kaputt");
2104 dom_bl = get_Block_cfgpred_block(get_nodes_block(src), i);
2108 dom_bl = node_users_smallest_common_dominator(irn, 1);
2111 assert(dom_bl && "dominator block not found");
2116 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
2117 ir_node *new_op = NULL;
2118 ir_node *node = env->irn;
2119 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2120 ir_node *mem = new_rd_NoMem(env->irg);
2121 ir_node *ptr = get_irn_n(node, 0);
2122 entity *ent = be_get_frame_entity(node);
2123 ir_mode *mode = env->mode;
2125 /* choose the block where to place the load */
2126 env->block = get_block_transformed_stack_param(node);
2128 if (mode_is_float(mode)) {
2130 if (USE_SSE2(env->cg))
2131 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2133 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2136 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2139 set_ia32_frame_ent(new_op, ent);
2140 set_ia32_use_frame(new_op);
2142 set_ia32_am_support(new_op, ia32_am_Source);
2143 set_ia32_op_type(new_op, ia32_AddrModeS);
2144 set_ia32_am_flavour(new_op, ia32_B);
2145 set_ia32_ls_mode(new_op, mode);
2147 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2149 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
2153 * Transforms a FrameAddr into an ia32 Add.
2155 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
2156 ir_node *new_op = NULL;
2157 ir_node *node = env->irn;
2158 ir_node *op = get_irn_n(node, 0);
2159 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2160 ir_node *nomem = new_rd_NoMem(env->irg);
2162 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
2163 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
2164 set_ia32_am_support(new_op, ia32_am_Full);
2165 set_ia32_use_frame(new_op);
2166 set_ia32_immop_type(new_op, ia32_ImmConst);
2167 set_ia32_commutative(new_op);
2169 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2171 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
2175 * Transforms a FrameLoad into an ia32 Load.
2177 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
2178 ir_node *new_op = NULL;
2179 ir_node *node = env->irn;
2180 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2181 ir_node *mem = get_irn_n(node, 0);
2182 ir_node *ptr = get_irn_n(node, 1);
2183 entity *ent = be_get_frame_entity(node);
2184 ir_mode *mode = get_type_mode(get_entity_type(ent));
2186 if (mode_is_float(mode)) {
2188 if (USE_SSE2(env->cg))
2189 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2191 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2194 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2196 set_ia32_frame_ent(new_op, ent);
2197 set_ia32_use_frame(new_op);
2199 set_ia32_am_support(new_op, ia32_am_Source);
2200 set_ia32_op_type(new_op, ia32_AddrModeS);
2201 set_ia32_am_flavour(new_op, ia32_B);
2202 set_ia32_ls_mode(new_op, mode);
2204 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2211 * Transforms a FrameStore into an ia32 Store.
2213 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
2214 ir_node *new_op = NULL;
2215 ir_node *node = env->irn;
2216 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2217 ir_node *mem = get_irn_n(node, 0);
2218 ir_node *ptr = get_irn_n(node, 1);
2219 ir_node *val = get_irn_n(node, 2);
2220 entity *ent = be_get_frame_entity(node);
2221 ir_mode *mode = get_irn_mode(val);
2223 if (mode_is_float(mode)) {
2225 if (USE_SSE2(env->cg))
2226 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2228 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2230 else if (get_mode_size_bits(mode) == 8) {
2231 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2234 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2237 set_ia32_frame_ent(new_op, ent);
2238 set_ia32_use_frame(new_op);
2240 set_ia32_am_support(new_op, ia32_am_Dest);
2241 set_ia32_op_type(new_op, ia32_AddrModeD);
2242 set_ia32_am_flavour(new_op, ia32_B);
2243 set_ia32_ls_mode(new_op, mode);
2245 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2251 * This function just sets the register for the Unknown node
2252 * as this is not done during register allocation because Unknown
2253 * is an "ignore" node.
2255 static ir_node *gen_Unknown(ia32_transform_env_t *env) {
2256 ir_mode *mode = env->mode;
2257 ir_node *irn = env->irn;
2259 if (mode_is_float(mode)) {
2260 if (USE_SSE2(env->cg))
2261 arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
2263 arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
2265 else if (mode_is_int(mode) || mode_is_reference(mode)) {
2266 arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
2269 assert(0 && "unsupported Unknown-Mode");
2275 /**********************************************************************
2278 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2279 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2280 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2281 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2283 **********************************************************************/
2285 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2287 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2290 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2291 ir_node *val, ir_node *mem);
2294 * Transforms a lowered Load into a "real" one.
2296 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, construct_load_func func, char fp_unit) {
2297 ir_node *node = env->irn;
2298 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2299 ir_mode *mode = get_ia32_ls_mode(node);
2302 ia32_am_flavour_t am_flav = ia32_B;
2305 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2306 lowering we have x87 nodes, so we need to enforce simulation.
2308 if (mode_is_float(mode)) {
2310 if (fp_unit == fp_x87)
2314 new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1));
2315 am_offs = get_ia32_am_offs(node);
2319 add_ia32_am_offs(new_op, am_offs);
2322 set_ia32_am_support(new_op, ia32_am_Source);
2323 set_ia32_op_type(new_op, ia32_AddrModeS);
2324 set_ia32_am_flavour(new_op, am_flav);
2325 set_ia32_ls_mode(new_op, mode);
2326 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2327 set_ia32_use_frame(new_op);
2329 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2335 * Transforms a lowered Store into a "real" one.
2337 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, construct_store_func func, char fp_unit) {
2338 ir_node *node = env->irn;
2339 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2340 ir_mode *mode = get_ia32_ls_mode(node);
2343 ia32_am_flavour_t am_flav = ia32_B;
2346 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2347 lowering we have x87 nodes, so we need to enforce simulation.
2349 if (mode_is_float(mode)) {
2351 if (fp_unit == fp_x87)
2355 new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1), get_irn_n(node, 2));
2357 if ((am_offs = get_ia32_am_offs(node)) != NULL) {
2359 add_ia32_am_offs(new_op, am_offs);
2362 set_ia32_am_support(new_op, ia32_am_Dest);
2363 set_ia32_op_type(new_op, ia32_AddrModeD);
2364 set_ia32_am_flavour(new_op, am_flav);
2365 set_ia32_ls_mode(new_op, mode);
2366 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2367 set_ia32_use_frame(new_op);
2369 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2376 * Transforms an ia32_l_XXX into a "real" XXX node
2378 * @param env The transformation environment
2379 * @return the created ia32 XXX node
2381 #define GEN_LOWERED_OP(op) \
2382 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2383 if (mode_is_float(env->mode)) \
2385 return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2388 #define GEN_LOWERED_x87_OP(op) \
2389 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2391 FORCE_x87(env->cg); \
2392 new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2393 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_None); \
2397 #define GEN_LOWERED_UNOP(op) \
2398 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2399 return gen_unop(env, get_unop_op(env->irn), new_rd_ia32_##op); \
2402 #define GEN_LOWERED_SHIFT_OP(op) \
2403 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2404 return gen_shift_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2407 #define GEN_LOWERED_LOAD(op, fp_unit) \
2408 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2409 return gen_lowered_Load(env, new_rd_ia32_##op, fp_unit); \
2412 #define GEN_LOWERED_STORE(op, fp_unit) \
2413 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2414 return gen_lowered_Store(env, new_rd_ia32_##op, fp_unit); \
2417 GEN_LOWERED_OP(AddC)
2419 GEN_LOWERED_OP(SubC)
2423 GEN_LOWERED_x87_OP(vfdiv)
2424 GEN_LOWERED_x87_OP(vfmul)
2425 GEN_LOWERED_x87_OP(vfsub)
2427 GEN_LOWERED_UNOP(Minus)
2429 GEN_LOWERED_LOAD(vfild, fp_x87)
2430 GEN_LOWERED_LOAD(Load, fp_none)
2431 GEN_LOWERED_STORE(vfist, fp_x87)
2432 GEN_LOWERED_STORE(Store, fp_none)
2435 * Transforms a l_MulS into a "real" MulS node.
2437 * @param env The transformation environment
2438 * @return the created ia32 MulS node
2440 static ir_node *gen_ia32_l_MulS(ia32_transform_env_t *env) {
2442 /* l_MulS is already a mode_T node, so we create the MulS in the normal way */
2443 /* and then skip the result Proj, because all needed Projs are already there. */
2445 ir_node *new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_MulS);
2446 ir_node *muls = get_Proj_pred(new_op);
2448 /* MulS cannot have AM for destination */
2449 if (get_ia32_am_support(muls) != ia32_am_None)
2450 set_ia32_am_support(muls, ia32_am_Source);
2455 GEN_LOWERED_SHIFT_OP(Shl)
2456 GEN_LOWERED_SHIFT_OP(Shr)
2457 GEN_LOWERED_SHIFT_OP(Shrs)
2460 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
2461 * op1 - target to be shifted
2462 * op2 - contains bits to be shifted into target
2464 * Only op3 can be an immediate.
2466 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, ir_node *count) {
2467 ir_node *new_op = NULL;
2468 ir_mode *mode = env->mode;
2469 dbg_info *dbg = env->dbg;
2470 ir_graph *irg = env->irg;
2471 ir_node *block = env->block;
2472 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2473 ir_node *nomem = new_NoMem();
2476 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
2478 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
2480 /* Check if immediate optimization is on and */
2481 /* if it's an operation with immediate. */
2482 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, count) : NULL;
2484 /* Limit imm_op within range imm8 */
2486 tv = get_ia32_Immop_tarval(imm_op);
2489 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
2490 set_ia32_Immop_tarval(imm_op, tv);
2497 /* integer operations */
2499 /* This is ShiftD with const */
2500 DB((mod, LEVEL_1, "ShiftD with immediate ..."));
2502 if (is_ia32_l_ShlD(env->irn))
2503 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, op1, op2, noreg, nomem);
2505 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, op1, op2, noreg, nomem);
2506 set_ia32_Immop_attr(new_op, imm_op);
2509 /* This is a normal ShiftD */
2510 DB((mod, LEVEL_1, "ShiftD binop ..."));
2511 if (is_ia32_l_ShlD(env->irn))
2512 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, op1, op2, count, nomem);
2514 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, op1, op2, count, nomem);
2517 /* set AM support */
2518 set_ia32_am_support(new_op, ia32_am_Dest);
2520 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2522 set_ia32_res_mode(new_op, mode);
2523 set_ia32_emit_cl(new_op);
2525 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
2528 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env) {
2529 return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2));
2532 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env) {
2533 return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2));
2537 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
2539 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env) {
2540 ia32_code_gen_t *cg = env->cg;
2541 ir_node *res = NULL;
2542 ir_node *ptr = get_irn_n(env->irn, 0);
2543 ir_node *val = get_irn_n(env->irn, 1);
2544 ir_node *mem = get_irn_n(env->irn, 2);
2547 ir_node *noreg = ia32_new_NoReg_gp(cg);
2549 /* Store x87 -> MEM */
2550 res = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2551 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2552 set_ia32_use_frame(res);
2553 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2554 set_ia32_am_support(res, ia32_am_Dest);
2555 set_ia32_am_flavour(res, ia32_B);
2556 res = new_rd_Proj(env->dbg, env->irg, env->block, res, mode_M, pn_ia32_vfst_M);
2558 /* Load MEM -> SSE */
2559 res = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, res);
2560 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2561 set_ia32_use_frame(res);
2562 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2563 set_ia32_am_support(res, ia32_am_Source);
2564 set_ia32_am_flavour(res, ia32_B);
2565 res = new_rd_Proj(env->dbg, env->irg, env->block, res, get_ia32_ls_mode(env->irn), pn_ia32_xLoad_res);
2568 /* SSE unit is not used -> skip this node. */
2571 edges_reroute(env->irn, val, env->irg);
2572 for (i = get_irn_arity(env->irn) - 1; i >= 0; i--)
2573 set_irn_n(env->irn, i, get_irg_bad(env->irg));
2580 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
2582 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env) {
2583 ia32_code_gen_t *cg = env->cg;
2584 ir_node *res = NULL;
2585 ir_node *ptr = get_irn_n(env->irn, 0);
2586 ir_node *val = get_irn_n(env->irn, 1);
2587 ir_node *mem = get_irn_n(env->irn, 2);
2590 ir_node *noreg = ia32_new_NoReg_gp(cg);
2592 /* Store SSE -> MEM */
2593 res = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2594 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2595 set_ia32_use_frame(res);
2596 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2597 set_ia32_am_support(res, ia32_am_Dest);
2598 set_ia32_am_flavour(res, ia32_B);
2599 res = new_rd_Proj(env->dbg, env->irg, env->block, res, mode_M, pn_ia32_xStore_M);
2601 /* Load MEM -> x87 */
2602 res = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2603 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2604 set_ia32_use_frame(res);
2605 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2606 set_ia32_am_support(res, ia32_am_Source);
2607 set_ia32_am_flavour(res, ia32_B);
2608 res = new_rd_Proj(env->dbg, env->irg, env->block, res, get_ia32_ls_mode(env->irn), pn_ia32_vfld_res);
2611 /* SSE unit is not used -> skip this node. */
2614 edges_reroute(env->irn, val, env->irg);
2615 for (i = get_irn_arity(env->irn) - 1; i >= 0; i--)
2616 set_irn_n(env->irn, i, get_irg_bad(env->irg));
2622 /*********************************************************
2625 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
2626 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
2627 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
2628 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
2630 *********************************************************/
2633 * the BAD transformer.
2635 static ir_node *bad_transform(ia32_transform_env_t *env) {
2636 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2642 * Enters all transform functions into the generic pointer
2644 void ia32_register_transformers(void) {
2645 ir_op *op_Max, *op_Min, *op_Mulh;
2647 /* first clear the generic function pointer for all ops */
2648 clear_irp_opcodes_generic_func();
2650 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2651 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
2685 /* transform ops from intrinsic lowering */
2706 GEN(ia32_l_X87toSSE);
2707 GEN(ia32_l_SSEtoX87);
2722 /* constant transformation happens earlier */
2746 /* set the register for all Unknown nodes */
2749 op_Max = get_op_Max();
2752 op_Min = get_op_Min();
2755 op_Mulh = get_op_Mulh();
2764 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
2767 * Transforms the given firm node (and maybe some other related nodes)
2768 * into one or more assembler nodes.
2770 * @param node the firm node
2771 * @param env the debug module
2773 void ia32_transform_node(ir_node *node, void *env) {
2774 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2775 ir_op *op = get_irn_op(node);
2776 ir_node *asm_node = NULL;
2782 /* link arguments pointing to Unknown to the UNKNOWN Proj */
2783 for (i = get_irn_arity(node) - 1; i >= 0; i--) {
2784 if (is_Unknown(get_irn_n(node, i)))
2785 set_irn_n(node, i, be_get_unknown_for_mode(cg, get_irn_mode(get_irn_n(node, i))));
2788 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
2789 if (op->ops.generic) {
2790 ia32_transform_env_t tenv;
2791 transform_func *transform = (transform_func *)op->ops.generic;
2793 tenv.block = get_nodes_block(node);
2794 tenv.dbg = get_irn_dbg_info(node);
2795 tenv.irg = current_ir_graph;
2797 tenv.mode = get_irn_mode(node);
2799 DEBUG_ONLY(tenv.mod = cg->mod;)
2801 asm_node = (*transform)(&tenv);
2804 /* exchange nodes if a new one was generated */
2806 exchange(node, asm_node);
2807 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2810 DB((cg->mod, LEVEL_1, "ignored\n"));
2815 * Transforms a psi condition.
2817 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
2820 /* if the mode is target mode, we have already seen this part of the tree */
2821 if (get_irn_mode(cond) == mode)
2824 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
2826 set_irn_mode(cond, mode);
2828 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
2829 ir_node *in = get_irn_n(cond, i);
2831 /* if in is a compare: transform into Set/xCmp */
2833 ir_node *new_op = NULL;
2834 ir_node *cmp = get_Proj_pred(in);
2835 ir_node *cmp_a = get_Cmp_left(cmp);
2836 ir_node *cmp_b = get_Cmp_right(cmp);
2837 dbg_info *dbg = get_irn_dbg_info(cmp);
2838 ir_graph *irg = get_irn_irg(cmp);
2839 ir_node *block = get_nodes_block(cmp);
2840 ir_node *noreg = ia32_new_NoReg_gp(cg);
2841 ir_node *nomem = new_rd_NoMem(irg);
2842 int pnc = get_Proj_proj(in);
2844 /* this is a compare */
2845 if (mode_is_float(mode)) {
2846 /* Psi is float, we need a floating point compare */
2850 if (! mode_is_float(get_irn_mode(cmp_a))) {
2851 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
2852 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
2856 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
2857 set_ia32_pncode(new_op, pnc);
2858 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
2867 ia32_transform_env_t tenv;
2868 construct_binop_func *set_func = NULL;
2870 if (mode_is_float(get_irn_mode(cmp_a))) {
2871 /* 1st case: compare operands are floats */
2876 set_func = new_rd_ia32_xCmpSet;
2880 set_func = new_rd_ia32_vfCmpSet;
2883 pnc &= 7; /* fp compare -> int compare */
2886 /* 2nd case: compare operand are integer too */
2887 set_func = new_rd_ia32_CmpSet;
2898 new_op = gen_binop(&tenv, cmp_a, cmp_b, set_func);
2899 set_ia32_pncode(get_Proj_pred(new_op), pnc);
2900 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
2903 /* the the new compare as in */
2904 set_irn_n(cond, i, new_op);
2907 /* another complex condition */
2908 transform_psi_cond(in, mode, cg);
2914 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
2915 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
2916 * compare, which causes the compare result to be stores in a register. The
2917 * "And"s and "Or"s are transformed later, we just have to set their mode right.
2919 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
2920 ia32_code_gen_t *cg = env;
2921 ir_node *psi_sel, *new_cmp, *block;
2926 if (get_irn_opcode(node) != iro_Psi)
2929 psi_sel = get_Psi_cond(node, 0);
2931 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
2932 if (is_Proj(psi_sel))
2935 mode = get_irn_mode(node);
2937 transform_psi_cond(psi_sel, mode, cg);
2939 irg = get_irn_irg(node);
2940 block = get_nodes_block(node);
2942 /* we need to compare the evaluated condition tree with 0 */
2944 /* BEWARE: new_r_Const_long works for floating point as well */
2945 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
2946 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne + (mode_is_float(mode) ? pn_Cmp_Uo : 0));
2948 set_Psi_cond(node, 0, new_cmp);