2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
15 #include "irgraph_t.h"
20 #include "iredges_t.h"
28 #include "archop.h" /* we need this for Min and Max nodes */
30 #include "../benode_t.h"
31 #include "../besched.h"
34 #include "bearch_ia32_t.h"
35 #include "ia32_nodes_attr.h"
36 #include "ia32_transform.h"
37 #include "ia32_new_nodes.h"
38 #include "ia32_map_regs.h"
39 #include "ia32_dbg_stat.h"
40 #include "ia32_optimize.h"
42 #include "gen_ia32_regalloc_if.h"
44 #define SFP_SIGN "0x80000000"
45 #define DFP_SIGN "0x8000000000000000"
46 #define SFP_ABS "0x7FFFFFFF"
47 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
49 #define TP_SFP_SIGN "ia32_sfp_sign"
50 #define TP_DFP_SIGN "ia32_dfp_sign"
51 #define TP_SFP_ABS "ia32_sfp_abs"
52 #define TP_DFP_ABS "ia32_dfp_abs"
54 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
55 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
56 #define ENT_SFP_ABS "IA32_SFP_ABS"
57 #define ENT_DFP_ABS "IA32_DFP_ABS"
59 extern ir_op *get_op_Mulh(void);
61 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
62 ir_node *op1, ir_node *op2, ir_node *mem);
64 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
65 ir_node *op, ir_node *mem);
68 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
71 /****************************************************************************************************
73 * | | | | / _| | | (_)
74 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
75 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
76 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
77 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
79 ****************************************************************************************************/
82 * Returns 1 if irn is a Const representing 0, 0 otherwise
84 static INLINE int is_ia32_Const_0(ir_node *irn) {
85 return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
89 * Returns 1 if irn is a Const representing 1, 0 otherwise
91 static INLINE int is_ia32_Const_1(ir_node *irn) {
92 return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
96 * Returns the Proj representing the UNKNOWN register for given mode.
98 static ir_node *be_get_unknown_for_mode(ia32_code_gen_t *cg, ir_mode *mode) {
99 be_abi_irg_t *babi = cg->birg->abi;
100 const arch_register_t *unknwn_reg = NULL;
102 if (mode_is_float(mode)) {
103 unknwn_reg = USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_UKNWN] : &ia32_vfp_regs[REG_VFP_UKNWN];
106 unknwn_reg = &ia32_gp_regs[REG_GP_UKNWN];
109 return be_abi_get_callee_save_irn(babi, unknwn_reg);
113 * Gets the Proj with number pn from irn.
115 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
116 const ir_edge_t *edge;
118 assert(get_irn_mode(irn) == mode_T && "need mode_T");
120 foreach_out_edge(irn, edge) {
121 proj = get_edge_src_irn(edge);
123 if (get_Proj_proj(proj) == pn)
131 * SSE convert of an integer node into a floating point node.
133 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block,
134 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
136 ir_node *noreg = ia32_new_NoReg_gp(cg);
137 ir_node *nomem = new_rd_NoMem(irg);
139 ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
140 set_ia32_src_mode(conv, get_irn_mode(in));
141 set_ia32_tgt_mode(conv, tgt_mode);
142 set_ia32_am_support(conv, ia32_am_Source);
143 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
145 return new_rd_Proj(dbg, irg, block, conv, tgt_mode, pn_ia32_Conv_I2FP_res);
148 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
149 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
150 static const struct {
152 const char *ent_name;
153 const char *cnst_str;
154 } names [ia32_known_const_max] = {
155 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
156 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
157 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
158 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
160 static struct entity *ent_cache[ia32_known_const_max];
162 const char *tp_name, *ent_name, *cnst_str;
169 ent_name = names[kct].ent_name;
170 if (! ent_cache[kct]) {
171 tp_name = names[kct].tp_name;
172 cnst_str = names[kct].cnst_str;
174 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
175 tp = new_type_primitive(new_id_from_str(tp_name), mode);
176 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
178 set_entity_ld_ident(ent, get_entity_ident(ent));
179 set_entity_visibility(ent, visibility_local);
180 set_entity_variability(ent, variability_constant);
181 set_entity_allocation(ent, allocation_static);
183 /* we create a new entity here: It's initialization must resist on the
185 rem = current_ir_graph;
186 current_ir_graph = get_const_code_irg();
187 cnst = new_Const(mode, tv);
188 current_ir_graph = rem;
190 set_atomic_ent_value(ent, cnst);
192 /* cache the entry */
193 ent_cache[kct] = ent;
196 return get_entity_ident(ent_cache[kct]);
201 * Prints the old node name on cg obst and returns a pointer to it.
203 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
204 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
206 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
207 obstack_1grow(isa->name_obst, 0);
208 isa->name_obst_size += obstack_object_size(isa->name_obst);
209 return obstack_finish(isa->name_obst);
213 /* determine if one operator is an Imm */
214 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
216 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
217 else return is_ia32_Cnst(op2) ? op2 : NULL;
220 /* determine if one operator is not an Imm */
221 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
222 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
227 * Construct a standard binary operation, set AM and immediate if required.
229 * @param env The transformation environment
230 * @param op1 The first operand
231 * @param op2 The second operand
232 * @param func The node constructor function
233 * @return The constructed ia32 node.
235 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
236 ir_node *new_op = NULL;
237 ir_mode *mode = env->mode;
238 dbg_info *dbg = env->dbg;
239 ir_graph *irg = env->irg;
240 ir_node *block = env->block;
241 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
242 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
243 ir_node *nomem = new_NoMem();
244 ir_node *expr_op, *imm_op;
245 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
247 /* Check if immediate optimization is on and */
248 /* if it's an operation with immediate. */
249 /* MulS and Mulh don't support immediates */
250 if (! (env->cg->opt & IA32_OPT_IMMOPS) ||
251 func == new_rd_ia32_Mulh ||
252 func == new_rd_ia32_MulS)
257 else if (is_op_commutative(get_irn_op(env->irn))) {
258 imm_op = get_immediate_op(op1, op2);
259 expr_op = get_expr_op(op1, op2);
262 imm_op = get_immediate_op(NULL, op2);
263 expr_op = get_expr_op(op1, op2);
266 assert((expr_op || imm_op) && "invalid operands");
269 /* We have two consts here: not yet supported */
273 if (mode_is_float(mode)) {
274 /* floating point operations */
276 DB((mod, LEVEL_1, "FP with immediate ..."));
277 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
278 set_ia32_Immop_attr(new_op, imm_op);
279 set_ia32_am_support(new_op, ia32_am_None);
282 DB((mod, LEVEL_1, "FP binop ..."));
283 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
284 set_ia32_am_support(new_op, ia32_am_Source);
286 set_ia32_ls_mode(new_op, mode);
289 /* integer operations */
291 /* This is expr + const */
292 DB((mod, LEVEL_1, "INT with immediate ..."));
293 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
294 set_ia32_Immop_attr(new_op, imm_op);
297 set_ia32_am_support(new_op, ia32_am_Dest);
300 DB((mod, LEVEL_1, "INT binop ..."));
301 /* This is a normal operation */
302 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
305 set_ia32_am_support(new_op, ia32_am_Full);
309 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
311 set_ia32_res_mode(new_op, mode);
313 if (is_op_commutative(get_irn_op(env->irn))) {
314 set_ia32_commutative(new_op);
317 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
323 * Construct a shift/rotate binary operation, sets AM and immediate if required.
325 * @param env The transformation environment
326 * @param op1 The first operand
327 * @param op2 The second operand
328 * @param func The node constructor function
329 * @return The constructed ia32 node.
331 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
332 ir_node *new_op = NULL;
333 ir_mode *mode = env->mode;
334 dbg_info *dbg = env->dbg;
335 ir_graph *irg = env->irg;
336 ir_node *block = env->block;
337 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
338 ir_node *nomem = new_NoMem();
339 ir_node *expr_op, *imm_op;
341 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
343 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
345 /* Check if immediate optimization is on and */
346 /* if it's an operation with immediate. */
347 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
348 expr_op = get_expr_op(op1, op2);
350 assert((expr_op || imm_op) && "invalid operands");
353 /* We have two consts here: not yet supported */
357 /* Limit imm_op within range imm8 */
359 tv = get_ia32_Immop_tarval(imm_op);
362 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
363 set_ia32_Immop_tarval(imm_op, tv);
370 /* integer operations */
372 /* This is shift/rot with const */
373 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
375 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
376 set_ia32_Immop_attr(new_op, imm_op);
379 /* This is a normal shift/rot */
380 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
381 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
385 set_ia32_am_support(new_op, ia32_am_Dest);
387 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
389 set_ia32_res_mode(new_op, mode);
390 set_ia32_emit_cl(new_op);
392 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
397 * Construct a standard unary operation, set AM and immediate if required.
399 * @param env The transformation environment
400 * @param op The operand
401 * @param func The node constructor function
402 * @return The constructed ia32 node.
404 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
405 ir_node *new_op = NULL;
406 ir_mode *mode = env->mode;
407 dbg_info *dbg = env->dbg;
408 ir_graph *irg = env->irg;
409 ir_node *block = env->block;
410 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
411 ir_node *nomem = new_NoMem();
412 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
414 new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
416 if (mode_is_float(mode)) {
417 DB((mod, LEVEL_1, "FP unop ..."));
418 /* floating point operations don't support implicit store */
419 set_ia32_am_support(new_op, ia32_am_None);
422 DB((mod, LEVEL_1, "INT unop ..."));
423 set_ia32_am_support(new_op, ia32_am_Dest);
426 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
428 set_ia32_res_mode(new_op, mode);
430 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
436 * Creates an ia32 Add with immediate.
438 * @param env The transformation environment
439 * @param expr_op The expression operator
440 * @param const_op The constant
441 * @return the created ia32 Add node
443 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
444 ir_node *new_op = NULL;
445 tarval *tv = get_ia32_Immop_tarval(const_op);
446 dbg_info *dbg = env->dbg;
447 ir_graph *irg = env->irg;
448 ir_node *block = env->block;
449 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
450 ir_node *nomem = new_NoMem();
452 tarval_classification_t class_tv, class_negtv;
453 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
455 /* try to optimize to inc/dec */
456 if ((env->cg->opt & IA32_OPT_INCDEC) && (get_ia32_op_type(const_op) == ia32_Const)) {
457 /* optimize tarvals */
458 class_tv = classify_tarval(tv);
459 class_negtv = classify_tarval(tarval_neg(tv));
461 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
462 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
463 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
466 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
467 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
468 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
474 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
475 set_ia32_Immop_attr(new_op, const_op);
476 set_ia32_commutative(new_op);
483 * Creates an ia32 Add.
485 * @param env The transformation environment
486 * @return the created ia32 Add node
488 static ir_node *gen_Add(ia32_transform_env_t *env) {
489 ir_node *new_op = NULL;
490 dbg_info *dbg = env->dbg;
491 ir_mode *mode = env->mode;
492 ir_graph *irg = env->irg;
493 ir_node *block = env->block;
494 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
495 ir_node *nomem = new_NoMem();
496 ir_node *expr_op, *imm_op;
497 ir_node *op1 = get_Add_left(env->irn);
498 ir_node *op2 = get_Add_right(env->irn);
500 /* Check if immediate optimization is on and */
501 /* if it's an operation with immediate. */
502 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
503 expr_op = get_expr_op(op1, op2);
505 assert((expr_op || imm_op) && "invalid operands");
507 if (mode_is_float(mode)) {
509 if (USE_SSE2(env->cg))
510 return gen_binop(env, op1, op2, new_rd_ia32_xAdd);
512 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
517 /* No expr_op means, that we have two const - one symconst and */
518 /* one tarval or another symconst - because this case is not */
519 /* covered by constant folding */
520 /* We need to check for: */
521 /* 1) symconst + const -> becomes a LEA */
522 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
523 /* linker doesn't support two symconsts */
525 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
526 /* this is the 2nd case */
527 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
528 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
529 set_ia32_am_flavour(new_op, ia32_am_OB);
531 DBG_OPT_LEA1(op2, new_op);
534 /* this is the 1st case */
535 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
537 DBG_OPT_LEA2(op1, op2, new_op);
539 if (get_ia32_op_type(op1) == ia32_SymConst) {
540 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
541 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
544 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
545 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
547 set_ia32_am_flavour(new_op, ia32_am_O);
551 set_ia32_am_support(new_op, ia32_am_Source);
552 set_ia32_op_type(new_op, ia32_AddrModeS);
554 /* Lea doesn't need a Proj */
558 /* This is expr + const */
559 new_op = gen_imm_Add(env, expr_op, imm_op);
562 set_ia32_am_support(new_op, ia32_am_Dest);
565 /* This is a normal add */
566 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
569 set_ia32_am_support(new_op, ia32_am_Full);
570 set_ia32_commutative(new_op);
574 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
576 set_ia32_res_mode(new_op, mode);
578 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Add_res);
584 * Creates an ia32 Mul.
586 * @param env The transformation environment
587 * @return the created ia32 Mul node
589 static ir_node *gen_Mul(ia32_transform_env_t *env) {
590 ir_node *op1 = get_Mul_left(env->irn);
591 ir_node *op2 = get_Mul_right(env->irn);
594 if (mode_is_float(env->mode)) {
596 if (USE_SSE2(env->cg))
597 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMul);
599 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
602 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
611 * Creates an ia32 Mulh.
612 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
613 * this result while Mul returns the lower 32 bit.
615 * @param env The transformation environment
616 * @return the created ia32 Mulh node
618 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
619 ir_node *op1 = get_irn_n(env->irn, 0);
620 ir_node *op2 = get_irn_n(env->irn, 1);
621 ir_node *proj_EAX, *proj_EDX, *mulh;
624 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
625 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
626 mulh = get_Proj_pred(proj_EAX);
627 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
629 /* to be on the save side */
630 set_Proj_proj(proj_EAX, pn_EAX);
632 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
633 /* Mulh with const cannot have AM */
634 set_ia32_am_support(mulh, ia32_am_None);
637 /* Mulh cannot have AM for destination */
638 set_ia32_am_support(mulh, ia32_am_Source);
644 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
652 * Creates an ia32 And.
654 * @param env The transformation environment
655 * @return The created ia32 And node
657 static ir_node *gen_And(ia32_transform_env_t *env) {
658 ir_node *op1 = get_And_left(env->irn);
659 ir_node *op2 = get_And_right(env->irn);
661 assert (! mode_is_float(env->mode));
662 return gen_binop(env, op1, op2, new_rd_ia32_And);
668 * Creates an ia32 Or.
670 * @param env The transformation environment
671 * @return The created ia32 Or node
673 static ir_node *gen_Or(ia32_transform_env_t *env) {
674 ir_node *op1 = get_Or_left(env->irn);
675 ir_node *op2 = get_Or_right(env->irn);
677 assert (! mode_is_float(env->mode));
678 return gen_binop(env, op1, op2, new_rd_ia32_Or);
684 * Creates an ia32 Eor.
686 * @param env The transformation environment
687 * @return The created ia32 Eor node
689 static ir_node *gen_Eor(ia32_transform_env_t *env) {
690 ir_node *op1 = get_Eor_left(env->irn);
691 ir_node *op2 = get_Eor_right(env->irn);
693 assert(! mode_is_float(env->mode));
694 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
700 * Creates an ia32 Max.
702 * @param env The transformation environment
703 * @return the created ia32 Max node
705 static ir_node *gen_Max(ia32_transform_env_t *env) {
706 ir_node *op1 = get_irn_n(env->irn, 0);
707 ir_node *op2 = get_irn_n(env->irn, 1);
710 if (mode_is_float(env->mode)) {
712 if (USE_SSE2(env->cg))
713 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMax);
719 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
720 set_ia32_am_support(new_op, ia32_am_None);
721 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
730 * Creates an ia32 Min.
732 * @param env The transformation environment
733 * @return the created ia32 Min node
735 static ir_node *gen_Min(ia32_transform_env_t *env) {
736 ir_node *op1 = get_irn_n(env->irn, 0);
737 ir_node *op2 = get_irn_n(env->irn, 1);
740 if (mode_is_float(env->mode)) {
742 if (USE_SSE2(env->cg))
743 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMin);
749 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
750 set_ia32_am_support(new_op, ia32_am_None);
751 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
760 * Creates an ia32 Sub with immediate.
762 * @param env The transformation environment
763 * @param expr_op The first operator
764 * @param const_op The constant operator
765 * @return The created ia32 Sub node
767 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
768 ir_node *new_op = NULL;
769 tarval *tv = get_ia32_Immop_tarval(const_op);
770 dbg_info *dbg = env->dbg;
771 ir_graph *irg = env->irg;
772 ir_node *block = env->block;
773 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
774 ir_node *nomem = new_NoMem();
776 tarval_classification_t class_tv, class_negtv;
777 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
779 /* try to optimize to inc/dec */
780 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
781 /* optimize tarvals */
782 class_tv = classify_tarval(tv);
783 class_negtv = classify_tarval(tarval_neg(tv));
785 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
786 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
787 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
790 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
791 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
792 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
798 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
799 set_ia32_Immop_attr(new_op, const_op);
806 * Creates an ia32 Sub.
808 * @param env The transformation environment
809 * @return The created ia32 Sub node
811 static ir_node *gen_Sub(ia32_transform_env_t *env) {
812 ir_node *new_op = NULL;
813 dbg_info *dbg = env->dbg;
814 ir_mode *mode = env->mode;
815 ir_graph *irg = env->irg;
816 ir_node *block = env->block;
817 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
818 ir_node *nomem = new_NoMem();
819 ir_node *op1 = get_Sub_left(env->irn);
820 ir_node *op2 = get_Sub_right(env->irn);
821 ir_node *expr_op, *imm_op;
823 /* Check if immediate optimization is on and */
824 /* if it's an operation with immediate. */
825 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
826 expr_op = get_expr_op(op1, op2);
828 assert((expr_op || imm_op) && "invalid operands");
830 if (mode_is_float(mode)) {
832 if (USE_SSE2(env->cg))
833 return gen_binop(env, op1, op2, new_rd_ia32_xSub);
835 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
840 /* No expr_op means, that we have two const - one symconst and */
841 /* one tarval or another symconst - because this case is not */
842 /* covered by constant folding */
843 /* We need to check for: */
844 /* 1) symconst + const -> becomes a LEA */
845 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
846 /* linker doesn't support two symconsts */
848 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
849 /* this is the 2nd case */
850 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
851 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
852 set_ia32_am_sc_sign(new_op);
853 set_ia32_am_flavour(new_op, ia32_am_OB);
855 DBG_OPT_LEA1(op2, new_op);
858 /* this is the 1st case */
859 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
861 DBG_OPT_LEA2(op1, op2, new_op);
863 if (get_ia32_op_type(op1) == ia32_SymConst) {
864 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
865 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
868 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
869 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
870 set_ia32_am_sc_sign(new_op);
872 set_ia32_am_flavour(new_op, ia32_am_O);
876 set_ia32_am_support(new_op, ia32_am_Source);
877 set_ia32_op_type(new_op, ia32_AddrModeS);
879 /* Lea doesn't need a Proj */
883 /* This is expr - const */
884 new_op = gen_imm_Sub(env, expr_op, imm_op);
887 set_ia32_am_support(new_op, ia32_am_Dest);
890 /* This is a normal sub */
891 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
894 set_ia32_am_support(new_op, ia32_am_Full);
898 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
900 set_ia32_res_mode(new_op, mode);
902 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Sub_res);
908 * Generates an ia32 DivMod with additional infrastructure for the
909 * register allocator if needed.
911 * @param env The transformation environment
912 * @param dividend -no comment- :)
913 * @param divisor -no comment- :)
914 * @param dm_flav flavour_Div/Mod/DivMod
915 * @return The created ia32 DivMod node
917 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
919 ir_node *edx_node, *cltd;
921 dbg_info *dbg = env->dbg;
922 ir_graph *irg = env->irg;
923 ir_node *block = env->block;
924 ir_mode *mode = env->mode;
925 ir_node *irn = env->irn;
930 mem = get_Div_mem(irn);
931 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
934 mem = get_Mod_mem(irn);
935 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
938 mem = get_DivMod_mem(irn);
939 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
945 if (mode_is_signed(mode)) {
946 /* in signed mode, we need to sign extend the dividend */
947 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
948 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
949 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
952 edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
953 set_ia32_Const_type(edx_node, ia32_Const);
954 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
957 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
959 set_ia32_n_res(res, 2);
961 /* Only one proj is used -> We must add a second proj and */
962 /* connect this one to a Keep node to eat up the second */
963 /* destroyed register. */
964 if (get_irn_n_edges(irn) == 1) {
965 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
966 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
968 if (get_irn_op(irn) == op_Div) {
969 set_Proj_proj(proj, pn_DivMod_res_div);
970 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
973 set_Proj_proj(proj, pn_DivMod_res_mod);
974 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
977 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
980 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
982 set_ia32_res_mode(res, mode_Is);
989 * Wrapper for generate_DivMod. Sets flavour_Mod.
991 * @param env The transformation environment
993 static ir_node *gen_Mod(ia32_transform_env_t *env) {
994 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
998 * Wrapper for generate_DivMod. Sets flavour_Div.
1000 * @param env The transformation environment
1002 static ir_node *gen_Div(ia32_transform_env_t *env) {
1003 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
1007 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1009 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
1010 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
1016 * Creates an ia32 floating Div.
1018 * @param env The transformation environment
1019 * @return The created ia32 xDiv node
1021 static ir_node *gen_Quot(ia32_transform_env_t *env) {
1022 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1024 ir_node *nomem = new_rd_NoMem(env->irg);
1025 ir_node *op1 = get_Quot_left(env->irn);
1026 ir_node *op2 = get_Quot_right(env->irn);
1029 if (USE_SSE2(env->cg)) {
1030 if (is_ia32_xConst(op2)) {
1031 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
1032 set_ia32_am_support(new_op, ia32_am_None);
1033 set_ia32_Immop_attr(new_op, op2);
1036 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1037 set_ia32_am_support(new_op, ia32_am_Source);
1041 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1042 set_ia32_am_support(new_op, ia32_am_Source);
1044 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
1045 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1053 * Creates an ia32 Shl.
1055 * @param env The transformation environment
1056 * @return The created ia32 Shl node
1058 static ir_node *gen_Shl(ia32_transform_env_t *env) {
1059 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
1065 * Creates an ia32 Shr.
1067 * @param env The transformation environment
1068 * @return The created ia32 Shr node
1070 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1071 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1077 * Creates an ia32 Shrs.
1079 * @param env The transformation environment
1080 * @return The created ia32 Shrs node
1082 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1083 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1089 * Creates an ia32 RotL.
1091 * @param env The transformation environment
1092 * @param op1 The first operator
1093 * @param op2 The second operator
1094 * @return The created ia32 RotL node
1096 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1097 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1103 * Creates an ia32 RotR.
1104 * NOTE: There is no RotR with immediate because this would always be a RotL
1105 * "imm-mode_size_bits" which can be pre-calculated.
1107 * @param env The transformation environment
1108 * @param op1 The first operator
1109 * @param op2 The second operator
1110 * @return The created ia32 RotR node
1112 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1113 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1119 * Creates an ia32 RotR or RotL (depending on the found pattern).
1121 * @param env The transformation environment
1122 * @return The created ia32 RotL or RotR node
1124 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1125 ir_node *rotate = NULL;
1126 ir_node *op1 = get_Rot_left(env->irn);
1127 ir_node *op2 = get_Rot_right(env->irn);
1129 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1130 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1131 that means we can create a RotR instead of an Add and a RotL */
1134 ir_node *pred = get_Proj_pred(op2);
1136 if (is_ia32_Add(pred)) {
1137 ir_node *pred_pred = get_irn_n(pred, 2);
1138 tarval *tv = get_ia32_Immop_tarval(pred);
1139 long bits = get_mode_size_bits(env->mode);
1141 if (is_Proj(pred_pred)) {
1142 pred_pred = get_Proj_pred(pred_pred);
1145 if (is_ia32_Minus(pred_pred) &&
1146 tarval_is_long(tv) &&
1147 get_tarval_long(tv) == bits)
1149 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1150 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1157 rotate = gen_RotL(env, op1, op2);
1166 * Transforms a Minus node.
1168 * @param env The transformation environment
1169 * @param op The Minus operand
1170 * @return The created ia32 Minus node
1172 static ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1177 if (mode_is_float(env->mode)) {
1179 if (USE_SSE2(env->cg)) {
1180 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1181 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1182 ir_node *nomem = new_rd_NoMem(env->irg);
1184 new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1186 size = get_mode_size_bits(env->mode);
1187 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1189 set_ia32_sc(new_op, name);
1191 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1193 set_ia32_res_mode(new_op, env->mode);
1194 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1196 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
1199 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1200 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1204 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1211 * Transforms a Minus node.
1213 * @param env The transformation environment
1214 * @return The created ia32 Minus node
1216 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1217 return gen_Minus_ex(env, get_Minus_op(env->irn));
1222 * Transforms a Not node.
1224 * @param env The transformation environment
1225 * @return The created ia32 Not node
1227 static ir_node *gen_Not(ia32_transform_env_t *env) {
1228 assert (! mode_is_float(env->mode));
1229 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1235 * Transforms an Abs node.
1237 * @param env The transformation environment
1238 * @return The created ia32 Abs node
1240 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1241 ir_node *res, *p_eax, *p_edx;
1242 dbg_info *dbg = env->dbg;
1243 ir_mode *mode = env->mode;
1244 ir_graph *irg = env->irg;
1245 ir_node *block = env->block;
1246 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1247 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1248 ir_node *nomem = new_NoMem();
1249 ir_node *op = get_Abs_op(env->irn);
1253 if (mode_is_float(mode)) {
1255 if (USE_SSE2(env->cg)) {
1256 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1258 size = get_mode_size_bits(mode);
1259 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1261 set_ia32_sc(res, name);
1263 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1265 set_ia32_res_mode(res, mode);
1266 set_ia32_immop_type(res, ia32_ImmSymConst);
1268 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
1271 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1272 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1276 res = new_rd_ia32_Cdq(dbg, irg, block, op);
1277 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1278 set_ia32_res_mode(res, mode);
1280 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
1281 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
1283 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1284 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1285 set_ia32_res_mode(res, mode);
1287 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
1289 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1290 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1291 set_ia32_res_mode(res, mode);
1293 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
1302 * Transforms a Load.
1304 * @param env The transformation environment
1305 * @return the created ia32 Load node
1307 static ir_node *gen_Load(ia32_transform_env_t *env) {
1308 ir_node *node = env->irn;
1309 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1310 ir_node *ptr = get_Load_ptr(node);
1311 ir_node *lptr = ptr;
1312 ir_mode *mode = get_Load_mode(node);
1315 ia32_am_flavour_t am_flav = ia32_B;
1317 /* address might be a constant (symconst or absolute address) */
1318 if (is_ia32_Const(ptr)) {
1323 if (mode_is_float(mode)) {
1325 if (USE_SSE2(env->cg))
1326 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1328 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1331 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1334 /* base is an constant address */
1336 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1337 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1340 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1346 set_ia32_am_support(new_op, ia32_am_Source);
1347 set_ia32_op_type(new_op, ia32_AddrModeS);
1348 set_ia32_am_flavour(new_op, am_flav);
1349 set_ia32_ls_mode(new_op, mode);
1352 check for special case: the loaded value might not be used (optimized, volatile, ...)
1353 we add a Proj + Keep for volatile loads and ignore all other cases
1355 if (! get_proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1356 /* add a result proj and a Keep to produce a pseudo use */
1357 ir_node *proj = new_r_Proj(env->irg, env->block, new_op, mode, pn_ia32_Load_res);
1358 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), env->irg, env->block, 1, &proj);
1361 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1369 * Transforms a Store.
1371 * @param env The transformation environment
1372 * @return the created ia32 Store node
1374 static ir_node *gen_Store(ia32_transform_env_t *env) {
1375 ir_node *node = env->irn;
1376 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1377 ir_node *val = get_Store_value(node);
1378 ir_node *ptr = get_Store_ptr(node);
1379 ir_node *sptr = ptr;
1380 ir_node *mem = get_Store_mem(node);
1381 ir_mode *mode = get_irn_link(node);
1382 ir_node *sval = val;
1385 ia32_am_flavour_t am_flav = ia32_B;
1386 ia32_immop_type_t immop = ia32_ImmNone;
1388 if (! mode_is_float(mode)) {
1389 /* in case of storing a const (but not a symconst) -> make it an attribute */
1390 if (is_ia32_Cnst(val)) {
1391 switch (get_ia32_op_type(val)) {
1393 immop = ia32_ImmConst;
1396 immop = ia32_ImmSymConst;
1399 assert(0 && "unsupported Const type");
1405 /* address might be a constant (symconst or absolute address) */
1406 if (is_ia32_Const(ptr)) {
1411 if (mode_is_float(mode)) {
1413 if (USE_SSE2(env->cg))
1414 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1416 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1418 else if (get_mode_size_bits(mode) == 8) {
1419 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1422 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1425 /* stored const is an attribute (saves a register) */
1426 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1427 set_ia32_Immop_attr(new_op, val);
1430 /* base is an constant address */
1432 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1433 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1436 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1442 set_ia32_am_support(new_op, ia32_am_Dest);
1443 set_ia32_op_type(new_op, ia32_AddrModeD);
1444 set_ia32_am_flavour(new_op, am_flav);
1445 set_ia32_ls_mode(new_op, mode);
1446 set_ia32_immop_type(new_op, immop);
1448 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1456 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1458 * @param env The transformation environment
1459 * @return The transformed node.
1461 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1462 dbg_info *dbg = env->dbg;
1463 ir_graph *irg = env->irg;
1464 ir_node *block = env->block;
1465 ir_node *node = env->irn;
1466 ir_node *sel = get_Cond_selector(node);
1467 ir_mode *sel_mode = get_irn_mode(sel);
1468 ir_node *res = NULL;
1469 ir_node *pred = NULL;
1470 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1471 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1473 if (is_Proj(sel) && sel_mode == mode_b) {
1474 ir_node *nomem = new_NoMem();
1476 pred = get_Proj_pred(sel);
1478 /* get both compare operators */
1479 cmp_a = get_Cmp_left(pred);
1480 cmp_b = get_Cmp_right(pred);
1482 /* check if we can use a CondJmp with immediate */
1483 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1484 expr = get_expr_op(cmp_a, cmp_b);
1487 pn_Cmp pnc = get_Proj_proj(sel);
1489 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1490 if (get_ia32_op_type(cnst) == ia32_Const &&
1491 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1493 /* a Cmp A =/!= 0 */
1494 ir_node *op1 = expr;
1495 ir_node *op2 = expr;
1496 ir_node *and = skip_Proj(expr);
1497 const char *cnst = NULL;
1499 /* check, if expr is an only once used And operation */
1500 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1501 op1 = get_irn_n(and, 2);
1502 op2 = get_irn_n(and, 3);
1504 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1506 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1507 set_ia32_pncode(res, get_Proj_proj(sel));
1508 set_ia32_res_mode(res, get_irn_mode(op1));
1511 copy_ia32_Immop_attr(res, and);
1514 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1519 if (mode_is_float(get_irn_mode(expr))) {
1521 if (USE_SSE2(env->cg))
1522 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1528 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1530 set_ia32_Immop_attr(res, cnst);
1531 set_ia32_res_mode(res, get_irn_mode(expr));
1534 if (mode_is_float(get_irn_mode(cmp_a))) {
1536 if (USE_SSE2(env->cg))
1537 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1540 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1541 proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
1542 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1546 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1547 set_ia32_commutative(res);
1549 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1552 set_ia32_pncode(res, get_Proj_proj(sel));
1553 //set_ia32_am_support(res, ia32_am_Source);
1556 /* determine the smallest switch case value */
1557 int switch_min = INT_MAX;
1558 const ir_edge_t *edge;
1561 foreach_out_edge(node, edge) {
1562 int pn = get_Proj_proj(get_edge_src_irn(edge));
1563 switch_min = pn < switch_min ? pn : switch_min;
1567 /* if smallest switch case is not 0 we need an additional sub */
1568 snprintf(buf, sizeof(buf), "%d", switch_min);
1569 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1570 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1571 sub_ia32_am_offs(res, buf);
1572 set_ia32_am_flavour(res, ia32_am_OB);
1573 set_ia32_am_support(res, ia32_am_Source);
1574 set_ia32_op_type(res, ia32_AddrModeS);
1577 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1578 set_ia32_pncode(res, get_Cond_defaultProj(node));
1579 set_ia32_res_mode(res, get_irn_mode(sel));
1582 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1589 * Transforms a CopyB node.
1591 * @param env The transformation environment
1592 * @return The transformed node.
1594 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1595 ir_node *res = NULL;
1596 dbg_info *dbg = env->dbg;
1597 ir_graph *irg = env->irg;
1598 ir_mode *mode = env->mode;
1599 ir_node *block = env->block;
1600 ir_node *node = env->irn;
1601 ir_node *src = get_CopyB_src(node);
1602 ir_node *dst = get_CopyB_dst(node);
1603 ir_node *mem = get_CopyB_mem(node);
1604 int size = get_type_size_bytes(get_CopyB_type(node));
1607 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1608 /* then we need the size explicitly in ECX. */
1609 if (size >= 16 * 4) {
1610 rem = size & 0x3; /* size % 4 */
1613 res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
1614 set_ia32_op_type(res, ia32_Const);
1615 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1617 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1618 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1621 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1622 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1623 set_ia32_immop_type(res, ia32_ImmConst);
1626 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1634 * Transforms a Mux node into CMov.
1636 * @param env The transformation environment
1637 * @return The transformed node.
1639 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1641 ir_node *node = env->irn;
1642 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1643 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1645 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1652 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *cmp_a, ir_node *cmp_b, \
1653 ir_node *psi_true, ir_node *psi_default, ir_mode *mode);
1656 * Transforms a Psi node into CMov.
1658 * @param env The transformation environment
1659 * @return The transformed node.
1661 static ir_node *gen_Psi(ia32_transform_env_t *env) {
1662 ia32_code_gen_t *cg = env->cg;
1663 dbg_info *dbg = env->dbg;
1664 ir_graph *irg = env->irg;
1665 ir_mode *mode = env->mode;
1666 ir_node *block = env->block;
1667 ir_node *node = env->irn;
1668 ir_node *cmp_proj = get_Mux_sel(node);
1669 ir_node *psi_true = get_Psi_val(node, 0);
1670 ir_node *psi_default = get_Psi_default(node);
1671 ir_node *noreg = ia32_new_NoReg_gp(cg);
1672 ir_node *nomem = new_rd_NoMem(irg);
1673 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
1676 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
1678 cmp = get_Proj_pred(cmp_proj);
1679 cmp_a = get_Cmp_left(cmp);
1680 cmp_b = get_Cmp_right(cmp);
1681 pnc = get_Proj_proj(cmp_proj);
1683 if (mode_is_float(mode)) {
1684 /* floating point psi */
1687 /* 1st case: compare operands are float too */
1689 /* psi(cmp(a, b), t, f) can be done as: */
1690 /* tmp = cmp a, b */
1691 /* tmp2 = t and tmp */
1692 /* tmp3 = f and not tmp */
1693 /* res = tmp2 or tmp3 */
1695 /* in case the compare operands are int, we move them into xmm register */
1696 if (! mode_is_float(get_irn_mode(cmp_a))) {
1697 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, node, mode_D);
1698 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, node, mode_D);
1700 pnc |= 8; /* transform integer compare to fp compare */
1703 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1704 set_ia32_pncode(new_op, pnc);
1705 set_ia32_am_support(new_op, ia32_am_Source);
1706 set_ia32_res_mode(new_op, mode);
1707 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1708 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xCmp_res);
1710 and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, psi_true, new_op, nomem);
1711 set_ia32_am_support(and1, ia32_am_Source);
1712 set_ia32_res_mode(and1, mode);
1713 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
1714 and1 = new_rd_Proj(dbg, irg, block, and1, mode, pn_ia32_xAnd_res);
1716 and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, psi_default, nomem);
1717 set_ia32_am_support(and2, ia32_am_Source);
1718 set_ia32_res_mode(and2, mode);
1719 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
1720 and2 = new_rd_Proj(dbg, irg, block, and2, mode, pn_ia32_xAndNot_res);
1722 new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
1723 set_ia32_am_support(new_op, ia32_am_Source);
1724 set_ia32_res_mode(new_op, mode);
1725 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1726 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xOr_res);
1730 new_op = new_rd_ia32_vfCMov(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1731 set_ia32_pncode(new_op, pnc);
1732 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1737 construct_binop_func *set_func = NULL;
1738 cmov_func_t *cmov_func = NULL;
1740 if (mode_is_float(get_irn_mode(cmp_a))) {
1741 /* 1st case: compare operands are floats */
1746 set_func = new_rd_ia32_xCmpSet;
1747 cmov_func = new_rd_ia32_xCmpCMov;
1751 set_func = new_rd_ia32_vfCmpSet;
1752 cmov_func = new_rd_ia32_vfCmpCMov;
1755 pnc &= 7; /* fp compare -> int compare */
1758 /* 2nd case: compare operand are integer too */
1759 set_func = new_rd_ia32_CmpSet;
1760 cmov_func = new_rd_ia32_CmpCMov;
1763 /* create the nodes */
1765 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
1766 if (is_ia32_Const_0(cmp_b) && is_Proj(cmp_a) && (is_ia32_And(get_Proj_pred(cmp_a)) || is_ia32_Or(get_Proj_pred(cmp_a)))) {
1767 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1768 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1769 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1770 set_ia32_pncode(new_op, pnc);
1772 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1773 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1774 /* we invert condition and set default to 0 */
1775 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1776 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
1779 /* otherwise: use CMOVcc */
1780 new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, cmp_a, psi_true, psi_default, mode);
1781 set_ia32_pncode(new_op, pnc);
1784 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1788 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1789 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1790 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1791 set_ia32_pncode(get_Proj_pred(new_op), pnc);
1792 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1794 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1795 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1796 /* we invert condition and set default to 0 */
1797 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1798 set_ia32_pncode(get_Proj_pred(new_op), get_inversed_pnc(pnc));
1799 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1802 /* otherwise: use CMOVcc */
1803 new_op = cmov_func(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1804 set_ia32_pncode(new_op, pnc);
1805 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1815 * Following conversion rules apply:
1819 * 1) n bit -> m bit n > m (downscale)
1820 * a) target is signed: movsx
1821 * b) target is unsigned: and with lower bits sets
1822 * 2) n bit -> m bit n == m (sign change)
1824 * 3) n bit -> m bit n < m (upscale)
1825 * a) source is signed: movsx
1826 * b) source is unsigned: and with lower bits sets
1830 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1834 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1835 * if target mode < 32bit: additional INT -> INT conversion (see above)
1839 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1840 * x87 is mode_E internally, conversions happen only at load and store
1841 * in non-strict semantic
1845 * Create a conversion from x87 state register to general purpose.
1847 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1848 ia32_code_gen_t *cg = env->cg;
1849 entity *ent = cg->fp_to_gp;
1850 ir_graph *irg = env->irg;
1851 ir_node *block = env->block;
1852 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1853 ir_node *op = get_Conv_op(env->irn);
1854 ir_node *fist, *mem, *load;
1857 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1858 ent = cg->fp_to_gp =
1859 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1863 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
1865 set_ia32_frame_ent(fist, ent);
1866 set_ia32_use_frame(fist);
1867 set_ia32_am_support(fist, ia32_am_Dest);
1868 set_ia32_op_type(fist, ia32_AddrModeD);
1869 set_ia32_am_flavour(fist, ia32_B);
1870 set_ia32_ls_mode(fist, mode_F);
1872 mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
1875 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1877 set_ia32_frame_ent(load, ent);
1878 set_ia32_use_frame(load);
1879 set_ia32_am_support(load, ia32_am_Source);
1880 set_ia32_op_type(load, ia32_AddrModeS);
1881 set_ia32_am_flavour(load, ia32_B);
1882 set_ia32_ls_mode(load, tgt_mode);
1884 return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
1888 * Create a conversion from x87 state register to general purpose.
1890 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1891 ia32_code_gen_t *cg = env->cg;
1892 entity *ent = cg->gp_to_fp;
1893 ir_graph *irg = env->irg;
1894 ir_node *block = env->block;
1895 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1896 ir_node *nomem = get_irg_no_mem(irg);
1897 ir_node *op = get_Conv_op(env->irn);
1898 ir_node *fild, *store, *mem;
1902 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
1903 ent = cg->gp_to_fp =
1904 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
1907 /* first convert to 32 bit */
1908 src_bits = get_mode_size_bits(src_mode);
1909 if (src_bits == 8) {
1910 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
1911 op = new_r_Proj(irg, block, op, mode_Is, 0);
1913 else if (src_bits < 32) {
1914 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
1915 op = new_r_Proj(irg, block, op, mode_Is, 0);
1919 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
1921 set_ia32_frame_ent(store, ent);
1922 set_ia32_use_frame(store);
1924 set_ia32_am_support(store, ia32_am_Dest);
1925 set_ia32_op_type(store, ia32_AddrModeD);
1926 set_ia32_am_flavour(store, ia32_B);
1927 set_ia32_ls_mode(store, mode_Is);
1929 mem = new_r_Proj(irg, block, store, mode_M, 0);
1932 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1934 set_ia32_frame_ent(fild, ent);
1935 set_ia32_use_frame(fild);
1936 set_ia32_am_support(fild, ia32_am_Source);
1937 set_ia32_op_type(fild, ia32_AddrModeS);
1938 set_ia32_am_flavour(fild, ia32_B);
1939 set_ia32_ls_mode(fild, mode_F);
1941 return new_r_Proj(irg, block, fild, mode_F, 0);
1945 * Transforms a Conv node.
1947 * @param env The transformation environment
1948 * @return The created ia32 Conv node
1950 static ir_node *gen_Conv(ia32_transform_env_t *env) {
1951 dbg_info *dbg = env->dbg;
1952 ir_graph *irg = env->irg;
1953 ir_node *op = get_Conv_op(env->irn);
1954 ir_mode *src_mode = get_irn_mode(op);
1955 ir_mode *tgt_mode = env->mode;
1956 int src_bits = get_mode_size_bits(src_mode);
1957 int tgt_bits = get_mode_size_bits(tgt_mode);
1959 ir_node *block = env->block;
1960 ir_node *new_op = NULL;
1961 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1962 ir_node *nomem = new_rd_NoMem(irg);
1964 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1966 if (src_mode == tgt_mode) {
1967 /* this can happen when changing mode_P to mode_Is */
1968 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1969 edges_reroute(env->irn, op, irg);
1971 else if (mode_is_float(src_mode)) {
1972 /* we convert from float ... */
1973 if (mode_is_float(tgt_mode)) {
1975 if (USE_SSE2(env->cg)) {
1976 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1977 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
1978 pn = pn_ia32_Conv_FP2FP_res;
1981 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
1982 edges_reroute(env->irn, op, irg);
1987 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1988 if (USE_SSE2(env->cg)) {
1989 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
1990 pn = pn_ia32_Conv_FP2I_res;
1993 return gen_x87_fp_to_gp(env, tgt_mode);
1995 /* if target mode is not int: add an additional downscale convert */
1996 if (tgt_bits < 32) {
1997 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1998 set_ia32_am_support(new_op, ia32_am_Source);
1999 set_ia32_tgt_mode(new_op, tgt_mode);
2000 set_ia32_src_mode(new_op, src_mode);
2002 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, pn_ia32_Conv_FP2I_res);
2004 if (tgt_bits == 8 || src_bits == 8) {
2005 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
2006 pn = pn_ia32_Conv_I2I8Bit_res;
2009 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
2010 pn = pn_ia32_Conv_I2I_res;
2016 /* we convert from int ... */
2017 if (mode_is_float(tgt_mode)) {
2020 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
2021 if (USE_SSE2(env->cg)) {
2022 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
2023 pn = pn_ia32_Conv_I2FP_res;
2026 return gen_x87_gp_to_fp(env, src_mode);
2030 if (get_mode_size_bits(src_mode) == tgt_bits) {
2031 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
2032 edges_reroute(env->irn, op, irg);
2035 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2036 if (tgt_bits == 8 || src_bits == 8) {
2037 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
2038 pn = pn_ia32_Conv_I2I8Bit_res;
2041 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
2042 pn = pn_ia32_Conv_I2I_res;
2049 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2050 set_ia32_tgt_mode(new_op, tgt_mode);
2051 set_ia32_src_mode(new_op, src_mode);
2053 set_ia32_am_support(new_op, ia32_am_Source);
2055 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, pn);
2063 /********************************************
2066 * | |__ ___ _ __ ___ __| | ___ ___
2067 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2068 * | |_) | __/ | | | (_) | (_| | __/\__ \
2069 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2071 ********************************************/
2074 * Decides in which block the transformed StackParam should be placed.
2075 * If the StackParam has more than one user, the dominator block of
2076 * the users will be returned. In case of only one user, this is either
2077 * the user block or, in case of a Phi, the predecessor block of the Phi.
2079 static ir_node *get_block_transformed_stack_param(ir_node *irn) {
2080 ir_node *dom_bl = NULL;
2082 if (get_irn_n_edges(irn) == 1) {
2083 ir_node *src = get_edge_src_irn(get_irn_out_edge_first(irn));
2085 if (! is_Phi(src)) {
2086 dom_bl = get_nodes_block(src);
2089 /* Determine on which in position of the Phi the irn is */
2090 /* and get the corresponding cfg predecessor block. */
2092 int i = get_irn_pred_pos(src, irn);
2093 assert(i >= 0 && "kaputt");
2094 dom_bl = get_Block_cfgpred_block(get_nodes_block(src), i);
2098 dom_bl = node_users_smallest_common_dominator(irn, 1);
2101 assert(dom_bl && "dominator block not found");
2106 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
2107 ir_node *new_op = NULL;
2108 ir_node *node = env->irn;
2109 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2110 ir_node *mem = new_rd_NoMem(env->irg);
2111 ir_node *ptr = get_irn_n(node, 0);
2112 entity *ent = be_get_frame_entity(node);
2113 ir_mode *mode = env->mode;
2115 /* choose the block where to place the load */
2116 env->block = get_block_transformed_stack_param(node);
2118 if (mode_is_float(mode)) {
2120 if (USE_SSE2(env->cg))
2121 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2123 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2126 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2129 set_ia32_frame_ent(new_op, ent);
2130 set_ia32_use_frame(new_op);
2132 set_ia32_am_support(new_op, ia32_am_Source);
2133 set_ia32_op_type(new_op, ia32_AddrModeS);
2134 set_ia32_am_flavour(new_op, ia32_B);
2135 set_ia32_ls_mode(new_op, mode);
2137 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2139 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
2143 * Transforms a FrameAddr into an ia32 Add.
2145 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
2146 ir_node *new_op = NULL;
2147 ir_node *node = env->irn;
2148 ir_node *op = get_irn_n(node, 0);
2149 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2150 ir_node *nomem = new_rd_NoMem(env->irg);
2152 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
2153 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
2154 set_ia32_am_support(new_op, ia32_am_Full);
2155 set_ia32_use_frame(new_op);
2156 set_ia32_immop_type(new_op, ia32_ImmConst);
2157 set_ia32_commutative(new_op);
2159 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2161 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
2165 * Transforms a FrameLoad into an ia32 Load.
2167 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
2168 ir_node *new_op = NULL;
2169 ir_node *node = env->irn;
2170 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2171 ir_node *mem = get_irn_n(node, 0);
2172 ir_node *ptr = get_irn_n(node, 1);
2173 entity *ent = be_get_frame_entity(node);
2174 ir_mode *mode = get_type_mode(get_entity_type(ent));
2176 if (mode_is_float(mode)) {
2178 if (USE_SSE2(env->cg))
2179 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2181 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2184 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2186 set_ia32_frame_ent(new_op, ent);
2187 set_ia32_use_frame(new_op);
2189 set_ia32_am_support(new_op, ia32_am_Source);
2190 set_ia32_op_type(new_op, ia32_AddrModeS);
2191 set_ia32_am_flavour(new_op, ia32_B);
2192 set_ia32_ls_mode(new_op, mode);
2194 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2201 * Transforms a FrameStore into an ia32 Store.
2203 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
2204 ir_node *new_op = NULL;
2205 ir_node *node = env->irn;
2206 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2207 ir_node *mem = get_irn_n(node, 0);
2208 ir_node *ptr = get_irn_n(node, 1);
2209 ir_node *val = get_irn_n(node, 2);
2210 entity *ent = be_get_frame_entity(node);
2211 ir_mode *mode = get_irn_mode(val);
2213 if (mode_is_float(mode)) {
2215 if (USE_SSE2(env->cg))
2216 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2218 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2220 else if (get_mode_size_bits(mode) == 8) {
2221 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2224 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2227 set_ia32_frame_ent(new_op, ent);
2228 set_ia32_use_frame(new_op);
2230 set_ia32_am_support(new_op, ia32_am_Dest);
2231 set_ia32_op_type(new_op, ia32_AddrModeD);
2232 set_ia32_am_flavour(new_op, ia32_B);
2233 set_ia32_ls_mode(new_op, mode);
2235 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2241 * This function just sets the register for the Unknown node
2242 * as this is not done during register allocation because Unknown
2243 * is an "ignore" node.
2245 static ir_node *gen_Unknown(ia32_transform_env_t *env) {
2246 ir_mode *mode = env->mode;
2247 ir_node *irn = env->irn;
2249 if (mode_is_float(mode)) {
2250 if (USE_SSE2(env->cg))
2251 arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
2253 arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
2255 else if (mode_is_int(mode) || mode_is_reference(mode)) {
2256 arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
2259 assert(0 && "unsupported Unknown-Mode");
2265 /**********************************************************************
2268 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2269 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2270 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2271 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2273 **********************************************************************/
2275 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2277 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2280 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2281 ir_node *val, ir_node *mem);
2284 * Transforms a lowered Load into a "real" one.
2286 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, construct_load_func func, char fp_unit) {
2287 ir_node *node = env->irn;
2288 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2289 ir_mode *mode = get_ia32_ls_mode(node);
2292 ia32_am_flavour_t am_flav = ia32_B;
2295 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2296 lowering we have x87 nodes, so we need to enforce simulation.
2298 if (mode_is_float(mode)) {
2300 if (fp_unit == fp_x87)
2304 new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1));
2306 if (am_offs = get_ia32_am_offs(node)) {
2308 add_ia32_am_offs(new_op, am_offs);
2311 set_ia32_am_support(new_op, ia32_am_Source);
2312 set_ia32_op_type(new_op, ia32_AddrModeS);
2313 set_ia32_am_flavour(new_op, am_flav);
2314 set_ia32_ls_mode(new_op, mode);
2315 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2316 set_ia32_use_frame(new_op);
2318 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2324 * Transforms a lowered Store into a "real" one.
2326 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, construct_store_func func, char fp_unit) {
2327 ir_node *node = env->irn;
2328 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2329 ir_mode *mode = get_ia32_ls_mode(node);
2332 ia32_am_flavour_t am_flav = ia32_B;
2335 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2336 lowering we have x87 nodes, so we need to enforce simulation.
2338 if (mode_is_float(mode)) {
2340 if (fp_unit == fp_x87)
2344 new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1), get_irn_n(node, 2));
2346 if (am_offs = get_ia32_am_offs(node)) {
2348 add_ia32_am_offs(new_op, am_offs);
2351 set_ia32_am_support(new_op, ia32_am_Dest);
2352 set_ia32_op_type(new_op, ia32_AddrModeD);
2353 set_ia32_am_flavour(new_op, am_flav);
2354 set_ia32_ls_mode(new_op, mode);
2355 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2356 set_ia32_use_frame(new_op);
2358 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2365 * Transforms an ia32_l_XXX into a "real" XXX node
2367 * @param env The transformation environment
2368 * @return the created ia32 XXX node
2370 #define GEN_LOWERED_OP(op) \
2371 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2372 if (mode_is_float(env->mode)) \
2374 return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2377 #define GEN_LOWERED_x87_OP(op) \
2378 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2380 FORCE_x87(env->cg); \
2381 new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2382 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_None); \
2386 #define GEN_LOWERED_UNOP(op) \
2387 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2388 return gen_unop(env, get_unop_op(env->irn), new_rd_ia32_##op); \
2391 #define GEN_LOWERED_SHIFT_OP(op) \
2392 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2393 return gen_shift_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2396 #define GEN_LOWERED_LOAD(op, fp_unit) \
2397 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2398 return gen_lowered_Load(env, new_rd_ia32_##op, fp_unit); \
2401 #define GEN_LOWERED_STORE(op, fp_unit) \
2402 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2403 return gen_lowered_Store(env, new_rd_ia32_##op, fp_unit); \
2406 GEN_LOWERED_OP(AddC)
2408 GEN_LOWERED_OP(SubC)
2412 GEN_LOWERED_x87_OP(vfdiv)
2413 GEN_LOWERED_x87_OP(vfmul)
2414 GEN_LOWERED_x87_OP(vfsub)
2416 GEN_LOWERED_UNOP(Minus)
2418 GEN_LOWERED_LOAD(vfild, fp_x87)
2419 GEN_LOWERED_LOAD(Load, fp_none)
2420 GEN_LOWERED_STORE(vfist, fp_x87)
2421 GEN_LOWERED_STORE(Store, fp_none)
2424 * Transforms a l_MulS into a "real" MulS node.
2426 * @param env The transformation environment
2427 * @return the created ia32 MulS node
2429 static ir_node *gen_ia32_l_MulS(ia32_transform_env_t *env) {
2431 /* l_MulS is already a mode_T node, so we create the MulS in the normal way */
2432 /* and then skip the result Proj, because all needed Projs are already there. */
2434 ir_node *new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_MulS);
2435 return get_Proj_pred(new_op);
2438 GEN_LOWERED_SHIFT_OP(Shl)
2439 GEN_LOWERED_SHIFT_OP(Shr)
2440 GEN_LOWERED_SHIFT_OP(Shrs)
2443 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
2444 * op1 - target to be shifted
2445 * op2 - contains bits to be shifted into target
2447 * Only op3 can be an immediate.
2449 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, ir_node *count) {
2450 ir_node *new_op = NULL;
2451 ir_mode *mode = env->mode;
2452 dbg_info *dbg = env->dbg;
2453 ir_graph *irg = env->irg;
2454 ir_node *block = env->block;
2455 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2456 ir_node *nomem = new_NoMem();
2459 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
2461 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
2463 /* Check if immediate optimization is on and */
2464 /* if it's an operation with immediate. */
2465 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, count) : NULL;
2467 /* Limit imm_op within range imm8 */
2469 tv = get_ia32_Immop_tarval(imm_op);
2472 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
2473 set_ia32_Immop_tarval(imm_op, tv);
2480 /* integer operations */
2482 /* This is ShiftD with const */
2483 DB((mod, LEVEL_1, "ShiftD with immediate ..."));
2485 if (is_ia32_l_ShlD(env->irn))
2486 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, op1, op2, noreg, nomem);
2488 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, op1, op2, noreg, nomem);
2489 set_ia32_Immop_attr(new_op, imm_op);
2492 /* This is a normal ShiftD */
2493 DB((mod, LEVEL_1, "ShiftD binop ..."));
2494 if (is_ia32_l_ShlD(env->irn))
2495 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, op1, op2, count, nomem);
2497 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, op1, op2, count, nomem);
2500 /* set AM support */
2501 set_ia32_am_support(new_op, ia32_am_Dest);
2503 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2505 set_ia32_res_mode(new_op, mode);
2506 set_ia32_emit_cl(new_op);
2508 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
2511 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env) {
2512 return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2));
2515 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env) {
2516 return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2));
2520 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
2522 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env) {
2523 ia32_code_gen_t *cg = env->cg;
2524 ir_node *res = NULL;
2525 ir_node *ptr = get_irn_n(env->irn, 0);
2526 ir_node *val = get_irn_n(env->irn, 1);
2527 ir_node *mem = get_irn_n(env->irn, 2);
2530 ir_node *noreg = ia32_new_NoReg_gp(cg);
2532 /* Store x87 -> MEM */
2533 res = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2534 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2535 set_ia32_use_frame(res);
2536 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2537 set_ia32_am_support(res, ia32_am_Dest);
2538 set_ia32_am_flavour(res, ia32_B);
2539 res = new_rd_Proj(env->dbg, env->irg, env->block, res, mode_M, pn_ia32_vfst_M);
2541 /* Load MEM -> SSE */
2542 res = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, res);
2543 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2544 set_ia32_use_frame(res);
2545 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2546 set_ia32_am_support(res, ia32_am_Source);
2547 set_ia32_am_flavour(res, ia32_B);
2548 res = new_rd_Proj(env->dbg, env->irg, env->block, res, get_ia32_ls_mode(env->irn), pn_ia32_xLoad_res);
2551 /* SSE unit is not used -> skip this node. */
2554 edges_reroute(env->irn, val, env->irg);
2555 for (i = get_irn_arity(env->irn) - 1; i >= 0; i--)
2556 set_irn_n(env->irn, i, get_irg_bad(env->irg));
2563 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
2565 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env) {
2566 ia32_code_gen_t *cg = env->cg;
2567 ir_node *res = NULL;
2568 ir_node *ptr = get_irn_n(env->irn, 0);
2569 ir_node *val = get_irn_n(env->irn, 1);
2570 ir_node *mem = get_irn_n(env->irn, 2);
2573 ir_node *noreg = ia32_new_NoReg_gp(cg);
2575 /* Store SSE -> MEM */
2576 res = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2577 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2578 set_ia32_use_frame(res);
2579 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2580 set_ia32_am_support(res, ia32_am_Dest);
2581 set_ia32_am_flavour(res, ia32_B);
2582 res = new_rd_Proj(env->dbg, env->irg, env->block, res, mode_M, pn_ia32_xStore_M);
2584 /* Load MEM -> x87 */
2585 res = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2586 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2587 set_ia32_use_frame(res);
2588 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2589 set_ia32_am_support(res, ia32_am_Source);
2590 set_ia32_am_flavour(res, ia32_B);
2591 res = new_rd_Proj(env->dbg, env->irg, env->block, res, get_ia32_ls_mode(env->irn), pn_ia32_vfld_res);
2594 /* SSE unit is not used -> skip this node. */
2597 edges_reroute(env->irn, val, env->irg);
2598 for (i = get_irn_arity(env->irn) - 1; i >= 0; i--)
2599 set_irn_n(env->irn, i, get_irg_bad(env->irg));
2605 /*********************************************************
2608 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
2609 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
2610 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
2611 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
2613 *********************************************************/
2616 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
2617 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2619 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
2620 ia32_transform_env_t tenv;
2621 ir_node *in1, *in2, *noreg, *nomem, *res;
2622 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
2624 /* Return if AM node or not a Sub or xSub */
2625 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_xSub(irn)))
2628 noreg = ia32_new_NoReg_gp(cg);
2629 nomem = new_rd_NoMem(cg->irg);
2630 in1 = get_irn_n(irn, 2);
2631 in2 = get_irn_n(irn, 3);
2632 in1_reg = arch_get_irn_register(cg->arch_env, in1);
2633 in2_reg = arch_get_irn_register(cg->arch_env, in2);
2634 out_reg = get_ia32_out_reg(irn, 0);
2636 tenv.block = get_nodes_block(irn);
2637 tenv.dbg = get_irn_dbg_info(irn);
2640 tenv.mode = get_ia32_res_mode(irn);
2642 DEBUG_ONLY(tenv.mod = cg->mod;)
2644 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
2645 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
2646 /* generate the neg src2 */
2647 res = gen_Minus_ex(&tenv, in2);
2648 arch_set_irn_register(cg->arch_env, res, in2_reg);
2650 /* add to schedule */
2651 sched_add_before(irn, res);
2653 /* generate the add */
2654 if (mode_is_float(tenv.mode)) {
2655 res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2656 set_ia32_am_support(res, ia32_am_Source);
2659 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2660 set_ia32_am_support(res, ia32_am_Full);
2661 set_ia32_commutative(res);
2663 set_ia32_res_mode(res, tenv.mode);
2665 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
2667 slots = get_ia32_slots(res);
2670 /* add to schedule */
2671 sched_add_before(irn, res);
2673 /* remove the old sub */
2676 DBG_OPT_SUB2NEGADD(irn, res);
2678 /* exchange the add and the sub */
2684 * Transforms a LEA into an Add if possible
2685 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2687 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
2688 ia32_am_flavour_t am_flav;
2690 ir_node *res = NULL;
2691 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
2693 ia32_transform_env_t tenv;
2694 const arch_register_t *out_reg, *base_reg, *index_reg;
2697 if (! is_ia32_Lea(irn))
2700 am_flav = get_ia32_am_flavour(irn);
2702 if (get_ia32_am_sc(irn))
2705 /* only some LEAs can be transformed to an Add */
2706 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
2709 noreg = ia32_new_NoReg_gp(cg);
2710 nomem = new_rd_NoMem(cg->irg);
2713 base = get_irn_n(irn, 0);
2714 index = get_irn_n(irn,1);
2716 offs = get_ia32_am_offs(irn);
2718 /* offset has a explicit sign -> we need to skip + */
2719 if (offs && offs[0] == '+')
2722 out_reg = arch_get_irn_register(cg->arch_env, irn);
2723 base_reg = arch_get_irn_register(cg->arch_env, base);
2724 index_reg = arch_get_irn_register(cg->arch_env, index);
2726 tenv.block = get_nodes_block(irn);
2727 tenv.dbg = get_irn_dbg_info(irn);
2730 DEBUG_ONLY(tenv.mod = cg->mod;)
2731 tenv.mode = get_irn_mode(irn);
2734 switch(get_ia32_am_flavour(irn)) {
2736 /* out register must be same as base register */
2737 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2743 /* out register must be same as base register */
2744 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2751 /* out register must be same as index register */
2752 if (! REGS_ARE_EQUAL(out_reg, index_reg))
2759 /* out register must be same as one in register */
2760 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
2764 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
2769 /* in registers a different from out -> no Add possible */
2776 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
2777 arch_set_irn_register(cg->arch_env, res, out_reg);
2778 set_ia32_op_type(res, ia32_Normal);
2779 set_ia32_commutative(res);
2780 set_ia32_res_mode(res, tenv.mode);
2783 set_ia32_cnst(res, offs);
2784 set_ia32_immop_type(res, ia32_ImmConst);
2787 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
2789 /* add Add to schedule */
2790 sched_add_before(irn, res);
2792 DBG_OPT_LEA2ADD(irn, res);
2794 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, pn_ia32_Add_res);
2796 /* add result Proj to schedule */
2797 sched_add_before(irn, res);
2799 /* remove the old LEA */
2802 /* exchange the Add and the LEA */
2807 * the BAD transformer.
2809 static ir_node *bad_transform(ia32_transform_env_t *env) {
2810 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2816 * Enters all transform functions into the generic pointer
2818 void ia32_register_transformers(void) {
2819 ir_op *op_Max, *op_Min, *op_Mulh;
2821 /* first clear the generic function pointer for all ops */
2822 clear_irp_opcodes_generic_func();
2824 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2825 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
2859 /* transform ops from intrinsic lowering */
2880 GEN(ia32_l_X87toSSE);
2881 GEN(ia32_l_SSEtoX87);
2896 /* constant transformation happens earlier */
2920 /* set the register for all Unknown nodes */
2923 op_Max = get_op_Max();
2926 op_Min = get_op_Min();
2929 op_Mulh = get_op_Mulh();
2938 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
2941 * Transforms the given firm node (and maybe some other related nodes)
2942 * into one or more assembler nodes.
2944 * @param node the firm node
2945 * @param env the debug module
2947 void ia32_transform_node(ir_node *node, void *env) {
2948 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2949 ir_op *op = get_irn_op(node);
2950 ir_node *asm_node = NULL;
2956 /* link arguments pointing to Unknown to the UNKNOWN Proj */
2957 for (i = get_irn_arity(node) - 1; i >= 0; i--) {
2958 if (is_Unknown(get_irn_n(node, i)))
2959 set_irn_n(node, i, be_get_unknown_for_mode(cg, get_irn_mode(get_irn_n(node, i))));
2962 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
2963 if (op->ops.generic) {
2964 ia32_transform_env_t tenv;
2965 transform_func *transform = (transform_func *)op->ops.generic;
2967 tenv.block = get_nodes_block(node);
2968 tenv.dbg = get_irn_dbg_info(node);
2969 tenv.irg = current_ir_graph;
2971 tenv.mode = get_irn_mode(node);
2973 DEBUG_ONLY(tenv.mod = cg->mod;)
2975 asm_node = (*transform)(&tenv);
2978 /* exchange nodes if a new one was generated */
2980 exchange(node, asm_node);
2981 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2984 DB((cg->mod, LEVEL_1, "ignored\n"));
2989 * Transforms a psi condition.
2991 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
2994 /* if the mode is target mode, we have already seen this part of the tree */
2995 if (get_irn_mode(cond) == mode)
2998 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
3000 set_irn_mode(cond, mode);
3002 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
3003 ir_node *in = get_irn_n(cond, i);
3005 /* if in is a compare: transform into Set/xCmp */
3007 ir_node *new_op = NULL;
3008 ir_node *cmp = get_Proj_pred(in);
3009 ir_node *cmp_a = get_Cmp_left(cmp);
3010 ir_node *cmp_b = get_Cmp_right(cmp);
3011 dbg_info *dbg = get_irn_dbg_info(cmp);
3012 ir_graph *irg = get_irn_irg(cmp);
3013 ir_node *block = get_nodes_block(cmp);
3014 ir_node *noreg = ia32_new_NoReg_gp(cg);
3015 ir_node *nomem = new_rd_NoMem(irg);
3016 int pnc = get_Proj_proj(in);
3018 /* this is a compare */
3019 if (mode_is_float(mode)) {
3020 /* Psi is float, we need a floating point compare */
3024 if (! mode_is_float(get_irn_mode(cmp_a))) {
3025 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
3026 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
3030 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
3031 set_ia32_pncode(new_op, pnc);
3032 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
3041 ia32_transform_env_t tenv;
3042 construct_binop_func *set_func = NULL;
3044 if (mode_is_float(get_irn_mode(cmp_a))) {
3045 /* 1st case: compare operands are floats */
3050 set_func = new_rd_ia32_xCmpSet;
3054 set_func = new_rd_ia32_vfCmpSet;
3057 pnc &= 7; /* fp compare -> int compare */
3060 /* 2nd case: compare operand are integer too */
3061 set_func = new_rd_ia32_CmpSet;
3072 new_op = gen_binop(&tenv, cmp_a, cmp_b, set_func);
3073 set_ia32_pncode(get_Proj_pred(new_op), pnc);
3074 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
3077 /* the the new compare as in */
3078 set_irn_n(cond, i, new_op);
3081 /* another complex condition */
3082 transform_psi_cond(in, mode, cg);
3088 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
3089 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
3090 * compare, which causes the compare result to be stores in a register. The
3091 * "And"s and "Or"s are transformed later, we just have to set their mode right.
3093 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
3094 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
3095 ir_node *psi_sel, *new_cmp, *block;
3100 if (get_irn_opcode(node) != iro_Psi)
3103 psi_sel = get_Psi_cond(node, 0);
3105 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
3106 if (is_Proj(psi_sel))
3109 mode = get_irn_mode(node);
3111 transform_psi_cond(psi_sel, mode, cg);
3113 irg = get_irn_irg(node);
3114 block = get_nodes_block(node);
3116 /* we need to compare the evaluated condition tree with 0 */
3118 /* BEWARE: new_r_Const_long works for floating point as well */
3119 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
3120 /* transform the const */
3121 ia32_place_consts_set_modes(new_cmp, cg);
3122 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne + (mode_is_float(mode) ? pn_Cmp_Uo : 0));
3124 set_Psi_cond(node, 0, new_cmp);