2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
30 #include "archop.h" /* we need this for Min and Max nodes */
37 #include "../benode_t.h"
38 #include "../besched.h"
40 #include "../beutil.h"
42 #include "bearch_ia32_t.h"
43 #include "ia32_nodes_attr.h"
44 #include "ia32_transform.h"
45 #include "ia32_new_nodes.h"
46 #include "ia32_map_regs.h"
47 #include "ia32_dbg_stat.h"
48 #include "ia32_optimize.h"
49 #include "ia32_util.h"
51 #include "gen_ia32_regalloc_if.h"
53 #define SFP_SIGN "0x80000000"
54 #define DFP_SIGN "0x8000000000000000"
55 #define SFP_ABS "0x7FFFFFFF"
56 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
58 #define TP_SFP_SIGN "ia32_sfp_sign"
59 #define TP_DFP_SIGN "ia32_dfp_sign"
60 #define TP_SFP_ABS "ia32_sfp_abs"
61 #define TP_DFP_ABS "ia32_dfp_abs"
63 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
64 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
65 #define ENT_SFP_ABS "IA32_SFP_ABS"
66 #define ENT_DFP_ABS "IA32_DFP_ABS"
68 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
70 typedef struct ia32_transform_env_t {
71 ir_graph *irg; /**< The irg, the node should be created in */
72 ia32_code_gen_t *cg; /**< The code generator */
73 int visited; /**< visited count that indicates whether a
74 node is already transformed */
75 pdeq *worklist; /**< worklist of nodes that still need to be
77 ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/
78 } ia32_transform_env_t;
80 extern ir_op *get_op_Mulh(void);
82 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
83 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
84 ir_node *op2, ir_node *mem);
86 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
87 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
90 typedef ir_node *(transform_func)(ia32_transform_env_t *env, ir_node *node);
92 /****************************************************************************************************
94 * | | | | / _| | | (_)
95 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
96 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
97 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
98 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
100 ****************************************************************************************************/
102 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node);
103 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node);
104 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
107 static INLINE void set_new_node(ir_node *old_node, ir_node *new_node)
109 set_irn_link(old_node, new_node);
112 static INLINE ir_node *get_new_node(ir_node *old_node)
114 assert(irn_visited(old_node));
115 return (ir_node*) get_irn_link(old_node);
119 * Returns 1 if irn is a Const representing 0, 0 otherwise
121 static INLINE int is_ia32_Const_0(ir_node *irn) {
122 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
123 && tarval_is_null(get_ia32_Immop_tarval(irn));
127 * Returns 1 if irn is a Const representing 1, 0 otherwise
129 static INLINE int is_ia32_Const_1(ir_node *irn) {
130 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
131 && tarval_is_one(get_ia32_Immop_tarval(irn));
135 * Collects all Projs of a node into the node array. Index is the projnum.
136 * BEWARE: The caller has to assure the appropriate array size!
138 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
139 const ir_edge_t *edge;
140 assert(get_irn_mode(irn) == mode_T && "need mode_T");
142 memset(projs, 0, size * sizeof(projs[0]));
144 foreach_out_edge(irn, edge) {
145 ir_node *proj = get_edge_src_irn(edge);
146 int proj_proj = get_Proj_proj(proj);
147 assert(proj_proj < size);
148 projs[proj_proj] = proj;
153 * Renumbers the proj having pn_old in the array tp pn_new
154 * and removes the proj from the array.
156 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
157 fprintf(stderr, "Warning: renumber_Proj used!\n");
159 set_Proj_proj(projs[pn_old], pn_new);
160 projs[pn_old] = NULL;
165 * creates a unique ident by adding a number to a tag
167 * @param tag the tag string, must contain a %d if a number
170 static ident *unique_id(const char *tag)
172 static unsigned id = 0;
175 snprintf(str, sizeof(str), tag, ++id);
176 return new_id_from_str(str);
180 * Get a primitive type for a mode.
182 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
184 pmap_entry *e = pmap_find(types, mode);
189 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
190 res = new_type_primitive(new_id_from_str(buf), mode);
191 pmap_insert(types, mode, res);
199 * Get an entity that is initialized with a tarval
201 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
203 tarval *tv = get_Const_tarval(cnst);
204 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
209 ir_mode *mode = get_irn_mode(cnst);
210 ir_type *tp = get_Const_type(cnst);
211 if (tp == firm_unknown_type)
212 tp = get_prim_type(cg->isa->types, mode);
214 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
216 set_entity_ld_ident(res, get_entity_ident(res));
217 set_entity_visibility(res, visibility_local);
218 set_entity_variability(res, variability_constant);
219 set_entity_allocation(res, allocation_static);
221 /* we create a new entity here: It's initialization must resist on the
223 rem = current_ir_graph;
224 current_ir_graph = get_const_code_irg();
225 set_atomic_ent_value(res, new_Const_type(tv, tp));
226 current_ir_graph = rem;
228 pmap_insert(cg->isa->tv_ent, tv, res);
236 * Transforms a Const.
238 static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) {
239 ir_graph *irg = env->irg;
240 dbg_info *dbgi = get_irn_dbg_info(node);
241 ir_mode *mode = get_irn_mode(node);
242 ir_node *block = transform_node(env, get_nodes_block(node));
244 if (mode_is_float(mode)) {
247 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
248 ir_node *nomem = new_NoMem();
252 if (! USE_SSE2(env->cg)) {
253 cnst_classify_t clss = classify_Const(node);
255 if (clss == CNST_NULL) {
256 load = new_rd_ia32_vfldz(dbgi, irg, block);
258 } else if (clss == CNST_ONE) {
259 load = new_rd_ia32_vfld1(dbgi, irg, block);
262 floatent = get_entity_for_tv(env->cg, node);
264 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem);
265 set_ia32_am_support(load, ia32_am_Source);
266 set_ia32_op_type(load, ia32_AddrModeS);
267 set_ia32_am_flavour(load, ia32_am_N);
268 set_ia32_am_sc(load, floatent);
269 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
272 floatent = get_entity_for_tv(env->cg, node);
274 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
275 set_ia32_am_support(load, ia32_am_Source);
276 set_ia32_op_type(load, ia32_AddrModeS);
277 set_ia32_am_flavour(load, ia32_am_N);
278 set_ia32_am_sc(load, floatent);
279 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_xLoad_res);
282 set_ia32_ls_mode(load, mode);
283 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
285 /* Const Nodes before the initial IncSP are a bad idea, because
286 * they could be spilled and we have no SP ready at that point yet
288 if (get_irg_start_block(irg) == block) {
289 add_irn_dep(load, get_irg_frame(irg));
292 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
295 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
298 if (get_irg_start_block(irg) == block) {
299 add_irn_dep(cnst, get_irg_frame(irg));
302 set_ia32_Const_attr(cnst, node);
303 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
308 return new_r_Bad(irg);
312 * Transforms a SymConst.
314 static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) {
315 ir_graph *irg = env->irg;
316 dbg_info *dbgi = get_irn_dbg_info(node);
317 ir_mode *mode = get_irn_mode(node);
318 ir_node *block = transform_node(env, get_nodes_block(node));
321 if (mode_is_float(mode)) {
323 if (USE_SSE2(env->cg))
324 cnst = new_rd_ia32_xConst(dbgi, irg, block);
326 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
327 set_ia32_ls_mode(cnst, mode);
329 cnst = new_rd_ia32_Const(dbgi, irg, block);
332 /* Const Nodes before the initial IncSP are a bad idea, because
333 * they could be spilled and we have no SP ready at that point yet
335 if (get_irg_start_block(irg) == block) {
336 add_irn_dep(cnst, get_irg_frame(irg));
339 set_ia32_Const_attr(cnst, node);
340 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
346 * SSE convert of an integer node into a floating point node.
348 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbgi,
349 ir_graph *irg, ir_node *block,
350 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
352 ir_node *noreg = ia32_new_NoReg_gp(cg);
353 ir_node *nomem = new_rd_NoMem(irg);
354 ir_node *old_pred = get_Cmp_left(old_node);
355 ir_mode *in_mode = get_irn_mode(old_pred);
356 int in_bits = get_mode_size_bits(in_mode);
358 ir_node *conv = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, in, nomem);
359 set_ia32_ls_mode(conv, tgt_mode);
361 set_ia32_am_support(conv, ia32_am_Source);
363 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
369 * SSE convert of an float node into a double node.
371 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbgi,
372 ir_graph *irg, ir_node *block,
373 ir_node *in, ir_node *old_node)
375 ir_node *noreg = ia32_new_NoReg_gp(cg);
376 ir_node *nomem = new_rd_NoMem(irg);
378 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, in, nomem);
379 set_ia32_am_support(conv, ia32_am_Source);
380 set_ia32_ls_mode(conv, mode_E);
381 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
386 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
387 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
388 static const struct {
390 const char *ent_name;
391 const char *cnst_str;
392 } names [ia32_known_const_max] = {
393 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
394 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
395 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
396 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
398 static ir_entity *ent_cache[ia32_known_const_max];
400 const char *tp_name, *ent_name, *cnst_str;
408 ent_name = names[kct].ent_name;
409 if (! ent_cache[kct]) {
410 tp_name = names[kct].tp_name;
411 cnst_str = names[kct].cnst_str;
413 //mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
415 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
416 tp = new_type_primitive(new_id_from_str(tp_name), mode);
417 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
419 set_entity_ld_ident(ent, get_entity_ident(ent));
420 set_entity_visibility(ent, visibility_local);
421 set_entity_variability(ent, variability_constant);
422 set_entity_allocation(ent, allocation_static);
424 /* we create a new entity here: It's initialization must resist on the
426 rem = current_ir_graph;
427 current_ir_graph = get_const_code_irg();
428 cnst = new_Const(mode, tv);
429 current_ir_graph = rem;
431 set_atomic_ent_value(ent, cnst);
433 /* cache the entry */
434 ent_cache[kct] = ent;
437 return ent_cache[kct];
442 * Prints the old node name on cg obst and returns a pointer to it.
444 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
445 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
447 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
448 obstack_1grow(isa->name_obst, 0);
449 return obstack_finish(isa->name_obst);
453 /* determine if one operator is an Imm */
454 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
456 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
457 else return is_ia32_Cnst(op2) ? op2 : NULL;
460 /* determine if one operator is not an Imm */
461 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
462 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
465 static void fold_immediate(ia32_transform_env_t *env, ir_node *node, int in1, int in2) {
469 if(! (env->cg->opt & IA32_OPT_IMMOPS))
472 left = get_irn_n(node, in1);
473 right = get_irn_n(node, in2);
474 if(!is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
475 /* we can only set right operand to immediate */
476 if(!is_ia32_commutative(node))
478 /* exchange left/right */
479 set_irn_n(node, in1, right);
480 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
481 copy_ia32_Immop_attr(node, left);
482 } else if(is_ia32_Cnst(right)) {
483 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
484 copy_ia32_Immop_attr(node, right);
489 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
493 * Construct a standard binary operation, set AM and immediate if required.
495 * @param env The transformation environment
496 * @param op1 The first operand
497 * @param op2 The second operand
498 * @param func The node constructor function
499 * @return The constructed ia32 node.
501 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *node,
502 ir_node *op1, ir_node *op2,
503 construct_binop_func *func) {
504 ir_node *new_node = NULL;
505 ir_graph *irg = env->irg;
506 dbg_info *dbgi = get_irn_dbg_info(node);
507 ir_node *block = transform_node(env, get_nodes_block(node));
508 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
509 ir_node *nomem = new_NoMem();
510 ir_node *new_op1 = transform_node(env, op1);
511 ir_node *new_op2 = transform_node(env, op2);
513 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
514 if(func == new_rd_ia32_IMul) {
515 set_ia32_am_support(new_node, ia32_am_Source);
517 set_ia32_am_support(new_node, ia32_am_Full);
520 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
521 if (is_op_commutative(get_irn_op(node))) {
522 set_ia32_commutative(new_node);
524 fold_immediate(env, new_node, 2, 3);
530 * Construct a standard binary operation, set AM and immediate if required.
532 * @param env The transformation environment
533 * @param op1 The first operand
534 * @param op2 The second operand
535 * @param func The node constructor function
536 * @return The constructed ia32 node.
538 static ir_node *gen_binop_float(ia32_transform_env_t *env, ir_node *node,
539 ir_node *op1, ir_node *op2,
540 construct_binop_func *func)
542 ir_node *new_node = NULL;
543 dbg_info *dbgi = get_irn_dbg_info(node);
544 ir_graph *irg = env->irg;
545 ir_mode *mode = get_irn_mode(node);
546 ir_node *block = transform_node(env, get_nodes_block(node));
547 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
548 ir_node *nomem = new_NoMem();
549 ir_node *new_op1 = transform_node(env, op1);
550 ir_node *new_op2 = transform_node(env, op2);
552 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
553 set_ia32_am_support(new_node, ia32_am_Source);
554 if (is_op_commutative(get_irn_op(node))) {
555 set_ia32_commutative(new_node);
557 if (USE_SSE2(env->cg)) {
558 set_ia32_ls_mode(new_node, mode);
561 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
568 * Construct a shift/rotate binary operation, sets AM and immediate if required.
570 * @param env The transformation environment
571 * @param op1 The first operand
572 * @param op2 The second operand
573 * @param func The node constructor function
574 * @return The constructed ia32 node.
576 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node,
577 ir_node *op1, ir_node *op2,
578 construct_binop_func *func) {
579 ir_node *new_op = NULL;
580 dbg_info *dbgi = get_irn_dbg_info(node);
581 ir_graph *irg = env->irg;
582 ir_node *block = transform_node(env, get_nodes_block(node));
583 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
584 ir_node *nomem = new_NoMem();
587 ir_node *new_op1 = transform_node(env, op1);
588 ir_node *new_op2 = transform_node(env, op2);
591 assert(! mode_is_float(get_irn_mode(node))
592 && "Shift/Rotate with float not supported");
594 /* Check if immediate optimization is on and */
595 /* if it's an operation with immediate. */
596 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
597 expr_op = get_expr_op(new_op1, new_op2);
599 assert((expr_op || imm_op) && "invalid operands");
602 /* We have two consts here: not yet supported */
606 /* Limit imm_op within range imm8 */
608 tv = get_ia32_Immop_tarval(imm_op);
611 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
612 set_ia32_Immop_tarval(imm_op, tv);
619 /* integer operations */
621 /* This is shift/rot with const */
622 DB((dbg, LEVEL_1, "Shift/Rot with immediate ..."));
624 new_op = func(dbgi, irg, block, noreg, noreg, expr_op, noreg, nomem);
625 copy_ia32_Immop_attr(new_op, imm_op);
627 /* This is a normal shift/rot */
628 DB((dbg, LEVEL_1, "Shift/Rot binop ..."));
629 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
633 set_ia32_am_support(new_op, ia32_am_Dest);
635 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
637 set_ia32_emit_cl(new_op);
644 * Construct a standard unary operation, set AM and immediate if required.
646 * @param env The transformation environment
647 * @param op The operand
648 * @param func The node constructor function
649 * @return The constructed ia32 node.
651 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *node, ir_node *op,
652 construct_unop_func *func) {
653 ir_node *new_node = NULL;
654 ir_graph *irg = env->irg;
655 dbg_info *dbgi = get_irn_dbg_info(node);
656 ir_node *block = transform_node(env, get_nodes_block(node));
657 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
658 ir_node *nomem = new_NoMem();
659 ir_node *new_op = transform_node(env, op);
661 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
662 DB((dbg, LEVEL_1, "INT unop ..."));
663 set_ia32_am_support(new_node, ia32_am_Dest);
665 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
672 * Creates an ia32 Add.
674 * @param env The transformation environment
675 * @return the created ia32 Add node
677 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) {
678 ir_node *new_op = NULL;
679 ir_graph *irg = env->irg;
680 dbg_info *dbgi = get_irn_dbg_info(node);
681 ir_mode *mode = get_irn_mode(node);
682 ir_node *block = transform_node(env, get_nodes_block(node));
683 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
684 ir_node *nomem = new_NoMem();
685 ir_node *expr_op, *imm_op;
686 ir_node *op1 = get_Add_left(node);
687 ir_node *op2 = get_Add_right(node);
688 ir_node *new_op1 = transform_node(env, op1);
689 ir_node *new_op2 = transform_node(env, op2);
691 /* Check if immediate optimization is on and */
692 /* if it's an operation with immediate. */
693 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
694 expr_op = get_expr_op(new_op1, new_op2);
696 assert((expr_op || imm_op) && "invalid operands");
698 if (mode_is_float(mode)) {
700 if (USE_SSE2(env->cg))
701 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xAdd);
703 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfadd);
708 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
709 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
711 /* No expr_op means, that we have two const - one symconst and */
712 /* one tarval or another symconst - because this case is not */
713 /* covered by constant folding */
714 /* We need to check for: */
715 /* 1) symconst + const -> becomes a LEA */
716 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
717 /* linker doesn't support two symconsts */
719 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
720 /* this is the 2nd case */
721 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
722 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
723 set_ia32_am_flavour(new_op, ia32_am_OB);
724 set_ia32_am_support(new_op, ia32_am_Source);
725 set_ia32_op_type(new_op, ia32_AddrModeS);
727 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
728 } else if (tp1 == ia32_ImmSymConst) {
729 tarval *tv = get_ia32_Immop_tarval(new_op2);
730 long offs = get_tarval_long(tv);
732 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
733 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
735 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
736 add_ia32_am_offs_int(new_op, offs);
737 set_ia32_am_flavour(new_op, ia32_am_O);
738 set_ia32_am_support(new_op, ia32_am_Source);
739 set_ia32_op_type(new_op, ia32_AddrModeS);
740 } else if (tp2 == ia32_ImmSymConst) {
741 tarval *tv = get_ia32_Immop_tarval(new_op1);
742 long offs = get_tarval_long(tv);
744 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
745 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
747 add_ia32_am_offs_int(new_op, offs);
748 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
749 set_ia32_am_flavour(new_op, ia32_am_O);
750 set_ia32_am_support(new_op, ia32_am_Source);
751 set_ia32_op_type(new_op, ia32_AddrModeS);
753 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
754 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
755 tarval *restv = tarval_add(tv1, tv2);
757 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
759 new_op = new_rd_ia32_Const(dbgi, irg, block);
760 set_ia32_Const_tarval(new_op, restv);
761 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
764 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
767 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
768 tarval_classification_t class_tv, class_negtv;
769 tarval *tv = get_ia32_Immop_tarval(imm_op);
771 /* optimize tarvals */
772 class_tv = classify_tarval(tv);
773 class_negtv = classify_tarval(tarval_neg(tv));
775 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
776 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
777 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
778 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
780 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
781 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
782 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
783 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
789 /* This is a normal add */
790 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
793 set_ia32_am_support(new_op, ia32_am_Full);
794 set_ia32_commutative(new_op);
796 fold_immediate(env, new_op, 2, 3);
798 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
804 static ir_node *create_ia32_Mul(ia32_transform_env_t *env, ir_node *node) {
805 ir_graph *irg = env->irg;
806 dbg_info *dbgi = get_irn_dbg_info(node);
807 ir_node *block = transform_node(env, get_nodes_block(node));
808 ir_node *op1 = get_Mul_left(node);
809 ir_node *op2 = get_Mul_right(node);
810 ir_node *new_op1 = transform_node(env, op1);
811 ir_node *new_op2 = transform_node(env, op2);
812 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
813 ir_node *proj_EAX, *proj_EDX, *res;
816 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
817 set_ia32_commutative(res);
818 set_ia32_am_support(res, ia32_am_Source);
820 /* imediates are not supported, so no fold_immediate */
821 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
822 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
826 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
834 * Creates an ia32 Mul.
836 * @param env The transformation environment
837 * @return the created ia32 Mul node
839 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) {
840 ir_node *op1 = get_Mul_left(node);
841 ir_node *op2 = get_Mul_right(node);
842 ir_mode *mode = get_irn_mode(node);
844 if (mode_is_float(mode)) {
846 if (USE_SSE2(env->cg))
847 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul);
849 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul);
852 // for the lower 32bit of the result it doesn't matter whether we use
853 // signed or unsigned multiplication so we use IMul as it has fewer
855 return gen_binop(env, node, op1, op2, new_rd_ia32_IMul);
859 * Creates an ia32 Mulh.
860 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
861 * this result while Mul returns the lower 32 bit.
863 * @param env The transformation environment
864 * @return the created ia32 Mulh node
866 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) {
867 ir_graph *irg = env->irg;
868 dbg_info *dbgi = get_irn_dbg_info(node);
869 ir_node *block = transform_node(env, get_nodes_block(node));
870 ir_node *op1 = get_irn_n(node, 0);
871 ir_node *op2 = get_irn_n(node, 1);
872 ir_node *new_op1 = transform_node(env, op1);
873 ir_node *new_op2 = transform_node(env, op2);
874 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
875 ir_node *proj_EAX, *proj_EDX, *res;
876 ir_mode *mode = get_irn_mode(node);
879 assert(!mode_is_float(mode) && "Mulh with float not supported");
880 if(mode_is_signed(mode)) {
881 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
883 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
886 set_ia32_commutative(res);
887 set_ia32_am_support(res, ia32_am_Source);
889 set_ia32_am_support(res, ia32_am_Source);
891 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
892 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
896 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
904 * Creates an ia32 And.
906 * @param env The transformation environment
907 * @return The created ia32 And node
909 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *node) {
910 ir_node *op1 = get_And_left(node);
911 ir_node *op2 = get_And_right(node);
913 assert (! mode_is_float(get_irn_mode(node)));
914 return gen_binop(env, node, op1, op2, new_rd_ia32_And);
920 * Creates an ia32 Or.
922 * @param env The transformation environment
923 * @return The created ia32 Or node
925 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *node) {
926 ir_node *op1 = get_Or_left(node);
927 ir_node *op2 = get_Or_right(node);
929 assert (! mode_is_float(get_irn_mode(node)));
930 return gen_binop(env, node, op1, op2, new_rd_ia32_Or);
936 * Creates an ia32 Eor.
938 * @param env The transformation environment
939 * @return The created ia32 Eor node
941 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *node) {
942 ir_node *op1 = get_Eor_left(node);
943 ir_node *op2 = get_Eor_right(node);
945 assert(! mode_is_float(get_irn_mode(node)));
946 return gen_binop(env, node, op1, op2, new_rd_ia32_Xor);
952 * Creates an ia32 Max.
954 * @param env The transformation environment
955 * @return the created ia32 Max node
957 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *node) {
958 ir_graph *irg = env->irg;
960 ir_mode *mode = get_irn_mode(node);
961 dbg_info *dbgi = get_irn_dbg_info(node);
962 ir_node *block = transform_node(env, get_nodes_block(node));
963 ir_node *op1 = get_irn_n(node, 0);
964 ir_node *op2 = get_irn_n(node, 1);
965 ir_node *new_op1 = transform_node(env, op1);
966 ir_node *new_op2 = transform_node(env, op2);
967 ir_mode *op_mode = get_irn_mode(op1);
969 assert(get_mode_size_bits(mode) == 32);
971 if (mode_is_float(mode)) {
973 if (USE_SSE2(env->cg)) {
974 new_op = gen_binop_float(env, node, new_op1, new_op2, new_rd_ia32_xMax);
976 panic("Can't create Max node");
979 long pnc = pn_Cmp_Gt;
980 if(!mode_is_signed(op_mode)) {
981 pnc |= ia32_pn_Cmp_Unsigned;
983 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
984 set_ia32_pncode(new_op, pnc);
985 set_ia32_am_support(new_op, ia32_am_None);
987 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
993 * Creates an ia32 Min.
995 * @param env The transformation environment
996 * @return the created ia32 Min node
998 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *node) {
999 ir_graph *irg = env->irg;
1001 ir_mode *mode = get_irn_mode(node);
1002 dbg_info *dbgi = get_irn_dbg_info(node);
1003 ir_node *block = transform_node(env, get_nodes_block(node));
1004 ir_node *op1 = get_irn_n(node, 0);
1005 ir_node *op2 = get_irn_n(node, 1);
1006 ir_node *new_op1 = transform_node(env, op1);
1007 ir_node *new_op2 = transform_node(env, op2);
1008 ir_mode *op_mode = get_irn_mode(op1);
1010 assert(get_mode_size_bits(mode) == 32);
1012 if (mode_is_float(mode)) {
1014 if (USE_SSE2(env->cg)) {
1015 new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMin);
1017 panic("can't create Min node");
1020 long pnc = pn_Cmp_Lt;
1021 if(!mode_is_signed(op_mode)) {
1022 pnc |= ia32_pn_Cmp_Unsigned;
1024 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1025 set_ia32_pncode(new_op, pnc);
1026 set_ia32_am_support(new_op, ia32_am_None);
1028 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1035 * Creates an ia32 Sub.
1037 * @param env The transformation environment
1038 * @return The created ia32 Sub node
1040 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) {
1041 ir_node *new_op = NULL;
1042 ir_graph *irg = env->irg;
1043 dbg_info *dbgi = get_irn_dbg_info(node);
1044 ir_mode *mode = get_irn_mode(node);
1045 ir_node *block = transform_node(env, get_nodes_block(node));
1046 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1047 ir_node *nomem = new_NoMem();
1048 ir_node *op1 = get_Sub_left(node);
1049 ir_node *op2 = get_Sub_right(node);
1050 ir_node *new_op1 = transform_node(env, op1);
1051 ir_node *new_op2 = transform_node(env, op2);
1052 ir_node *expr_op, *imm_op;
1054 /* Check if immediate optimization is on and */
1055 /* if it's an operation with immediate. */
1056 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1057 expr_op = get_expr_op(new_op1, new_op2);
1059 assert((expr_op || imm_op) && "invalid operands");
1061 if (mode_is_float(mode)) {
1063 if (USE_SSE2(env->cg))
1064 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xSub);
1066 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfsub);
1071 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1072 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1074 /* No expr_op means, that we have two const - one symconst and */
1075 /* one tarval or another symconst - because this case is not */
1076 /* covered by constant folding */
1077 /* We need to check for: */
1078 /* 1) symconst - const -> becomes a LEA */
1079 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1080 /* linker doesn't support two symconsts */
1081 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1082 /* this is the 2nd case */
1083 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1084 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1085 set_ia32_am_sc_sign(new_op);
1086 set_ia32_am_flavour(new_op, ia32_am_OB);
1088 DBG_OPT_LEA3(op1, op2, node, new_op);
1089 } else if (tp1 == ia32_ImmSymConst) {
1090 tarval *tv = get_ia32_Immop_tarval(new_op2);
1091 long offs = get_tarval_long(tv);
1093 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1094 DBG_OPT_LEA3(op1, op2, node, new_op);
1096 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1097 add_ia32_am_offs_int(new_op, -offs);
1098 set_ia32_am_flavour(new_op, ia32_am_O);
1099 set_ia32_am_support(new_op, ia32_am_Source);
1100 set_ia32_op_type(new_op, ia32_AddrModeS);
1101 } else if (tp2 == ia32_ImmSymConst) {
1102 tarval *tv = get_ia32_Immop_tarval(new_op1);
1103 long offs = get_tarval_long(tv);
1105 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1106 DBG_OPT_LEA3(op1, op2, node, new_op);
1108 add_ia32_am_offs_int(new_op, offs);
1109 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1110 set_ia32_am_sc_sign(new_op);
1111 set_ia32_am_flavour(new_op, ia32_am_O);
1112 set_ia32_am_support(new_op, ia32_am_Source);
1113 set_ia32_op_type(new_op, ia32_AddrModeS);
1115 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1116 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1117 tarval *restv = tarval_sub(tv1, tv2);
1119 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1121 new_op = new_rd_ia32_Const(dbgi, irg, block);
1122 set_ia32_Const_tarval(new_op, restv);
1123 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1126 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1128 } else if (imm_op) {
1129 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1130 tarval_classification_t class_tv, class_negtv;
1131 tarval *tv = get_ia32_Immop_tarval(imm_op);
1133 /* optimize tarvals */
1134 class_tv = classify_tarval(tv);
1135 class_negtv = classify_tarval(tarval_neg(tv));
1137 if (class_tv == TV_CLASSIFY_ONE) {
1138 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1139 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1140 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1142 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1143 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1144 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1145 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1151 /* This is a normal sub */
1152 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1154 /* set AM support */
1155 set_ia32_am_support(new_op, ia32_am_Full);
1157 fold_immediate(env, new_op, 2, 3);
1159 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1167 * Generates an ia32 DivMod with additional infrastructure for the
1168 * register allocator if needed.
1170 * @param env The transformation environment
1171 * @param dividend -no comment- :)
1172 * @param divisor -no comment- :)
1173 * @param dm_flav flavour_Div/Mod/DivMod
1174 * @return The created ia32 DivMod node
1176 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *node,
1177 ir_node *dividend, ir_node *divisor,
1178 ia32_op_flavour_t dm_flav) {
1179 ir_graph *irg = env->irg;
1180 dbg_info *dbgi = get_irn_dbg_info(node);
1181 ir_mode *mode = get_irn_mode(node);
1182 ir_node *block = transform_node(env, get_nodes_block(node));
1183 ir_node *res, *proj_div, *proj_mod;
1184 ir_node *edx_node, *cltd;
1185 ir_node *in_keep[1];
1186 ir_node *mem, *new_mem;
1187 ir_node *projs[pn_DivMod_max];
1188 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1189 ir_node *new_dividend = transform_node(env, dividend);
1190 ir_node *new_divisor = transform_node(env, divisor);
1192 ia32_collect_Projs(node, projs, pn_DivMod_max);
1196 mem = get_Div_mem(node);
1197 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Div_res));
1200 mem = get_Mod_mem(node);
1201 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Mod_res));
1203 case flavour_DivMod:
1204 mem = get_DivMod_mem(node);
1205 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1206 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1207 mode = proj_div ? get_irn_mode(proj_div) : get_irn_mode(proj_mod);
1210 panic("invalid divmod flavour!");
1212 new_mem = transform_node(env, mem);
1214 if (mode_is_signed(mode)) {
1215 /* in signed mode, we need to sign extend the dividend */
1216 cltd = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1217 new_dividend = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1218 edx_node = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1220 edx_node = new_rd_ia32_Const(dbgi, irg, block);
1221 add_irn_dep(edx_node, be_abi_get_start_barrier(env->cg->birg->abi));
1222 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1225 if(mode_is_signed(mode)) {
1226 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1228 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1231 /* Matze: code can't handle this at the moment... */
1233 /* set AM support */
1234 set_ia32_am_support(res, ia32_am_Source);
1237 set_ia32_n_res(res, 2);
1239 /* Only one proj is used -> We must add a second proj and */
1240 /* connect this one to a Keep node to eat up the second */
1241 /* destroyed register. */
1242 /* We also renumber the Firm projs into ia32 projs. */
1244 switch (get_irn_opcode(node)) {
1246 /* add Proj-Keep for mod res */
1247 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1248 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1251 /* add Proj-Keep for div res */
1252 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1253 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1256 /* check, which Proj-Keep, we need to add */
1257 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1258 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1260 if (proj_div && proj_mod) {
1261 /* nothing to be done */
1263 else if (! proj_div && ! proj_mod) {
1264 assert(0 && "Missing DivMod result proj");
1266 else if (! proj_div) {
1267 /* We have only mod result: add div res Proj-Keep */
1268 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1269 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1272 /* We have only div result: add mod res Proj-Keep */
1273 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1274 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1278 assert(0 && "Div, Mod, or DivMod expected.");
1282 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1289 * Wrapper for generate_DivMod. Sets flavour_Mod.
1291 * @param env The transformation environment
1293 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *node) {
1294 return generate_DivMod(env, node, get_Mod_left(node),
1295 get_Mod_right(node), flavour_Mod);
1299 * Wrapper for generate_DivMod. Sets flavour_Div.
1301 * @param env The transformation environment
1303 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *node) {
1304 return generate_DivMod(env, node, get_Div_left(node),
1305 get_Div_right(node), flavour_Div);
1309 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1311 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *node) {
1312 return generate_DivMod(env, node, get_DivMod_left(node),
1313 get_DivMod_right(node), flavour_DivMod);
1319 * Creates an ia32 floating Div.
1321 * @param env The transformation environment
1322 * @return The created ia32 xDiv node
1324 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *node) {
1325 ir_graph *irg = env->irg;
1326 dbg_info *dbgi = get_irn_dbg_info(node);
1327 ir_node *block = transform_node(env, get_nodes_block(node));
1328 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1330 ir_node *nomem = new_rd_NoMem(env->irg);
1331 ir_node *op1 = get_Quot_left(node);
1332 ir_node *op2 = get_Quot_right(node);
1333 ir_node *new_op1 = transform_node(env, op1);
1334 ir_node *new_op2 = transform_node(env, op2);
1337 if (USE_SSE2(env->cg)) {
1338 ir_mode *mode = get_irn_mode(op1);
1339 if (is_ia32_xConst(new_op2)) {
1340 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1341 set_ia32_am_support(new_op, ia32_am_None);
1342 copy_ia32_Immop_attr(new_op, new_op2);
1344 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1345 // Matze: disabled for now, spillslot coalescer fails
1346 //set_ia32_am_support(new_op, ia32_am_Source);
1348 set_ia32_ls_mode(new_op, mode);
1350 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1351 // Matze: disabled for now (spillslot coalescer fails)
1352 //set_ia32_am_support(new_op, ia32_am_Source);
1354 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1360 * Creates an ia32 Shl.
1362 * @param env The transformation environment
1363 * @return The created ia32 Shl node
1365 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *node) {
1366 return gen_shift_binop(env, node, get_Shl_left(node), get_Shl_right(node),
1373 * Creates an ia32 Shr.
1375 * @param env The transformation environment
1376 * @return The created ia32 Shr node
1378 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *node) {
1379 return gen_shift_binop(env, node, get_Shr_left(node),
1380 get_Shr_right(node), new_rd_ia32_Shr);
1386 * Creates an ia32 Sar.
1388 * @param env The transformation environment
1389 * @return The created ia32 Shrs node
1391 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) {
1392 return gen_shift_binop(env, node, get_Shrs_left(node),
1393 get_Shrs_right(node), new_rd_ia32_Sar);
1399 * Creates an ia32 RotL.
1401 * @param env The transformation environment
1402 * @param op1 The first operator
1403 * @param op2 The second operator
1404 * @return The created ia32 RotL node
1406 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node,
1407 ir_node *op1, ir_node *op2) {
1408 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Rol);
1414 * Creates an ia32 RotR.
1415 * NOTE: There is no RotR with immediate because this would always be a RotL
1416 * "imm-mode_size_bits" which can be pre-calculated.
1418 * @param env The transformation environment
1419 * @param op1 The first operator
1420 * @param op2 The second operator
1421 * @return The created ia32 RotR node
1423 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1,
1425 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Ror);
1431 * Creates an ia32 RotR or RotL (depending on the found pattern).
1433 * @param env The transformation environment
1434 * @return The created ia32 RotL or RotR node
1436 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) {
1437 ir_node *rotate = NULL;
1438 ir_node *op1 = get_Rot_left(node);
1439 ir_node *op2 = get_Rot_right(node);
1441 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1442 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1443 that means we can create a RotR instead of an Add and a RotL */
1445 if (get_irn_op(op2) == op_Add) {
1447 ir_node *left = get_Add_left(add);
1448 ir_node *right = get_Add_right(add);
1449 if (is_Const(right)) {
1450 tarval *tv = get_Const_tarval(right);
1451 ir_mode *mode = get_irn_mode(node);
1452 long bits = get_mode_size_bits(mode);
1454 if (get_irn_op(left) == op_Minus &&
1455 tarval_is_long(tv) &&
1456 get_tarval_long(tv) == bits)
1458 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1459 rotate = gen_RotR(env, node, op1, get_Minus_op(left));
1464 if (rotate == NULL) {
1465 rotate = gen_RotL(env, node, op1, op2);
1474 * Transforms a Minus node.
1476 * @param env The transformation environment
1477 * @param op The Minus operand
1478 * @return The created ia32 Minus node
1480 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *node, ir_node *op) {
1483 ir_graph *irg = env->irg;
1484 dbg_info *dbgi = get_irn_dbg_info(node);
1485 ir_node *block = transform_node(env, get_nodes_block(node));
1486 ir_mode *mode = get_irn_mode(node);
1489 if (mode_is_float(mode)) {
1490 ir_node *new_op = transform_node(env, op);
1492 if (USE_SSE2(env->cg)) {
1493 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1494 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1495 ir_node *nomem = new_rd_NoMem(irg);
1497 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1499 size = get_mode_size_bits(mode);
1500 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1502 set_ia32_am_sc(res, ent);
1503 set_ia32_op_type(res, ia32_AddrModeS);
1504 set_ia32_ls_mode(res, mode);
1506 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1509 res = gen_unop(env, node, op, new_rd_ia32_Neg);
1512 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1518 * Transforms a Minus node.
1520 * @param env The transformation environment
1521 * @return The created ia32 Minus node
1523 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *node) {
1524 return gen_Minus_ex(env, node, get_Minus_op(node));
1529 * Transforms a Not node.
1531 * @param env The transformation environment
1532 * @return The created ia32 Not node
1534 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *node) {
1535 ir_node *op = get_Not_op(node);
1537 assert (! mode_is_float(get_irn_mode(node)));
1538 return gen_unop(env, node, op, new_rd_ia32_Not);
1544 * Transforms an Abs node.
1546 * @param env The transformation environment
1547 * @return The created ia32 Abs node
1549 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *node) {
1550 ir_node *res, *p_eax, *p_edx;
1551 ir_graph *irg = env->irg;
1552 dbg_info *dbgi = get_irn_dbg_info(node);
1553 ir_node *block = transform_node(env, get_nodes_block(node));
1554 ir_mode *mode = get_irn_mode(node);
1555 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1556 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1557 ir_node *nomem = new_NoMem();
1558 ir_node *op = get_Abs_op(node);
1559 ir_node *new_op = transform_node(env, op);
1563 if (mode_is_float(mode)) {
1565 if (USE_SSE2(env->cg)) {
1566 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1568 size = get_mode_size_bits(mode);
1569 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1571 set_ia32_am_sc(res, ent);
1573 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1575 set_ia32_op_type(res, ia32_AddrModeS);
1576 set_ia32_ls_mode(res, mode);
1579 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1580 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1584 res = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1585 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1587 p_eax = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
1588 p_edx = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1590 res = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1591 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1593 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1594 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1603 * Transforms a Load.
1605 * @param env The transformation environment
1606 * @return the created ia32 Load node
1608 static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) {
1609 ir_graph *irg = env->irg;
1610 dbg_info *dbgi = get_irn_dbg_info(node);
1611 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1612 ir_mode *mode = get_Load_mode(node);
1613 ir_node *block = transform_node(env, get_nodes_block(node));
1614 ir_node *ptr = get_Load_ptr(node);
1615 ir_node *new_ptr = transform_node(env, ptr);
1616 ir_node *lptr = new_ptr;
1617 ir_node *mem = get_Load_mem(node);
1618 ir_node *new_mem = transform_node(env, mem);
1621 ia32_am_flavour_t am_flav = ia32_am_B;
1622 ir_node *projs[pn_Load_max];
1624 ia32_collect_Projs(node, projs, pn_Load_max);
1627 check for special case: the loaded value might not be used (optimized, volatile, ...)
1628 we add a Proj + Keep for volatile loads and ignore all other cases
1630 if (! be_get_Proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1631 /* add a result proj and a Keep to produce a pseudo use */
1632 ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res);
1633 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), irg, block, 1, &proj);
1636 /* address might be a constant (symconst or absolute address) */
1637 if (is_ia32_Const(new_ptr)) {
1642 if (mode_is_float(mode)) {
1644 if (USE_SSE2(env->cg)) {
1645 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1647 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem);
1650 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1653 /* base is a constant address */
1655 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1656 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1657 am_flav = ia32_am_N;
1659 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1660 long offs = get_tarval_long(tv);
1662 add_ia32_am_offs_int(new_op, offs);
1663 am_flav = ia32_am_O;
1667 set_ia32_am_support(new_op, ia32_am_Source);
1668 set_ia32_op_type(new_op, ia32_AddrModeS);
1669 set_ia32_am_flavour(new_op, am_flav);
1670 set_ia32_ls_mode(new_op, mode);
1672 /* make sure we are scheduled behind the intial IncSP/Barrier
1673 * to avoid spills being placed before it
1675 if(block == get_irg_start_block(irg)) {
1676 add_irn_dep(new_op, get_irg_frame(irg));
1679 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1687 * Transforms a Store.
1689 * @param env The transformation environment
1690 * @return the created ia32 Store node
1692 static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) {
1693 ir_graph *irg = env->irg;
1694 dbg_info *dbgi = get_irn_dbg_info(node);
1695 ir_node *block = transform_node(env, get_nodes_block(node));
1696 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1697 ir_node *ptr = get_Store_ptr(node);
1698 ir_node *new_ptr = transform_node(env, ptr);
1699 ir_node *sptr = new_ptr;
1700 ir_node *val = get_Store_value(node);
1701 ir_node *new_val = transform_node(env, val);
1702 ir_node *mem = get_Store_mem(node);
1703 ir_node *new_mem = transform_node(env, mem);
1704 ir_mode *mode = get_irn_mode(val);
1705 ir_node *sval = new_val;
1708 ia32_am_flavour_t am_flav = ia32_am_B;
1710 if (is_ia32_Const(new_val)) {
1711 assert(!mode_is_float(mode));
1715 /* address might be a constant (symconst or absolute address) */
1716 if (is_ia32_Const(new_ptr)) {
1721 if (mode_is_float(mode)) {
1723 if (USE_SSE2(env->cg)) {
1724 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, sval, new_mem);
1726 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, sval, new_mem);
1728 } else if (get_mode_size_bits(mode) == 8) {
1729 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg, sval, new_mem);
1731 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, sval, new_mem);
1734 /* stored const is an immediate value */
1735 if (is_ia32_Const(new_val)) {
1736 assert(!mode_is_float(mode));
1737 copy_ia32_Immop_attr(new_op, new_val);
1740 /* base is an constant address */
1742 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1743 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1744 am_flav = ia32_am_N;
1746 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1747 long offs = get_tarval_long(tv);
1749 add_ia32_am_offs_int(new_op, offs);
1750 am_flav = ia32_am_O;
1754 set_ia32_am_support(new_op, ia32_am_Dest);
1755 set_ia32_op_type(new_op, ia32_AddrModeD);
1756 set_ia32_am_flavour(new_op, am_flav);
1757 set_ia32_ls_mode(new_op, mode);
1759 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1767 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1769 * @param env The transformation environment
1770 * @return The transformed node.
1772 static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) {
1773 ir_graph *irg = env->irg;
1774 dbg_info *dbgi = get_irn_dbg_info(node);
1775 ir_node *block = transform_node(env, get_nodes_block(node));
1776 ir_node *sel = get_Cond_selector(node);
1777 ir_mode *sel_mode = get_irn_mode(sel);
1778 ir_node *res = NULL;
1779 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1780 ir_node *cnst, *expr;
1782 if (is_Proj(sel) && sel_mode == mode_b) {
1783 ir_node *nomem = new_NoMem();
1784 ir_node *pred = get_Proj_pred(sel);
1785 ir_node *cmp_a = get_Cmp_left(pred);
1786 ir_node *new_cmp_a = transform_node(env, cmp_a);
1787 ir_node *cmp_b = get_Cmp_right(pred);
1788 ir_node *new_cmp_b = transform_node(env, cmp_b);
1789 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1791 int pnc = get_Proj_proj(sel);
1792 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1793 pnc |= ia32_pn_Cmp_Unsigned;
1796 /* check if we can use a CondJmp with immediate */
1797 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1798 expr = get_expr_op(new_cmp_a, new_cmp_b);
1800 if (cnst != NULL && expr != NULL) {
1801 /* immop has to be the right operand, we might need to flip pnc */
1802 if(cnst != new_cmp_b) {
1803 pnc = get_inversed_pnc(pnc);
1806 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1807 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1808 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1810 /* a Cmp A =/!= 0 */
1811 ir_node *op1 = expr;
1812 ir_node *op2 = expr;
1815 /* check, if expr is an only once used And operation */
1816 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1817 op1 = get_irn_n(expr, 2);
1818 op2 = get_irn_n(expr, 3);
1820 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1822 res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2);
1823 set_ia32_pncode(res, pnc);
1826 copy_ia32_Immop_attr(res, expr);
1829 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1834 if (mode_is_float(cmp_mode)) {
1836 if (USE_SSE2(env->cg)) {
1837 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1838 set_ia32_ls_mode(res, cmp_mode);
1844 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1846 copy_ia32_Immop_attr(res, cnst);
1849 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1851 if (mode_is_float(cmp_mode)) {
1853 if (USE_SSE2(env->cg)) {
1854 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1855 set_ia32_ls_mode(res, cmp_mode);
1858 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1859 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1860 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1864 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1865 set_ia32_commutative(res);
1869 set_ia32_pncode(res, pnc);
1870 // Matze: disabled for now, because the default collect_spills_walker
1871 // is not able to detect the mode of the spilled value
1872 // moreover, the lea optimize phase freely exchanges left/right
1873 // without updating the pnc
1874 //set_ia32_am_support(res, ia32_am_Source);
1877 /* determine the smallest switch case value */
1878 int switch_min = INT_MAX;
1879 const ir_edge_t *edge;
1880 ir_node *new_sel = transform_node(env, sel);
1882 foreach_out_edge(node, edge) {
1883 int pn = get_Proj_proj(get_edge_src_irn(edge));
1884 switch_min = pn < switch_min ? pn : switch_min;
1888 /* if smallest switch case is not 0 we need an additional sub */
1889 res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1890 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1891 add_ia32_am_offs_int(res, -switch_min);
1892 set_ia32_am_flavour(res, ia32_am_OB);
1893 set_ia32_am_support(res, ia32_am_Source);
1894 set_ia32_op_type(res, ia32_AddrModeS);
1897 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T);
1898 set_ia32_pncode(res, get_Cond_defaultProj(node));
1901 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1908 * Transforms a CopyB node.
1910 * @param env The transformation environment
1911 * @return The transformed node.
1913 static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) {
1914 ir_node *res = NULL;
1915 ir_graph *irg = env->irg;
1916 dbg_info *dbgi = get_irn_dbg_info(node);
1917 ir_node *block = transform_node(env, get_nodes_block(node));
1918 ir_node *src = get_CopyB_src(node);
1919 ir_node *new_src = transform_node(env, src);
1920 ir_node *dst = get_CopyB_dst(node);
1921 ir_node *new_dst = transform_node(env, dst);
1922 ir_node *mem = get_CopyB_mem(node);
1923 ir_node *new_mem = transform_node(env, mem);
1924 int size = get_type_size_bytes(get_CopyB_type(node));
1925 ir_mode *dst_mode = get_irn_mode(dst);
1926 ir_mode *src_mode = get_irn_mode(src);
1930 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1931 /* then we need the size explicitly in ECX. */
1932 if (size >= 32 * 4) {
1933 rem = size & 0x3; /* size % 4 */
1936 res = new_rd_ia32_Const(dbgi, irg, block);
1937 add_irn_dep(res, be_abi_get_start_barrier(env->cg->birg->abi));
1938 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1940 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1941 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1943 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1944 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1945 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1946 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1947 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1950 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1951 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1953 /* ok: now attach Proj's because movsd will destroy esi and edi */
1954 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1955 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1956 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1959 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1967 * Transforms a Mux node into CMov.
1969 * @param env The transformation environment
1970 * @return The transformed node.
1972 static ir_node *gen_Mux(ia32_transform_env_t *env, ir_node *node) {
1973 ir_node *new_op = new_rd_ia32_CMov(env->dbgi, env->irg, env->block, \
1974 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1976 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1982 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
1983 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
1984 ir_node *psi_default);
1987 * Transforms a Psi node into CMov.
1989 * @param env The transformation environment
1990 * @return The transformed node.
1992 static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) {
1993 ia32_code_gen_t *cg = env->cg;
1994 ir_graph *irg = env->irg;
1995 dbg_info *dbgi = get_irn_dbg_info(node);
1996 ir_mode *mode = get_irn_mode(node);
1997 ir_node *block = transform_node(env, get_nodes_block(node));
1998 ir_node *cmp_proj = get_Mux_sel(node);
1999 ir_node *psi_true = get_Psi_val(node, 0);
2000 ir_node *psi_default = get_Psi_default(node);
2001 ir_node *new_psi_true = transform_node(env, psi_true);
2002 ir_node *new_psi_default = transform_node(env, psi_default);
2003 ir_node *noreg = ia32_new_NoReg_gp(cg);
2004 ir_node *nomem = new_rd_NoMem(irg);
2005 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
2006 ir_node *new_cmp_a, *new_cmp_b;
2010 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
2012 cmp = get_Proj_pred(cmp_proj);
2013 cmp_a = get_Cmp_left(cmp);
2014 cmp_b = get_Cmp_right(cmp);
2015 cmp_mode = get_irn_mode(cmp_a);
2016 new_cmp_a = transform_node(env, cmp_a);
2017 new_cmp_b = transform_node(env, cmp_b);
2019 pnc = get_Proj_proj(cmp_proj);
2020 if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2021 pnc |= ia32_pn_Cmp_Unsigned;
2024 if (mode_is_float(mode)) {
2025 /* floating point psi */
2028 /* 1st case: compare operands are float too */
2030 /* psi(cmp(a, b), t, f) can be done as: */
2031 /* tmp = cmp a, b */
2032 /* tmp2 = t and tmp */
2033 /* tmp3 = f and not tmp */
2034 /* res = tmp2 or tmp3 */
2036 /* in case the compare operands are int, we move them into xmm register */
2037 if (! mode_is_float(get_irn_mode(cmp_a))) {
2038 new_cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_a, node, mode_E);
2039 new_cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_b, node, mode_E);
2041 pnc |= 8; /* transform integer compare to fp compare */
2044 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2045 set_ia32_pncode(new_op, pnc);
2046 set_ia32_am_support(new_op, ia32_am_Source);
2047 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2049 and1 = new_rd_ia32_xAnd(dbgi, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2050 set_ia32_am_support(and1, ia32_am_None);
2051 set_ia32_commutative(and1);
2052 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2054 and2 = new_rd_ia32_xAndNot(dbgi, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2055 set_ia32_am_support(and2, ia32_am_None);
2056 set_ia32_commutative(and2);
2057 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2059 new_op = new_rd_ia32_xOr(dbgi, irg, block, noreg, noreg, and1, and2, nomem);
2060 set_ia32_am_support(new_op, ia32_am_None);
2061 set_ia32_commutative(new_op);
2062 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2066 new_op = new_rd_ia32_vfCMov(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2067 set_ia32_pncode(new_op, pnc);
2068 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2073 construct_binop_func *set_func = NULL;
2074 cmov_func_t *cmov_func = NULL;
2076 if (mode_is_float(get_irn_mode(cmp_a))) {
2077 /* 1st case: compare operands are floats */
2082 set_func = new_rd_ia32_xCmpSet;
2083 cmov_func = new_rd_ia32_xCmpCMov;
2087 set_func = new_rd_ia32_vfCmpSet;
2088 cmov_func = new_rd_ia32_vfCmpCMov;
2091 pnc &= ~0x8; /* fp compare -> int compare */
2094 /* 2nd case: compare operand are integer too */
2095 set_func = new_rd_ia32_CmpSet;
2096 cmov_func = new_rd_ia32_CmpCMov;
2099 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2100 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2101 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2102 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2103 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2104 set_ia32_pncode(new_op, pnc);
2106 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2107 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2108 /* we invert condition and set default to 0 */
2109 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2110 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2113 /* otherwise: use CMOVcc */
2114 new_op = new_rd_ia32_PsiCondCMov(dbgi, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2115 set_ia32_pncode(new_op, pnc);
2118 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2121 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2122 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2123 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2124 set_ia32_pncode(new_op, pnc);
2125 set_ia32_am_support(new_op, ia32_am_Source);
2127 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2128 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2129 /* we invert condition and set default to 0 */
2130 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2131 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2132 set_ia32_am_support(new_op, ia32_am_Source);
2135 /* otherwise: use CMOVcc */
2136 new_op = cmov_func(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2137 set_ia32_pncode(new_op, pnc);
2138 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2148 * Following conversion rules apply:
2152 * 1) n bit -> m bit n > m (downscale)
2154 * 2) n bit -> m bit n == m (sign change)
2156 * 3) n bit -> m bit n < m (upscale)
2157 * a) source is signed: movsx
2158 * b) source is unsigned: and with lower bits sets
2162 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2166 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2170 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2171 * x87 is mode_E internally, conversions happen only at load and store
2172 * in non-strict semantic
2176 * Create a conversion from x87 state register to general purpose.
2178 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) {
2179 ia32_code_gen_t *cg = env->cg;
2180 ir_graph *irg = env->irg;
2181 dbg_info *dbgi = get_irn_dbg_info(node);
2182 ir_node *block = transform_node(env, get_nodes_block(node));
2183 ir_node *noreg = ia32_new_NoReg_gp(cg);
2184 ir_node *op = get_Conv_op(node);
2185 ir_node *new_op = transform_node(env, op);
2186 ir_node *fist, *load;
2187 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2190 fist = new_rd_ia32_vfist(dbgi, irg, block,
2191 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2193 set_ia32_use_frame(fist);
2194 set_ia32_am_support(fist, ia32_am_Dest);
2195 set_ia32_op_type(fist, ia32_AddrModeD);
2196 set_ia32_am_flavour(fist, ia32_am_B);
2197 set_ia32_ls_mode(fist, mode_Iu);
2198 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2201 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2203 set_ia32_use_frame(load);
2204 set_ia32_am_support(load, ia32_am_Source);
2205 set_ia32_op_type(load, ia32_AddrModeS);
2206 set_ia32_am_flavour(load, ia32_am_B);
2207 set_ia32_ls_mode(load, mode_Iu);
2208 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2210 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2214 * Create a conversion from general purpose to x87 register
2216 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mode *src_mode) {
2218 ia32_code_gen_t *cg = env->cg;
2220 ir_graph *irg = env->irg;
2221 dbg_info *dbgi = get_irn_dbg_info(node);
2222 ir_mode *mode = get_irn_mode(node);
2223 ir_node *block = transform_node(env, get_nodes_block(node));
2224 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2225 ir_node *nomem = new_NoMem();
2226 ir_node *op = get_Conv_op(node);
2227 ir_node *new_op = transform_node(env, op);
2228 ir_node *fild, *store;
2231 /* first convert to 32 bit if necessary */
2232 src_bits = get_mode_size_bits(src_mode);
2233 if (src_bits == 8) {
2234 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2235 set_ia32_am_support(new_op, ia32_am_Source);
2236 set_ia32_ls_mode(new_op, src_mode);
2237 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2238 } else if (src_bits < 32) {
2239 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2240 set_ia32_am_support(new_op, ia32_am_Source);
2241 set_ia32_ls_mode(new_op, src_mode);
2242 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2246 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2248 set_ia32_use_frame(store);
2249 set_ia32_am_support(store, ia32_am_Dest);
2250 set_ia32_op_type(store, ia32_AddrModeD);
2251 set_ia32_am_flavour(store, ia32_am_OB);
2252 set_ia32_ls_mode(store, mode_Iu);
2255 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2257 set_ia32_use_frame(fild);
2258 set_ia32_am_support(fild, ia32_am_Source);
2259 set_ia32_op_type(fild, ia32_AddrModeS);
2260 set_ia32_am_flavour(fild, ia32_am_OB);
2261 set_ia32_ls_mode(fild, mode);
2263 return new_r_Proj(irg, block, fild, mode_F, pn_ia32_vfild_res);
2267 * Transforms a Conv node.
2269 * @param env The transformation environment
2270 * @return The created ia32 Conv node
2272 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) {
2273 ir_graph *irg = env->irg;
2274 dbg_info *dbgi = get_irn_dbg_info(node);
2275 ir_node *op = get_Conv_op(node);
2276 ir_mode *src_mode = get_irn_mode(op);
2277 ir_mode *tgt_mode = get_irn_mode(node);
2278 int src_bits = get_mode_size_bits(src_mode);
2279 int tgt_bits = get_mode_size_bits(tgt_mode);
2280 ir_node *block = transform_node(env, get_nodes_block(node));
2282 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2283 ir_node *nomem = new_rd_NoMem(irg);
2284 ir_node *new_op = transform_node(env, op);
2286 if (src_mode == tgt_mode) {
2287 /* this should be optimized already, but who knows... */
2288 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2289 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2293 if (mode_is_float(src_mode)) {
2294 /* we convert from float ... */
2295 if (mode_is_float(tgt_mode)) {
2297 if (USE_SSE2(env->cg)) {
2298 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2299 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2300 set_ia32_ls_mode(res, tgt_mode);
2302 // Matze: TODO what about strict convs?
2303 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2308 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2309 if (USE_SSE2(env->cg)) {
2310 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2311 set_ia32_ls_mode(res, src_mode);
2313 return gen_x87_fp_to_gp(env, node);
2317 /* we convert from int ... */
2318 if (mode_is_float(tgt_mode)) {
2321 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2322 if (USE_SSE2(env->cg)) {
2323 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2324 set_ia32_ls_mode(res, tgt_mode);
2325 if(src_bits == 32) {
2326 set_ia32_am_support(res, ia32_am_Source);
2329 return gen_x87_gp_to_fp(env, node, src_mode);
2333 ir_mode *smaller_mode;
2336 if (src_bits == tgt_bits) {
2337 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2341 if(src_bits < tgt_bits) {
2342 smaller_mode = src_mode;
2343 smaller_bits = src_bits;
2345 smaller_mode = tgt_mode;
2346 smaller_bits = tgt_bits;
2349 // The following is not correct, we can't change the mode,
2350 // maybe others are using the load too
2351 // better move this to a separate phase!
2354 if(is_Proj(new_op)) {
2355 /* load operations do already sign/zero extend, so we have
2356 * nothing left to do */
2357 ir_node *pred = get_Proj_pred(new_op);
2358 if(is_ia32_Load(pred)) {
2359 set_ia32_ls_mode(pred, smaller_mode);
2365 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2366 if (smaller_bits == 8) {
2367 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2368 set_ia32_ls_mode(res, smaller_mode);
2370 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2371 set_ia32_ls_mode(res, smaller_mode);
2373 set_ia32_am_support(res, ia32_am_Source);
2377 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2384 /********************************************
2387 * | |__ ___ _ __ ___ __| | ___ ___
2388 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2389 * | |_) | __/ | | | (_) | (_| | __/\__ \
2390 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2392 ********************************************/
2394 static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) {
2395 ir_node *new_op = NULL;
2396 ir_graph *irg = env->irg;
2397 dbg_info *dbgi = get_irn_dbg_info(node);
2398 ir_node *block = transform_node(env, get_nodes_block(node));
2399 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2400 ir_node *nomem = new_rd_NoMem(env->irg);
2401 ir_node *ptr = get_irn_n(node, 0);
2402 ir_node *new_ptr = transform_node(env, ptr);
2403 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2404 ir_mode *load_mode = get_irn_mode(node);
2408 if (mode_is_float(load_mode)) {
2410 if (USE_SSE2(env->cg)) {
2411 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2412 pn_res = pn_ia32_xLoad_res;
2414 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem);
2415 pn_res = pn_ia32_vfld_res;
2420 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2421 proj_mode = mode_Iu;
2422 pn_res = pn_ia32_Load_res;
2425 set_ia32_frame_ent(new_op, ent);
2426 set_ia32_use_frame(new_op);
2428 set_ia32_am_support(new_op, ia32_am_Source);
2429 set_ia32_op_type(new_op, ia32_AddrModeS);
2430 set_ia32_am_flavour(new_op, ia32_am_B);
2431 set_ia32_ls_mode(new_op, load_mode);
2432 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2434 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2436 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2440 * Transforms a FrameAddr into an ia32 Add.
2442 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) {
2443 ir_graph *irg = env->irg;
2444 dbg_info *dbgi = get_irn_dbg_info(node);
2445 ir_node *block = transform_node(env, get_nodes_block(node));
2446 ir_node *op = get_irn_n(node, 0);
2447 ir_node *new_op = transform_node(env, op);
2449 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2451 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2452 set_ia32_frame_ent(res, arch_get_frame_entity(env->cg->arch_env, node));
2453 set_ia32_am_support(res, ia32_am_Full);
2454 set_ia32_use_frame(res);
2455 set_ia32_am_flavour(res, ia32_am_OB);
2457 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2463 * Transforms a FrameLoad into an ia32 Load.
2465 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) {
2466 ir_node *new_op = NULL;
2467 ir_graph *irg = env->irg;
2468 dbg_info *dbgi = get_irn_dbg_info(node);
2469 ir_node *block = transform_node(env, get_nodes_block(node));
2470 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2471 ir_node *mem = get_irn_n(node, 0);
2472 ir_node *ptr = get_irn_n(node, 1);
2473 ir_node *new_mem = transform_node(env, mem);
2474 ir_node *new_ptr = transform_node(env, ptr);
2475 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2476 ir_mode *mode = get_type_mode(get_entity_type(ent));
2477 ir_node *projs[pn_Load_max];
2479 ia32_collect_Projs(node, projs, pn_Load_max);
2481 if (mode_is_float(mode)) {
2483 if (USE_SSE2(env->cg)) {
2484 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2487 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
2491 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2494 set_ia32_frame_ent(new_op, ent);
2495 set_ia32_use_frame(new_op);
2497 set_ia32_am_support(new_op, ia32_am_Source);
2498 set_ia32_op_type(new_op, ia32_AddrModeS);
2499 set_ia32_am_flavour(new_op, ia32_am_B);
2500 set_ia32_ls_mode(new_op, mode);
2502 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2509 * Transforms a FrameStore into an ia32 Store.
2511 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) {
2512 ir_node *new_op = NULL;
2513 ir_graph *irg = env->irg;
2514 dbg_info *dbgi = get_irn_dbg_info(node);
2515 ir_node *block = transform_node(env, get_nodes_block(node));
2516 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2517 ir_node *mem = get_irn_n(node, 0);
2518 ir_node *ptr = get_irn_n(node, 1);
2519 ir_node *val = get_irn_n(node, 2);
2520 ir_node *new_mem = transform_node(env, mem);
2521 ir_node *new_ptr = transform_node(env, ptr);
2522 ir_node *new_val = transform_node(env, val);
2523 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2524 ir_mode *mode = get_irn_mode(val);
2526 if (mode_is_float(mode)) {
2528 if (USE_SSE2(env->cg)) {
2529 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2532 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2535 else if (get_mode_size_bits(mode) == 8) {
2536 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2539 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2542 set_ia32_frame_ent(new_op, ent);
2543 set_ia32_use_frame(new_op);
2545 set_ia32_am_support(new_op, ia32_am_Dest);
2546 set_ia32_op_type(new_op, ia32_AddrModeD);
2547 set_ia32_am_flavour(new_op, ia32_am_B);
2548 set_ia32_ls_mode(new_op, mode);
2550 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2556 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2558 static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
2559 ir_graph *irg = env->irg;
2562 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2563 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2564 ir_entity *ent = get_irg_entity(irg);
2565 ir_type *tp = get_entity_type(ent);
2568 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2569 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2571 int pn_ret_val, pn_ret_mem, arity, i;
2573 assert(ret_val != NULL);
2574 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env->cg)) {
2575 return duplicate_node(env, node);
2578 res_type = get_method_res_type(tp, 0);
2580 if (!is_Primitive_type(res_type)) {
2581 return duplicate_node(env, node);
2584 mode = get_type_mode(res_type);
2585 if (!mode_is_float(mode)) {
2586 return duplicate_node(env, node);
2589 assert(get_method_n_ress(tp) == 1);
2591 pn_ret_val = get_Proj_proj(ret_val);
2592 pn_ret_mem = get_Proj_proj(ret_mem);
2594 /* get the Barrier */
2595 barrier = get_Proj_pred(ret_val);
2597 /* get result input of the Barrier */
2598 ret_val = get_irn_n(barrier, pn_ret_val);
2599 new_ret_val = transform_node(env, ret_val);
2601 /* get memory input of the Barrier */
2602 ret_mem = get_irn_n(barrier, pn_ret_mem);
2603 new_ret_mem = transform_node(env, ret_mem);
2605 frame = get_irg_frame(irg);
2607 dbgi = get_irn_dbg_info(barrier);
2608 block = transform_node(env, get_nodes_block(barrier));
2610 /* store xmm0 onto stack */
2611 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, new_ret_val, new_ret_mem);
2612 set_ia32_ls_mode(sse_store, mode);
2613 set_ia32_op_type(sse_store, ia32_AddrModeD);
2614 set_ia32_use_frame(sse_store);
2615 set_ia32_am_flavour(sse_store, ia32_am_B);
2616 set_ia32_am_support(sse_store, ia32_am_Dest);
2619 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, sse_store);
2620 set_ia32_ls_mode(fld, mode);
2621 set_ia32_op_type(fld, ia32_AddrModeS);
2622 set_ia32_use_frame(fld);
2623 set_ia32_am_flavour(fld, ia32_am_B);
2624 set_ia32_am_support(fld, ia32_am_Source);
2626 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
2627 fld = new_r_Proj(irg, block, fld, mode_E, pn_ia32_SetST0_res);
2628 arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2630 /* create a new barrier */
2631 arity = get_irn_arity(barrier);
2632 in = alloca(arity * sizeof(in[0]));
2633 for(i = 0; i < arity; ++i) {
2635 if(i == pn_ret_val) {
2637 } else if(i == pn_ret_mem) {
2640 ir_node *in = get_irn_n(barrier, i);
2641 new_in = transform_node(env, in);
2646 new_barrier = new_ir_node(dbgi, irg, block,
2647 get_irn_op(barrier), get_irn_mode(barrier),
2649 copy_node_attr(barrier, new_barrier);
2650 duplicate_deps(env, barrier, new_barrier);
2651 set_new_node(barrier, new_barrier);
2652 mark_irn_visited(barrier);
2654 /* transform normally */
2655 return duplicate_node(env, node);
2659 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2661 static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
2663 ir_graph *irg = env->irg;
2664 dbg_info *dbgi = get_irn_dbg_info(node);
2665 ir_node *block = transform_node(env, get_nodes_block(node));
2666 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
2667 ir_node *new_sz = transform_node(env, sz);
2668 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
2669 ir_node *new_sp = transform_node(env, sp);
2670 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2671 ir_node *nomem = new_NoMem();
2673 /* ia32 stack grows in reverse direction, make a SubSP */
2674 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2675 set_ia32_am_support(new_op, ia32_am_Source);
2676 fold_immediate(env, new_op, 2, 3);
2678 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2684 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
2686 static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
2688 ir_graph *irg = env->irg;
2689 dbg_info *dbgi = get_irn_dbg_info(node);
2690 ir_node *block = transform_node(env, get_nodes_block(node));
2691 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
2692 ir_node *new_sz = transform_node(env, sz);
2693 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
2694 ir_node *new_sp = transform_node(env, sp);
2695 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2696 ir_node *nomem = new_NoMem();
2698 /* ia32 stack grows in reverse direction, make an AddSP */
2699 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2700 set_ia32_am_support(new_op, ia32_am_Source);
2701 fold_immediate(env, new_op, 2, 3);
2703 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2709 * This function just sets the register for the Unknown node
2710 * as this is not done during register allocation because Unknown
2711 * is an "ignore" node.
2713 static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) {
2714 ir_mode *mode = get_irn_mode(node);
2716 if (mode_is_float(mode)) {
2717 if (USE_SSE2(env->cg))
2718 return ia32_new_Unknown_xmm(env->cg);
2720 return ia32_new_Unknown_vfp(env->cg);
2721 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
2722 return ia32_new_Unknown_gp(env->cg);
2724 assert(0 && "unsupported Unknown-Mode");
2731 * Change some phi modes
2733 static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
2734 ir_graph *irg = env->irg;
2735 dbg_info *dbgi = get_irn_dbg_info(node);
2736 ir_mode *mode = get_irn_mode(node);
2737 ir_node *block = transform_node(env, get_nodes_block(node));
2741 if(mode_is_int(mode) || mode_is_reference(mode)) {
2742 // we shouldn't have any 64bit stuff around anymore
2743 assert(get_mode_size_bits(mode) <= 32);
2744 // all integer operations are on 32bit registers now
2746 } else if(mode_is_float(mode)) {
2747 assert(mode == mode_D || mode == mode_F);
2748 // all float operations are on mode_E registers
2752 /* phi nodes allow loops, so we use the old arguments for now
2753 * and fix this later */
2754 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
2755 get_irn_in(node) + 1);
2756 copy_node_attr(node, phi);
2757 duplicate_deps(env, node, phi);
2759 set_new_node(node, phi);
2761 /* put the preds in the worklist */
2762 arity = get_irn_arity(node);
2763 for(i = 0; i < arity; ++i) {
2764 ir_node *pred = get_irn_n(node, i);
2765 pdeq_putr(env->worklist, pred);
2771 /**********************************************************************
2774 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2775 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2776 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2777 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2779 **********************************************************************/
2781 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2783 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2786 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2787 ir_node *val, ir_node *mem);
2790 * Transforms a lowered Load into a "real" one.
2792 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) {
2793 ir_graph *irg = env->irg;
2794 dbg_info *dbgi = get_irn_dbg_info(node);
2795 ir_node *block = transform_node(env, get_nodes_block(node));
2796 ir_mode *mode = get_ia32_ls_mode(node);
2798 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2799 ir_node *ptr = get_irn_n(node, 0);
2800 ir_node *mem = get_irn_n(node, 1);
2801 ir_node *new_ptr = transform_node(env, ptr);
2802 ir_node *new_mem = transform_node(env, mem);
2805 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2806 lowering we have x87 nodes, so we need to enforce simulation.
2808 if (mode_is_float(mode)) {
2810 if (fp_unit == fp_x87)
2814 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
2816 set_ia32_am_support(new_op, ia32_am_Source);
2817 set_ia32_op_type(new_op, ia32_AddrModeS);
2818 set_ia32_am_flavour(new_op, ia32_am_OB);
2819 set_ia32_am_offs_int(new_op, 0);
2820 set_ia32_am_scale(new_op, 1);
2821 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
2822 if(is_ia32_am_sc_sign(node))
2823 set_ia32_am_sc_sign(new_op);
2824 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
2825 if(is_ia32_use_frame(node)) {
2826 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2827 set_ia32_use_frame(new_op);
2830 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2836 * Transforms a lowered Store into a "real" one.
2838 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) {
2839 ir_graph *irg = env->irg;
2840 dbg_info *dbgi = get_irn_dbg_info(node);
2841 ir_node *block = transform_node(env, get_nodes_block(node));
2842 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2843 ir_mode *mode = get_ia32_ls_mode(node);
2846 ia32_am_flavour_t am_flav = ia32_B;
2847 ir_node *ptr = get_irn_n(node, 0);
2848 ir_node *val = get_irn_n(node, 1);
2849 ir_node *mem = get_irn_n(node, 2);
2850 ir_node *new_ptr = transform_node(env, ptr);
2851 ir_node *new_val = transform_node(env, val);
2852 ir_node *new_mem = transform_node(env, mem);
2855 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2856 lowering we have x87 nodes, so we need to enforce simulation.
2858 if (mode_is_float(mode)) {
2860 if (fp_unit == fp_x87)
2864 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2866 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
2868 add_ia32_am_offs_int(new_op, am_offs);
2871 set_ia32_am_support(new_op, ia32_am_Dest);
2872 set_ia32_op_type(new_op, ia32_AddrModeD);
2873 set_ia32_am_flavour(new_op, am_flav);
2874 set_ia32_ls_mode(new_op, mode);
2875 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2876 set_ia32_use_frame(new_op);
2878 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2885 * Transforms an ia32_l_XXX into a "real" XXX node
2887 * @param env The transformation environment
2888 * @return the created ia32 XXX node
2890 #define GEN_LOWERED_OP(op) \
2891 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2892 ir_mode *mode = get_irn_mode(node); \
2893 if (mode_is_float(mode)) \
2895 return gen_binop(env, node, get_binop_left(node), \
2896 get_binop_right(node), new_rd_ia32_##op); \
2899 #define GEN_LOWERED_x87_OP(op) \
2900 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2902 FORCE_x87(env->cg); \
2903 new_op = gen_binop_float(env, node, get_binop_left(node), \
2904 get_binop_right(node), new_rd_ia32_##op); \
2908 #define GEN_LOWERED_UNOP(op) \
2909 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2910 return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \
2913 #define GEN_LOWERED_SHIFT_OP(op) \
2914 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2915 return gen_shift_binop(env, node, get_binop_left(node), \
2916 get_binop_right(node), new_rd_ia32_##op); \
2919 #define GEN_LOWERED_LOAD(op, fp_unit) \
2920 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2921 return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \
2924 #define GEN_LOWERED_STORE(op, fp_unit) \
2925 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2926 return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \
2933 GEN_LOWERED_OP(IMul)
2935 GEN_LOWERED_x87_OP(vfprem)
2936 GEN_LOWERED_x87_OP(vfmul)
2937 GEN_LOWERED_x87_OP(vfsub)
2939 GEN_LOWERED_UNOP(Neg)
2941 GEN_LOWERED_LOAD(vfild, fp_x87)
2942 GEN_LOWERED_LOAD(Load, fp_none)
2943 /*GEN_LOWERED_STORE(vfist, fp_x87)
2946 GEN_LOWERED_STORE(Store, fp_none)
2948 static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
2949 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2950 ir_graph *irg = env->irg;
2951 dbg_info *dbgi = get_irn_dbg_info(node);
2952 ir_node *block = transform_node(env, get_nodes_block(node));
2953 ir_node *left = get_binop_left(node);
2954 ir_node *right = get_binop_right(node);
2955 ir_node *new_left = transform_node(env, left);
2956 ir_node *new_right = transform_node(env, right);
2959 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
2960 clear_ia32_commutative(vfdiv);
2961 set_ia32_am_support(vfdiv, ia32_am_Source);
2962 fold_immediate(env, vfdiv, 2, 3);
2964 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env->cg, node));
2972 * Transforms a l_MulS into a "real" MulS node.
2974 * @param env The transformation environment
2975 * @return the created ia32 Mul node
2977 static ir_node *gen_ia32_l_Mul(ia32_transform_env_t *env, ir_node *node) {
2978 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2979 ir_graph *irg = env->irg;
2980 dbg_info *dbgi = get_irn_dbg_info(node);
2981 ir_node *block = transform_node(env, get_nodes_block(node));
2982 ir_node *left = get_binop_left(node);
2983 ir_node *right = get_binop_right(node);
2984 ir_node *new_left = transform_node(env, left);
2985 ir_node *new_right = transform_node(env, right);
2988 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
2989 /* and then skip the result Proj, because all needed Projs are already there. */
2990 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
2991 clear_ia32_commutative(muls);
2992 set_ia32_am_support(muls, ia32_am_Source);
2993 fold_immediate(env, muls, 2, 3);
2995 /* check if EAX and EDX proj exist, add missing one */
2996 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
2997 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
2998 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3000 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env->cg, node));
3005 GEN_LOWERED_SHIFT_OP(Shl)
3006 GEN_LOWERED_SHIFT_OP(Shr)
3007 GEN_LOWERED_SHIFT_OP(Sar)
3010 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3011 * op1 - target to be shifted
3012 * op2 - contains bits to be shifted into target
3014 * Only op3 can be an immediate.
3016 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *node,
3017 ir_node *op1, ir_node *op2,
3019 ir_node *new_op = NULL;
3020 ir_graph *irg = env->irg;
3021 dbg_info *dbgi = get_irn_dbg_info(node);
3022 ir_node *block = transform_node(env, get_nodes_block(node));
3023 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3024 ir_node *nomem = new_NoMem();
3026 ir_node *new_op1 = transform_node(env, op1);
3027 ir_node *new_op2 = transform_node(env, op2);
3028 ir_node *new_count = transform_node(env, count);
3031 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3033 /* Check if immediate optimization is on and */
3034 /* if it's an operation with immediate. */
3035 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3037 /* Limit imm_op within range imm8 */
3039 tv = get_ia32_Immop_tarval(imm_op);
3042 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3043 set_ia32_Immop_tarval(imm_op, tv);
3050 /* integer operations */
3052 /* This is ShiftD with const */
3053 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3055 if (is_ia32_l_ShlD(node))
3056 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3057 new_op1, new_op2, noreg, nomem);
3059 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3060 new_op1, new_op2, noreg, nomem);
3061 copy_ia32_Immop_attr(new_op, imm_op);
3064 /* This is a normal ShiftD */
3065 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3066 if (is_ia32_l_ShlD(node))
3067 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3068 new_op1, new_op2, new_count, nomem);
3070 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3071 new_op1, new_op2, new_count, nomem);
3074 /* set AM support */
3075 // Matze: node has unsupported format (6inputs)
3076 //set_ia32_am_support(new_op, ia32_am_Dest);
3078 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3080 set_ia32_emit_cl(new_op);
3085 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env, ir_node *node) {
3086 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3087 get_irn_n(node, 1), get_irn_n(node, 2));
3090 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env, ir_node *node) {
3091 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3092 get_irn_n(node, 1), get_irn_n(node, 2));
3096 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3098 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) {
3099 ia32_code_gen_t *cg = env->cg;
3100 ir_node *res = NULL;
3101 ir_graph *irg = env->irg;
3102 dbg_info *dbgi = get_irn_dbg_info(node);
3103 ir_node *block = transform_node(env, get_nodes_block(node));
3104 ir_node *ptr = get_irn_n(node, 0);
3105 ir_node *val = get_irn_n(node, 1);
3106 ir_node *new_val = transform_node(env, val);
3107 ir_node *mem = get_irn_n(node, 2);
3108 ir_node *noreg, *new_ptr, *new_mem;
3114 noreg = ia32_new_NoReg_gp(cg);
3115 new_mem = transform_node(env, mem);
3116 new_ptr = transform_node(env, ptr);
3118 /* Store x87 -> MEM */
3119 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3120 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3121 set_ia32_use_frame(res);
3122 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3123 set_ia32_am_support(res, ia32_am_Dest);
3124 set_ia32_am_flavour(res, ia32_B);
3125 set_ia32_op_type(res, ia32_AddrModeD);
3127 /* Load MEM -> SSE */
3128 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3129 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3130 set_ia32_use_frame(res);
3131 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3132 set_ia32_am_support(res, ia32_am_Source);
3133 set_ia32_am_flavour(res, ia32_B);
3134 set_ia32_op_type(res, ia32_AddrModeS);
3135 res = new_rd_Proj(dbgi, irg, block, res, mode_E, pn_ia32_xLoad_res);
3141 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3143 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) {
3144 ia32_code_gen_t *cg = env->cg;
3145 ir_graph *irg = env->irg;
3146 dbg_info *dbgi = get_irn_dbg_info(node);
3147 ir_node *block = transform_node(env, get_nodes_block(node));
3148 ir_node *res = NULL;
3149 ir_node *ptr = get_irn_n(node, 0);
3150 ir_node *val = get_irn_n(node, 1);
3151 ir_node *mem = get_irn_n(node, 2);
3152 ir_entity *fent = get_ia32_frame_ent(node);
3153 ir_mode *lsmode = get_ia32_ls_mode(node);
3154 ir_node *new_val = transform_node(env, val);
3155 ir_node *noreg, *new_ptr, *new_mem;
3158 if (!USE_SSE2(cg)) {
3159 /* SSE unit is not used -> skip this node. */
3163 noreg = ia32_new_NoReg_gp(cg);
3164 new_val = transform_node(env, val);
3165 new_ptr = transform_node(env, ptr);
3166 new_mem = transform_node(env, mem);
3168 /* Store SSE -> MEM */
3169 if (is_ia32_xLoad(skip_Proj(new_val))) {
3170 ir_node *ld = skip_Proj(new_val);
3172 /* we can vfld the value directly into the fpu */
3173 fent = get_ia32_frame_ent(ld);
3174 ptr = get_irn_n(ld, 0);
3175 offs = get_ia32_am_offs_int(ld);
3177 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3178 set_ia32_frame_ent(res, fent);
3179 set_ia32_use_frame(res);
3180 set_ia32_ls_mode(res, lsmode);
3181 set_ia32_am_support(res, ia32_am_Dest);
3182 set_ia32_am_flavour(res, ia32_B);
3183 set_ia32_op_type(res, ia32_AddrModeD);
3187 /* Load MEM -> x87 */
3188 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
3189 set_ia32_frame_ent(res, fent);
3190 set_ia32_use_frame(res);
3191 set_ia32_ls_mode(res, lsmode);
3192 add_ia32_am_offs_int(res, offs);
3193 set_ia32_am_support(res, ia32_am_Source);
3194 set_ia32_am_flavour(res, ia32_B);
3195 set_ia32_op_type(res, ia32_AddrModeS);
3196 res = new_rd_Proj(dbgi, irg, block, res, lsmode, pn_ia32_vfld_res);
3201 /*********************************************************
3204 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3205 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3206 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3207 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3209 *********************************************************/
3212 * the BAD transformer.
3214 static ir_node *bad_transform(ia32_transform_env_t *env, ir_node *node) {
3215 panic("No transform function for %+F available.\n", node);
3219 static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) {
3220 /* end has to be duplicated manually because we need a dynamic in array */
3221 ir_graph *irg = env->irg;
3222 dbg_info *dbgi = get_irn_dbg_info(node);
3223 ir_node *block = transform_node(env, get_nodes_block(node));
3227 new_end = new_ir_node(dbgi, irg, block, op_End, mode_X, -1, NULL);
3228 copy_node_attr(node, new_end);
3229 duplicate_deps(env, node, new_end);
3231 set_irg_end(irg, new_end);
3232 set_new_node(new_end, new_end);
3234 /* transform preds */
3235 arity = get_irn_arity(node);
3236 for(i = 0; i < arity; ++i) {
3237 ir_node *in = get_irn_n(node, i);
3238 ir_node *new_in = transform_node(env, in);
3240 add_End_keepalive(new_end, new_in);
3246 static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) {
3247 ir_graph *irg = env->irg;
3248 dbg_info *dbgi = get_irn_dbg_info(node);
3249 ir_node *start_block = env->old_anchors[anchor_start_block];
3254 * We replace the ProjX from the start node with a jump,
3255 * so the startblock has no preds anymore now
3257 if(node == start_block) {
3258 return new_rd_Block(dbgi, irg, 0, NULL);
3261 /* we use the old blocks for now, because jumps allow cycles in the graph
3262 * we have to fix this later */
3263 block = new_ir_node(dbgi, irg, NULL, get_irn_op(node), get_irn_mode(node),
3264 get_irn_arity(node), get_irn_in(node) + 1);
3265 copy_node_attr(node, block);
3267 #ifdef DEBUG_libfirm
3268 block->node_nr = node->node_nr;
3270 set_new_node(node, block);
3272 /* put the preds in the worklist */
3273 arity = get_irn_arity(node);
3274 for(i = 0; i < arity; ++i) {
3275 ir_node *in = get_irn_n(node, i);
3276 pdeq_putr(env->worklist, in);
3282 static ir_node *gen_Proj_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
3283 ir_graph *irg = env->irg;
3284 ir_node *block = transform_node(env, get_nodes_block(node));
3285 dbg_info *dbgi = get_irn_dbg_info(node);
3286 ir_node *pred = get_Proj_pred(node);
3287 ir_node *new_pred = transform_node(env, pred);
3288 long proj = get_Proj_proj(node);
3290 if(proj == pn_be_AddSP_res) {
3291 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3292 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3294 } else if(proj == pn_be_AddSP_M) {
3295 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3299 return new_rd_Unknown(irg, get_irn_mode(node));
3302 static ir_node *gen_Proj_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
3303 ir_graph *irg = env->irg;
3304 ir_node *block = transform_node(env, get_nodes_block(node));
3305 dbg_info *dbgi = get_irn_dbg_info(node);
3306 ir_node *pred = get_Proj_pred(node);
3307 ir_node *new_pred = transform_node(env, pred);
3308 long proj = get_Proj_proj(node);
3310 if(proj == pn_be_SubSP_res) {
3311 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3312 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3314 } else if(proj == pn_be_SubSP_M) {
3315 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3319 return new_rd_Unknown(irg, get_irn_mode(node));
3322 static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) {
3323 ir_graph *irg = env->irg;
3324 ir_node *block = transform_node(env, get_nodes_block(node));
3325 dbg_info *dbgi = get_irn_dbg_info(node);
3326 ir_node *pred = get_Proj_pred(node);
3327 ir_node *new_pred = transform_node(env, pred);
3328 long proj = get_Proj_proj(node);
3330 /* renumber the proj */
3331 if(is_ia32_Load(new_pred)) {
3332 if(proj == pn_Load_res) {
3333 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3334 } else if(proj == pn_Load_M) {
3335 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3337 } else if(is_ia32_xLoad(new_pred)) {
3338 if(proj == pn_Load_res) {
3339 return new_rd_Proj(dbgi, irg, block, new_pred, mode_E, pn_ia32_xLoad_res);
3340 } else if(proj == pn_Load_M) {
3341 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3343 } else if(is_ia32_vfld(new_pred)) {
3344 if(proj == pn_Load_res) {
3345 return new_rd_Proj(dbgi, irg, block, new_pred, mode_E, pn_ia32_vfld_res);
3346 } else if(proj == pn_Load_M) {
3347 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3352 return new_rd_Unknown(irg, get_irn_mode(node));
3355 static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) {
3356 ir_graph *irg = env->irg;
3357 dbg_info *dbgi = get_irn_dbg_info(node);
3358 ir_node *block = transform_node(env, get_nodes_block(node));
3359 ir_mode *mode = get_irn_mode(node);
3361 ir_node *pred = get_Proj_pred(node);
3362 ir_node *new_pred = transform_node(env, pred);
3363 long proj = get_Proj_proj(node);
3365 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3367 switch(get_irn_opcode(pred)) {
3371 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3373 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3381 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3383 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3391 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3392 case pn_DivMod_res_div:
3393 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3394 case pn_DivMod_res_mod:
3395 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3405 return new_rd_Unknown(irg, mode);
3408 static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node)
3410 ir_graph *irg = env->irg;
3411 dbg_info *dbgi = get_irn_dbg_info(node);
3412 ir_node *block = transform_node(env, get_nodes_block(node));
3413 ir_mode *mode = get_irn_mode(node);
3415 ir_node *pred = get_Proj_pred(node);
3416 ir_node *new_pred = transform_node(env, pred);
3417 long proj = get_Proj_proj(node);
3420 case pn_CopyB_M_regular:
3421 if(is_ia32_CopyB_i(new_pred)) {
3422 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3424 } else if(is_ia32_CopyB(new_pred)) {
3425 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3434 return new_rd_Unknown(irg, mode);
3437 static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node)
3439 ir_graph *irg = env->irg;
3440 dbg_info *dbgi = get_irn_dbg_info(node);
3441 ir_node *block = transform_node(env, get_nodes_block(node));
3442 ir_mode *mode = get_irn_mode(node);
3444 ir_node *pred = get_Proj_pred(node);
3445 ir_node *new_pred = transform_node(env, pred);
3446 long proj = get_Proj_proj(node);
3449 case pn_ia32_l_vfdiv_M:
3450 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3451 case pn_ia32_l_vfdiv_res:
3452 return new_rd_Proj(dbgi, irg, block, new_pred, mode_E, pn_ia32_vfdiv_res);
3457 return new_rd_Unknown(irg, mode);
3460 static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node)
3462 ir_graph *irg = env->irg;
3463 dbg_info *dbgi = get_irn_dbg_info(node);
3464 ir_node *block = transform_node(env, get_nodes_block(node));
3465 ir_mode *mode = get_irn_mode(node);
3467 ir_node *pred = get_Proj_pred(node);
3468 ir_node *new_pred = transform_node(env, pred);
3469 long proj = get_Proj_proj(node);
3473 if(is_ia32_xDiv(new_pred)) {
3474 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3476 } else if(is_ia32_vfdiv(new_pred)) {
3477 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3482 if(is_ia32_xDiv(new_pred)) {
3483 return new_rd_Proj(dbgi, irg, block, new_pred, mode_E,
3485 } else if(is_ia32_vfdiv(new_pred)) {
3486 return new_rd_Proj(dbgi, irg, block, new_pred, mode_E,
3495 return new_rd_Unknown(irg, mode);
3498 static ir_node *gen_Proj_tls(ia32_transform_env_t *env, ir_node *node) {
3499 ir_graph *irg = env->irg;
3500 //dbg_info *dbgi = get_irn_dbg_info(node);
3501 dbg_info *dbgi = NULL;
3502 ir_node *block = transform_node(env, get_nodes_block(node));
3504 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3509 static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) {
3510 ir_graph *irg = env->irg;
3511 dbg_info *dbgi = get_irn_dbg_info(node);
3512 long proj = get_Proj_proj(node);
3513 ir_mode *mode = get_irn_mode(node);
3514 ir_node *block = transform_node(env, get_nodes_block(node));
3516 ir_node *call = get_Proj_pred(node);
3517 ir_node *new_call = transform_node(env, call);
3518 const arch_register_class_t *cls;
3520 /* The following is kinda tricky: If we're using SSE, then we have to
3521 * move the result value of the call in floating point registers to an
3522 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3523 * after the call, we have to make sure to correctly make the
3524 * MemProj and the result Proj use these 2 nodes
3526 if(proj == pn_be_Call_M_regular) {
3527 // get new node for result, are we doing the sse load/store hack?
3528 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3529 ir_node *call_res_new;
3530 ir_node *call_res_pred = NULL;
3532 if(call_res != NULL) {
3533 call_res_new = transform_node(env, call_res);
3534 call_res_pred = get_Proj_pred(call_res_new);
3537 if(call_res_pred == NULL || be_is_Call(call_res_pred)) {
3538 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3540 assert(is_ia32_xLoad(call_res_pred));
3541 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3544 if(proj == pn_be_Call_first_res && mode_is_float(mode)
3545 && USE_SSE2(env->cg)) {
3547 ir_node *frame = get_irg_frame(irg);
3548 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3550 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3552 const arch_register_class_t *cls;
3554 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3555 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3557 /* store st(0) onto stack */
3558 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3560 set_ia32_ls_mode(fstp, mode);
3561 set_ia32_op_type(fstp, ia32_AddrModeD);
3562 set_ia32_use_frame(fstp);
3563 set_ia32_am_flavour(fstp, ia32_am_B);
3564 set_ia32_am_support(fstp, ia32_am_Dest);
3566 /* load into SSE register */
3567 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3568 set_ia32_ls_mode(sse_load, mode);
3569 set_ia32_op_type(sse_load, ia32_AddrModeS);
3570 set_ia32_use_frame(sse_load);
3571 set_ia32_am_flavour(sse_load, ia32_am_B);
3572 set_ia32_am_support(sse_load, ia32_am_Source);
3574 //mproj = new_rd_Proj(dbgi, irg, block, sse_load, mode_M, pn_ia32_xLoad_M);
3575 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_E, pn_ia32_xLoad_res);
3577 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3579 /* get a Proj representing a caller save register */
3580 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3581 assert(is_Proj(p) && "Proj expected.");
3583 /* user of the the proj is the Keep */
3584 p = get_edge_src_irn(get_irn_out_edge_first(p));
3585 assert(be_is_Keep(p) && "Keep expected.");
3587 /* keep the result */
3588 cls = arch_get_irn_reg_class(env->cg->arch_env, sse_load, -1);
3589 keepin[0] = sse_load;
3590 be_new_Keep(cls, irg, block, 1, keepin);
3595 /* transform call modes to the mode_Iu or mode_E */
3596 if(mode != mode_M) {
3597 cls = arch_get_irn_reg_class(env->cg->arch_env, node, -1);
3601 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3604 static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) {
3605 ir_graph *irg = env->irg;
3606 dbg_info *dbgi = get_irn_dbg_info(node);
3607 ir_node *pred = get_Proj_pred(node);
3608 long proj = get_Proj_proj(node);
3610 if(is_Store(pred) || be_is_FrameStore(pred)) {
3611 if(proj == pn_Store_M) {
3612 return transform_node(env, pred);
3615 return new_r_Bad(irg);
3617 } else if(is_Load(pred) || be_is_FrameLoad(pred)) {
3618 return gen_Proj_Load(env, node);
3619 } else if(is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3620 return gen_Proj_DivMod(env, node);
3621 } else if(is_CopyB(pred)) {
3622 return gen_Proj_CopyB(env, node);
3623 } else if(is_Quot(pred)) {
3624 return gen_Proj_Quot(env, node);
3625 } else if(is_ia32_l_vfdiv(pred)) {
3626 return gen_Proj_l_vfdiv(env, node);
3627 } else if(be_is_SubSP(pred)) {
3628 return gen_Proj_be_SubSP(env, node);
3629 } else if(be_is_AddSP(pred)) {
3630 return gen_Proj_be_AddSP(env, node);
3631 } else if(be_is_Call(pred)) {
3632 return gen_Proj_be_Call(env, node);
3633 } else if(get_irn_op(pred) == op_Start) {
3634 if(proj == pn_Start_X_initial_exec) {
3635 ir_node *block = get_nodes_block(pred);
3638 block = transform_node(env, block);
3639 // we exchange the ProjX with a jump
3640 jump = new_rd_Jmp(dbgi, irg, block);
3641 ir_fprintf(stderr, "created jump: %+F\n", jump);
3644 if(node == env->old_anchors[anchor_tls]) {
3645 return gen_Proj_tls(env, node);
3649 return duplicate_node(env, node);
3653 * Enters all transform functions into the generic pointer
3655 static void register_transformers(void) {
3656 ir_op *op_Max, *op_Min, *op_Mulh;
3658 /* first clear the generic function pointer for all ops */
3659 clear_irp_opcodes_generic_func();
3661 #define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3662 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
3701 /* transform ops from intrinsic lowering */
3721 /* GEN(ia32_l_vfist); TODO */
3723 GEN(ia32_l_X87toSSE);
3724 GEN(ia32_l_SSEtoX87);
3729 /* we should never see these nodes */
3744 /* handle generic backend nodes */
3754 /* set the register for all Unknown nodes */
3757 op_Max = get_op_Max();
3760 op_Min = get_op_Min();
3763 op_Mulh = get_op_Mulh();
3771 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
3775 int deps = get_irn_deps(old_node);
3777 for(i = 0; i < deps; ++i) {
3778 ir_node *dep = get_irn_dep(old_node, i);
3779 ir_node *new_dep = transform_node(env, dep);
3781 add_irn_dep(new_node, new_dep);
3785 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node)
3787 ir_graph *irg = env->irg;
3788 dbg_info *dbgi = get_irn_dbg_info(node);
3789 ir_mode *mode = get_irn_mode(node);
3790 ir_op *op = get_irn_op(node);
3795 block = transform_node(env, get_nodes_block(node));
3797 arity = get_irn_arity(node);
3798 if(op->opar == oparity_dynamic) {
3799 new_node = new_ir_node(dbgi, irg, block, op, mode, -1, NULL);
3800 for(i = 0; i < arity; ++i) {
3801 ir_node *in = get_irn_n(node, i);
3802 in = transform_node(env, in);
3803 add_irn_n(new_node, in);
3806 ir_node **ins = alloca(arity * sizeof(ins[0]));
3807 for(i = 0; i < arity; ++i) {
3808 ir_node *in = get_irn_n(node, i);
3809 ins[i] = transform_node(env, in);
3812 new_node = new_ir_node(dbgi, irg, block, op, mode, arity, ins);
3815 copy_node_attr(node, new_node);
3816 duplicate_deps(env, node, new_node);
3821 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node)
3824 ir_op *op = get_irn_op(node);
3826 if(irn_visited(node)) {
3827 assert(get_new_node(node) != NULL);
3828 return get_new_node(node);
3831 mark_irn_visited(node);
3832 DEBUG_ONLY(set_new_node(node, NULL));
3834 if (op->ops.generic) {
3835 transform_func *transform = (transform_func *)op->ops.generic;
3837 new_node = (*transform)(env, node);
3838 assert(new_node != NULL);
3840 new_node = duplicate_node(env, node);
3842 //ir_fprintf(stderr, "%+F -> %+F\n", node, new_node);
3844 set_new_node(node, new_node);
3845 mark_irn_visited(new_node);
3846 hook_dead_node_elim_subst(current_ir_graph, node, new_node);
3850 static void fix_loops(ia32_transform_env_t *env, ir_node *node)
3854 if(irn_visited(node))
3856 mark_irn_visited(node);
3858 assert(node_is_in_irgs_storage(env->irg, node));
3860 if(!is_Block(node)) {
3861 ir_node *block = get_nodes_block(node);
3862 ir_node *new_block = (ir_node*) get_irn_link(block);
3864 if(new_block != NULL) {
3865 set_nodes_block(node, new_block);
3869 fix_loops(env, block);
3872 arity = get_irn_arity(node);
3873 for(i = 0; i < arity; ++i) {
3874 ir_node *in = get_irn_n(node, i);
3875 ir_node *new = (ir_node*) get_irn_link(in);
3877 if(new != NULL && new != in) {
3878 set_irn_n(node, i, new);
3885 arity = get_irn_deps(node);
3886 for(i = 0; i < arity; ++i) {
3887 ir_node *in = get_irn_dep(node, i);
3888 ir_node *new = (ir_node*) get_irn_link(in);
3890 if(new != NULL && new != in) {
3891 set_irn_dep(node, i, new);
3899 static void pre_transform_node(ir_node **place, ia32_transform_env_t *env)
3904 *place = transform_node(env, *place);
3907 static void transform_nodes(ia32_code_gen_t *cg)
3910 ir_graph *irg = cg->irg;
3912 ia32_transform_env_t env;
3914 hook_dead_node_elim(irg, 1);
3916 inc_irg_visited(irg);
3920 env.visited = get_irg_visited(irg);
3921 env.worklist = new_pdeq();
3922 env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
3924 old_end = get_irg_end(irg);
3926 /* put all anchor nodes in the worklist */
3927 for(i = 0; i < anchor_max; ++i) {
3928 ir_node *anchor = irg->anchors[i];
3931 pdeq_putr(env.worklist, anchor);
3934 env.old_anchors[i] = anchor;
3935 // and set it to NULL to make sure we don't accidently use it
3936 irg->anchors[i] = NULL;
3939 // pre transform some anchors (so they are available in the other transform
3941 set_irg_bad(irg, transform_node(&env, env.old_anchors[anchor_bad]));
3942 set_irg_no_mem(irg, transform_node(&env, env.old_anchors[anchor_no_mem]));
3943 set_irg_start_block(irg, transform_node(&env, env.old_anchors[anchor_start_block]));
3944 set_irg_start(irg, transform_node(&env, env.old_anchors[anchor_start]));
3945 set_irg_frame(irg, transform_node(&env, env.old_anchors[anchor_frame]));
3947 pre_transform_node(&cg->unknown_gp, &env);
3948 pre_transform_node(&cg->unknown_vfp, &env);
3949 pre_transform_node(&cg->unknown_xmm, &env);
3950 pre_transform_node(&cg->noreg_gp, &env);
3951 pre_transform_node(&cg->noreg_vfp, &env);
3952 pre_transform_node(&cg->noreg_xmm, &env);
3954 /* process worklist (this should transform all nodes in the graph) */
3955 while(!pdeq_empty(env.worklist)) {
3956 ir_node *node = pdeq_getl(env.worklist);
3957 transform_node(&env, node);
3960 /* fix loops and set new anchors*/
3961 inc_irg_visited(irg);
3962 for(i = 0; i < anchor_max; ++i) {
3963 ir_node *anchor = env.old_anchors[i];
3967 anchor = get_irn_link(anchor);
3968 fix_loops(&env, anchor);
3969 assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
3970 irg->anchors[i] = anchor;
3973 del_pdeq(env.worklist);
3975 hook_dead_node_elim(irg, 0);
3978 void ia32_transform_graph(ia32_code_gen_t *cg)
3980 ir_graph *irg = cg->irg;
3981 be_irg_t *birg = cg->birg;
3982 ir_graph *old_current_ir_graph = current_ir_graph;
3983 int old_interprocedural_view = get_interprocedural_view();
3984 struct obstack *old_obst = NULL;
3985 struct obstack *new_obst = NULL;
3987 current_ir_graph = irg;
3988 set_interprocedural_view(0);
3989 register_transformers();
3991 /* most analysis info is wrong after transformation */
3992 free_callee_info(irg);
3994 irg->outs_state = outs_none;
3996 free_loop_information(irg);
3997 set_irg_doms_inconsistent(irg);
3998 be_invalidate_liveness(birg);
3999 be_invalidate_dom_front(birg);
4001 /* create a new obstack */
4002 old_obst = irg->obst;
4003 new_obst = xmalloc(sizeof(*new_obst));
4004 obstack_init(new_obst);
4005 irg->obst = new_obst;
4006 irg->last_node_idx = 0;
4008 /* create new value table for CSE */
4009 del_identities(irg->value_table);
4010 irg->value_table = new_identities();
4012 /* do the main transformation */
4013 transform_nodes(cg);
4015 /* we don't want the globals anchor anymore */
4016 set_irg_globals(irg, new_r_Bad(irg));
4018 /* free the old obstack */
4019 obstack_free(old_obst, 0);
4023 current_ir_graph = old_current_ir_graph;
4024 set_interprocedural_view(old_interprocedural_view);
4026 /* recalculate edges */
4027 edges_deactivate(irg);
4028 edges_activate(irg);
4032 * Transforms a psi condition.
4034 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
4037 /* if the mode is target mode, we have already seen this part of the tree */
4038 if (get_irn_mode(cond) == mode)
4041 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
4043 set_irn_mode(cond, mode);
4045 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
4046 ir_node *in = get_irn_n(cond, i);
4048 /* if in is a compare: transform into Set/xCmp */
4050 ir_node *new_op = NULL;
4051 ir_node *cmp = get_Proj_pred(in);
4052 ir_node *cmp_a = get_Cmp_left(cmp);
4053 ir_node *cmp_b = get_Cmp_right(cmp);
4054 dbg_info *dbgi = get_irn_dbg_info(cmp);
4055 ir_graph *irg = get_irn_irg(cmp);
4056 ir_node *block = get_nodes_block(cmp);
4057 ir_node *noreg = ia32_new_NoReg_gp(cg);
4058 ir_node *nomem = new_rd_NoMem(irg);
4059 int pnc = get_Proj_proj(in);
4061 /* this is a compare */
4062 if (mode_is_float(mode)) {
4063 /* Psi is float, we need a floating point compare */
4066 ir_mode *m = get_irn_mode(cmp_a);
4068 if (! mode_is_float(m)) {
4069 cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_a, cmp_a, mode);
4070 cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_b, cmp_b, mode);
4072 else if (m == mode_F) {
4073 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
4074 cmp_a = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_a, cmp_a);
4075 cmp_b = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_b, cmp_b);
4078 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4079 set_ia32_pncode(new_op, pnc);
4080 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
4089 construct_binop_func *set_func = NULL;
4091 if (mode_is_float(get_irn_mode(cmp_a))) {
4092 /* 1st case: compare operands are floats */
4097 set_func = new_rd_ia32_xCmpSet;
4101 set_func = new_rd_ia32_vfCmpSet;
4104 pnc &= 7; /* fp compare -> int compare */
4107 /* 2nd case: compare operand are integer too */
4108 set_func = new_rd_ia32_CmpSet;
4111 new_op = set_func(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4112 if(!mode_is_signed(mode))
4113 pnc |= ia32_pn_Cmp_Unsigned;
4115 set_ia32_pncode(new_op, pnc);
4116 set_ia32_am_support(new_op, ia32_am_Source);
4119 /* the the new compare as in */
4120 set_irn_n(cond, i, new_op);
4123 /* another complex condition */
4124 transform_psi_cond(in, mode, cg);
4130 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
4131 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
4132 * compare, which causes the compare result to be stores in a register. The
4133 * "And"s and "Or"s are transformed later, we just have to set their mode right.
4135 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
4136 ia32_code_gen_t *cg = env;
4137 ir_node *psi_sel, *new_cmp, *block;
4142 if (get_irn_opcode(node) != iro_Psi)
4145 psi_sel = get_Psi_cond(node, 0);
4147 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
4148 if (is_Proj(psi_sel))
4151 //mode = get_irn_mode(node);
4152 // TODO this is probably wrong...
4155 transform_psi_cond(psi_sel, mode, cg);
4157 irg = get_irn_irg(node);
4158 block = get_nodes_block(node);
4160 /* we need to compare the evaluated condition tree with 0 */
4161 mode = get_irn_mode(node);
4162 if (mode_is_float(mode)) {
4163 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
4164 /* BEWARE: new_r_Const_long works for floating point as well */
4165 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
4166 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
4169 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode_Iu, 0));
4170 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
4173 set_Psi_cond(node, 0, new_cmp);
4176 void ia32_init_transform(void)
4178 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");