2 * This file implements the IR transformation from firm into
16 #include "irgraph_t.h"
21 #include "iredges_t.h"
29 #include "../benode_t.h"
30 #include "../besched.h"
33 #include "bearch_ia32_t.h"
35 #include "ia32_nodes_attr.h"
36 #include "../arch/archop.h" /* we need this for Min and Max nodes */
37 #include "ia32_transform.h"
38 #include "ia32_new_nodes.h"
39 #include "ia32_map_regs.h"
40 #include "ia32_dbg_stat.h"
42 #include "gen_ia32_regalloc_if.h"
44 #define SFP_SIGN "0x80000000"
45 #define DFP_SIGN "0x8000000000000000"
46 #define SFP_ABS "0x7FFFFFFF"
47 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
49 #define TP_SFP_SIGN "ia32_sfp_sign"
50 #define TP_DFP_SIGN "ia32_dfp_sign"
51 #define TP_SFP_ABS "ia32_sfp_abs"
52 #define TP_DFP_ABS "ia32_dfp_abs"
54 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
55 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
56 #define ENT_SFP_ABS "IA32_SFP_ABS"
57 #define ENT_DFP_ABS "IA32_DFP_ABS"
59 extern ir_op *get_op_Mulh(void);
61 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
62 ir_node *op1, ir_node *op2, ir_node *mem);
64 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
65 ir_node *op, ir_node *mem);
68 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
71 /****************************************************************************************************
73 * | | | | / _| | | (_)
74 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
75 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
76 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
77 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
79 ****************************************************************************************************/
82 * Returns 1 if irn is a Const representing 0, 0 otherwise
84 static INLINE int is_ia32_Const_0(ir_node *irn) {
85 return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
89 * Returns 1 if irn is a Const representing 1, 0 otherwise
91 static INLINE int is_ia32_Const_1(ir_node *irn) {
92 return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
96 * Returns the Proj representing the UNKNOWN register for given mode.
98 static ir_node *be_get_unknown_for_mode(ia32_code_gen_t *cg, ir_mode *mode) {
99 be_abi_irg_t *babi = cg->birg->abi;
100 const arch_register_t *unknwn_reg = NULL;
102 if (mode_is_float(mode)) {
103 unknwn_reg = USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_UKNWN] : &ia32_vfp_regs[REG_VFP_UKNWN];
106 unknwn_reg = &ia32_gp_regs[REG_GP_UKNWN];
109 return be_abi_get_callee_save_irn(babi, unknwn_reg);
113 * Gets the Proj with number pn from irn.
115 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
116 const ir_edge_t *edge;
118 assert(get_irn_mode(irn) == mode_T && "need mode_T");
120 foreach_out_edge(irn, edge) {
121 proj = get_edge_src_irn(edge);
123 if (get_Proj_proj(proj) == pn)
130 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
131 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
132 static const struct {
134 const char *ent_name;
135 const char *cnst_str;
136 } names [ia32_known_const_max] = {
137 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
138 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
139 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
140 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
142 static struct entity *ent_cache[ia32_known_const_max];
144 const char *tp_name, *ent_name, *cnst_str;
151 ent_name = names[kct].ent_name;
152 if (! ent_cache[kct]) {
153 tp_name = names[kct].tp_name;
154 cnst_str = names[kct].cnst_str;
156 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
157 tp = new_type_primitive(new_id_from_str(tp_name), mode);
158 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
160 set_entity_ld_ident(ent, get_entity_ident(ent));
161 set_entity_visibility(ent, visibility_local);
162 set_entity_variability(ent, variability_constant);
163 set_entity_allocation(ent, allocation_static);
165 /* we create a new entity here: It's initialization must resist on the
167 rem = current_ir_graph;
168 current_ir_graph = get_const_code_irg();
169 cnst = new_Const(mode, tv);
170 current_ir_graph = rem;
172 set_atomic_ent_value(ent, cnst);
174 /* cache the entry */
175 ent_cache[kct] = ent;
178 return get_entity_ident(ent_cache[kct]);
183 * Prints the old node name on cg obst and returns a pointer to it.
185 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
186 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
188 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
189 obstack_1grow(isa->name_obst, 0);
190 isa->name_obst_size += obstack_object_size(isa->name_obst);
191 return obstack_finish(isa->name_obst);
195 /* determine if one operator is an Imm */
196 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
198 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
199 else return is_ia32_Cnst(op2) ? op2 : NULL;
202 /* determine if one operator is not an Imm */
203 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
204 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
209 * Construct a standard binary operation, set AM and immediate if required.
211 * @param env The transformation environment
212 * @param op1 The first operand
213 * @param op2 The second operand
214 * @param func The node constructor function
215 * @return The constructed ia32 node.
217 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
218 ir_node *new_op = NULL;
219 ir_mode *mode = env->mode;
220 dbg_info *dbg = env->dbg;
221 ir_graph *irg = env->irg;
222 ir_node *block = env->block;
223 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
224 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
225 ir_node *nomem = new_NoMem();
226 ir_node *expr_op, *imm_op;
227 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
229 /* Check if immediate optimization is on and */
230 /* if it's an operation with immediate. */
231 if (! (env->cg->opt & IA32_OPT_IMMOPS)) {
235 else if (is_op_commutative(get_irn_op(env->irn))) {
236 imm_op = get_immediate_op(op1, op2);
237 expr_op = get_expr_op(op1, op2);
240 imm_op = get_immediate_op(NULL, op2);
241 expr_op = get_expr_op(op1, op2);
244 assert((expr_op || imm_op) && "invalid operands");
247 /* We have two consts here: not yet supported */
251 if (mode_is_float(mode)) {
252 /* floating point operations */
254 DB((mod, LEVEL_1, "FP with immediate ..."));
255 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
256 set_ia32_Immop_attr(new_op, imm_op);
257 set_ia32_am_support(new_op, ia32_am_None);
260 DB((mod, LEVEL_1, "FP binop ..."));
261 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
262 set_ia32_am_support(new_op, ia32_am_Source);
264 set_ia32_ls_mode(new_op, mode);
267 /* integer operations */
269 /* This is expr + const */
270 DB((mod, LEVEL_1, "INT with immediate ..."));
271 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
272 set_ia32_Immop_attr(new_op, imm_op);
275 set_ia32_am_support(new_op, ia32_am_Dest);
278 DB((mod, LEVEL_1, "INT binop ..."));
279 /* This is a normal operation */
280 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
283 set_ia32_am_support(new_op, ia32_am_Full);
287 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
289 set_ia32_res_mode(new_op, mode);
291 if (is_op_commutative(get_irn_op(env->irn))) {
292 set_ia32_commutative(new_op);
295 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
301 * Construct a shift/rotate binary operation, sets AM and immediate if required.
303 * @param env The transformation environment
304 * @param op1 The first operand
305 * @param op2 The second operand
306 * @param func The node constructor function
307 * @return The constructed ia32 node.
309 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
310 ir_node *new_op = NULL;
311 ir_mode *mode = env->mode;
312 dbg_info *dbg = env->dbg;
313 ir_graph *irg = env->irg;
314 ir_node *block = env->block;
315 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
316 ir_node *nomem = new_NoMem();
317 ir_node *expr_op, *imm_op;
319 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
321 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
323 /* Check if immediate optimization is on and */
324 /* if it's an operation with immediate. */
325 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
326 expr_op = get_expr_op(op1, op2);
328 assert((expr_op || imm_op) && "invalid operands");
331 /* We have two consts here: not yet supported */
335 /* Limit imm_op within range imm8 */
337 tv = get_ia32_Immop_tarval(imm_op);
340 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
347 /* integer operations */
349 /* This is shift/rot with const */
350 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
352 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
353 set_ia32_Immop_attr(new_op, imm_op);
356 /* This is a normal shift/rot */
357 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
358 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
362 set_ia32_am_support(new_op, ia32_am_Dest);
364 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
366 set_ia32_res_mode(new_op, mode);
367 set_ia32_emit_cl(new_op);
369 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
374 * Construct a standard unary operation, set AM and immediate if required.
376 * @param env The transformation environment
377 * @param op The operand
378 * @param func The node constructor function
379 * @return The constructed ia32 node.
381 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
382 ir_node *new_op = NULL;
383 ir_mode *mode = env->mode;
384 dbg_info *dbg = env->dbg;
385 ir_graph *irg = env->irg;
386 ir_node *block = env->block;
387 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
388 ir_node *nomem = new_NoMem();
389 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
391 new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
393 if (mode_is_float(mode)) {
394 DB((mod, LEVEL_1, "FP unop ..."));
395 /* floating point operations don't support implicit store */
396 set_ia32_am_support(new_op, ia32_am_None);
399 DB((mod, LEVEL_1, "INT unop ..."));
400 set_ia32_am_support(new_op, ia32_am_Dest);
403 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
405 set_ia32_res_mode(new_op, mode);
407 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
413 * Creates an ia32 Add with immediate.
415 * @param env The transformation environment
416 * @param expr_op The expression operator
417 * @param const_op The constant
418 * @return the created ia32 Add node
420 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
421 ir_node *new_op = NULL;
422 tarval *tv = get_ia32_Immop_tarval(const_op);
423 dbg_info *dbg = env->dbg;
424 ir_graph *irg = env->irg;
425 ir_node *block = env->block;
426 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
427 ir_node *nomem = new_NoMem();
429 tarval_classification_t class_tv, class_negtv;
430 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
432 /* try to optimize to inc/dec */
433 if ((env->cg->opt & IA32_OPT_INCDEC) && (get_ia32_op_type(const_op) == ia32_Const)) {
434 /* optimize tarvals */
435 class_tv = classify_tarval(tv);
436 class_negtv = classify_tarval(tarval_neg(tv));
438 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
439 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
440 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
443 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
444 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
445 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
451 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
452 set_ia32_Immop_attr(new_op, const_op);
453 set_ia32_commutative(new_op);
460 * Creates an ia32 Add.
462 * @param env The transformation environment
463 * @return the created ia32 Add node
465 static ir_node *gen_Add(ia32_transform_env_t *env) {
466 ir_node *new_op = NULL;
467 dbg_info *dbg = env->dbg;
468 ir_mode *mode = env->mode;
469 ir_graph *irg = env->irg;
470 ir_node *block = env->block;
471 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
472 ir_node *nomem = new_NoMem();
473 ir_node *expr_op, *imm_op;
474 ir_node *op1 = get_Add_left(env->irn);
475 ir_node *op2 = get_Add_right(env->irn);
477 /* Check if immediate optimization is on and */
478 /* if it's an operation with immediate. */
479 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
480 expr_op = get_expr_op(op1, op2);
482 assert((expr_op || imm_op) && "invalid operands");
484 if (mode_is_float(mode)) {
486 if (USE_SSE2(env->cg))
487 return gen_binop(env, op1, op2, new_rd_ia32_xAdd);
489 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
494 /* No expr_op means, that we have two const - one symconst and */
495 /* one tarval or another symconst - because this case is not */
496 /* covered by constant folding */
497 /* We need to check for: */
498 /* 1) symconst + const -> becomes a LEA */
499 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
500 /* linker doesn't support two symconsts */
502 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
503 /* this is the 2nd case */
504 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
505 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
506 set_ia32_am_flavour(new_op, ia32_am_OB);
508 DBG_OPT_LEA1(op2, new_op);
511 /* this is the 1st case */
512 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
514 DBG_OPT_LEA2(op1, op2, new_op);
516 if (get_ia32_op_type(op1) == ia32_SymConst) {
517 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
518 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
521 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
522 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
524 set_ia32_am_flavour(new_op, ia32_am_O);
528 set_ia32_am_support(new_op, ia32_am_Source);
529 set_ia32_op_type(new_op, ia32_AddrModeS);
531 /* Lea doesn't need a Proj */
535 /* This is expr + const */
536 new_op = gen_imm_Add(env, expr_op, imm_op);
539 set_ia32_am_support(new_op, ia32_am_Dest);
542 /* This is a normal add */
543 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
546 set_ia32_am_support(new_op, ia32_am_Full);
547 set_ia32_commutative(new_op);
551 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
553 set_ia32_res_mode(new_op, mode);
555 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
561 * Creates an ia32 Mul.
563 * @param env The transformation environment
564 * @return the created ia32 Mul node
566 static ir_node *gen_Mul(ia32_transform_env_t *env) {
567 ir_node *op1 = get_Mul_left(env->irn);
568 ir_node *op2 = get_Mul_right(env->irn);
571 if (mode_is_float(env->mode)) {
573 if (USE_SSE2(env->cg))
574 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMul);
576 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
579 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
588 * Creates an ia32 Mulh.
589 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
590 * this result while Mul returns the lower 32 bit.
592 * @param env The transformation environment
593 * @return the created ia32 Mulh node
595 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
596 ir_node *op1 = get_irn_n(env->irn, 0);
597 ir_node *op2 = get_irn_n(env->irn, 1);
598 ir_node *proj_EAX, *proj_EDX, *mulh;
601 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
602 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
603 mulh = get_Proj_pred(proj_EAX);
604 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
606 /* to be on the save side */
607 set_Proj_proj(proj_EAX, pn_EAX);
609 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
610 /* Mulh with const cannot have AM */
611 set_ia32_am_support(mulh, ia32_am_None);
614 /* Mulh cannot have AM for destination */
615 set_ia32_am_support(mulh, ia32_am_Source);
621 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
629 * Creates an ia32 And.
631 * @param env The transformation environment
632 * @return The created ia32 And node
634 static ir_node *gen_And(ia32_transform_env_t *env) {
635 ir_node *op1 = get_And_left(env->irn);
636 ir_node *op2 = get_And_right(env->irn);
638 assert (! mode_is_float(env->mode));
639 return gen_binop(env, op1, op2, new_rd_ia32_And);
645 * Creates an ia32 Or.
647 * @param env The transformation environment
648 * @return The created ia32 Or node
650 static ir_node *gen_Or(ia32_transform_env_t *env) {
651 ir_node *op1 = get_Or_left(env->irn);
652 ir_node *op2 = get_Or_right(env->irn);
654 assert (! mode_is_float(env->mode));
655 return gen_binop(env, op1, op2, new_rd_ia32_Or);
661 * Creates an ia32 Eor.
663 * @param env The transformation environment
664 * @return The created ia32 Eor node
666 static ir_node *gen_Eor(ia32_transform_env_t *env) {
667 ir_node *op1 = get_Eor_left(env->irn);
668 ir_node *op2 = get_Eor_right(env->irn);
670 assert(! mode_is_float(env->mode));
671 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
677 * Creates an ia32 Max.
679 * @param env The transformation environment
680 * @return the created ia32 Max node
682 static ir_node *gen_Max(ia32_transform_env_t *env) {
683 ir_node *op1 = get_irn_n(env->irn, 0);
684 ir_node *op2 = get_irn_n(env->irn, 1);
687 if (mode_is_float(env->mode)) {
689 if (USE_SSE2(env->cg))
690 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMax);
696 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
697 set_ia32_am_support(new_op, ia32_am_None);
698 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
707 * Creates an ia32 Min.
709 * @param env The transformation environment
710 * @return the created ia32 Min node
712 static ir_node *gen_Min(ia32_transform_env_t *env) {
713 ir_node *op1 = get_irn_n(env->irn, 0);
714 ir_node *op2 = get_irn_n(env->irn, 1);
717 if (mode_is_float(env->mode)) {
719 if (USE_SSE2(env->cg))
720 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMin);
726 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
727 set_ia32_am_support(new_op, ia32_am_None);
728 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
737 * Creates an ia32 Sub with immediate.
739 * @param env The transformation environment
740 * @param expr_op The first operator
741 * @param const_op The constant operator
742 * @return The created ia32 Sub node
744 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
745 ir_node *new_op = NULL;
746 tarval *tv = get_ia32_Immop_tarval(const_op);
747 dbg_info *dbg = env->dbg;
748 ir_graph *irg = env->irg;
749 ir_node *block = env->block;
750 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
751 ir_node *nomem = new_NoMem();
753 tarval_classification_t class_tv, class_negtv;
754 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
756 /* try to optimize to inc/dec */
757 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
758 /* optimize tarvals */
759 class_tv = classify_tarval(tv);
760 class_negtv = classify_tarval(tarval_neg(tv));
762 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
763 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
764 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
767 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
768 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
769 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
775 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
776 set_ia32_Immop_attr(new_op, const_op);
783 * Creates an ia32 Sub.
785 * @param env The transformation environment
786 * @return The created ia32 Sub node
788 static ir_node *gen_Sub(ia32_transform_env_t *env) {
789 ir_node *new_op = NULL;
790 dbg_info *dbg = env->dbg;
791 ir_mode *mode = env->mode;
792 ir_graph *irg = env->irg;
793 ir_node *block = env->block;
794 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
795 ir_node *nomem = new_NoMem();
796 ir_node *op1 = get_Sub_left(env->irn);
797 ir_node *op2 = get_Sub_right(env->irn);
798 ir_node *expr_op, *imm_op;
800 /* Check if immediate optimization is on and */
801 /* if it's an operation with immediate. */
802 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
803 expr_op = get_expr_op(op1, op2);
805 assert((expr_op || imm_op) && "invalid operands");
807 if (mode_is_float(mode)) {
809 if (USE_SSE2(env->cg))
810 return gen_binop(env, op1, op2, new_rd_ia32_xSub);
812 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
817 /* No expr_op means, that we have two const - one symconst and */
818 /* one tarval or another symconst - because this case is not */
819 /* covered by constant folding */
820 /* We need to check for: */
821 /* 1) symconst + const -> becomes a LEA */
822 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
823 /* linker doesn't support two symconsts */
825 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
826 /* this is the 2nd case */
827 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
828 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
829 set_ia32_am_sc_sign(new_op);
830 set_ia32_am_flavour(new_op, ia32_am_OB);
832 DBG_OPT_LEA1(op2, new_op);
835 /* this is the 1st case */
836 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
838 DBG_OPT_LEA2(op1, op2, new_op);
840 if (get_ia32_op_type(op1) == ia32_SymConst) {
841 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
842 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
845 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
846 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
847 set_ia32_am_sc_sign(new_op);
849 set_ia32_am_flavour(new_op, ia32_am_O);
853 set_ia32_am_support(new_op, ia32_am_Source);
854 set_ia32_op_type(new_op, ia32_AddrModeS);
856 /* Lea doesn't need a Proj */
860 /* This is expr - const */
861 new_op = gen_imm_Sub(env, expr_op, imm_op);
864 set_ia32_am_support(new_op, ia32_am_Dest);
867 /* This is a normal sub */
868 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
871 set_ia32_am_support(new_op, ia32_am_Full);
875 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
877 set_ia32_res_mode(new_op, mode);
879 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
885 * Generates an ia32 DivMod with additional infrastructure for the
886 * register allocator if needed.
888 * @param env The transformation environment
889 * @param dividend -no comment- :)
890 * @param divisor -no comment- :)
891 * @param dm_flav flavour_Div/Mod/DivMod
892 * @return The created ia32 DivMod node
894 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
896 ir_node *edx_node, *cltd;
898 dbg_info *dbg = env->dbg;
899 ir_graph *irg = env->irg;
900 ir_node *block = env->block;
901 ir_mode *mode = env->mode;
902 ir_node *irn = env->irn;
907 mem = get_Div_mem(irn);
908 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
911 mem = get_Mod_mem(irn);
912 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
915 mem = get_DivMod_mem(irn);
916 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
922 if (mode_is_signed(mode)) {
923 /* in signed mode, we need to sign extend the dividend */
924 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
925 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
926 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
929 edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
930 set_ia32_Const_type(edx_node, ia32_Const);
931 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
934 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
936 set_ia32_n_res(res, 2);
938 /* Only one proj is used -> We must add a second proj and */
939 /* connect this one to a Keep node to eat up the second */
940 /* destroyed register. */
941 if (get_irn_n_edges(irn) == 1) {
942 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
943 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
945 if (get_irn_op(irn) == op_Div) {
946 set_Proj_proj(proj, pn_DivMod_res_div);
947 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
950 set_Proj_proj(proj, pn_DivMod_res_mod);
951 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
954 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
957 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
959 set_ia32_res_mode(res, mode_Is);
966 * Wrapper for generate_DivMod. Sets flavour_Mod.
968 * @param env The transformation environment
970 static ir_node *gen_Mod(ia32_transform_env_t *env) {
971 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
975 * Wrapper for generate_DivMod. Sets flavour_Div.
977 * @param env The transformation environment
979 static ir_node *gen_Div(ia32_transform_env_t *env) {
980 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
984 * Wrapper for generate_DivMod. Sets flavour_DivMod.
986 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
987 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
993 * Creates an ia32 floating Div.
995 * @param env The transformation environment
996 * @return The created ia32 xDiv node
998 static ir_node *gen_Quot(ia32_transform_env_t *env) {
999 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1001 ir_node *nomem = new_rd_NoMem(env->irg);
1002 ir_node *op1 = get_Quot_left(env->irn);
1003 ir_node *op2 = get_Quot_right(env->irn);
1006 if (USE_SSE2(env->cg)) {
1007 if (is_ia32_xConst(op2)) {
1008 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
1009 set_ia32_am_support(new_op, ia32_am_None);
1010 set_ia32_Immop_attr(new_op, op2);
1013 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1014 set_ia32_am_support(new_op, ia32_am_Source);
1018 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1019 set_ia32_am_support(new_op, ia32_am_Source);
1021 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
1022 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1030 * Creates an ia32 Shl.
1032 * @param env The transformation environment
1033 * @return The created ia32 Shl node
1035 static ir_node *gen_Shl(ia32_transform_env_t *env) {
1036 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
1042 * Creates an ia32 Shr.
1044 * @param env The transformation environment
1045 * @return The created ia32 Shr node
1047 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1048 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1054 * Creates an ia32 Shrs.
1056 * @param env The transformation environment
1057 * @return The created ia32 Shrs node
1059 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1060 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1066 * Creates an ia32 RotL.
1068 * @param env The transformation environment
1069 * @param op1 The first operator
1070 * @param op2 The second operator
1071 * @return The created ia32 RotL node
1073 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1074 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1080 * Creates an ia32 RotR.
1081 * NOTE: There is no RotR with immediate because this would always be a RotL
1082 * "imm-mode_size_bits" which can be pre-calculated.
1084 * @param env The transformation environment
1085 * @param op1 The first operator
1086 * @param op2 The second operator
1087 * @return The created ia32 RotR node
1089 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1090 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1096 * Creates an ia32 RotR or RotL (depending on the found pattern).
1098 * @param env The transformation environment
1099 * @return The created ia32 RotL or RotR node
1101 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1102 ir_node *rotate = NULL;
1103 ir_node *op1 = get_Rot_left(env->irn);
1104 ir_node *op2 = get_Rot_right(env->irn);
1106 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1107 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1108 that means we can create a RotR instead of an Add and a RotL */
1111 ir_node *pred = get_Proj_pred(op2);
1113 if (is_ia32_Add(pred)) {
1114 ir_node *pred_pred = get_irn_n(pred, 2);
1115 tarval *tv = get_ia32_Immop_tarval(pred);
1116 long bits = get_mode_size_bits(env->mode);
1118 if (is_Proj(pred_pred)) {
1119 pred_pred = get_Proj_pred(pred_pred);
1122 if (is_ia32_Minus(pred_pred) &&
1123 tarval_is_long(tv) &&
1124 get_tarval_long(tv) == bits)
1126 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1127 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1134 rotate = gen_RotL(env, op1, op2);
1143 * Transforms a Minus node.
1145 * @param env The transformation environment
1146 * @param op The Minus operand
1147 * @return The created ia32 Minus node
1149 static ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1154 if (mode_is_float(env->mode)) {
1156 if (USE_SSE2(env->cg)) {
1157 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1158 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1159 ir_node *nomem = new_rd_NoMem(env->irg);
1161 new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1163 size = get_mode_size_bits(env->mode);
1164 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1166 set_ia32_sc(new_op, name);
1168 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1170 set_ia32_res_mode(new_op, env->mode);
1171 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1173 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
1176 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1177 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1181 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1188 * Transforms a Minus node.
1190 * @param env The transformation environment
1191 * @return The created ia32 Minus node
1193 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1194 return gen_Minus_ex(env, get_Minus_op(env->irn));
1199 * Transforms a Not node.
1201 * @param env The transformation environment
1202 * @return The created ia32 Not node
1204 static ir_node *gen_Not(ia32_transform_env_t *env) {
1205 assert (! mode_is_float(env->mode));
1206 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1212 * Transforms an Abs node.
1214 * @param env The transformation environment
1215 * @return The created ia32 Abs node
1217 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1218 ir_node *res, *p_eax, *p_edx;
1219 dbg_info *dbg = env->dbg;
1220 ir_mode *mode = env->mode;
1221 ir_graph *irg = env->irg;
1222 ir_node *block = env->block;
1223 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1224 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1225 ir_node *nomem = new_NoMem();
1226 ir_node *op = get_Abs_op(env->irn);
1230 if (mode_is_float(mode)) {
1232 if (USE_SSE2(env->cg)) {
1233 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1235 size = get_mode_size_bits(mode);
1236 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1238 set_ia32_sc(res, name);
1240 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1242 set_ia32_res_mode(res, mode);
1243 set_ia32_immop_type(res, ia32_ImmSymConst);
1245 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
1248 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1249 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1253 res = new_rd_ia32_Cdq(dbg, irg, block, op);
1254 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1255 set_ia32_res_mode(res, mode);
1257 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
1258 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
1260 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1261 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1262 set_ia32_res_mode(res, mode);
1264 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
1266 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1267 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1268 set_ia32_res_mode(res, mode);
1270 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
1279 * Transforms a Load.
1281 * @param env The transformation environment
1282 * @return the created ia32 Load node
1284 static ir_node *gen_Load(ia32_transform_env_t *env) {
1285 ir_node *node = env->irn;
1286 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1287 ir_node *ptr = get_Load_ptr(node);
1288 ir_node *lptr = ptr;
1289 ir_mode *mode = get_Load_mode(node);
1292 ia32_am_flavour_t am_flav = ia32_B;
1294 /* address might be a constant (symconst or absolute address) */
1295 if (is_ia32_Const(ptr)) {
1300 if (mode_is_float(mode)) {
1302 if (USE_SSE2(env->cg))
1303 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1305 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1308 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1311 /* base is an constant address */
1313 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1314 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1317 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1323 set_ia32_am_support(new_op, ia32_am_Source);
1324 set_ia32_op_type(new_op, ia32_AddrModeS);
1325 set_ia32_am_flavour(new_op, am_flav);
1326 set_ia32_ls_mode(new_op, mode);
1328 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1336 * Transforms a Store.
1338 * @param env The transformation environment
1339 * @return the created ia32 Store node
1341 static ir_node *gen_Store(ia32_transform_env_t *env) {
1342 ir_node *node = env->irn;
1343 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1344 ir_node *val = get_Store_value(node);
1345 ir_node *ptr = get_Store_ptr(node);
1346 ir_node *sptr = ptr;
1347 ir_node *mem = get_Store_mem(node);
1348 ir_mode *mode = get_irn_mode(val);
1349 ir_node *sval = val;
1352 ia32_am_flavour_t am_flav = ia32_B;
1353 ia32_immop_type_t immop = ia32_ImmNone;
1355 if (! mode_is_float(mode)) {
1356 /* in case of storing a const (but not a symconst) -> make it an attribute */
1357 if (is_ia32_Cnst(val)) {
1358 switch (get_ia32_op_type(val)) {
1360 immop = ia32_ImmConst;
1363 immop = ia32_ImmSymConst;
1366 assert(0 && "unsupported Const type");
1372 /* address might be a constant (symconst or absolute address) */
1373 if (is_ia32_Const(ptr)) {
1378 if (mode_is_float(mode)) {
1380 if (USE_SSE2(env->cg))
1381 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1383 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1385 else if (get_mode_size_bits(mode) == 8) {
1386 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1389 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1392 /* stored const is an attribute (saves a register) */
1393 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1394 set_ia32_Immop_attr(new_op, val);
1397 /* base is an constant address */
1399 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1400 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1403 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1409 set_ia32_am_support(new_op, ia32_am_Dest);
1410 set_ia32_op_type(new_op, ia32_AddrModeD);
1411 set_ia32_am_flavour(new_op, am_flav);
1412 set_ia32_ls_mode(new_op, get_irn_mode(val));
1413 set_ia32_immop_type(new_op, immop);
1415 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1423 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1425 * @param env The transformation environment
1426 * @return The transformed node.
1428 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1429 dbg_info *dbg = env->dbg;
1430 ir_graph *irg = env->irg;
1431 ir_node *block = env->block;
1432 ir_node *node = env->irn;
1433 ir_node *sel = get_Cond_selector(node);
1434 ir_mode *sel_mode = get_irn_mode(sel);
1435 ir_node *res = NULL;
1436 ir_node *pred = NULL;
1437 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1438 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1440 if (is_Proj(sel) && sel_mode == mode_b) {
1441 ir_node *nomem = new_NoMem();
1443 pred = get_Proj_pred(sel);
1445 /* get both compare operators */
1446 cmp_a = get_Cmp_left(pred);
1447 cmp_b = get_Cmp_right(pred);
1449 /* check if we can use a CondJmp with immediate */
1450 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1451 expr = get_expr_op(cmp_a, cmp_b);
1454 pn_Cmp pnc = get_Proj_proj(sel);
1456 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1457 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1458 /* a Cmp A =/!= 0 */
1459 ir_node *op1 = expr;
1460 ir_node *op2 = expr;
1461 ir_node *and = skip_Proj(expr);
1462 const char *cnst = NULL;
1464 /* check, if expr is an only once used And operation */
1465 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1466 op1 = get_irn_n(and, 2);
1467 op2 = get_irn_n(and, 3);
1469 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1471 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1472 set_ia32_pncode(res, get_Proj_proj(sel));
1473 set_ia32_res_mode(res, get_irn_mode(op1));
1476 copy_ia32_Immop_attr(res, and);
1479 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1484 if (mode_is_float(get_irn_mode(expr))) {
1486 if (USE_SSE2(env->cg))
1487 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1493 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1495 set_ia32_Immop_attr(res, cnst);
1496 set_ia32_res_mode(res, get_irn_mode(expr));
1499 if (mode_is_float(get_irn_mode(cmp_a))) {
1501 if (USE_SSE2(env->cg))
1502 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1505 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1506 proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
1507 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1511 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1512 set_ia32_commutative(res);
1514 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1517 set_ia32_pncode(res, get_Proj_proj(sel));
1518 //set_ia32_am_support(res, ia32_am_Source);
1521 /* determine the smallest switch case value */
1522 int switch_min = INT_MAX;
1523 const ir_edge_t *edge;
1526 foreach_out_edge(node, edge) {
1527 int pn = get_Proj_proj(get_edge_src_irn(edge));
1528 switch_min = pn < switch_min ? pn : switch_min;
1532 /* if smallest switch case is not 0 we need an additional sub */
1533 snprintf(buf, sizeof(buf), "%d", switch_min);
1534 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1535 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1536 sub_ia32_am_offs(res, buf);
1537 set_ia32_am_flavour(res, ia32_am_OB);
1538 set_ia32_am_support(res, ia32_am_Source);
1539 set_ia32_op_type(res, ia32_AddrModeS);
1542 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1543 set_ia32_pncode(res, get_Cond_defaultProj(node));
1544 set_ia32_res_mode(res, get_irn_mode(sel));
1547 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1554 * Transforms a CopyB node.
1556 * @param env The transformation environment
1557 * @return The transformed node.
1559 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1560 ir_node *res = NULL;
1561 dbg_info *dbg = env->dbg;
1562 ir_graph *irg = env->irg;
1563 ir_mode *mode = env->mode;
1564 ir_node *block = env->block;
1565 ir_node *node = env->irn;
1566 ir_node *src = get_CopyB_src(node);
1567 ir_node *dst = get_CopyB_dst(node);
1568 ir_node *mem = get_CopyB_mem(node);
1569 int size = get_type_size_bytes(get_CopyB_type(node));
1572 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1573 /* then we need the size explicitly in ECX. */
1574 if (size >= 16 * 4) {
1575 rem = size & 0x3; /* size % 4 */
1578 res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
1579 set_ia32_op_type(res, ia32_Const);
1580 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1582 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1583 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1586 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1587 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1588 set_ia32_immop_type(res, ia32_ImmConst);
1591 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1599 * Transforms a Mux node into CMov.
1601 * @param env The transformation environment
1602 * @return The transformed node.
1604 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1606 ir_node *node = env->irn;
1607 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1608 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1610 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1619 * Transforms a Psi node into CMov.
1621 * @param env The transformation environment
1622 * @return The transformed node.
1624 static ir_node *gen_Psi(ia32_transform_env_t *env) {
1625 ir_node *node = env->irn;
1626 ir_node *cmp_proj = get_Mux_sel(node);
1627 ir_node *cmp, *cmp_a, *cmp_b, *new_op = NULL;
1629 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
1631 if (mode_is_float(env->mode)) {
1632 /* floating point psi */
1634 if (USE_SSE2(env->cg)) {
1635 /* unfortunately there is no conditional move for SSE */
1641 ir_node *psi_true = get_Psi_val(node, 0);
1642 ir_node *psi_default = get_Psi_default(node);
1645 cmp = get_Proj_pred(cmp_proj);
1646 cmp_a = get_Cmp_left(cmp);
1647 cmp_b = get_Cmp_right(cmp);
1649 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1650 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1651 new_op = new_rd_ia32_Set(env->dbg, env->irg, env->block, cmp_a, cmp_b, env->mode);
1652 set_ia32_pncode(new_op, get_Proj_proj(cmp_proj));
1654 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1655 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1656 /* we invert condition and set default to 0 */
1657 new_op = new_rd_ia32_Set(env->dbg, env->irg, env->block, cmp_a, cmp_b, env->mode);
1658 set_ia32_pncode(new_op, get_inversed_pnc(get_Proj_proj(cmp_proj)));
1661 /* otherwise: use CMOVcc */
1662 new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, cmp_a, cmp_b, psi_true, psi_default, env->mode);
1663 set_ia32_pncode(new_op, get_Proj_proj(cmp_proj));
1666 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1674 * Following conversion rules apply:
1678 * 1) n bit -> m bit n > m (downscale)
1679 * a) target is signed: movsx
1680 * b) target is unsigned: and with lower bits sets
1681 * 2) n bit -> m bit n == m (sign change)
1683 * 3) n bit -> m bit n < m (upscale)
1684 * a) source is signed: movsx
1685 * b) source is unsigned: and with lower bits sets
1689 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1693 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1694 * if target mode < 32bit: additional INT -> INT conversion (see above)
1698 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1699 * x87 is mode_E internally, conversions happen only at load and store
1700 * in non-strict semantic
1704 * Create a conversion from x87 state register to general purpose.
1706 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1707 ia32_code_gen_t *cg = env->cg;
1708 entity *ent = cg->fp_to_gp;
1709 ir_graph *irg = env->irg;
1710 ir_node *block = env->block;
1711 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1712 ir_node *op = get_Conv_op(env->irn);
1713 ir_node *fist, *mem, *load;
1716 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1717 ent = cg->fp_to_gp =
1718 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1722 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
1724 set_ia32_frame_ent(fist, ent);
1725 set_ia32_use_frame(fist);
1726 set_ia32_am_support(fist, ia32_am_Dest);
1727 set_ia32_op_type(fist, ia32_AddrModeD);
1728 set_ia32_am_flavour(fist, ia32_B);
1729 set_ia32_ls_mode(fist, mode_E);
1731 mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
1734 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1736 set_ia32_frame_ent(load, ent);
1737 set_ia32_use_frame(load);
1738 set_ia32_am_support(load, ia32_am_Source);
1739 set_ia32_op_type(load, ia32_AddrModeS);
1740 set_ia32_am_flavour(load, ia32_B);
1741 set_ia32_ls_mode(load, tgt_mode);
1743 return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
1747 * Create a conversion from x87 state register to general purpose.
1749 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1750 ia32_code_gen_t *cg = env->cg;
1751 entity *ent = cg->gp_to_fp;
1752 ir_graph *irg = env->irg;
1753 ir_node *block = env->block;
1754 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1755 ir_node *nomem = get_irg_no_mem(irg);
1756 ir_node *op = get_Conv_op(env->irn);
1757 ir_node *fild, *store, *mem;
1761 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
1762 ent = cg->gp_to_fp =
1763 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
1766 /* first convert to 32 bit */
1767 src_bits = get_mode_size_bits(src_mode);
1768 if (src_bits == 8) {
1769 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
1770 op = new_r_Proj(irg, block, op, mode_Is, 0);
1772 else if (src_bits < 32) {
1773 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
1774 op = new_r_Proj(irg, block, op, mode_Is, 0);
1778 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
1780 set_ia32_frame_ent(store, ent);
1781 set_ia32_use_frame(store);
1783 set_ia32_am_support(store, ia32_am_Dest);
1784 set_ia32_op_type(store, ia32_AddrModeD);
1785 set_ia32_am_flavour(store, ia32_B);
1786 set_ia32_ls_mode(store, mode_Is);
1788 mem = new_r_Proj(irg, block, store, mode_M, 0);
1791 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1793 set_ia32_frame_ent(fild, ent);
1794 set_ia32_use_frame(fild);
1795 set_ia32_am_support(fild, ia32_am_Source);
1796 set_ia32_op_type(fild, ia32_AddrModeS);
1797 set_ia32_am_flavour(fild, ia32_B);
1798 set_ia32_ls_mode(fild, mode_E);
1800 return new_r_Proj(irg, block, fild, mode_E, 0);
1804 * Transforms a Conv node.
1806 * @param env The transformation environment
1807 * @return The created ia32 Conv node
1809 static ir_node *gen_Conv(ia32_transform_env_t *env) {
1810 dbg_info *dbg = env->dbg;
1811 ir_graph *irg = env->irg;
1812 ir_node *op = get_Conv_op(env->irn);
1813 ir_mode *src_mode = get_irn_mode(op);
1814 ir_mode *tgt_mode = env->mode;
1815 int src_bits = get_mode_size_bits(src_mode);
1816 int tgt_bits = get_mode_size_bits(tgt_mode);
1817 ir_node *block = env->block;
1818 ir_node *new_op = NULL;
1819 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1820 ir_node *nomem = new_rd_NoMem(irg);
1822 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1824 if (src_mode == tgt_mode) {
1825 /* this can happen when changing mode_P to mode_Is */
1826 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1827 edges_reroute(env->irn, op, irg);
1829 else if (mode_is_float(src_mode)) {
1830 /* we convert from float ... */
1831 if (mode_is_float(tgt_mode)) {
1833 if (USE_SSE2(env->cg)) {
1834 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1835 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
1838 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
1839 edges_reroute(env->irn, op, irg);
1844 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1845 if (USE_SSE2(env->cg))
1846 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
1848 return gen_x87_fp_to_gp(env, tgt_mode);
1850 /* if target mode is not int: add an additional downscale convert */
1851 if (tgt_bits < 32) {
1852 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1853 set_ia32_am_support(new_op, ia32_am_Source);
1854 set_ia32_tgt_mode(new_op, tgt_mode);
1855 set_ia32_src_mode(new_op, src_mode);
1857 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
1859 if (tgt_bits == 8 || src_bits == 8) {
1860 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
1863 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
1869 /* we convert from int ... */
1870 if (mode_is_float(tgt_mode)) {
1873 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1874 if (USE_SSE2(env->cg))
1875 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
1877 return gen_x87_gp_to_fp(env, src_mode);
1881 if (get_mode_size_bits(src_mode) == tgt_bits) {
1882 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
1883 edges_reroute(env->irn, op, irg);
1886 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
1887 if (tgt_bits == 8 || src_bits == 8) {
1888 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
1891 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
1898 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1899 set_ia32_tgt_mode(new_op, tgt_mode);
1900 set_ia32_src_mode(new_op, src_mode);
1902 set_ia32_am_support(new_op, ia32_am_Source);
1904 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
1912 /********************************************
1915 * | |__ ___ _ __ ___ __| | ___ ___
1916 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1917 * | |_) | __/ | | | (_) | (_| | __/\__ \
1918 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1920 ********************************************/
1922 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
1923 ir_node *new_op = NULL;
1924 ir_node *node = env->irn;
1925 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1926 ir_node *mem = new_rd_NoMem(env->irg);
1927 ir_node *ptr = get_irn_n(node, 0);
1928 entity *ent = be_get_frame_entity(node);
1929 ir_mode *mode = env->mode;
1931 // /* If the StackParam has only one user -> */
1932 // /* put it in the Block where the user resides */
1933 // if (get_irn_n_edges(node) == 1) {
1934 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
1937 if (mode_is_float(mode)) {
1939 if (USE_SSE2(env->cg))
1940 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
1942 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
1945 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
1948 set_ia32_frame_ent(new_op, ent);
1949 set_ia32_use_frame(new_op);
1951 set_ia32_am_support(new_op, ia32_am_Source);
1952 set_ia32_op_type(new_op, ia32_AddrModeS);
1953 set_ia32_am_flavour(new_op, ia32_B);
1954 set_ia32_ls_mode(new_op, mode);
1956 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1958 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
1962 * Transforms a FrameAddr into an ia32 Add.
1964 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
1965 ir_node *new_op = NULL;
1966 ir_node *node = env->irn;
1967 ir_node *op = get_irn_n(node, 0);
1968 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1969 ir_node *nomem = new_rd_NoMem(env->irg);
1971 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
1972 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1973 set_ia32_am_support(new_op, ia32_am_Full);
1974 set_ia32_use_frame(new_op);
1975 set_ia32_immop_type(new_op, ia32_ImmConst);
1976 set_ia32_commutative(new_op);
1978 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1980 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
1984 * Transforms a FrameLoad into an ia32 Load.
1986 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
1987 ir_node *new_op = NULL;
1988 ir_node *node = env->irn;
1989 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1990 ir_node *mem = get_irn_n(node, 0);
1991 ir_node *ptr = get_irn_n(node, 1);
1992 entity *ent = be_get_frame_entity(node);
1993 ir_mode *mode = get_type_mode(get_entity_type(ent));
1995 if (mode_is_float(mode)) {
1997 if (USE_SSE2(env->cg))
1998 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2000 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2003 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2005 set_ia32_frame_ent(new_op, ent);
2006 set_ia32_use_frame(new_op);
2008 set_ia32_am_support(new_op, ia32_am_Source);
2009 set_ia32_op_type(new_op, ia32_AddrModeS);
2010 set_ia32_am_flavour(new_op, ia32_B);
2011 set_ia32_ls_mode(new_op, mode);
2013 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2020 * Transforms a FrameStore into an ia32 Store.
2022 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
2023 ir_node *new_op = NULL;
2024 ir_node *node = env->irn;
2025 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2026 ir_node *mem = get_irn_n(node, 0);
2027 ir_node *ptr = get_irn_n(node, 1);
2028 ir_node *val = get_irn_n(node, 2);
2029 entity *ent = be_get_frame_entity(node);
2030 ir_mode *mode = get_irn_mode(val);
2032 if (mode_is_float(mode)) {
2034 if (USE_SSE2(env->cg))
2035 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2037 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2039 else if (get_mode_size_bits(mode) == 8) {
2040 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2043 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2046 set_ia32_frame_ent(new_op, ent);
2047 set_ia32_use_frame(new_op);
2049 set_ia32_am_support(new_op, ia32_am_Dest);
2050 set_ia32_op_type(new_op, ia32_AddrModeD);
2051 set_ia32_am_flavour(new_op, ia32_B);
2052 set_ia32_ls_mode(new_op, mode);
2054 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2060 * This function just sets the register for the Unknown node
2061 * as this is not done during register allocation because Unknown
2062 * is an "ignore" node.
2064 static ir_node *gen_Unknown(ia32_transform_env_t *env) {
2065 ir_mode *mode = env->mode;
2066 ir_node *irn = env->irn;
2068 if (mode_is_float(mode)) {
2069 if (USE_SSE2(env->cg))
2070 arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
2072 arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
2074 else if (mode_is_int(mode) || mode_is_reference(mode)) {
2075 arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
2078 assert(0 && "unsupported Unknown-Mode");
2085 /*********************************************************
2088 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
2089 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
2090 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
2091 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
2093 *********************************************************/
2096 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
2097 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2099 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
2100 ia32_transform_env_t tenv;
2101 ir_node *in1, *in2, *noreg, *nomem, *res;
2102 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
2104 /* Return if AM node or not a Sub or xSub */
2105 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_xSub(irn)))
2108 noreg = ia32_new_NoReg_gp(cg);
2109 nomem = new_rd_NoMem(cg->irg);
2110 in1 = get_irn_n(irn, 2);
2111 in2 = get_irn_n(irn, 3);
2112 in1_reg = arch_get_irn_register(cg->arch_env, in1);
2113 in2_reg = arch_get_irn_register(cg->arch_env, in2);
2114 out_reg = get_ia32_out_reg(irn, 0);
2116 tenv.block = get_nodes_block(irn);
2117 tenv.dbg = get_irn_dbg_info(irn);
2120 tenv.mode = get_ia32_res_mode(irn);
2122 DEBUG_ONLY(tenv.mod = cg->mod;)
2124 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
2125 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
2126 /* generate the neg src2 */
2127 res = gen_Minus_ex(&tenv, in2);
2128 arch_set_irn_register(cg->arch_env, res, in2_reg);
2130 /* add to schedule */
2131 sched_add_before(irn, res);
2133 /* generate the add */
2134 if (mode_is_float(tenv.mode)) {
2135 res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2136 set_ia32_am_support(res, ia32_am_Source);
2139 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2140 set_ia32_am_support(res, ia32_am_Full);
2141 set_ia32_commutative(res);
2143 set_ia32_res_mode(res, tenv.mode);
2145 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
2147 slots = get_ia32_slots(res);
2150 /* add to schedule */
2151 sched_add_before(irn, res);
2153 /* remove the old sub */
2156 DBG_OPT_SUB2NEGADD(irn, res);
2158 /* exchange the add and the sub */
2164 * Transforms a LEA into an Add if possible
2165 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2167 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
2168 ia32_am_flavour_t am_flav;
2170 ir_node *res = NULL;
2171 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
2173 ia32_transform_env_t tenv;
2174 const arch_register_t *out_reg, *base_reg, *index_reg;
2177 if (! is_ia32_Lea(irn))
2180 am_flav = get_ia32_am_flavour(irn);
2182 /* only some LEAs can be transformed to an Add */
2183 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
2186 noreg = ia32_new_NoReg_gp(cg);
2187 nomem = new_rd_NoMem(cg->irg);
2190 base = get_irn_n(irn, 0);
2191 index = get_irn_n(irn,1);
2193 offs = get_ia32_am_offs(irn);
2195 /* offset has a explicit sign -> we need to skip + */
2196 if (offs && offs[0] == '+')
2199 out_reg = arch_get_irn_register(cg->arch_env, irn);
2200 base_reg = arch_get_irn_register(cg->arch_env, base);
2201 index_reg = arch_get_irn_register(cg->arch_env, index);
2203 tenv.block = get_nodes_block(irn);
2204 tenv.dbg = get_irn_dbg_info(irn);
2207 DEBUG_ONLY(tenv.mod = cg->mod;)
2208 tenv.mode = get_irn_mode(irn);
2211 switch(get_ia32_am_flavour(irn)) {
2213 /* out register must be same as base register */
2214 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2220 /* out register must be same as base register */
2221 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2228 /* out register must be same as index register */
2229 if (! REGS_ARE_EQUAL(out_reg, index_reg))
2236 /* out register must be same as one in register */
2237 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
2241 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
2246 /* in registers a different from out -> no Add possible */
2253 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
2254 arch_set_irn_register(cg->arch_env, res, out_reg);
2255 set_ia32_op_type(res, ia32_Normal);
2256 set_ia32_commutative(res);
2257 set_ia32_res_mode(res, tenv.mode);
2260 set_ia32_cnst(res, offs);
2261 set_ia32_immop_type(res, ia32_ImmConst);
2264 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
2266 /* add Add to schedule */
2267 sched_add_before(irn, res);
2269 DBG_OPT_LEA2ADD(irn, res);
2271 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, 0);
2273 /* add result Proj to schedule */
2274 sched_add_before(irn, res);
2276 /* remove the old LEA */
2279 /* exchange the Add and the LEA */
2284 * the BAD transformer.
2286 static ir_node *bad_transform(ia32_transform_env_t *env) {
2287 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2293 * Enters all transform functions into the generic pointer
2295 void ia32_register_transformers(void) {
2296 ir_op *op_Max, *op_Min, *op_Mulh;
2298 /* first clear the generic function pointer for all ops */
2299 clear_irp_opcodes_generic_func();
2301 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2302 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
2349 /* constant transformation happens earlier */
2373 /* set the register for all Unknown nodes */
2376 op_Max = get_op_Max();
2379 op_Min = get_op_Min();
2382 op_Mulh = get_op_Mulh();
2391 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
2394 * Transforms the given firm node (and maybe some other related nodes)
2395 * into one or more assembler nodes.
2397 * @param node the firm node
2398 * @param env the debug module
2400 void ia32_transform_node(ir_node *node, void *env) {
2401 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2402 ir_op *op = get_irn_op(node);
2403 ir_node *asm_node = NULL;
2409 /* link arguments pointing to Unknown to the UNKNOWN Proj */
2410 for (i = get_irn_arity(node) - 1; i >= 0; i--) {
2411 if (is_Unknown(get_irn_n(node, i)))
2412 set_irn_n(node, i, be_get_unknown_for_mode(cg, get_irn_mode(get_irn_n(node, i))));
2415 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
2416 if (op->ops.generic) {
2417 ia32_transform_env_t tenv;
2418 transform_func *transform = (transform_func *)op->ops.generic;
2420 tenv.block = get_nodes_block(node);
2421 tenv.dbg = get_irn_dbg_info(node);
2422 tenv.irg = current_ir_graph;
2424 tenv.mode = get_irn_mode(node);
2426 DEBUG_ONLY(tenv.mod = cg->mod;)
2428 asm_node = (*transform)(&tenv);
2431 /* exchange nodes if a new one was generated */
2433 exchange(node, asm_node);
2434 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2437 DB((cg->mod, LEVEL_1, "ignored\n"));