2 * This file implements the IR transformation from firm into
16 #include "irgraph_t.h"
21 #include "iredges_t.h"
29 #include "../benode_t.h"
30 #include "../besched.h"
32 #include "bearch_ia32_t.h"
34 #include "ia32_nodes_attr.h"
35 #include "../arch/archop.h" /* we need this for Min and Max nodes */
36 #include "ia32_transform.h"
37 #include "ia32_new_nodes.h"
38 #include "ia32_map_regs.h"
39 #include "ia32_dbg_stat.h"
41 #include "gen_ia32_regalloc_if.h"
43 #define SFP_SIGN "0x80000000"
44 #define DFP_SIGN "0x8000000000000000"
45 #define SFP_ABS "0x7FFFFFFF"
46 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
48 #define TP_SFP_SIGN "ia32_sfp_sign"
49 #define TP_DFP_SIGN "ia32_dfp_sign"
50 #define TP_SFP_ABS "ia32_sfp_abs"
51 #define TP_DFP_ABS "ia32_dfp_abs"
53 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
54 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
55 #define ENT_SFP_ABS "IA32_SFP_ABS"
56 #define ENT_DFP_ABS "IA32_DFP_ABS"
58 extern ir_op *get_op_Mulh(void);
60 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
61 ir_node *op1, ir_node *op2, ir_node *mem);
63 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
64 ir_node *op, ir_node *mem);
67 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
70 /****************************************************************************************************
72 * | | | | / _| | | (_)
73 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
74 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
75 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
76 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
78 ****************************************************************************************************/
81 * Gets the Proj with number pn from irn.
83 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
84 const ir_edge_t *edge;
86 assert(get_irn_mode(irn) == mode_T && "need mode_T");
88 foreach_out_edge(irn, edge) {
89 proj = get_edge_src_irn(edge);
91 if (get_Proj_proj(proj) == pn)
98 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
99 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
100 static const struct {
102 const char *ent_name;
103 const char *cnst_str;
104 } names [ia32_known_const_max] = {
105 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
106 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
107 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
108 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
110 static struct entity *ent_cache[ia32_known_const_max];
112 const char *tp_name, *ent_name, *cnst_str;
119 ent_name = names[kct].ent_name;
120 if (! ent_cache[kct]) {
121 tp_name = names[kct].tp_name;
122 cnst_str = names[kct].cnst_str;
124 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
125 tp = new_type_primitive(new_id_from_str(tp_name), mode);
126 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
128 set_entity_ld_ident(ent, get_entity_ident(ent));
129 set_entity_visibility(ent, visibility_local);
130 set_entity_variability(ent, variability_constant);
131 set_entity_allocation(ent, allocation_static);
133 /* we create a new entity here: It's initialization must resist on the
135 rem = current_ir_graph;
136 current_ir_graph = get_const_code_irg();
137 cnst = new_Const(mode, tv);
138 current_ir_graph = rem;
140 set_atomic_ent_value(ent, cnst);
142 /* cache the entry */
143 ent_cache[kct] = ent;
146 return get_entity_ident(ent_cache[kct]);
151 * Prints the old node name on cg obst and returns a pointer to it.
153 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
154 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
156 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
157 obstack_1grow(isa->name_obst, 0);
158 isa->name_obst_size += obstack_object_size(isa->name_obst);
159 return obstack_finish(isa->name_obst);
163 /* determine if one operator is an Imm */
164 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
166 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
167 else return is_ia32_Cnst(op2) ? op2 : NULL;
170 /* determine if one operator is not an Imm */
171 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
172 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
177 * Construct a standard binary operation, set AM and immediate if required.
179 * @param env The transformation environment
180 * @param op1 The first operand
181 * @param op2 The second operand
182 * @param func The node constructor function
183 * @return The constructed ia32 node.
185 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
186 ir_node *new_op = NULL;
187 ir_mode *mode = env->mode;
188 dbg_info *dbg = env->dbg;
189 ir_graph *irg = env->irg;
190 ir_node *block = env->block;
191 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
192 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
193 ir_node *nomem = new_NoMem();
194 ir_node *expr_op, *imm_op;
195 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
197 /* Check if immediate optimization is on and */
198 /* if it's an operation with immediate. */
199 if (! (env->cg->opt & IA32_OPT_IMMOPS)) {
203 else if (is_op_commutative(get_irn_op(env->irn))) {
204 imm_op = get_immediate_op(op1, op2);
205 expr_op = get_expr_op(op1, op2);
208 imm_op = get_immediate_op(NULL, op2);
209 expr_op = get_expr_op(op1, op2);
212 assert((expr_op || imm_op) && "invalid operands");
215 /* We have two consts here: not yet supported */
219 if (mode_is_float(mode)) {
220 /* floating point operations */
222 DB((mod, LEVEL_1, "FP with immediate ..."));
223 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
224 set_ia32_Immop_attr(new_op, imm_op);
225 set_ia32_am_support(new_op, ia32_am_None);
228 DB((mod, LEVEL_1, "FP binop ..."));
229 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
230 set_ia32_am_support(new_op, ia32_am_Source);
234 /* integer operations */
236 /* This is expr + const */
237 DB((mod, LEVEL_1, "INT with immediate ..."));
238 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
239 set_ia32_Immop_attr(new_op, imm_op);
242 set_ia32_am_support(new_op, ia32_am_Dest);
245 DB((mod, LEVEL_1, "INT binop ..."));
246 /* This is a normal operation */
247 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
250 set_ia32_am_support(new_op, ia32_am_Full);
254 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
256 set_ia32_res_mode(new_op, mode);
258 if (is_op_commutative(get_irn_op(env->irn))) {
259 set_ia32_commutative(new_op);
262 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
268 * Construct a shift/rotate binary operation, sets AM and immediate if required.
270 * @param env The transformation environment
271 * @param op1 The first operand
272 * @param op2 The second operand
273 * @param func The node constructor function
274 * @return The constructed ia32 node.
276 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
277 ir_node *new_op = NULL;
278 ir_mode *mode = env->mode;
279 dbg_info *dbg = env->dbg;
280 ir_graph *irg = env->irg;
281 ir_node *block = env->block;
282 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
283 ir_node *nomem = new_NoMem();
284 ir_node *expr_op, *imm_op;
286 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
288 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
290 /* Check if immediate optimization is on and */
291 /* if it's an operation with immediate. */
292 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
293 expr_op = get_expr_op(op1, op2);
295 assert((expr_op || imm_op) && "invalid operands");
298 /* We have two consts here: not yet supported */
302 /* Limit imm_op within range imm8 */
304 tv = get_ia32_Immop_tarval(imm_op);
307 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
314 /* integer operations */
316 /* This is shift/rot with const */
317 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
319 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
320 set_ia32_Immop_attr(new_op, imm_op);
323 /* This is a normal shift/rot */
324 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
325 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
329 set_ia32_am_support(new_op, ia32_am_Dest);
331 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
333 set_ia32_res_mode(new_op, mode);
334 set_ia32_emit_cl(new_op);
336 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
341 * Construct a standard unary operation, set AM and immediate if required.
343 * @param env The transformation environment
344 * @param op The operand
345 * @param func The node constructor function
346 * @return The constructed ia32 node.
348 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
349 ir_node *new_op = NULL;
350 ir_mode *mode = env->mode;
351 dbg_info *dbg = env->dbg;
352 ir_graph *irg = env->irg;
353 ir_node *block = env->block;
354 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
355 ir_node *nomem = new_NoMem();
356 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
358 new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
360 if (mode_is_float(mode)) {
361 DB((mod, LEVEL_1, "FP unop ..."));
362 /* floating point operations don't support implicit store */
363 set_ia32_am_support(new_op, ia32_am_None);
366 DB((mod, LEVEL_1, "INT unop ..."));
367 set_ia32_am_support(new_op, ia32_am_Dest);
370 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
372 set_ia32_res_mode(new_op, mode);
374 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
380 * Creates an ia32 Add with immediate.
382 * @param env The transformation environment
383 * @param expr_op The expression operator
384 * @param const_op The constant
385 * @return the created ia32 Add node
387 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
388 ir_node *new_op = NULL;
389 tarval *tv = get_ia32_Immop_tarval(const_op);
390 dbg_info *dbg = env->dbg;
391 ir_graph *irg = env->irg;
392 ir_node *block = env->block;
393 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
394 ir_node *nomem = new_NoMem();
396 tarval_classification_t class_tv, class_negtv;
397 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
399 /* try to optimize to inc/dec */
400 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
401 /* optimize tarvals */
402 class_tv = classify_tarval(tv);
403 class_negtv = classify_tarval(tarval_neg(tv));
405 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
406 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
407 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
410 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
411 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
412 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
418 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
419 set_ia32_Immop_attr(new_op, const_op);
426 * Creates an ia32 Add.
428 * @param env The transformation environment
429 * @return the created ia32 Add node
431 static ir_node *gen_Add(ia32_transform_env_t *env) {
432 ir_node *new_op = NULL;
433 dbg_info *dbg = env->dbg;
434 ir_mode *mode = env->mode;
435 ir_graph *irg = env->irg;
436 ir_node *block = env->block;
437 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
438 ir_node *nomem = new_NoMem();
439 ir_node *expr_op, *imm_op;
440 ir_node *op1 = get_Add_left(env->irn);
441 ir_node *op2 = get_Add_right(env->irn);
443 /* Check if immediate optimization is on and */
444 /* if it's an operation with immediate. */
445 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
446 expr_op = get_expr_op(op1, op2);
448 assert((expr_op || imm_op) && "invalid operands");
450 if (mode_is_float(mode)) {
452 if (USE_SSE2(env->cg))
453 return gen_binop(env, op1, op2, new_rd_ia32_xAdd);
455 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
460 /* No expr_op means, that we have two const - one symconst and */
461 /* one tarval or another symconst - because this case is not */
462 /* covered by constant folding */
463 /* We need to check for: */
464 /* 1) symconst + const -> becomes a LEA */
465 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
466 /* linker doesn't support two symconsts */
468 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
469 /* this is the 2nd case */
470 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
471 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
472 set_ia32_am_flavour(new_op, ia32_am_OB);
475 /* this is the 1st case */
476 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
478 if (get_ia32_op_type(op1) == ia32_SymConst) {
479 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
480 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
483 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
484 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
486 set_ia32_am_flavour(new_op, ia32_am_O);
490 set_ia32_am_support(new_op, ia32_am_Source);
491 set_ia32_op_type(new_op, ia32_AddrModeS);
493 /* Lea doesn't need a Proj */
497 /* This is expr + const */
498 new_op = gen_imm_Add(env, expr_op, imm_op);
501 set_ia32_am_support(new_op, ia32_am_Dest);
502 set_ia32_commutative(new_op);
505 /* This is a normal add */
506 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
509 set_ia32_am_support(new_op, ia32_am_Full);
510 set_ia32_commutative(new_op);
514 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
516 set_ia32_res_mode(new_op, mode);
518 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
524 * Creates an ia32 Mul.
526 * @param env The transformation environment
527 * @return the created ia32 Mul node
529 static ir_node *gen_Mul(ia32_transform_env_t *env) {
530 ir_node *op1 = get_Mul_left(env->irn);
531 ir_node *op2 = get_Mul_right(env->irn);
534 if (mode_is_float(env->mode)) {
536 if (USE_SSE2(env->cg))
537 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMul);
539 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
542 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
551 * Creates an ia32 Mulh.
552 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
553 * this result while Mul returns the lower 32 bit.
555 * @param env The transformation environment
556 * @return the created ia32 Mulh node
558 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
559 ir_node *op1 = get_irn_n(env->irn, 0);
560 ir_node *op2 = get_irn_n(env->irn, 1);
561 ir_node *proj_EAX, *proj_EDX, *mulh;
564 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
565 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
566 mulh = get_Proj_pred(proj_EAX);
567 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
569 /* to be on the save side */
570 set_Proj_proj(proj_EAX, pn_EAX);
572 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
573 /* Mulh with const cannot have AM */
574 set_ia32_am_support(mulh, ia32_am_None);
577 /* Mulh cannot have AM for destination */
578 set_ia32_am_support(mulh, ia32_am_Source);
584 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
592 * Creates an ia32 And.
594 * @param env The transformation environment
595 * @return The created ia32 And node
597 static ir_node *gen_And(ia32_transform_env_t *env) {
598 ir_node *op1 = get_And_left(env->irn);
599 ir_node *op2 = get_And_right(env->irn);
601 assert (! mode_is_float(env->mode));
602 return gen_binop(env, op1, op2, new_rd_ia32_And);
608 * Creates an ia32 Or.
610 * @param env The transformation environment
611 * @return The created ia32 Or node
613 static ir_node *gen_Or(ia32_transform_env_t *env) {
614 ir_node *op1 = get_Or_left(env->irn);
615 ir_node *op2 = get_Or_right(env->irn);
617 assert (! mode_is_float(env->mode));
618 return gen_binop(env, op1, op2, new_rd_ia32_Or);
624 * Creates an ia32 Eor.
626 * @param env The transformation environment
627 * @return The created ia32 Eor node
629 static ir_node *gen_Eor(ia32_transform_env_t *env) {
630 ir_node *op1 = get_Eor_left(env->irn);
631 ir_node *op2 = get_Eor_right(env->irn);
633 assert(! mode_is_float(env->mode));
634 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
640 * Creates an ia32 Max.
642 * @param env The transformation environment
643 * @return the created ia32 Max node
645 static ir_node *gen_Max(ia32_transform_env_t *env) {
646 ir_node *op1 = get_irn_n(env->irn, 0);
647 ir_node *op2 = get_irn_n(env->irn, 1);
650 if (mode_is_float(env->mode)) {
652 if (USE_SSE2(env->cg))
653 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMax);
659 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
660 set_ia32_am_support(new_op, ia32_am_None);
661 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
670 * Creates an ia32 Min.
672 * @param env The transformation environment
673 * @return the created ia32 Min node
675 static ir_node *gen_Min(ia32_transform_env_t *env) {
676 ir_node *op1 = get_irn_n(env->irn, 0);
677 ir_node *op2 = get_irn_n(env->irn, 1);
680 if (mode_is_float(env->mode)) {
682 if (USE_SSE2(env->cg))
683 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMin);
689 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
690 set_ia32_am_support(new_op, ia32_am_None);
691 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
700 * Creates an ia32 Sub with immediate.
702 * @param env The transformation environment
703 * @param expr_op The first operator
704 * @param const_op The constant operator
705 * @return The created ia32 Sub node
707 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
708 ir_node *new_op = NULL;
709 tarval *tv = get_ia32_Immop_tarval(const_op);
710 dbg_info *dbg = env->dbg;
711 ir_graph *irg = env->irg;
712 ir_node *block = env->block;
713 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
714 ir_node *nomem = new_NoMem();
716 tarval_classification_t class_tv, class_negtv;
717 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
719 /* try to optimize to inc/dec */
720 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
721 /* optimize tarvals */
722 class_tv = classify_tarval(tv);
723 class_negtv = classify_tarval(tarval_neg(tv));
725 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
726 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
727 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
730 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
731 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
732 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
738 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
739 set_ia32_Immop_attr(new_op, const_op);
746 * Creates an ia32 Sub.
748 * @param env The transformation environment
749 * @return The created ia32 Sub node
751 static ir_node *gen_Sub(ia32_transform_env_t *env) {
752 ir_node *new_op = NULL;
753 dbg_info *dbg = env->dbg;
754 ir_mode *mode = env->mode;
755 ir_graph *irg = env->irg;
756 ir_node *block = env->block;
757 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
758 ir_node *nomem = new_NoMem();
759 ir_node *op1 = get_Sub_left(env->irn);
760 ir_node *op2 = get_Sub_right(env->irn);
761 ir_node *expr_op, *imm_op;
763 /* Check if immediate optimization is on and */
764 /* if it's an operation with immediate. */
765 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
766 expr_op = get_expr_op(op1, op2);
768 assert((expr_op || imm_op) && "invalid operands");
770 if (mode_is_float(mode)) {
772 if (USE_SSE2(env->cg))
773 return gen_binop(env, op1, op2, new_rd_ia32_xSub);
775 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
780 /* No expr_op means, that we have two const - one symconst and */
781 /* one tarval or another symconst - because this case is not */
782 /* covered by constant folding */
783 /* We need to check for: */
784 /* 1) symconst + const -> becomes a LEA */
785 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
786 /* linker doesn't support two symconsts */
788 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
789 /* this is the 2nd case */
790 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
791 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
792 set_ia32_am_sc_sign(new_op);
793 set_ia32_am_flavour(new_op, ia32_am_OB);
796 /* this is the 1st case */
797 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
799 if (get_ia32_op_type(op1) == ia32_SymConst) {
800 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
801 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
804 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
805 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
806 set_ia32_am_sc_sign(new_op);
808 set_ia32_am_flavour(new_op, ia32_am_O);
812 set_ia32_am_support(new_op, ia32_am_Source);
813 set_ia32_op_type(new_op, ia32_AddrModeS);
815 /* Lea doesn't need a Proj */
819 /* This is expr - const */
820 new_op = gen_imm_Sub(env, expr_op, imm_op);
823 set_ia32_am_support(new_op, ia32_am_Dest);
826 /* This is a normal sub */
827 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
830 set_ia32_am_support(new_op, ia32_am_Full);
834 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
836 set_ia32_res_mode(new_op, mode);
838 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
844 * Generates an ia32 DivMod with additional infrastructure for the
845 * register allocator if needed.
847 * @param env The transformation environment
848 * @param dividend -no comment- :)
849 * @param divisor -no comment- :)
850 * @param dm_flav flavour_Div/Mod/DivMod
851 * @return The created ia32 DivMod node
853 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
855 ir_node *edx_node, *cltd;
857 dbg_info *dbg = env->dbg;
858 ir_graph *irg = env->irg;
859 ir_node *block = env->block;
860 ir_mode *mode = env->mode;
861 ir_node *irn = env->irn;
866 mem = get_Div_mem(irn);
867 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
870 mem = get_Mod_mem(irn);
871 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
874 mem = get_DivMod_mem(irn);
875 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
881 if (mode_is_signed(mode)) {
882 /* in signed mode, we need to sign extend the dividend */
883 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
884 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
885 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
888 edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
889 set_ia32_Const_type(edx_node, ia32_Const);
890 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
893 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
895 set_ia32_n_res(res, 2);
897 /* Only one proj is used -> We must add a second proj and */
898 /* connect this one to a Keep node to eat up the second */
899 /* destroyed register. */
900 if (get_irn_n_edges(irn) == 1) {
901 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
902 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
904 if (get_Proj_proj(proj) == pn_DivMod_res_div) {
905 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
908 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
911 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
914 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
916 set_ia32_res_mode(res, mode_Is);
923 * Wrapper for generate_DivMod. Sets flavour_Mod.
925 * @param env The transformation environment
927 static ir_node *gen_Mod(ia32_transform_env_t *env) {
928 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
932 * Wrapper for generate_DivMod. Sets flavour_Div.
934 * @param env The transformation environment
936 static ir_node *gen_Div(ia32_transform_env_t *env) {
937 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
941 * Wrapper for generate_DivMod. Sets flavour_DivMod.
943 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
944 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
950 * Creates an ia32 floating Div.
952 * @param env The transformation environment
953 * @return The created ia32 xDiv node
955 static ir_node *gen_Quot(ia32_transform_env_t *env) {
956 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
958 ir_node *nomem = new_rd_NoMem(env->irg);
959 ir_node *op1 = get_Quot_left(env->irn);
960 ir_node *op2 = get_Quot_right(env->irn);
963 if (USE_SSE2(env->cg)) {
964 if (is_ia32_xConst(op2)) {
965 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
966 set_ia32_am_support(new_op, ia32_am_None);
967 set_ia32_Immop_attr(new_op, op2);
970 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
971 set_ia32_am_support(new_op, ia32_am_Source);
975 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
976 set_ia32_am_support(new_op, ia32_am_Source);
978 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
979 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
987 * Creates an ia32 Shl.
989 * @param env The transformation environment
990 * @return The created ia32 Shl node
992 static ir_node *gen_Shl(ia32_transform_env_t *env) {
993 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
999 * Creates an ia32 Shr.
1001 * @param env The transformation environment
1002 * @return The created ia32 Shr node
1004 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1005 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1011 * Creates an ia32 Shrs.
1013 * @param env The transformation environment
1014 * @return The created ia32 Shrs node
1016 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1017 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1023 * Creates an ia32 RotL.
1025 * @param env The transformation environment
1026 * @param op1 The first operator
1027 * @param op2 The second operator
1028 * @return The created ia32 RotL node
1030 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1031 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1037 * Creates an ia32 RotR.
1038 * NOTE: There is no RotR with immediate because this would always be a RotL
1039 * "imm-mode_size_bits" which can be pre-calculated.
1041 * @param env The transformation environment
1042 * @param op1 The first operator
1043 * @param op2 The second operator
1044 * @return The created ia32 RotR node
1046 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1047 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1053 * Creates an ia32 RotR or RotL (depending on the found pattern).
1055 * @param env The transformation environment
1056 * @return The created ia32 RotL or RotR node
1058 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1059 ir_node *rotate = NULL;
1060 ir_node *op1 = get_Rot_left(env->irn);
1061 ir_node *op2 = get_Rot_right(env->irn);
1063 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1064 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1065 that means we can create a RotR instead of an Add and a RotL */
1068 ir_node *pred = get_Proj_pred(op2);
1070 if (is_ia32_Add(pred)) {
1071 ir_node *pred_pred = get_irn_n(pred, 2);
1072 tarval *tv = get_ia32_Immop_tarval(pred);
1073 long bits = get_mode_size_bits(env->mode);
1075 if (is_Proj(pred_pred)) {
1076 pred_pred = get_Proj_pred(pred_pred);
1079 if (is_ia32_Minus(pred_pred) &&
1080 tarval_is_long(tv) &&
1081 get_tarval_long(tv) == bits)
1083 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1084 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1091 rotate = gen_RotL(env, op1, op2);
1100 * Transforms a Minus node.
1102 * @param env The transformation environment
1103 * @param op The Minus operand
1104 * @return The created ia32 Minus node
1106 static ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1111 if (mode_is_float(env->mode)) {
1113 if (USE_SSE2(env->cg)) {
1114 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1115 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1116 ir_node *nomem = new_rd_NoMem(env->irg);
1118 new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1120 size = get_mode_size_bits(env->mode);
1121 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1123 set_ia32_sc(new_op, name);
1125 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1127 set_ia32_res_mode(new_op, env->mode);
1128 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1130 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
1133 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1134 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1138 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1145 * Transforms a Minus node.
1147 * @param env The transformation environment
1148 * @return The created ia32 Minus node
1150 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1151 return gen_Minus_ex(env, get_Minus_op(env->irn));
1156 * Transforms a Not node.
1158 * @param env The transformation environment
1159 * @return The created ia32 Not node
1161 static ir_node *gen_Not(ia32_transform_env_t *env) {
1162 assert (! mode_is_float(env->mode));
1163 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1169 * Transforms an Abs node.
1171 * @param env The transformation environment
1172 * @return The created ia32 Abs node
1174 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1175 ir_node *res, *p_eax, *p_edx;
1176 dbg_info *dbg = env->dbg;
1177 ir_mode *mode = env->mode;
1178 ir_graph *irg = env->irg;
1179 ir_node *block = env->block;
1180 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1181 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1182 ir_node *nomem = new_NoMem();
1183 ir_node *op = get_Abs_op(env->irn);
1187 if (mode_is_float(mode)) {
1189 if (USE_SSE2(env->cg)) {
1190 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1192 size = get_mode_size_bits(mode);
1193 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1195 set_ia32_sc(res, name);
1197 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1199 set_ia32_res_mode(res, mode);
1200 set_ia32_immop_type(res, ia32_ImmSymConst);
1202 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
1205 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1206 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1210 res = new_rd_ia32_Cdq(dbg, irg, block, op);
1211 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1212 set_ia32_res_mode(res, mode);
1214 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
1215 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
1217 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1218 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1219 set_ia32_res_mode(res, mode);
1221 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
1223 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1224 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1225 set_ia32_res_mode(res, mode);
1227 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
1236 * Transforms a Load.
1238 * @param env The transformation environment
1239 * @return the created ia32 Load node
1241 static ir_node *gen_Load(ia32_transform_env_t *env) {
1242 ir_node *node = env->irn;
1243 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1244 ir_node *ptr = get_Load_ptr(node);
1245 ir_node *lptr = ptr;
1246 ir_mode *mode = get_Load_mode(node);
1249 ia32_am_flavour_t am_flav = ia32_B;
1251 /* address might be a constant (symconst or absolute address) */
1252 if (is_ia32_Const(ptr)) {
1257 if (mode_is_float(mode)) {
1259 if (USE_SSE2(env->cg))
1260 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1262 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1265 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1268 /* base is an constant address */
1270 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1271 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1274 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1280 set_ia32_am_support(new_op, ia32_am_Source);
1281 set_ia32_op_type(new_op, ia32_AddrModeS);
1282 set_ia32_am_flavour(new_op, am_flav);
1283 set_ia32_ls_mode(new_op, mode);
1285 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1293 * Transforms a Store.
1295 * @param env The transformation environment
1296 * @return the created ia32 Store node
1298 static ir_node *gen_Store(ia32_transform_env_t *env) {
1299 ir_node *node = env->irn;
1300 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1301 ir_node *val = get_Store_value(node);
1302 ir_node *ptr = get_Store_ptr(node);
1303 ir_node *sptr = ptr;
1304 ir_node *mem = get_Store_mem(node);
1305 ir_mode *mode = get_irn_mode(val);
1306 ir_node *sval = val;
1309 ia32_am_flavour_t am_flav = ia32_B;
1310 ia32_immop_type_t immop = ia32_ImmNone;
1312 if (! mode_is_float(mode)) {
1313 /* in case of storing a const (but not a symconst) -> make it an attribute */
1314 if (is_ia32_Cnst(val)) {
1315 switch (get_ia32_op_type(val)) {
1317 immop = ia32_ImmConst;
1320 immop = ia32_ImmSymConst;
1323 assert(0 && "unsupported Const type");
1329 /* address might be a constant (symconst or absolute address) */
1330 if (is_ia32_Const(ptr)) {
1335 if (mode_is_float(mode)) {
1337 if (USE_SSE2(env->cg))
1338 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1340 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1342 else if (get_mode_size_bits(mode) == 8) {
1343 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1346 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem);
1349 /* stored const is an attribute (saves a register) */
1350 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1351 set_ia32_Immop_attr(new_op, val);
1354 /* base is an constant address */
1356 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1357 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1360 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1366 set_ia32_am_support(new_op, ia32_am_Dest);
1367 set_ia32_op_type(new_op, ia32_AddrModeD);
1368 set_ia32_am_flavour(new_op, am_flav);
1369 set_ia32_ls_mode(new_op, get_irn_mode(val));
1370 set_ia32_immop_type(new_op, immop);
1372 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1380 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1382 * @param env The transformation environment
1383 * @return The transformed node.
1385 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1386 dbg_info *dbg = env->dbg;
1387 ir_graph *irg = env->irg;
1388 ir_node *block = env->block;
1389 ir_node *node = env->irn;
1390 ir_node *sel = get_Cond_selector(node);
1391 ir_mode *sel_mode = get_irn_mode(sel);
1392 ir_node *res = NULL;
1393 ir_node *pred = NULL;
1394 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1395 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1397 if (is_Proj(sel) && sel_mode == mode_b) {
1398 ir_node *nomem = new_NoMem();
1400 pred = get_Proj_pred(sel);
1402 /* get both compare operators */
1403 cmp_a = get_Cmp_left(pred);
1404 cmp_b = get_Cmp_right(pred);
1406 /* check if we can use a CondJmp with immediate */
1407 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1408 expr = get_expr_op(cmp_a, cmp_b);
1411 pn_Cmp pnc = get_Proj_proj(sel);
1413 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1414 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1415 /* a Cmp A =/!= 0 */
1416 ir_node *op1 = expr;
1417 ir_node *op2 = expr;
1418 ir_node *and = skip_Proj(expr);
1419 const char *cnst = NULL;
1421 /* check, if expr is an only once used And operation */
1422 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1423 op1 = get_irn_n(and, 2);
1424 op2 = get_irn_n(and, 3);
1426 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1428 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1429 set_ia32_pncode(res, get_Proj_proj(sel));
1430 set_ia32_res_mode(res, get_irn_mode(op1));
1433 copy_ia32_Immop_attr(res, and);
1436 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1441 if (mode_is_float(get_irn_mode(expr))) {
1443 if (USE_SSE2(env->cg))
1444 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1450 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1452 set_ia32_Immop_attr(res, cnst);
1453 set_ia32_res_mode(res, get_irn_mode(expr));
1456 if (mode_is_float(get_irn_mode(cmp_a))) {
1458 if (USE_SSE2(env->cg))
1459 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1462 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1463 proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
1464 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1468 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1469 set_ia32_commutative(res);
1471 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1474 set_ia32_pncode(res, get_Proj_proj(sel));
1475 set_ia32_am_support(res, ia32_am_Source);
1478 /* determine the smallest switch case value */
1479 int switch_min = INT_MAX;
1480 const ir_edge_t *edge;
1483 foreach_out_edge(node, edge) {
1484 int pn = get_Proj_proj(get_edge_src_irn(edge));
1485 switch_min = pn < switch_min ? pn : switch_min;
1489 /* if smallest switch case is not 0 we need an additional sub */
1490 snprintf(buf, sizeof(buf), "%d", switch_min);
1491 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1492 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1493 sub_ia32_am_offs(res, buf);
1494 set_ia32_am_flavour(res, ia32_am_OB);
1495 set_ia32_am_support(res, ia32_am_Source);
1496 set_ia32_op_type(res, ia32_AddrModeS);
1499 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1500 set_ia32_pncode(res, get_Cond_defaultProj(node));
1501 set_ia32_res_mode(res, get_irn_mode(sel));
1504 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1511 * Transforms a CopyB node.
1513 * @param env The transformation environment
1514 * @return The transformed node.
1516 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1517 ir_node *res = NULL;
1518 dbg_info *dbg = env->dbg;
1519 ir_graph *irg = env->irg;
1520 ir_mode *mode = env->mode;
1521 ir_node *block = env->block;
1522 ir_node *node = env->irn;
1523 ir_node *src = get_CopyB_src(node);
1524 ir_node *dst = get_CopyB_dst(node);
1525 ir_node *mem = get_CopyB_mem(node);
1526 int size = get_type_size_bytes(get_CopyB_type(node));
1529 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1530 /* then we need the size explicitly in ECX. */
1531 if (size >= 16 * 4) {
1532 rem = size & 0x3; /* size % 4 */
1535 res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
1536 set_ia32_op_type(res, ia32_Const);
1537 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1539 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1540 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1543 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1544 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1545 set_ia32_immop_type(res, ia32_ImmConst);
1548 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1556 * Transforms a Mux node into CMov.
1558 * @param env The transformation environment
1559 * @return The transformed node.
1561 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1562 ir_node *node = env->irn;
1563 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1564 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1566 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1573 * Following conversion rules apply:
1577 * 1) n bit -> m bit n > m (downscale)
1578 * a) target is signed: movsx
1579 * b) target is unsigned: and with lower bits sets
1580 * 2) n bit -> m bit n == m (sign change)
1582 * 3) n bit -> m bit n < m (upscale)
1583 * a) source is signed: movsx
1584 * b) source is unsigned: and with lower bits sets
1588 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1592 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1593 * if target mode < 32bit: additional INT -> INT conversion (see above)
1597 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1598 * x87 is mode_E internally, conversions happen only at load and store
1599 * in non-strict semantic
1603 * Create a conversion from x87 state register to general purpose.
1605 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1606 ia32_code_gen_t *cg = env->cg;
1607 entity *ent = cg->fp_to_gp;
1608 ir_graph *irg = env->irg;
1609 ir_node *block = env->block;
1610 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1611 ir_node *op = get_Conv_op(env->irn);
1612 ir_node *fist, *mem, *load;
1615 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1616 ent = cg->fp_to_gp =
1617 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1621 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
1623 set_ia32_frame_ent(fist, ent);
1624 set_ia32_use_frame(fist);
1625 set_ia32_am_support(fist, ia32_am_Dest);
1626 set_ia32_op_type(fist, ia32_AddrModeD);
1627 set_ia32_am_flavour(fist, ia32_B);
1628 set_ia32_ls_mode(fist, mode_E);
1630 mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
1633 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1635 set_ia32_frame_ent(load, ent);
1636 set_ia32_use_frame(load);
1637 set_ia32_am_support(load, ia32_am_Source);
1638 set_ia32_op_type(load, ia32_AddrModeS);
1639 set_ia32_am_flavour(load, ia32_B);
1640 set_ia32_ls_mode(load, tgt_mode);
1642 return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
1646 * Create a conversion from x87 state register to general purpose.
1648 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1649 ia32_code_gen_t *cg = env->cg;
1650 entity *ent = cg->gp_to_fp;
1651 ir_graph *irg = env->irg;
1652 ir_node *block = env->block;
1653 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1654 ir_node *nomem = get_irg_no_mem(irg);
1655 ir_node *op = get_Conv_op(env->irn);
1656 ir_node *fild, *store, *mem;
1660 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
1661 ent = cg->gp_to_fp =
1662 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
1665 /* first convert to 32 bit */
1666 src_bits = get_mode_size_bits(src_mode);
1667 if (src_bits == 8) {
1668 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
1669 op = new_r_Proj(irg, block, op, mode_Is, 0);
1671 else if (src_bits < 32) {
1672 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
1673 op = new_r_Proj(irg, block, op, mode_Is, 0);
1677 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
1679 set_ia32_frame_ent(store, ent);
1680 set_ia32_use_frame(store);
1682 set_ia32_am_support(store, ia32_am_Dest);
1683 set_ia32_op_type(store, ia32_AddrModeD);
1684 set_ia32_am_flavour(store, ia32_B);
1685 set_ia32_ls_mode(store, mode_Is);
1687 mem = new_r_Proj(irg, block, store, mode_M, 0);
1690 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1692 set_ia32_frame_ent(fild, ent);
1693 set_ia32_use_frame(fild);
1694 set_ia32_am_support(fild, ia32_am_Source);
1695 set_ia32_op_type(fild, ia32_AddrModeS);
1696 set_ia32_am_flavour(fild, ia32_B);
1697 set_ia32_ls_mode(fild, mode_E);
1699 return new_r_Proj(irg, block, fild, mode_E, 0);
1703 * Transforms a Conv node.
1705 * @param env The transformation environment
1706 * @return The created ia32 Conv node
1708 static ir_node *gen_Conv(ia32_transform_env_t *env) {
1709 dbg_info *dbg = env->dbg;
1710 ir_graph *irg = env->irg;
1711 ir_node *op = get_Conv_op(env->irn);
1712 ir_mode *src_mode = get_irn_mode(op);
1713 ir_mode *tgt_mode = env->mode;
1714 int src_bits = get_mode_size_bits(src_mode);
1715 int tgt_bits = get_mode_size_bits(tgt_mode);
1716 ir_node *block = env->block;
1717 ir_node *new_op = NULL;
1718 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1719 ir_node *nomem = new_rd_NoMem(irg);
1721 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1723 if (src_mode == tgt_mode) {
1724 /* this can happen when changing mode_P to mode_Is */
1725 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1726 edges_reroute(env->irn, op, irg);
1728 else if (mode_is_float(src_mode)) {
1729 /* we convert from float ... */
1730 if (mode_is_float(tgt_mode)) {
1732 if (USE_SSE2(env->cg)) {
1733 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1734 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
1737 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
1738 edges_reroute(env->irn, op, irg);
1743 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1744 if (USE_SSE2(env->cg))
1745 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
1747 return gen_x87_fp_to_gp(env, tgt_mode);
1749 /* if target mode is not int: add an additional downscale convert */
1750 if (tgt_bits < 32) {
1751 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1752 set_ia32_am_support(new_op, ia32_am_Source);
1753 set_ia32_tgt_mode(new_op, tgt_mode);
1754 set_ia32_src_mode(new_op, src_mode);
1756 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
1758 if (tgt_bits == 8 || src_bits == 8) {
1759 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
1762 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
1768 /* we convert from int ... */
1769 if (mode_is_float(tgt_mode)) {
1772 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1773 if (USE_SSE2(env->cg))
1774 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
1776 return gen_x87_gp_to_fp(env, src_mode);
1780 if (get_mode_size_bits(src_mode) == tgt_bits) {
1781 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
1782 edges_reroute(env->irn, op, irg);
1785 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
1786 if (tgt_bits == 8 || src_bits == 8) {
1787 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
1790 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
1797 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1798 set_ia32_tgt_mode(new_op, tgt_mode);
1799 set_ia32_src_mode(new_op, src_mode);
1801 set_ia32_am_support(new_op, ia32_am_Source);
1803 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
1811 /********************************************
1814 * | |__ ___ _ __ ___ __| | ___ ___
1815 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1816 * | |_) | __/ | | | (_) | (_| | __/\__ \
1817 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1819 ********************************************/
1821 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
1822 ir_node *new_op = NULL;
1823 ir_node *node = env->irn;
1824 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1825 ir_node *mem = new_rd_NoMem(env->irg);
1826 ir_node *ptr = get_irn_n(node, 0);
1827 entity *ent = be_get_frame_entity(node);
1828 ir_mode *mode = env->mode;
1830 // /* If the StackParam has only one user -> */
1831 // /* put it in the Block where the user resides */
1832 // if (get_irn_n_edges(node) == 1) {
1833 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
1836 if (mode_is_float(mode)) {
1838 if (USE_SSE2(env->cg))
1839 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
1841 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
1844 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
1847 set_ia32_frame_ent(new_op, ent);
1848 set_ia32_use_frame(new_op);
1850 set_ia32_am_support(new_op, ia32_am_Source);
1851 set_ia32_op_type(new_op, ia32_AddrModeS);
1852 set_ia32_am_flavour(new_op, ia32_B);
1853 set_ia32_ls_mode(new_op, mode);
1855 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1857 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
1861 * Transforms a FrameAddr into an ia32 Add.
1863 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
1864 ir_node *new_op = NULL;
1865 ir_node *node = env->irn;
1866 ir_node *op = get_irn_n(node, 0);
1867 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1868 ir_node *nomem = new_rd_NoMem(env->irg);
1870 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
1871 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1872 set_ia32_am_support(new_op, ia32_am_Full);
1873 set_ia32_use_frame(new_op);
1874 set_ia32_immop_type(new_op, ia32_ImmConst);
1875 set_ia32_commutative(new_op);
1877 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1879 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
1883 * Transforms a FrameLoad into an ia32 Load.
1885 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
1886 ir_node *new_op = NULL;
1887 ir_node *node = env->irn;
1888 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1889 ir_node *mem = get_irn_n(node, 0);
1890 ir_node *ptr = get_irn_n(node, 1);
1891 entity *ent = be_get_frame_entity(node);
1892 ir_mode *mode = get_type_mode(get_entity_type(ent));
1894 if (mode_is_float(mode)) {
1896 if (USE_SSE2(env->cg))
1897 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
1899 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
1902 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
1904 set_ia32_frame_ent(new_op, ent);
1905 set_ia32_use_frame(new_op);
1907 set_ia32_am_support(new_op, ia32_am_Source);
1908 set_ia32_op_type(new_op, ia32_AddrModeS);
1909 set_ia32_am_flavour(new_op, ia32_B);
1910 set_ia32_ls_mode(new_op, mode);
1912 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1919 * Transforms a FrameStore into an ia32 Store.
1921 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
1922 ir_node *new_op = NULL;
1923 ir_node *node = env->irn;
1924 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1925 ir_node *mem = get_irn_n(node, 0);
1926 ir_node *ptr = get_irn_n(node, 1);
1927 ir_node *val = get_irn_n(node, 2);
1928 entity *ent = be_get_frame_entity(node);
1929 ir_mode *mode = get_irn_mode(val);
1931 if (mode_is_float(mode)) {
1933 if (USE_SSE2(env->cg))
1934 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
1936 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
1938 else if (get_mode_size_bits(mode) == 8) {
1939 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
1942 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
1945 set_ia32_frame_ent(new_op, ent);
1946 set_ia32_use_frame(new_op);
1948 set_ia32_am_support(new_op, ia32_am_Dest);
1949 set_ia32_op_type(new_op, ia32_AddrModeD);
1950 set_ia32_am_flavour(new_op, ia32_B);
1951 set_ia32_ls_mode(new_op, mode);
1953 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1959 * This function just sets the register for the Unknown node
1960 * as this is not done during register allocation because Unknown
1961 * is an "ignore" node.
1963 static ir_node *gen_Unknown(ia32_transform_env_t *env) {
1964 ir_mode *mode = env->mode;
1965 ir_node *irn = env->irn;
1967 if (mode_is_float(mode)) {
1968 if (USE_SSE2(env->cg))
1969 arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
1971 arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
1973 else if (mode_is_int(mode) || mode_is_reference(mode)) {
1974 arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
1977 assert(0 && "unsupported Unknown-Mode");
1984 /*********************************************************
1987 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1988 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1989 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1990 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1992 *********************************************************/
1995 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
1996 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
1998 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
1999 ia32_transform_env_t tenv;
2000 ir_node *in1, *in2, *noreg, *nomem, *res;
2001 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
2003 /* Return if AM node or not a Sub or xSub */
2004 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_xSub(irn)))
2007 noreg = ia32_new_NoReg_gp(cg);
2008 nomem = new_rd_NoMem(cg->irg);
2009 in1 = get_irn_n(irn, 2);
2010 in2 = get_irn_n(irn, 3);
2011 in1_reg = arch_get_irn_register(cg->arch_env, in1);
2012 in2_reg = arch_get_irn_register(cg->arch_env, in2);
2013 out_reg = get_ia32_out_reg(irn, 0);
2015 tenv.block = get_nodes_block(irn);
2016 tenv.dbg = get_irn_dbg_info(irn);
2019 tenv.mode = get_ia32_res_mode(irn);
2021 DEBUG_ONLY(tenv.mod = cg->mod;)
2023 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
2024 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
2025 /* generate the neg src2 */
2026 res = gen_Minus_ex(&tenv, in2);
2027 arch_set_irn_register(cg->arch_env, res, in2_reg);
2029 /* add to schedule */
2030 sched_add_before(irn, res);
2032 /* generate the add */
2033 if (mode_is_float(tenv.mode)) {
2034 res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2035 set_ia32_am_support(res, ia32_am_Source);
2038 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2039 set_ia32_am_support(res, ia32_am_Full);
2040 set_ia32_commutative(res);
2043 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
2045 slots = get_ia32_slots(res);
2048 /* add to schedule */
2049 sched_add_before(irn, res);
2051 /* remove the old sub */
2054 DBG_OPT_SUB2NEGADD(irn, res);
2056 /* exchange the add and the sub */
2062 * Transforms a LEA into an Add if possible
2063 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2065 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
2066 ia32_am_flavour_t am_flav;
2068 ir_node *res = NULL;
2069 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
2071 ia32_transform_env_t tenv;
2072 const arch_register_t *out_reg, *base_reg, *index_reg;
2075 if (! is_ia32_Lea(irn))
2078 am_flav = get_ia32_am_flavour(irn);
2080 /* only some LEAs can be transformed to an Add */
2081 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
2084 noreg = ia32_new_NoReg_gp(cg);
2085 nomem = new_rd_NoMem(cg->irg);
2088 base = get_irn_n(irn, 0);
2089 index = get_irn_n(irn,1);
2091 offs = get_ia32_am_offs(irn);
2093 /* offset has a explicit sign -> we need to skip + */
2094 if (offs && offs[0] == '+')
2097 out_reg = arch_get_irn_register(cg->arch_env, irn);
2098 base_reg = arch_get_irn_register(cg->arch_env, base);
2099 index_reg = arch_get_irn_register(cg->arch_env, index);
2101 tenv.block = get_nodes_block(irn);
2102 tenv.dbg = get_irn_dbg_info(irn);
2105 DEBUG_ONLY(tenv.mod = cg->mod;)
2106 tenv.mode = get_irn_mode(irn);
2109 switch(get_ia32_am_flavour(irn)) {
2111 /* out register must be same as base register */
2112 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2118 /* out register must be same as base register */
2119 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2126 /* out register must be same as index register */
2127 if (! REGS_ARE_EQUAL(out_reg, index_reg))
2134 /* out register must be same as one in register */
2135 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
2139 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
2144 /* in registers a different from out -> no Add possible */
2151 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
2152 arch_set_irn_register(cg->arch_env, res, out_reg);
2153 set_ia32_op_type(res, ia32_Normal);
2154 set_ia32_commutative(res);
2157 set_ia32_cnst(res, offs);
2158 set_ia32_immop_type(res, ia32_ImmConst);
2161 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
2163 /* add Add to schedule */
2164 sched_add_before(irn, res);
2166 DBG_OPT_LEA2ADD(irn, res);
2168 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, 0);
2170 /* add result Proj to schedule */
2171 sched_add_before(irn, res);
2173 /* remove the old LEA */
2176 /* exchange the Add and the LEA */
2181 * the BAD transformer.
2183 static ir_node *bad_transform(ia32_transform_env_t *env) {
2184 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2190 * Enters all transform functions into the generic pointer
2192 void ia32_register_transformers(void) {
2193 ir_op *op_Max, *op_Min, *op_Mulh;
2195 /* first clear the generic function pointer for all ops */
2196 clear_irp_opcodes_generic_func();
2198 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2199 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
2245 /* constant transformation happens earlier */
2269 /* set the register for all Unknown nodes */
2272 op_Max = get_op_Max();
2275 op_Min = get_op_Min();
2278 op_Mulh = get_op_Mulh();
2287 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
2290 * Transforms the given firm node (and maybe some other related nodes)
2291 * into one or more assembler nodes.
2293 * @param node the firm node
2294 * @param env the debug module
2296 void ia32_transform_node(ir_node *node, void *env) {
2297 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2298 ir_op *op = get_irn_op(node);
2299 ir_node *asm_node = NULL;
2304 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
2305 if (op->ops.generic) {
2306 ia32_transform_env_t tenv;
2307 transform_func *transform = (transform_func *)op->ops.generic;
2309 tenv.block = get_nodes_block(node);
2310 tenv.dbg = get_irn_dbg_info(node);
2311 tenv.irg = current_ir_graph;
2313 tenv.mode = get_irn_mode(node);
2315 DEBUG_ONLY(tenv.mod = cg->mod;)
2317 asm_node = (*transform)(&tenv);
2320 /* exchange nodes if a new one was generated */
2322 exchange(node, asm_node);
2323 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2326 DB((cg->mod, LEVEL_1, "ignored\n"));