2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
30 #include "archop.h" /* we need this for Min and Max nodes */
37 #include "../benode_t.h"
38 #include "../besched.h"
40 #include "../beutil.h"
42 #include "bearch_ia32_t.h"
43 #include "ia32_nodes_attr.h"
44 #include "ia32_transform.h"
45 #include "ia32_new_nodes.h"
46 #include "ia32_map_regs.h"
47 #include "ia32_dbg_stat.h"
48 #include "ia32_optimize.h"
49 #include "ia32_util.h"
51 #include "gen_ia32_regalloc_if.h"
53 #define SFP_SIGN "0x80000000"
54 #define DFP_SIGN "0x8000000000000000"
55 #define SFP_ABS "0x7FFFFFFF"
56 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
58 #define TP_SFP_SIGN "ia32_sfp_sign"
59 #define TP_DFP_SIGN "ia32_dfp_sign"
60 #define TP_SFP_ABS "ia32_sfp_abs"
61 #define TP_DFP_ABS "ia32_dfp_abs"
63 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
64 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
65 #define ENT_SFP_ABS "IA32_SFP_ABS"
66 #define ENT_DFP_ABS "IA32_DFP_ABS"
68 typedef struct ia32_transform_env_t {
69 ir_graph *irg; /**< The irg, the node should be created in */
70 ia32_code_gen_t *cg; /**< The code generator */
71 int visited; /**< visited count that indicates whether a
72 node is already transformed */
73 pdeq *worklist; /**< worklist of nodes that still need to be
75 ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/
76 DEBUG_ONLY(firm_dbg_module_t *mod;) /**< The firm debugger */
77 } ia32_transform_env_t;
79 extern ir_op *get_op_Mulh(void);
81 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
82 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
83 ir_node *op2, ir_node *mem);
85 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
86 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
89 typedef ir_node *(transform_func)(ia32_transform_env_t *env, ir_node *node);
91 /****************************************************************************************************
93 * | | | | / _| | | (_)
94 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
95 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
96 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
97 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
99 ****************************************************************************************************/
101 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node);
102 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node);
103 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
106 static INLINE void set_new_node(ir_node *old_node, ir_node *new_node)
108 set_irn_link(old_node, new_node);
111 static INLINE ir_node *get_new_node(ir_node *old_node)
113 assert(irn_visited(old_node));
114 return (ir_node*) get_irn_link(old_node);
118 * Returns 1 if irn is a Const representing 0, 0 otherwise
120 static INLINE int is_ia32_Const_0(ir_node *irn) {
121 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
122 && tarval_is_null(get_ia32_Immop_tarval(irn));
126 * Returns 1 if irn is a Const representing 1, 0 otherwise
128 static INLINE int is_ia32_Const_1(ir_node *irn) {
129 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
130 && tarval_is_one(get_ia32_Immop_tarval(irn));
134 * Collects all Projs of a node into the node array. Index is the projnum.
135 * BEWARE: The caller has to assure the appropriate array size!
137 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
138 const ir_edge_t *edge;
139 assert(get_irn_mode(irn) == mode_T && "need mode_T");
141 memset(projs, 0, size * sizeof(projs[0]));
143 foreach_out_edge(irn, edge) {
144 ir_node *proj = get_edge_src_irn(edge);
145 int proj_proj = get_Proj_proj(proj);
146 assert(proj_proj < size);
147 projs[proj_proj] = proj;
152 * Renumbers the proj having pn_old in the array tp pn_new
153 * and removes the proj from the array.
155 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
156 fprintf(stderr, "Warning: renumber_Proj used!\n");
158 set_Proj_proj(projs[pn_old], pn_new);
159 projs[pn_old] = NULL;
164 * creates a unique ident by adding a number to a tag
166 * @param tag the tag string, must contain a %d if a number
169 static ident *unique_id(const char *tag)
171 static unsigned id = 0;
174 snprintf(str, sizeof(str), tag, ++id);
175 return new_id_from_str(str);
179 * Get a primitive type for a mode.
181 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
183 pmap_entry *e = pmap_find(types, mode);
188 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
189 res = new_type_primitive(new_id_from_str(buf), mode);
190 pmap_insert(types, mode, res);
198 * Get an entity that is initialized with a tarval
200 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
202 tarval *tv = get_Const_tarval(cnst);
203 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
208 ir_mode *mode = get_irn_mode(cnst);
209 ir_type *tp = get_Const_type(cnst);
210 if (tp == firm_unknown_type)
211 tp = get_prim_type(cg->isa->types, mode);
213 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
215 set_entity_ld_ident(res, get_entity_ident(res));
216 set_entity_visibility(res, visibility_local);
217 set_entity_variability(res, variability_constant);
218 set_entity_allocation(res, allocation_static);
220 /* we create a new entity here: It's initialization must resist on the
222 rem = current_ir_graph;
223 current_ir_graph = get_const_code_irg();
224 set_atomic_ent_value(res, new_Const_type(tv, tp));
225 current_ir_graph = rem;
227 pmap_insert(cg->isa->tv_ent, tv, res);
235 * Transforms a Const.
237 * @param mod the debug module
238 * @param block the block the new node should belong to
239 * @param node the ir Const node
240 * @param mode mode of the Const
241 * @return the created ia32 Const node
243 static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) {
244 ir_graph *irg = env->irg;
245 dbg_info *dbg = get_irn_dbg_info(node);
246 ir_mode *mode = get_irn_mode(node);
247 ir_node *block = transform_node(env, get_nodes_block(node));
249 if (mode_is_float(mode)) {
252 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
253 ir_node *nomem = new_NoMem();
257 if (! USE_SSE2(env->cg)) {
258 cnst_classify_t clss = classify_Const(node);
260 if (clss == CNST_NULL) {
261 load = new_rd_ia32_vfldz(dbg, irg, block);
263 } else if (clss == CNST_ONE) {
264 load = new_rd_ia32_vfld1(dbg, irg, block);
267 floatent = get_entity_for_tv(env->cg, node);
269 load = new_rd_ia32_vfld(dbg, irg, block, noreg, noreg, nomem);
270 set_ia32_am_support(load, ia32_am_Source);
271 set_ia32_op_type(load, ia32_AddrModeS);
272 set_ia32_am_flavour(load, ia32_am_N);
273 set_ia32_am_sc(load, ia32_get_ent_ident(floatent));
274 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
277 floatent = get_entity_for_tv(env->cg, node);
279 load = new_rd_ia32_xLoad(dbg, irg, block, noreg, noreg, nomem);
280 set_ia32_am_support(load, ia32_am_Source);
281 set_ia32_op_type(load, ia32_AddrModeS);
282 set_ia32_am_flavour(load, ia32_am_N);
283 set_ia32_am_sc(load, ia32_get_ent_ident(floatent));
284 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_xLoad_res);
287 set_ia32_ls_mode(load, mode);
288 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
290 /* Const Nodes before the initial IncSP are a bad idea, because
291 * they could be spilled and we have no SP ready at that point yet
293 if (get_irg_start_block(irg) == block) {
294 add_irn_dep(load, get_irg_frame(irg));
297 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
300 ir_node *cnst = new_rd_ia32_Const(dbg, irg, block);
303 if (get_irg_start_block(irg) == block) {
304 add_irn_dep(cnst, get_irg_frame(irg));
307 set_ia32_Const_attr(cnst, node);
308 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
313 return new_r_Bad(irg);
317 * Transforms a SymConst.
319 * @param mod the debug module
320 * @param block the block the new node should belong to
321 * @param node the ir SymConst node
322 * @param mode mode of the SymConst
323 * @return the created ia32 Const node
325 static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) {
326 ir_graph *irg = env->irg;
327 dbg_info *dbg = get_irn_dbg_info(node);
328 ir_mode *mode = get_irn_mode(node);
329 ir_node *block = transform_node(env, get_nodes_block(node));
332 if (mode_is_float(mode)) {
334 if (USE_SSE2(env->cg))
335 cnst = new_rd_ia32_xConst(dbg, irg, block);
337 cnst = new_rd_ia32_vfConst(dbg, irg, block);
338 set_ia32_ls_mode(cnst, mode);
340 cnst = new_rd_ia32_Const(dbg, irg, block);
343 /* Const Nodes before the initial IncSP are a bad idea, because
344 * they could be spilled and we have no SP ready at that point yet
346 if (get_irg_start_block(irg) == block) {
347 add_irn_dep(cnst, get_irg_frame(irg));
350 set_ia32_Const_attr(cnst, node);
351 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
357 * SSE convert of an integer node into a floating point node.
359 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg,
360 ir_graph *irg, ir_node *block,
361 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
363 ir_node *noreg = ia32_new_NoReg_gp(cg);
364 ir_node *nomem = new_rd_NoMem(irg);
365 ir_node *old_pred = get_Cmp_left(old_node);
366 ir_mode *in_mode = get_irn_mode(old_pred);
367 int in_bits = get_mode_size_bits(in_mode);
369 ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
370 set_ia32_ls_mode(conv, tgt_mode);
372 set_ia32_am_support(conv, ia32_am_Source);
374 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
380 * SSE convert of an float node into a double node.
382 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbg,
383 ir_graph *irg, ir_node *block,
384 ir_node *in, ir_node *old_node)
386 ir_node *noreg = ia32_new_NoReg_gp(cg);
387 ir_node *nomem = new_rd_NoMem(irg);
389 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, in, nomem);
390 set_ia32_am_support(conv, ia32_am_Source);
391 set_ia32_ls_mode(conv, mode_E);
392 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
397 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
398 ident *ia32_gen_fp_known_const(ia32_known_const_t kct) {
399 static const struct {
401 const char *ent_name;
402 const char *cnst_str;
403 } names [ia32_known_const_max] = {
404 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
405 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
406 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
407 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
409 static ir_entity *ent_cache[ia32_known_const_max];
411 const char *tp_name, *ent_name, *cnst_str;
419 ent_name = names[kct].ent_name;
420 if (! ent_cache[kct]) {
421 tp_name = names[kct].tp_name;
422 cnst_str = names[kct].cnst_str;
424 //mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
426 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
427 tp = new_type_primitive(new_id_from_str(tp_name), mode);
428 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
430 set_entity_ld_ident(ent, get_entity_ident(ent));
431 set_entity_visibility(ent, visibility_local);
432 set_entity_variability(ent, variability_constant);
433 set_entity_allocation(ent, allocation_static);
435 /* we create a new entity here: It's initialization must resist on the
437 rem = current_ir_graph;
438 current_ir_graph = get_const_code_irg();
439 cnst = new_Const(mode, tv);
440 current_ir_graph = rem;
442 set_atomic_ent_value(ent, cnst);
444 /* cache the entry */
445 ent_cache[kct] = ent;
448 return get_entity_ident(ent_cache[kct]);
453 * Prints the old node name on cg obst and returns a pointer to it.
455 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
456 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
458 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
459 obstack_1grow(isa->name_obst, 0);
460 return obstack_finish(isa->name_obst);
464 /* determine if one operator is an Imm */
465 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
467 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
468 else return is_ia32_Cnst(op2) ? op2 : NULL;
471 /* determine if one operator is not an Imm */
472 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
473 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
476 static void fold_immediate(ia32_transform_env_t *env, ir_node *node, int in1, int in2) {
480 if(! (env->cg->opt & IA32_OPT_IMMOPS))
483 left = get_irn_n(node, in1);
484 right = get_irn_n(node, in2);
485 if(!is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
486 /* we can only set right operand to immediate */
487 if(!is_ia32_commutative(node))
489 /* exchange left/right */
490 set_irn_n(node, in1, right);
491 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
492 copy_ia32_Immop_attr(node, left);
493 } else if(is_ia32_Cnst(right)) {
494 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
495 copy_ia32_Immop_attr(node, right);
500 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
504 * Construct a standard binary operation, set AM and immediate if required.
506 * @param env The transformation environment
507 * @param op1 The first operand
508 * @param op2 The second operand
509 * @param func The node constructor function
510 * @return The constructed ia32 node.
512 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *node,
513 ir_node *op1, ir_node *op2,
514 construct_binop_func *func) {
515 ir_node *new_node = NULL;
516 ir_graph *irg = env->irg;
517 dbg_info *dbg = get_irn_dbg_info(node);
518 ir_node *block = transform_node(env, get_nodes_block(node));
519 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
520 ir_node *nomem = new_NoMem();
521 ir_node *new_op1 = transform_node(env, op1);
522 ir_node *new_op2 = transform_node(env, op2);
524 new_node = func(dbg, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
525 if(func == new_rd_ia32_IMul) {
526 set_ia32_am_support(new_node, ia32_am_Source);
528 set_ia32_am_support(new_node, ia32_am_Full);
531 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
532 if (is_op_commutative(get_irn_op(node))) {
533 set_ia32_commutative(new_node);
535 fold_immediate(env, new_node, 2, 3);
541 * Construct a standard binary operation, set AM and immediate if required.
543 * @param env The transformation environment
544 * @param op1 The first operand
545 * @param op2 The second operand
546 * @param func The node constructor function
547 * @return The constructed ia32 node.
549 static ir_node *gen_binop_float(ia32_transform_env_t *env, ir_node *node,
550 ir_node *op1, ir_node *op2,
551 construct_binop_func *func)
553 ir_node *new_node = NULL;
554 dbg_info *dbg = get_irn_dbg_info(node);
555 ir_graph *irg = env->irg;
556 ir_mode *mode = get_irn_mode(node);
557 ir_node *block = transform_node(env, get_nodes_block(node));
558 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
559 ir_node *nomem = new_NoMem();
560 ir_node *new_op1 = transform_node(env, op1);
561 ir_node *new_op2 = transform_node(env, op2);
563 new_node = func(dbg, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
564 set_ia32_am_support(new_node, ia32_am_Source);
565 if (is_op_commutative(get_irn_op(node))) {
566 set_ia32_commutative(new_node);
568 if (USE_SSE2(env->cg)) {
569 set_ia32_ls_mode(new_node, mode);
572 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
579 * Construct a shift/rotate binary operation, sets AM and immediate if required.
581 * @param env The transformation environment
582 * @param op1 The first operand
583 * @param op2 The second operand
584 * @param func The node constructor function
585 * @return The constructed ia32 node.
587 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node,
588 ir_node *op1, ir_node *op2,
589 construct_binop_func *func) {
590 ir_node *new_op = NULL;
591 ir_mode *mode = get_irn_mode(node);
592 dbg_info *dbg = get_irn_dbg_info(node);
593 ir_graph *irg = env->irg;
594 ir_node *block = transform_node(env, get_nodes_block(node));
595 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
596 ir_node *nomem = new_NoMem();
599 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
600 ir_node *new_op1 = transform_node(env, op1);
601 ir_node *new_op2 = transform_node(env, op2);
604 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
606 /* Check if immediate optimization is on and */
607 /* if it's an operation with immediate. */
608 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
609 expr_op = get_expr_op(new_op1, new_op2);
611 assert((expr_op || imm_op) && "invalid operands");
614 /* We have two consts here: not yet supported */
618 /* Limit imm_op within range imm8 */
620 tv = get_ia32_Immop_tarval(imm_op);
623 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
624 set_ia32_Immop_tarval(imm_op, tv);
631 /* integer operations */
633 /* This is shift/rot with const */
634 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
636 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
637 copy_ia32_Immop_attr(new_op, imm_op);
639 /* This is a normal shift/rot */
640 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
641 new_op = func(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
645 set_ia32_am_support(new_op, ia32_am_Dest);
647 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
649 set_ia32_emit_cl(new_op);
656 * Construct a standard unary operation, set AM and immediate if required.
658 * @param env The transformation environment
659 * @param op The operand
660 * @param func The node constructor function
661 * @return The constructed ia32 node.
663 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *node, ir_node *op,
664 construct_unop_func *func) {
665 ir_node *new_node = NULL;
666 ir_graph *irg = env->irg;
667 dbg_info *dbg = get_irn_dbg_info(node);
668 ir_node *block = transform_node(env, get_nodes_block(node));
669 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
670 ir_node *nomem = new_NoMem();
671 ir_node *new_op = transform_node(env, op);
672 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
674 new_node = func(dbg, irg, block, noreg, noreg, new_op, nomem);
675 DB((mod, LEVEL_1, "INT unop ..."));
676 set_ia32_am_support(new_node, ia32_am_Dest);
678 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
685 * Creates an ia32 Add.
687 * @param env The transformation environment
688 * @return the created ia32 Add node
690 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) {
691 ir_node *new_op = NULL;
692 ir_graph *irg = env->irg;
693 dbg_info *dbg = get_irn_dbg_info(node);
694 ir_mode *mode = get_irn_mode(node);
695 ir_node *block = transform_node(env, get_nodes_block(node));
696 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
697 ir_node *nomem = new_NoMem();
698 ir_node *expr_op, *imm_op;
699 ir_node *op1 = get_Add_left(node);
700 ir_node *op2 = get_Add_right(node);
701 ir_node *new_op1 = transform_node(env, op1);
702 ir_node *new_op2 = transform_node(env, op2);
704 /* Check if immediate optimization is on and */
705 /* if it's an operation with immediate. */
706 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
707 expr_op = get_expr_op(new_op1, new_op2);
709 assert((expr_op || imm_op) && "invalid operands");
711 if (mode_is_float(mode)) {
713 if (USE_SSE2(env->cg))
714 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xAdd);
716 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfadd);
721 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
722 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
724 /* No expr_op means, that we have two const - one symconst and */
725 /* one tarval or another symconst - because this case is not */
726 /* covered by constant folding */
727 /* We need to check for: */
728 /* 1) symconst + const -> becomes a LEA */
729 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
730 /* linker doesn't support two symconsts */
732 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
733 /* this is the 2nd case */
734 new_op = new_rd_ia32_Lea(dbg, irg, block, new_op1, noreg);
735 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
736 set_ia32_am_flavour(new_op, ia32_am_OB);
737 set_ia32_am_support(new_op, ia32_am_Source);
738 set_ia32_op_type(new_op, ia32_AddrModeS);
740 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
741 } else if (tp1 == ia32_ImmSymConst) {
742 tarval *tv = get_ia32_Immop_tarval(new_op2);
743 long offs = get_tarval_long(tv);
745 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
746 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
748 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
749 add_ia32_am_offs_int(new_op, offs);
750 set_ia32_am_flavour(new_op, ia32_am_O);
751 set_ia32_am_support(new_op, ia32_am_Source);
752 set_ia32_op_type(new_op, ia32_AddrModeS);
753 } else if (tp2 == ia32_ImmSymConst) {
754 tarval *tv = get_ia32_Immop_tarval(new_op1);
755 long offs = get_tarval_long(tv);
757 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
758 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
760 add_ia32_am_offs_int(new_op, offs);
761 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
762 set_ia32_am_flavour(new_op, ia32_am_O);
763 set_ia32_am_support(new_op, ia32_am_Source);
764 set_ia32_op_type(new_op, ia32_AddrModeS);
766 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
767 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
768 tarval *restv = tarval_add(tv1, tv2);
770 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
772 new_op = new_rd_ia32_Const(dbg, irg, block);
773 set_ia32_Const_tarval(new_op, restv);
774 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
777 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
780 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
781 tarval_classification_t class_tv, class_negtv;
782 tarval *tv = get_ia32_Immop_tarval(imm_op);
784 /* optimize tarvals */
785 class_tv = classify_tarval(tv);
786 class_negtv = classify_tarval(tarval_neg(tv));
788 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
789 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
790 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
791 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
793 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
794 DB((env->mod, LEVEL_2, "Add(-1) to Dec ... "));
795 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
796 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
802 /* This is a normal add */
803 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
806 set_ia32_am_support(new_op, ia32_am_Full);
807 set_ia32_commutative(new_op);
809 fold_immediate(env, new_op, 2, 3);
811 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
817 static ir_node *create_ia32_Mul(ia32_transform_env_t *env, ir_node *node) {
818 ir_graph *irg = env->irg;
819 dbg_info *dbg = get_irn_dbg_info(node);
820 ir_node *block = transform_node(env, get_nodes_block(node));
821 ir_node *op1 = get_Mul_left(node);
822 ir_node *op2 = get_Mul_right(node);
823 ir_node *new_op1 = transform_node(env, op1);
824 ir_node *new_op2 = transform_node(env, op2);
825 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
826 ir_node *proj_EAX, *proj_EDX, *res;
829 res = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
830 set_ia32_commutative(res);
831 set_ia32_am_support(res, ia32_am_Source);
833 /* imediates are not supported, so no fold_immediate */
834 proj_EAX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX);
835 proj_EDX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX);
839 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
847 * Creates an ia32 Mul.
849 * @param env The transformation environment
850 * @return the created ia32 Mul node
852 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) {
853 ir_node *op1 = get_Mul_left(node);
854 ir_node *op2 = get_Mul_right(node);
855 ir_mode *mode = get_irn_mode(node);
857 if (mode_is_float(mode)) {
859 if (USE_SSE2(env->cg))
860 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul);
862 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul);
865 // for the lower 32bit of the result it doesn't matter whether we use
866 // signed or unsigned multiplication so we use IMul as it has fewer
868 return gen_binop(env, node, op1, op2, new_rd_ia32_IMul);
872 * Creates an ia32 Mulh.
873 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
874 * this result while Mul returns the lower 32 bit.
876 * @param env The transformation environment
877 * @return the created ia32 Mulh node
879 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) {
880 ir_graph *irg = env->irg;
881 dbg_info *dbg = get_irn_dbg_info(node);
882 ir_node *block = transform_node(env, get_nodes_block(node));
883 ir_node *op1 = get_irn_n(node, 0);
884 ir_node *op2 = get_irn_n(node, 1);
885 ir_node *new_op1 = transform_node(env, op1);
886 ir_node *new_op2 = transform_node(env, op2);
887 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
888 ir_node *proj_EAX, *proj_EDX, *res;
889 ir_mode *mode = get_irn_mode(node);
892 assert(!mode_is_float(mode) && "Mulh with float not supported");
893 if(mode_is_signed(mode)) {
894 res = new_rd_ia32_IMul1OP(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
896 res = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
899 set_ia32_commutative(res);
900 set_ia32_am_support(res, ia32_am_Source);
902 set_ia32_am_support(res, ia32_am_Source);
904 proj_EAX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX);
905 proj_EDX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX);
909 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
917 * Creates an ia32 And.
919 * @param env The transformation environment
920 * @return The created ia32 And node
922 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *node) {
923 ir_node *op1 = get_And_left(node);
924 ir_node *op2 = get_And_right(node);
925 ir_mode *mode = get_irn_mode(node);
927 assert (! mode_is_float(mode));
928 return gen_binop(env, node, op1, op2, new_rd_ia32_And);
934 * Creates an ia32 Or.
936 * @param env The transformation environment
937 * @return The created ia32 Or node
939 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *node) {
940 ir_node *op1 = get_Or_left(node);
941 ir_node *op2 = get_Or_right(node);
942 ir_mode *mode = get_irn_mode(node);
944 assert (! mode_is_float(mode));
945 return gen_binop(env, node, op1, op2, new_rd_ia32_Or);
951 * Creates an ia32 Eor.
953 * @param env The transformation environment
954 * @return The created ia32 Eor node
956 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *node) {
957 ir_node *op1 = get_Eor_left(node);
958 ir_node *op2 = get_Eor_right(node);
959 ir_mode *mode = get_irn_mode(node);
961 assert(! mode_is_float(mode));
962 return gen_binop(env, node, op1, op2, new_rd_ia32_Xor);
968 * Creates an ia32 Max.
970 * @param env The transformation environment
971 * @return the created ia32 Max node
973 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *node) {
974 ir_graph *irg = env->irg;
976 ir_mode *mode = get_irn_mode(node);
977 dbg_info *dbg = get_irn_dbg_info(node);
978 ir_node *block = transform_node(env, get_nodes_block(node));
979 ir_node *op1 = get_irn_n(node, 0);
980 ir_node *op2 = get_irn_n(node, 1);
981 ir_node *new_op1 = transform_node(env, op1);
982 ir_node *new_op2 = transform_node(env, op2);
983 ir_mode *op_mode = get_irn_mode(op1);
985 assert(get_mode_size_bits(mode) == 32);
987 if (mode_is_float(mode)) {
989 if (USE_SSE2(env->cg))
990 new_op = gen_binop_float(env, node, new_op1, new_op2, new_rd_ia32_xMax);
996 long pnc = pn_Cmp_Gt;
997 if(!mode_is_signed(op_mode)) {
998 pnc |= ia32_pn_Cmp_Unsigned;
1000 new_op = new_rd_ia32_CmpCMov(dbg, irg, block, new_op1, new_op2, new_op1, new_op2);
1001 set_ia32_pncode(new_op, pnc);
1002 set_ia32_am_support(new_op, ia32_am_None);
1004 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1010 * Creates an ia32 Min.
1012 * @param env The transformation environment
1013 * @return the created ia32 Min node
1015 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *node) {
1016 ir_graph *irg = env->irg;
1018 ir_mode *mode = get_irn_mode(node);
1019 dbg_info *dbg = get_irn_dbg_info(node);
1020 ir_node *block = transform_node(env, get_nodes_block(node));
1021 ir_node *op1 = get_irn_n(node, 0);
1022 ir_node *op2 = get_irn_n(node, 1);
1023 ir_node *new_op1 = transform_node(env, op1);
1024 ir_node *new_op2 = transform_node(env, op2);
1025 ir_mode *op_mode = get_irn_mode(op1);
1027 assert(get_mode_size_bits(mode) == 32);
1029 if (mode_is_float(mode)) {
1031 if (USE_SSE2(env->cg))
1032 new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMin);
1038 long pnc = pn_Cmp_Lt;
1039 if(!mode_is_signed(op_mode)) {
1040 pnc |= ia32_pn_Cmp_Unsigned;
1042 new_op = new_rd_ia32_CmpCMov(dbg, irg, block, new_op1, new_op2, new_op1, new_op2);
1043 set_ia32_pncode(new_op, pnc);
1044 set_ia32_am_support(new_op, ia32_am_None);
1046 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1053 * Creates an ia32 Sub.
1055 * @param env The transformation environment
1056 * @return The created ia32 Sub node
1058 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) {
1059 ir_node *new_op = NULL;
1060 ir_graph *irg = env->irg;
1061 dbg_info *dbg = get_irn_dbg_info(node);
1062 ir_mode *mode = get_irn_mode(node);
1063 ir_node *block = transform_node(env, get_nodes_block(node));
1064 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1065 ir_node *nomem = new_NoMem();
1066 ir_node *op1 = get_Sub_left(node);
1067 ir_node *op2 = get_Sub_right(node);
1068 ir_node *new_op1 = transform_node(env, op1);
1069 ir_node *new_op2 = transform_node(env, op2);
1070 ir_node *expr_op, *imm_op;
1072 /* Check if immediate optimization is on and */
1073 /* if it's an operation with immediate. */
1074 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1075 expr_op = get_expr_op(new_op1, new_op2);
1077 assert((expr_op || imm_op) && "invalid operands");
1079 if (mode_is_float(mode)) {
1081 if (USE_SSE2(env->cg))
1082 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xSub);
1084 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfsub);
1089 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1090 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1092 /* No expr_op means, that we have two const - one symconst and */
1093 /* one tarval or another symconst - because this case is not */
1094 /* covered by constant folding */
1095 /* We need to check for: */
1096 /* 1) symconst - const -> becomes a LEA */
1097 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1098 /* linker doesn't support two symconsts */
1099 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1100 /* this is the 2nd case */
1101 new_op = new_rd_ia32_Lea(dbg, irg, block, new_op1, noreg);
1102 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1103 set_ia32_am_sc_sign(new_op);
1104 set_ia32_am_flavour(new_op, ia32_am_OB);
1106 DBG_OPT_LEA3(op1, op2, node, new_op);
1107 } else if (tp1 == ia32_ImmSymConst) {
1108 tarval *tv = get_ia32_Immop_tarval(new_op2);
1109 long offs = get_tarval_long(tv);
1111 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
1112 DBG_OPT_LEA3(op1, op2, node, new_op);
1114 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1115 add_ia32_am_offs_int(new_op, -offs);
1116 set_ia32_am_flavour(new_op, ia32_am_O);
1117 set_ia32_am_support(new_op, ia32_am_Source);
1118 set_ia32_op_type(new_op, ia32_AddrModeS);
1119 } else if (tp2 == ia32_ImmSymConst) {
1120 tarval *tv = get_ia32_Immop_tarval(new_op1);
1121 long offs = get_tarval_long(tv);
1123 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
1124 DBG_OPT_LEA3(op1, op2, node, new_op);
1126 add_ia32_am_offs_int(new_op, offs);
1127 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1128 set_ia32_am_sc_sign(new_op);
1129 set_ia32_am_flavour(new_op, ia32_am_O);
1130 set_ia32_am_support(new_op, ia32_am_Source);
1131 set_ia32_op_type(new_op, ia32_AddrModeS);
1133 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1134 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1135 tarval *restv = tarval_sub(tv1, tv2);
1137 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1139 new_op = new_rd_ia32_Const(dbg, irg, block);
1140 set_ia32_Const_tarval(new_op, restv);
1141 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1144 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1146 } else if (imm_op) {
1147 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1148 tarval_classification_t class_tv, class_negtv;
1149 tarval *tv = get_ia32_Immop_tarval(imm_op);
1151 /* optimize tarvals */
1152 class_tv = classify_tarval(tv);
1153 class_negtv = classify_tarval(tarval_neg(tv));
1155 if (class_tv == TV_CLASSIFY_ONE) {
1156 DB((env->mod, LEVEL_2, "Sub(1) to Dec ... "));
1157 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
1158 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1160 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1161 DB((env->mod, LEVEL_2, "Sub(-1) to Inc ... "));
1162 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
1163 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1169 /* This is a normal sub */
1170 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1172 /* set AM support */
1173 set_ia32_am_support(new_op, ia32_am_Full);
1175 fold_immediate(env, new_op, 2, 3);
1177 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1185 * Generates an ia32 DivMod with additional infrastructure for the
1186 * register allocator if needed.
1188 * @param env The transformation environment
1189 * @param dividend -no comment- :)
1190 * @param divisor -no comment- :)
1191 * @param dm_flav flavour_Div/Mod/DivMod
1192 * @return The created ia32 DivMod node
1194 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *node,
1195 ir_node *dividend, ir_node *divisor,
1196 ia32_op_flavour_t dm_flav) {
1197 ir_graph *irg = env->irg;
1198 dbg_info *dbg = get_irn_dbg_info(node);
1199 ir_mode *mode = get_irn_mode(node);
1200 ir_node *block = transform_node(env, get_nodes_block(node));
1201 ir_node *res, *proj_div, *proj_mod;
1202 ir_node *edx_node, *cltd;
1203 ir_node *in_keep[1];
1204 ir_node *mem, *new_mem;
1205 ir_node *projs[pn_DivMod_max];
1206 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1207 ir_node *new_dividend = transform_node(env, dividend);
1208 ir_node *new_divisor = transform_node(env, divisor);
1210 ia32_collect_Projs(node, projs, pn_DivMod_max);
1214 mem = get_Div_mem(node);
1215 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Div_res));
1218 mem = get_Mod_mem(node);
1219 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Mod_res));
1221 case flavour_DivMod:
1222 mem = get_DivMod_mem(node);
1223 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1224 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1225 mode = proj_div ? get_irn_mode(proj_div) : get_irn_mode(proj_mod);
1230 new_mem = transform_node(env, mem);
1232 if (mode_is_signed(mode)) {
1233 /* in signed mode, we need to sign extend the dividend */
1234 cltd = new_rd_ia32_Cltd(dbg, irg, block, new_dividend);
1235 new_dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1236 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1238 edx_node = new_rd_ia32_Const(dbg, irg, block);
1239 add_irn_dep(edx_node, be_abi_get_start_barrier(env->cg->birg->abi));
1240 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1243 if(mode_is_signed(mode)) {
1244 res = new_rd_ia32_IDiv(dbg, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1246 res = new_rd_ia32_Div(dbg, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1249 /* Matze: code can't handle this at the moment... */
1251 /* set AM support */
1252 set_ia32_am_support(res, ia32_am_Source);
1255 set_ia32_n_res(res, 2);
1257 /* Only one proj is used -> We must add a second proj and */
1258 /* connect this one to a Keep node to eat up the second */
1259 /* destroyed register. */
1260 /* We also renumber the Firm projs into ia32 projs. */
1262 switch (get_irn_opcode(node)) {
1264 /* add Proj-Keep for mod res */
1265 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1266 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1269 /* add Proj-Keep for div res */
1270 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1271 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1274 /* check, which Proj-Keep, we need to add */
1275 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1276 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1278 if (proj_div && proj_mod) {
1279 /* nothing to be done */
1281 else if (! proj_div && ! proj_mod) {
1282 assert(0 && "Missing DivMod result proj");
1284 else if (! proj_div) {
1285 /* We have only mod result: add div res Proj-Keep */
1286 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1287 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1290 /* We have only div result: add mod res Proj-Keep */
1291 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1292 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1296 assert(0 && "Div, Mod, or DivMod expected.");
1300 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1307 * Wrapper for generate_DivMod. Sets flavour_Mod.
1309 * @param env The transformation environment
1311 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *node) {
1312 return generate_DivMod(env, node, get_Mod_left(node),
1313 get_Mod_right(node), flavour_Mod);
1317 * Wrapper for generate_DivMod. Sets flavour_Div.
1319 * @param env The transformation environment
1321 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *node) {
1322 return generate_DivMod(env, node, get_Div_left(node),
1323 get_Div_right(node), flavour_Div);
1327 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1329 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *node) {
1330 return generate_DivMod(env, node, get_DivMod_left(node),
1331 get_DivMod_right(node), flavour_DivMod);
1337 * Creates an ia32 floating Div.
1339 * @param env The transformation environment
1340 * @return The created ia32 xDiv node
1342 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *node) {
1343 ir_graph *irg = env->irg;
1344 dbg_info *dbg = get_irn_dbg_info(node);
1345 ir_node *block = transform_node(env, get_nodes_block(node));
1346 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1348 ir_node *nomem = new_rd_NoMem(env->irg);
1349 ir_node *op1 = get_Quot_left(node);
1350 ir_node *op2 = get_Quot_right(node);
1351 ir_node *new_op1 = transform_node(env, op1);
1352 ir_node *new_op2 = transform_node(env, op2);
1355 if (USE_SSE2(env->cg)) {
1356 ir_mode *mode = get_irn_mode(op1);
1357 if (is_ia32_xConst(new_op2)) {
1358 new_op = new_rd_ia32_xDiv(dbg, irg, block, noreg, noreg, new_op1, noreg, nomem);
1359 set_ia32_am_support(new_op, ia32_am_None);
1360 copy_ia32_Immop_attr(new_op, new_op2);
1362 new_op = new_rd_ia32_xDiv(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1363 // Matze: disabled for now, spillslot coalescer fails
1364 //set_ia32_am_support(new_op, ia32_am_Source);
1366 set_ia32_ls_mode(new_op, mode);
1368 new_op = new_rd_ia32_vfdiv(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1369 // Matze: disabled for now (spillslot coalescer fails)
1370 //set_ia32_am_support(new_op, ia32_am_Source);
1372 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1378 * Creates an ia32 Shl.
1380 * @param env The transformation environment
1381 * @return The created ia32 Shl node
1383 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *node) {
1384 return gen_shift_binop(env, node, get_Shl_left(node), get_Shl_right(node),
1391 * Creates an ia32 Shr.
1393 * @param env The transformation environment
1394 * @return The created ia32 Shr node
1396 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *node) {
1397 return gen_shift_binop(env, node, get_Shr_left(node),
1398 get_Shr_right(node), new_rd_ia32_Shr);
1404 * Creates an ia32 Sar.
1406 * @param env The transformation environment
1407 * @return The created ia32 Shrs node
1409 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) {
1410 return gen_shift_binop(env, node, get_Shrs_left(node),
1411 get_Shrs_right(node), new_rd_ia32_Sar);
1417 * Creates an ia32 RotL.
1419 * @param env The transformation environment
1420 * @param op1 The first operator
1421 * @param op2 The second operator
1422 * @return The created ia32 RotL node
1424 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node,
1425 ir_node *op1, ir_node *op2) {
1426 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Rol);
1432 * Creates an ia32 RotR.
1433 * NOTE: There is no RotR with immediate because this would always be a RotL
1434 * "imm-mode_size_bits" which can be pre-calculated.
1436 * @param env The transformation environment
1437 * @param op1 The first operator
1438 * @param op2 The second operator
1439 * @return The created ia32 RotR node
1441 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1,
1443 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Ror);
1449 * Creates an ia32 RotR or RotL (depending on the found pattern).
1451 * @param env The transformation environment
1452 * @return The created ia32 RotL or RotR node
1454 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) {
1455 ir_node *rotate = NULL;
1456 ir_node *op1 = get_Rot_left(node);
1457 ir_node *op2 = get_Rot_right(node);
1459 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1460 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1461 that means we can create a RotR instead of an Add and a RotL */
1463 if (get_irn_op(op2) == op_Add) {
1465 ir_node *left = get_Add_left(add);
1466 ir_node *right = get_Add_right(add);
1467 if (is_Const(right)) {
1468 tarval *tv = get_Const_tarval(right);
1469 ir_mode *mode = get_irn_mode(node);
1470 long bits = get_mode_size_bits(mode);
1472 if (get_irn_op(left) == op_Minus &&
1473 tarval_is_long(tv) &&
1474 get_tarval_long(tv) == bits)
1476 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1477 rotate = gen_RotR(env, node, op1, get_Minus_op(left));
1482 if (rotate == NULL) {
1483 rotate = gen_RotL(env, node, op1, op2);
1492 * Transforms a Minus node.
1494 * @param env The transformation environment
1495 * @param op The Minus operand
1496 * @return The created ia32 Minus node
1498 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *node, ir_node *op) {
1501 ir_graph *irg = env->irg;
1502 dbg_info *dbg = get_irn_dbg_info(node);
1503 ir_node *block = transform_node(env, get_nodes_block(node));
1504 ir_mode *mode = get_irn_mode(node);
1507 if (mode_is_float(mode)) {
1508 ir_node *new_op = transform_node(env, op);
1510 if (USE_SSE2(env->cg)) {
1511 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1512 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1513 ir_node *nomem = new_rd_NoMem(irg);
1515 res = new_rd_ia32_xXor(dbg, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1517 size = get_mode_size_bits(mode);
1518 name = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1520 set_ia32_am_sc(res, name);
1521 set_ia32_op_type(res, ia32_AddrModeS);
1522 set_ia32_ls_mode(res, mode);
1524 res = new_rd_ia32_vfchs(dbg, irg, block, new_op);
1527 res = gen_unop(env, node, op, new_rd_ia32_Neg);
1530 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1536 * Transforms a Minus node.
1538 * @param env The transformation environment
1539 * @return The created ia32 Minus node
1541 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *node) {
1542 return gen_Minus_ex(env, node, get_Minus_op(node));
1547 * Transforms a Not node.
1549 * @param env The transformation environment
1550 * @return The created ia32 Not node
1552 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *node) {
1553 ir_mode *mode = get_irn_mode(node);
1554 ir_node *op = get_Not_op(node);
1556 assert (! mode_is_float(mode));
1557 return gen_unop(env, node, op, new_rd_ia32_Not);
1563 * Transforms an Abs node.
1565 * @param env The transformation environment
1566 * @return The created ia32 Abs node
1568 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *node) {
1569 ir_node *res, *p_eax, *p_edx;
1570 ir_graph *irg = env->irg;
1571 dbg_info *dbg = get_irn_dbg_info(node);
1572 ir_node *block = transform_node(env, get_nodes_block(node));
1573 ir_mode *mode = get_irn_mode(node);
1574 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1575 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1576 ir_node *nomem = new_NoMem();
1577 ir_node *op = get_Abs_op(node);
1578 ir_node *new_op = transform_node(env, op);
1582 if (mode_is_float(mode)) {
1584 if (USE_SSE2(env->cg)) {
1585 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1587 size = get_mode_size_bits(mode);
1588 name = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1590 set_ia32_am_sc(res, name);
1592 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1594 set_ia32_op_type(res, ia32_AddrModeS);
1595 set_ia32_ls_mode(res, mode);
1598 res = new_rd_ia32_vfabs(dbg, irg, block, new_op);
1599 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1603 res = new_rd_ia32_Cltd(dbg, irg, block, new_op);
1604 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1606 p_eax = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX);
1607 p_edx = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX);
1609 res = new_rd_ia32_Xor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1610 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1612 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1613 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1622 * Transforms a Load.
1624 * @param env The transformation environment
1625 * @return the created ia32 Load node
1627 static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) {
1628 ir_graph *irg = env->irg;
1629 dbg_info *dbg = get_irn_dbg_info(node);
1630 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1631 ir_mode *mode = get_Load_mode(node);
1632 ir_node *block = transform_node(env, get_nodes_block(node));
1633 ir_node *ptr = get_Load_ptr(node);
1634 ir_node *new_ptr = transform_node(env, ptr);
1635 ir_node *lptr = new_ptr;
1636 ir_node *mem = get_Load_mem(node);
1637 ir_node *new_mem = transform_node(env, mem);
1640 ia32_am_flavour_t am_flav = ia32_am_B;
1641 ir_node *projs[pn_Load_max];
1643 ia32_collect_Projs(node, projs, pn_Load_max);
1646 check for special case: the loaded value might not be used (optimized, volatile, ...)
1647 we add a Proj + Keep for volatile loads and ignore all other cases
1649 if (! be_get_Proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1650 /* add a result proj and a Keep to produce a pseudo use */
1651 ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res);
1652 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), irg, block, 1, &proj);
1655 /* address might be a constant (symconst or absolute address) */
1656 if (is_ia32_Const(new_ptr)) {
1661 if (mode_is_float(mode)) {
1663 if (USE_SSE2(env->cg)) {
1664 new_op = new_rd_ia32_xLoad(dbg, irg, block, lptr, noreg, new_mem);
1666 new_op = new_rd_ia32_vfld(dbg, irg, block, lptr, noreg, new_mem);
1669 new_op = new_rd_ia32_Load(dbg, irg, block, lptr, noreg, new_mem);
1672 /* base is a constant address */
1674 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1675 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1676 am_flav = ia32_am_N;
1678 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1679 long offs = get_tarval_long(tv);
1681 add_ia32_am_offs_int(new_op, offs);
1682 am_flav = ia32_am_O;
1686 set_ia32_am_support(new_op, ia32_am_Source);
1687 set_ia32_op_type(new_op, ia32_AddrModeS);
1688 set_ia32_am_flavour(new_op, am_flav);
1689 set_ia32_ls_mode(new_op, mode);
1691 /* make sure we are scheduled behind the intial IncSP/Barrier
1692 * to avoid spills being placed before it
1694 if(block == get_irg_start_block(irg)) {
1695 add_irn_dep(new_op, get_irg_frame(irg));
1698 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1706 * Transforms a Store.
1708 * @param env The transformation environment
1709 * @return the created ia32 Store node
1711 static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) {
1712 ir_graph *irg = env->irg;
1713 dbg_info *dbg = get_irn_dbg_info(node);
1714 ir_node *block = transform_node(env, get_nodes_block(node));
1715 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1716 ir_node *ptr = get_Store_ptr(node);
1717 ir_node *new_ptr = transform_node(env, ptr);
1718 ir_node *sptr = new_ptr;
1719 ir_node *val = get_Store_value(node);
1720 ir_node *new_val = transform_node(env, val);
1721 ir_node *mem = get_Store_mem(node);
1722 ir_node *new_mem = transform_node(env, mem);
1723 ir_mode *mode = get_irn_mode(val);
1724 ir_node *sval = new_val;
1727 ia32_am_flavour_t am_flav = ia32_am_B;
1729 if (is_ia32_Const(new_val)) {
1730 assert(!mode_is_float(mode));
1734 /* address might be a constant (symconst or absolute address) */
1735 if (is_ia32_Const(new_ptr)) {
1740 if (mode_is_float(mode)) {
1742 if (USE_SSE2(env->cg)) {
1743 new_op = new_rd_ia32_xStore(dbg, irg, block, sptr, noreg, sval, new_mem);
1745 new_op = new_rd_ia32_vfst(dbg, irg, block, sptr, noreg, sval, new_mem);
1747 } else if (get_mode_size_bits(mode) == 8) {
1748 new_op = new_rd_ia32_Store8Bit(dbg, irg, block, sptr, noreg, sval, new_mem);
1750 new_op = new_rd_ia32_Store(dbg, irg, block, sptr, noreg, sval, new_mem);
1753 /* stored const is an immediate value */
1754 if (is_ia32_Const(new_val)) {
1755 assert(!mode_is_float(mode));
1756 copy_ia32_Immop_attr(new_op, new_val);
1759 /* base is an constant address */
1761 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1762 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1763 am_flav = ia32_am_N;
1765 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1766 long offs = get_tarval_long(tv);
1768 add_ia32_am_offs_int(new_op, offs);
1769 am_flav = ia32_am_O;
1773 set_ia32_am_support(new_op, ia32_am_Dest);
1774 set_ia32_op_type(new_op, ia32_AddrModeD);
1775 set_ia32_am_flavour(new_op, am_flav);
1776 set_ia32_ls_mode(new_op, mode);
1778 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1786 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1788 * @param env The transformation environment
1789 * @return The transformed node.
1791 static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) {
1792 ir_graph *irg = env->irg;
1793 dbg_info *dbg = get_irn_dbg_info(node);
1794 ir_node *block = transform_node(env, get_nodes_block(node));
1795 ir_node *sel = get_Cond_selector(node);
1796 ir_mode *sel_mode = get_irn_mode(sel);
1797 ir_node *res = NULL;
1798 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1799 ir_node *cnst, *expr;
1801 if (is_Proj(sel) && sel_mode == mode_b) {
1802 ir_node *nomem = new_NoMem();
1803 ir_node *pred = get_Proj_pred(sel);
1804 ir_node *cmp_a = get_Cmp_left(pred);
1805 ir_node *new_cmp_a = transform_node(env, cmp_a);
1806 ir_node *cmp_b = get_Cmp_right(pred);
1807 ir_node *new_cmp_b = transform_node(env, cmp_b);
1808 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1810 int pnc = get_Proj_proj(sel);
1811 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1812 pnc |= ia32_pn_Cmp_Unsigned;
1815 /* check if we can use a CondJmp with immediate */
1816 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1817 expr = get_expr_op(new_cmp_a, new_cmp_b);
1819 if (cnst != NULL && expr != NULL) {
1820 /* immop has to be the right operand, we might need to flip pnc */
1821 if(cnst != new_cmp_b) {
1822 pnc = get_inversed_pnc(pnc);
1825 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1826 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1827 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1829 /* a Cmp A =/!= 0 */
1830 ir_node *op1 = expr;
1831 ir_node *op2 = expr;
1834 /* check, if expr is an only once used And operation */
1835 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1836 op1 = get_irn_n(expr, 2);
1837 op2 = get_irn_n(expr, 3);
1839 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1841 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1842 set_ia32_pncode(res, pnc);
1845 copy_ia32_Immop_attr(res, expr);
1848 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1853 if (mode_is_float(cmp_mode)) {
1855 if (USE_SSE2(env->cg)) {
1856 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1857 set_ia32_ls_mode(res, cmp_mode);
1863 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1865 copy_ia32_Immop_attr(res, cnst);
1868 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1870 if (mode_is_float(cmp_mode)) {
1872 if (USE_SSE2(env->cg)) {
1873 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1874 set_ia32_ls_mode(res, cmp_mode);
1877 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1878 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1879 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1883 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1884 set_ia32_commutative(res);
1888 set_ia32_pncode(res, pnc);
1889 // Matze: disabled for now, because the default collect_spills_walker
1890 // is not able to detect the mode of the spilled value
1891 // moreover, the lea optimize phase freely exchanges left/right
1892 // without updating the pnc
1893 //set_ia32_am_support(res, ia32_am_Source);
1896 /* determine the smallest switch case value */
1897 int switch_min = INT_MAX;
1898 const ir_edge_t *edge;
1899 ir_node *new_sel = transform_node(env, sel);
1901 foreach_out_edge(node, edge) {
1902 int pn = get_Proj_proj(get_edge_src_irn(edge));
1903 switch_min = pn < switch_min ? pn : switch_min;
1907 /* if smallest switch case is not 0 we need an additional sub */
1908 res = new_rd_ia32_Lea(dbg, irg, block, new_sel, noreg);
1909 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1910 add_ia32_am_offs_int(res, -switch_min);
1911 set_ia32_am_flavour(res, ia32_am_OB);
1912 set_ia32_am_support(res, ia32_am_Source);
1913 set_ia32_op_type(res, ia32_AddrModeS);
1916 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : new_sel, mode_T);
1917 set_ia32_pncode(res, get_Cond_defaultProj(node));
1920 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1927 * Transforms a CopyB node.
1929 * @param env The transformation environment
1930 * @return The transformed node.
1932 static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) {
1933 ir_node *res = NULL;
1934 ir_graph *irg = env->irg;
1935 dbg_info *dbg = get_irn_dbg_info(node);
1936 ir_node *block = transform_node(env, get_nodes_block(node));
1937 ir_node *src = get_CopyB_src(node);
1938 ir_node *new_src = transform_node(env, src);
1939 ir_node *dst = get_CopyB_dst(node);
1940 ir_node *new_dst = transform_node(env, dst);
1941 ir_node *mem = get_CopyB_mem(node);
1942 ir_node *new_mem = transform_node(env, mem);
1943 int size = get_type_size_bytes(get_CopyB_type(node));
1944 ir_mode *dst_mode = get_irn_mode(dst);
1945 ir_mode *src_mode = get_irn_mode(src);
1949 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1950 /* then we need the size explicitly in ECX. */
1951 if (size >= 32 * 4) {
1952 rem = size & 0x3; /* size % 4 */
1955 res = new_rd_ia32_Const(dbg, irg, block);
1956 add_irn_dep(res, be_abi_get_start_barrier(env->cg->birg->abi));
1957 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1959 res = new_rd_ia32_CopyB(dbg, irg, block, new_dst, new_src, res, new_mem);
1960 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1962 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1963 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1964 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1965 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1966 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1969 res = new_rd_ia32_CopyB_i(dbg, irg, block, new_dst, new_src, new_mem);
1970 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1972 /* ok: now attach Proj's because movsd will destroy esi and edi */
1973 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1974 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1975 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1978 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1986 * Transforms a Mux node into CMov.
1988 * @param env The transformation environment
1989 * @return The transformed node.
1991 static ir_node *gen_Mux(ia32_transform_env_t *env, ir_node *node) {
1992 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1993 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1995 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2001 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
2002 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
2003 ir_node *psi_default);
2006 * Transforms a Psi node into CMov.
2008 * @param env The transformation environment
2009 * @return The transformed node.
2011 static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) {
2012 ia32_code_gen_t *cg = env->cg;
2013 ir_graph *irg = env->irg;
2014 dbg_info *dbg = get_irn_dbg_info(node);
2015 ir_mode *mode = get_irn_mode(node);
2016 ir_node *block = transform_node(env, get_nodes_block(node));
2017 ir_node *cmp_proj = get_Mux_sel(node);
2018 ir_node *psi_true = get_Psi_val(node, 0);
2019 ir_node *psi_default = get_Psi_default(node);
2020 ir_node *new_psi_true = transform_node(env, psi_true);
2021 ir_node *new_psi_default = transform_node(env, psi_default);
2022 ir_node *noreg = ia32_new_NoReg_gp(cg);
2023 ir_node *nomem = new_rd_NoMem(irg);
2024 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
2025 ir_node *new_cmp_a, *new_cmp_b;
2029 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
2031 cmp = get_Proj_pred(cmp_proj);
2032 cmp_a = get_Cmp_left(cmp);
2033 cmp_b = get_Cmp_right(cmp);
2034 cmp_mode = get_irn_mode(cmp_a);
2035 new_cmp_a = transform_node(env, cmp_a);
2036 new_cmp_b = transform_node(env, cmp_b);
2038 pnc = get_Proj_proj(cmp_proj);
2039 if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2040 pnc |= ia32_pn_Cmp_Unsigned;
2043 if (mode_is_float(mode)) {
2044 /* floating point psi */
2047 /* 1st case: compare operands are float too */
2049 /* psi(cmp(a, b), t, f) can be done as: */
2050 /* tmp = cmp a, b */
2051 /* tmp2 = t and tmp */
2052 /* tmp3 = f and not tmp */
2053 /* res = tmp2 or tmp3 */
2055 /* in case the compare operands are int, we move them into xmm register */
2056 if (! mode_is_float(get_irn_mode(cmp_a))) {
2057 new_cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_a, node, mode_E);
2058 new_cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_b, node, mode_E);
2060 pnc |= 8; /* transform integer compare to fp compare */
2063 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2064 set_ia32_pncode(new_op, pnc);
2065 set_ia32_am_support(new_op, ia32_am_Source);
2066 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2068 and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2069 set_ia32_am_support(and1, ia32_am_None);
2070 set_ia32_commutative(and1);
2071 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2073 and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2074 set_ia32_am_support(and2, ia32_am_None);
2075 set_ia32_commutative(and2);
2076 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2078 new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
2079 set_ia32_am_support(new_op, ia32_am_None);
2080 set_ia32_commutative(new_op);
2081 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2085 new_op = new_rd_ia32_vfCMov(dbg, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2086 set_ia32_pncode(new_op, pnc);
2087 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2092 construct_binop_func *set_func = NULL;
2093 cmov_func_t *cmov_func = NULL;
2095 if (mode_is_float(get_irn_mode(cmp_a))) {
2096 /* 1st case: compare operands are floats */
2101 set_func = new_rd_ia32_xCmpSet;
2102 cmov_func = new_rd_ia32_xCmpCMov;
2106 set_func = new_rd_ia32_vfCmpSet;
2107 cmov_func = new_rd_ia32_vfCmpCMov;
2110 pnc &= ~0x8; /* fp compare -> int compare */
2113 /* 2nd case: compare operand are integer too */
2114 set_func = new_rd_ia32_CmpSet;
2115 cmov_func = new_rd_ia32_CmpCMov;
2118 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2119 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2120 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2121 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2122 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, new_cmp_a);
2123 set_ia32_pncode(new_op, pnc);
2125 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2126 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2127 /* we invert condition and set default to 0 */
2128 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, new_cmp_a);
2129 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2132 /* otherwise: use CMOVcc */
2133 new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2134 set_ia32_pncode(new_op, pnc);
2137 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2140 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2141 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2142 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2143 set_ia32_pncode(new_op, pnc);
2144 set_ia32_am_support(new_op, ia32_am_Source);
2146 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2147 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2148 /* we invert condition and set default to 0 */
2149 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2150 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2151 set_ia32_am_support(new_op, ia32_am_Source);
2154 /* otherwise: use CMOVcc */
2155 new_op = cmov_func(dbg, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2156 set_ia32_pncode(new_op, pnc);
2157 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2167 * Following conversion rules apply:
2171 * 1) n bit -> m bit n > m (downscale)
2173 * 2) n bit -> m bit n == m (sign change)
2175 * 3) n bit -> m bit n < m (upscale)
2176 * a) source is signed: movsx
2177 * b) source is unsigned: and with lower bits sets
2181 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2185 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2189 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2190 * x87 is mode_E internally, conversions happen only at load and store
2191 * in non-strict semantic
2195 * Create a conversion from x87 state register to general purpose.
2197 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) {
2198 ia32_code_gen_t *cg = env->cg;
2199 ir_graph *irg = env->irg;
2200 dbg_info *dbg = get_irn_dbg_info(node);
2201 ir_node *block = transform_node(env, get_nodes_block(node));
2202 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2203 ir_node *op = get_Conv_op(node);
2204 ir_node *new_op = transform_node(env, op);
2205 ir_node *fist, *load;
2208 fist = new_rd_ia32_vfist(dbg, irg, block, get_irg_frame(irg), noreg, new_op, new_NoMem());
2210 set_ia32_use_frame(fist);
2211 set_ia32_am_support(fist, ia32_am_Dest);
2212 set_ia32_op_type(fist, ia32_AddrModeD);
2213 set_ia32_am_flavour(fist, ia32_am_B);
2214 set_ia32_ls_mode(fist, mode_Iu);
2215 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2218 load = new_rd_ia32_Load(dbg, irg, block, get_irg_frame(irg), noreg, fist);
2220 set_ia32_use_frame(load);
2221 set_ia32_am_support(load, ia32_am_Source);
2222 set_ia32_op_type(load, ia32_AddrModeS);
2223 set_ia32_am_flavour(load, ia32_am_B);
2224 set_ia32_ls_mode(load, mode_Iu);
2225 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2227 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2231 * Create a conversion from general purpose to x87 register
2233 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mode *src_mode) {
2234 ia32_code_gen_t *cg = env->cg;
2235 ir_graph *irg = env->irg;
2236 dbg_info *dbg = get_irn_dbg_info(node);
2237 ir_mode *mode = get_irn_mode(node);
2238 ir_node *block = transform_node(env, get_nodes_block(node));
2239 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2240 ir_node *nomem = new_NoMem();
2241 ir_node *op = get_Conv_op(node);
2242 ir_node *new_op = transform_node(env, op);
2243 ir_node *fild, *store;
2246 /* first convert to 32 bit if necessary */
2247 src_bits = get_mode_size_bits(src_mode);
2248 if (src_bits == 8) {
2249 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, new_op, nomem);
2250 set_ia32_am_support(new_op, ia32_am_Source);
2251 set_ia32_ls_mode(new_op, src_mode);
2252 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2253 } else if (src_bits < 32) {
2254 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, new_op, nomem);
2255 set_ia32_am_support(new_op, ia32_am_Source);
2256 set_ia32_ls_mode(new_op, src_mode);
2257 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2261 store = new_rd_ia32_Store(dbg, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2263 set_ia32_use_frame(store);
2264 set_ia32_am_support(store, ia32_am_Dest);
2265 set_ia32_op_type(store, ia32_AddrModeD);
2266 set_ia32_am_flavour(store, ia32_am_OB);
2267 set_ia32_ls_mode(store, mode_Iu);
2270 fild = new_rd_ia32_vfild(dbg, irg, block, get_irg_frame(irg), noreg, store);
2272 set_ia32_use_frame(fild);
2273 set_ia32_am_support(fild, ia32_am_Source);
2274 set_ia32_op_type(fild, ia32_AddrModeS);
2275 set_ia32_am_flavour(fild, ia32_am_OB);
2276 set_ia32_ls_mode(fild, mode);
2278 return new_r_Proj(irg, block, fild, mode_F, pn_ia32_vfild_res);
2282 * Transforms a Conv node.
2284 * @param env The transformation environment
2285 * @return The created ia32 Conv node
2287 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) {
2288 ir_graph *irg = env->irg;
2289 dbg_info *dbg = get_irn_dbg_info(node);
2290 ir_node *op = get_Conv_op(node);
2291 ir_mode *src_mode = get_irn_mode(op);
2292 ir_mode *tgt_mode = get_irn_mode(node);
2293 int src_bits = get_mode_size_bits(src_mode);
2294 int tgt_bits = get_mode_size_bits(tgt_mode);
2295 ir_node *block = transform_node(env, get_nodes_block(node));
2297 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2298 ir_node *nomem = new_rd_NoMem(irg);
2299 ir_node *new_op = transform_node(env, op);
2300 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
2302 if (src_mode == tgt_mode) {
2303 /* this should be optimized already, but who knows... */
2304 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2305 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
2309 if (mode_is_float(src_mode)) {
2310 /* we convert from float ... */
2311 if (mode_is_float(tgt_mode)) {
2313 if (USE_SSE2(env->cg)) {
2314 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
2315 res = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, new_op, nomem);
2316 set_ia32_ls_mode(res, tgt_mode);
2318 // Matze: TODO what about strict convs?
2319 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
2324 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
2325 if (USE_SSE2(env->cg)) {
2326 res = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, new_op, nomem);
2327 set_ia32_ls_mode(res, src_mode);
2329 return gen_x87_fp_to_gp(env, node);
2333 /* we convert from int ... */
2334 if (mode_is_float(tgt_mode)) {
2337 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
2338 if (USE_SSE2(env->cg)) {
2339 res = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, new_op, nomem);
2340 set_ia32_ls_mode(res, tgt_mode);
2341 if(src_bits == 32) {
2342 set_ia32_am_support(res, ia32_am_Source);
2345 return gen_x87_gp_to_fp(env, node, src_mode);
2349 ir_mode *smaller_mode;
2352 if (src_bits == tgt_bits) {
2353 DB((mod, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2357 if(src_bits < tgt_bits) {
2358 smaller_mode = src_mode;
2359 smaller_bits = src_bits;
2361 smaller_mode = tgt_mode;
2362 smaller_bits = tgt_bits;
2365 // The following is not correct, we can't change the mode,
2366 // maybe others are using the load too
2367 // better move this to a separate phase!
2370 if(is_Proj(new_op)) {
2371 /* load operations do already sign/zero extend, so we have
2372 * nothing left to do */
2373 ir_node *pred = get_Proj_pred(new_op);
2374 if(is_ia32_Load(pred)) {
2375 set_ia32_ls_mode(pred, smaller_mode);
2381 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2382 if (smaller_bits == 8) {
2383 res = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, new_op, nomem);
2384 set_ia32_ls_mode(res, smaller_mode);
2386 res = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, new_op, nomem);
2387 set_ia32_ls_mode(res, smaller_mode);
2389 set_ia32_am_support(res, ia32_am_Source);
2393 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2400 /********************************************
2403 * | |__ ___ _ __ ___ __| | ___ ___
2404 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2405 * | |_) | __/ | | | (_) | (_| | __/\__ \
2406 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2408 ********************************************/
2410 static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) {
2411 ir_node *new_op = NULL;
2412 ir_graph *irg = env->irg;
2413 dbg_info *dbg = get_irn_dbg_info(node);
2414 ir_node *block = transform_node(env, get_nodes_block(node));
2415 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2416 ir_node *nomem = new_rd_NoMem(env->irg);
2417 ir_node *ptr = get_irn_n(node, 0);
2418 ir_node *new_ptr = transform_node(env, ptr);
2419 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2420 ir_mode *load_mode = get_irn_mode(node);
2424 if (mode_is_float(load_mode)) {
2426 if (USE_SSE2(env->cg)) {
2427 new_op = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, nomem);
2428 pn_res = pn_ia32_xLoad_res;
2430 new_op = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, nomem);
2431 pn_res = pn_ia32_vfld_res;
2436 new_op = new_rd_ia32_Load(dbg, irg, block, new_ptr, noreg, nomem);
2437 proj_mode = mode_Iu;
2438 pn_res = pn_ia32_Load_res;
2441 set_ia32_frame_ent(new_op, ent);
2442 set_ia32_use_frame(new_op);
2444 set_ia32_am_support(new_op, ia32_am_Source);
2445 set_ia32_op_type(new_op, ia32_AddrModeS);
2446 set_ia32_am_flavour(new_op, ia32_am_B);
2447 set_ia32_ls_mode(new_op, load_mode);
2448 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2450 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2452 return new_rd_Proj(dbg, irg, block, new_op, proj_mode, pn_res);
2456 * Transforms a FrameAddr into an ia32 Add.
2458 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) {
2459 ir_graph *irg = env->irg;
2460 dbg_info *dbg = get_irn_dbg_info(node);
2461 ir_node *block = transform_node(env, get_nodes_block(node));
2462 ir_node *op = get_irn_n(node, 0);
2463 ir_node *new_op = transform_node(env, op);
2465 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2467 res = new_rd_ia32_Lea(dbg, irg, block, new_op, noreg);
2468 set_ia32_frame_ent(res, arch_get_frame_entity(env->cg->arch_env, node));
2469 set_ia32_am_support(res, ia32_am_Full);
2470 set_ia32_use_frame(res);
2471 set_ia32_am_flavour(res, ia32_am_OB);
2473 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2479 * Transforms a FrameLoad into an ia32 Load.
2481 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) {
2482 ir_node *new_op = NULL;
2483 ir_graph *irg = env->irg;
2484 dbg_info *dbg = get_irn_dbg_info(node);
2485 ir_node *block = transform_node(env, get_nodes_block(node));
2486 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2487 ir_node *mem = get_irn_n(node, 0);
2488 ir_node *ptr = get_irn_n(node, 1);
2489 ir_node *new_mem = transform_node(env, mem);
2490 ir_node *new_ptr = transform_node(env, ptr);
2491 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2492 ir_mode *mode = get_type_mode(get_entity_type(ent));
2493 ir_node *projs[pn_Load_max];
2495 ia32_collect_Projs(node, projs, pn_Load_max);
2497 if (mode_is_float(mode)) {
2499 if (USE_SSE2(env->cg)) {
2500 new_op = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, new_mem);
2503 new_op = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, new_mem);
2507 new_op = new_rd_ia32_Load(dbg, irg, block, new_ptr, noreg, new_mem);
2510 set_ia32_frame_ent(new_op, ent);
2511 set_ia32_use_frame(new_op);
2513 set_ia32_am_support(new_op, ia32_am_Source);
2514 set_ia32_op_type(new_op, ia32_AddrModeS);
2515 set_ia32_am_flavour(new_op, ia32_am_B);
2516 set_ia32_ls_mode(new_op, mode);
2518 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2525 * Transforms a FrameStore into an ia32 Store.
2527 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) {
2528 ir_node *new_op = NULL;
2529 ir_graph *irg = env->irg;
2530 dbg_info *dbg = get_irn_dbg_info(node);
2531 ir_node *block = transform_node(env, get_nodes_block(node));
2532 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2533 ir_node *mem = get_irn_n(node, 0);
2534 ir_node *ptr = get_irn_n(node, 1);
2535 ir_node *val = get_irn_n(node, 2);
2536 ir_node *new_mem = transform_node(env, mem);
2537 ir_node *new_ptr = transform_node(env, ptr);
2538 ir_node *new_val = transform_node(env, val);
2539 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2540 ir_mode *mode = get_irn_mode(val);
2542 if (mode_is_float(mode)) {
2544 if (USE_SSE2(env->cg)) {
2545 new_op = new_rd_ia32_xStore(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2548 new_op = new_rd_ia32_vfst(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2551 else if (get_mode_size_bits(mode) == 8) {
2552 new_op = new_rd_ia32_Store8Bit(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2555 new_op = new_rd_ia32_Store(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2558 set_ia32_frame_ent(new_op, ent);
2559 set_ia32_use_frame(new_op);
2561 set_ia32_am_support(new_op, ia32_am_Dest);
2562 set_ia32_op_type(new_op, ia32_AddrModeD);
2563 set_ia32_am_flavour(new_op, ia32_am_B);
2564 set_ia32_ls_mode(new_op, mode);
2566 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2572 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2574 static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
2575 ir_graph *irg = env->irg;
2578 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2579 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2580 ir_entity *ent = get_irg_entity(irg);
2581 ir_type *tp = get_entity_type(ent);
2584 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2585 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2587 int pn_ret_val, pn_ret_mem, arity, i;
2589 assert(ret_val != NULL);
2590 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env->cg)) {
2591 return duplicate_node(env, node);
2594 res_type = get_method_res_type(tp, 0);
2596 if (!is_Primitive_type(res_type)) {
2597 return duplicate_node(env, node);
2600 mode = get_type_mode(res_type);
2601 if (!mode_is_float(mode)) {
2602 return duplicate_node(env, node);
2605 assert(get_method_n_ress(tp) == 1);
2607 pn_ret_val = get_Proj_proj(ret_val);
2608 pn_ret_mem = get_Proj_proj(ret_mem);
2610 /* get the Barrier */
2611 barrier = get_Proj_pred(ret_val);
2613 /* get result input of the Barrier */
2614 ret_val = get_irn_n(barrier, pn_ret_val);
2615 new_ret_val = transform_node(env, ret_val);
2617 /* get memory input of the Barrier */
2618 ret_mem = get_irn_n(barrier, pn_ret_mem);
2619 new_ret_mem = transform_node(env, ret_mem);
2621 frame = get_irg_frame(irg);
2623 dbg = get_irn_dbg_info(barrier);
2624 block = transform_node(env, get_nodes_block(barrier));
2626 /* store xmm0 onto stack */
2627 sse_store = new_rd_ia32_xStoreSimple(dbg, irg, block, frame, new_ret_val, new_ret_mem);
2628 set_ia32_ls_mode(sse_store, mode);
2629 set_ia32_op_type(sse_store, ia32_AddrModeD);
2630 set_ia32_use_frame(sse_store);
2631 set_ia32_am_flavour(sse_store, ia32_am_B);
2632 set_ia32_am_support(sse_store, ia32_am_Dest);
2635 fld = new_rd_ia32_SetST0(dbg, irg, block, frame, sse_store);
2636 set_ia32_ls_mode(fld, mode);
2637 set_ia32_op_type(fld, ia32_AddrModeS);
2638 set_ia32_use_frame(fld);
2639 set_ia32_am_flavour(fld, ia32_am_B);
2640 set_ia32_am_support(fld, ia32_am_Source);
2642 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
2643 fld = new_r_Proj(irg, block, fld, mode_E, pn_ia32_SetST0_res);
2644 arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2646 /* create a new barrier */
2647 arity = get_irn_arity(barrier);
2648 in = alloca(arity * sizeof(in[0]));
2649 for(i = 0; i < arity; ++i) {
2651 if(i == pn_ret_val) {
2653 } else if(i == pn_ret_mem) {
2656 ir_node *in = get_irn_n(barrier, i);
2657 new_in = transform_node(env, in);
2662 new_barrier = new_ir_node(dbg, irg, block,
2663 get_irn_op(barrier), get_irn_mode(barrier),
2665 copy_node_attr(barrier, new_barrier);
2666 duplicate_deps(env, barrier, new_barrier);
2667 set_new_node(barrier, new_barrier);
2668 mark_irn_visited(barrier);
2670 /* transform normally */
2671 return duplicate_node(env, node);
2675 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2677 static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
2679 ir_graph *irg = env->irg;
2680 dbg_info *dbg = get_irn_dbg_info(node);
2681 ir_node *block = transform_node(env, get_nodes_block(node));
2682 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
2683 ir_node *new_sz = transform_node(env, sz);
2684 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
2685 ir_node *new_sp = transform_node(env, sp);
2686 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2687 ir_node *nomem = new_NoMem();
2689 /* ia32 stack grows in reverse direction, make a SubSP */
2690 new_op = new_rd_ia32_SubSP(dbg, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2691 set_ia32_am_support(new_op, ia32_am_Source);
2692 fold_immediate(env, new_op, 2, 3);
2694 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2700 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
2702 static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
2704 ir_graph *irg = env->irg;
2705 dbg_info *dbg = get_irn_dbg_info(node);
2706 ir_node *block = transform_node(env, get_nodes_block(node));
2707 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
2708 ir_node *new_sz = transform_node(env, sz);
2709 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
2710 ir_node *new_sp = transform_node(env, sp);
2711 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2712 ir_node *nomem = new_NoMem();
2714 /* ia32 stack grows in reverse direction, make an AddSP */
2715 new_op = new_rd_ia32_AddSP(dbg, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2716 set_ia32_am_support(new_op, ia32_am_Source);
2717 fold_immediate(env, new_op, 2, 3);
2719 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2725 * This function just sets the register for the Unknown node
2726 * as this is not done during register allocation because Unknown
2727 * is an "ignore" node.
2729 static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) {
2730 ir_mode *mode = get_irn_mode(node);
2732 if (mode_is_float(mode)) {
2733 if (USE_SSE2(env->cg))
2734 return ia32_new_Unknown_xmm(env->cg);
2736 return ia32_new_Unknown_vfp(env->cg);
2737 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
2738 return ia32_new_Unknown_gp(env->cg);
2740 assert(0 && "unsupported Unknown-Mode");
2747 * Change some phi modes
2749 static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
2750 ir_graph *irg = env->irg;
2751 dbg_info *dbg = get_irn_dbg_info(node);
2752 ir_mode *mode = get_irn_mode(node);
2753 ir_node *block = transform_node(env, get_nodes_block(node));
2757 if(mode_is_int(mode) || mode_is_reference(mode)) {
2758 // we shouldn't have any 64bit stuff around anymore
2759 assert(get_mode_size_bits(mode) <= 32);
2760 // all integer operations are on 32bit registers now
2762 } else if(mode_is_float(mode)) {
2763 assert(mode == mode_D || mode == mode_F);
2764 // all float operations are on mode_E registers
2768 /* phi nodes allow loops, so we use the old arguments for now
2769 * and fix this later */
2770 phi = new_ir_node(dbg, irg, block, op_Phi, mode, get_irn_arity(node),
2771 get_irn_in(node) + 1);
2772 copy_node_attr(node, phi);
2773 duplicate_deps(env, node, phi);
2775 set_new_node(node, phi);
2777 /* put the preds in the worklist */
2778 arity = get_irn_arity(node);
2779 for(i = 0; i < arity; ++i) {
2780 ir_node *pred = get_irn_n(node, i);
2781 pdeq_putr(env->worklist, pred);
2787 /**********************************************************************
2790 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2791 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2792 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2793 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2795 **********************************************************************/
2797 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2799 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2802 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2803 ir_node *val, ir_node *mem);
2806 * Transforms a lowered Load into a "real" one.
2808 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) {
2809 ir_graph *irg = env->irg;
2810 dbg_info *dbg = get_irn_dbg_info(node);
2811 ir_node *block = transform_node(env, get_nodes_block(node));
2812 ir_mode *mode = get_ia32_ls_mode(node);
2814 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2815 ir_node *ptr = get_irn_n(node, 0);
2816 ir_node *mem = get_irn_n(node, 1);
2817 ir_node *new_ptr = transform_node(env, ptr);
2818 ir_node *new_mem = transform_node(env, mem);
2821 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2822 lowering we have x87 nodes, so we need to enforce simulation.
2824 if (mode_is_float(mode)) {
2826 if (fp_unit == fp_x87)
2830 new_op = func(dbg, irg, block, new_ptr, noreg, new_mem);
2832 set_ia32_am_support(new_op, ia32_am_Source);
2833 set_ia32_op_type(new_op, ia32_AddrModeS);
2834 set_ia32_am_flavour(new_op, ia32_am_OB);
2835 set_ia32_am_offs_int(new_op, 0);
2836 set_ia32_am_scale(new_op, 1);
2837 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
2838 if(is_ia32_am_sc_sign(node))
2839 set_ia32_am_sc_sign(new_op);
2840 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
2841 if(is_ia32_use_frame(node)) {
2842 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2843 set_ia32_use_frame(new_op);
2846 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2852 * Transforms a lowered Store into a "real" one.
2854 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) {
2855 ir_graph *irg = env->irg;
2856 dbg_info *dbg = get_irn_dbg_info(node);
2857 ir_node *block = transform_node(env, get_nodes_block(node));
2858 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2859 ir_mode *mode = get_ia32_ls_mode(node);
2862 ia32_am_flavour_t am_flav = ia32_B;
2863 ir_node *ptr = get_irn_n(node, 0);
2864 ir_node *val = get_irn_n(node, 1);
2865 ir_node *mem = get_irn_n(node, 2);
2866 ir_node *new_ptr = transform_node(env, ptr);
2867 ir_node *new_val = transform_node(env, val);
2868 ir_node *new_mem = transform_node(env, mem);
2871 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2872 lowering we have x87 nodes, so we need to enforce simulation.
2874 if (mode_is_float(mode)) {
2876 if (fp_unit == fp_x87)
2880 new_op = func(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2882 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
2884 add_ia32_am_offs_int(new_op, am_offs);
2887 set_ia32_am_support(new_op, ia32_am_Dest);
2888 set_ia32_op_type(new_op, ia32_AddrModeD);
2889 set_ia32_am_flavour(new_op, am_flav);
2890 set_ia32_ls_mode(new_op, mode);
2891 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2892 set_ia32_use_frame(new_op);
2894 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2901 * Transforms an ia32_l_XXX into a "real" XXX node
2903 * @param env The transformation environment
2904 * @return the created ia32 XXX node
2906 #define GEN_LOWERED_OP(op) \
2907 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2908 ir_mode *mode = get_irn_mode(node); \
2909 if (mode_is_float(mode)) \
2911 return gen_binop(env, node, get_binop_left(node), \
2912 get_binop_right(node), new_rd_ia32_##op); \
2915 #define GEN_LOWERED_x87_OP(op) \
2916 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2918 FORCE_x87(env->cg); \
2919 new_op = gen_binop_float(env, node, get_binop_left(node), \
2920 get_binop_right(node), new_rd_ia32_##op); \
2924 #define GEN_LOWERED_UNOP(op) \
2925 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2926 return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \
2929 #define GEN_LOWERED_SHIFT_OP(op) \
2930 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2931 return gen_shift_binop(env, node, get_binop_left(node), \
2932 get_binop_right(node), new_rd_ia32_##op); \
2935 #define GEN_LOWERED_LOAD(op, fp_unit) \
2936 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2937 return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \
2940 #define GEN_LOWERED_STORE(op, fp_unit) \
2941 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2942 return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \
2949 GEN_LOWERED_OP(IMul)
2951 GEN_LOWERED_x87_OP(vfprem)
2952 GEN_LOWERED_x87_OP(vfmul)
2953 GEN_LOWERED_x87_OP(vfsub)
2955 GEN_LOWERED_UNOP(Neg)
2957 GEN_LOWERED_LOAD(vfild, fp_x87)
2958 GEN_LOWERED_LOAD(Load, fp_none)
2959 GEN_LOWERED_STORE(vfist, fp_x87)
2960 GEN_LOWERED_STORE(Store, fp_none)
2962 static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
2963 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2964 ir_graph *irg = env->irg;
2965 dbg_info *dbg = get_irn_dbg_info(node);
2966 ir_node *block = transform_node(env, get_nodes_block(node));
2967 ir_node *left = get_binop_left(node);
2968 ir_node *right = get_binop_right(node);
2969 ir_node *new_left = transform_node(env, left);
2970 ir_node *new_right = transform_node(env, right);
2973 vfdiv = new_rd_ia32_vfdiv(dbg, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
2974 clear_ia32_commutative(vfdiv);
2975 set_ia32_am_support(vfdiv, ia32_am_Source);
2976 fold_immediate(env, vfdiv, 2, 3);
2978 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env->cg, node));
2986 * Transforms a l_MulS into a "real" MulS node.
2988 * @param env The transformation environment
2989 * @return the created ia32 Mul node
2991 static ir_node *gen_ia32_l_Mul(ia32_transform_env_t *env, ir_node *node) {
2992 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2993 ir_graph *irg = env->irg;
2994 dbg_info *dbg = get_irn_dbg_info(node);
2995 ir_node *block = transform_node(env, get_nodes_block(node));
2996 ir_node *left = get_binop_left(node);
2997 ir_node *right = get_binop_right(node);
2998 ir_node *new_left = transform_node(env, left);
2999 ir_node *new_right = transform_node(env, right);
3002 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3003 /* and then skip the result Proj, because all needed Projs are already there. */
3004 ir_node *muls = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3005 clear_ia32_commutative(muls);
3006 set_ia32_am_support(muls, ia32_am_Source);
3007 fold_immediate(env, muls, 2, 3);
3009 /* check if EAX and EDX proj exist, add missing one */
3010 in[0] = new_rd_Proj(dbg, irg, block, muls, mode_Iu, pn_EAX);
3011 in[1] = new_rd_Proj(dbg, irg, block, muls, mode_Iu, pn_EDX);
3012 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3014 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env->cg, node));
3019 GEN_LOWERED_SHIFT_OP(Shl)
3020 GEN_LOWERED_SHIFT_OP(Shr)
3021 GEN_LOWERED_SHIFT_OP(Sar)
3024 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3025 * op1 - target to be shifted
3026 * op2 - contains bits to be shifted into target
3028 * Only op3 can be an immediate.
3030 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *node,
3031 ir_node *op1, ir_node *op2,
3033 ir_node *new_op = NULL;
3034 ir_graph *irg = env->irg;
3035 ir_mode *mode = get_irn_mode(node);
3036 dbg_info *dbg = get_irn_dbg_info(node);
3037 ir_node *block = transform_node(env, get_nodes_block(node));
3038 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3039 ir_node *nomem = new_NoMem();
3041 ir_node *new_op1 = transform_node(env, op1);
3042 ir_node *new_op2 = transform_node(env, op2);
3043 ir_node *new_count = transform_node(env, count);
3045 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
3047 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
3049 /* Check if immediate optimization is on and */
3050 /* if it's an operation with immediate. */
3051 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3053 /* Limit imm_op within range imm8 */
3055 tv = get_ia32_Immop_tarval(imm_op);
3058 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3059 set_ia32_Immop_tarval(imm_op, tv);
3066 /* integer operations */
3068 /* This is ShiftD with const */
3069 DB((mod, LEVEL_1, "ShiftD with immediate ..."));
3071 if (is_ia32_l_ShlD(node))
3072 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg,
3073 new_op1, new_op2, noreg, nomem);
3075 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg,
3076 new_op1, new_op2, noreg, nomem);
3077 copy_ia32_Immop_attr(new_op, imm_op);
3080 /* This is a normal ShiftD */
3081 DB((mod, LEVEL_1, "ShiftD binop ..."));
3082 if (is_ia32_l_ShlD(node))
3083 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg,
3084 new_op1, new_op2, new_count, nomem);
3086 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg,
3087 new_op1, new_op2, new_count, nomem);
3090 /* set AM support */
3091 // Matze: node has unsupported format (6inputs)
3092 //set_ia32_am_support(new_op, ia32_am_Dest);
3094 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3096 set_ia32_emit_cl(new_op);
3101 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env, ir_node *node) {
3102 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3103 get_irn_n(node, 1), get_irn_n(node, 2));
3106 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env, ir_node *node) {
3107 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3108 get_irn_n(node, 1), get_irn_n(node, 2));
3112 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3114 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) {
3115 ia32_code_gen_t *cg = env->cg;
3116 ir_node *res = NULL;
3117 ir_graph *irg = env->irg;
3118 dbg_info *dbg = get_irn_dbg_info(node);
3119 ir_node *block = transform_node(env, get_nodes_block(node));
3120 ir_node *ptr = get_irn_n(node, 0);
3121 ir_node *val = get_irn_n(node, 1);
3122 ir_node *new_val = transform_node(env, val);
3123 ir_node *mem = get_irn_n(node, 2);
3124 ir_node *noreg, *new_ptr, *new_mem;
3130 noreg = ia32_new_NoReg_gp(cg);
3131 new_mem = transform_node(env, mem);
3132 new_ptr = transform_node(env, ptr);
3134 /* Store x87 -> MEM */
3135 res = new_rd_ia32_vfst(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
3136 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3137 set_ia32_use_frame(res);
3138 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3139 set_ia32_am_support(res, ia32_am_Dest);
3140 set_ia32_am_flavour(res, ia32_B);
3141 set_ia32_op_type(res, ia32_AddrModeD);
3143 /* Load MEM -> SSE */
3144 res = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, res);
3145 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3146 set_ia32_use_frame(res);
3147 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3148 set_ia32_am_support(res, ia32_am_Source);
3149 set_ia32_am_flavour(res, ia32_B);
3150 set_ia32_op_type(res, ia32_AddrModeS);
3151 res = new_rd_Proj(dbg, irg, block, res, mode_E, pn_ia32_xLoad_res);
3157 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3159 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) {
3160 ia32_code_gen_t *cg = env->cg;
3161 ir_graph *irg = env->irg;
3162 dbg_info *dbg = get_irn_dbg_info(node);
3163 ir_node *block = transform_node(env, get_nodes_block(node));
3164 ir_node *res = NULL;
3165 ir_node *ptr = get_irn_n(node, 0);
3166 ir_node *val = get_irn_n(node, 1);
3167 ir_node *mem = get_irn_n(node, 2);
3168 ir_entity *fent = get_ia32_frame_ent(node);
3169 ir_mode *lsmode = get_ia32_ls_mode(node);
3170 ir_node *new_val = transform_node(env, val);
3171 ir_node *noreg, *new_ptr, *new_mem;
3174 if (!USE_SSE2(cg)) {
3175 /* SSE unit is not used -> skip this node. */
3179 noreg = ia32_new_NoReg_gp(cg);
3180 new_val = transform_node(env, val);
3181 new_ptr = transform_node(env, ptr);
3182 new_mem = transform_node(env, mem);
3184 /* Store SSE -> MEM */
3185 if (is_ia32_xLoad(skip_Proj(new_val))) {
3186 ir_node *ld = skip_Proj(new_val);
3188 /* we can vfld the value directly into the fpu */
3189 fent = get_ia32_frame_ent(ld);
3190 ptr = get_irn_n(ld, 0);
3191 offs = get_ia32_am_offs_int(ld);
3193 res = new_rd_ia32_xStore(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
3194 set_ia32_frame_ent(res, fent);
3195 set_ia32_use_frame(res);
3196 set_ia32_ls_mode(res, lsmode);
3197 set_ia32_am_support(res, ia32_am_Dest);
3198 set_ia32_am_flavour(res, ia32_B);
3199 set_ia32_op_type(res, ia32_AddrModeD);
3203 /* Load MEM -> x87 */
3204 res = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, new_mem);
3205 set_ia32_frame_ent(res, fent);
3206 set_ia32_use_frame(res);
3207 set_ia32_ls_mode(res, lsmode);
3208 add_ia32_am_offs_int(res, offs);
3209 set_ia32_am_support(res, ia32_am_Source);
3210 set_ia32_am_flavour(res, ia32_B);
3211 set_ia32_op_type(res, ia32_AddrModeS);
3212 res = new_rd_Proj(dbg, irg, block, res, lsmode, pn_ia32_vfld_res);
3217 /*********************************************************
3220 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3221 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3222 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3223 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3225 *********************************************************/
3228 * the BAD transformer.
3230 static ir_node *bad_transform(ia32_transform_env_t *env, ir_node *node) {
3231 panic("No transform function for %+F available.\n", node);
3235 static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) {
3236 /* end has to be duplicated manually because we need a dynamic in array */
3237 ir_graph *irg = env->irg;
3238 dbg_info *dbg = get_irn_dbg_info(node);
3239 ir_node *block = transform_node(env, get_nodes_block(node));
3243 new_end = new_ir_node(dbg, irg, block, op_End, mode_X, -1, NULL);
3244 copy_node_attr(node, new_end);
3245 duplicate_deps(env, node, new_end);
3247 set_irg_end(irg, new_end);
3248 set_new_node(new_end, new_end);
3250 /* transform preds */
3251 arity = get_irn_arity(node);
3252 for(i = 0; i < arity; ++i) {
3253 ir_node *in = get_irn_n(node, i);
3254 ir_node *new_in = transform_node(env, in);
3256 add_End_keepalive(new_end, new_in);
3262 static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) {
3263 ir_graph *irg = env->irg;
3264 dbg_info *dbg = get_irn_dbg_info(node);
3265 ir_node *start_block = env->old_anchors[anchor_start_block];
3270 * We replace the ProjX from the start node with a jump,
3271 * so the startblock has no preds anymore now
3273 if(node == start_block) {
3274 return new_rd_Block(dbg, irg, 0, NULL);
3277 /* we use the old blocks for now, because jumps allow cycles in the graph
3278 * we have to fix this later */
3279 block = new_ir_node(dbg, irg, NULL, get_irn_op(node), get_irn_mode(node),
3280 get_irn_arity(node), get_irn_in(node) + 1);
3281 copy_node_attr(node, block);
3283 #ifdef DEBUG_libfirm
3284 block->node_nr = node->node_nr;
3286 set_new_node(node, block);
3288 /* put the preds in the worklist */
3289 arity = get_irn_arity(node);
3290 for(i = 0; i < arity; ++i) {
3291 ir_node *in = get_irn_n(node, i);
3292 pdeq_putr(env->worklist, in);
3298 static ir_node *gen_Proj_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
3299 ir_graph *irg = env->irg;
3300 ir_node *block = transform_node(env, get_nodes_block(node));
3301 dbg_info *dbg = get_irn_dbg_info(node);
3302 ir_node *pred = get_Proj_pred(node);
3303 ir_node *new_pred = transform_node(env, pred);
3304 long proj = get_Proj_proj(node);
3306 if(proj == pn_be_AddSP_res) {
3307 ir_node *res = new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3308 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3310 } else if(proj == pn_be_AddSP_M) {
3311 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3315 return new_rd_Unknown(irg, get_irn_mode(node));
3318 static ir_node *gen_Proj_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
3319 ir_graph *irg = env->irg;
3320 ir_node *block = transform_node(env, get_nodes_block(node));
3321 dbg_info *dbg = get_irn_dbg_info(node);
3322 ir_node *pred = get_Proj_pred(node);
3323 ir_node *new_pred = transform_node(env, pred);
3324 long proj = get_Proj_proj(node);
3326 if(proj == pn_be_SubSP_res) {
3327 ir_node *res = new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3328 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3330 } else if(proj == pn_be_SubSP_M) {
3331 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3335 return new_rd_Unknown(irg, get_irn_mode(node));
3338 static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) {
3339 ir_graph *irg = env->irg;
3340 ir_node *block = transform_node(env, get_nodes_block(node));
3341 dbg_info *dbg = get_irn_dbg_info(node);
3342 ir_node *pred = get_Proj_pred(node);
3343 ir_node *new_pred = transform_node(env, pred);
3344 long proj = get_Proj_proj(node);
3346 /* renumber the proj */
3347 if(is_ia32_Load(new_pred)) {
3348 if(proj == pn_Load_res) {
3349 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3350 } else if(proj == pn_Load_M) {
3351 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3353 } else if(is_ia32_xLoad(new_pred)) {
3354 if(proj == pn_Load_res) {
3355 return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_xLoad_res);
3356 } else if(proj == pn_Load_M) {
3357 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3359 } else if(is_ia32_vfld(new_pred)) {
3360 if(proj == pn_Load_res) {
3361 return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_vfld_res);
3362 } else if(proj == pn_Load_M) {
3363 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3368 return new_rd_Unknown(irg, get_irn_mode(node));
3371 static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) {
3372 ir_graph *irg = env->irg;
3373 dbg_info *dbg = get_irn_dbg_info(node);
3374 ir_node *block = transform_node(env, get_nodes_block(node));
3375 ir_mode *mode = get_irn_mode(node);
3377 ir_node *pred = get_Proj_pred(node);
3378 ir_node *new_pred = transform_node(env, pred);
3379 long proj = get_Proj_proj(node);
3381 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3383 switch(get_irn_opcode(pred)) {
3387 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3389 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3397 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3399 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3407 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3408 case pn_DivMod_res_div:
3409 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3410 case pn_DivMod_res_mod:
3411 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3421 return new_rd_Unknown(irg, mode);
3424 static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node)
3426 ir_graph *irg = env->irg;
3427 dbg_info *dbg = get_irn_dbg_info(node);
3428 ir_node *block = transform_node(env, get_nodes_block(node));
3429 ir_mode *mode = get_irn_mode(node);
3431 ir_node *pred = get_Proj_pred(node);
3432 ir_node *new_pred = transform_node(env, pred);
3433 long proj = get_Proj_proj(node);
3436 case pn_CopyB_M_regular:
3437 if(is_ia32_CopyB_i(new_pred)) {
3438 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3440 } else if(is_ia32_CopyB(new_pred)) {
3441 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3450 return new_rd_Unknown(irg, mode);
3453 static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node)
3455 ir_graph *irg = env->irg;
3456 dbg_info *dbg = get_irn_dbg_info(node);
3457 ir_node *block = transform_node(env, get_nodes_block(node));
3458 ir_mode *mode = get_irn_mode(node);
3460 ir_node *pred = get_Proj_pred(node);
3461 ir_node *new_pred = transform_node(env, pred);
3462 long proj = get_Proj_proj(node);
3465 case pn_ia32_l_vfdiv_M:
3466 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3467 case pn_ia32_l_vfdiv_res:
3468 return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_vfdiv_res);
3473 return new_rd_Unknown(irg, mode);
3476 static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node)
3478 ir_graph *irg = env->irg;
3479 dbg_info *dbg = get_irn_dbg_info(node);
3480 ir_node *block = transform_node(env, get_nodes_block(node));
3481 ir_mode *mode = get_irn_mode(node);
3483 ir_node *pred = get_Proj_pred(node);
3484 ir_node *new_pred = transform_node(env, pred);
3485 long proj = get_Proj_proj(node);
3489 if(is_ia32_xDiv(new_pred)) {
3490 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3492 } else if(is_ia32_vfdiv(new_pred)) {
3493 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3498 if(is_ia32_xDiv(new_pred)) {
3499 return new_rd_Proj(dbg, irg, block, new_pred, mode_E,
3501 } else if(is_ia32_vfdiv(new_pred)) {
3502 return new_rd_Proj(dbg, irg, block, new_pred, mode_E,
3511 return new_rd_Unknown(irg, mode);
3514 static ir_node *gen_Proj_tls(ia32_transform_env_t *env, ir_node *node) {
3515 ir_graph *irg = env->irg;
3516 //dbg_info *dbg = get_irn_dbg_info(node);
3517 dbg_info *dbg = NULL;
3518 ir_node *block = transform_node(env, get_nodes_block(node));
3520 ir_node *res = new_rd_ia32_LdTls(dbg, irg, block, mode_Iu);
3525 static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) {
3526 ir_graph *irg = env->irg;
3527 dbg_info *dbg = get_irn_dbg_info(node);
3528 long proj = get_Proj_proj(node);
3529 ir_mode *mode = get_irn_mode(node);
3530 ir_node *block = transform_node(env, get_nodes_block(node));
3532 ir_node *call = get_Proj_pred(node);
3533 ir_node *new_call = transform_node(env, call);
3535 /* The following is kinda tricky: If we're using SSE, then we have to
3536 * move the result value of the call in floating point registers to an
3537 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3538 * after the call, we have to make sure to correctly make the
3539 * MemProj and the result Proj use these 2 nodes
3541 if(proj == pn_be_Call_M_regular) {
3542 // get new node for result, are we doing the sse load/store hack?
3543 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3544 ir_node *call_res_new;
3545 ir_node *call_res_pred = NULL;
3547 if(call_res != NULL) {
3548 call_res_new = transform_node(env, call_res);
3549 call_res_pred = get_Proj_pred(call_res_new);
3552 if(call_res_pred == NULL || be_is_Call(call_res_pred)) {
3553 return new_rd_Proj(dbg, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3555 assert(is_ia32_xLoad(call_res_pred));
3556 return new_rd_Proj(dbg, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3559 if(proj == pn_be_Call_first_res && mode_is_float(mode)
3560 && USE_SSE2(env->cg)) {
3562 ir_node *frame = get_irg_frame(irg);
3563 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3565 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3567 const arch_register_class_t *cls;
3569 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3570 call_mem = new_rd_Proj(dbg, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3572 /* store st(0) onto stack */
3573 fstp = new_rd_ia32_GetST0(dbg, irg, block, frame, noreg, call_mem);
3575 set_ia32_ls_mode(fstp, mode);
3576 set_ia32_op_type(fstp, ia32_AddrModeD);
3577 set_ia32_use_frame(fstp);
3578 set_ia32_am_flavour(fstp, ia32_am_B);
3579 set_ia32_am_support(fstp, ia32_am_Dest);
3581 /* load into SSE register */
3582 sse_load = new_rd_ia32_xLoad(dbg, irg, block, frame, noreg, fstp);
3583 set_ia32_ls_mode(sse_load, mode);
3584 set_ia32_op_type(sse_load, ia32_AddrModeS);
3585 set_ia32_use_frame(sse_load);
3586 set_ia32_am_flavour(sse_load, ia32_am_B);
3587 set_ia32_am_support(sse_load, ia32_am_Source);
3589 //mproj = new_rd_Proj(dbg, irg, block, sse_load, mode_M, pn_ia32_xLoad_M);
3590 sse_load = new_rd_Proj(dbg, irg, block, sse_load, mode_E, pn_ia32_xLoad_res);
3592 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3594 /* get a Proj representing a caller save register */
3595 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3596 assert(is_Proj(p) && "Proj expected.");
3598 /* user of the the proj is the Keep */
3599 p = get_edge_src_irn(get_irn_out_edge_first(p));
3600 assert(be_is_Keep(p) && "Keep expected.");
3602 /* keep the result */
3603 cls = arch_get_irn_reg_class(env->cg->arch_env, sse_load, -1);
3604 keepin[0] = sse_load;
3605 be_new_Keep(cls, irg, block, 1, keepin);
3610 /* transform call modes to the mode_Iu or mode_E */
3611 if(mode_is_float(mode)) {
3613 } else if(mode != mode_M) {
3617 return new_rd_Proj(dbg, irg, block, new_call, mode, proj);
3620 static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) {
3621 ir_graph *irg = env->irg;
3622 dbg_info *dbg = get_irn_dbg_info(node);
3623 ir_node *pred = get_Proj_pred(node);
3624 long proj = get_Proj_proj(node);
3626 if(is_Store(pred) || be_is_FrameStore(pred)) {
3627 if(proj == pn_Store_M) {
3628 return transform_node(env, pred);
3631 return new_r_Bad(irg);
3633 } else if(is_Load(pred) || be_is_FrameLoad(pred)) {
3634 return gen_Proj_Load(env, node);
3635 } else if(is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3636 return gen_Proj_DivMod(env, node);
3637 } else if(is_CopyB(pred)) {
3638 return gen_Proj_CopyB(env, node);
3639 } else if(is_Quot(pred)) {
3640 return gen_Proj_Quot(env, node);
3641 } else if(is_ia32_l_vfdiv(pred)) {
3642 return gen_Proj_l_vfdiv(env, node);
3643 } else if(be_is_SubSP(pred)) {
3644 return gen_Proj_be_SubSP(env, node);
3645 } else if(be_is_AddSP(pred)) {
3646 return gen_Proj_be_AddSP(env, node);
3647 } else if(be_is_Call(pred)) {
3648 return gen_Proj_be_Call(env, node);
3649 } else if(get_irn_op(pred) == op_Start) {
3650 if(proj == pn_Start_X_initial_exec) {
3651 ir_node *block = get_nodes_block(pred);
3654 block = transform_node(env, block);
3655 // we exchange the ProjX with a jump
3656 jump = new_rd_Jmp(dbg, irg, block);
3657 ir_fprintf(stderr, "created jump: %+F\n", jump);
3660 if(node == env->old_anchors[anchor_tls]) {
3661 return gen_Proj_tls(env, node);
3665 return duplicate_node(env, node);
3669 * Enters all transform functions into the generic pointer
3671 static void register_transformers(void) {
3672 ir_op *op_Max, *op_Min, *op_Mulh;
3674 /* first clear the generic function pointer for all ops */
3675 clear_irp_opcodes_generic_func();
3677 #define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3678 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
3717 /* transform ops from intrinsic lowering */
3739 GEN(ia32_l_X87toSSE);
3740 GEN(ia32_l_SSEtoX87);
3745 /* we should never see these nodes */
3760 /* handle generic backend nodes */
3770 /* set the register for all Unknown nodes */
3773 op_Max = get_op_Max();
3776 op_Min = get_op_Min();
3779 op_Mulh = get_op_Mulh();
3787 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
3791 int deps = get_irn_deps(old_node);
3793 for(i = 0; i < deps; ++i) {
3794 ir_node *dep = get_irn_dep(old_node, i);
3795 ir_node *new_dep = transform_node(env, dep);
3797 add_irn_dep(new_node, new_dep);
3801 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node)
3803 ir_graph *irg = env->irg;
3804 dbg_info *dbg = get_irn_dbg_info(node);
3805 ir_mode *mode = get_irn_mode(node);
3806 ir_op *op = get_irn_op(node);
3811 block = transform_node(env, get_nodes_block(node));
3813 arity = get_irn_arity(node);
3814 if(op->opar == oparity_dynamic) {
3815 new_node = new_ir_node(dbg, irg, block, op, mode, -1, NULL);
3816 for(i = 0; i < arity; ++i) {
3817 ir_node *in = get_irn_n(node, i);
3818 in = transform_node(env, in);
3819 add_irn_n(new_node, in);
3822 ir_node **ins = alloca(arity * sizeof(ins[0]));
3823 for(i = 0; i < arity; ++i) {
3824 ir_node *in = get_irn_n(node, i);
3825 ins[i] = transform_node(env, in);
3828 new_node = new_ir_node(dbg, irg, block, op, mode, arity, ins);
3831 copy_node_attr(node, new_node);
3832 duplicate_deps(env, node, new_node);
3837 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node)
3840 ir_op *op = get_irn_op(node);
3842 if(irn_visited(node)) {
3843 assert(get_new_node(node) != NULL);
3844 return get_new_node(node);
3847 mark_irn_visited(node);
3848 DEBUG_ONLY(set_new_node(node, NULL));
3850 if (op->ops.generic) {
3851 transform_func *transform = (transform_func *)op->ops.generic;
3853 new_node = (*transform)(env, node);
3854 assert(new_node != NULL);
3856 new_node = duplicate_node(env, node);
3858 //ir_fprintf(stderr, "%+F -> %+F\n", node, new_node);
3860 set_new_node(node, new_node);
3861 mark_irn_visited(new_node);
3862 hook_dead_node_elim_subst(current_ir_graph, node, new_node);
3866 static void fix_loops(ia32_transform_env_t *env, ir_node *node)
3870 if(irn_visited(node))
3872 mark_irn_visited(node);
3874 assert(node_is_in_irgs_storage(env->irg, node));
3876 if(!is_Block(node)) {
3877 ir_node *block = get_nodes_block(node);
3878 ir_node *new_block = (ir_node*) get_irn_link(block);
3880 if(new_block != NULL) {
3881 set_nodes_block(node, new_block);
3885 fix_loops(env, block);
3888 arity = get_irn_arity(node);
3889 for(i = 0; i < arity; ++i) {
3890 ir_node *in = get_irn_n(node, i);
3891 ir_node *new = (ir_node*) get_irn_link(in);
3893 if(new != NULL && new != in) {
3894 set_irn_n(node, i, new);
3901 arity = get_irn_deps(node);
3902 for(i = 0; i < arity; ++i) {
3903 ir_node *in = get_irn_dep(node, i);
3904 ir_node *new = (ir_node*) get_irn_link(in);
3906 if(new != NULL && new != in) {
3907 set_irn_dep(node, i, new);
3915 static void pre_transform_node(ir_node **place, ia32_transform_env_t *env)
3920 *place = transform_node(env, *place);
3923 static void transform_nodes(ia32_code_gen_t *cg)
3926 ir_graph *irg = cg->irg;
3928 ia32_transform_env_t env;
3930 hook_dead_node_elim(irg, 1);
3932 inc_irg_visited(irg);
3936 env.visited = get_irg_visited(irg);
3937 env.worklist = new_pdeq();
3938 env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
3939 DEBUG_ONLY(env.mod = cg->mod);
3941 old_end = get_irg_end(irg);
3943 /* put all anchor nodes in the worklist */
3944 for(i = 0; i < anchor_max; ++i) {
3945 ir_node *anchor = irg->anchors[i];
3948 pdeq_putr(env.worklist, anchor);
3951 env.old_anchors[i] = anchor;
3952 // and set it to NULL to make sure we don't accidently use it
3953 irg->anchors[i] = NULL;
3956 // pre transform some anchors (so they are available in the other transform
3958 set_irg_bad(irg, transform_node(&env, env.old_anchors[anchor_bad]));
3959 set_irg_no_mem(irg, transform_node(&env, env.old_anchors[anchor_no_mem]));
3960 set_irg_start_block(irg, transform_node(&env, env.old_anchors[anchor_start_block]));
3961 set_irg_start(irg, transform_node(&env, env.old_anchors[anchor_start]));
3962 set_irg_frame(irg, transform_node(&env, env.old_anchors[anchor_frame]));
3964 pre_transform_node(&cg->unknown_gp, &env);
3965 pre_transform_node(&cg->unknown_vfp, &env);
3966 pre_transform_node(&cg->unknown_xmm, &env);
3967 pre_transform_node(&cg->noreg_gp, &env);
3968 pre_transform_node(&cg->noreg_vfp, &env);
3969 pre_transform_node(&cg->noreg_xmm, &env);
3971 /* process worklist (this should transform all nodes in the graph) */
3972 while(!pdeq_empty(env.worklist)) {
3973 ir_node *node = pdeq_getl(env.worklist);
3974 transform_node(&env, node);
3977 /* fix loops and set new anchors*/
3978 inc_irg_visited(irg);
3979 for(i = 0; i < anchor_max; ++i) {
3980 ir_node *anchor = env.old_anchors[i];
3984 anchor = get_irn_link(anchor);
3985 fix_loops(&env, anchor);
3986 assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
3987 irg->anchors[i] = anchor;
3990 del_pdeq(env.worklist);
3992 hook_dead_node_elim(irg, 0);
3995 void ia32_transform_graph(ia32_code_gen_t *cg)
3997 ir_graph *irg = cg->irg;
3998 be_irg_t *birg = cg->birg;
3999 ir_graph *old_current_ir_graph = current_ir_graph;
4000 int old_interprocedural_view = get_interprocedural_view();
4001 struct obstack *old_obst = NULL;
4002 struct obstack *new_obst = NULL;
4004 current_ir_graph = irg;
4005 set_interprocedural_view(0);
4006 register_transformers();
4008 /* most analysis info is wrong after transformation */
4009 free_callee_info(irg);
4011 irg->outs_state = outs_none;
4013 free_loop_information(irg);
4014 set_irg_doms_inconsistent(irg);
4015 be_invalidate_liveness(birg);
4016 be_invalidate_dom_front(birg);
4018 /* create a new obstack */
4019 old_obst = irg->obst;
4020 new_obst = xmalloc(sizeof(*new_obst));
4021 obstack_init(new_obst);
4022 irg->obst = new_obst;
4023 irg->last_node_idx = 0;
4025 /* create new value table for CSE */
4026 del_identities(irg->value_table);
4027 irg->value_table = new_identities();
4029 /* do the main transformation */
4030 transform_nodes(cg);
4032 /* we don't want the globals anchor anymore */
4033 set_irg_globals(irg, new_r_Bad(irg));
4035 /* free the old obstack */
4036 obstack_free(old_obst, 0);
4040 current_ir_graph = old_current_ir_graph;
4041 set_interprocedural_view(old_interprocedural_view);
4043 /* recalculate edges */
4044 edges_deactivate(irg);
4045 edges_activate(irg);
4049 * Transforms a psi condition.
4051 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
4054 /* if the mode is target mode, we have already seen this part of the tree */
4055 if (get_irn_mode(cond) == mode)
4058 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
4060 set_irn_mode(cond, mode);
4062 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
4063 ir_node *in = get_irn_n(cond, i);
4065 /* if in is a compare: transform into Set/xCmp */
4067 ir_node *new_op = NULL;
4068 ir_node *cmp = get_Proj_pred(in);
4069 ir_node *cmp_a = get_Cmp_left(cmp);
4070 ir_node *cmp_b = get_Cmp_right(cmp);
4071 dbg_info *dbg = get_irn_dbg_info(cmp);
4072 ir_graph *irg = get_irn_irg(cmp);
4073 ir_node *block = get_nodes_block(cmp);
4074 ir_node *noreg = ia32_new_NoReg_gp(cg);
4075 ir_node *nomem = new_rd_NoMem(irg);
4076 int pnc = get_Proj_proj(in);
4078 /* this is a compare */
4079 if (mode_is_float(mode)) {
4080 /* Psi is float, we need a floating point compare */
4083 ir_mode *m = get_irn_mode(cmp_a);
4085 if (! mode_is_float(m)) {
4086 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
4087 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
4089 else if (m == mode_F) {
4090 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
4091 cmp_a = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_a, cmp_a);
4092 cmp_b = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_b, cmp_b);
4095 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4096 set_ia32_pncode(new_op, pnc);
4097 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
4106 construct_binop_func *set_func = NULL;
4108 if (mode_is_float(get_irn_mode(cmp_a))) {
4109 /* 1st case: compare operands are floats */
4114 set_func = new_rd_ia32_xCmpSet;
4118 set_func = new_rd_ia32_vfCmpSet;
4121 pnc &= 7; /* fp compare -> int compare */
4124 /* 2nd case: compare operand are integer too */
4125 set_func = new_rd_ia32_CmpSet;
4128 new_op = set_func(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4129 if(!mode_is_signed(mode))
4130 pnc |= ia32_pn_Cmp_Unsigned;
4132 set_ia32_pncode(new_op, pnc);
4133 set_ia32_am_support(new_op, ia32_am_Source);
4136 /* the the new compare as in */
4137 set_irn_n(cond, i, new_op);
4140 /* another complex condition */
4141 transform_psi_cond(in, mode, cg);
4147 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
4148 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
4149 * compare, which causes the compare result to be stores in a register. The
4150 * "And"s and "Or"s are transformed later, we just have to set their mode right.
4152 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
4153 ia32_code_gen_t *cg = env;
4154 ir_node *psi_sel, *new_cmp, *block;
4159 if (get_irn_opcode(node) != iro_Psi)
4162 psi_sel = get_Psi_cond(node, 0);
4164 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
4165 if (is_Proj(psi_sel))
4168 //mode = get_irn_mode(node);
4169 // TODO this is probably wrong...
4172 transform_psi_cond(psi_sel, mode, cg);
4174 irg = get_irn_irg(node);
4175 block = get_nodes_block(node);
4177 /* we need to compare the evaluated condition tree with 0 */
4178 mode = get_irn_mode(node);
4179 if (mode_is_float(mode)) {
4180 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
4181 /* BEWARE: new_r_Const_long works for floating point as well */
4182 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
4183 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
4186 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode_Iu, 0));
4187 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
4190 set_Psi_cond(node, 0, new_cmp);