2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
30 #include "archop.h" /* we need this for Min and Max nodes */
37 #include "../benode_t.h"
38 #include "../besched.h"
40 #include "../beutil.h"
41 #include "../beirg_t.h"
43 #include "bearch_ia32_t.h"
44 #include "ia32_nodes_attr.h"
45 #include "ia32_transform.h"
46 #include "ia32_new_nodes.h"
47 #include "ia32_map_regs.h"
48 #include "ia32_dbg_stat.h"
49 #include "ia32_optimize.h"
50 #include "ia32_util.h"
52 #include "gen_ia32_regalloc_if.h"
54 #define SFP_SIGN "0x80000000"
55 #define DFP_SIGN "0x8000000000000000"
56 #define SFP_ABS "0x7FFFFFFF"
57 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
59 #define TP_SFP_SIGN "ia32_sfp_sign"
60 #define TP_DFP_SIGN "ia32_dfp_sign"
61 #define TP_SFP_ABS "ia32_sfp_abs"
62 #define TP_DFP_ABS "ia32_dfp_abs"
64 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
65 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
66 #define ENT_SFP_ABS "IA32_SFP_ABS"
67 #define ENT_DFP_ABS "IA32_DFP_ABS"
69 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
70 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
72 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
74 typedef struct ia32_transform_env_t {
75 ir_graph *irg; /**< The irg, the node should be created in */
76 ia32_code_gen_t *cg; /**< The code generator */
77 int visited; /**< visited count that indicates whether a
78 node is already transformed */
79 pdeq *worklist; /**< worklist of nodes that still need to be
81 ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/
82 } ia32_transform_env_t;
84 extern ir_op *get_op_Mulh(void);
86 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
87 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
88 ir_node *op2, ir_node *mem);
90 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
91 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
94 typedef ir_node *(transform_func)(ia32_transform_env_t *env, ir_node *node);
96 /****************************************************************************************************
98 * | | | | / _| | | (_)
99 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
100 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
101 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
102 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
104 ****************************************************************************************************/
106 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node);
107 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node);
108 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
111 static INLINE int mode_needs_gp_reg(ir_mode *mode)
113 if(mode == mode_fpcw)
116 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
119 static INLINE void set_new_node(ir_node *old_node, ir_node *new_node)
121 set_irn_link(old_node, new_node);
124 static INLINE ir_node *get_new_node(ir_node *old_node)
126 assert(irn_visited(old_node));
127 return (ir_node*) get_irn_link(old_node);
131 * Returns 1 if irn is a Const representing 0, 0 otherwise
133 static INLINE int is_ia32_Const_0(ir_node *irn) {
134 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
135 && tarval_is_null(get_ia32_Immop_tarval(irn));
139 * Returns 1 if irn is a Const representing 1, 0 otherwise
141 static INLINE int is_ia32_Const_1(ir_node *irn) {
142 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
143 && tarval_is_one(get_ia32_Immop_tarval(irn));
147 * Collects all Projs of a node into the node array. Index is the projnum.
148 * BEWARE: The caller has to assure the appropriate array size!
150 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
151 const ir_edge_t *edge;
152 assert(get_irn_mode(irn) == mode_T && "need mode_T");
154 memset(projs, 0, size * sizeof(projs[0]));
156 foreach_out_edge(irn, edge) {
157 ir_node *proj = get_edge_src_irn(edge);
158 int proj_proj = get_Proj_proj(proj);
159 assert(proj_proj < size);
160 projs[proj_proj] = proj;
165 * Renumbers the proj having pn_old in the array tp pn_new
166 * and removes the proj from the array.
168 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
169 fprintf(stderr, "Warning: renumber_Proj used!\n");
171 set_Proj_proj(projs[pn_old], pn_new);
172 projs[pn_old] = NULL;
177 * creates a unique ident by adding a number to a tag
179 * @param tag the tag string, must contain a %d if a number
182 static ident *unique_id(const char *tag)
184 static unsigned id = 0;
187 snprintf(str, sizeof(str), tag, ++id);
188 return new_id_from_str(str);
192 * Get a primitive type for a mode.
194 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
196 pmap_entry *e = pmap_find(types, mode);
201 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
202 res = new_type_primitive(new_id_from_str(buf), mode);
203 pmap_insert(types, mode, res);
211 * Get an entity that is initialized with a tarval
213 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
215 tarval *tv = get_Const_tarval(cnst);
216 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
221 ir_mode *mode = get_irn_mode(cnst);
222 ir_type *tp = get_Const_type(cnst);
223 if (tp == firm_unknown_type)
224 tp = get_prim_type(cg->isa->types, mode);
226 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
228 set_entity_ld_ident(res, get_entity_ident(res));
229 set_entity_visibility(res, visibility_local);
230 set_entity_variability(res, variability_constant);
231 set_entity_allocation(res, allocation_static);
233 /* we create a new entity here: It's initialization must resist on the
235 rem = current_ir_graph;
236 current_ir_graph = get_const_code_irg();
237 set_atomic_ent_value(res, new_Const_type(tv, tp));
238 current_ir_graph = rem;
240 pmap_insert(cg->isa->tv_ent, tv, res);
249 * Transforms a Const.
251 static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) {
252 ir_graph *irg = env->irg;
253 dbg_info *dbgi = get_irn_dbg_info(node);
254 ir_mode *mode = get_irn_mode(node);
255 ir_node *block = transform_node(env, get_nodes_block(node));
257 if (mode_is_float(mode)) {
260 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
261 ir_node *nomem = new_NoMem();
265 if (! USE_SSE2(env->cg)) {
266 cnst_classify_t clss = classify_Const(node);
268 if (clss == CNST_NULL) {
269 load = new_rd_ia32_vfldz(dbgi, irg, block);
271 } else if (clss == CNST_ONE) {
272 load = new_rd_ia32_vfld1(dbgi, irg, block);
275 floatent = get_entity_for_tv(env->cg, node);
277 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem);
278 set_ia32_am_support(load, ia32_am_Source);
279 set_ia32_op_type(load, ia32_AddrModeS);
280 set_ia32_am_flavour(load, ia32_am_N);
281 set_ia32_am_sc(load, floatent);
282 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
284 set_ia32_ls_mode(load, mode);
286 floatent = get_entity_for_tv(env->cg, node);
288 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
289 set_ia32_am_support(load, ia32_am_Source);
290 set_ia32_op_type(load, ia32_AddrModeS);
291 set_ia32_am_flavour(load, ia32_am_N);
292 set_ia32_am_sc(load, floatent);
293 set_ia32_ls_mode(load, mode);
295 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
298 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
300 /* Const Nodes before the initial IncSP are a bad idea, because
301 * they could be spilled and we have no SP ready at that point yet
303 if (get_irg_start_block(irg) == block) {
304 add_irn_dep(load, get_irg_frame(irg));
307 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
310 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
313 if (get_irg_start_block(irg) == block) {
314 add_irn_dep(cnst, get_irg_frame(irg));
317 set_ia32_Const_attr(cnst, node);
318 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
323 return new_r_Bad(irg);
327 * Transforms a SymConst.
329 static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) {
330 ir_graph *irg = env->irg;
331 dbg_info *dbgi = get_irn_dbg_info(node);
332 ir_mode *mode = get_irn_mode(node);
333 ir_node *block = transform_node(env, get_nodes_block(node));
336 if (mode_is_float(mode)) {
338 if (USE_SSE2(env->cg))
339 cnst = new_rd_ia32_xConst(dbgi, irg, block);
341 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
342 set_ia32_ls_mode(cnst, mode);
344 cnst = new_rd_ia32_Const(dbgi, irg, block);
347 /* Const Nodes before the initial IncSP are a bad idea, because
348 * they could be spilled and we have no SP ready at that point yet
350 if (get_irg_start_block(irg) == block) {
351 add_irn_dep(cnst, get_irg_frame(irg));
354 set_ia32_Const_attr(cnst, node);
355 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
361 * SSE convert of an integer node into a floating point node.
363 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbgi,
364 ir_graph *irg, ir_node *block,
365 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
367 ir_node *noreg = ia32_new_NoReg_gp(cg);
368 ir_node *nomem = new_rd_NoMem(irg);
369 ir_node *old_pred = get_Cmp_left(old_node);
370 ir_mode *in_mode = get_irn_mode(old_pred);
371 int in_bits = get_mode_size_bits(in_mode);
373 ir_node *conv = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, in, nomem);
374 set_ia32_ls_mode(conv, tgt_mode);
376 set_ia32_am_support(conv, ia32_am_Source);
378 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
384 * SSE convert of an float node into a double node.
386 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbgi,
387 ir_graph *irg, ir_node *block,
388 ir_node *in, ir_node *old_node)
390 ir_node *noreg = ia32_new_NoReg_gp(cg);
391 ir_node *nomem = new_rd_NoMem(irg);
393 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, in, nomem);
394 set_ia32_am_support(conv, ia32_am_Source);
395 set_ia32_ls_mode(conv, mode_xmm);
396 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
401 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
402 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
403 static const struct {
405 const char *ent_name;
406 const char *cnst_str;
407 } names [ia32_known_const_max] = {
408 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
409 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
410 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
411 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
413 static ir_entity *ent_cache[ia32_known_const_max];
415 const char *tp_name, *ent_name, *cnst_str;
423 ent_name = names[kct].ent_name;
424 if (! ent_cache[kct]) {
425 tp_name = names[kct].tp_name;
426 cnst_str = names[kct].cnst_str;
428 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
430 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
431 tp = new_type_primitive(new_id_from_str(tp_name), mode);
432 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
434 set_entity_ld_ident(ent, get_entity_ident(ent));
435 set_entity_visibility(ent, visibility_local);
436 set_entity_variability(ent, variability_constant);
437 set_entity_allocation(ent, allocation_static);
439 /* we create a new entity here: It's initialization must resist on the
441 rem = current_ir_graph;
442 current_ir_graph = get_const_code_irg();
443 cnst = new_Const(mode, tv);
444 current_ir_graph = rem;
446 set_atomic_ent_value(ent, cnst);
448 /* cache the entry */
449 ent_cache[kct] = ent;
452 return ent_cache[kct];
457 * Prints the old node name on cg obst and returns a pointer to it.
459 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
460 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
462 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
463 obstack_1grow(isa->name_obst, 0);
464 return obstack_finish(isa->name_obst);
468 /* determine if one operator is an Imm */
469 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
471 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
473 return is_ia32_Cnst(op2) ? op2 : NULL;
477 /* determine if one operator is not an Imm */
478 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
479 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
482 static void fold_immediate(ia32_transform_env_t *env, ir_node *node, int in1, int in2) {
486 if(! (env->cg->opt & IA32_OPT_IMMOPS))
489 left = get_irn_n(node, in1);
490 right = get_irn_n(node, in2);
491 if(!is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
492 /* we can only set right operand to immediate */
493 if(!is_ia32_commutative(node))
495 /* exchange left/right */
496 set_irn_n(node, in1, right);
497 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
498 copy_ia32_Immop_attr(node, left);
499 } else if(is_ia32_Cnst(right)) {
500 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
501 copy_ia32_Immop_attr(node, right);
506 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
510 * Construct a standard binary operation, set AM and immediate if required.
512 * @param env The transformation environment
513 * @param op1 The first operand
514 * @param op2 The second operand
515 * @param func The node constructor function
516 * @return The constructed ia32 node.
518 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *node,
519 ir_node *op1, ir_node *op2,
520 construct_binop_func *func) {
521 ir_node *new_node = NULL;
522 ir_graph *irg = env->irg;
523 dbg_info *dbgi = get_irn_dbg_info(node);
524 ir_node *block = transform_node(env, get_nodes_block(node));
525 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
526 ir_node *nomem = new_NoMem();
527 ir_node *new_op1 = transform_node(env, op1);
528 ir_node *new_op2 = transform_node(env, op2);
530 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
531 if(func == new_rd_ia32_IMul) {
532 set_ia32_am_support(new_node, ia32_am_Source);
534 set_ia32_am_support(new_node, ia32_am_Full);
537 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
538 if (is_op_commutative(get_irn_op(node))) {
539 set_ia32_commutative(new_node);
541 fold_immediate(env, new_node, 2, 3);
547 * Construct a standard binary operation, set AM and immediate if required.
549 * @param env The transformation environment
550 * @param op1 The first operand
551 * @param op2 The second operand
552 * @param func The node constructor function
553 * @return The constructed ia32 node.
555 static ir_node *gen_binop_float(ia32_transform_env_t *env, ir_node *node,
556 ir_node *op1, ir_node *op2,
557 construct_binop_func *func)
559 ir_node *new_node = NULL;
560 dbg_info *dbgi = get_irn_dbg_info(node);
561 ir_graph *irg = env->irg;
562 ir_mode *mode = get_irn_mode(node);
563 ir_node *block = transform_node(env, get_nodes_block(node));
564 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
565 ir_node *nomem = new_NoMem();
566 ir_node *new_op1 = transform_node(env, op1);
567 ir_node *new_op2 = transform_node(env, op2);
569 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
570 set_ia32_am_support(new_node, ia32_am_Source);
571 if (is_op_commutative(get_irn_op(node))) {
572 set_ia32_commutative(new_node);
574 if (USE_SSE2(env->cg)) {
575 set_ia32_ls_mode(new_node, mode);
578 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
585 * Construct a shift/rotate binary operation, sets AM and immediate if required.
587 * @param env The transformation environment
588 * @param op1 The first operand
589 * @param op2 The second operand
590 * @param func The node constructor function
591 * @return The constructed ia32 node.
593 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node,
594 ir_node *op1, ir_node *op2,
595 construct_binop_func *func) {
596 ir_node *new_op = NULL;
597 dbg_info *dbgi = get_irn_dbg_info(node);
598 ir_graph *irg = env->irg;
599 ir_node *block = transform_node(env, get_nodes_block(node));
600 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
601 ir_node *nomem = new_NoMem();
604 ir_node *new_op1 = transform_node(env, op1);
605 ir_node *new_op2 = transform_node(env, op2);
608 assert(! mode_is_float(get_irn_mode(node))
609 && "Shift/Rotate with float not supported");
611 /* Check if immediate optimization is on and */
612 /* if it's an operation with immediate. */
613 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
614 expr_op = get_expr_op(new_op1, new_op2);
616 assert((expr_op || imm_op) && "invalid operands");
619 /* We have two consts here: not yet supported */
623 /* Limit imm_op within range imm8 */
625 tv = get_ia32_Immop_tarval(imm_op);
628 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
629 set_ia32_Immop_tarval(imm_op, tv);
636 /* integer operations */
638 /* This is shift/rot with const */
639 DB((dbg, LEVEL_1, "Shift/Rot with immediate ..."));
641 new_op = func(dbgi, irg, block, noreg, noreg, expr_op, noreg, nomem);
642 copy_ia32_Immop_attr(new_op, imm_op);
644 /* This is a normal shift/rot */
645 DB((dbg, LEVEL_1, "Shift/Rot binop ..."));
646 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
650 set_ia32_am_support(new_op, ia32_am_Dest);
652 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
654 set_ia32_emit_cl(new_op);
661 * Construct a standard unary operation, set AM and immediate if required.
663 * @param env The transformation environment
664 * @param op The operand
665 * @param func The node constructor function
666 * @return The constructed ia32 node.
668 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *node, ir_node *op,
669 construct_unop_func *func) {
670 ir_node *new_node = NULL;
671 ir_graph *irg = env->irg;
672 dbg_info *dbgi = get_irn_dbg_info(node);
673 ir_node *block = transform_node(env, get_nodes_block(node));
674 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
675 ir_node *nomem = new_NoMem();
676 ir_node *new_op = transform_node(env, op);
678 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
679 DB((dbg, LEVEL_1, "INT unop ..."));
680 set_ia32_am_support(new_node, ia32_am_Dest);
682 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
689 * Creates an ia32 Add.
691 * @param env The transformation environment
692 * @return the created ia32 Add node
694 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) {
695 ir_node *new_op = NULL;
696 ir_graph *irg = env->irg;
697 dbg_info *dbgi = get_irn_dbg_info(node);
698 ir_mode *mode = get_irn_mode(node);
699 ir_node *block = transform_node(env, get_nodes_block(node));
700 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
701 ir_node *nomem = new_NoMem();
702 ir_node *expr_op, *imm_op;
703 ir_node *op1 = get_Add_left(node);
704 ir_node *op2 = get_Add_right(node);
705 ir_node *new_op1 = transform_node(env, op1);
706 ir_node *new_op2 = transform_node(env, op2);
708 /* Check if immediate optimization is on and */
709 /* if it's an operation with immediate. */
710 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
711 expr_op = get_expr_op(new_op1, new_op2);
713 assert((expr_op || imm_op) && "invalid operands");
715 if (mode_is_float(mode)) {
717 if (USE_SSE2(env->cg))
718 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xAdd);
720 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfadd);
725 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
726 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
728 /* No expr_op means, that we have two const - one symconst and */
729 /* one tarval or another symconst - because this case is not */
730 /* covered by constant folding */
731 /* We need to check for: */
732 /* 1) symconst + const -> becomes a LEA */
733 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
734 /* linker doesn't support two symconsts */
736 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
737 /* this is the 2nd case */
738 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
739 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
740 set_ia32_am_flavour(new_op, ia32_am_OB);
741 set_ia32_am_support(new_op, ia32_am_Source);
742 set_ia32_op_type(new_op, ia32_AddrModeS);
744 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
745 } else if (tp1 == ia32_ImmSymConst) {
746 tarval *tv = get_ia32_Immop_tarval(new_op2);
747 long offs = get_tarval_long(tv);
749 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
750 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
752 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
753 add_ia32_am_offs_int(new_op, offs);
754 set_ia32_am_flavour(new_op, ia32_am_O);
755 set_ia32_am_support(new_op, ia32_am_Source);
756 set_ia32_op_type(new_op, ia32_AddrModeS);
757 } else if (tp2 == ia32_ImmSymConst) {
758 tarval *tv = get_ia32_Immop_tarval(new_op1);
759 long offs = get_tarval_long(tv);
761 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
762 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
764 add_ia32_am_offs_int(new_op, offs);
765 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
766 set_ia32_am_flavour(new_op, ia32_am_O);
767 set_ia32_am_support(new_op, ia32_am_Source);
768 set_ia32_op_type(new_op, ia32_AddrModeS);
770 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
771 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
772 tarval *restv = tarval_add(tv1, tv2);
774 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
776 new_op = new_rd_ia32_Const(dbgi, irg, block);
777 set_ia32_Const_tarval(new_op, restv);
778 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
781 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
784 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
785 tarval_classification_t class_tv, class_negtv;
786 tarval *tv = get_ia32_Immop_tarval(imm_op);
788 /* optimize tarvals */
789 class_tv = classify_tarval(tv);
790 class_negtv = classify_tarval(tarval_neg(tv));
792 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
793 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
794 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
795 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
797 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
798 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
799 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
800 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
806 /* This is a normal add */
807 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
810 set_ia32_am_support(new_op, ia32_am_Full);
811 set_ia32_commutative(new_op);
813 fold_immediate(env, new_op, 2, 3);
815 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
821 static ir_node *create_ia32_Mul(ia32_transform_env_t *env, ir_node *node) {
822 ir_graph *irg = env->irg;
823 dbg_info *dbgi = get_irn_dbg_info(node);
824 ir_node *block = transform_node(env, get_nodes_block(node));
825 ir_node *op1 = get_Mul_left(node);
826 ir_node *op2 = get_Mul_right(node);
827 ir_node *new_op1 = transform_node(env, op1);
828 ir_node *new_op2 = transform_node(env, op2);
829 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
830 ir_node *proj_EAX, *proj_EDX, *res;
833 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
834 set_ia32_commutative(res);
835 set_ia32_am_support(res, ia32_am_Source);
837 /* imediates are not supported, so no fold_immediate */
838 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
839 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
843 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
851 * Creates an ia32 Mul.
853 * @param env The transformation environment
854 * @return the created ia32 Mul node
856 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) {
857 ir_node *op1 = get_Mul_left(node);
858 ir_node *op2 = get_Mul_right(node);
859 ir_mode *mode = get_irn_mode(node);
861 if (mode_is_float(mode)) {
863 if (USE_SSE2(env->cg))
864 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul);
866 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul);
869 // for the lower 32bit of the result it doesn't matter whether we use
870 // signed or unsigned multiplication so we use IMul as it has fewer
872 return gen_binop(env, node, op1, op2, new_rd_ia32_IMul);
876 * Creates an ia32 Mulh.
877 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
878 * this result while Mul returns the lower 32 bit.
880 * @param env The transformation environment
881 * @return the created ia32 Mulh node
883 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) {
884 ir_graph *irg = env->irg;
885 dbg_info *dbgi = get_irn_dbg_info(node);
886 ir_node *block = transform_node(env, get_nodes_block(node));
887 ir_node *op1 = get_irn_n(node, 0);
888 ir_node *op2 = get_irn_n(node, 1);
889 ir_node *new_op1 = transform_node(env, op1);
890 ir_node *new_op2 = transform_node(env, op2);
891 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
892 ir_node *proj_EAX, *proj_EDX, *res;
893 ir_mode *mode = get_irn_mode(node);
896 assert(!mode_is_float(mode) && "Mulh with float not supported");
897 if(mode_is_signed(mode)) {
898 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
900 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
903 set_ia32_commutative(res);
904 set_ia32_am_support(res, ia32_am_Source);
906 set_ia32_am_support(res, ia32_am_Source);
908 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
909 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
913 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
921 * Creates an ia32 And.
923 * @param env The transformation environment
924 * @return The created ia32 And node
926 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *node) {
927 ir_node *op1 = get_And_left(node);
928 ir_node *op2 = get_And_right(node);
930 assert (! mode_is_float(get_irn_mode(node)));
931 return gen_binop(env, node, op1, op2, new_rd_ia32_And);
937 * Creates an ia32 Or.
939 * @param env The transformation environment
940 * @return The created ia32 Or node
942 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *node) {
943 ir_node *op1 = get_Or_left(node);
944 ir_node *op2 = get_Or_right(node);
946 assert (! mode_is_float(get_irn_mode(node)));
947 return gen_binop(env, node, op1, op2, new_rd_ia32_Or);
953 * Creates an ia32 Eor.
955 * @param env The transformation environment
956 * @return The created ia32 Eor node
958 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *node) {
959 ir_node *op1 = get_Eor_left(node);
960 ir_node *op2 = get_Eor_right(node);
962 assert(! mode_is_float(get_irn_mode(node)));
963 return gen_binop(env, node, op1, op2, new_rd_ia32_Xor);
969 * Creates an ia32 Max.
971 * @param env The transformation environment
972 * @return the created ia32 Max node
974 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *node) {
975 ir_graph *irg = env->irg;
977 ir_mode *mode = get_irn_mode(node);
978 dbg_info *dbgi = get_irn_dbg_info(node);
979 ir_node *block = transform_node(env, get_nodes_block(node));
980 ir_node *op1 = get_irn_n(node, 0);
981 ir_node *op2 = get_irn_n(node, 1);
982 ir_node *new_op1 = transform_node(env, op1);
983 ir_node *new_op2 = transform_node(env, op2);
984 ir_mode *op_mode = get_irn_mode(op1);
986 assert(get_mode_size_bits(mode) == 32);
988 if (mode_is_float(mode)) {
990 if (USE_SSE2(env->cg)) {
991 new_op = gen_binop_float(env, node, new_op1, new_op2, new_rd_ia32_xMax);
993 panic("Can't create Max node");
996 long pnc = pn_Cmp_Gt;
997 if(!mode_is_signed(op_mode)) {
998 pnc |= ia32_pn_Cmp_Unsigned;
1000 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1001 set_ia32_pncode(new_op, pnc);
1002 set_ia32_am_support(new_op, ia32_am_None);
1004 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1010 * Creates an ia32 Min.
1012 * @param env The transformation environment
1013 * @return the created ia32 Min node
1015 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *node) {
1016 ir_graph *irg = env->irg;
1018 ir_mode *mode = get_irn_mode(node);
1019 dbg_info *dbgi = get_irn_dbg_info(node);
1020 ir_node *block = transform_node(env, get_nodes_block(node));
1021 ir_node *op1 = get_irn_n(node, 0);
1022 ir_node *op2 = get_irn_n(node, 1);
1023 ir_node *new_op1 = transform_node(env, op1);
1024 ir_node *new_op2 = transform_node(env, op2);
1025 ir_mode *op_mode = get_irn_mode(op1);
1027 assert(get_mode_size_bits(mode) == 32);
1029 if (mode_is_float(mode)) {
1031 if (USE_SSE2(env->cg)) {
1032 new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMin);
1034 panic("can't create Min node");
1037 long pnc = pn_Cmp_Lt;
1038 if(!mode_is_signed(op_mode)) {
1039 pnc |= ia32_pn_Cmp_Unsigned;
1041 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1042 set_ia32_pncode(new_op, pnc);
1043 set_ia32_am_support(new_op, ia32_am_None);
1045 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1052 * Creates an ia32 Sub.
1054 * @param env The transformation environment
1055 * @return The created ia32 Sub node
1057 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) {
1058 ir_node *new_op = NULL;
1059 ir_graph *irg = env->irg;
1060 dbg_info *dbgi = get_irn_dbg_info(node);
1061 ir_mode *mode = get_irn_mode(node);
1062 ir_node *block = transform_node(env, get_nodes_block(node));
1063 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1064 ir_node *nomem = new_NoMem();
1065 ir_node *op1 = get_Sub_left(node);
1066 ir_node *op2 = get_Sub_right(node);
1067 ir_node *new_op1 = transform_node(env, op1);
1068 ir_node *new_op2 = transform_node(env, op2);
1069 ir_node *expr_op, *imm_op;
1071 /* Check if immediate optimization is on and */
1072 /* if it's an operation with immediate. */
1073 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1074 expr_op = get_expr_op(new_op1, new_op2);
1076 assert((expr_op || imm_op) && "invalid operands");
1078 if (mode_is_float(mode)) {
1080 if (USE_SSE2(env->cg))
1081 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xSub);
1083 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfsub);
1088 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1089 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1091 /* No expr_op means, that we have two const - one symconst and */
1092 /* one tarval or another symconst - because this case is not */
1093 /* covered by constant folding */
1094 /* We need to check for: */
1095 /* 1) symconst - const -> becomes a LEA */
1096 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1097 /* linker doesn't support two symconsts */
1098 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1099 /* this is the 2nd case */
1100 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1101 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1102 set_ia32_am_sc_sign(new_op);
1103 set_ia32_am_flavour(new_op, ia32_am_OB);
1105 DBG_OPT_LEA3(op1, op2, node, new_op);
1106 } else if (tp1 == ia32_ImmSymConst) {
1107 tarval *tv = get_ia32_Immop_tarval(new_op2);
1108 long offs = get_tarval_long(tv);
1110 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1111 DBG_OPT_LEA3(op1, op2, node, new_op);
1113 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1114 add_ia32_am_offs_int(new_op, -offs);
1115 set_ia32_am_flavour(new_op, ia32_am_O);
1116 set_ia32_am_support(new_op, ia32_am_Source);
1117 set_ia32_op_type(new_op, ia32_AddrModeS);
1118 } else if (tp2 == ia32_ImmSymConst) {
1119 tarval *tv = get_ia32_Immop_tarval(new_op1);
1120 long offs = get_tarval_long(tv);
1122 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1123 DBG_OPT_LEA3(op1, op2, node, new_op);
1125 add_ia32_am_offs_int(new_op, offs);
1126 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1127 set_ia32_am_sc_sign(new_op);
1128 set_ia32_am_flavour(new_op, ia32_am_O);
1129 set_ia32_am_support(new_op, ia32_am_Source);
1130 set_ia32_op_type(new_op, ia32_AddrModeS);
1132 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1133 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1134 tarval *restv = tarval_sub(tv1, tv2);
1136 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1138 new_op = new_rd_ia32_Const(dbgi, irg, block);
1139 set_ia32_Const_tarval(new_op, restv);
1140 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1143 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1145 } else if (imm_op) {
1146 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1147 tarval_classification_t class_tv, class_negtv;
1148 tarval *tv = get_ia32_Immop_tarval(imm_op);
1150 /* optimize tarvals */
1151 class_tv = classify_tarval(tv);
1152 class_negtv = classify_tarval(tarval_neg(tv));
1154 if (class_tv == TV_CLASSIFY_ONE) {
1155 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1156 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1157 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1159 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1160 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1161 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1162 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1168 /* This is a normal sub */
1169 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1171 /* set AM support */
1172 set_ia32_am_support(new_op, ia32_am_Full);
1174 fold_immediate(env, new_op, 2, 3);
1176 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1184 * Generates an ia32 DivMod with additional infrastructure for the
1185 * register allocator if needed.
1187 * @param env The transformation environment
1188 * @param dividend -no comment- :)
1189 * @param divisor -no comment- :)
1190 * @param dm_flav flavour_Div/Mod/DivMod
1191 * @return The created ia32 DivMod node
1193 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *node,
1194 ir_node *dividend, ir_node *divisor,
1195 ia32_op_flavour_t dm_flav) {
1196 ir_graph *irg = env->irg;
1197 dbg_info *dbgi = get_irn_dbg_info(node);
1198 ir_mode *mode = get_irn_mode(node);
1199 ir_node *block = transform_node(env, get_nodes_block(node));
1200 ir_node *res, *proj_div, *proj_mod;
1201 ir_node *edx_node, *cltd;
1202 ir_node *in_keep[1];
1203 ir_node *mem, *new_mem;
1204 ir_node *projs[pn_DivMod_max];
1205 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1206 ir_node *new_dividend = transform_node(env, dividend);
1207 ir_node *new_divisor = transform_node(env, divisor);
1209 ia32_collect_Projs(node, projs, pn_DivMod_max);
1213 mem = get_Div_mem(node);
1214 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Div_res));
1217 mem = get_Mod_mem(node);
1218 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Mod_res));
1220 case flavour_DivMod:
1221 mem = get_DivMod_mem(node);
1222 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1223 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1224 mode = proj_div ? get_irn_mode(proj_div) : get_irn_mode(proj_mod);
1227 panic("invalid divmod flavour!");
1229 new_mem = transform_node(env, mem);
1231 if (mode_is_signed(mode)) {
1232 /* in signed mode, we need to sign extend the dividend */
1233 cltd = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1234 new_dividend = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1235 edx_node = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1237 edx_node = new_rd_ia32_Const(dbgi, irg, block);
1238 add_irn_dep(edx_node, be_abi_get_start_barrier(env->cg->birg->abi));
1239 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1242 if(mode_is_signed(mode)) {
1243 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1245 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1248 /* Matze: code can't handle this at the moment... */
1250 /* set AM support */
1251 set_ia32_am_support(res, ia32_am_Source);
1254 set_ia32_n_res(res, 2);
1256 /* Only one proj is used -> We must add a second proj and */
1257 /* connect this one to a Keep node to eat up the second */
1258 /* destroyed register. */
1259 /* We also renumber the Firm projs into ia32 projs. */
1261 switch (get_irn_opcode(node)) {
1263 /* add Proj-Keep for mod res */
1264 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1265 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1268 /* add Proj-Keep for div res */
1269 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1270 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1273 /* check, which Proj-Keep, we need to add */
1274 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1275 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1277 if (proj_div && proj_mod) {
1278 /* nothing to be done */
1280 else if (! proj_div && ! proj_mod) {
1281 assert(0 && "Missing DivMod result proj");
1283 else if (! proj_div) {
1284 /* We have only mod result: add div res Proj-Keep */
1285 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1286 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1289 /* We have only div result: add mod res Proj-Keep */
1290 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1291 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1295 assert(0 && "Div, Mod, or DivMod expected.");
1299 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1306 * Wrapper for generate_DivMod. Sets flavour_Mod.
1308 * @param env The transformation environment
1310 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *node) {
1311 return generate_DivMod(env, node, get_Mod_left(node),
1312 get_Mod_right(node), flavour_Mod);
1316 * Wrapper for generate_DivMod. Sets flavour_Div.
1318 * @param env The transformation environment
1320 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *node) {
1321 return generate_DivMod(env, node, get_Div_left(node),
1322 get_Div_right(node), flavour_Div);
1326 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1328 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *node) {
1329 return generate_DivMod(env, node, get_DivMod_left(node),
1330 get_DivMod_right(node), flavour_DivMod);
1336 * Creates an ia32 floating Div.
1338 * @param env The transformation environment
1339 * @return The created ia32 xDiv node
1341 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *node) {
1342 ir_graph *irg = env->irg;
1343 dbg_info *dbgi = get_irn_dbg_info(node);
1344 ir_node *block = transform_node(env, get_nodes_block(node));
1345 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1347 ir_node *nomem = new_rd_NoMem(env->irg);
1348 ir_node *op1 = get_Quot_left(node);
1349 ir_node *op2 = get_Quot_right(node);
1350 ir_node *new_op1 = transform_node(env, op1);
1351 ir_node *new_op2 = transform_node(env, op2);
1354 if (USE_SSE2(env->cg)) {
1355 ir_mode *mode = get_irn_mode(op1);
1356 if (is_ia32_xConst(new_op2)) {
1357 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1358 set_ia32_am_support(new_op, ia32_am_None);
1359 copy_ia32_Immop_attr(new_op, new_op2);
1361 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1362 // Matze: disabled for now, spillslot coalescer fails
1363 //set_ia32_am_support(new_op, ia32_am_Source);
1365 set_ia32_ls_mode(new_op, mode);
1367 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1368 // Matze: disabled for now (spillslot coalescer fails)
1369 //set_ia32_am_support(new_op, ia32_am_Source);
1371 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1377 * Creates an ia32 Shl.
1379 * @param env The transformation environment
1380 * @return The created ia32 Shl node
1382 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *node) {
1383 return gen_shift_binop(env, node, get_Shl_left(node), get_Shl_right(node),
1390 * Creates an ia32 Shr.
1392 * @param env The transformation environment
1393 * @return The created ia32 Shr node
1395 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *node) {
1396 return gen_shift_binop(env, node, get_Shr_left(node),
1397 get_Shr_right(node), new_rd_ia32_Shr);
1403 * Creates an ia32 Sar.
1405 * @param env The transformation environment
1406 * @return The created ia32 Shrs node
1408 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) {
1409 return gen_shift_binop(env, node, get_Shrs_left(node),
1410 get_Shrs_right(node), new_rd_ia32_Sar);
1416 * Creates an ia32 RotL.
1418 * @param env The transformation environment
1419 * @param op1 The first operator
1420 * @param op2 The second operator
1421 * @return The created ia32 RotL node
1423 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node,
1424 ir_node *op1, ir_node *op2) {
1425 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Rol);
1431 * Creates an ia32 RotR.
1432 * NOTE: There is no RotR with immediate because this would always be a RotL
1433 * "imm-mode_size_bits" which can be pre-calculated.
1435 * @param env The transformation environment
1436 * @param op1 The first operator
1437 * @param op2 The second operator
1438 * @return The created ia32 RotR node
1440 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1,
1442 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Ror);
1448 * Creates an ia32 RotR or RotL (depending on the found pattern).
1450 * @param env The transformation environment
1451 * @return The created ia32 RotL or RotR node
1453 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) {
1454 ir_node *rotate = NULL;
1455 ir_node *op1 = get_Rot_left(node);
1456 ir_node *op2 = get_Rot_right(node);
1458 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1459 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1460 that means we can create a RotR instead of an Add and a RotL */
1462 if (get_irn_op(op2) == op_Add) {
1464 ir_node *left = get_Add_left(add);
1465 ir_node *right = get_Add_right(add);
1466 if (is_Const(right)) {
1467 tarval *tv = get_Const_tarval(right);
1468 ir_mode *mode = get_irn_mode(node);
1469 long bits = get_mode_size_bits(mode);
1471 if (get_irn_op(left) == op_Minus &&
1472 tarval_is_long(tv) &&
1473 get_tarval_long(tv) == bits)
1475 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1476 rotate = gen_RotR(env, node, op1, get_Minus_op(left));
1481 if (rotate == NULL) {
1482 rotate = gen_RotL(env, node, op1, op2);
1491 * Transforms a Minus node.
1493 * @param env The transformation environment
1494 * @param op The Minus operand
1495 * @return The created ia32 Minus node
1497 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *node, ir_node *op) {
1500 ir_graph *irg = env->irg;
1501 dbg_info *dbgi = get_irn_dbg_info(node);
1502 ir_node *block = transform_node(env, get_nodes_block(node));
1503 ir_mode *mode = get_irn_mode(node);
1506 if (mode_is_float(mode)) {
1507 ir_node *new_op = transform_node(env, op);
1509 if (USE_SSE2(env->cg)) {
1510 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1511 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1512 ir_node *nomem = new_rd_NoMem(irg);
1514 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1516 size = get_mode_size_bits(mode);
1517 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1519 set_ia32_am_sc(res, ent);
1520 set_ia32_op_type(res, ia32_AddrModeS);
1521 set_ia32_ls_mode(res, mode);
1523 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1526 res = gen_unop(env, node, op, new_rd_ia32_Neg);
1529 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1535 * Transforms a Minus node.
1537 * @param env The transformation environment
1538 * @return The created ia32 Minus node
1540 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *node) {
1541 return gen_Minus_ex(env, node, get_Minus_op(node));
1546 * Transforms a Not node.
1548 * @param env The transformation environment
1549 * @return The created ia32 Not node
1551 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *node) {
1552 ir_node *op = get_Not_op(node);
1554 assert (! mode_is_float(get_irn_mode(node)));
1555 return gen_unop(env, node, op, new_rd_ia32_Not);
1561 * Transforms an Abs node.
1563 * @param env The transformation environment
1564 * @return The created ia32 Abs node
1566 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *node) {
1567 ir_node *res, *p_eax, *p_edx;
1568 ir_graph *irg = env->irg;
1569 dbg_info *dbgi = get_irn_dbg_info(node);
1570 ir_node *block = transform_node(env, get_nodes_block(node));
1571 ir_mode *mode = get_irn_mode(node);
1572 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1573 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1574 ir_node *nomem = new_NoMem();
1575 ir_node *op = get_Abs_op(node);
1576 ir_node *new_op = transform_node(env, op);
1580 if (mode_is_float(mode)) {
1582 if (USE_SSE2(env->cg)) {
1583 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1585 size = get_mode_size_bits(mode);
1586 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1588 set_ia32_am_sc(res, ent);
1590 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1592 set_ia32_op_type(res, ia32_AddrModeS);
1593 set_ia32_ls_mode(res, mode);
1596 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1597 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1601 res = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1602 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1604 p_eax = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
1605 p_edx = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1607 res = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1608 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1610 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1611 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1620 * Transforms a Load.
1622 * @param env The transformation environment
1623 * @return the created ia32 Load node
1625 static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) {
1626 ir_graph *irg = env->irg;
1627 dbg_info *dbgi = get_irn_dbg_info(node);
1628 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1629 ir_mode *mode = get_Load_mode(node);
1630 ir_node *block = transform_node(env, get_nodes_block(node));
1631 ir_node *ptr = get_Load_ptr(node);
1632 ir_node *new_ptr = transform_node(env, ptr);
1633 ir_node *lptr = new_ptr;
1634 ir_node *mem = get_Load_mem(node);
1635 ir_node *new_mem = transform_node(env, mem);
1638 ia32_am_flavour_t am_flav = ia32_am_B;
1639 ir_node *projs[pn_Load_max];
1641 ia32_collect_Projs(node, projs, pn_Load_max);
1644 check for special case: the loaded value might not be used (optimized, volatile, ...)
1645 we add a Proj + Keep for volatile loads and ignore all other cases
1647 if (! be_get_Proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1648 /* add a result proj and a Keep to produce a pseudo use */
1649 ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res);
1650 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), irg, block, 1, &proj);
1653 /* address might be a constant (symconst or absolute address) */
1654 if (is_ia32_Const(new_ptr)) {
1659 if (mode_is_float(mode)) {
1661 if (USE_SSE2(env->cg)) {
1662 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1664 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem);
1667 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1670 /* base is a constant address */
1672 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1673 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1674 am_flav = ia32_am_N;
1676 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1677 long offs = get_tarval_long(tv);
1679 add_ia32_am_offs_int(new_op, offs);
1680 am_flav = ia32_am_O;
1684 set_ia32_am_support(new_op, ia32_am_Source);
1685 set_ia32_op_type(new_op, ia32_AddrModeS);
1686 set_ia32_am_flavour(new_op, am_flav);
1687 set_ia32_ls_mode(new_op, mode);
1689 /* make sure we are scheduled behind the intial IncSP/Barrier
1690 * to avoid spills being placed before it
1692 if(block == get_irg_start_block(irg)) {
1693 add_irn_dep(new_op, get_irg_frame(irg));
1696 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1704 * Transforms a Store.
1706 * @param env The transformation environment
1707 * @return the created ia32 Store node
1709 static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) {
1710 ir_graph *irg = env->irg;
1711 dbg_info *dbgi = get_irn_dbg_info(node);
1712 ir_node *block = transform_node(env, get_nodes_block(node));
1713 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1714 ir_node *ptr = get_Store_ptr(node);
1715 ir_node *new_ptr = transform_node(env, ptr);
1716 ir_node *sptr = new_ptr;
1717 ir_node *val = get_Store_value(node);
1718 ir_node *new_val = transform_node(env, val);
1719 ir_node *mem = get_Store_mem(node);
1720 ir_node *new_mem = transform_node(env, mem);
1721 ir_mode *mode = get_irn_mode(val);
1722 ir_node *sval = new_val;
1725 ia32_am_flavour_t am_flav = ia32_am_B;
1727 if (is_ia32_Const(new_val)) {
1728 assert(!mode_is_float(mode));
1732 /* address might be a constant (symconst or absolute address) */
1733 if (is_ia32_Const(new_ptr)) {
1738 if (mode_is_float(mode)) {
1740 if (USE_SSE2(env->cg)) {
1741 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, sval, new_mem);
1743 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, sval, new_mem);
1745 } else if (get_mode_size_bits(mode) == 8) {
1746 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg, sval, new_mem);
1748 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, sval, new_mem);
1751 /* stored const is an immediate value */
1752 if (is_ia32_Const(new_val)) {
1753 assert(!mode_is_float(mode));
1754 copy_ia32_Immop_attr(new_op, new_val);
1757 /* base is an constant address */
1759 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1760 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1761 am_flav = ia32_am_N;
1763 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1764 long offs = get_tarval_long(tv);
1766 add_ia32_am_offs_int(new_op, offs);
1767 am_flav = ia32_am_O;
1771 set_ia32_am_support(new_op, ia32_am_Dest);
1772 set_ia32_op_type(new_op, ia32_AddrModeD);
1773 set_ia32_am_flavour(new_op, am_flav);
1774 set_ia32_ls_mode(new_op, mode);
1776 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1784 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1786 * @param env The transformation environment
1787 * @return The transformed node.
1789 static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) {
1790 ir_graph *irg = env->irg;
1791 dbg_info *dbgi = get_irn_dbg_info(node);
1792 ir_node *block = transform_node(env, get_nodes_block(node));
1793 ir_node *sel = get_Cond_selector(node);
1794 ir_mode *sel_mode = get_irn_mode(sel);
1795 ir_node *res = NULL;
1796 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1797 ir_node *cnst, *expr;
1799 if (is_Proj(sel) && sel_mode == mode_b) {
1800 ir_node *nomem = new_NoMem();
1801 ir_node *pred = get_Proj_pred(sel);
1802 ir_node *cmp_a = get_Cmp_left(pred);
1803 ir_node *new_cmp_a = transform_node(env, cmp_a);
1804 ir_node *cmp_b = get_Cmp_right(pred);
1805 ir_node *new_cmp_b = transform_node(env, cmp_b);
1806 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1808 int pnc = get_Proj_proj(sel);
1809 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1810 pnc |= ia32_pn_Cmp_Unsigned;
1813 /* check if we can use a CondJmp with immediate */
1814 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1815 expr = get_expr_op(new_cmp_a, new_cmp_b);
1817 if (cnst != NULL && expr != NULL) {
1818 /* immop has to be the right operand, we might need to flip pnc */
1819 if(cnst != new_cmp_b) {
1820 pnc = get_inversed_pnc(pnc);
1823 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_needs_gp_reg(get_irn_mode(expr))) {
1824 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1825 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1827 /* a Cmp A =/!= 0 */
1828 ir_node *op1 = expr;
1829 ir_node *op2 = expr;
1832 /* check, if expr is an only once used And operation */
1833 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1834 op1 = get_irn_n(expr, 2);
1835 op2 = get_irn_n(expr, 3);
1837 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1839 res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2);
1840 set_ia32_pncode(res, pnc);
1843 copy_ia32_Immop_attr(res, expr);
1846 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1851 if (mode_is_float(cmp_mode)) {
1853 if (USE_SSE2(env->cg)) {
1854 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1855 set_ia32_ls_mode(res, cmp_mode);
1861 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1863 copy_ia32_Immop_attr(res, cnst);
1866 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1868 if (mode_is_float(cmp_mode)) {
1870 if (USE_SSE2(env->cg)) {
1871 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1872 set_ia32_ls_mode(res, cmp_mode);
1875 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1876 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1877 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1881 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1882 set_ia32_commutative(res);
1886 set_ia32_pncode(res, pnc);
1887 // Matze: disabled for now, because the default collect_spills_walker
1888 // is not able to detect the mode of the spilled value
1889 // moreover, the lea optimize phase freely exchanges left/right
1890 // without updating the pnc
1891 //set_ia32_am_support(res, ia32_am_Source);
1894 /* determine the smallest switch case value */
1895 int switch_min = INT_MAX;
1896 const ir_edge_t *edge;
1897 ir_node *new_sel = transform_node(env, sel);
1899 foreach_out_edge(node, edge) {
1900 int pn = get_Proj_proj(get_edge_src_irn(edge));
1901 switch_min = pn < switch_min ? pn : switch_min;
1905 /* if smallest switch case is not 0 we need an additional sub */
1906 res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1907 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1908 add_ia32_am_offs_int(res, -switch_min);
1909 set_ia32_am_flavour(res, ia32_am_OB);
1910 set_ia32_am_support(res, ia32_am_Source);
1911 set_ia32_op_type(res, ia32_AddrModeS);
1914 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T);
1915 set_ia32_pncode(res, get_Cond_defaultProj(node));
1918 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1925 * Transforms a CopyB node.
1927 * @param env The transformation environment
1928 * @return The transformed node.
1930 static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) {
1931 ir_node *res = NULL;
1932 ir_graph *irg = env->irg;
1933 dbg_info *dbgi = get_irn_dbg_info(node);
1934 ir_node *block = transform_node(env, get_nodes_block(node));
1935 ir_node *src = get_CopyB_src(node);
1936 ir_node *new_src = transform_node(env, src);
1937 ir_node *dst = get_CopyB_dst(node);
1938 ir_node *new_dst = transform_node(env, dst);
1939 ir_node *mem = get_CopyB_mem(node);
1940 ir_node *new_mem = transform_node(env, mem);
1941 int size = get_type_size_bytes(get_CopyB_type(node));
1942 ir_mode *dst_mode = get_irn_mode(dst);
1943 ir_mode *src_mode = get_irn_mode(src);
1947 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1948 /* then we need the size explicitly in ECX. */
1949 if (size >= 32 * 4) {
1950 rem = size & 0x3; /* size % 4 */
1953 res = new_rd_ia32_Const(dbgi, irg, block);
1954 add_irn_dep(res, be_abi_get_start_barrier(env->cg->birg->abi));
1955 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1957 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1958 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1960 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1961 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1962 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1963 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1964 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1967 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1968 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1970 /* ok: now attach Proj's because movsd will destroy esi and edi */
1971 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1972 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1973 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1976 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1984 * Transforms a Mux node into CMov.
1986 * @param env The transformation environment
1987 * @return The transformed node.
1989 static ir_node *gen_Mux(ia32_transform_env_t *env, ir_node *node) {
1990 ir_node *new_op = new_rd_ia32_CMov(env->dbgi, env->irg, env->block, \
1991 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1993 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1999 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
2000 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
2001 ir_node *psi_default);
2004 * Transforms a Psi node into CMov.
2006 * @param env The transformation environment
2007 * @return The transformed node.
2009 static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) {
2010 ia32_code_gen_t *cg = env->cg;
2011 ir_graph *irg = env->irg;
2012 dbg_info *dbgi = get_irn_dbg_info(node);
2013 ir_mode *mode = get_irn_mode(node);
2014 ir_node *block = transform_node(env, get_nodes_block(node));
2015 ir_node *cmp_proj = get_Mux_sel(node);
2016 ir_node *psi_true = get_Psi_val(node, 0);
2017 ir_node *psi_default = get_Psi_default(node);
2018 ir_node *new_psi_true = transform_node(env, psi_true);
2019 ir_node *new_psi_default = transform_node(env, psi_default);
2020 ir_node *noreg = ia32_new_NoReg_gp(cg);
2021 ir_node *nomem = new_rd_NoMem(irg);
2022 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
2023 ir_node *new_cmp_a, *new_cmp_b;
2027 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
2029 cmp = get_Proj_pred(cmp_proj);
2030 cmp_a = get_Cmp_left(cmp);
2031 cmp_b = get_Cmp_right(cmp);
2032 cmp_mode = get_irn_mode(cmp_a);
2033 new_cmp_a = transform_node(env, cmp_a);
2034 new_cmp_b = transform_node(env, cmp_b);
2036 pnc = get_Proj_proj(cmp_proj);
2037 if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2038 pnc |= ia32_pn_Cmp_Unsigned;
2041 if (mode_is_float(mode)) {
2042 /* floating point psi */
2045 /* 1st case: compare operands are float too */
2047 /* psi(cmp(a, b), t, f) can be done as: */
2048 /* tmp = cmp a, b */
2049 /* tmp2 = t and tmp */
2050 /* tmp3 = f and not tmp */
2051 /* res = tmp2 or tmp3 */
2053 /* in case the compare operands are int, we move them into xmm register */
2054 if (! mode_is_float(get_irn_mode(cmp_a))) {
2055 new_cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_a, node, mode_xmm);
2056 new_cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_b, node, mode_xmm);
2058 pnc |= 8; /* transform integer compare to fp compare */
2061 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2062 set_ia32_pncode(new_op, pnc);
2063 set_ia32_am_support(new_op, ia32_am_Source);
2064 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2066 and1 = new_rd_ia32_xAnd(dbgi, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2067 set_ia32_am_support(and1, ia32_am_None);
2068 set_ia32_commutative(and1);
2069 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2071 and2 = new_rd_ia32_xAndNot(dbgi, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2072 set_ia32_am_support(and2, ia32_am_None);
2073 set_ia32_commutative(and2);
2074 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2076 new_op = new_rd_ia32_xOr(dbgi, irg, block, noreg, noreg, and1, and2, nomem);
2077 set_ia32_am_support(new_op, ia32_am_None);
2078 set_ia32_commutative(new_op);
2079 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2083 new_op = new_rd_ia32_vfCMov(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2084 set_ia32_pncode(new_op, pnc);
2085 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2090 construct_binop_func *set_func = NULL;
2091 cmov_func_t *cmov_func = NULL;
2093 if (mode_is_float(get_irn_mode(cmp_a))) {
2094 /* 1st case: compare operands are floats */
2099 set_func = new_rd_ia32_xCmpSet;
2100 cmov_func = new_rd_ia32_xCmpCMov;
2104 set_func = new_rd_ia32_vfCmpSet;
2105 cmov_func = new_rd_ia32_vfCmpCMov;
2108 pnc &= ~0x8; /* fp compare -> int compare */
2111 /* 2nd case: compare operand are integer too */
2112 set_func = new_rd_ia32_CmpSet;
2113 cmov_func = new_rd_ia32_CmpCMov;
2116 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2117 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2118 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2119 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2120 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2121 set_ia32_pncode(new_op, pnc);
2123 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2124 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2125 /* we invert condition and set default to 0 */
2126 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2127 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2130 /* otherwise: use CMOVcc */
2131 new_op = new_rd_ia32_PsiCondCMov(dbgi, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2132 set_ia32_pncode(new_op, pnc);
2135 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2138 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2139 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2140 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2141 set_ia32_pncode(new_op, pnc);
2142 set_ia32_am_support(new_op, ia32_am_Source);
2144 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2145 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2146 /* we invert condition and set default to 0 */
2147 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2148 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2149 set_ia32_am_support(new_op, ia32_am_Source);
2152 /* otherwise: use CMOVcc */
2153 new_op = cmov_func(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2154 set_ia32_pncode(new_op, pnc);
2155 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2165 * Following conversion rules apply:
2169 * 1) n bit -> m bit n > m (downscale)
2171 * 2) n bit -> m bit n == m (sign change)
2173 * 3) n bit -> m bit n < m (upscale)
2174 * a) source is signed: movsx
2175 * b) source is unsigned: and with lower bits sets
2179 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2183 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2187 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2188 * x87 is mode_E internally, conversions happen only at load and store
2189 * in non-strict semantic
2193 * Create a conversion from x87 state register to general purpose.
2195 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) {
2196 ia32_code_gen_t *cg = env->cg;
2197 ir_graph *irg = env->irg;
2198 dbg_info *dbgi = get_irn_dbg_info(node);
2199 ir_node *block = transform_node(env, get_nodes_block(node));
2200 ir_node *noreg = ia32_new_NoReg_gp(cg);
2201 ir_node *op = get_Conv_op(node);
2202 ir_node *new_op = transform_node(env, op);
2203 ir_node *fist, *load;
2204 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2207 fist = new_rd_ia32_vfist(dbgi, irg, block,
2208 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2210 set_ia32_use_frame(fist);
2211 set_ia32_am_support(fist, ia32_am_Dest);
2212 set_ia32_op_type(fist, ia32_AddrModeD);
2213 set_ia32_am_flavour(fist, ia32_am_B);
2214 set_ia32_ls_mode(fist, mode_Iu);
2215 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2218 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2220 set_ia32_use_frame(load);
2221 set_ia32_am_support(load, ia32_am_Source);
2222 set_ia32_op_type(load, ia32_AddrModeS);
2223 set_ia32_am_flavour(load, ia32_am_B);
2224 set_ia32_ls_mode(load, mode_Iu);
2225 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2227 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2231 * Create a conversion from general purpose to x87 register
2233 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mode *src_mode) {
2235 ia32_code_gen_t *cg = env->cg;
2237 ir_graph *irg = env->irg;
2238 dbg_info *dbgi = get_irn_dbg_info(node);
2239 ir_node *block = transform_node(env, get_nodes_block(node));
2240 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2241 ir_node *nomem = new_NoMem();
2242 ir_node *op = get_Conv_op(node);
2243 ir_node *new_op = transform_node(env, op);
2244 ir_node *fild, *store;
2247 /* first convert to 32 bit if necessary */
2248 src_bits = get_mode_size_bits(src_mode);
2249 if (src_bits == 8) {
2250 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2251 set_ia32_am_support(new_op, ia32_am_Source);
2252 set_ia32_ls_mode(new_op, src_mode);
2253 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2254 } else if (src_bits < 32) {
2255 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2256 set_ia32_am_support(new_op, ia32_am_Source);
2257 set_ia32_ls_mode(new_op, src_mode);
2258 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2262 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2264 set_ia32_use_frame(store);
2265 set_ia32_am_support(store, ia32_am_Dest);
2266 set_ia32_op_type(store, ia32_AddrModeD);
2267 set_ia32_am_flavour(store, ia32_am_OB);
2268 set_ia32_ls_mode(store, mode_Iu);
2271 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2273 set_ia32_use_frame(fild);
2274 set_ia32_am_support(fild, ia32_am_Source);
2275 set_ia32_op_type(fild, ia32_AddrModeS);
2276 set_ia32_am_flavour(fild, ia32_am_OB);
2277 set_ia32_ls_mode(fild, mode_Iu);
2279 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2283 * Transforms a Conv node.
2285 * @param env The transformation environment
2286 * @return The created ia32 Conv node
2288 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) {
2289 ir_graph *irg = env->irg;
2290 dbg_info *dbgi = get_irn_dbg_info(node);
2291 ir_node *op = get_Conv_op(node);
2292 ir_mode *src_mode = get_irn_mode(op);
2293 ir_mode *tgt_mode = get_irn_mode(node);
2294 int src_bits = get_mode_size_bits(src_mode);
2295 int tgt_bits = get_mode_size_bits(tgt_mode);
2296 ir_node *block = transform_node(env, get_nodes_block(node));
2298 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2299 ir_node *nomem = new_rd_NoMem(irg);
2300 ir_node *new_op = transform_node(env, op);
2302 if (src_mode == tgt_mode) {
2303 /* this should be optimized already, but who knows... */
2304 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2305 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2309 if (mode_is_float(src_mode)) {
2310 /* we convert from float ... */
2311 if (mode_is_float(tgt_mode)) {
2313 if (USE_SSE2(env->cg)) {
2314 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2315 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2316 set_ia32_ls_mode(res, tgt_mode);
2318 // Matze: TODO what about strict convs?
2319 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2324 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2325 if (USE_SSE2(env->cg)) {
2326 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2327 set_ia32_ls_mode(res, src_mode);
2329 return gen_x87_fp_to_gp(env, node);
2333 /* we convert from int ... */
2334 if (mode_is_float(tgt_mode)) {
2337 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2338 if (USE_SSE2(env->cg)) {
2339 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2340 set_ia32_ls_mode(res, tgt_mode);
2341 if(src_bits == 32) {
2342 set_ia32_am_support(res, ia32_am_Source);
2345 return gen_x87_gp_to_fp(env, node, src_mode);
2349 ir_mode *smaller_mode;
2352 if (src_bits == tgt_bits) {
2353 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2357 if(src_bits < tgt_bits) {
2358 smaller_mode = src_mode;
2359 smaller_bits = src_bits;
2361 smaller_mode = tgt_mode;
2362 smaller_bits = tgt_bits;
2365 // The following is not correct, we can't change the mode,
2366 // maybe others are using the load too
2367 // better move this to a separate phase!
2370 if(is_Proj(new_op)) {
2371 /* load operations do already sign/zero extend, so we have
2372 * nothing left to do */
2373 ir_node *pred = get_Proj_pred(new_op);
2374 if(is_ia32_Load(pred)) {
2375 set_ia32_ls_mode(pred, smaller_mode);
2381 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2382 if (smaller_bits == 8) {
2383 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2384 set_ia32_ls_mode(res, smaller_mode);
2386 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2387 set_ia32_ls_mode(res, smaller_mode);
2389 set_ia32_am_support(res, ia32_am_Source);
2393 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2400 /********************************************
2403 * | |__ ___ _ __ ___ __| | ___ ___
2404 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2405 * | |_) | __/ | | | (_) | (_| | __/\__ \
2406 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2408 ********************************************/
2410 static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) {
2411 ir_node *new_op = NULL;
2412 ir_graph *irg = env->irg;
2413 dbg_info *dbgi = get_irn_dbg_info(node);
2414 ir_node *block = transform_node(env, get_nodes_block(node));
2415 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2416 ir_node *nomem = new_rd_NoMem(env->irg);
2417 ir_node *ptr = get_irn_n(node, 0);
2418 ir_node *new_ptr = transform_node(env, ptr);
2419 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2420 ir_mode *load_mode = get_irn_mode(node);
2424 if (mode_is_float(load_mode)) {
2426 if (USE_SSE2(env->cg)) {
2427 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2428 pn_res = pn_ia32_xLoad_res;
2429 proj_mode = mode_xmm;
2431 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem);
2432 pn_res = pn_ia32_vfld_res;
2433 proj_mode = mode_vfp;
2436 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2437 proj_mode = mode_Iu;
2438 pn_res = pn_ia32_Load_res;
2441 set_ia32_frame_ent(new_op, ent);
2442 set_ia32_use_frame(new_op);
2444 set_ia32_am_support(new_op, ia32_am_Source);
2445 set_ia32_op_type(new_op, ia32_AddrModeS);
2446 set_ia32_am_flavour(new_op, ia32_am_B);
2447 set_ia32_ls_mode(new_op, load_mode);
2448 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2450 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2452 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2456 * Transforms a FrameAddr into an ia32 Add.
2458 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) {
2459 ir_graph *irg = env->irg;
2460 dbg_info *dbgi = get_irn_dbg_info(node);
2461 ir_node *block = transform_node(env, get_nodes_block(node));
2462 ir_node *op = get_irn_n(node, 0);
2463 ir_node *new_op = transform_node(env, op);
2465 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2467 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2468 set_ia32_frame_ent(res, arch_get_frame_entity(env->cg->arch_env, node));
2469 set_ia32_am_support(res, ia32_am_Full);
2470 set_ia32_use_frame(res);
2471 set_ia32_am_flavour(res, ia32_am_OB);
2473 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2479 * Transforms a FrameLoad into an ia32 Load.
2481 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) {
2482 ir_node *new_op = NULL;
2483 ir_graph *irg = env->irg;
2484 dbg_info *dbgi = get_irn_dbg_info(node);
2485 ir_node *block = transform_node(env, get_nodes_block(node));
2486 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2487 ir_node *mem = get_irn_n(node, 0);
2488 ir_node *ptr = get_irn_n(node, 1);
2489 ir_node *new_mem = transform_node(env, mem);
2490 ir_node *new_ptr = transform_node(env, ptr);
2491 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2492 ir_mode *mode = get_type_mode(get_entity_type(ent));
2493 ir_node *projs[pn_Load_max];
2495 ia32_collect_Projs(node, projs, pn_Load_max);
2497 if (mode_is_float(mode)) {
2499 if (USE_SSE2(env->cg)) {
2500 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2503 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
2507 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2510 set_ia32_frame_ent(new_op, ent);
2511 set_ia32_use_frame(new_op);
2513 set_ia32_am_support(new_op, ia32_am_Source);
2514 set_ia32_op_type(new_op, ia32_AddrModeS);
2515 set_ia32_am_flavour(new_op, ia32_am_B);
2516 set_ia32_ls_mode(new_op, mode);
2518 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2525 * Transforms a FrameStore into an ia32 Store.
2527 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) {
2528 ir_node *new_op = NULL;
2529 ir_graph *irg = env->irg;
2530 dbg_info *dbgi = get_irn_dbg_info(node);
2531 ir_node *block = transform_node(env, get_nodes_block(node));
2532 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2533 ir_node *mem = get_irn_n(node, 0);
2534 ir_node *ptr = get_irn_n(node, 1);
2535 ir_node *val = get_irn_n(node, 2);
2536 ir_node *new_mem = transform_node(env, mem);
2537 ir_node *new_ptr = transform_node(env, ptr);
2538 ir_node *new_val = transform_node(env, val);
2539 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2540 ir_mode *mode = get_irn_mode(val);
2542 if (mode_is_float(mode)) {
2544 if (USE_SSE2(env->cg)) {
2545 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2547 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2549 } else if (get_mode_size_bits(mode) == 8) {
2550 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2552 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2555 set_ia32_frame_ent(new_op, ent);
2556 set_ia32_use_frame(new_op);
2558 set_ia32_am_support(new_op, ia32_am_Dest);
2559 set_ia32_op_type(new_op, ia32_AddrModeD);
2560 set_ia32_am_flavour(new_op, ia32_am_B);
2561 set_ia32_ls_mode(new_op, mode);
2563 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2569 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2571 static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
2572 ir_graph *irg = env->irg;
2575 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2576 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2577 ir_entity *ent = get_irg_entity(irg);
2578 ir_type *tp = get_entity_type(ent);
2581 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2582 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2584 int pn_ret_val, pn_ret_mem, arity, i;
2586 assert(ret_val != NULL);
2587 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env->cg)) {
2588 return duplicate_node(env, node);
2591 res_type = get_method_res_type(tp, 0);
2593 if (!is_Primitive_type(res_type)) {
2594 return duplicate_node(env, node);
2597 mode = get_type_mode(res_type);
2598 if (!mode_is_float(mode)) {
2599 return duplicate_node(env, node);
2602 assert(get_method_n_ress(tp) == 1);
2604 pn_ret_val = get_Proj_proj(ret_val);
2605 pn_ret_mem = get_Proj_proj(ret_mem);
2607 /* get the Barrier */
2608 barrier = get_Proj_pred(ret_val);
2610 /* get result input of the Barrier */
2611 ret_val = get_irn_n(barrier, pn_ret_val);
2612 new_ret_val = transform_node(env, ret_val);
2614 /* get memory input of the Barrier */
2615 ret_mem = get_irn_n(barrier, pn_ret_mem);
2616 new_ret_mem = transform_node(env, ret_mem);
2618 frame = get_irg_frame(irg);
2620 dbgi = get_irn_dbg_info(barrier);
2621 block = transform_node(env, get_nodes_block(barrier));
2623 /* store xmm0 onto stack */
2624 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, new_ret_val, new_ret_mem);
2625 set_ia32_ls_mode(sse_store, mode);
2626 set_ia32_op_type(sse_store, ia32_AddrModeD);
2627 set_ia32_use_frame(sse_store);
2628 set_ia32_am_flavour(sse_store, ia32_am_B);
2629 set_ia32_am_support(sse_store, ia32_am_Dest);
2632 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, sse_store);
2633 set_ia32_ls_mode(fld, mode);
2634 set_ia32_op_type(fld, ia32_AddrModeS);
2635 set_ia32_use_frame(fld);
2636 set_ia32_am_flavour(fld, ia32_am_B);
2637 set_ia32_am_support(fld, ia32_am_Source);
2639 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
2640 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
2641 arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2643 /* create a new barrier */
2644 arity = get_irn_arity(barrier);
2645 in = alloca(arity * sizeof(in[0]));
2646 for(i = 0; i < arity; ++i) {
2648 if(i == pn_ret_val) {
2650 } else if(i == pn_ret_mem) {
2653 ir_node *in = get_irn_n(barrier, i);
2654 new_in = transform_node(env, in);
2659 new_barrier = new_ir_node(dbgi, irg, block,
2660 get_irn_op(barrier), get_irn_mode(barrier),
2662 copy_node_attr(barrier, new_barrier);
2663 duplicate_deps(env, barrier, new_barrier);
2664 set_new_node(barrier, new_barrier);
2665 mark_irn_visited(barrier);
2667 /* transform normally */
2668 return duplicate_node(env, node);
2672 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2674 static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
2676 ir_graph *irg = env->irg;
2677 dbg_info *dbgi = get_irn_dbg_info(node);
2678 ir_node *block = transform_node(env, get_nodes_block(node));
2679 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
2680 ir_node *new_sz = transform_node(env, sz);
2681 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
2682 ir_node *new_sp = transform_node(env, sp);
2683 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2684 ir_node *nomem = new_NoMem();
2686 /* ia32 stack grows in reverse direction, make a SubSP */
2687 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2688 set_ia32_am_support(new_op, ia32_am_Source);
2689 fold_immediate(env, new_op, 2, 3);
2691 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2697 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
2699 static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
2701 ir_graph *irg = env->irg;
2702 dbg_info *dbgi = get_irn_dbg_info(node);
2703 ir_node *block = transform_node(env, get_nodes_block(node));
2704 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
2705 ir_node *new_sz = transform_node(env, sz);
2706 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
2707 ir_node *new_sp = transform_node(env, sp);
2708 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2709 ir_node *nomem = new_NoMem();
2711 /* ia32 stack grows in reverse direction, make an AddSP */
2712 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2713 set_ia32_am_support(new_op, ia32_am_Source);
2714 fold_immediate(env, new_op, 2, 3);
2716 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2722 * This function just sets the register for the Unknown node
2723 * as this is not done during register allocation because Unknown
2724 * is an "ignore" node.
2726 static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) {
2727 ir_mode *mode = get_irn_mode(node);
2729 if (mode_is_float(mode)) {
2730 if (USE_SSE2(env->cg))
2731 return ia32_new_Unknown_xmm(env->cg);
2733 return ia32_new_Unknown_vfp(env->cg);
2734 } else if (mode_needs_gp_reg(mode)) {
2735 return ia32_new_Unknown_gp(env->cg);
2737 assert(0 && "unsupported Unknown-Mode");
2744 * Change some phi modes
2746 static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
2747 ir_graph *irg = env->irg;
2748 dbg_info *dbgi = get_irn_dbg_info(node);
2749 ir_mode *mode = get_irn_mode(node);
2750 ir_node *block = transform_node(env, get_nodes_block(node));
2754 if(mode_needs_gp_reg(mode)) {
2755 // we shouldn't have any 64bit stuff around anymore
2756 assert(get_mode_size_bits(mode) <= 32);
2757 // all integer operations are on 32bit registers now
2759 } else if(mode_is_float(mode)) {
2760 assert(mode == mode_D || mode == mode_F);
2761 if (USE_SSE2(env->cg)) {
2768 /* phi nodes allow loops, so we use the old arguments for now
2769 * and fix this later */
2770 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
2771 get_irn_in(node) + 1);
2772 copy_node_attr(node, phi);
2773 duplicate_deps(env, node, phi);
2775 set_new_node(node, phi);
2777 /* put the preds in the worklist */
2778 arity = get_irn_arity(node);
2779 for(i = 0; i < arity; ++i) {
2780 ir_node *pred = get_irn_n(node, i);
2781 pdeq_putr(env->worklist, pred);
2787 /**********************************************************************
2790 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2791 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2792 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2793 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2795 **********************************************************************/
2797 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2799 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2802 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2803 ir_node *val, ir_node *mem);
2806 * Transforms a lowered Load into a "real" one.
2808 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) {
2809 ir_graph *irg = env->irg;
2810 dbg_info *dbgi = get_irn_dbg_info(node);
2811 ir_node *block = transform_node(env, get_nodes_block(node));
2812 ir_mode *mode = get_ia32_ls_mode(node);
2814 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2815 ir_node *ptr = get_irn_n(node, 0);
2816 ir_node *mem = get_irn_n(node, 1);
2817 ir_node *new_ptr = transform_node(env, ptr);
2818 ir_node *new_mem = transform_node(env, mem);
2821 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2822 lowering we have x87 nodes, so we need to enforce simulation.
2824 if (mode_is_float(mode)) {
2826 if (fp_unit == fp_x87)
2830 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
2832 set_ia32_am_support(new_op, ia32_am_Source);
2833 set_ia32_op_type(new_op, ia32_AddrModeS);
2834 set_ia32_am_flavour(new_op, ia32_am_OB);
2835 set_ia32_am_offs_int(new_op, 0);
2836 set_ia32_am_scale(new_op, 1);
2837 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
2838 if(is_ia32_am_sc_sign(node))
2839 set_ia32_am_sc_sign(new_op);
2840 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
2841 if(is_ia32_use_frame(node)) {
2842 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2843 set_ia32_use_frame(new_op);
2846 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2852 * Transforms a lowered Store into a "real" one.
2854 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) {
2855 ir_graph *irg = env->irg;
2856 dbg_info *dbgi = get_irn_dbg_info(node);
2857 ir_node *block = transform_node(env, get_nodes_block(node));
2858 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2859 ir_mode *mode = get_ia32_ls_mode(node);
2862 ia32_am_flavour_t am_flav = ia32_B;
2863 ir_node *ptr = get_irn_n(node, 0);
2864 ir_node *val = get_irn_n(node, 1);
2865 ir_node *mem = get_irn_n(node, 2);
2866 ir_node *new_ptr = transform_node(env, ptr);
2867 ir_node *new_val = transform_node(env, val);
2868 ir_node *new_mem = transform_node(env, mem);
2871 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2872 lowering we have x87 nodes, so we need to enforce simulation.
2874 if (mode_is_float(mode)) {
2876 if (fp_unit == fp_x87)
2880 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2882 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
2884 add_ia32_am_offs_int(new_op, am_offs);
2887 set_ia32_am_support(new_op, ia32_am_Dest);
2888 set_ia32_op_type(new_op, ia32_AddrModeD);
2889 set_ia32_am_flavour(new_op, am_flav);
2890 set_ia32_ls_mode(new_op, mode);
2891 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2892 set_ia32_use_frame(new_op);
2894 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2901 * Transforms an ia32_l_XXX into a "real" XXX node
2903 * @param env The transformation environment
2904 * @return the created ia32 XXX node
2906 #define GEN_LOWERED_OP(op) \
2907 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2908 ir_mode *mode = get_irn_mode(node); \
2909 if (mode_is_float(mode)) \
2911 return gen_binop(env, node, get_binop_left(node), \
2912 get_binop_right(node), new_rd_ia32_##op); \
2915 #define GEN_LOWERED_x87_OP(op) \
2916 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2918 FORCE_x87(env->cg); \
2919 new_op = gen_binop_float(env, node, get_binop_left(node), \
2920 get_binop_right(node), new_rd_ia32_##op); \
2924 #define GEN_LOWERED_UNOP(op) \
2925 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2926 return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \
2929 #define GEN_LOWERED_SHIFT_OP(op) \
2930 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2931 return gen_shift_binop(env, node, get_binop_left(node), \
2932 get_binop_right(node), new_rd_ia32_##op); \
2935 #define GEN_LOWERED_LOAD(op, fp_unit) \
2936 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2937 return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \
2940 #define GEN_LOWERED_STORE(op, fp_unit) \
2941 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2942 return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \
2949 GEN_LOWERED_OP(IMul)
2951 GEN_LOWERED_x87_OP(vfprem)
2952 GEN_LOWERED_x87_OP(vfmul)
2953 GEN_LOWERED_x87_OP(vfsub)
2955 GEN_LOWERED_UNOP(Neg)
2957 GEN_LOWERED_LOAD(vfild, fp_x87)
2958 GEN_LOWERED_LOAD(Load, fp_none)
2959 /*GEN_LOWERED_STORE(vfist, fp_x87)
2962 GEN_LOWERED_STORE(Store, fp_none)
2964 static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
2965 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2966 ir_graph *irg = env->irg;
2967 dbg_info *dbgi = get_irn_dbg_info(node);
2968 ir_node *block = transform_node(env, get_nodes_block(node));
2969 ir_node *left = get_binop_left(node);
2970 ir_node *right = get_binop_right(node);
2971 ir_node *new_left = transform_node(env, left);
2972 ir_node *new_right = transform_node(env, right);
2975 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
2976 clear_ia32_commutative(vfdiv);
2977 set_ia32_am_support(vfdiv, ia32_am_Source);
2978 fold_immediate(env, vfdiv, 2, 3);
2980 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env->cg, node));
2988 * Transforms a l_MulS into a "real" MulS node.
2990 * @param env The transformation environment
2991 * @return the created ia32 Mul node
2993 static ir_node *gen_ia32_l_Mul(ia32_transform_env_t *env, ir_node *node) {
2994 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2995 ir_graph *irg = env->irg;
2996 dbg_info *dbgi = get_irn_dbg_info(node);
2997 ir_node *block = transform_node(env, get_nodes_block(node));
2998 ir_node *left = get_binop_left(node);
2999 ir_node *right = get_binop_right(node);
3000 ir_node *new_left = transform_node(env, left);
3001 ir_node *new_right = transform_node(env, right);
3004 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3005 /* and then skip the result Proj, because all needed Projs are already there. */
3006 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3007 clear_ia32_commutative(muls);
3008 set_ia32_am_support(muls, ia32_am_Source);
3009 fold_immediate(env, muls, 2, 3);
3011 /* check if EAX and EDX proj exist, add missing one */
3012 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3013 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3014 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3016 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env->cg, node));
3021 GEN_LOWERED_SHIFT_OP(Shl)
3022 GEN_LOWERED_SHIFT_OP(Shr)
3023 GEN_LOWERED_SHIFT_OP(Sar)
3026 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3027 * op1 - target to be shifted
3028 * op2 - contains bits to be shifted into target
3030 * Only op3 can be an immediate.
3032 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *node,
3033 ir_node *op1, ir_node *op2,
3035 ir_node *new_op = NULL;
3036 ir_graph *irg = env->irg;
3037 dbg_info *dbgi = get_irn_dbg_info(node);
3038 ir_node *block = transform_node(env, get_nodes_block(node));
3039 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3040 ir_node *nomem = new_NoMem();
3042 ir_node *new_op1 = transform_node(env, op1);
3043 ir_node *new_op2 = transform_node(env, op2);
3044 ir_node *new_count = transform_node(env, count);
3047 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3049 /* Check if immediate optimization is on and */
3050 /* if it's an operation with immediate. */
3051 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3053 /* Limit imm_op within range imm8 */
3055 tv = get_ia32_Immop_tarval(imm_op);
3058 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3059 set_ia32_Immop_tarval(imm_op, tv);
3066 /* integer operations */
3068 /* This is ShiftD with const */
3069 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3071 if (is_ia32_l_ShlD(node))
3072 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3073 new_op1, new_op2, noreg, nomem);
3075 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3076 new_op1, new_op2, noreg, nomem);
3077 copy_ia32_Immop_attr(new_op, imm_op);
3080 /* This is a normal ShiftD */
3081 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3082 if (is_ia32_l_ShlD(node))
3083 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3084 new_op1, new_op2, new_count, nomem);
3086 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3087 new_op1, new_op2, new_count, nomem);
3090 /* set AM support */
3091 // Matze: node has unsupported format (6inputs)
3092 //set_ia32_am_support(new_op, ia32_am_Dest);
3094 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3096 set_ia32_emit_cl(new_op);
3101 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env, ir_node *node) {
3102 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3103 get_irn_n(node, 1), get_irn_n(node, 2));
3106 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env, ir_node *node) {
3107 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3108 get_irn_n(node, 1), get_irn_n(node, 2));
3112 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3114 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) {
3115 ia32_code_gen_t *cg = env->cg;
3116 ir_node *res = NULL;
3117 ir_graph *irg = env->irg;
3118 dbg_info *dbgi = get_irn_dbg_info(node);
3119 ir_node *block = transform_node(env, get_nodes_block(node));
3120 ir_node *ptr = get_irn_n(node, 0);
3121 ir_node *val = get_irn_n(node, 1);
3122 ir_node *new_val = transform_node(env, val);
3123 ir_node *mem = get_irn_n(node, 2);
3124 ir_node *noreg, *new_ptr, *new_mem;
3130 noreg = ia32_new_NoReg_gp(cg);
3131 new_mem = transform_node(env, mem);
3132 new_ptr = transform_node(env, ptr);
3134 /* Store x87 -> MEM */
3135 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3136 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3137 set_ia32_use_frame(res);
3138 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3139 set_ia32_am_support(res, ia32_am_Dest);
3140 set_ia32_am_flavour(res, ia32_B);
3141 set_ia32_op_type(res, ia32_AddrModeD);
3143 /* Load MEM -> SSE */
3144 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3145 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3146 set_ia32_use_frame(res);
3147 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3148 set_ia32_am_support(res, ia32_am_Source);
3149 set_ia32_am_flavour(res, ia32_B);
3150 set_ia32_op_type(res, ia32_AddrModeS);
3151 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3157 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3159 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) {
3160 ia32_code_gen_t *cg = env->cg;
3161 ir_graph *irg = env->irg;
3162 dbg_info *dbgi = get_irn_dbg_info(node);
3163 ir_node *block = transform_node(env, get_nodes_block(node));
3164 ir_node *res = NULL;
3165 ir_node *ptr = get_irn_n(node, 0);
3166 ir_node *val = get_irn_n(node, 1);
3167 ir_node *mem = get_irn_n(node, 2);
3168 ir_entity *fent = get_ia32_frame_ent(node);
3169 ir_mode *lsmode = get_ia32_ls_mode(node);
3170 ir_node *new_val = transform_node(env, val);
3171 ir_node *noreg, *new_ptr, *new_mem;
3174 if (!USE_SSE2(cg)) {
3175 /* SSE unit is not used -> skip this node. */
3179 noreg = ia32_new_NoReg_gp(cg);
3180 new_val = transform_node(env, val);
3181 new_ptr = transform_node(env, ptr);
3182 new_mem = transform_node(env, mem);
3184 /* Store SSE -> MEM */
3185 if (is_ia32_xLoad(skip_Proj(new_val))) {
3186 ir_node *ld = skip_Proj(new_val);
3188 /* we can vfld the value directly into the fpu */
3189 fent = get_ia32_frame_ent(ld);
3190 ptr = get_irn_n(ld, 0);
3191 offs = get_ia32_am_offs_int(ld);
3193 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3194 set_ia32_frame_ent(res, fent);
3195 set_ia32_use_frame(res);
3196 set_ia32_ls_mode(res, lsmode);
3197 set_ia32_am_support(res, ia32_am_Dest);
3198 set_ia32_am_flavour(res, ia32_B);
3199 set_ia32_op_type(res, ia32_AddrModeD);
3203 /* Load MEM -> x87 */
3204 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
3205 set_ia32_frame_ent(res, fent);
3206 set_ia32_use_frame(res);
3207 set_ia32_ls_mode(res, lsmode);
3208 add_ia32_am_offs_int(res, offs);
3209 set_ia32_am_support(res, ia32_am_Source);
3210 set_ia32_am_flavour(res, ia32_B);
3211 set_ia32_op_type(res, ia32_AddrModeS);
3212 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3217 /*********************************************************
3220 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3221 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3222 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3223 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3225 *********************************************************/
3228 * the BAD transformer.
3230 static ir_node *bad_transform(ia32_transform_env_t *env, ir_node *node) {
3231 panic("No transform function for %+F available.\n", node);
3235 static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) {
3236 /* end has to be duplicated manually because we need a dynamic in array */
3237 ir_graph *irg = env->irg;
3238 dbg_info *dbgi = get_irn_dbg_info(node);
3239 ir_node *block = transform_node(env, get_nodes_block(node));
3243 new_end = new_ir_node(dbgi, irg, block, op_End, mode_X, -1, NULL);
3244 copy_node_attr(node, new_end);
3245 duplicate_deps(env, node, new_end);
3247 set_irg_end(irg, new_end);
3248 set_new_node(new_end, new_end);
3250 /* transform preds */
3251 arity = get_irn_arity(node);
3252 for(i = 0; i < arity; ++i) {
3253 ir_node *in = get_irn_n(node, i);
3254 ir_node *new_in = transform_node(env, in);
3256 add_End_keepalive(new_end, new_in);
3262 static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) {
3263 ir_graph *irg = env->irg;
3264 dbg_info *dbgi = get_irn_dbg_info(node);
3265 ir_node *start_block = env->old_anchors[anchor_start_block];
3270 * We replace the ProjX from the start node with a jump,
3271 * so the startblock has no preds anymore now
3273 if(node == start_block) {
3274 return new_rd_Block(dbgi, irg, 0, NULL);
3277 /* we use the old blocks for now, because jumps allow cycles in the graph
3278 * we have to fix this later */
3279 block = new_ir_node(dbgi, irg, NULL, get_irn_op(node), get_irn_mode(node),
3280 get_irn_arity(node), get_irn_in(node) + 1);
3281 copy_node_attr(node, block);
3283 #ifdef DEBUG_libfirm
3284 block->node_nr = node->node_nr;
3286 set_new_node(node, block);
3288 /* put the preds in the worklist */
3289 arity = get_irn_arity(node);
3290 for(i = 0; i < arity; ++i) {
3291 ir_node *in = get_irn_n(node, i);
3292 pdeq_putr(env->worklist, in);
3298 static ir_node *gen_Proj_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
3299 ir_graph *irg = env->irg;
3300 ir_node *block = transform_node(env, get_nodes_block(node));
3301 dbg_info *dbgi = get_irn_dbg_info(node);
3302 ir_node *pred = get_Proj_pred(node);
3303 ir_node *new_pred = transform_node(env, pred);
3304 long proj = get_Proj_proj(node);
3306 if(proj == pn_be_AddSP_res) {
3307 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3308 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3310 } else if(proj == pn_be_AddSP_M) {
3311 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3315 return new_rd_Unknown(irg, get_irn_mode(node));
3318 static ir_node *gen_Proj_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
3319 ir_graph *irg = env->irg;
3320 ir_node *block = transform_node(env, get_nodes_block(node));
3321 dbg_info *dbgi = get_irn_dbg_info(node);
3322 ir_node *pred = get_Proj_pred(node);
3323 ir_node *new_pred = transform_node(env, pred);
3324 long proj = get_Proj_proj(node);
3326 if(proj == pn_be_SubSP_res) {
3327 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3328 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3330 } else if(proj == pn_be_SubSP_M) {
3331 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3335 return new_rd_Unknown(irg, get_irn_mode(node));
3338 static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) {
3339 ir_graph *irg = env->irg;
3340 ir_node *block = transform_node(env, get_nodes_block(node));
3341 dbg_info *dbgi = get_irn_dbg_info(node);
3342 ir_node *pred = get_Proj_pred(node);
3343 ir_node *new_pred = transform_node(env, pred);
3344 long proj = get_Proj_proj(node);
3346 /* renumber the proj */
3347 if(is_ia32_Load(new_pred)) {
3348 if(proj == pn_Load_res) {
3349 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3350 } else if(proj == pn_Load_M) {
3351 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3353 } else if(is_ia32_xLoad(new_pred)) {
3354 if(proj == pn_Load_res) {
3355 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3356 } else if(proj == pn_Load_M) {
3357 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3359 } else if(is_ia32_vfld(new_pred)) {
3360 if(proj == pn_Load_res) {
3361 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3362 } else if(proj == pn_Load_M) {
3363 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3368 return new_rd_Unknown(irg, get_irn_mode(node));
3371 static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) {
3372 ir_graph *irg = env->irg;
3373 dbg_info *dbgi = get_irn_dbg_info(node);
3374 ir_node *block = transform_node(env, get_nodes_block(node));
3375 ir_mode *mode = get_irn_mode(node);
3377 ir_node *pred = get_Proj_pred(node);
3378 ir_node *new_pred = transform_node(env, pred);
3379 long proj = get_Proj_proj(node);
3381 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3383 switch(get_irn_opcode(pred)) {
3387 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3389 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3397 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3399 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3407 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3408 case pn_DivMod_res_div:
3409 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3410 case pn_DivMod_res_mod:
3411 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3421 return new_rd_Unknown(irg, mode);
3424 static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node)
3426 ir_graph *irg = env->irg;
3427 dbg_info *dbgi = get_irn_dbg_info(node);
3428 ir_node *block = transform_node(env, get_nodes_block(node));
3429 ir_mode *mode = get_irn_mode(node);
3431 ir_node *pred = get_Proj_pred(node);
3432 ir_node *new_pred = transform_node(env, pred);
3433 long proj = get_Proj_proj(node);
3436 case pn_CopyB_M_regular:
3437 if(is_ia32_CopyB_i(new_pred)) {
3438 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3440 } else if(is_ia32_CopyB(new_pred)) {
3441 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3450 return new_rd_Unknown(irg, mode);
3453 static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node)
3455 ir_graph *irg = env->irg;
3456 dbg_info *dbgi = get_irn_dbg_info(node);
3457 ir_node *block = transform_node(env, get_nodes_block(node));
3458 ir_mode *mode = get_irn_mode(node);
3460 ir_node *pred = get_Proj_pred(node);
3461 ir_node *new_pred = transform_node(env, pred);
3462 long proj = get_Proj_proj(node);
3465 case pn_ia32_l_vfdiv_M:
3466 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3467 case pn_ia32_l_vfdiv_res:
3468 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3473 return new_rd_Unknown(irg, mode);
3476 static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node)
3478 ir_graph *irg = env->irg;
3479 dbg_info *dbgi = get_irn_dbg_info(node);
3480 ir_node *block = transform_node(env, get_nodes_block(node));
3481 ir_mode *mode = get_irn_mode(node);
3483 ir_node *pred = get_Proj_pred(node);
3484 ir_node *new_pred = transform_node(env, pred);
3485 long proj = get_Proj_proj(node);
3489 if(is_ia32_xDiv(new_pred)) {
3490 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3492 } else if(is_ia32_vfdiv(new_pred)) {
3493 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3498 if(is_ia32_xDiv(new_pred)) {
3499 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
3501 } else if(is_ia32_vfdiv(new_pred)) {
3502 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
3511 return new_rd_Unknown(irg, mode);
3514 static ir_node *gen_Proj_tls(ia32_transform_env_t *env, ir_node *node) {
3515 ir_graph *irg = env->irg;
3516 //dbg_info *dbgi = get_irn_dbg_info(node);
3517 dbg_info *dbgi = NULL;
3518 ir_node *block = transform_node(env, get_nodes_block(node));
3520 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3525 static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) {
3526 ir_graph *irg = env->irg;
3527 dbg_info *dbgi = get_irn_dbg_info(node);
3528 long proj = get_Proj_proj(node);
3529 ir_mode *mode = get_irn_mode(node);
3530 ir_node *block = transform_node(env, get_nodes_block(node));
3532 ir_node *call = get_Proj_pred(node);
3533 ir_node *new_call = transform_node(env, call);
3534 const arch_register_class_t *cls;
3536 /* The following is kinda tricky: If we're using SSE, then we have to
3537 * move the result value of the call in floating point registers to an
3538 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3539 * after the call, we have to make sure to correctly make the
3540 * MemProj and the result Proj use these 2 nodes
3542 if(proj == pn_be_Call_M_regular) {
3543 // get new node for result, are we doing the sse load/store hack?
3544 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3545 ir_node *call_res_new;
3546 ir_node *call_res_pred = NULL;
3548 if(call_res != NULL) {
3549 call_res_new = transform_node(env, call_res);
3550 call_res_pred = get_Proj_pred(call_res_new);
3553 if(call_res_pred == NULL || be_is_Call(call_res_pred)) {
3554 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3556 assert(is_ia32_xLoad(call_res_pred));
3557 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3560 if(proj == pn_be_Call_first_res && mode_is_float(mode)
3561 && USE_SSE2(env->cg)) {
3563 ir_node *frame = get_irg_frame(irg);
3564 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3566 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3568 const arch_register_class_t *cls;
3570 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3571 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3573 /* store st(0) onto stack */
3574 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3576 set_ia32_ls_mode(fstp, mode);
3577 set_ia32_op_type(fstp, ia32_AddrModeD);
3578 set_ia32_use_frame(fstp);
3579 set_ia32_am_flavour(fstp, ia32_am_B);
3580 set_ia32_am_support(fstp, ia32_am_Dest);
3582 /* load into SSE register */
3583 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3584 set_ia32_ls_mode(sse_load, mode);
3585 set_ia32_op_type(sse_load, ia32_AddrModeS);
3586 set_ia32_use_frame(sse_load);
3587 set_ia32_am_flavour(sse_load, ia32_am_B);
3588 set_ia32_am_support(sse_load, ia32_am_Source);
3590 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3592 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3594 /* get a Proj representing a caller save register */
3595 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3596 assert(is_Proj(p) && "Proj expected.");
3598 /* user of the the proj is the Keep */
3599 p = get_edge_src_irn(get_irn_out_edge_first(p));
3600 assert(be_is_Keep(p) && "Keep expected.");
3602 /* keep the result */
3603 cls = arch_get_irn_reg_class(env->cg->arch_env, sse_load, -1);
3604 keepin[0] = sse_load;
3605 be_new_Keep(cls, irg, block, 1, keepin);
3610 /* transform call modes */
3611 if(mode != mode_M) {
3612 cls = arch_get_irn_reg_class(env->cg->arch_env, node, -1);
3616 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3619 static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) {
3620 ir_graph *irg = env->irg;
3621 dbg_info *dbgi = get_irn_dbg_info(node);
3622 ir_node *pred = get_Proj_pred(node);
3623 long proj = get_Proj_proj(node);
3625 if(is_Store(pred) || be_is_FrameStore(pred)) {
3626 if(proj == pn_Store_M) {
3627 return transform_node(env, pred);
3630 return new_r_Bad(irg);
3632 } else if(is_Load(pred) || be_is_FrameLoad(pred)) {
3633 return gen_Proj_Load(env, node);
3634 } else if(is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3635 return gen_Proj_DivMod(env, node);
3636 } else if(is_CopyB(pred)) {
3637 return gen_Proj_CopyB(env, node);
3638 } else if(is_Quot(pred)) {
3639 return gen_Proj_Quot(env, node);
3640 } else if(is_ia32_l_vfdiv(pred)) {
3641 return gen_Proj_l_vfdiv(env, node);
3642 } else if(be_is_SubSP(pred)) {
3643 return gen_Proj_be_SubSP(env, node);
3644 } else if(be_is_AddSP(pred)) {
3645 return gen_Proj_be_AddSP(env, node);
3646 } else if(be_is_Call(pred)) {
3647 return gen_Proj_be_Call(env, node);
3648 } else if(get_irn_op(pred) == op_Start) {
3649 if(proj == pn_Start_X_initial_exec) {
3650 ir_node *block = get_nodes_block(pred);
3653 block = transform_node(env, block);
3654 // we exchange the ProjX with a jump
3655 jump = new_rd_Jmp(dbgi, irg, block);
3656 ir_fprintf(stderr, "created jump: %+F\n", jump);
3659 if(node == env->old_anchors[anchor_tls]) {
3660 return gen_Proj_tls(env, node);
3663 ir_node *new_pred = transform_node(env, pred);
3664 ir_node *block = transform_node(env, get_nodes_block(node));
3665 ir_mode *mode = get_irn_mode(node);
3666 if (mode_needs_gp_reg(mode)) {
3667 return new_r_Proj(irg, block, new_pred, mode_Iu, get_Proj_proj(node));
3671 return duplicate_node(env, node);
3675 * Enters all transform functions into the generic pointer
3677 static void register_transformers(void) {
3678 ir_op *op_Max, *op_Min, *op_Mulh;
3680 /* first clear the generic function pointer for all ops */
3681 clear_irp_opcodes_generic_func();
3683 #define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3684 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
3723 /* transform ops from intrinsic lowering */
3743 /* GEN(ia32_l_vfist); TODO */
3745 GEN(ia32_l_X87toSSE);
3746 GEN(ia32_l_SSEtoX87);
3751 /* we should never see these nodes */
3766 /* handle generic backend nodes */
3776 /* set the register for all Unknown nodes */
3779 op_Max = get_op_Max();
3782 op_Min = get_op_Min();
3785 op_Mulh = get_op_Mulh();
3793 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
3797 int deps = get_irn_deps(old_node);
3799 for(i = 0; i < deps; ++i) {
3800 ir_node *dep = get_irn_dep(old_node, i);
3801 ir_node *new_dep = transform_node(env, dep);
3803 add_irn_dep(new_node, new_dep);
3807 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node)
3809 ir_graph *irg = env->irg;
3810 dbg_info *dbgi = get_irn_dbg_info(node);
3811 ir_mode *mode = get_irn_mode(node);
3812 ir_op *op = get_irn_op(node);
3817 block = transform_node(env, get_nodes_block(node));
3819 arity = get_irn_arity(node);
3820 if(op->opar == oparity_dynamic) {
3821 new_node = new_ir_node(dbgi, irg, block, op, mode, -1, NULL);
3822 for(i = 0; i < arity; ++i) {
3823 ir_node *in = get_irn_n(node, i);
3824 in = transform_node(env, in);
3825 add_irn_n(new_node, in);
3828 ir_node **ins = alloca(arity * sizeof(ins[0]));
3829 for(i = 0; i < arity; ++i) {
3830 ir_node *in = get_irn_n(node, i);
3831 ins[i] = transform_node(env, in);
3834 new_node = new_ir_node(dbgi, irg, block, op, mode, arity, ins);
3837 copy_node_attr(node, new_node);
3838 duplicate_deps(env, node, new_node);
3843 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node)
3846 ir_op *op = get_irn_op(node);
3848 if(irn_visited(node)) {
3849 assert(get_new_node(node) != NULL);
3850 return get_new_node(node);
3853 mark_irn_visited(node);
3854 DEBUG_ONLY(set_new_node(node, NULL));
3856 if (op->ops.generic) {
3857 transform_func *transform = (transform_func *)op->ops.generic;
3859 new_node = (*transform)(env, node);
3860 assert(new_node != NULL);
3862 new_node = duplicate_node(env, node);
3864 //ir_fprintf(stderr, "%+F -> %+F\n", node, new_node);
3866 set_new_node(node, new_node);
3867 mark_irn_visited(new_node);
3868 hook_dead_node_elim_subst(current_ir_graph, node, new_node);
3872 static void fix_loops(ia32_transform_env_t *env, ir_node *node)
3876 if(irn_visited(node))
3878 mark_irn_visited(node);
3880 assert(node_is_in_irgs_storage(env->irg, node));
3882 if(!is_Block(node)) {
3883 ir_node *block = get_nodes_block(node);
3884 ir_node *new_block = (ir_node*) get_irn_link(block);
3886 if(new_block != NULL) {
3887 set_nodes_block(node, new_block);
3891 fix_loops(env, block);
3894 arity = get_irn_arity(node);
3895 for(i = 0; i < arity; ++i) {
3896 ir_node *in = get_irn_n(node, i);
3897 ir_node *new = (ir_node*) get_irn_link(in);
3899 if(new != NULL && new != in) {
3900 set_irn_n(node, i, new);
3907 arity = get_irn_deps(node);
3908 for(i = 0; i < arity; ++i) {
3909 ir_node *in = get_irn_dep(node, i);
3910 ir_node *new = (ir_node*) get_irn_link(in);
3912 if(new != NULL && new != in) {
3913 set_irn_dep(node, i, new);
3921 static void pre_transform_node(ir_node **place, ia32_transform_env_t *env)
3926 *place = transform_node(env, *place);
3929 static void transform_nodes(ia32_code_gen_t *cg)
3932 ir_graph *irg = cg->irg;
3934 ia32_transform_env_t env;
3936 hook_dead_node_elim(irg, 1);
3938 inc_irg_visited(irg);
3942 env.visited = get_irg_visited(irg);
3943 env.worklist = new_pdeq();
3944 env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
3946 old_end = get_irg_end(irg);
3948 /* put all anchor nodes in the worklist */
3949 for(i = 0; i < anchor_max; ++i) {
3950 ir_node *anchor = irg->anchors[i];
3953 pdeq_putr(env.worklist, anchor);
3956 env.old_anchors[i] = anchor;
3957 // and set it to NULL to make sure we don't accidently use it
3958 irg->anchors[i] = NULL;
3961 // pre transform some anchors (so they are available in the other transform
3963 set_irg_bad(irg, transform_node(&env, env.old_anchors[anchor_bad]));
3964 set_irg_no_mem(irg, transform_node(&env, env.old_anchors[anchor_no_mem]));
3965 set_irg_start_block(irg, transform_node(&env, env.old_anchors[anchor_start_block]));
3966 set_irg_start(irg, transform_node(&env, env.old_anchors[anchor_start]));
3967 set_irg_frame(irg, transform_node(&env, env.old_anchors[anchor_frame]));
3969 pre_transform_node(&cg->unknown_gp, &env);
3970 pre_transform_node(&cg->unknown_vfp, &env);
3971 pre_transform_node(&cg->unknown_xmm, &env);
3972 pre_transform_node(&cg->noreg_gp, &env);
3973 pre_transform_node(&cg->noreg_vfp, &env);
3974 pre_transform_node(&cg->noreg_xmm, &env);
3976 /* process worklist (this should transform all nodes in the graph) */
3977 while(!pdeq_empty(env.worklist)) {
3978 ir_node *node = pdeq_getl(env.worklist);
3979 transform_node(&env, node);
3982 /* fix loops and set new anchors*/
3983 inc_irg_visited(irg);
3984 for(i = 0; i < anchor_max; ++i) {
3985 ir_node *anchor = env.old_anchors[i];
3989 anchor = get_irn_link(anchor);
3990 fix_loops(&env, anchor);
3991 assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
3992 irg->anchors[i] = anchor;
3995 del_pdeq(env.worklist);
3997 hook_dead_node_elim(irg, 0);
4000 void ia32_transform_graph(ia32_code_gen_t *cg)
4002 ir_graph *irg = cg->irg;
4003 be_irg_t *birg = cg->birg;
4004 ir_graph *old_current_ir_graph = current_ir_graph;
4005 int old_interprocedural_view = get_interprocedural_view();
4006 struct obstack *old_obst = NULL;
4007 struct obstack *new_obst = NULL;
4009 current_ir_graph = irg;
4010 set_interprocedural_view(0);
4011 register_transformers();
4013 /* most analysis info is wrong after transformation */
4014 free_callee_info(irg);
4016 irg->outs_state = outs_none;
4018 free_loop_information(irg);
4019 set_irg_doms_inconsistent(irg);
4020 be_invalidate_liveness(birg);
4021 be_invalidate_dom_front(birg);
4023 /* create a new obstack */
4024 old_obst = irg->obst;
4025 new_obst = xmalloc(sizeof(*new_obst));
4026 obstack_init(new_obst);
4027 irg->obst = new_obst;
4028 irg->last_node_idx = 0;
4030 /* create new value table for CSE */
4031 del_identities(irg->value_table);
4032 irg->value_table = new_identities();
4034 /* do the main transformation */
4035 transform_nodes(cg);
4037 /* we don't want the globals anchor anymore */
4038 set_irg_globals(irg, new_r_Bad(irg));
4040 /* free the old obstack */
4041 obstack_free(old_obst, 0);
4045 current_ir_graph = old_current_ir_graph;
4046 set_interprocedural_view(old_interprocedural_view);
4048 /* recalculate edges */
4049 edges_deactivate(irg);
4050 edges_activate(irg);
4054 * Transforms a psi condition.
4056 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
4059 /* if the mode is target mode, we have already seen this part of the tree */
4060 if (get_irn_mode(cond) == mode)
4063 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
4065 set_irn_mode(cond, mode);
4067 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
4068 ir_node *in = get_irn_n(cond, i);
4070 /* if in is a compare: transform into Set/xCmp */
4072 ir_node *new_op = NULL;
4073 ir_node *cmp = get_Proj_pred(in);
4074 ir_node *cmp_a = get_Cmp_left(cmp);
4075 ir_node *cmp_b = get_Cmp_right(cmp);
4076 dbg_info *dbgi = get_irn_dbg_info(cmp);
4077 ir_graph *irg = get_irn_irg(cmp);
4078 ir_node *block = get_nodes_block(cmp);
4079 ir_node *noreg = ia32_new_NoReg_gp(cg);
4080 ir_node *nomem = new_rd_NoMem(irg);
4081 int pnc = get_Proj_proj(in);
4083 /* this is a compare */
4084 if (mode_is_float(mode)) {
4085 /* Psi is float, we need a floating point compare */
4088 ir_mode *m = get_irn_mode(cmp_a);
4090 if (! mode_is_float(m)) {
4091 cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_a, cmp_a, mode);
4092 cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_b, cmp_b, mode);
4093 } else if (m == mode_F) {
4094 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
4095 cmp_a = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_a, cmp_a);
4096 cmp_b = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_b, cmp_b);
4099 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4100 set_ia32_pncode(new_op, pnc);
4101 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
4108 construct_binop_func *set_func = NULL;
4110 if (mode_is_float(get_irn_mode(cmp_a))) {
4111 /* 1st case: compare operands are floats */
4116 set_func = new_rd_ia32_xCmpSet;
4119 set_func = new_rd_ia32_vfCmpSet;
4122 pnc &= 7; /* fp compare -> int compare */
4124 /* 2nd case: compare operand are integer too */
4125 set_func = new_rd_ia32_CmpSet;
4128 new_op = set_func(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4129 if(!mode_is_signed(mode))
4130 pnc |= ia32_pn_Cmp_Unsigned;
4132 set_ia32_pncode(new_op, pnc);
4133 set_ia32_am_support(new_op, ia32_am_Source);
4136 /* the the new compare as in */
4137 set_irn_n(cond, i, new_op);
4139 /* another complex condition */
4140 transform_psi_cond(in, mode, cg);
4146 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
4147 * We create a Set node, respectively a xCmp in case the Psi is a float, for
4148 * each compare, which causes the compare result to be stored in a register. The
4149 * "And"s and "Or"s are transformed later, we just have to set their mode right.
4151 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
4152 ia32_code_gen_t *cg = env;
4153 ir_node *psi_sel, *new_cmp, *block;
4158 if (get_irn_opcode(node) != iro_Psi)
4161 psi_sel = get_Psi_cond(node, 0);
4163 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
4164 if (is_Proj(psi_sel)) {
4165 assert(is_Cmp(get_Proj_pred(psi_sel)));
4169 //mode = get_irn_mode(node);
4170 // TODO probably wrong...
4173 transform_psi_cond(psi_sel, mode, cg);
4175 irg = get_irn_irg(node);
4176 block = get_nodes_block(node);
4178 /* we need to compare the evaluated condition tree with 0 */
4179 mode = get_irn_mode(node);
4180 if (mode_is_float(mode)) {
4181 /* BEWARE: new_r_Const_long works for floating point as well */
4182 ir_node *zero = new_r_Const_long(irg, block, mode, 0);
4184 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
4185 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4186 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
4188 ir_node *zero = new_r_Const_long(irg, block, mode_Iu, 0);
4189 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4190 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
4193 set_Psi_cond(node, 0, new_cmp);
4196 void ia32_init_transform(void)
4198 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");