2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
48 #include "archop.h" /* we need this for Min and Max nodes */
55 #include "../benode_t.h"
56 #include "../besched.h"
58 #include "../beutil.h"
59 #include "../beirg_t.h"
61 #include "bearch_ia32_t.h"
62 #include "ia32_nodes_attr.h"
63 #include "ia32_transform.h"
64 #include "ia32_new_nodes.h"
65 #include "ia32_map_regs.h"
66 #include "ia32_dbg_stat.h"
67 #include "ia32_optimize.h"
68 #include "ia32_util.h"
70 #include "gen_ia32_regalloc_if.h"
72 #define SFP_SIGN "0x80000000"
73 #define DFP_SIGN "0x8000000000000000"
74 #define SFP_ABS "0x7FFFFFFF"
75 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
82 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
83 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
84 #define ENT_SFP_ABS "IA32_SFP_ABS"
85 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
88 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
90 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
92 typedef struct ia32_transform_env_t {
93 ir_graph *irg; /**< The irg, the node should be created in */
94 ia32_code_gen_t *cg; /**< The code generator */
95 int visited; /**< visited count that indicates whether a
96 node is already transformed */
97 pdeq *worklist; /**< worklist of nodes that still need to be
99 ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/
100 } ia32_transform_env_t;
102 extern ir_op *get_op_Mulh(void);
104 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
105 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
106 ir_node *op2, ir_node *mem);
108 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
109 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
112 typedef ir_node *(transform_func)(ia32_transform_env_t *env, ir_node *node);
114 /****************************************************************************************************
116 * | | | | / _| | | (_)
117 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
118 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
119 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
120 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
122 ****************************************************************************************************/
124 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node);
125 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node);
126 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
129 static INLINE int mode_needs_gp_reg(ir_mode *mode)
131 if(mode == mode_fpcw)
134 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
137 static INLINE void set_new_node(ir_node *old_node, ir_node *new_node)
139 set_irn_link(old_node, new_node);
142 static INLINE ir_node *get_new_node(ir_node *old_node)
144 assert(irn_visited(old_node));
145 return (ir_node*) get_irn_link(old_node);
149 * Returns 1 if irn is a Const representing 0, 0 otherwise
151 static INLINE int is_ia32_Const_0(ir_node *irn) {
152 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
153 && tarval_is_null(get_ia32_Immop_tarval(irn));
157 * Returns 1 if irn is a Const representing 1, 0 otherwise
159 static INLINE int is_ia32_Const_1(ir_node *irn) {
160 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
161 && tarval_is_one(get_ia32_Immop_tarval(irn));
165 * Collects all Projs of a node into the node array. Index is the projnum.
166 * BEWARE: The caller has to assure the appropriate array size!
168 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
169 const ir_edge_t *edge;
170 assert(get_irn_mode(irn) == mode_T && "need mode_T");
172 memset(projs, 0, size * sizeof(projs[0]));
174 foreach_out_edge(irn, edge) {
175 ir_node *proj = get_edge_src_irn(edge);
176 int proj_proj = get_Proj_proj(proj);
177 assert(proj_proj < size);
178 projs[proj_proj] = proj;
183 * Renumbers the proj having pn_old in the array tp pn_new
184 * and removes the proj from the array.
186 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
187 fprintf(stderr, "Warning: renumber_Proj used!\n");
189 set_Proj_proj(projs[pn_old], pn_new);
190 projs[pn_old] = NULL;
195 * creates a unique ident by adding a number to a tag
197 * @param tag the tag string, must contain a %d if a number
200 static ident *unique_id(const char *tag)
202 static unsigned id = 0;
205 snprintf(str, sizeof(str), tag, ++id);
206 return new_id_from_str(str);
210 * Get a primitive type for a mode.
212 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
214 pmap_entry *e = pmap_find(types, mode);
219 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
220 res = new_type_primitive(new_id_from_str(buf), mode);
221 pmap_insert(types, mode, res);
229 * Get an entity that is initialized with a tarval
231 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
233 tarval *tv = get_Const_tarval(cnst);
234 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
239 ir_mode *mode = get_irn_mode(cnst);
240 ir_type *tp = get_Const_type(cnst);
241 if (tp == firm_unknown_type)
242 tp = get_prim_type(cg->isa->types, mode);
244 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
246 set_entity_ld_ident(res, get_entity_ident(res));
247 set_entity_visibility(res, visibility_local);
248 set_entity_variability(res, variability_constant);
249 set_entity_allocation(res, allocation_static);
251 /* we create a new entity here: It's initialization must resist on the
253 rem = current_ir_graph;
254 current_ir_graph = get_const_code_irg();
255 set_atomic_ent_value(res, new_Const_type(tv, tp));
256 current_ir_graph = rem;
258 pmap_insert(cg->isa->tv_ent, tv, res);
267 * Transforms a Const.
269 static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) {
270 ir_graph *irg = env->irg;
271 ir_node *block = transform_node(env, get_nodes_block(node));
272 dbg_info *dbgi = get_irn_dbg_info(node);
273 ir_mode *mode = get_irn_mode(node);
275 if (mode_is_float(mode)) {
277 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
278 ir_node *nomem = new_NoMem();
283 if (! USE_SSE2(env->cg)) {
284 cnst_classify_t clss = classify_Const(node);
286 if (clss == CNST_NULL) {
287 load = new_rd_ia32_vfldz(dbgi, irg, block);
289 } else if (clss == CNST_ONE) {
290 load = new_rd_ia32_vfld1(dbgi, irg, block);
293 floatent = get_entity_for_tv(env->cg, node);
295 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem);
296 set_ia32_am_support(load, ia32_am_Source);
297 set_ia32_op_type(load, ia32_AddrModeS);
298 set_ia32_am_flavour(load, ia32_am_N);
299 set_ia32_am_sc(load, floatent);
300 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
302 set_ia32_ls_mode(load, mode);
304 floatent = get_entity_for_tv(env->cg, node);
306 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
307 set_ia32_am_support(load, ia32_am_Source);
308 set_ia32_op_type(load, ia32_AddrModeS);
309 set_ia32_am_flavour(load, ia32_am_N);
310 set_ia32_am_sc(load, floatent);
311 set_ia32_ls_mode(load, mode);
313 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
316 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
318 /* Const Nodes before the initial IncSP are a bad idea, because
319 * they could be spilled and we have no SP ready at that point yet
321 if (get_irg_start_block(irg) == block) {
322 add_irn_dep(load, get_irg_frame(irg));
325 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
328 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
331 if (get_irg_start_block(irg) == block) {
332 add_irn_dep(cnst, get_irg_frame(irg));
335 set_ia32_Const_attr(cnst, node);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
341 return new_r_Bad(irg);
345 * Transforms a SymConst.
347 static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) {
348 ir_graph *irg = env->irg;
349 ir_node *block = transform_node(env, get_nodes_block(node));
350 dbg_info *dbgi = get_irn_dbg_info(node);
351 ir_mode *mode = get_irn_mode(node);
354 if (mode_is_float(mode)) {
356 if (USE_SSE2(env->cg))
357 cnst = new_rd_ia32_xConst(dbgi, irg, block);
359 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
360 set_ia32_ls_mode(cnst, mode);
362 cnst = new_rd_ia32_Const(dbgi, irg, block);
365 /* Const Nodes before the initial IncSP are a bad idea, because
366 * they could be spilled and we have no SP ready at that point yet
368 if (get_irg_start_block(irg) == block) {
369 add_irn_dep(cnst, get_irg_frame(irg));
372 set_ia32_Const_attr(cnst, node);
373 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
379 * SSE convert of an integer node into a floating point node.
381 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbgi,
382 ir_graph *irg, ir_node *block,
383 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
385 ir_node *noreg = ia32_new_NoReg_gp(cg);
386 ir_node *nomem = new_rd_NoMem(irg);
387 ir_node *old_pred = get_Cmp_left(old_node);
388 ir_mode *in_mode = get_irn_mode(old_pred);
389 int in_bits = get_mode_size_bits(in_mode);
390 ir_node *conv = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, in, nomem);
392 set_ia32_ls_mode(conv, tgt_mode);
394 set_ia32_am_support(conv, ia32_am_Source);
396 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
402 * SSE convert of an float node into a double node.
404 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbgi,
405 ir_graph *irg, ir_node *block,
406 ir_node *in, ir_node *old_node)
408 ir_node *noreg = ia32_new_NoReg_gp(cg);
409 ir_node *nomem = new_rd_NoMem(irg);
410 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, in, nomem);
412 set_ia32_am_support(conv, ia32_am_Source);
413 set_ia32_ls_mode(conv, mode_xmm);
414 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
419 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
420 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
421 static const struct {
423 const char *ent_name;
424 const char *cnst_str;
425 } names [ia32_known_const_max] = {
426 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
427 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
428 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
429 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
431 static ir_entity *ent_cache[ia32_known_const_max];
433 const char *tp_name, *ent_name, *cnst_str;
441 ent_name = names[kct].ent_name;
442 if (! ent_cache[kct]) {
443 tp_name = names[kct].tp_name;
444 cnst_str = names[kct].cnst_str;
446 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
448 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
449 tp = new_type_primitive(new_id_from_str(tp_name), mode);
450 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
452 set_entity_ld_ident(ent, get_entity_ident(ent));
453 set_entity_visibility(ent, visibility_local);
454 set_entity_variability(ent, variability_constant);
455 set_entity_allocation(ent, allocation_static);
457 /* we create a new entity here: It's initialization must resist on the
459 rem = current_ir_graph;
460 current_ir_graph = get_const_code_irg();
461 cnst = new_Const(mode, tv);
462 current_ir_graph = rem;
464 set_atomic_ent_value(ent, cnst);
466 /* cache the entry */
467 ent_cache[kct] = ent;
470 return ent_cache[kct];
475 * Prints the old node name on cg obst and returns a pointer to it.
477 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
478 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
480 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
481 obstack_1grow(isa->name_obst, 0);
482 return obstack_finish(isa->name_obst);
486 /* determine if one operator is an Imm */
487 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
489 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
491 return is_ia32_Cnst(op2) ? op2 : NULL;
495 /* determine if one operator is not an Imm */
496 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
497 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
500 static void fold_immediate(ia32_transform_env_t *env, ir_node *node, int in1, int in2) {
504 if (! (env->cg->opt & IA32_OPT_IMMOPS))
507 left = get_irn_n(node, in1);
508 right = get_irn_n(node, in2);
509 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
510 /* we can only set right operand to immediate */
511 if(!is_ia32_commutative(node))
513 /* exchange left/right */
514 set_irn_n(node, in1, right);
515 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
516 copy_ia32_Immop_attr(node, left);
517 } else if(is_ia32_Cnst(right)) {
518 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
519 copy_ia32_Immop_attr(node, right);
524 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
528 * Construct a standard binary operation, set AM and immediate if required.
530 * @param env The transformation environment
531 * @param op1 The first operand
532 * @param op2 The second operand
533 * @param func The node constructor function
534 * @return The constructed ia32 node.
536 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *node,
537 ir_node *op1, ir_node *op2,
538 construct_binop_func *func)
540 ir_node *block = transform_node(env, get_nodes_block(node));
541 ir_node *new_op1 = transform_node(env, op1);
542 ir_node *new_op2 = transform_node(env, op2);
543 ir_node *new_node = NULL;
544 ir_graph *irg = env->irg;
545 dbg_info *dbgi = get_irn_dbg_info(node);
546 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
547 ir_node *nomem = new_NoMem();
549 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
550 if (func == new_rd_ia32_IMul) {
551 set_ia32_am_support(new_node, ia32_am_Source);
553 set_ia32_am_support(new_node, ia32_am_Full);
556 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
557 if (is_op_commutative(get_irn_op(node))) {
558 set_ia32_commutative(new_node);
560 fold_immediate(env, new_node, 2, 3);
566 * Construct a standard binary operation, set AM and immediate if required.
568 * @param env The transformation environment
569 * @param op1 The first operand
570 * @param op2 The second operand
571 * @param func The node constructor function
572 * @return The constructed ia32 node.
574 static ir_node *gen_binop_float(ia32_transform_env_t *env, ir_node *node,
575 ir_node *op1, ir_node *op2,
576 construct_binop_func *func)
578 ir_node *block = transform_node(env, get_nodes_block(node));
579 ir_node *new_op1 = transform_node(env, op1);
580 ir_node *new_op2 = transform_node(env, op2);
581 ir_node *new_node = NULL;
582 dbg_info *dbgi = get_irn_dbg_info(node);
583 ir_graph *irg = env->irg;
584 ir_mode *mode = get_irn_mode(node);
585 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
586 ir_node *nomem = new_NoMem();
588 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
589 set_ia32_am_support(new_node, ia32_am_Source);
590 if (is_op_commutative(get_irn_op(node))) {
591 set_ia32_commutative(new_node);
593 if (USE_SSE2(env->cg)) {
594 set_ia32_ls_mode(new_node, mode);
597 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
604 * Construct a shift/rotate binary operation, sets AM and immediate if required.
606 * @param env The transformation environment
607 * @param op1 The first operand
608 * @param op2 The second operand
609 * @param func The node constructor function
610 * @return The constructed ia32 node.
612 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node,
613 ir_node *op1, ir_node *op2,
614 construct_binop_func *func)
616 ir_node *block = transform_node(env, get_nodes_block(node));
617 ir_node *new_op1 = transform_node(env, op1);
618 ir_node *new_op2 = transform_node(env, op2);
619 ir_node *new_op = NULL;
620 dbg_info *dbgi = get_irn_dbg_info(node);
621 ir_graph *irg = env->irg;
622 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
623 ir_node *nomem = new_NoMem();
628 assert(! mode_is_float(get_irn_mode(node))
629 && "Shift/Rotate with float not supported");
631 /* Check if immediate optimization is on and */
632 /* if it's an operation with immediate. */
633 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
634 expr_op = get_expr_op(new_op1, new_op2);
636 assert((expr_op || imm_op) && "invalid operands");
639 /* We have two consts here: not yet supported */
643 /* Limit imm_op within range imm8 */
645 tv = get_ia32_Immop_tarval(imm_op);
648 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
649 set_ia32_Immop_tarval(imm_op, tv);
656 /* integer operations */
658 /* This is shift/rot with const */
659 DB((dbg, LEVEL_1, "Shift/Rot with immediate ..."));
661 new_op = func(dbgi, irg, block, noreg, noreg, expr_op, noreg, nomem);
662 copy_ia32_Immop_attr(new_op, imm_op);
664 /* This is a normal shift/rot */
665 DB((dbg, LEVEL_1, "Shift/Rot binop ..."));
666 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
670 set_ia32_am_support(new_op, ia32_am_Dest);
672 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
674 set_ia32_emit_cl(new_op);
681 * Construct a standard unary operation, set AM and immediate if required.
683 * @param env The transformation environment
684 * @param op The operand
685 * @param func The node constructor function
686 * @return The constructed ia32 node.
688 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *node, ir_node *op,
689 construct_unop_func *func)
691 ir_node *block = transform_node(env, get_nodes_block(node));
692 ir_node *new_op = transform_node(env, op);
693 ir_node *new_node = NULL;
694 ir_graph *irg = env->irg;
695 dbg_info *dbgi = get_irn_dbg_info(node);
696 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
697 ir_node *nomem = new_NoMem();
699 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
700 DB((dbg, LEVEL_1, "INT unop ..."));
701 set_ia32_am_support(new_node, ia32_am_Dest);
703 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
710 * Creates an ia32 Add.
712 * @param env The transformation environment
713 * @return the created ia32 Add node
715 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) {
716 ir_node *block = transform_node(env, get_nodes_block(node));
717 ir_node *op1 = get_Add_left(node);
718 ir_node *new_op1 = transform_node(env, op1);
719 ir_node *op2 = get_Add_right(node);
720 ir_node *new_op2 = transform_node(env, op2);
721 ir_node *new_op = NULL;
722 ir_graph *irg = env->irg;
723 dbg_info *dbgi = get_irn_dbg_info(node);
724 ir_mode *mode = get_irn_mode(node);
725 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
726 ir_node *nomem = new_NoMem();
727 ir_node *expr_op, *imm_op;
729 /* Check if immediate optimization is on and */
730 /* if it's an operation with immediate. */
731 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
732 expr_op = get_expr_op(new_op1, new_op2);
734 assert((expr_op || imm_op) && "invalid operands");
736 if (mode_is_float(mode)) {
738 if (USE_SSE2(env->cg))
739 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xAdd);
741 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfadd);
746 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
747 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
749 /* No expr_op means, that we have two const - one symconst and */
750 /* one tarval or another symconst - because this case is not */
751 /* covered by constant folding */
752 /* We need to check for: */
753 /* 1) symconst + const -> becomes a LEA */
754 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
755 /* linker doesn't support two symconsts */
757 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
758 /* this is the 2nd case */
759 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
760 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
761 set_ia32_am_flavour(new_op, ia32_am_OB);
762 set_ia32_am_support(new_op, ia32_am_Source);
763 set_ia32_op_type(new_op, ia32_AddrModeS);
765 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
766 } else if (tp1 == ia32_ImmSymConst) {
767 tarval *tv = get_ia32_Immop_tarval(new_op2);
768 long offs = get_tarval_long(tv);
770 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
771 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
773 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
774 add_ia32_am_offs_int(new_op, offs);
775 set_ia32_am_flavour(new_op, ia32_am_O);
776 set_ia32_am_support(new_op, ia32_am_Source);
777 set_ia32_op_type(new_op, ia32_AddrModeS);
778 } else if (tp2 == ia32_ImmSymConst) {
779 tarval *tv = get_ia32_Immop_tarval(new_op1);
780 long offs = get_tarval_long(tv);
782 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
783 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
785 add_ia32_am_offs_int(new_op, offs);
786 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
787 set_ia32_am_flavour(new_op, ia32_am_O);
788 set_ia32_am_support(new_op, ia32_am_Source);
789 set_ia32_op_type(new_op, ia32_AddrModeS);
791 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
792 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
793 tarval *restv = tarval_add(tv1, tv2);
795 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
797 new_op = new_rd_ia32_Const(dbgi, irg, block);
798 set_ia32_Const_tarval(new_op, restv);
799 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
802 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
805 if ((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
806 tarval_classification_t class_tv, class_negtv;
807 tarval *tv = get_ia32_Immop_tarval(imm_op);
809 /* optimize tarvals */
810 class_tv = classify_tarval(tv);
811 class_negtv = classify_tarval(tarval_neg(tv));
813 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
814 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
815 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
816 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
818 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
819 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
820 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
821 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
827 /* This is a normal add */
828 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
831 set_ia32_am_support(new_op, ia32_am_Full);
832 set_ia32_commutative(new_op);
834 fold_immediate(env, new_op, 2, 3);
836 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
842 static ir_node *create_ia32_Mul(ia32_transform_env_t *env, ir_node *node) {
843 ir_graph *irg = env->irg;
844 dbg_info *dbgi = get_irn_dbg_info(node);
845 ir_node *block = transform_node(env, get_nodes_block(node));
846 ir_node *op1 = get_Mul_left(node);
847 ir_node *op2 = get_Mul_right(node);
848 ir_node *new_op1 = transform_node(env, op1);
849 ir_node *new_op2 = transform_node(env, op2);
850 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
851 ir_node *proj_EAX, *proj_EDX, *res;
854 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
855 set_ia32_commutative(res);
856 set_ia32_am_support(res, ia32_am_Source);
858 /* imediates are not supported, so no fold_immediate */
859 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
860 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
864 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
872 * Creates an ia32 Mul.
874 * @param env The transformation environment
875 * @return the created ia32 Mul node
877 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) {
878 ir_node *op1 = get_Mul_left(node);
879 ir_node *op2 = get_Mul_right(node);
880 ir_mode *mode = get_irn_mode(node);
882 if (mode_is_float(mode)) {
884 if (USE_SSE2(env->cg))
885 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul);
887 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul);
891 for the lower 32bit of the result it doesn't matter whether we use
892 signed or unsigned multiplication so we use IMul as it has fewer
895 return gen_binop(env, node, op1, op2, new_rd_ia32_IMul);
899 * Creates an ia32 Mulh.
900 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
901 * this result while Mul returns the lower 32 bit.
903 * @param env The transformation environment
904 * @return the created ia32 Mulh node
906 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) {
907 ir_node *block = transform_node(env, get_nodes_block(node));
908 ir_node *op1 = get_irn_n(node, 0);
909 ir_node *new_op1 = transform_node(env, op1);
910 ir_node *op2 = get_irn_n(node, 1);
911 ir_node *new_op2 = transform_node(env, op2);
912 ir_graph *irg = env->irg;
913 dbg_info *dbgi = get_irn_dbg_info(node);
914 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
915 ir_mode *mode = get_irn_mode(node);
916 ir_node *proj_EAX, *proj_EDX, *res;
919 assert(!mode_is_float(mode) && "Mulh with float not supported");
920 if (mode_is_signed(mode)) {
921 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
923 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
926 set_ia32_commutative(res);
927 set_ia32_am_support(res, ia32_am_Source);
929 set_ia32_am_support(res, ia32_am_Source);
931 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
932 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
936 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
944 * Creates an ia32 And.
946 * @param env The transformation environment
947 * @return The created ia32 And node
949 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *node) {
950 ir_node *op1 = get_And_left(node);
951 ir_node *op2 = get_And_right(node);
953 assert (! mode_is_float(get_irn_mode(node)));
954 return gen_binop(env, node, op1, op2, new_rd_ia32_And);
960 * Creates an ia32 Or.
962 * @param env The transformation environment
963 * @return The created ia32 Or node
965 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *node) {
966 ir_node *op1 = get_Or_left(node);
967 ir_node *op2 = get_Or_right(node);
969 assert (! mode_is_float(get_irn_mode(node)));
970 return gen_binop(env, node, op1, op2, new_rd_ia32_Or);
976 * Creates an ia32 Eor.
978 * @param env The transformation environment
979 * @return The created ia32 Eor node
981 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *node) {
982 ir_node *op1 = get_Eor_left(node);
983 ir_node *op2 = get_Eor_right(node);
985 assert(! mode_is_float(get_irn_mode(node)));
986 return gen_binop(env, node, op1, op2, new_rd_ia32_Xor);
992 * Creates an ia32 Max.
994 * @param env The transformation environment
995 * @return the created ia32 Max node
997 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *node) {
998 ir_node *block = transform_node(env, get_nodes_block(node));
999 ir_node *op1 = get_irn_n(node, 0);
1000 ir_node *new_op1 = transform_node(env, op1);
1001 ir_node *op2 = get_irn_n(node, 1);
1002 ir_node *new_op2 = transform_node(env, op2);
1003 ir_graph *irg = env->irg;
1004 ir_mode *mode = get_irn_mode(node);
1005 dbg_info *dbgi = get_irn_dbg_info(node);
1006 ir_mode *op_mode = get_irn_mode(op1);
1009 assert(get_mode_size_bits(mode) == 32);
1011 if (mode_is_float(mode)) {
1013 if (USE_SSE2(env->cg)) {
1014 new_op = gen_binop_float(env, node, new_op1, new_op2, new_rd_ia32_xMax);
1016 panic("Can't create Max node");
1019 long pnc = pn_Cmp_Gt;
1020 if (! mode_is_signed(op_mode)) {
1021 pnc |= ia32_pn_Cmp_Unsigned;
1023 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1024 set_ia32_pncode(new_op, pnc);
1025 set_ia32_am_support(new_op, ia32_am_None);
1027 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1033 * Creates an ia32 Min.
1035 * @param env The transformation environment
1036 * @return the created ia32 Min node
1038 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *node) {
1039 ir_node *block = transform_node(env, get_nodes_block(node));
1040 ir_node *op1 = get_irn_n(node, 0);
1041 ir_node *new_op1 = transform_node(env, op1);
1042 ir_node *op2 = get_irn_n(node, 1);
1043 ir_node *new_op2 = transform_node(env, op2);
1044 ir_graph *irg = env->irg;
1045 ir_mode *mode = get_irn_mode(node);
1046 dbg_info *dbgi = get_irn_dbg_info(node);
1047 ir_mode *op_mode = get_irn_mode(op1);
1050 assert(get_mode_size_bits(mode) == 32);
1052 if (mode_is_float(mode)) {
1054 if (USE_SSE2(env->cg)) {
1055 new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMin);
1057 panic("can't create Min node");
1060 long pnc = pn_Cmp_Lt;
1061 if (! mode_is_signed(op_mode)) {
1062 pnc |= ia32_pn_Cmp_Unsigned;
1064 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1065 set_ia32_pncode(new_op, pnc);
1066 set_ia32_am_support(new_op, ia32_am_None);
1068 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1075 * Creates an ia32 Sub.
1077 * @param env The transformation environment
1078 * @return The created ia32 Sub node
1080 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) {
1081 ir_node *block = transform_node(env, get_nodes_block(node));
1082 ir_node *op1 = get_Sub_left(node);
1083 ir_node *new_op1 = transform_node(env, op1);
1084 ir_node *op2 = get_Sub_right(node);
1085 ir_node *new_op2 = transform_node(env, op2);
1086 ir_node *new_op = NULL;
1087 ir_graph *irg = env->irg;
1088 dbg_info *dbgi = get_irn_dbg_info(node);
1089 ir_mode *mode = get_irn_mode(node);
1090 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1091 ir_node *nomem = new_NoMem();
1092 ir_node *expr_op, *imm_op;
1094 /* Check if immediate optimization is on and */
1095 /* if it's an operation with immediate. */
1096 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1097 expr_op = get_expr_op(new_op1, new_op2);
1099 assert((expr_op || imm_op) && "invalid operands");
1101 if (mode_is_float(mode)) {
1103 if (USE_SSE2(env->cg))
1104 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xSub);
1106 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfsub);
1111 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1112 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1114 /* No expr_op means, that we have two const - one symconst and */
1115 /* one tarval or another symconst - because this case is not */
1116 /* covered by constant folding */
1117 /* We need to check for: */
1118 /* 1) symconst - const -> becomes a LEA */
1119 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1120 /* linker doesn't support two symconsts */
1121 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1122 /* this is the 2nd case */
1123 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1124 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1125 set_ia32_am_sc_sign(new_op);
1126 set_ia32_am_flavour(new_op, ia32_am_OB);
1128 DBG_OPT_LEA3(op1, op2, node, new_op);
1129 } else if (tp1 == ia32_ImmSymConst) {
1130 tarval *tv = get_ia32_Immop_tarval(new_op2);
1131 long offs = get_tarval_long(tv);
1133 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1134 DBG_OPT_LEA3(op1, op2, node, new_op);
1136 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1137 add_ia32_am_offs_int(new_op, -offs);
1138 set_ia32_am_flavour(new_op, ia32_am_O);
1139 set_ia32_am_support(new_op, ia32_am_Source);
1140 set_ia32_op_type(new_op, ia32_AddrModeS);
1141 } else if (tp2 == ia32_ImmSymConst) {
1142 tarval *tv = get_ia32_Immop_tarval(new_op1);
1143 long offs = get_tarval_long(tv);
1145 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1146 DBG_OPT_LEA3(op1, op2, node, new_op);
1148 add_ia32_am_offs_int(new_op, offs);
1149 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1150 set_ia32_am_sc_sign(new_op);
1151 set_ia32_am_flavour(new_op, ia32_am_O);
1152 set_ia32_am_support(new_op, ia32_am_Source);
1153 set_ia32_op_type(new_op, ia32_AddrModeS);
1155 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1156 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1157 tarval *restv = tarval_sub(tv1, tv2);
1159 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1161 new_op = new_rd_ia32_Const(dbgi, irg, block);
1162 set_ia32_Const_tarval(new_op, restv);
1163 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1166 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1168 } else if (imm_op) {
1169 if ((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1170 tarval_classification_t class_tv, class_negtv;
1171 tarval *tv = get_ia32_Immop_tarval(imm_op);
1173 /* optimize tarvals */
1174 class_tv = classify_tarval(tv);
1175 class_negtv = classify_tarval(tarval_neg(tv));
1177 if (class_tv == TV_CLASSIFY_ONE) {
1178 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1179 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1180 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1182 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1183 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1184 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1185 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1191 /* This is a normal sub */
1192 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1194 /* set AM support */
1195 set_ia32_am_support(new_op, ia32_am_Full);
1197 fold_immediate(env, new_op, 2, 3);
1199 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1207 * Generates an ia32 DivMod with additional infrastructure for the
1208 * register allocator if needed.
1210 * @param env The transformation environment
1211 * @param dividend -no comment- :)
1212 * @param divisor -no comment- :)
1213 * @param dm_flav flavour_Div/Mod/DivMod
1214 * @return The created ia32 DivMod node
1216 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *node,
1217 ir_node *dividend, ir_node *divisor,
1218 ia32_op_flavour_t dm_flav)
1220 ir_node *block = transform_node(env, get_nodes_block(node));
1221 ir_node *new_dividend = transform_node(env, dividend);
1222 ir_node *new_divisor = transform_node(env, divisor);
1223 ir_graph *irg = env->irg;
1224 dbg_info *dbgi = get_irn_dbg_info(node);
1225 ir_mode *mode = get_irn_mode(node);
1226 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1227 ir_node *res, *proj_div, *proj_mod;
1228 ir_node *edx_node, *cltd;
1229 ir_node *in_keep[2];
1230 ir_node *mem, *new_mem;
1231 ir_node *projs[pn_DivMod_max];
1234 ia32_collect_Projs(node, projs, pn_DivMod_max);
1240 mem = get_Div_mem(node);
1241 mode = get_Div_resmode(node);
1242 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1245 mem = get_Mod_mem(node);
1246 mode = get_Mod_resmode(node);
1247 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1249 case flavour_DivMod:
1250 mem = get_DivMod_mem(node);
1251 mode = get_DivMod_resmode(node);
1252 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1253 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1256 panic("invalid divmod flavour!");
1258 new_mem = transform_node(env, mem);
1260 if (mode_is_signed(mode)) {
1261 /* in signed mode, we need to sign extend the dividend */
1262 cltd = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1263 new_dividend = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1264 edx_node = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1266 edx_node = new_rd_ia32_Const(dbgi, irg, block);
1267 add_irn_dep(edx_node, be_abi_get_start_barrier(env->cg->birg->abi));
1268 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1271 if (mode_is_signed(mode)) {
1272 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1274 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1277 /* Matze: code can't handle this at the moment... */
1279 /* set AM support */
1280 set_ia32_am_support(res, ia32_am_Source);
1283 set_ia32_n_res(res, 2);
1285 /* check, which Proj-Keep, we need to add */
1287 if (proj_div == NULL) {
1288 /* We have only mod result: add div res Proj-Keep */
1289 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1292 if (proj_mod == NULL) {
1293 /* We have only div result: add mod res Proj-Keep */
1294 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1298 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1300 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1307 * Wrapper for generate_DivMod. Sets flavour_Mod.
1309 * @param env The transformation environment
1311 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *node) {
1312 return generate_DivMod(env, node, get_Mod_left(node),
1313 get_Mod_right(node), flavour_Mod);
1317 * Wrapper for generate_DivMod. Sets flavour_Div.
1319 * @param env The transformation environment
1321 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *node) {
1322 return generate_DivMod(env, node, get_Div_left(node),
1323 get_Div_right(node), flavour_Div);
1327 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1329 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *node) {
1330 return generate_DivMod(env, node, get_DivMod_left(node),
1331 get_DivMod_right(node), flavour_DivMod);
1337 * Creates an ia32 floating Div.
1339 * @param env The transformation environment
1340 * @return The created ia32 xDiv node
1342 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *node) {
1343 ir_node *block = transform_node(env, get_nodes_block(node));
1344 ir_node *op1 = get_Quot_left(node);
1345 ir_node *new_op1 = transform_node(env, op1);
1346 ir_node *op2 = get_Quot_right(node);
1347 ir_node *new_op2 = transform_node(env, op2);
1348 ir_graph *irg = env->irg;
1349 dbg_info *dbgi = get_irn_dbg_info(node);
1350 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1351 ir_node *nomem = new_rd_NoMem(env->irg);
1355 if (USE_SSE2(env->cg)) {
1356 ir_mode *mode = get_irn_mode(op1);
1357 if (is_ia32_xConst(new_op2)) {
1358 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1359 set_ia32_am_support(new_op, ia32_am_None);
1360 copy_ia32_Immop_attr(new_op, new_op2);
1362 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1363 // Matze: disabled for now, spillslot coalescer fails
1364 //set_ia32_am_support(new_op, ia32_am_Source);
1366 set_ia32_ls_mode(new_op, mode);
1368 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1369 // Matze: disabled for now (spillslot coalescer fails)
1370 //set_ia32_am_support(new_op, ia32_am_Source);
1372 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1378 * Creates an ia32 Shl.
1380 * @param env The transformation environment
1381 * @return The created ia32 Shl node
1383 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *node) {
1384 return gen_shift_binop(env, node, get_Shl_left(node), get_Shl_right(node),
1391 * Creates an ia32 Shr.
1393 * @param env The transformation environment
1394 * @return The created ia32 Shr node
1396 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *node) {
1397 return gen_shift_binop(env, node, get_Shr_left(node),
1398 get_Shr_right(node), new_rd_ia32_Shr);
1404 * Creates an ia32 Sar.
1406 * @param env The transformation environment
1407 * @return The created ia32 Shrs node
1409 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) {
1410 return gen_shift_binop(env, node, get_Shrs_left(node),
1411 get_Shrs_right(node), new_rd_ia32_Sar);
1417 * Creates an ia32 RotL.
1419 * @param env The transformation environment
1420 * @param op1 The first operator
1421 * @param op2 The second operator
1422 * @return The created ia32 RotL node
1424 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node,
1425 ir_node *op1, ir_node *op2) {
1426 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Rol);
1432 * Creates an ia32 RotR.
1433 * NOTE: There is no RotR with immediate because this would always be a RotL
1434 * "imm-mode_size_bits" which can be pre-calculated.
1436 * @param env The transformation environment
1437 * @param op1 The first operator
1438 * @param op2 The second operator
1439 * @return The created ia32 RotR node
1441 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1,
1443 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Ror);
1449 * Creates an ia32 RotR or RotL (depending on the found pattern).
1451 * @param env The transformation environment
1452 * @return The created ia32 RotL or RotR node
1454 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) {
1455 ir_node *rotate = NULL;
1456 ir_node *op1 = get_Rot_left(node);
1457 ir_node *op2 = get_Rot_right(node);
1459 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1460 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1461 that means we can create a RotR instead of an Add and a RotL */
1463 if (get_irn_op(op2) == op_Add) {
1465 ir_node *left = get_Add_left(add);
1466 ir_node *right = get_Add_right(add);
1467 if (is_Const(right)) {
1468 tarval *tv = get_Const_tarval(right);
1469 ir_mode *mode = get_irn_mode(node);
1470 long bits = get_mode_size_bits(mode);
1472 if (get_irn_op(left) == op_Minus &&
1473 tarval_is_long(tv) &&
1474 get_tarval_long(tv) == bits)
1476 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1477 rotate = gen_RotR(env, node, op1, get_Minus_op(left));
1482 if (rotate == NULL) {
1483 rotate = gen_RotL(env, node, op1, op2);
1492 * Transforms a Minus node.
1494 * @param env The transformation environment
1495 * @param op The Minus operand
1496 * @return The created ia32 Minus node
1498 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *node, ir_node *op) {
1499 ir_node *block = transform_node(env, get_nodes_block(node));
1500 ir_graph *irg = env->irg;
1501 dbg_info *dbgi = get_irn_dbg_info(node);
1502 ir_mode *mode = get_irn_mode(node);
1507 if (mode_is_float(mode)) {
1508 ir_node *new_op = transform_node(env, op);
1510 if (USE_SSE2(env->cg)) {
1511 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1512 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1513 ir_node *nomem = new_rd_NoMem(irg);
1515 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1517 size = get_mode_size_bits(mode);
1518 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1520 set_ia32_am_sc(res, ent);
1521 set_ia32_op_type(res, ia32_AddrModeS);
1522 set_ia32_ls_mode(res, mode);
1524 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1527 res = gen_unop(env, node, op, new_rd_ia32_Neg);
1530 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1536 * Transforms a Minus node.
1538 * @param env The transformation environment
1539 * @return The created ia32 Minus node
1541 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *node) {
1542 return gen_Minus_ex(env, node, get_Minus_op(node));
1547 * Transforms a Not node.
1549 * @param env The transformation environment
1550 * @return The created ia32 Not node
1552 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *node) {
1553 ir_node *op = get_Not_op(node);
1555 assert (! mode_is_float(get_irn_mode(node)));
1556 return gen_unop(env, node, op, new_rd_ia32_Not);
1562 * Transforms an Abs node.
1564 * @param env The transformation environment
1565 * @return The created ia32 Abs node
1567 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *node) {
1568 ir_node *block = transform_node(env, get_nodes_block(node));
1569 ir_node *op = get_Abs_op(node);
1570 ir_node *new_op = transform_node(env, op);
1571 ir_graph *irg = env->irg;
1572 dbg_info *dbgi = get_irn_dbg_info(node);
1573 ir_mode *mode = get_irn_mode(node);
1574 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1575 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1576 ir_node *nomem = new_NoMem();
1577 ir_node *res, *p_eax, *p_edx;
1581 if (mode_is_float(mode)) {
1583 if (USE_SSE2(env->cg)) {
1584 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1586 size = get_mode_size_bits(mode);
1587 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1589 set_ia32_am_sc(res, ent);
1591 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1593 set_ia32_op_type(res, ia32_AddrModeS);
1594 set_ia32_ls_mode(res, mode);
1597 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1598 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1602 res = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1603 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1605 p_eax = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
1606 p_edx = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1608 res = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1609 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1611 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1612 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1621 * Transforms a Load.
1623 * @param env The transformation environment
1624 * @return the created ia32 Load node
1626 static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) {
1627 ir_node *block = transform_node(env, get_nodes_block(node));
1628 ir_node *ptr = get_Load_ptr(node);
1629 ir_node *new_ptr = transform_node(env, ptr);
1630 ir_node *mem = get_Load_mem(node);
1631 ir_node *new_mem = transform_node(env, mem);
1632 ir_graph *irg = env->irg;
1633 dbg_info *dbgi = get_irn_dbg_info(node);
1634 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1635 ir_mode *mode = get_Load_mode(node);
1636 ir_node *lptr = new_ptr;
1639 ir_node *projs[pn_Load_max];
1640 ia32_am_flavour_t am_flav = ia32_am_B;
1642 ia32_collect_Projs(node, projs, pn_Load_max);
1645 check for special case: the loaded value might not be used (optimized, volatile, ...)
1646 we add a Proj + Keep for volatile loads and ignore all other cases
1648 if (! be_get_Proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1649 /* add a result proj and a Keep to produce a pseudo use */
1650 ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res);
1651 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), irg, block, 1, &proj);
1654 /* address might be a constant (symconst or absolute address) */
1655 if (is_ia32_Const(new_ptr)) {
1660 if (mode_is_float(mode)) {
1662 if (USE_SSE2(env->cg)) {
1663 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1665 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem);
1668 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1671 /* base is a constant address */
1673 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1674 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1675 am_flav = ia32_am_N;
1677 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1678 long offs = get_tarval_long(tv);
1680 add_ia32_am_offs_int(new_op, offs);
1681 am_flav = ia32_am_O;
1685 set_ia32_am_support(new_op, ia32_am_Source);
1686 set_ia32_op_type(new_op, ia32_AddrModeS);
1687 set_ia32_am_flavour(new_op, am_flav);
1688 set_ia32_ls_mode(new_op, mode);
1690 /* make sure we are scheduled behind the initial IncSP/Barrier
1691 * to avoid spills being placed before it
1693 if (block == get_irg_start_block(irg)) {
1694 add_irn_dep(new_op, get_irg_frame(irg));
1697 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1705 * Transforms a Store.
1707 * @param env The transformation environment
1708 * @return the created ia32 Store node
1710 static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) {
1711 ir_node *block = transform_node(env, get_nodes_block(node));
1712 ir_node *ptr = get_Store_ptr(node);
1713 ir_node *new_ptr = transform_node(env, ptr);
1714 ir_node *val = get_Store_value(node);
1715 ir_node *new_val = transform_node(env, val);
1716 ir_node *mem = get_Store_mem(node);
1717 ir_node *new_mem = transform_node(env, mem);
1718 ir_graph *irg = env->irg;
1719 dbg_info *dbgi = get_irn_dbg_info(node);
1720 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1721 ir_node *sptr = new_ptr;
1722 ir_mode *mode = get_irn_mode(val);
1723 ir_node *sval = new_val;
1726 ia32_am_flavour_t am_flav = ia32_am_B;
1728 if (is_ia32_Const(new_val)) {
1729 assert(!mode_is_float(mode));
1733 /* address might be a constant (symconst or absolute address) */
1734 if (is_ia32_Const(new_ptr)) {
1739 if (mode_is_float(mode)) {
1741 if (USE_SSE2(env->cg)) {
1742 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, sval, new_mem);
1744 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, sval, new_mem);
1746 } else if (get_mode_size_bits(mode) == 8) {
1747 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg, sval, new_mem);
1749 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, sval, new_mem);
1752 /* stored const is an immediate value */
1753 if (is_ia32_Const(new_val)) {
1754 assert(!mode_is_float(mode));
1755 copy_ia32_Immop_attr(new_op, new_val);
1758 /* base is an constant address */
1760 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1761 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1762 am_flav = ia32_am_N;
1764 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1765 long offs = get_tarval_long(tv);
1767 add_ia32_am_offs_int(new_op, offs);
1768 am_flav = ia32_am_O;
1772 set_ia32_am_support(new_op, ia32_am_Dest);
1773 set_ia32_op_type(new_op, ia32_AddrModeD);
1774 set_ia32_am_flavour(new_op, am_flav);
1775 set_ia32_ls_mode(new_op, mode);
1777 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1785 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1787 * @param env The transformation environment
1788 * @return The transformed node.
1790 static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) {
1791 ir_node *block = transform_node(env, get_nodes_block(node));
1792 ir_graph *irg = env->irg;
1793 dbg_info *dbgi = get_irn_dbg_info(node);
1794 ir_node *sel = get_Cond_selector(node);
1795 ir_mode *sel_mode = get_irn_mode(sel);
1796 ir_node *res = NULL;
1797 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1798 ir_node *cnst, *expr;
1800 if (is_Proj(sel) && sel_mode == mode_b) {
1801 ir_node *pred = get_Proj_pred(sel);
1802 ir_node *cmp_a = get_Cmp_left(pred);
1803 ir_node *new_cmp_a = transform_node(env, cmp_a);
1804 ir_node *cmp_b = get_Cmp_right(pred);
1805 ir_node *new_cmp_b = transform_node(env, cmp_b);
1806 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1807 ir_node *nomem = new_NoMem();
1809 int pnc = get_Proj_proj(sel);
1810 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1811 pnc |= ia32_pn_Cmp_Unsigned;
1814 /* check if we can use a CondJmp with immediate */
1815 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1816 expr = get_expr_op(new_cmp_a, new_cmp_b);
1818 if (cnst != NULL && expr != NULL) {
1819 /* immop has to be the right operand, we might need to flip pnc */
1820 if(cnst != new_cmp_b) {
1821 pnc = get_inversed_pnc(pnc);
1824 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_needs_gp_reg(get_irn_mode(expr))) {
1825 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1826 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1828 /* a Cmp A =/!= 0 */
1829 ir_node *op1 = expr;
1830 ir_node *op2 = expr;
1833 /* check, if expr is an only once used And operation */
1834 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1835 op1 = get_irn_n(expr, 2);
1836 op2 = get_irn_n(expr, 3);
1838 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1840 res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2);
1841 set_ia32_pncode(res, pnc);
1844 copy_ia32_Immop_attr(res, expr);
1847 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1852 if (mode_is_float(cmp_mode)) {
1854 if (USE_SSE2(env->cg)) {
1855 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1856 set_ia32_ls_mode(res, cmp_mode);
1862 assert(get_mode_size_bits(cmp_mode) == 32);
1863 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1865 copy_ia32_Immop_attr(res, cnst);
1868 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1870 if (mode_is_float(cmp_mode)) {
1872 if (USE_SSE2(env->cg)) {
1873 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1874 set_ia32_ls_mode(res, cmp_mode);
1877 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1878 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1879 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1883 assert(get_mode_size_bits(cmp_mode) == 32);
1884 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1885 set_ia32_commutative(res);
1889 set_ia32_pncode(res, pnc);
1890 // Matze: disabled for now, because the default collect_spills_walker
1891 // is not able to detect the mode of the spilled value
1892 // moreover, the lea optimize phase freely exchanges left/right
1893 // without updating the pnc
1894 //set_ia32_am_support(res, ia32_am_Source);
1897 /* determine the smallest switch case value */
1898 ir_node *new_sel = transform_node(env, sel);
1899 int switch_min = INT_MAX;
1900 const ir_edge_t *edge;
1902 foreach_out_edge(node, edge) {
1903 int pn = get_Proj_proj(get_edge_src_irn(edge));
1904 switch_min = pn < switch_min ? pn : switch_min;
1908 /* if smallest switch case is not 0 we need an additional sub */
1909 res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1910 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1911 add_ia32_am_offs_int(res, -switch_min);
1912 set_ia32_am_flavour(res, ia32_am_OB);
1913 set_ia32_am_support(res, ia32_am_Source);
1914 set_ia32_op_type(res, ia32_AddrModeS);
1917 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T);
1918 set_ia32_pncode(res, get_Cond_defaultProj(node));
1921 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1928 * Transforms a CopyB node.
1930 * @param env The transformation environment
1931 * @return The transformed node.
1933 static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) {
1934 ir_node *block = transform_node(env, get_nodes_block(node));
1935 ir_node *src = get_CopyB_src(node);
1936 ir_node *new_src = transform_node(env, src);
1937 ir_node *dst = get_CopyB_dst(node);
1938 ir_node *new_dst = transform_node(env, dst);
1939 ir_node *mem = get_CopyB_mem(node);
1940 ir_node *new_mem = transform_node(env, mem);
1941 ir_node *res = NULL;
1942 ir_graph *irg = env->irg;
1943 dbg_info *dbgi = get_irn_dbg_info(node);
1944 int size = get_type_size_bytes(get_CopyB_type(node));
1945 ir_mode *dst_mode = get_irn_mode(dst);
1946 ir_mode *src_mode = get_irn_mode(src);
1950 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1951 /* then we need the size explicitly in ECX. */
1952 if (size >= 32 * 4) {
1953 rem = size & 0x3; /* size % 4 */
1956 res = new_rd_ia32_Const(dbgi, irg, block);
1957 add_irn_dep(res, be_abi_get_start_barrier(env->cg->birg->abi));
1958 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1960 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1961 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1963 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1964 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1965 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1966 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1967 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1970 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1971 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1973 /* ok: now attach Proj's because movsd will destroy esi and edi */
1974 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1975 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1976 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1979 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1987 * Transforms a Mux node into CMov.
1989 * @param env The transformation environment
1990 * @return The transformed node.
1992 static ir_node *gen_Mux(ia32_transform_env_t *env, ir_node *node) {
1993 ir_node *new_op = new_rd_ia32_CMov(env->dbgi, env->irg, env->block, \
1994 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1996 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2002 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
2003 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
2004 ir_node *psi_default);
2007 * Transforms a Psi node into CMov.
2009 * @param env The transformation environment
2010 * @return The transformed node.
2012 static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) {
2013 ir_node *block = transform_node(env, get_nodes_block(node));
2014 ir_node *psi_true = get_Psi_val(node, 0);
2015 ir_node *new_psi_true = transform_node(env, psi_true);
2016 ir_node *psi_default = get_Psi_default(node);
2017 ir_node *new_psi_default = transform_node(env, psi_default);
2018 ia32_code_gen_t *cg = env->cg;
2019 ir_graph *irg = env->irg;
2020 dbg_info *dbgi = get_irn_dbg_info(node);
2021 ir_mode *mode = get_irn_mode(node);
2022 ir_node *cmp_proj = get_Mux_sel(node);
2023 ir_node *noreg = ia32_new_NoReg_gp(cg);
2024 ir_node *nomem = new_rd_NoMem(irg);
2025 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
2026 ir_node *new_cmp_a, *new_cmp_b;
2030 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
2032 cmp = get_Proj_pred(cmp_proj);
2033 cmp_a = get_Cmp_left(cmp);
2034 cmp_b = get_Cmp_right(cmp);
2035 cmp_mode = get_irn_mode(cmp_a);
2036 new_cmp_a = transform_node(env, cmp_a);
2037 new_cmp_b = transform_node(env, cmp_b);
2039 pnc = get_Proj_proj(cmp_proj);
2040 if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2041 pnc |= ia32_pn_Cmp_Unsigned;
2044 if (mode_is_float(mode)) {
2045 /* floating point psi */
2048 /* 1st case: compare operands are float too */
2050 /* psi(cmp(a, b), t, f) can be done as: */
2051 /* tmp = cmp a, b */
2052 /* tmp2 = t and tmp */
2053 /* tmp3 = f and not tmp */
2054 /* res = tmp2 or tmp3 */
2056 /* in case the compare operands are int, we move them into xmm register */
2057 if (! mode_is_float(get_irn_mode(cmp_a))) {
2058 new_cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_a, node, mode_xmm);
2059 new_cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_b, node, mode_xmm);
2061 pnc |= 8; /* transform integer compare to fp compare */
2064 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2065 set_ia32_pncode(new_op, pnc);
2066 set_ia32_am_support(new_op, ia32_am_Source);
2067 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2069 and1 = new_rd_ia32_xAnd(dbgi, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2070 set_ia32_am_support(and1, ia32_am_None);
2071 set_ia32_commutative(and1);
2072 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2074 and2 = new_rd_ia32_xAndNot(dbgi, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2075 set_ia32_am_support(and2, ia32_am_None);
2076 set_ia32_commutative(and2);
2077 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2079 new_op = new_rd_ia32_xOr(dbgi, irg, block, noreg, noreg, and1, and2, nomem);
2080 set_ia32_am_support(new_op, ia32_am_None);
2081 set_ia32_commutative(new_op);
2082 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2086 new_op = new_rd_ia32_vfCMov(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2087 set_ia32_pncode(new_op, pnc);
2088 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2093 construct_binop_func *set_func = NULL;
2094 cmov_func_t *cmov_func = NULL;
2096 if (mode_is_float(get_irn_mode(cmp_a))) {
2097 /* 1st case: compare operands are floats */
2102 set_func = new_rd_ia32_xCmpSet;
2103 cmov_func = new_rd_ia32_xCmpCMov;
2107 set_func = new_rd_ia32_vfCmpSet;
2108 cmov_func = new_rd_ia32_vfCmpCMov;
2111 pnc &= ~0x8; /* fp compare -> int compare */
2114 /* 2nd case: compare operand are integer too */
2115 set_func = new_rd_ia32_CmpSet;
2116 cmov_func = new_rd_ia32_CmpCMov;
2119 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2120 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2121 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2122 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2123 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2124 set_ia32_pncode(new_op, pnc);
2126 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2127 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2128 /* we invert condition and set default to 0 */
2129 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2130 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2133 /* otherwise: use CMOVcc */
2134 new_op = new_rd_ia32_PsiCondCMov(dbgi, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2135 set_ia32_pncode(new_op, pnc);
2138 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2141 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2142 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2143 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2144 set_ia32_pncode(new_op, pnc);
2145 set_ia32_am_support(new_op, ia32_am_Source);
2147 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2148 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2149 /* we invert condition and set default to 0 */
2150 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2151 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2152 set_ia32_am_support(new_op, ia32_am_Source);
2155 /* otherwise: use CMOVcc */
2156 new_op = cmov_func(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2157 set_ia32_pncode(new_op, pnc);
2158 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2168 * Following conversion rules apply:
2172 * 1) n bit -> m bit n > m (downscale)
2174 * 2) n bit -> m bit n == m (sign change)
2176 * 3) n bit -> m bit n < m (upscale)
2177 * a) source is signed: movsx
2178 * b) source is unsigned: and with lower bits sets
2182 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2186 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2190 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2191 * x87 is mode_E internally, conversions happen only at load and store
2192 * in non-strict semantic
2196 * Create a conversion from x87 state register to general purpose.
2198 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) {
2199 ir_node *block = transform_node(env, get_nodes_block(node));
2200 ir_node *op = get_Conv_op(node);
2201 ir_node *new_op = transform_node(env, op);
2202 ia32_code_gen_t *cg = env->cg;
2203 ir_graph *irg = env->irg;
2204 dbg_info *dbgi = get_irn_dbg_info(node);
2205 ir_node *noreg = ia32_new_NoReg_gp(cg);
2206 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2207 ir_node *fist, *load;
2210 fist = new_rd_ia32_vfist(dbgi, irg, block,
2211 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2213 set_ia32_use_frame(fist);
2214 set_ia32_am_support(fist, ia32_am_Dest);
2215 set_ia32_op_type(fist, ia32_AddrModeD);
2216 set_ia32_am_flavour(fist, ia32_am_B);
2217 set_ia32_ls_mode(fist, mode_Iu);
2218 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2221 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2223 set_ia32_use_frame(load);
2224 set_ia32_am_support(load, ia32_am_Source);
2225 set_ia32_op_type(load, ia32_AddrModeS);
2226 set_ia32_am_flavour(load, ia32_am_B);
2227 set_ia32_ls_mode(load, mode_Iu);
2228 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2230 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2234 * Create a conversion from general purpose to x87 register
2236 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mode *src_mode) {
2237 ir_node *block = transform_node(env, get_nodes_block(node));
2238 ir_node *op = get_Conv_op(node);
2239 ir_node *new_op = transform_node(env, op);
2240 ir_graph *irg = env->irg;
2241 dbg_info *dbgi = get_irn_dbg_info(node);
2242 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2243 ir_node *nomem = new_NoMem();
2244 ir_node *fild, *store;
2247 /* first convert to 32 bit if necessary */
2248 src_bits = get_mode_size_bits(src_mode);
2249 if (src_bits == 8) {
2250 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2251 set_ia32_am_support(new_op, ia32_am_Source);
2252 set_ia32_ls_mode(new_op, src_mode);
2253 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2254 } else if (src_bits < 32) {
2255 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2256 set_ia32_am_support(new_op, ia32_am_Source);
2257 set_ia32_ls_mode(new_op, src_mode);
2258 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2262 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2264 set_ia32_use_frame(store);
2265 set_ia32_am_support(store, ia32_am_Dest);
2266 set_ia32_op_type(store, ia32_AddrModeD);
2267 set_ia32_am_flavour(store, ia32_am_OB);
2268 set_ia32_ls_mode(store, mode_Iu);
2271 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2273 set_ia32_use_frame(fild);
2274 set_ia32_am_support(fild, ia32_am_Source);
2275 set_ia32_op_type(fild, ia32_AddrModeS);
2276 set_ia32_am_flavour(fild, ia32_am_OB);
2277 set_ia32_ls_mode(fild, mode_Iu);
2279 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2283 * Transforms a Conv node.
2285 * @param env The transformation environment
2286 * @return The created ia32 Conv node
2288 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) {
2289 ir_node *block = transform_node(env, get_nodes_block(node));
2290 ir_node *op = get_Conv_op(node);
2291 ir_node *new_op = transform_node(env, op);
2292 ir_graph *irg = env->irg;
2293 dbg_info *dbgi = get_irn_dbg_info(node);
2294 ir_mode *src_mode = get_irn_mode(op);
2295 ir_mode *tgt_mode = get_irn_mode(node);
2296 int src_bits = get_mode_size_bits(src_mode);
2297 int tgt_bits = get_mode_size_bits(tgt_mode);
2298 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2299 ir_node *nomem = new_rd_NoMem(irg);
2302 if (src_mode == tgt_mode) {
2303 if (get_Conv_strict(node)) {
2304 if (USE_SSE2(env->cg)) {
2305 /* when we are in SSE mode, we can kill all strict no-op conversion */
2309 /* this should be optimized already, but who knows... */
2310 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2311 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2316 if (mode_is_float(src_mode)) {
2317 /* we convert from float ... */
2318 if (mode_is_float(tgt_mode)) {
2320 if (USE_SSE2(env->cg)) {
2321 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2322 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2323 set_ia32_ls_mode(res, tgt_mode);
2325 // Matze: TODO what about strict convs?
2326 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: strict conv %+F ignored yet\n", node));
2327 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2332 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2333 if (USE_SSE2(env->cg)) {
2334 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2335 set_ia32_ls_mode(res, src_mode);
2337 return gen_x87_fp_to_gp(env, node);
2341 /* we convert from int ... */
2342 if (mode_is_float(tgt_mode)) {
2345 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2346 if (USE_SSE2(env->cg)) {
2347 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2348 set_ia32_ls_mode(res, tgt_mode);
2349 if(src_bits == 32) {
2350 set_ia32_am_support(res, ia32_am_Source);
2353 return gen_x87_gp_to_fp(env, node, src_mode);
2357 ir_mode *smaller_mode;
2360 if (src_bits == tgt_bits) {
2361 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2365 if (src_bits < tgt_bits) {
2366 smaller_mode = src_mode;
2367 smaller_bits = src_bits;
2369 smaller_mode = tgt_mode;
2370 smaller_bits = tgt_bits;
2374 The following is not correct, we can't change the mode,
2375 maybe others are using the load too
2376 better move this to a separate phase!
2380 if(is_Proj(new_op)) {
2381 /* load operations do already sign/zero extend, so we have
2382 * nothing left to do */
2383 ir_node *pred = get_Proj_pred(new_op);
2384 if(is_ia32_Load(pred)) {
2385 set_ia32_ls_mode(pred, smaller_mode);
2391 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2392 if (smaller_bits == 8) {
2393 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2394 set_ia32_ls_mode(res, smaller_mode);
2396 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2397 set_ia32_ls_mode(res, smaller_mode);
2399 set_ia32_am_support(res, ia32_am_Source);
2403 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2410 /********************************************
2413 * | |__ ___ _ __ ___ __| | ___ ___
2414 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2415 * | |_) | __/ | | | (_) | (_| | __/\__ \
2416 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2418 ********************************************/
2420 static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) {
2421 ir_node *block = transform_node(env, get_nodes_block(node));
2422 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2423 ir_node *new_ptr = transform_node(env, ptr);
2424 ir_node *new_op = NULL;
2425 ir_graph *irg = env->irg;
2426 dbg_info *dbgi = get_irn_dbg_info(node);
2427 ir_node *nomem = new_rd_NoMem(env->irg);
2428 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2429 ir_mode *load_mode = get_irn_mode(node);
2430 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2434 if (mode_is_float(load_mode)) {
2436 if (USE_SSE2(env->cg)) {
2437 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2438 pn_res = pn_ia32_xLoad_res;
2439 proj_mode = mode_xmm;
2441 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem);
2442 pn_res = pn_ia32_vfld_res;
2443 proj_mode = mode_vfp;
2446 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2447 proj_mode = mode_Iu;
2448 pn_res = pn_ia32_Load_res;
2451 set_ia32_frame_ent(new_op, ent);
2452 set_ia32_use_frame(new_op);
2454 set_ia32_am_support(new_op, ia32_am_Source);
2455 set_ia32_op_type(new_op, ia32_AddrModeS);
2456 set_ia32_am_flavour(new_op, ia32_am_B);
2457 set_ia32_ls_mode(new_op, load_mode);
2458 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2460 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2462 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2466 * Transforms a FrameAddr into an ia32 Add.
2468 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) {
2469 ir_node *block = transform_node(env, get_nodes_block(node));
2470 ir_node *op = get_irn_n(node, be_pos_FrameAddr_ptr);
2471 ir_node *new_op = transform_node(env, op);
2472 ir_graph *irg = env->irg;
2473 dbg_info *dbgi = get_irn_dbg_info(node);
2474 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2477 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2478 set_ia32_frame_ent(res, arch_get_frame_entity(env->cg->arch_env, node));
2479 set_ia32_am_support(res, ia32_am_Full);
2480 set_ia32_use_frame(res);
2481 set_ia32_am_flavour(res, ia32_am_OB);
2483 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2489 * Transforms a FrameLoad into an ia32 Load.
2491 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) {
2492 ir_node *block = transform_node(env, get_nodes_block(node));
2493 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2494 ir_node *new_mem = transform_node(env, mem);
2495 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2496 ir_node *new_ptr = transform_node(env, ptr);
2497 ir_node *new_op = NULL;
2498 ir_graph *irg = env->irg;
2499 dbg_info *dbgi = get_irn_dbg_info(node);
2500 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2501 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2502 ir_mode *mode = get_type_mode(get_entity_type(ent));
2503 ir_node *projs[pn_Load_max];
2505 ia32_collect_Projs(node, projs, pn_Load_max);
2507 if (mode_is_float(mode)) {
2509 if (USE_SSE2(env->cg)) {
2510 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2513 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
2517 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2520 set_ia32_frame_ent(new_op, ent);
2521 set_ia32_use_frame(new_op);
2523 set_ia32_am_support(new_op, ia32_am_Source);
2524 set_ia32_op_type(new_op, ia32_AddrModeS);
2525 set_ia32_am_flavour(new_op, ia32_am_B);
2526 set_ia32_ls_mode(new_op, mode);
2528 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2535 * Transforms a FrameStore into an ia32 Store.
2537 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) {
2538 ir_node *block = transform_node(env, get_nodes_block(node));
2539 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2540 ir_node *new_mem = transform_node(env, mem);
2541 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2542 ir_node *new_ptr = transform_node(env, ptr);
2543 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2544 ir_node *new_val = transform_node(env, val);
2545 ir_node *new_op = NULL;
2546 ir_graph *irg = env->irg;
2547 dbg_info *dbgi = get_irn_dbg_info(node);
2548 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2549 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2550 ir_mode *mode = get_irn_mode(val);
2552 if (mode_is_float(mode)) {
2554 if (USE_SSE2(env->cg)) {
2555 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2557 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2559 } else if (get_mode_size_bits(mode) == 8) {
2560 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2562 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2565 set_ia32_frame_ent(new_op, ent);
2566 set_ia32_use_frame(new_op);
2568 set_ia32_am_support(new_op, ia32_am_Dest);
2569 set_ia32_op_type(new_op, ia32_AddrModeD);
2570 set_ia32_am_flavour(new_op, ia32_am_B);
2571 set_ia32_ls_mode(new_op, mode);
2573 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2579 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2581 static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
2582 ir_graph *irg = env->irg;
2583 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2584 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2585 ir_entity *ent = get_irg_entity(irg);
2586 ir_type *tp = get_entity_type(ent);
2591 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2592 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2595 int pn_ret_val, pn_ret_mem, arity, i;
2597 assert(ret_val != NULL);
2598 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env->cg)) {
2599 return duplicate_node(env, node);
2602 res_type = get_method_res_type(tp, 0);
2604 if (! is_Primitive_type(res_type)) {
2605 return duplicate_node(env, node);
2608 mode = get_type_mode(res_type);
2609 if (! mode_is_float(mode)) {
2610 return duplicate_node(env, node);
2613 assert(get_method_n_ress(tp) == 1);
2615 pn_ret_val = get_Proj_proj(ret_val);
2616 pn_ret_mem = get_Proj_proj(ret_mem);
2618 /* get the Barrier */
2619 barrier = get_Proj_pred(ret_val);
2621 /* get result input of the Barrier */
2622 ret_val = get_irn_n(barrier, pn_ret_val);
2623 new_ret_val = transform_node(env, ret_val);
2625 /* get memory input of the Barrier */
2626 ret_mem = get_irn_n(barrier, pn_ret_mem);
2627 new_ret_mem = transform_node(env, ret_mem);
2629 frame = get_irg_frame(irg);
2631 dbgi = get_irn_dbg_info(barrier);
2632 block = transform_node(env, get_nodes_block(barrier));
2634 noreg = ia32_new_NoReg_gp(env->cg);
2636 /* store xmm0 onto stack */
2637 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
2638 set_ia32_ls_mode(sse_store, mode);
2639 set_ia32_op_type(sse_store, ia32_AddrModeD);
2640 set_ia32_use_frame(sse_store);
2641 set_ia32_am_flavour(sse_store, ia32_am_B);
2642 set_ia32_am_support(sse_store, ia32_am_Dest);
2645 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
2646 set_ia32_ls_mode(fld, mode);
2647 set_ia32_op_type(fld, ia32_AddrModeS);
2648 set_ia32_use_frame(fld);
2649 set_ia32_am_flavour(fld, ia32_am_B);
2650 set_ia32_am_support(fld, ia32_am_Source);
2652 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
2653 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
2654 arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2656 /* create a new barrier */
2657 arity = get_irn_arity(barrier);
2658 in = alloca(arity * sizeof(in[0]));
2659 for (i = 0; i < arity; ++i) {
2662 if (i == pn_ret_val) {
2664 } else if (i == pn_ret_mem) {
2667 ir_node *in = get_irn_n(barrier, i);
2668 new_in = transform_node(env, in);
2673 new_barrier = new_ir_node(dbgi, irg, block,
2674 get_irn_op(barrier), get_irn_mode(barrier),
2676 copy_node_attr(barrier, new_barrier);
2677 duplicate_deps(env, barrier, new_barrier);
2678 set_new_node(barrier, new_barrier);
2679 mark_irn_visited(barrier);
2681 /* transform normally */
2682 return duplicate_node(env, node);
2686 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2688 static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
2689 ir_node *block = transform_node(env, get_nodes_block(node));
2690 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
2691 ir_node *new_sz = transform_node(env, sz);
2692 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
2693 ir_node *new_sp = transform_node(env, sp);
2694 ir_graph *irg = env->irg;
2695 dbg_info *dbgi = get_irn_dbg_info(node);
2696 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2697 ir_node *nomem = new_NoMem();
2700 /* ia32 stack grows in reverse direction, make a SubSP */
2701 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2702 set_ia32_am_support(new_op, ia32_am_Source);
2703 fold_immediate(env, new_op, 2, 3);
2705 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2711 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
2713 static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
2714 ir_node *block = transform_node(env, get_nodes_block(node));
2715 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
2716 ir_node *new_sz = transform_node(env, sz);
2717 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
2718 ir_node *new_sp = transform_node(env, sp);
2719 ir_graph *irg = env->irg;
2720 dbg_info *dbgi = get_irn_dbg_info(node);
2721 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2722 ir_node *nomem = new_NoMem();
2725 /* ia32 stack grows in reverse direction, make an AddSP */
2726 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2727 set_ia32_am_support(new_op, ia32_am_Source);
2728 fold_immediate(env, new_op, 2, 3);
2730 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2736 * This function just sets the register for the Unknown node
2737 * as this is not done during register allocation because Unknown
2738 * is an "ignore" node.
2740 static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) {
2741 ir_mode *mode = get_irn_mode(node);
2743 if (mode_is_float(mode)) {
2744 if (USE_SSE2(env->cg))
2745 return ia32_new_Unknown_xmm(env->cg);
2747 return ia32_new_Unknown_vfp(env->cg);
2748 } else if (mode_needs_gp_reg(mode)) {
2749 return ia32_new_Unknown_gp(env->cg);
2751 assert(0 && "unsupported Unknown-Mode");
2758 * Change some phi modes
2760 static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
2761 ir_node *block = transform_node(env, get_nodes_block(node));
2762 ir_graph *irg = env->irg;
2763 dbg_info *dbgi = get_irn_dbg_info(node);
2764 ir_mode *mode = get_irn_mode(node);
2768 if(mode_needs_gp_reg(mode)) {
2769 /* we shouldn't have any 64bit stuff around anymore */
2770 assert(get_mode_size_bits(mode) <= 32);
2771 /* all integer operations are on 32bit registers now */
2773 } else if(mode_is_float(mode)) {
2774 assert(mode == mode_D || mode == mode_F);
2775 if (USE_SSE2(env->cg)) {
2782 /* phi nodes allow loops, so we use the old arguments for now
2783 * and fix this later */
2784 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
2785 copy_node_attr(node, phi);
2786 duplicate_deps(env, node, phi);
2788 set_new_node(node, phi);
2790 /* put the preds in the worklist */
2791 arity = get_irn_arity(node);
2792 for (i = 0; i < arity; ++i) {
2793 ir_node *pred = get_irn_n(node, i);
2794 pdeq_putr(env->worklist, pred);
2800 /**********************************************************************
2803 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2804 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2805 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2806 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2808 **********************************************************************/
2810 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2812 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2815 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2816 ir_node *val, ir_node *mem);
2819 * Transforms a lowered Load into a "real" one.
2821 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) {
2822 ir_node *block = transform_node(env, get_nodes_block(node));
2823 ir_node *ptr = get_irn_n(node, 0);
2824 ir_node *new_ptr = transform_node(env, ptr);
2825 ir_node *mem = get_irn_n(node, 1);
2826 ir_node *new_mem = transform_node(env, mem);
2827 ir_graph *irg = env->irg;
2828 dbg_info *dbgi = get_irn_dbg_info(node);
2829 ir_mode *mode = get_ia32_ls_mode(node);
2830 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2834 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2835 lowering we have x87 nodes, so we need to enforce simulation.
2837 if (mode_is_float(mode)) {
2839 if (fp_unit == fp_x87)
2843 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
2845 set_ia32_am_support(new_op, ia32_am_Source);
2846 set_ia32_op_type(new_op, ia32_AddrModeS);
2847 set_ia32_am_flavour(new_op, ia32_am_OB);
2848 set_ia32_am_offs_int(new_op, 0);
2849 set_ia32_am_scale(new_op, 1);
2850 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
2851 if (is_ia32_am_sc_sign(node))
2852 set_ia32_am_sc_sign(new_op);
2853 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
2854 if (is_ia32_use_frame(node)) {
2855 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2856 set_ia32_use_frame(new_op);
2859 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2865 * Transforms a lowered Store into a "real" one.
2867 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) {
2868 ir_node *block = transform_node(env, get_nodes_block(node));
2869 ir_node *ptr = get_irn_n(node, 0);
2870 ir_node *new_ptr = transform_node(env, ptr);
2871 ir_node *val = get_irn_n(node, 1);
2872 ir_node *new_val = transform_node(env, val);
2873 ir_node *mem = get_irn_n(node, 2);
2874 ir_node *new_mem = transform_node(env, mem);
2875 ir_graph *irg = env->irg;
2876 dbg_info *dbgi = get_irn_dbg_info(node);
2877 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2878 ir_mode *mode = get_ia32_ls_mode(node);
2881 ia32_am_flavour_t am_flav = ia32_B;
2884 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2885 lowering we have x87 nodes, so we need to enforce simulation.
2887 if (mode_is_float(mode)) {
2889 if (fp_unit == fp_x87)
2893 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2895 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
2897 add_ia32_am_offs_int(new_op, am_offs);
2900 set_ia32_am_support(new_op, ia32_am_Dest);
2901 set_ia32_op_type(new_op, ia32_AddrModeD);
2902 set_ia32_am_flavour(new_op, am_flav);
2903 set_ia32_ls_mode(new_op, mode);
2904 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2905 set_ia32_use_frame(new_op);
2907 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2914 * Transforms an ia32_l_XXX into a "real" XXX node
2916 * @param env The transformation environment
2917 * @return the created ia32 XXX node
2919 #define GEN_LOWERED_OP(op) \
2920 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2921 ir_mode *mode = get_irn_mode(node); \
2922 if (mode_is_float(mode)) \
2924 return gen_binop(env, node, get_binop_left(node), \
2925 get_binop_right(node), new_rd_ia32_##op); \
2928 #define GEN_LOWERED_x87_OP(op) \
2929 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2931 FORCE_x87(env->cg); \
2932 new_op = gen_binop_float(env, node, get_binop_left(node), \
2933 get_binop_right(node), new_rd_ia32_##op); \
2937 #define GEN_LOWERED_UNOP(op) \
2938 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2939 return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \
2942 #define GEN_LOWERED_SHIFT_OP(op) \
2943 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2944 return gen_shift_binop(env, node, get_binop_left(node), \
2945 get_binop_right(node), new_rd_ia32_##op); \
2948 #define GEN_LOWERED_LOAD(op, fp_unit) \
2949 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2950 return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \
2953 #define GEN_LOWERED_STORE(op, fp_unit) \
2954 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2955 return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \
2962 GEN_LOWERED_OP(IMul)
2964 GEN_LOWERED_x87_OP(vfprem)
2965 GEN_LOWERED_x87_OP(vfmul)
2966 GEN_LOWERED_x87_OP(vfsub)
2968 GEN_LOWERED_UNOP(Neg)
2970 GEN_LOWERED_LOAD(vfild, fp_x87)
2971 GEN_LOWERED_LOAD(Load, fp_none)
2972 /*GEN_LOWERED_STORE(vfist, fp_x87)
2975 GEN_LOWERED_STORE(Store, fp_none)
2977 static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
2978 ir_node *block = transform_node(env, get_nodes_block(node));
2979 ir_node *left = get_binop_left(node);
2980 ir_node *new_left = transform_node(env, left);
2981 ir_node *right = get_binop_right(node);
2982 ir_node *new_right = transform_node(env, right);
2983 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2984 ir_graph *irg = env->irg;
2985 dbg_info *dbgi = get_irn_dbg_info(node);
2988 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
2989 clear_ia32_commutative(vfdiv);
2990 set_ia32_am_support(vfdiv, ia32_am_Source);
2991 fold_immediate(env, vfdiv, 2, 3);
2993 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env->cg, node));
3001 * Transforms a l_MulS into a "real" MulS node.
3003 * @param env The transformation environment
3004 * @return the created ia32 Mul node
3006 static ir_node *gen_ia32_l_Mul(ia32_transform_env_t *env, ir_node *node) {
3007 ir_node *block = transform_node(env, get_nodes_block(node));
3008 ir_node *left = get_binop_left(node);
3009 ir_node *new_left = transform_node(env, left);
3010 ir_node *right = get_binop_right(node);
3011 ir_node *new_right = transform_node(env, right);
3012 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3013 ir_graph *irg = env->irg;
3014 dbg_info *dbgi = get_irn_dbg_info(node);
3017 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3018 /* and then skip the result Proj, because all needed Projs are already there. */
3019 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3020 clear_ia32_commutative(muls);
3021 set_ia32_am_support(muls, ia32_am_Source);
3022 fold_immediate(env, muls, 2, 3);
3024 /* check if EAX and EDX proj exist, add missing one */
3025 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3026 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3027 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3029 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env->cg, node));
3034 GEN_LOWERED_SHIFT_OP(Shl)
3035 GEN_LOWERED_SHIFT_OP(Shr)
3036 GEN_LOWERED_SHIFT_OP(Sar)
3039 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3040 * op1 - target to be shifted
3041 * op2 - contains bits to be shifted into target
3043 * Only op3 can be an immediate.
3045 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *node,
3046 ir_node *op1, ir_node *op2,
3049 ir_node *block = transform_node(env, get_nodes_block(node));
3050 ir_node *new_op1 = transform_node(env, op1);
3051 ir_node *new_op2 = transform_node(env, op2);
3052 ir_node *new_count = transform_node(env, count);
3053 ir_node *new_op = NULL;
3054 ir_graph *irg = env->irg;
3055 dbg_info *dbgi = get_irn_dbg_info(node);
3056 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3057 ir_node *nomem = new_NoMem();
3061 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3063 /* Check if immediate optimization is on and */
3064 /* if it's an operation with immediate. */
3065 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3067 /* Limit imm_op within range imm8 */
3069 tv = get_ia32_Immop_tarval(imm_op);
3072 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3073 set_ia32_Immop_tarval(imm_op, tv);
3080 /* integer operations */
3082 /* This is ShiftD with const */
3083 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3085 if (is_ia32_l_ShlD(node))
3086 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3087 new_op1, new_op2, noreg, nomem);
3089 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3090 new_op1, new_op2, noreg, nomem);
3091 copy_ia32_Immop_attr(new_op, imm_op);
3094 /* This is a normal ShiftD */
3095 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3096 if (is_ia32_l_ShlD(node))
3097 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3098 new_op1, new_op2, new_count, nomem);
3100 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3101 new_op1, new_op2, new_count, nomem);
3104 /* set AM support */
3105 // Matze: node has unsupported format (6inputs)
3106 //set_ia32_am_support(new_op, ia32_am_Dest);
3108 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3110 set_ia32_emit_cl(new_op);
3115 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env, ir_node *node) {
3116 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3117 get_irn_n(node, 1), get_irn_n(node, 2));
3120 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env, ir_node *node) {
3121 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3122 get_irn_n(node, 1), get_irn_n(node, 2));
3126 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3128 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) {
3129 ir_node *block = transform_node(env, get_nodes_block(node));
3130 ir_node *val = get_irn_n(node, 1);
3131 ir_node *new_val = transform_node(env, val);
3132 ia32_code_gen_t *cg = env->cg;
3133 ir_node *res = NULL;
3134 ir_graph *irg = env->irg;
3136 ir_node *noreg, *new_ptr, *new_mem;
3143 mem = get_irn_n(node, 2);
3144 new_mem = transform_node(env, mem);
3145 ptr = get_irn_n(node, 0);
3146 new_ptr = transform_node(env, ptr);
3147 noreg = ia32_new_NoReg_gp(cg);
3148 dbgi = get_irn_dbg_info(node);
3150 /* Store x87 -> MEM */
3151 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3152 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3153 set_ia32_use_frame(res);
3154 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3155 set_ia32_am_support(res, ia32_am_Dest);
3156 set_ia32_am_flavour(res, ia32_B);
3157 set_ia32_op_type(res, ia32_AddrModeD);
3159 /* Load MEM -> SSE */
3160 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3161 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3162 set_ia32_use_frame(res);
3163 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3164 set_ia32_am_support(res, ia32_am_Source);
3165 set_ia32_am_flavour(res, ia32_B);
3166 set_ia32_op_type(res, ia32_AddrModeS);
3167 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3173 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3175 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) {
3176 ir_node *block = transform_node(env, get_nodes_block(node));
3177 ir_node *val = get_irn_n(node, 1);
3178 ir_node *new_val = transform_node(env, val);
3179 ia32_code_gen_t *cg = env->cg;
3180 ir_graph *irg = env->irg;
3181 ir_node *res = NULL;
3182 ir_entity *fent = get_ia32_frame_ent(node);
3183 ir_mode *lsmode = get_ia32_ls_mode(node);
3185 ir_node *noreg, *new_ptr, *new_mem;
3189 if (! USE_SSE2(cg)) {
3190 /* SSE unit is not used -> skip this node. */
3194 ptr = get_irn_n(node, 0);
3195 new_ptr = transform_node(env, ptr);
3196 mem = get_irn_n(node, 2);
3197 new_mem = transform_node(env, mem);
3198 noreg = ia32_new_NoReg_gp(cg);
3199 dbgi = get_irn_dbg_info(node);
3201 /* Store SSE -> MEM */
3202 if (is_ia32_xLoad(skip_Proj(new_val))) {
3203 ir_node *ld = skip_Proj(new_val);
3205 /* we can vfld the value directly into the fpu */
3206 fent = get_ia32_frame_ent(ld);
3207 ptr = get_irn_n(ld, 0);
3208 offs = get_ia32_am_offs_int(ld);
3210 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3211 set_ia32_frame_ent(res, fent);
3212 set_ia32_use_frame(res);
3213 set_ia32_ls_mode(res, lsmode);
3214 set_ia32_am_support(res, ia32_am_Dest);
3215 set_ia32_am_flavour(res, ia32_B);
3216 set_ia32_op_type(res, ia32_AddrModeD);
3220 /* Load MEM -> x87 */
3221 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
3222 set_ia32_frame_ent(res, fent);
3223 set_ia32_use_frame(res);
3224 set_ia32_ls_mode(res, lsmode);
3225 add_ia32_am_offs_int(res, offs);
3226 set_ia32_am_support(res, ia32_am_Source);
3227 set_ia32_am_flavour(res, ia32_B);
3228 set_ia32_op_type(res, ia32_AddrModeS);
3229 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3234 /*********************************************************
3237 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3238 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3239 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3240 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3242 *********************************************************/
3245 * the BAD transformer.
3247 static ir_node *bad_transform(ia32_transform_env_t *env, ir_node *node) {
3248 panic("No transform function for %+F available.\n", node);
3252 static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) {
3253 /* end has to be duplicated manually because we need a dynamic in array */
3254 ir_graph *irg = env->irg;
3255 dbg_info *dbgi = get_irn_dbg_info(node);
3256 ir_node *block = transform_node(env, get_nodes_block(node));
3260 new_end = new_ir_node(dbgi, irg, block, op_End, mode_X, -1, NULL);
3261 copy_node_attr(node, new_end);
3262 duplicate_deps(env, node, new_end);
3264 set_irg_end(irg, new_end);
3265 set_new_node(new_end, new_end);
3267 /* transform preds */
3268 arity = get_irn_arity(node);
3269 for (i = 0; i < arity; ++i) {
3270 ir_node *in = get_irn_n(node, i);
3271 ir_node *new_in = transform_node(env, in);
3273 add_End_keepalive(new_end, new_in);
3279 static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) {
3280 ir_graph *irg = env->irg;
3281 dbg_info *dbgi = get_irn_dbg_info(node);
3282 ir_node *start_block = env->old_anchors[anchor_start_block];
3287 * We replace the ProjX from the start node with a jump,
3288 * so the startblock has no preds anymore now
3290 if (node == start_block) {
3291 return new_rd_Block(dbgi, irg, 0, NULL);
3294 /* we use the old blocks for now, because jumps allow cycles in the graph
3295 * we have to fix this later */
3296 block = new_ir_node(dbgi, irg, NULL, get_irn_op(node), get_irn_mode(node),
3297 get_irn_arity(node), get_irn_in(node) + 1);
3298 copy_node_attr(node, block);
3300 #ifdef DEBUG_libfirm
3301 block->node_nr = node->node_nr;
3303 set_new_node(node, block);
3305 /* put the preds in the worklist */
3306 arity = get_irn_arity(node);
3307 for (i = 0; i < arity; ++i) {
3308 ir_node *in = get_irn_n(node, i);
3309 pdeq_putr(env->worklist, in);
3315 static ir_node *gen_Proj_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
3316 ir_node *block = transform_node(env, get_nodes_block(node));
3317 ir_node *pred = get_Proj_pred(node);
3318 ir_node *new_pred = transform_node(env, pred);
3319 ir_graph *irg = env->irg;
3320 dbg_info *dbgi = get_irn_dbg_info(node);
3321 long proj = get_Proj_proj(node);
3323 if (proj == pn_be_AddSP_res) {
3324 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3325 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3327 } else if (proj == pn_be_AddSP_M) {
3328 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3332 return new_rd_Unknown(irg, get_irn_mode(node));
3335 static ir_node *gen_Proj_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
3336 ir_node *block = transform_node(env, get_nodes_block(node));
3337 ir_node *pred = get_Proj_pred(node);
3338 ir_node *new_pred = transform_node(env, pred);
3339 ir_graph *irg = env->irg;
3340 dbg_info *dbgi = get_irn_dbg_info(node);
3341 long proj = get_Proj_proj(node);
3343 if (proj == pn_be_SubSP_res) {
3344 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3345 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3347 } else if (proj == pn_be_SubSP_M) {
3348 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3352 return new_rd_Unknown(irg, get_irn_mode(node));
3355 static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) {
3356 ir_node *block = transform_node(env, get_nodes_block(node));
3357 ir_node *pred = get_Proj_pred(node);
3358 ir_node *new_pred = transform_node(env, pred);
3359 ir_graph *irg = env->irg;
3360 dbg_info *dbgi = get_irn_dbg_info(node);
3361 long proj = get_Proj_proj(node);
3363 /* renumber the proj */
3364 if (is_ia32_Load(new_pred)) {
3365 if (proj == pn_Load_res) {
3366 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3367 } else if (proj == pn_Load_M) {
3368 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3370 } else if (is_ia32_xLoad(new_pred)) {
3371 if (proj == pn_Load_res) {
3372 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3373 } else if (proj == pn_Load_M) {
3374 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3376 } else if (is_ia32_vfld(new_pred)) {
3377 if (proj == pn_Load_res) {
3378 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3379 } else if (proj == pn_Load_M) {
3380 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3385 return new_rd_Unknown(irg, get_irn_mode(node));
3388 static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) {
3389 ir_node *block = transform_node(env, get_nodes_block(node));
3390 ir_node *pred = get_Proj_pred(node);
3391 ir_node *new_pred = transform_node(env, pred);
3392 ir_graph *irg = env->irg;
3393 dbg_info *dbgi = get_irn_dbg_info(node);
3394 ir_mode *mode = get_irn_mode(node);
3395 long proj = get_Proj_proj(node);
3397 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3399 switch (get_irn_opcode(pred)) {
3403 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3405 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3413 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3415 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3423 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3424 case pn_DivMod_res_div:
3425 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3426 case pn_DivMod_res_mod:
3427 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3437 return new_rd_Unknown(irg, mode);
3440 static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node) {
3441 ir_node *block = transform_node(env, get_nodes_block(node));
3442 ir_node *pred = get_Proj_pred(node);
3443 ir_node *new_pred = transform_node(env, pred);
3444 ir_graph *irg = env->irg;
3445 dbg_info *dbgi = get_irn_dbg_info(node);
3446 ir_mode *mode = get_irn_mode(node);
3447 long proj = get_Proj_proj(node);
3450 case pn_CopyB_M_regular:
3451 if (is_ia32_CopyB_i(new_pred)) {
3452 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3453 } else if (is_ia32_CopyB(new_pred)) {
3454 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3462 return new_rd_Unknown(irg, mode);
3465 static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
3466 ir_node *block = transform_node(env, get_nodes_block(node));
3467 ir_node *pred = get_Proj_pred(node);
3468 ir_node *new_pred = transform_node(env, pred);
3469 ir_graph *irg = env->irg;
3470 dbg_info *dbgi = get_irn_dbg_info(node);
3471 ir_mode *mode = get_irn_mode(node);
3472 long proj = get_Proj_proj(node);
3475 case pn_ia32_l_vfdiv_M:
3476 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3477 case pn_ia32_l_vfdiv_res:
3478 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3483 return new_rd_Unknown(irg, mode);
3486 static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node) {
3487 ir_node *block = transform_node(env, get_nodes_block(node));
3488 ir_node *pred = get_Proj_pred(node);
3489 ir_node *new_pred = transform_node(env, pred);
3490 ir_graph *irg = env->irg;
3491 dbg_info *dbgi = get_irn_dbg_info(node);
3492 ir_mode *mode = get_irn_mode(node);
3493 long proj = get_Proj_proj(node);
3497 if (is_ia32_xDiv(new_pred)) {
3498 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3499 } else if (is_ia32_vfdiv(new_pred)) {
3500 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3504 if (is_ia32_xDiv(new_pred)) {
3505 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3506 } else if (is_ia32_vfdiv(new_pred)) {
3507 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3515 return new_rd_Unknown(irg, mode);
3518 static ir_node *gen_Proj_tls(ia32_transform_env_t *env, ir_node *node) {
3519 ir_node *block = transform_node(env, get_nodes_block(node));
3520 ir_graph *irg = env->irg;
3521 dbg_info *dbgi = NULL;
3522 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3527 static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) {
3528 ir_node *block = transform_node(env, get_nodes_block(node));
3529 ir_node *call = get_Proj_pred(node);
3530 ir_node *new_call = transform_node(env, call);
3531 ir_graph *irg = env->irg;
3532 dbg_info *dbgi = get_irn_dbg_info(node);
3533 long proj = get_Proj_proj(node);
3534 ir_mode *mode = get_irn_mode(node);
3536 const arch_register_class_t *cls;
3538 /* The following is kinda tricky: If we're using SSE, then we have to
3539 * move the result value of the call in floating point registers to an
3540 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3541 * after the call, we have to make sure to correctly make the
3542 * MemProj and the result Proj use these 2 nodes
3544 if (proj == pn_be_Call_M_regular) {
3545 // get new node for result, are we doing the sse load/store hack?
3546 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3547 ir_node *call_res_new;
3548 ir_node *call_res_pred = NULL;
3550 if (call_res != NULL) {
3551 call_res_new = transform_node(env, call_res);
3552 call_res_pred = get_Proj_pred(call_res_new);
3555 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3556 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3558 assert(is_ia32_xLoad(call_res_pred));
3559 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3562 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env->cg)) {
3564 ir_node *frame = get_irg_frame(irg);
3565 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3567 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3569 const arch_register_class_t *cls;
3571 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3572 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3574 /* store st(0) onto stack */
3575 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3577 set_ia32_ls_mode(fstp, mode);
3578 set_ia32_op_type(fstp, ia32_AddrModeD);
3579 set_ia32_use_frame(fstp);
3580 set_ia32_am_flavour(fstp, ia32_am_B);
3581 set_ia32_am_support(fstp, ia32_am_Dest);
3583 /* load into SSE register */
3584 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3585 set_ia32_ls_mode(sse_load, mode);
3586 set_ia32_op_type(sse_load, ia32_AddrModeS);
3587 set_ia32_use_frame(sse_load);
3588 set_ia32_am_flavour(sse_load, ia32_am_B);
3589 set_ia32_am_support(sse_load, ia32_am_Source);
3591 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3593 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3595 /* get a Proj representing a caller save register */
3596 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3597 assert(is_Proj(p) && "Proj expected.");
3599 /* user of the the proj is the Keep */
3600 p = get_edge_src_irn(get_irn_out_edge_first(p));
3601 assert(be_is_Keep(p) && "Keep expected.");
3603 /* keep the result */
3604 cls = arch_get_irn_reg_class(env->cg->arch_env, sse_load, -1);
3605 keepin[0] = sse_load;
3606 be_new_Keep(cls, irg, block, 1, keepin);
3611 /* transform call modes */
3612 if (mode_is_data(mode)) {
3613 cls = arch_get_irn_reg_class(env->cg->arch_env, node, -1);
3617 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3620 static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) {
3621 ir_graph *irg = env->irg;
3622 dbg_info *dbgi = get_irn_dbg_info(node);
3623 ir_node *pred = get_Proj_pred(node);
3624 long proj = get_Proj_proj(node);
3626 if (is_Store(pred) || be_is_FrameStore(pred)) {
3627 if (proj == pn_Store_M) {
3628 return transform_node(env, pred);
3631 return new_r_Bad(irg);
3633 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
3634 return gen_Proj_Load(env, node);
3635 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3636 return gen_Proj_DivMod(env, node);
3637 } else if (is_CopyB(pred)) {
3638 return gen_Proj_CopyB(env, node);
3639 } else if (is_Quot(pred)) {
3640 return gen_Proj_Quot(env, node);
3641 } else if (is_ia32_l_vfdiv(pred)) {
3642 return gen_Proj_l_vfdiv(env, node);
3643 } else if (be_is_SubSP(pred)) {
3644 return gen_Proj_be_SubSP(env, node);
3645 } else if (be_is_AddSP(pred)) {
3646 return gen_Proj_be_AddSP(env, node);
3647 } else if (be_is_Call(pred)) {
3648 return gen_Proj_be_Call(env, node);
3649 } else if (get_irn_op(pred) == op_Start) {
3650 if (proj == pn_Start_X_initial_exec) {
3651 ir_node *block = get_nodes_block(pred);
3654 /* we exchange the ProjX with a jump */
3655 block = transform_node(env, block);
3656 jump = new_rd_Jmp(dbgi, irg, block);
3657 ir_fprintf(stderr, "created jump: %+F\n", jump);
3660 if (node == env->old_anchors[anchor_tls]) {
3661 return gen_Proj_tls(env, node);
3664 ir_node *new_pred = transform_node(env, pred);
3665 ir_node *block = transform_node(env, get_nodes_block(node));
3666 ir_mode *mode = get_irn_mode(node);
3667 if (mode_needs_gp_reg(mode)) {
3668 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
3669 get_Proj_proj(node));
3670 #ifdef DEBUG_libfirm
3671 new_proj->node_nr = node->node_nr;
3677 return duplicate_node(env, node);
3681 * Enters all transform functions into the generic pointer
3683 static void register_transformers(void) {
3684 ir_op *op_Max, *op_Min, *op_Mulh;
3686 /* first clear the generic function pointer for all ops */
3687 clear_irp_opcodes_generic_func();
3689 #define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3690 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
3729 /* transform ops from intrinsic lowering */
3749 /* GEN(ia32_l_vfist); TODO */
3751 GEN(ia32_l_X87toSSE);
3752 GEN(ia32_l_SSEtoX87);
3757 /* we should never see these nodes */
3772 /* handle generic backend nodes */
3782 /* set the register for all Unknown nodes */
3785 op_Max = get_op_Max();
3788 op_Min = get_op_Min();
3791 op_Mulh = get_op_Mulh();
3799 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
3803 int deps = get_irn_deps(old_node);
3805 for (i = 0; i < deps; ++i) {
3806 ir_node *dep = get_irn_dep(old_node, i);
3807 ir_node *new_dep = transform_node(env, dep);
3809 add_irn_dep(new_node, new_dep);
3813 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node)
3815 ir_node *block = transform_node(env, get_nodes_block(node));
3816 ir_graph *irg = env->irg;
3817 dbg_info *dbgi = get_irn_dbg_info(node);
3818 ir_mode *mode = get_irn_mode(node);
3819 ir_op *op = get_irn_op(node);
3823 arity = get_irn_arity(node);
3824 if (op->opar == oparity_dynamic) {
3825 new_node = new_ir_node(dbgi, irg, block, op, mode, -1, NULL);
3826 for (i = 0; i < arity; ++i) {
3827 ir_node *in = get_irn_n(node, i);
3828 in = transform_node(env, in);
3829 add_irn_n(new_node, in);
3832 ir_node **ins = alloca(arity * sizeof(ins[0]));
3833 for (i = 0; i < arity; ++i) {
3834 ir_node *in = get_irn_n(node, i);
3835 ins[i] = transform_node(env, in);
3838 new_node = new_ir_node(dbgi, irg, block, op, mode, arity, ins);
3841 copy_node_attr(node, new_node);
3842 duplicate_deps(env, node, new_node);
3844 #ifdef DEBUG_libfirm
3845 new_node->node_nr = node->node_nr;
3852 * Calls transformation function for given node and marks it visited.
3854 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node) {
3856 ir_op *op = get_irn_op(node);
3858 if (irn_visited(node)) {
3859 assert(get_new_node(node) != NULL);
3860 return get_new_node(node);
3863 mark_irn_visited(node);
3864 DEBUG_ONLY(set_new_node(node, NULL));
3866 if (op->ops.generic) {
3867 transform_func *transform = (transform_func *)op->ops.generic;
3869 new_node = (*transform)(env, node);
3870 assert(new_node != NULL);
3872 new_node = duplicate_node(env, node);
3874 DB((dbg, LEVEL_4, "%+F -> %+F\n", node, new_node));
3876 set_new_node(node, new_node);
3877 mark_irn_visited(new_node);
3878 hook_dead_node_elim_subst(current_ir_graph, node, new_node);
3883 * Rewire nodes which are potential loops (like Phis) to avoid endless loops.
3885 static void fix_loops(ia32_transform_env_t *env, ir_node *node) {
3888 if (irn_visited(node))
3891 mark_irn_visited(node);
3893 assert(node_is_in_irgs_storage(env->irg, node));
3895 if (! is_Block(node)) {
3896 ir_node *block = get_nodes_block(node);
3897 ir_node *new_block = (ir_node *)get_irn_link(block);
3899 if (new_block != NULL) {
3900 set_nodes_block(node, new_block);
3904 fix_loops(env, block);
3907 arity = get_irn_arity(node);
3908 for (i = 0; i < arity; ++i) {
3909 ir_node *in = get_irn_n(node, i);
3910 ir_node *nw = (ir_node *)get_irn_link(in);
3912 if (nw != NULL && nw != in) {
3913 set_irn_n(node, i, nw);
3920 arity = get_irn_deps(node);
3921 for (i = 0; i < arity; ++i) {
3922 ir_node *in = get_irn_dep(node, i);
3923 ir_node *nw = (ir_node *)get_irn_link(in);
3925 if (nw != NULL && nw != in) {
3926 set_irn_dep(node, i, nw);
3934 static void pre_transform_node(ir_node **place, ia32_transform_env_t *env)
3939 *place = transform_node(env, *place);
3943 * Transforms all nodes. Deletes the old obstack and creates a new one.
3945 static void transform_nodes(ia32_code_gen_t *cg) {
3947 ir_graph *irg = cg->irg;
3949 ia32_transform_env_t env;
3951 hook_dead_node_elim(irg, 1);
3953 inc_irg_visited(irg);
3957 env.visited = get_irg_visited(irg);
3958 env.worklist = new_pdeq();
3959 env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
3961 old_end = get_irg_end(irg);
3963 /* put all anchor nodes in the worklist */
3964 for (i = 0; i < anchor_max; ++i) {
3965 ir_node *anchor = irg->anchors[i];
3969 pdeq_putr(env.worklist, anchor);
3971 /* remember anchor */
3972 env.old_anchors[i] = anchor;
3973 /* and set it to NULL to make sure we don't accidently use it */
3974 irg->anchors[i] = NULL;
3977 /* pre transform some anchors (so they are available in the other transform
3979 set_irg_bad(irg, transform_node(&env, env.old_anchors[anchor_bad]));
3980 set_irg_no_mem(irg, transform_node(&env, env.old_anchors[anchor_no_mem]));
3981 set_irg_start_block(irg, transform_node(&env, env.old_anchors[anchor_start_block]));
3982 set_irg_start(irg, transform_node(&env, env.old_anchors[anchor_start]));
3983 set_irg_frame(irg, transform_node(&env, env.old_anchors[anchor_frame]));
3985 pre_transform_node(&cg->unknown_gp, &env);
3986 pre_transform_node(&cg->unknown_vfp, &env);
3987 pre_transform_node(&cg->unknown_xmm, &env);
3988 pre_transform_node(&cg->noreg_gp, &env);
3989 pre_transform_node(&cg->noreg_vfp, &env);
3990 pre_transform_node(&cg->noreg_xmm, &env);
3992 /* process worklist (this should transform all nodes in the graph) */
3993 while (! pdeq_empty(env.worklist)) {
3994 ir_node *node = pdeq_getl(env.worklist);
3995 transform_node(&env, node);
3998 /* fix loops and set new anchors*/
3999 inc_irg_visited(irg);
4000 for (i = 0; i < anchor_max; ++i) {
4001 ir_node *anchor = env.old_anchors[i];
4006 anchor = get_irn_link(anchor);
4007 fix_loops(&env, anchor);
4008 assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
4009 irg->anchors[i] = anchor;
4012 del_pdeq(env.worklist);
4014 hook_dead_node_elim(irg, 0);
4017 void ia32_transform_graph(ia32_code_gen_t *cg)
4019 ir_graph *irg = cg->irg;
4020 be_irg_t *birg = cg->birg;
4021 ir_graph *old_current_ir_graph = current_ir_graph;
4022 int old_interprocedural_view = get_interprocedural_view();
4023 struct obstack *old_obst = NULL;
4024 struct obstack *new_obst = NULL;
4026 current_ir_graph = irg;
4027 set_interprocedural_view(0);
4028 register_transformers();
4030 /* most analysis info is wrong after transformation */
4031 free_callee_info(irg);
4033 irg->outs_state = outs_none;
4035 free_loop_information(irg);
4036 set_irg_doms_inconsistent(irg);
4037 be_invalidate_liveness(birg);
4038 be_invalidate_dom_front(birg);
4040 /* create a new obstack */
4041 old_obst = irg->obst;
4042 new_obst = xmalloc(sizeof(*new_obst));
4043 obstack_init(new_obst);
4044 irg->obst = new_obst;
4045 irg->last_node_idx = 0;
4047 /* create new value table for CSE */
4048 del_identities(irg->value_table);
4049 irg->value_table = new_identities();
4051 /* do the main transformation */
4052 transform_nodes(cg);
4054 /* we don't want the globals anchor anymore */
4055 set_irg_globals(irg, new_r_Bad(irg));
4057 /* free the old obstack */
4058 obstack_free(old_obst, 0);
4062 current_ir_graph = old_current_ir_graph;
4063 set_interprocedural_view(old_interprocedural_view);
4065 /* recalculate edges */
4066 edges_deactivate(irg);
4067 edges_activate(irg);
4071 * Transforms a psi condition.
4073 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
4076 /* if the mode is target mode, we have already seen this part of the tree */
4077 if (get_irn_mode(cond) == mode)
4080 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
4082 set_irn_mode(cond, mode);
4084 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
4085 ir_node *in = get_irn_n(cond, i);
4087 /* if in is a compare: transform into Set/xCmp */
4089 ir_node *new_op = NULL;
4090 ir_node *cmp = get_Proj_pred(in);
4091 ir_node *cmp_a = get_Cmp_left(cmp);
4092 ir_node *cmp_b = get_Cmp_right(cmp);
4093 dbg_info *dbgi = get_irn_dbg_info(cmp);
4094 ir_graph *irg = get_irn_irg(cmp);
4095 ir_node *block = get_nodes_block(cmp);
4096 ir_node *noreg = ia32_new_NoReg_gp(cg);
4097 ir_node *nomem = new_rd_NoMem(irg);
4098 int pnc = get_Proj_proj(in);
4100 /* this is a compare */
4101 if (mode_is_float(mode)) {
4102 /* Psi is float, we need a floating point compare */
4105 ir_mode *m = get_irn_mode(cmp_a);
4107 if (! mode_is_float(m)) {
4108 cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_a, cmp_a, mode);
4109 cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_b, cmp_b, mode);
4110 } else if (m == mode_F) {
4111 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
4112 cmp_a = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_a, cmp_a);
4113 cmp_b = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_b, cmp_b);
4116 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4117 set_ia32_pncode(new_op, pnc);
4118 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
4125 construct_binop_func *set_func = NULL;
4127 if (mode_is_float(get_irn_mode(cmp_a))) {
4128 /* 1st case: compare operands are floats */
4133 set_func = new_rd_ia32_xCmpSet;
4136 set_func = new_rd_ia32_vfCmpSet;
4139 pnc &= 7; /* fp compare -> int compare */
4141 /* 2nd case: compare operand are integer too */
4142 set_func = new_rd_ia32_CmpSet;
4145 new_op = set_func(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4146 if (! mode_is_signed(mode))
4147 pnc |= ia32_pn_Cmp_Unsigned;
4149 set_ia32_pncode(new_op, pnc);
4150 set_ia32_am_support(new_op, ia32_am_Source);
4153 /* the the new compare as in */
4154 set_irn_n(cond, i, new_op);
4156 /* another complex condition */
4157 transform_psi_cond(in, mode, cg);
4163 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
4164 * We create a Set node, respectively a xCmp in case the Psi is a float, for
4165 * each compare, which causes the compare result to be stored in a register. The
4166 * "And"s and "Or"s are transformed later, we just have to set their mode right.
4168 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
4169 ia32_code_gen_t *cg = env;
4170 ir_node *psi_sel, *new_cmp, *block;
4175 if (get_irn_opcode(node) != iro_Psi)
4178 psi_sel = get_Psi_cond(node, 0);
4180 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
4181 if (is_Proj(psi_sel)) {
4182 assert(is_Cmp(get_Proj_pred(psi_sel)));
4186 //mode = get_irn_mode(node);
4187 // TODO probably wrong...
4190 transform_psi_cond(psi_sel, mode, cg);
4192 irg = get_irn_irg(node);
4193 block = get_nodes_block(node);
4195 /* we need to compare the evaluated condition tree with 0 */
4196 mode = get_irn_mode(node);
4197 if (mode_is_float(mode)) {
4198 /* BEWARE: new_r_Const_long works for floating point as well */
4199 ir_node *zero = new_r_Const_long(irg, block, mode, 0);
4201 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
4202 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4203 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
4205 ir_node *zero = new_r_Const_long(irg, block, mode_Iu, 0);
4206 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4207 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
4210 set_Psi_cond(node, 0, new_cmp);
4213 void ia32_init_transform(void)
4215 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");