2 * This file implements the IR transformation from firm into
16 #include "irgraph_t.h"
21 #include "iredges_t.h"
29 #include "../benode_t.h"
30 #include "../besched.h"
32 #include "bearch_ia32_t.h"
34 #include "ia32_nodes_attr.h"
35 #include "../arch/archop.h" /* we need this for Min and Max nodes */
36 #include "ia32_transform.h"
37 #include "ia32_new_nodes.h"
38 #include "ia32_map_regs.h"
39 #include "ia32_dbg_stat.h"
41 #include "gen_ia32_regalloc_if.h"
43 #define SFP_SIGN "0x80000000"
44 #define DFP_SIGN "0x8000000000000000"
45 #define SFP_ABS "0x7FFFFFFF"
46 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
48 #define TP_SFP_SIGN "ia32_sfp_sign"
49 #define TP_DFP_SIGN "ia32_dfp_sign"
50 #define TP_SFP_ABS "ia32_sfp_abs"
51 #define TP_DFP_ABS "ia32_dfp_abs"
53 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
54 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
55 #define ENT_SFP_ABS "IA32_SFP_ABS"
56 #define ENT_DFP_ABS "IA32_DFP_ABS"
58 extern ir_op *get_op_Mulh(void);
60 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
61 ir_node *op1, ir_node *op2, ir_node *mem);
63 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
64 ir_node *op, ir_node *mem);
67 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
70 /****************************************************************************************************
72 * | | | | / _| | | (_)
73 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
74 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
75 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
76 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
78 ****************************************************************************************************/
81 * Gets the Proj with number pn from irn.
83 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
84 const ir_edge_t *edge;
86 assert(get_irn_mode(irn) == mode_T && "need mode_T");
88 foreach_out_edge(irn, edge) {
89 proj = get_edge_src_irn(edge);
91 if (get_Proj_proj(proj) == pn)
98 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
99 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
100 static const struct {
102 const char *ent_name;
103 const char *cnst_str;
104 } names [ia32_known_const_max] = {
105 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
106 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
107 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
108 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
110 static struct entity *ent_cache[ia32_known_const_max];
112 const char *tp_name, *ent_name, *cnst_str;
119 ent_name = names[kct].ent_name;
120 if (! ent_cache[kct]) {
121 tp_name = names[kct].tp_name;
122 cnst_str = names[kct].cnst_str;
124 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
125 tp = new_type_primitive(new_id_from_str(tp_name), mode);
126 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
128 set_entity_ld_ident(ent, get_entity_ident(ent));
129 set_entity_visibility(ent, visibility_local);
130 set_entity_variability(ent, variability_constant);
131 set_entity_allocation(ent, allocation_static);
133 /* we create a new entity here: It's initialization must resist on the
135 rem = current_ir_graph;
136 current_ir_graph = get_const_code_irg();
137 cnst = new_Const(mode, tv);
138 current_ir_graph = rem;
140 set_atomic_ent_value(ent, cnst);
142 /* cache the entry */
143 ent_cache[kct] = ent;
146 return get_entity_ident(ent_cache[kct]);
151 * Prints the old node name on cg obst and returns a pointer to it.
153 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
154 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
156 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
157 obstack_1grow(isa->name_obst, 0);
158 isa->name_obst_size += obstack_object_size(isa->name_obst);
159 return obstack_finish(isa->name_obst);
163 /* determine if one operator is an Imm */
164 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
166 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
167 else return is_ia32_Cnst(op2) ? op2 : NULL;
170 /* determine if one operator is not an Imm */
171 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
172 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
177 * Construct a standard binary operation, set AM and immediate if required.
179 * @param env The transformation environment
180 * @param op1 The first operand
181 * @param op2 The second operand
182 * @param func The node constructor function
183 * @return The constructed ia32 node.
185 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
186 ir_node *new_op = NULL;
187 ir_mode *mode = env->mode;
188 dbg_info *dbg = env->dbg;
189 ir_graph *irg = env->irg;
190 ir_node *block = env->block;
191 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
192 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
193 ir_node *nomem = new_NoMem();
194 ir_node *expr_op, *imm_op;
195 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
197 /* Check if immediate optimization is on and */
198 /* if it's an operation with immediate. */
199 if (! (env->cg->opt & IA32_OPT_IMMOPS)) {
203 else if (is_op_commutative(get_irn_op(env->irn))) {
204 imm_op = get_immediate_op(op1, op2);
205 expr_op = get_expr_op(op1, op2);
208 imm_op = get_immediate_op(NULL, op2);
209 expr_op = get_expr_op(op1, op2);
212 assert((expr_op || imm_op) && "invalid operands");
215 /* We have two consts here: not yet supported */
219 if (mode_is_float(mode)) {
220 /* floating point operations */
222 DB((mod, LEVEL_1, "FP with immediate ..."));
223 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
224 set_ia32_Immop_attr(new_op, imm_op);
225 set_ia32_am_support(new_op, ia32_am_None);
228 DB((mod, LEVEL_1, "FP binop ..."));
229 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
230 set_ia32_am_support(new_op, ia32_am_Source);
232 set_ia32_ls_mode(new_op, mode);
235 /* integer operations */
237 /* This is expr + const */
238 DB((mod, LEVEL_1, "INT with immediate ..."));
239 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
240 set_ia32_Immop_attr(new_op, imm_op);
243 set_ia32_am_support(new_op, ia32_am_Dest);
246 DB((mod, LEVEL_1, "INT binop ..."));
247 /* This is a normal operation */
248 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
251 set_ia32_am_support(new_op, ia32_am_Full);
255 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
257 set_ia32_res_mode(new_op, mode);
259 if (is_op_commutative(get_irn_op(env->irn))) {
260 set_ia32_commutative(new_op);
263 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
269 * Construct a shift/rotate binary operation, sets AM and immediate if required.
271 * @param env The transformation environment
272 * @param op1 The first operand
273 * @param op2 The second operand
274 * @param func The node constructor function
275 * @return The constructed ia32 node.
277 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
278 ir_node *new_op = NULL;
279 ir_mode *mode = env->mode;
280 dbg_info *dbg = env->dbg;
281 ir_graph *irg = env->irg;
282 ir_node *block = env->block;
283 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
284 ir_node *nomem = new_NoMem();
285 ir_node *expr_op, *imm_op;
287 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
289 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
291 /* Check if immediate optimization is on and */
292 /* if it's an operation with immediate. */
293 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
294 expr_op = get_expr_op(op1, op2);
296 assert((expr_op || imm_op) && "invalid operands");
299 /* We have two consts here: not yet supported */
303 /* Limit imm_op within range imm8 */
305 tv = get_ia32_Immop_tarval(imm_op);
308 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
315 /* integer operations */
317 /* This is shift/rot with const */
318 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
320 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
321 set_ia32_Immop_attr(new_op, imm_op);
324 /* This is a normal shift/rot */
325 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
326 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
330 set_ia32_am_support(new_op, ia32_am_Dest);
332 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
334 set_ia32_res_mode(new_op, mode);
335 set_ia32_emit_cl(new_op);
337 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
342 * Construct a standard unary operation, set AM and immediate if required.
344 * @param env The transformation environment
345 * @param op The operand
346 * @param func The node constructor function
347 * @return The constructed ia32 node.
349 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
350 ir_node *new_op = NULL;
351 ir_mode *mode = env->mode;
352 dbg_info *dbg = env->dbg;
353 ir_graph *irg = env->irg;
354 ir_node *block = env->block;
355 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
356 ir_node *nomem = new_NoMem();
357 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
359 new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
361 if (mode_is_float(mode)) {
362 DB((mod, LEVEL_1, "FP unop ..."));
363 /* floating point operations don't support implicit store */
364 set_ia32_am_support(new_op, ia32_am_None);
367 DB((mod, LEVEL_1, "INT unop ..."));
368 set_ia32_am_support(new_op, ia32_am_Dest);
371 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
373 set_ia32_res_mode(new_op, mode);
375 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
381 * Creates an ia32 Add with immediate.
383 * @param env The transformation environment
384 * @param expr_op The expression operator
385 * @param const_op The constant
386 * @return the created ia32 Add node
388 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
389 ir_node *new_op = NULL;
390 tarval *tv = get_ia32_Immop_tarval(const_op);
391 dbg_info *dbg = env->dbg;
392 ir_graph *irg = env->irg;
393 ir_node *block = env->block;
394 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
395 ir_node *nomem = new_NoMem();
397 tarval_classification_t class_tv, class_negtv;
398 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
400 /* try to optimize to inc/dec */
401 if ((env->cg->opt & IA32_OPT_INCDEC) && (get_ia32_op_type(const_op) == ia32_Const)) {
402 /* optimize tarvals */
403 class_tv = classify_tarval(tv);
404 class_negtv = classify_tarval(tarval_neg(tv));
406 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
407 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
408 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
411 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
412 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
413 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
419 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
420 set_ia32_Immop_attr(new_op, const_op);
421 set_ia32_commutative(new_op);
428 * Creates an ia32 Add.
430 * @param env The transformation environment
431 * @return the created ia32 Add node
433 static ir_node *gen_Add(ia32_transform_env_t *env) {
434 ir_node *new_op = NULL;
435 dbg_info *dbg = env->dbg;
436 ir_mode *mode = env->mode;
437 ir_graph *irg = env->irg;
438 ir_node *block = env->block;
439 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
440 ir_node *nomem = new_NoMem();
441 ir_node *expr_op, *imm_op;
442 ir_node *op1 = get_Add_left(env->irn);
443 ir_node *op2 = get_Add_right(env->irn);
445 /* Check if immediate optimization is on and */
446 /* if it's an operation with immediate. */
447 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
448 expr_op = get_expr_op(op1, op2);
450 assert((expr_op || imm_op) && "invalid operands");
452 if (mode_is_float(mode)) {
454 if (USE_SSE2(env->cg))
455 return gen_binop(env, op1, op2, new_rd_ia32_xAdd);
457 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
462 /* No expr_op means, that we have two const - one symconst and */
463 /* one tarval or another symconst - because this case is not */
464 /* covered by constant folding */
465 /* We need to check for: */
466 /* 1) symconst + const -> becomes a LEA */
467 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
468 /* linker doesn't support two symconsts */
470 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
471 /* this is the 2nd case */
472 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
473 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
474 set_ia32_am_flavour(new_op, ia32_am_OB);
477 /* this is the 1st case */
478 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
480 if (get_ia32_op_type(op1) == ia32_SymConst) {
481 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
482 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
485 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
486 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
488 set_ia32_am_flavour(new_op, ia32_am_O);
492 set_ia32_am_support(new_op, ia32_am_Source);
493 set_ia32_op_type(new_op, ia32_AddrModeS);
495 /* Lea doesn't need a Proj */
499 /* This is expr + const */
500 new_op = gen_imm_Add(env, expr_op, imm_op);
503 set_ia32_am_support(new_op, ia32_am_Dest);
506 /* This is a normal add */
507 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
510 set_ia32_am_support(new_op, ia32_am_Full);
511 set_ia32_commutative(new_op);
515 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
517 set_ia32_res_mode(new_op, mode);
519 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
525 * Creates an ia32 Mul.
527 * @param env The transformation environment
528 * @return the created ia32 Mul node
530 static ir_node *gen_Mul(ia32_transform_env_t *env) {
531 ir_node *op1 = get_Mul_left(env->irn);
532 ir_node *op2 = get_Mul_right(env->irn);
535 if (mode_is_float(env->mode)) {
537 if (USE_SSE2(env->cg))
538 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMul);
540 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
543 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
552 * Creates an ia32 Mulh.
553 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
554 * this result while Mul returns the lower 32 bit.
556 * @param env The transformation environment
557 * @return the created ia32 Mulh node
559 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
560 ir_node *op1 = get_irn_n(env->irn, 0);
561 ir_node *op2 = get_irn_n(env->irn, 1);
562 ir_node *proj_EAX, *proj_EDX, *mulh;
565 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
566 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
567 mulh = get_Proj_pred(proj_EAX);
568 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
570 /* to be on the save side */
571 set_Proj_proj(proj_EAX, pn_EAX);
573 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
574 /* Mulh with const cannot have AM */
575 set_ia32_am_support(mulh, ia32_am_None);
578 /* Mulh cannot have AM for destination */
579 set_ia32_am_support(mulh, ia32_am_Source);
585 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
593 * Creates an ia32 And.
595 * @param env The transformation environment
596 * @return The created ia32 And node
598 static ir_node *gen_And(ia32_transform_env_t *env) {
599 ir_node *op1 = get_And_left(env->irn);
600 ir_node *op2 = get_And_right(env->irn);
602 assert (! mode_is_float(env->mode));
603 return gen_binop(env, op1, op2, new_rd_ia32_And);
609 * Creates an ia32 Or.
611 * @param env The transformation environment
612 * @return The created ia32 Or node
614 static ir_node *gen_Or(ia32_transform_env_t *env) {
615 ir_node *op1 = get_Or_left(env->irn);
616 ir_node *op2 = get_Or_right(env->irn);
618 assert (! mode_is_float(env->mode));
619 return gen_binop(env, op1, op2, new_rd_ia32_Or);
625 * Creates an ia32 Eor.
627 * @param env The transformation environment
628 * @return The created ia32 Eor node
630 static ir_node *gen_Eor(ia32_transform_env_t *env) {
631 ir_node *op1 = get_Eor_left(env->irn);
632 ir_node *op2 = get_Eor_right(env->irn);
634 assert(! mode_is_float(env->mode));
635 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
641 * Creates an ia32 Max.
643 * @param env The transformation environment
644 * @return the created ia32 Max node
646 static ir_node *gen_Max(ia32_transform_env_t *env) {
647 ir_node *op1 = get_irn_n(env->irn, 0);
648 ir_node *op2 = get_irn_n(env->irn, 1);
651 if (mode_is_float(env->mode)) {
653 if (USE_SSE2(env->cg))
654 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMax);
660 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
661 set_ia32_am_support(new_op, ia32_am_None);
662 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
671 * Creates an ia32 Min.
673 * @param env The transformation environment
674 * @return the created ia32 Min node
676 static ir_node *gen_Min(ia32_transform_env_t *env) {
677 ir_node *op1 = get_irn_n(env->irn, 0);
678 ir_node *op2 = get_irn_n(env->irn, 1);
681 if (mode_is_float(env->mode)) {
683 if (USE_SSE2(env->cg))
684 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMin);
690 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
691 set_ia32_am_support(new_op, ia32_am_None);
692 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
701 * Creates an ia32 Sub with immediate.
703 * @param env The transformation environment
704 * @param expr_op The first operator
705 * @param const_op The constant operator
706 * @return The created ia32 Sub node
708 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
709 ir_node *new_op = NULL;
710 tarval *tv = get_ia32_Immop_tarval(const_op);
711 dbg_info *dbg = env->dbg;
712 ir_graph *irg = env->irg;
713 ir_node *block = env->block;
714 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
715 ir_node *nomem = new_NoMem();
717 tarval_classification_t class_tv, class_negtv;
718 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
720 /* try to optimize to inc/dec */
721 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
722 /* optimize tarvals */
723 class_tv = classify_tarval(tv);
724 class_negtv = classify_tarval(tarval_neg(tv));
726 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
727 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
728 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
731 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
732 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
733 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
739 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
740 set_ia32_Immop_attr(new_op, const_op);
747 * Creates an ia32 Sub.
749 * @param env The transformation environment
750 * @return The created ia32 Sub node
752 static ir_node *gen_Sub(ia32_transform_env_t *env) {
753 ir_node *new_op = NULL;
754 dbg_info *dbg = env->dbg;
755 ir_mode *mode = env->mode;
756 ir_graph *irg = env->irg;
757 ir_node *block = env->block;
758 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
759 ir_node *nomem = new_NoMem();
760 ir_node *op1 = get_Sub_left(env->irn);
761 ir_node *op2 = get_Sub_right(env->irn);
762 ir_node *expr_op, *imm_op;
764 /* Check if immediate optimization is on and */
765 /* if it's an operation with immediate. */
766 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
767 expr_op = get_expr_op(op1, op2);
769 assert((expr_op || imm_op) && "invalid operands");
771 if (mode_is_float(mode)) {
773 if (USE_SSE2(env->cg))
774 return gen_binop(env, op1, op2, new_rd_ia32_xSub);
776 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
781 /* No expr_op means, that we have two const - one symconst and */
782 /* one tarval or another symconst - because this case is not */
783 /* covered by constant folding */
784 /* We need to check for: */
785 /* 1) symconst + const -> becomes a LEA */
786 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
787 /* linker doesn't support two symconsts */
789 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
790 /* this is the 2nd case */
791 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
792 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
793 set_ia32_am_sc_sign(new_op);
794 set_ia32_am_flavour(new_op, ia32_am_OB);
797 /* this is the 1st case */
798 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
800 if (get_ia32_op_type(op1) == ia32_SymConst) {
801 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
802 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
805 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
806 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
807 set_ia32_am_sc_sign(new_op);
809 set_ia32_am_flavour(new_op, ia32_am_O);
813 set_ia32_am_support(new_op, ia32_am_Source);
814 set_ia32_op_type(new_op, ia32_AddrModeS);
816 /* Lea doesn't need a Proj */
820 /* This is expr - const */
821 new_op = gen_imm_Sub(env, expr_op, imm_op);
824 set_ia32_am_support(new_op, ia32_am_Dest);
827 /* This is a normal sub */
828 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
831 set_ia32_am_support(new_op, ia32_am_Full);
835 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
837 set_ia32_res_mode(new_op, mode);
839 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
845 * Generates an ia32 DivMod with additional infrastructure for the
846 * register allocator if needed.
848 * @param env The transformation environment
849 * @param dividend -no comment- :)
850 * @param divisor -no comment- :)
851 * @param dm_flav flavour_Div/Mod/DivMod
852 * @return The created ia32 DivMod node
854 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
856 ir_node *edx_node, *cltd;
858 dbg_info *dbg = env->dbg;
859 ir_graph *irg = env->irg;
860 ir_node *block = env->block;
861 ir_mode *mode = env->mode;
862 ir_node *irn = env->irn;
867 mem = get_Div_mem(irn);
868 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
871 mem = get_Mod_mem(irn);
872 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
875 mem = get_DivMod_mem(irn);
876 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
882 if (mode_is_signed(mode)) {
883 /* in signed mode, we need to sign extend the dividend */
884 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
885 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
886 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
889 edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
890 set_ia32_Const_type(edx_node, ia32_Const);
891 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
894 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
896 set_ia32_n_res(res, 2);
898 /* Only one proj is used -> We must add a second proj and */
899 /* connect this one to a Keep node to eat up the second */
900 /* destroyed register. */
901 if (get_irn_n_edges(irn) == 1) {
902 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
903 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
905 if (get_irn_op(irn) == op_Div) {
906 set_Proj_proj(proj, pn_DivMod_res_div);
907 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
910 set_Proj_proj(proj, pn_DivMod_res_mod);
911 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
914 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
917 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
919 set_ia32_res_mode(res, mode_Is);
926 * Wrapper for generate_DivMod. Sets flavour_Mod.
928 * @param env The transformation environment
930 static ir_node *gen_Mod(ia32_transform_env_t *env) {
931 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
935 * Wrapper for generate_DivMod. Sets flavour_Div.
937 * @param env The transformation environment
939 static ir_node *gen_Div(ia32_transform_env_t *env) {
940 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
944 * Wrapper for generate_DivMod. Sets flavour_DivMod.
946 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
947 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
953 * Creates an ia32 floating Div.
955 * @param env The transformation environment
956 * @return The created ia32 xDiv node
958 static ir_node *gen_Quot(ia32_transform_env_t *env) {
959 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
961 ir_node *nomem = new_rd_NoMem(env->irg);
962 ir_node *op1 = get_Quot_left(env->irn);
963 ir_node *op2 = get_Quot_right(env->irn);
966 if (USE_SSE2(env->cg)) {
967 if (is_ia32_xConst(op2)) {
968 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
969 set_ia32_am_support(new_op, ia32_am_None);
970 set_ia32_Immop_attr(new_op, op2);
973 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
974 set_ia32_am_support(new_op, ia32_am_Source);
978 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
979 set_ia32_am_support(new_op, ia32_am_Source);
981 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
982 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
990 * Creates an ia32 Shl.
992 * @param env The transformation environment
993 * @return The created ia32 Shl node
995 static ir_node *gen_Shl(ia32_transform_env_t *env) {
996 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
1002 * Creates an ia32 Shr.
1004 * @param env The transformation environment
1005 * @return The created ia32 Shr node
1007 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1008 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1014 * Creates an ia32 Shrs.
1016 * @param env The transformation environment
1017 * @return The created ia32 Shrs node
1019 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1020 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1026 * Creates an ia32 RotL.
1028 * @param env The transformation environment
1029 * @param op1 The first operator
1030 * @param op2 The second operator
1031 * @return The created ia32 RotL node
1033 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1034 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1040 * Creates an ia32 RotR.
1041 * NOTE: There is no RotR with immediate because this would always be a RotL
1042 * "imm-mode_size_bits" which can be pre-calculated.
1044 * @param env The transformation environment
1045 * @param op1 The first operator
1046 * @param op2 The second operator
1047 * @return The created ia32 RotR node
1049 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1050 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1056 * Creates an ia32 RotR or RotL (depending on the found pattern).
1058 * @param env The transformation environment
1059 * @return The created ia32 RotL or RotR node
1061 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1062 ir_node *rotate = NULL;
1063 ir_node *op1 = get_Rot_left(env->irn);
1064 ir_node *op2 = get_Rot_right(env->irn);
1066 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1067 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1068 that means we can create a RotR instead of an Add and a RotL */
1071 ir_node *pred = get_Proj_pred(op2);
1073 if (is_ia32_Add(pred)) {
1074 ir_node *pred_pred = get_irn_n(pred, 2);
1075 tarval *tv = get_ia32_Immop_tarval(pred);
1076 long bits = get_mode_size_bits(env->mode);
1078 if (is_Proj(pred_pred)) {
1079 pred_pred = get_Proj_pred(pred_pred);
1082 if (is_ia32_Minus(pred_pred) &&
1083 tarval_is_long(tv) &&
1084 get_tarval_long(tv) == bits)
1086 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1087 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1094 rotate = gen_RotL(env, op1, op2);
1103 * Transforms a Minus node.
1105 * @param env The transformation environment
1106 * @param op The Minus operand
1107 * @return The created ia32 Minus node
1109 static ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1114 if (mode_is_float(env->mode)) {
1116 if (USE_SSE2(env->cg)) {
1117 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1118 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1119 ir_node *nomem = new_rd_NoMem(env->irg);
1121 new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1123 size = get_mode_size_bits(env->mode);
1124 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1126 set_ia32_sc(new_op, name);
1128 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1130 set_ia32_res_mode(new_op, env->mode);
1131 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1133 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
1136 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1137 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1141 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1148 * Transforms a Minus node.
1150 * @param env The transformation environment
1151 * @return The created ia32 Minus node
1153 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1154 return gen_Minus_ex(env, get_Minus_op(env->irn));
1159 * Transforms a Not node.
1161 * @param env The transformation environment
1162 * @return The created ia32 Not node
1164 static ir_node *gen_Not(ia32_transform_env_t *env) {
1165 assert (! mode_is_float(env->mode));
1166 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1172 * Transforms an Abs node.
1174 * @param env The transformation environment
1175 * @return The created ia32 Abs node
1177 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1178 ir_node *res, *p_eax, *p_edx;
1179 dbg_info *dbg = env->dbg;
1180 ir_mode *mode = env->mode;
1181 ir_graph *irg = env->irg;
1182 ir_node *block = env->block;
1183 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1184 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1185 ir_node *nomem = new_NoMem();
1186 ir_node *op = get_Abs_op(env->irn);
1190 if (mode_is_float(mode)) {
1192 if (USE_SSE2(env->cg)) {
1193 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1195 size = get_mode_size_bits(mode);
1196 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1198 set_ia32_sc(res, name);
1200 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1202 set_ia32_res_mode(res, mode);
1203 set_ia32_immop_type(res, ia32_ImmSymConst);
1205 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
1208 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1209 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1213 res = new_rd_ia32_Cdq(dbg, irg, block, op);
1214 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1215 set_ia32_res_mode(res, mode);
1217 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
1218 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
1220 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1221 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1222 set_ia32_res_mode(res, mode);
1224 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
1226 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1227 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1228 set_ia32_res_mode(res, mode);
1230 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
1239 * Transforms a Load.
1241 * @param env The transformation environment
1242 * @return the created ia32 Load node
1244 static ir_node *gen_Load(ia32_transform_env_t *env) {
1245 ir_node *node = env->irn;
1246 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1247 ir_node *ptr = get_Load_ptr(node);
1248 ir_node *lptr = ptr;
1249 ir_mode *mode = get_Load_mode(node);
1252 ia32_am_flavour_t am_flav = ia32_B;
1254 /* address might be a constant (symconst or absolute address) */
1255 if (is_ia32_Const(ptr)) {
1260 if (mode_is_float(mode)) {
1262 if (USE_SSE2(env->cg))
1263 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1265 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1268 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1271 /* base is an constant address */
1273 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1274 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1277 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1283 set_ia32_am_support(new_op, ia32_am_Source);
1284 set_ia32_op_type(new_op, ia32_AddrModeS);
1285 set_ia32_am_flavour(new_op, am_flav);
1286 set_ia32_ls_mode(new_op, mode);
1288 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1296 * Transforms a Store.
1298 * @param env The transformation environment
1299 * @return the created ia32 Store node
1301 static ir_node *gen_Store(ia32_transform_env_t *env) {
1302 ir_node *node = env->irn;
1303 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1304 ir_node *val = get_Store_value(node);
1305 ir_node *ptr = get_Store_ptr(node);
1306 ir_node *sptr = ptr;
1307 ir_node *mem = get_Store_mem(node);
1308 ir_mode *mode = get_irn_mode(val);
1309 ir_node *sval = val;
1312 ia32_am_flavour_t am_flav = ia32_B;
1313 ia32_immop_type_t immop = ia32_ImmNone;
1315 if (! mode_is_float(mode)) {
1316 /* in case of storing a const (but not a symconst) -> make it an attribute */
1317 if (is_ia32_Cnst(val)) {
1318 switch (get_ia32_op_type(val)) {
1320 immop = ia32_ImmConst;
1323 immop = ia32_ImmSymConst;
1326 assert(0 && "unsupported Const type");
1332 /* address might be a constant (symconst or absolute address) */
1333 if (is_ia32_Const(ptr)) {
1338 if (mode_is_float(mode)) {
1340 if (USE_SSE2(env->cg))
1341 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1343 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1345 else if (get_mode_size_bits(mode) == 8) {
1346 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1349 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1352 /* stored const is an attribute (saves a register) */
1353 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1354 set_ia32_Immop_attr(new_op, val);
1357 /* base is an constant address */
1359 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1360 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1363 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1369 set_ia32_am_support(new_op, ia32_am_Dest);
1370 set_ia32_op_type(new_op, ia32_AddrModeD);
1371 set_ia32_am_flavour(new_op, am_flav);
1372 set_ia32_ls_mode(new_op, get_irn_mode(val));
1373 set_ia32_immop_type(new_op, immop);
1375 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1383 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1385 * @param env The transformation environment
1386 * @return The transformed node.
1388 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1389 dbg_info *dbg = env->dbg;
1390 ir_graph *irg = env->irg;
1391 ir_node *block = env->block;
1392 ir_node *node = env->irn;
1393 ir_node *sel = get_Cond_selector(node);
1394 ir_mode *sel_mode = get_irn_mode(sel);
1395 ir_node *res = NULL;
1396 ir_node *pred = NULL;
1397 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1398 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1400 if (is_Proj(sel) && sel_mode == mode_b) {
1401 ir_node *nomem = new_NoMem();
1403 pred = get_Proj_pred(sel);
1405 /* get both compare operators */
1406 cmp_a = get_Cmp_left(pred);
1407 cmp_b = get_Cmp_right(pred);
1409 /* check if we can use a CondJmp with immediate */
1410 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1411 expr = get_expr_op(cmp_a, cmp_b);
1414 pn_Cmp pnc = get_Proj_proj(sel);
1416 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1417 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1418 /* a Cmp A =/!= 0 */
1419 ir_node *op1 = expr;
1420 ir_node *op2 = expr;
1421 ir_node *and = skip_Proj(expr);
1422 const char *cnst = NULL;
1424 /* check, if expr is an only once used And operation */
1425 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1426 op1 = get_irn_n(and, 2);
1427 op2 = get_irn_n(and, 3);
1429 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1431 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1432 set_ia32_pncode(res, get_Proj_proj(sel));
1433 set_ia32_res_mode(res, get_irn_mode(op1));
1436 copy_ia32_Immop_attr(res, and);
1439 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1444 if (mode_is_float(get_irn_mode(expr))) {
1446 if (USE_SSE2(env->cg))
1447 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1453 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1455 set_ia32_Immop_attr(res, cnst);
1456 set_ia32_res_mode(res, get_irn_mode(expr));
1459 if (mode_is_float(get_irn_mode(cmp_a))) {
1461 if (USE_SSE2(env->cg))
1462 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1465 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1466 proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
1467 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1471 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1472 set_ia32_commutative(res);
1474 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1477 set_ia32_pncode(res, get_Proj_proj(sel));
1478 //set_ia32_am_support(res, ia32_am_Source);
1481 /* determine the smallest switch case value */
1482 int switch_min = INT_MAX;
1483 const ir_edge_t *edge;
1486 foreach_out_edge(node, edge) {
1487 int pn = get_Proj_proj(get_edge_src_irn(edge));
1488 switch_min = pn < switch_min ? pn : switch_min;
1492 /* if smallest switch case is not 0 we need an additional sub */
1493 snprintf(buf, sizeof(buf), "%d", switch_min);
1494 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1495 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1496 sub_ia32_am_offs(res, buf);
1497 set_ia32_am_flavour(res, ia32_am_OB);
1498 set_ia32_am_support(res, ia32_am_Source);
1499 set_ia32_op_type(res, ia32_AddrModeS);
1502 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1503 set_ia32_pncode(res, get_Cond_defaultProj(node));
1504 set_ia32_res_mode(res, get_irn_mode(sel));
1507 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1514 * Transforms a CopyB node.
1516 * @param env The transformation environment
1517 * @return The transformed node.
1519 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1520 ir_node *res = NULL;
1521 dbg_info *dbg = env->dbg;
1522 ir_graph *irg = env->irg;
1523 ir_mode *mode = env->mode;
1524 ir_node *block = env->block;
1525 ir_node *node = env->irn;
1526 ir_node *src = get_CopyB_src(node);
1527 ir_node *dst = get_CopyB_dst(node);
1528 ir_node *mem = get_CopyB_mem(node);
1529 int size = get_type_size_bytes(get_CopyB_type(node));
1532 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1533 /* then we need the size explicitly in ECX. */
1534 if (size >= 16 * 4) {
1535 rem = size & 0x3; /* size % 4 */
1538 res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
1539 set_ia32_op_type(res, ia32_Const);
1540 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1542 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1543 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1546 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1547 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1548 set_ia32_immop_type(res, ia32_ImmConst);
1551 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1559 * Transforms a Mux node into CMov.
1561 * @param env The transformation environment
1562 * @return The transformed node.
1564 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1565 ir_node *node = env->irn;
1566 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1567 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1569 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1576 * Following conversion rules apply:
1580 * 1) n bit -> m bit n > m (downscale)
1581 * a) target is signed: movsx
1582 * b) target is unsigned: and with lower bits sets
1583 * 2) n bit -> m bit n == m (sign change)
1585 * 3) n bit -> m bit n < m (upscale)
1586 * a) source is signed: movsx
1587 * b) source is unsigned: and with lower bits sets
1591 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1595 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1596 * if target mode < 32bit: additional INT -> INT conversion (see above)
1600 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1601 * x87 is mode_E internally, conversions happen only at load and store
1602 * in non-strict semantic
1606 * Create a conversion from x87 state register to general purpose.
1608 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1609 ia32_code_gen_t *cg = env->cg;
1610 entity *ent = cg->fp_to_gp;
1611 ir_graph *irg = env->irg;
1612 ir_node *block = env->block;
1613 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1614 ir_node *op = get_Conv_op(env->irn);
1615 ir_node *fist, *mem, *load;
1618 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1619 ent = cg->fp_to_gp =
1620 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1624 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
1626 set_ia32_frame_ent(fist, ent);
1627 set_ia32_use_frame(fist);
1628 set_ia32_am_support(fist, ia32_am_Dest);
1629 set_ia32_op_type(fist, ia32_AddrModeD);
1630 set_ia32_am_flavour(fist, ia32_B);
1631 set_ia32_ls_mode(fist, mode_E);
1633 mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
1636 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1638 set_ia32_frame_ent(load, ent);
1639 set_ia32_use_frame(load);
1640 set_ia32_am_support(load, ia32_am_Source);
1641 set_ia32_op_type(load, ia32_AddrModeS);
1642 set_ia32_am_flavour(load, ia32_B);
1643 set_ia32_ls_mode(load, tgt_mode);
1645 return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
1649 * Create a conversion from x87 state register to general purpose.
1651 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1652 ia32_code_gen_t *cg = env->cg;
1653 entity *ent = cg->gp_to_fp;
1654 ir_graph *irg = env->irg;
1655 ir_node *block = env->block;
1656 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1657 ir_node *nomem = get_irg_no_mem(irg);
1658 ir_node *op = get_Conv_op(env->irn);
1659 ir_node *fild, *store, *mem;
1663 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
1664 ent = cg->gp_to_fp =
1665 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
1668 /* first convert to 32 bit */
1669 src_bits = get_mode_size_bits(src_mode);
1670 if (src_bits == 8) {
1671 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
1672 op = new_r_Proj(irg, block, op, mode_Is, 0);
1674 else if (src_bits < 32) {
1675 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
1676 op = new_r_Proj(irg, block, op, mode_Is, 0);
1680 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
1682 set_ia32_frame_ent(store, ent);
1683 set_ia32_use_frame(store);
1685 set_ia32_am_support(store, ia32_am_Dest);
1686 set_ia32_op_type(store, ia32_AddrModeD);
1687 set_ia32_am_flavour(store, ia32_B);
1688 set_ia32_ls_mode(store, mode_Is);
1690 mem = new_r_Proj(irg, block, store, mode_M, 0);
1693 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1695 set_ia32_frame_ent(fild, ent);
1696 set_ia32_use_frame(fild);
1697 set_ia32_am_support(fild, ia32_am_Source);
1698 set_ia32_op_type(fild, ia32_AddrModeS);
1699 set_ia32_am_flavour(fild, ia32_B);
1700 set_ia32_ls_mode(fild, mode_E);
1702 return new_r_Proj(irg, block, fild, mode_E, 0);
1706 * Transforms a Conv node.
1708 * @param env The transformation environment
1709 * @return The created ia32 Conv node
1711 static ir_node *gen_Conv(ia32_transform_env_t *env) {
1712 dbg_info *dbg = env->dbg;
1713 ir_graph *irg = env->irg;
1714 ir_node *op = get_Conv_op(env->irn);
1715 ir_mode *src_mode = get_irn_mode(op);
1716 ir_mode *tgt_mode = env->mode;
1717 int src_bits = get_mode_size_bits(src_mode);
1718 int tgt_bits = get_mode_size_bits(tgt_mode);
1719 ir_node *block = env->block;
1720 ir_node *new_op = NULL;
1721 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1722 ir_node *nomem = new_rd_NoMem(irg);
1724 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1726 if (src_mode == tgt_mode) {
1727 /* this can happen when changing mode_P to mode_Is */
1728 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1729 edges_reroute(env->irn, op, irg);
1731 else if (mode_is_float(src_mode)) {
1732 /* we convert from float ... */
1733 if (mode_is_float(tgt_mode)) {
1735 if (USE_SSE2(env->cg)) {
1736 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1737 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
1740 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
1741 edges_reroute(env->irn, op, irg);
1746 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1747 if (USE_SSE2(env->cg))
1748 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
1750 return gen_x87_fp_to_gp(env, tgt_mode);
1752 /* if target mode is not int: add an additional downscale convert */
1753 if (tgt_bits < 32) {
1754 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1755 set_ia32_am_support(new_op, ia32_am_Source);
1756 set_ia32_tgt_mode(new_op, tgt_mode);
1757 set_ia32_src_mode(new_op, src_mode);
1759 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
1761 if (tgt_bits == 8 || src_bits == 8) {
1762 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
1765 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
1771 /* we convert from int ... */
1772 if (mode_is_float(tgt_mode)) {
1775 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1776 if (USE_SSE2(env->cg))
1777 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
1779 return gen_x87_gp_to_fp(env, src_mode);
1783 if (get_mode_size_bits(src_mode) == tgt_bits) {
1784 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
1785 edges_reroute(env->irn, op, irg);
1788 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
1789 if (tgt_bits == 8 || src_bits == 8) {
1790 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
1793 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
1800 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1801 set_ia32_tgt_mode(new_op, tgt_mode);
1802 set_ia32_src_mode(new_op, src_mode);
1804 set_ia32_am_support(new_op, ia32_am_Source);
1806 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
1814 /********************************************
1817 * | |__ ___ _ __ ___ __| | ___ ___
1818 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1819 * | |_) | __/ | | | (_) | (_| | __/\__ \
1820 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1822 ********************************************/
1824 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
1825 ir_node *new_op = NULL;
1826 ir_node *node = env->irn;
1827 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1828 ir_node *mem = new_rd_NoMem(env->irg);
1829 ir_node *ptr = get_irn_n(node, 0);
1830 entity *ent = be_get_frame_entity(node);
1831 ir_mode *mode = env->mode;
1833 // /* If the StackParam has only one user -> */
1834 // /* put it in the Block where the user resides */
1835 // if (get_irn_n_edges(node) == 1) {
1836 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
1839 if (mode_is_float(mode)) {
1841 if (USE_SSE2(env->cg))
1842 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
1844 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
1847 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
1850 set_ia32_frame_ent(new_op, ent);
1851 set_ia32_use_frame(new_op);
1853 set_ia32_am_support(new_op, ia32_am_Source);
1854 set_ia32_op_type(new_op, ia32_AddrModeS);
1855 set_ia32_am_flavour(new_op, ia32_B);
1856 set_ia32_ls_mode(new_op, mode);
1858 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1860 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
1864 * Transforms a FrameAddr into an ia32 Add.
1866 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
1867 ir_node *new_op = NULL;
1868 ir_node *node = env->irn;
1869 ir_node *op = get_irn_n(node, 0);
1870 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1871 ir_node *nomem = new_rd_NoMem(env->irg);
1873 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
1874 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1875 set_ia32_am_support(new_op, ia32_am_Full);
1876 set_ia32_use_frame(new_op);
1877 set_ia32_immop_type(new_op, ia32_ImmConst);
1878 set_ia32_commutative(new_op);
1880 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1882 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
1886 * Transforms a FrameLoad into an ia32 Load.
1888 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
1889 ir_node *new_op = NULL;
1890 ir_node *node = env->irn;
1891 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1892 ir_node *mem = get_irn_n(node, 0);
1893 ir_node *ptr = get_irn_n(node, 1);
1894 entity *ent = be_get_frame_entity(node);
1895 ir_mode *mode = get_type_mode(get_entity_type(ent));
1897 if (mode_is_float(mode)) {
1899 if (USE_SSE2(env->cg))
1900 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
1902 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
1905 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
1907 set_ia32_frame_ent(new_op, ent);
1908 set_ia32_use_frame(new_op);
1910 set_ia32_am_support(new_op, ia32_am_Source);
1911 set_ia32_op_type(new_op, ia32_AddrModeS);
1912 set_ia32_am_flavour(new_op, ia32_B);
1913 set_ia32_ls_mode(new_op, mode);
1915 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1922 * Transforms a FrameStore into an ia32 Store.
1924 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
1925 ir_node *new_op = NULL;
1926 ir_node *node = env->irn;
1927 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1928 ir_node *mem = get_irn_n(node, 0);
1929 ir_node *ptr = get_irn_n(node, 1);
1930 ir_node *val = get_irn_n(node, 2);
1931 entity *ent = be_get_frame_entity(node);
1932 ir_mode *mode = get_irn_mode(val);
1934 if (mode_is_float(mode)) {
1936 if (USE_SSE2(env->cg))
1937 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
1939 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
1941 else if (get_mode_size_bits(mode) == 8) {
1942 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
1945 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
1948 set_ia32_frame_ent(new_op, ent);
1949 set_ia32_use_frame(new_op);
1951 set_ia32_am_support(new_op, ia32_am_Dest);
1952 set_ia32_op_type(new_op, ia32_AddrModeD);
1953 set_ia32_am_flavour(new_op, ia32_B);
1954 set_ia32_ls_mode(new_op, mode);
1956 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1962 * This function just sets the register for the Unknown node
1963 * as this is not done during register allocation because Unknown
1964 * is an "ignore" node.
1966 static ir_node *gen_Unknown(ia32_transform_env_t *env) {
1967 ir_mode *mode = env->mode;
1968 ir_node *irn = env->irn;
1970 if (mode_is_float(mode)) {
1971 if (USE_SSE2(env->cg))
1972 arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
1974 arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
1976 else if (mode_is_int(mode) || mode_is_reference(mode)) {
1977 arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
1980 assert(0 && "unsupported Unknown-Mode");
1987 /*********************************************************
1990 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1991 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1992 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1993 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1995 *********************************************************/
1998 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
1999 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2001 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
2002 ia32_transform_env_t tenv;
2003 ir_node *in1, *in2, *noreg, *nomem, *res;
2004 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
2006 /* Return if AM node or not a Sub or xSub */
2007 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_xSub(irn)))
2010 noreg = ia32_new_NoReg_gp(cg);
2011 nomem = new_rd_NoMem(cg->irg);
2012 in1 = get_irn_n(irn, 2);
2013 in2 = get_irn_n(irn, 3);
2014 in1_reg = arch_get_irn_register(cg->arch_env, in1);
2015 in2_reg = arch_get_irn_register(cg->arch_env, in2);
2016 out_reg = get_ia32_out_reg(irn, 0);
2018 tenv.block = get_nodes_block(irn);
2019 tenv.dbg = get_irn_dbg_info(irn);
2022 tenv.mode = get_ia32_res_mode(irn);
2024 DEBUG_ONLY(tenv.mod = cg->mod;)
2026 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
2027 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
2028 /* generate the neg src2 */
2029 res = gen_Minus_ex(&tenv, in2);
2030 arch_set_irn_register(cg->arch_env, res, in2_reg);
2032 /* add to schedule */
2033 sched_add_before(irn, res);
2035 /* generate the add */
2036 if (mode_is_float(tenv.mode)) {
2037 res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2038 set_ia32_am_support(res, ia32_am_Source);
2041 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2042 set_ia32_am_support(res, ia32_am_Full);
2043 set_ia32_commutative(res);
2045 set_ia32_res_mode(res, tenv.mode);
2047 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
2049 slots = get_ia32_slots(res);
2052 /* add to schedule */
2053 sched_add_before(irn, res);
2055 /* remove the old sub */
2058 DBG_OPT_SUB2NEGADD(irn, res);
2060 /* exchange the add and the sub */
2066 * Transforms a LEA into an Add if possible
2067 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2069 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
2070 ia32_am_flavour_t am_flav;
2072 ir_node *res = NULL;
2073 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
2075 ia32_transform_env_t tenv;
2076 const arch_register_t *out_reg, *base_reg, *index_reg;
2079 if (! is_ia32_Lea(irn))
2082 am_flav = get_ia32_am_flavour(irn);
2084 /* only some LEAs can be transformed to an Add */
2085 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
2088 noreg = ia32_new_NoReg_gp(cg);
2089 nomem = new_rd_NoMem(cg->irg);
2092 base = get_irn_n(irn, 0);
2093 index = get_irn_n(irn,1);
2095 offs = get_ia32_am_offs(irn);
2097 /* offset has a explicit sign -> we need to skip + */
2098 if (offs && offs[0] == '+')
2101 out_reg = arch_get_irn_register(cg->arch_env, irn);
2102 base_reg = arch_get_irn_register(cg->arch_env, base);
2103 index_reg = arch_get_irn_register(cg->arch_env, index);
2105 tenv.block = get_nodes_block(irn);
2106 tenv.dbg = get_irn_dbg_info(irn);
2109 DEBUG_ONLY(tenv.mod = cg->mod;)
2110 tenv.mode = get_irn_mode(irn);
2113 switch(get_ia32_am_flavour(irn)) {
2115 /* out register must be same as base register */
2116 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2122 /* out register must be same as base register */
2123 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2130 /* out register must be same as index register */
2131 if (! REGS_ARE_EQUAL(out_reg, index_reg))
2138 /* out register must be same as one in register */
2139 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
2143 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
2148 /* in registers a different from out -> no Add possible */
2155 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
2156 arch_set_irn_register(cg->arch_env, res, out_reg);
2157 set_ia32_op_type(res, ia32_Normal);
2158 set_ia32_commutative(res);
2159 set_ia32_res_mode(res, tenv.mode);
2162 set_ia32_cnst(res, offs);
2163 set_ia32_immop_type(res, ia32_ImmConst);
2166 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
2168 /* add Add to schedule */
2169 sched_add_before(irn, res);
2171 DBG_OPT_LEA2ADD(irn, res);
2173 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, 0);
2175 /* add result Proj to schedule */
2176 sched_add_before(irn, res);
2178 /* remove the old LEA */
2181 /* exchange the Add and the LEA */
2186 * the BAD transformer.
2188 static ir_node *bad_transform(ia32_transform_env_t *env) {
2189 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2195 * Enters all transform functions into the generic pointer
2197 void ia32_register_transformers(void) {
2198 ir_op *op_Max, *op_Min, *op_Mulh;
2200 /* first clear the generic function pointer for all ops */
2201 clear_irp_opcodes_generic_func();
2203 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2204 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
2250 /* constant transformation happens earlier */
2274 /* set the register for all Unknown nodes */
2277 op_Max = get_op_Max();
2280 op_Min = get_op_Min();
2283 op_Mulh = get_op_Mulh();
2292 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
2295 * Transforms the given firm node (and maybe some other related nodes)
2296 * into one or more assembler nodes.
2298 * @param node the firm node
2299 * @param env the debug module
2301 void ia32_transform_node(ir_node *node, void *env) {
2302 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2303 ir_op *op = get_irn_op(node);
2304 ir_node *asm_node = NULL;
2309 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
2310 if (op->ops.generic) {
2311 ia32_transform_env_t tenv;
2312 transform_func *transform = (transform_func *)op->ops.generic;
2314 tenv.block = get_nodes_block(node);
2315 tenv.dbg = get_irn_dbg_info(node);
2316 tenv.irg = current_ir_graph;
2318 tenv.mode = get_irn_mode(node);
2320 DEBUG_ONLY(tenv.mod = cg->mod;)
2322 asm_node = (*transform)(&tenv);
2325 /* exchange nodes if a new one was generated */
2327 exchange(node, asm_node);
2328 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2331 DB((cg->mod, LEVEL_1, "ignored\n"));