2 * This file implements the IR transformation from firm into
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
26 #include "../benode_t.h"
27 #include "../besched.h"
29 #include "bearch_ia32_t.h"
31 #include "ia32_nodes_attr.h"
32 #include "../arch/archop.h" /* we need this for Min and Max nodes */
33 #include "ia32_transform.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
37 #include "gen_ia32_regalloc_if.h"
40 #define SET_IA32_ORIG_NODE(n, o)
42 #define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
46 #define SFP_SIGN "0x80000000"
47 #define DFP_SIGN "0x8000000000000000"
48 #define SFP_ABS "0x7FFFFFFF"
49 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
51 #define TP_SFP_SIGN "ia32_sfp_sign"
52 #define TP_DFP_SIGN "ia32_dfp_sign"
53 #define TP_SFP_ABS "ia32_sfp_abs"
54 #define TP_DFP_ABS "ia32_dfp_abs"
56 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
57 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
58 #define ENT_SFP_ABS "IA32_SFP_ABS"
59 #define ENT_DFP_ABS "IA32_DFP_ABS"
61 extern ir_op *get_op_Mulh(void);
63 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
64 ir_node *op1, ir_node *op2, ir_node *mem, ir_mode *mode);
66 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
67 ir_node *op, ir_node *mem, ir_mode *mode);
70 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
73 /****************************************************************************************************
75 * | | | | / _| | | (_)
76 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
77 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
78 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
79 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
81 ****************************************************************************************************/
84 * Gets the Proj with number pn from irn.
86 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
87 const ir_edge_t *edge;
89 assert(get_irn_mode(irn) == mode_T && "need mode_T");
91 foreach_out_edge(irn, edge) {
92 proj = get_edge_src_irn(edge);
94 if (get_Proj_proj(proj) == pn)
101 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
102 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
103 static const struct {
105 const char *ent_name;
106 const char *cnst_str;
107 } names [ia32_known_const_max] = {
108 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
109 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
110 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
111 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
113 static struct entity *ent_cache[ia32_known_const_max];
115 const char *tp_name, *ent_name, *cnst_str;
122 ent_name = names[kct].ent_name;
123 if (! ent_cache[kct]) {
124 tp_name = names[kct].tp_name;
125 cnst_str = names[kct].cnst_str;
127 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
128 tp = new_type_primitive(new_id_from_str(tp_name), mode);
129 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
131 set_entity_ld_ident(ent, get_entity_ident(ent));
132 set_entity_visibility(ent, visibility_local);
133 set_entity_variability(ent, variability_constant);
134 set_entity_allocation(ent, allocation_static);
136 /* we create a new entity here: It's initialization must resist on the
138 rem = current_ir_graph;
139 current_ir_graph = get_const_code_irg();
140 cnst = new_Const(mode, tv);
141 current_ir_graph = rem;
143 set_atomic_ent_value(ent, cnst);
145 /* cache the entry */
146 ent_cache[kct] = ent;
149 return get_entity_ident(ent_cache[kct]);
154 * Prints the old node name on cg obst and returns a pointer to it.
156 const char *get_old_node_name(ia32_transform_env_t *env) {
157 ia32_isa_t *isa = (ia32_isa_t *)env->cg->arch_env->isa;
159 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", env->irn);
160 obstack_1grow(isa->name_obst, 0);
161 isa->name_obst_size += obstack_object_size(isa->name_obst);
162 return obstack_finish(isa->name_obst);
166 /* determine if one operator is an Imm */
167 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
169 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
170 else return is_ia32_Cnst(op2) ? op2 : NULL;
173 /* determine if one operator is not an Imm */
174 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
175 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
180 * Construct a standard binary operation, set AM and immediate if required.
182 * @param env The transformation environment
183 * @param op1 The first operand
184 * @param op2 The second operand
185 * @param func The node constructor function
186 * @return The constructed ia32 node.
188 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
189 ir_node *new_op = NULL;
190 ir_mode *mode = env->mode;
191 dbg_info *dbg = env->dbg;
192 ir_graph *irg = env->irg;
193 ir_node *block = env->block;
194 firm_dbg_module_t *mod = env->mod;
195 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
196 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
197 ir_node *nomem = new_NoMem();
198 ir_node *expr_op, *imm_op;
200 /* Check if immediate optimization is on and */
201 /* if it's an operation with immediate. */
202 if (! env->cg->opt.immops) {
206 else if (is_op_commutative(get_irn_op(env->irn))) {
207 imm_op = get_immediate_op(op1, op2);
208 expr_op = get_expr_op(op1, op2);
211 imm_op = get_immediate_op(NULL, op2);
212 expr_op = get_expr_op(op1, op2);
215 assert((expr_op || imm_op) && "invalid operands");
218 /* We have two consts here: not yet supported */
222 if (mode_is_float(mode)) {
223 /* floating point operations */
225 DB((mod, LEVEL_1, "FP with immediate ..."));
226 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem, mode_T);
227 set_ia32_Immop_attr(new_op, imm_op);
228 set_ia32_am_support(new_op, ia32_am_None);
231 DB((mod, LEVEL_1, "FP binop ..."));
232 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
233 set_ia32_am_support(new_op, ia32_am_Source);
237 /* integer operations */
239 /* This is expr + const */
240 DB((mod, LEVEL_1, "INT with immediate ..."));
241 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem, mode_T);
242 set_ia32_Immop_attr(new_op, imm_op);
245 set_ia32_am_support(new_op, ia32_am_Dest);
248 DB((mod, LEVEL_1, "INT binop ..."));
249 /* This is a normal operation */
250 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
253 set_ia32_am_support(new_op, ia32_am_Full);
257 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
259 set_ia32_res_mode(new_op, mode);
261 if (is_op_commutative(get_irn_op(env->irn))) {
262 set_ia32_commutative(new_op);
265 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
271 * Construct a shift/rotate binary operation, sets AM and immediate if required.
273 * @param env The transformation environment
274 * @param op1 The first operand
275 * @param op2 The second operand
276 * @param func The node constructor function
277 * @return The constructed ia32 node.
279 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
280 ir_node *new_op = NULL;
281 ir_mode *mode = env->mode;
282 dbg_info *dbg = env->dbg;
283 ir_graph *irg = env->irg;
284 ir_node *block = env->block;
285 firm_dbg_module_t *mod = env->mod;
286 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
287 ir_node *nomem = new_NoMem();
288 ir_node *expr_op, *imm_op;
291 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
293 /* Check if immediate optimization is on and */
294 /* if it's an operation with immediate. */
295 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
296 expr_op = get_expr_op(op1, op2);
298 assert((expr_op || imm_op) && "invalid operands");
301 /* We have two consts here: not yet supported */
305 /* Limit imm_op within range imm8 */
307 tv = get_ia32_Immop_tarval(imm_op);
310 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
317 /* integer operations */
319 /* This is shift/rot with const */
320 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
322 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
323 set_ia32_Immop_attr(new_op, imm_op);
326 /* This is a normal shift/rot */
327 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
328 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
332 set_ia32_am_support(new_op, ia32_am_Dest);
334 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
336 set_ia32_res_mode(new_op, mode);
338 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
343 * Construct a standard unary operation, set AM and immediate if required.
345 * @param env The transformation environment
346 * @param op The operand
347 * @param func The node constructor function
348 * @return The constructed ia32 node.
350 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
351 ir_node *new_op = NULL;
352 ir_mode *mode = env->mode;
353 dbg_info *dbg = env->dbg;
354 firm_dbg_module_t *mod = env->mod;
355 ir_graph *irg = env->irg;
356 ir_node *block = env->block;
357 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
358 ir_node *nomem = new_NoMem();
360 new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
362 if (mode_is_float(mode)) {
363 DB((mod, LEVEL_1, "FP unop ..."));
364 /* floating point operations don't support implicit store */
365 set_ia32_am_support(new_op, ia32_am_None);
368 DB((mod, LEVEL_1, "INT unop ..."));
369 set_ia32_am_support(new_op, ia32_am_Dest);
372 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
374 set_ia32_res_mode(new_op, mode);
376 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
382 * Creates an ia32 Add with immediate.
384 * @param env The transformation environment
385 * @param expr_op The expression operator
386 * @param const_op The constant
387 * @return the created ia32 Add node
389 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
390 ir_node *new_op = NULL;
391 tarval *tv = get_ia32_Immop_tarval(const_op);
392 firm_dbg_module_t *mod = env->mod;
393 dbg_info *dbg = env->dbg;
394 ir_graph *irg = env->irg;
395 ir_node *block = env->block;
396 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
397 ir_node *nomem = new_NoMem();
399 tarval_classification_t class_tv, class_negtv;
401 /* try to optimize to inc/dec */
402 if (env->cg->opt.incdec && tv) {
403 /* optimize tarvals */
404 class_tv = classify_tarval(tv);
405 class_negtv = classify_tarval(tarval_neg(tv));
407 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
408 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
409 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
412 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
413 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
414 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
420 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
421 set_ia32_Immop_attr(new_op, const_op);
428 * Creates an ia32 Add.
430 * @param dbg firm node dbg
431 * @param block the block the new node should belong to
432 * @param op1 first operator
433 * @param op2 second operator
434 * @param mode node mode
435 * @return the created ia32 Add node
437 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
438 ir_node *new_op = NULL;
439 dbg_info *dbg = env->dbg;
440 ir_mode *mode = env->mode;
441 ir_graph *irg = env->irg;
442 ir_node *block = env->block;
443 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
444 ir_node *nomem = new_NoMem();
445 ir_node *expr_op, *imm_op;
447 /* Check if immediate optimization is on and */
448 /* if it's an operation with immediate. */
449 imm_op = env->cg->opt.immops ? get_immediate_op(op1, op2) : NULL;
450 expr_op = get_expr_op(op1, op2);
452 assert((expr_op || imm_op) && "invalid operands");
454 if (mode_is_float(mode)) {
455 return gen_binop(env, op1, op2, new_rd_ia32_fAdd);
460 /* No expr_op means, that we have two const - one symconst and */
461 /* one tarval or another symconst - because this case is not */
462 /* covered by constant folding */
464 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
465 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
466 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
469 set_ia32_am_support(new_op, ia32_am_Source);
470 set_ia32_op_type(new_op, ia32_AddrModeS);
471 set_ia32_am_flavour(new_op, ia32_am_O);
473 /* Lea doesn't need a Proj */
477 /* This is expr + const */
478 new_op = gen_imm_Add(env, expr_op, imm_op);
481 set_ia32_am_support(new_op, ia32_am_Dest);
484 /* This is a normal add */
485 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
488 set_ia32_am_support(new_op, ia32_am_Full);
492 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
494 set_ia32_res_mode(new_op, mode);
496 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
502 * Creates an ia32 Mul.
504 * @param dbg firm node dbg
505 * @param block the block the new node should belong to
506 * @param op1 first operator
507 * @param op2 second operator
508 * @param mode node mode
509 * @return the created ia32 Mul node
511 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
514 if (mode_is_float(env->mode)) {
515 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul);
518 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
527 * Creates an ia32 Mulh.
528 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
529 * this result while Mul returns the lower 32 bit.
531 * @param env The transformation environment
532 * @param op1 The first operator
533 * @param op2 The second operator
534 * @return the created ia32 Mulh node
536 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
537 ir_node *proj_EAX, *proj_EDX, *mulh;
540 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
541 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
542 mulh = get_Proj_pred(proj_EAX);
543 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
545 /* to be on the save side */
546 set_Proj_proj(proj_EAX, pn_EAX);
548 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
549 /* Mulh with const cannot have AM */
550 set_ia32_am_support(mulh, ia32_am_None);
553 /* Mulh cannot have AM for destination */
554 set_ia32_am_support(mulh, ia32_am_Source);
560 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
568 * Creates an ia32 And.
570 * @param env The transformation environment
571 * @param op1 The first operator
572 * @param op2 The second operator
573 * @return The created ia32 And node
575 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
576 if (mode_is_float(env->mode)) {
577 return gen_binop(env, op1, op2, new_rd_ia32_fAnd);
580 return gen_binop(env, op1, op2, new_rd_ia32_And);
587 * Creates an ia32 Or.
589 * @param env The transformation environment
590 * @param op1 The first operator
591 * @param op2 The second operator
592 * @return The created ia32 Or node
594 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
595 if (mode_is_float(env->mode)) {
596 return gen_binop(env, op1, op2, new_rd_ia32_fOr);
599 return gen_binop(env, op1, op2, new_rd_ia32_Or);
606 * Creates an ia32 Eor.
608 * @param env The transformation environment
609 * @param op1 The first operator
610 * @param op2 The second operator
611 * @return The created ia32 Eor node
613 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
614 if (mode_is_float(env->mode)) {
615 return gen_binop(env, op1, op2, new_rd_ia32_fEor);
618 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
625 * Creates an ia32 Max.
627 * @param env The transformation environment
628 * @param op1 The first operator
629 * @param op2 The second operator
630 * @return the created ia32 Max node
632 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
635 if (mode_is_float(env->mode)) {
636 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
639 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
640 set_ia32_am_support(new_op, ia32_am_None);
641 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
650 * Creates an ia32 Min.
652 * @param env The transformation environment
653 * @param op1 The first operator
654 * @param op2 The second operator
655 * @return the created ia32 Min node
657 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
660 if (mode_is_float(env->mode)) {
661 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
664 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
665 set_ia32_am_support(new_op, ia32_am_None);
666 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
675 * Creates an ia32 Sub with immediate.
677 * @param env The transformation environment
678 * @param op1 The first operator
679 * @param op2 The second operator
680 * @return The created ia32 Sub node
682 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
683 ir_node *new_op = NULL;
684 tarval *tv = get_ia32_Immop_tarval(const_op);
685 firm_dbg_module_t *mod = env->mod;
686 dbg_info *dbg = env->dbg;
687 ir_graph *irg = env->irg;
688 ir_node *block = env->block;
689 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
690 ir_node *nomem = new_NoMem();
692 tarval_classification_t class_tv, class_negtv;
694 /* try to optimize to inc/dec */
695 if (env->cg->opt.incdec && tv) {
696 /* optimize tarvals */
697 class_tv = classify_tarval(tv);
698 class_negtv = classify_tarval(tarval_neg(tv));
700 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
701 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
702 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
705 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
706 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
707 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
713 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
714 set_ia32_Immop_attr(new_op, const_op);
721 * Creates an ia32 Sub.
723 * @param env The transformation environment
724 * @param op1 The first operator
725 * @param op2 The second operator
726 * @return The created ia32 Sub node
728 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
729 ir_node *new_op = NULL;
730 dbg_info *dbg = env->dbg;
731 ir_mode *mode = env->mode;
732 ir_graph *irg = env->irg;
733 ir_node *block = env->block;
734 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
735 ir_node *nomem = new_NoMem();
736 ir_node *expr_op, *imm_op;
738 /* Check if immediate optimization is on and */
739 /* if it's an operation with immediate. */
740 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
741 expr_op = get_expr_op(op1, op2);
743 assert((expr_op || imm_op) && "invalid operands");
745 if (mode_is_float(mode)) {
746 return gen_binop(env, op1, op2, new_rd_ia32_fSub);
751 /* No expr_op means, that we have two const - one symconst and */
752 /* one tarval or another symconst - because this case is not */
753 /* covered by constant folding */
755 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
756 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
757 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
760 set_ia32_am_support(new_op, ia32_am_Source);
761 set_ia32_op_type(new_op, ia32_AddrModeS);
762 set_ia32_am_flavour(new_op, ia32_am_O);
764 /* Lea doesn't need a Proj */
768 /* This is expr - const */
769 new_op = gen_imm_Sub(env, expr_op, imm_op);
772 set_ia32_am_support(new_op, ia32_am_Dest);
775 /* This is a normal sub */
776 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
779 set_ia32_am_support(new_op, ia32_am_Full);
783 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
785 set_ia32_res_mode(new_op, mode);
787 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
793 * Generates an ia32 DivMod with additional infrastructure for the
794 * register allocator if needed.
796 * @param env The transformation environment
797 * @param dividend -no comment- :)
798 * @param divisor -no comment- :)
799 * @param dm_flav flavour_Div/Mod/DivMod
800 * @return The created ia32 DivMod node
802 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
804 ir_node *edx_node, *cltd;
806 dbg_info *dbg = env->dbg;
807 ir_graph *irg = env->irg;
808 ir_node *block = env->block;
809 ir_mode *mode = env->mode;
810 ir_node *irn = env->irn;
815 mem = get_Div_mem(irn);
816 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
819 mem = get_Mod_mem(irn);
820 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
823 mem = get_DivMod_mem(irn);
824 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
830 if (mode_is_signed(mode)) {
831 /* in signed mode, we need to sign extend the dividend */
832 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend, mode_T);
833 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EAX);
834 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EDX);
837 edx_node = new_rd_ia32_Const(dbg, irg, block, mode_Iu);
838 set_ia32_Const_type(edx_node, ia32_Const);
839 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
842 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode_T);
844 set_ia32_flavour(res, dm_flav);
845 set_ia32_n_res(res, 2);
847 /* Only one proj is used -> We must add a second proj and */
848 /* connect this one to a Keep node to eat up the second */
849 /* destroyed register. */
850 if (get_irn_n_edges(irn) == 1) {
851 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
852 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
854 if (get_Proj_proj(proj) == pn_DivMod_res_div) {
855 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
858 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
861 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
864 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
866 set_ia32_res_mode(res, mode_Is);
873 * Wrapper for generate_DivMod. Sets flavour_Mod.
875 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
876 return generate_DivMod(env, op1, op2, flavour_Mod);
882 * Wrapper for generate_DivMod. Sets flavour_Div.
884 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
885 return generate_DivMod(env, op1, op2, flavour_Div);
891 * Wrapper for generate_DivMod. Sets flavour_DivMod.
893 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
894 return generate_DivMod(env, op1, op2, flavour_DivMod);
900 * Creates an ia32 floating Div.
902 * @param env The transformation environment
903 * @param op1 The first operator
904 * @param op2 The second operator
905 * @return The created ia32 fDiv node
907 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
908 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
909 ir_node *nomem = new_rd_NoMem(env->irg);
912 if (is_ia32_fConst(op2)) {
913 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem, mode_T);
914 set_ia32_am_support(new_op, ia32_am_None);
915 set_ia32_Immop_attr(new_op, op2);
918 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T);
919 set_ia32_am_support(new_op, ia32_am_Source);
921 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
923 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
931 * Creates an ia32 Shl.
933 * @param env The transformation environment
934 * @param op1 The first operator
935 * @param op2 The second operator
936 * @return The created ia32 Shl node
938 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
939 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shl);
945 * Creates an ia32 Shr.
947 * @param env The transformation environment
948 * @param op1 The first operator
949 * @param op2 The second operator
950 * @return The created ia32 Shr node
952 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
953 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shr);
959 * Creates an ia32 Shrs.
961 * @param env The transformation environment
962 * @param op1 The first operator
963 * @param op2 The second operator
964 * @return The created ia32 Shrs node
966 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
967 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shrs);
973 * Creates an ia32 RotL.
975 * @param env The transformation environment
976 * @param op1 The first operator
977 * @param op2 The second operator
978 * @return The created ia32 RotL node
980 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
981 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
987 * Creates an ia32 RotR.
988 * NOTE: There is no RotR with immediate because this would always be a RotL
989 * "imm-mode_size_bits" which can be pre-calculated.
991 * @param env The transformation environment
992 * @param op1 The first operator
993 * @param op2 The second operator
994 * @return The created ia32 RotR node
996 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
997 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1003 * Creates an ia32 RotR or RotL (depending on the found pattern).
1005 * @param env The transformation environment
1006 * @param op1 The first operator
1007 * @param op2 The second operator
1008 * @return The created ia32 RotL or RotR node
1010 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1011 ir_node *rotate = NULL;
1013 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1014 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1015 that means we can create a RotR instead of an Add and a RotL */
1018 ir_node *pred = get_Proj_pred(op2);
1020 if (is_ia32_Add(pred)) {
1021 ir_node *pred_pred = get_irn_n(pred, 2);
1022 tarval *tv = get_ia32_Immop_tarval(pred);
1023 long bits = get_mode_size_bits(env->mode);
1025 if (is_Proj(pred_pred)) {
1026 pred_pred = get_Proj_pred(pred_pred);
1029 if (is_ia32_Minus(pred_pred) &&
1030 tarval_is_long(tv) &&
1031 get_tarval_long(tv) == bits)
1033 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1034 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1041 rotate = gen_RotL(env, op1, op2);
1050 * Transforms a Minus node.
1052 * @param env The transformation environment
1053 * @param op The operator
1054 * @return The created ia32 Minus node
1056 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
1059 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1060 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1061 ir_node *nomem = new_rd_NoMem(env->irg);
1064 if (mode_is_float(env->mode)) {
1065 new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1067 size = get_mode_size_bits(env->mode);
1068 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1070 set_ia32_sc(new_op, name);
1072 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1074 set_ia32_res_mode(new_op, env->mode);
1075 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1077 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1080 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1089 * Transforms a Not node.
1091 * @param env The transformation environment
1092 * @param op The operator
1093 * @return The created ia32 Not node
1095 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) {
1098 if (mode_is_float(env->mode)) {
1102 new_op = gen_unop(env, op, new_rd_ia32_Not);
1111 * Transforms an Abs node.
1113 * @param env The transformation environment
1114 * @param op The operator
1115 * @return The created ia32 Abs node
1117 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
1118 ir_node *res, *p_eax, *p_edx;
1119 dbg_info *dbg = env->dbg;
1120 ir_mode *mode = env->mode;
1121 ir_graph *irg = env->irg;
1122 ir_node *block = env->block;
1123 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1124 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1125 ir_node *nomem = new_NoMem();
1129 if (mode_is_float(mode)) {
1130 res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1132 size = get_mode_size_bits(mode);
1133 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1135 set_ia32_sc(res, name);
1137 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1139 set_ia32_res_mode(res, mode);
1140 set_ia32_immop_type(res, ia32_ImmSymConst);
1142 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1145 res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T);
1146 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1147 set_ia32_res_mode(res, mode);
1149 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
1150 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
1152 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T);
1153 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1154 set_ia32_res_mode(res, mode);
1156 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1158 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T);
1159 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1160 set_ia32_res_mode(res, mode);
1162 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1171 * Transforms a Load.
1173 * @param mod the debug module
1174 * @param block the block the new node should belong to
1175 * @param node the ir Load node
1176 * @param mode node mode
1177 * @return the created ia32 Load node
1179 static ir_node *gen_Load(ia32_transform_env_t *env) {
1180 ir_node *node = env->irn;
1181 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1182 ir_mode *mode = get_Load_mode(node);
1185 if (mode_is_float(mode)) {
1186 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1189 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1192 set_ia32_am_support(new_op, ia32_am_Source);
1193 set_ia32_op_type(new_op, ia32_AddrModeS);
1194 set_ia32_am_flavour(new_op, ia32_B);
1195 set_ia32_ls_mode(new_op, mode);
1197 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1205 * Transforms a Store.
1207 * @param mod the debug module
1208 * @param block the block the new node should belong to
1209 * @param node the ir Store node
1210 * @param mode node mode
1211 * @return the created ia32 Store node
1213 static ir_node *gen_Store(ia32_transform_env_t *env) {
1214 ir_node *node = env->irn;
1215 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1216 ir_node *val = get_Store_value(node);
1217 ir_node *ptr = get_Store_ptr(node);
1218 ir_node *mem = get_Store_mem(node);
1219 ir_mode *mode = get_irn_mode(val);
1220 ir_node *sval = val;
1223 /* in case of storing a const (but not a symconst) -> make it an attribute */
1224 if (is_ia32_Const(val)) {
1228 if (mode_is_float(mode)) {
1229 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1231 else if (get_mode_size_bits(mode) == 8) {
1232 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1235 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1238 /* stored const is an attribute (saves a register) */
1239 if (is_ia32_Const(val)) {
1240 set_ia32_Immop_attr(new_op, val);
1243 set_ia32_am_support(new_op, ia32_am_Dest);
1244 set_ia32_op_type(new_op, ia32_AddrModeD);
1245 set_ia32_am_flavour(new_op, ia32_B);
1246 set_ia32_ls_mode(new_op, get_irn_mode(val));
1248 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1256 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1258 * @param env The transformation environment
1259 * @return The transformed node.
1261 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1262 dbg_info *dbg = env->dbg;
1263 ir_graph *irg = env->irg;
1264 ir_node *block = env->block;
1265 ir_node *node = env->irn;
1266 ir_node *sel = get_Cond_selector(node);
1267 ir_mode *sel_mode = get_irn_mode(sel);
1268 ir_node *res = NULL;
1269 ir_node *pred = NULL;
1270 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1271 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1273 if (is_Proj(sel) && sel_mode == mode_b) {
1274 ir_node *nomem = new_NoMem();
1276 pred = get_Proj_pred(sel);
1278 /* get both compare operators */
1279 cmp_a = get_Cmp_left(pred);
1280 cmp_b = get_Cmp_right(pred);
1282 /* check if we can use a CondJmp with immediate */
1283 cnst = env->cg->opt.immops ? get_immediate_op(cmp_a, cmp_b) : NULL;
1284 expr = get_expr_op(cmp_a, cmp_b);
1287 pn_Cmp pnc = get_Proj_proj(sel);
1289 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1290 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1291 /* a Cmp A =/!= 0 */
1292 ir_node *op1 = expr;
1293 ir_node *op2 = expr;
1294 ir_node *and = skip_Proj(expr);
1295 const char *cnst = NULL;
1297 /* check, if expr is an only once used And operation */
1298 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1299 op1 = get_irn_n(and, 2);
1300 op2 = get_irn_n(and, 3);
1302 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1304 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2, mode_T);
1305 set_ia32_pncode(res, get_Proj_proj(sel));
1308 copy_ia32_Immop_attr(res, and);
1311 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1316 if (mode_is_float(get_irn_mode(expr))) {
1317 res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1320 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1322 set_ia32_Immop_attr(res, cnst);
1325 if (mode_is_float(get_irn_mode(cmp_a))) {
1326 res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1329 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1333 set_ia32_pncode(res, get_Proj_proj(sel));
1334 set_ia32_am_support(res, ia32_am_Source);
1337 res = new_rd_ia32_SwitchJmp(dbg, irg, block, sel, mode_T);
1338 set_ia32_pncode(res, get_Cond_defaultProj(node));
1341 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1348 * Transforms a CopyB node.
1350 * @param env The transformation environment
1351 * @return The transformed node.
1353 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1354 ir_node *res = NULL;
1355 dbg_info *dbg = env->dbg;
1356 ir_graph *irg = env->irg;
1357 ir_mode *mode = env->mode;
1358 ir_node *block = env->block;
1359 ir_node *node = env->irn;
1360 ir_node *src = get_CopyB_src(node);
1361 ir_node *dst = get_CopyB_dst(node);
1362 ir_node *mem = get_CopyB_mem(node);
1363 int size = get_type_size_bytes(get_CopyB_type(node));
1366 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1367 /* then we need the size explicitly in ECX. */
1368 if (size >= 16 * 4) {
1369 rem = size & 0x3; /* size % 4 */
1372 res = new_rd_ia32_Const(dbg, irg, block, mode_Is);
1373 set_ia32_op_type(res, ia32_Const);
1374 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1376 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1377 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1380 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1381 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1382 set_ia32_immop_type(res, ia32_ImmConst);
1385 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1393 * Transforms a Mux node into CMov.
1395 * @param env The transformation environment
1396 * @return The transformed node.
1398 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1399 ir_node *node = env->irn;
1400 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1401 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1403 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1410 * Following conversion rules apply:
1414 * 1) n bit -> m bit n > m (downscale)
1415 * a) target is signed: movsx
1416 * b) target is unsigned: and with lower bits sets
1417 * 2) n bit -> m bit n == m (sign change)
1419 * 3) n bit -> m bit n < m (upscale)
1420 * a) source is signed: movsx
1421 * b) source is unsigned: and with lower bits sets
1425 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1429 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1430 * if target mode < 32bit: additional INT -> INT conversion (see above)
1434 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1437 //static ir_node *gen_int_downscale_conv(ia32_transform_env_t *env, ir_node *op,
1438 // ir_mode *src_mode, ir_mode *tgt_mode)
1440 // int n = get_mode_size_bits(src_mode);
1441 // int m = get_mode_size_bits(tgt_mode);
1442 // dbg_info *dbg = env->dbg;
1443 // ir_graph *irg = env->irg;
1444 // ir_node *block = env->block;
1445 // ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1446 // ir_node *nomem = new_rd_NoMem(irg);
1447 // ir_node *new_op, *proj;
1448 // assert(n > m && "downscale expected");
1449 // if (mode_is_signed(src_mode) && mode_is_signed(tgt_mode)) {
1450 // /* ASHL Sn, n - m */
1451 // new_op = new_rd_ia32_Shl(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
1452 // proj = new_rd_Proj(dbg, irg, block, new_op, src_mode, 0);
1453 // set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
1454 // set_ia32_am_support(new_op, ia32_am_Source);
1455 // SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1456 // /* ASHR Sn, n - m */
1457 // new_op = new_rd_ia32_Shrs(dbg, irg, block, noreg, noreg, proj, noreg, nomem, mode_T);
1458 // set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
1461 // new_op = new_rd_ia32_And(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
1462 // set_ia32_Immop_tarval(new_op, new_tarval_from_long((1 << m) - 1, mode_Is));
1468 * Transforms a Conv node.
1470 * @param env The transformation environment
1471 * @param op The operator
1472 * @return The created ia32 Conv node
1474 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
1475 dbg_info *dbg = env->dbg;
1476 ir_graph *irg = env->irg;
1477 ir_mode *src_mode = get_irn_mode(op);
1478 ir_mode *tgt_mode = env->mode;
1479 int src_bits = get_mode_size_bits(src_mode);
1480 int tgt_bits = get_mode_size_bits(tgt_mode);
1481 ir_node *block = env->block;
1482 ir_node *new_op = NULL;
1483 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1484 ir_node *nomem = new_rd_NoMem(irg);
1485 firm_dbg_module_t *mod = env->mod;
1488 if (src_mode == tgt_mode) {
1489 /* this can happen when changing mode_P to mode_Is */
1490 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1491 edges_reroute(env->irn, op, irg);
1493 else if (mode_is_float(src_mode)) {
1494 /* we convert from float ... */
1495 if (mode_is_float(tgt_mode)) {
1497 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1498 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1502 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1503 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1504 /* if target mode is not int: add an additional downscale convert */
1505 if (tgt_bits < 32) {
1506 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1507 set_ia32_res_mode(new_op, tgt_mode);
1508 set_ia32_am_support(new_op, ia32_am_Source);
1510 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
1512 if (tgt_bits == 8 || src_bits == 8) {
1513 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem, mode_T);
1516 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem, mode_T);
1522 /* we convert from int ... */
1523 if (mode_is_float(tgt_mode)) {
1525 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1526 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1530 if (get_mode_size_bits(src_mode) == tgt_bits) {
1531 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
1532 edges_reroute(env->irn, op, irg);
1535 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
1536 if (tgt_bits == 8 || src_bits == 8) {
1537 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1540 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1547 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1548 set_ia32_res_mode(new_op, tgt_mode);
1550 set_ia32_am_support(new_op, ia32_am_Source);
1552 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
1560 /********************************************
1563 * | |__ ___ _ __ ___ __| | ___ ___
1564 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1565 * | |_) | __/ | | | (_) | (_| | __/\__ \
1566 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1568 ********************************************/
1570 static ir_node *gen_StackParam(ia32_transform_env_t *env) {
1571 ir_node *new_op = NULL;
1572 ir_node *node = env->irn;
1573 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1574 ir_node *mem = new_rd_NoMem(env->irg);
1575 ir_node *ptr = get_irn_n(node, 0);
1576 entity *ent = be_get_frame_entity(node);
1577 ir_mode *mode = env->mode;
1579 if (mode_is_float(mode)) {
1580 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1583 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1586 set_ia32_frame_ent(new_op, ent);
1587 set_ia32_use_frame(new_op);
1589 set_ia32_am_support(new_op, ia32_am_Source);
1590 set_ia32_op_type(new_op, ia32_AddrModeS);
1591 set_ia32_am_flavour(new_op, ia32_B);
1592 set_ia32_ls_mode(new_op, mode);
1594 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1596 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
1600 * Transforms a FrameAddr into an ia32 Add.
1602 static ir_node *gen_FrameAddr(ia32_transform_env_t *env) {
1603 ir_node *new_op = NULL;
1604 ir_node *node = env->irn;
1605 ir_node *op = get_irn_n(node, 0);
1606 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1607 ir_node *nomem = new_rd_NoMem(env->irg);
1609 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem, mode_T);
1610 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1611 set_ia32_am_support(new_op, ia32_am_Full);
1612 set_ia32_use_frame(new_op);
1613 set_ia32_immop_type(new_op, ia32_ImmConst);
1615 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1617 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1621 * Transforms a FrameLoad into an ia32 Load.
1623 static ir_node *gen_FrameLoad(ia32_transform_env_t *env) {
1624 ir_node *new_op = NULL;
1625 ir_node *node = env->irn;
1626 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1627 ir_node *mem = get_irn_n(node, 0);
1628 ir_node *ptr = get_irn_n(node, 1);
1629 entity *ent = be_get_frame_entity(node);
1630 ir_mode *mode = get_type_mode(get_entity_type(ent));
1632 if (mode_is_float(mode)) {
1633 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1636 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1639 set_ia32_frame_ent(new_op, ent);
1640 set_ia32_use_frame(new_op);
1642 set_ia32_am_support(new_op, ia32_am_Source);
1643 set_ia32_op_type(new_op, ia32_AddrModeS);
1644 set_ia32_am_flavour(new_op, ia32_B);
1645 set_ia32_ls_mode(new_op, mode);
1647 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1654 * Transforms a FrameStore into an ia32 Store.
1656 static ir_node *gen_FrameStore(ia32_transform_env_t *env) {
1657 ir_node *new_op = NULL;
1658 ir_node *node = env->irn;
1659 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1660 ir_node *mem = get_irn_n(node, 0);
1661 ir_node *ptr = get_irn_n(node, 1);
1662 ir_node *val = get_irn_n(node, 2);
1663 entity *ent = be_get_frame_entity(node);
1664 ir_mode *mode = get_irn_mode(val);
1666 if (mode_is_float(mode)) {
1667 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1669 else if (get_mode_size_bits(mode) == 8) {
1670 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1673 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1676 set_ia32_frame_ent(new_op, ent);
1677 set_ia32_use_frame(new_op);
1679 set_ia32_am_support(new_op, ia32_am_Dest);
1680 set_ia32_op_type(new_op, ia32_AddrModeD);
1681 set_ia32_am_flavour(new_op, ia32_B);
1682 set_ia32_ls_mode(new_op, mode);
1684 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1691 /*********************************************************
1694 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1695 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1696 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1697 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1699 *********************************************************/
1702 * Transforms a Sub or fSub into Neg--Add iff OUT_REG == SRC2_REG.
1703 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
1705 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
1706 ia32_transform_env_t tenv;
1707 ir_node *in1, *in2, *noreg, *nomem, *res;
1708 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
1710 /* Return if AM node or not a Sub or fSub */
1711 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_fSub(irn)))
1714 noreg = ia32_new_NoReg_gp(cg);
1715 nomem = new_rd_NoMem(cg->irg);
1716 in1 = get_irn_n(irn, 2);
1717 in2 = get_irn_n(irn, 3);
1718 in1_reg = arch_get_irn_register(cg->arch_env, in1);
1719 in2_reg = arch_get_irn_register(cg->arch_env, in2);
1720 out_reg = get_ia32_out_reg(irn, 0);
1722 tenv.block = get_nodes_block(irn);
1723 tenv.dbg = get_irn_dbg_info(irn);
1727 tenv.mode = get_ia32_res_mode(irn);
1730 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
1731 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
1732 /* generate the neg src2 */
1733 res = gen_Minus(&tenv, in2);
1734 arch_set_irn_register(cg->arch_env, res, in2_reg);
1736 /* add to schedule */
1737 sched_add_before(irn, res);
1739 /* generate the add */
1740 if (mode_is_float(tenv.mode)) {
1741 res = new_rd_ia32_fAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
1742 set_ia32_am_support(res, ia32_am_Source);
1745 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
1746 set_ia32_am_support(res, ia32_am_Full);
1749 SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv));
1751 slots = get_ia32_slots(res);
1754 /* add to schedule */
1755 sched_add_before(irn, res);
1757 /* remove the old sub */
1760 /* exchange the add and the sub */
1766 * Transforms a LEA into an Add if possible
1767 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
1769 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
1770 ia32_am_flavour_t am_flav;
1772 ir_node *res = NULL;
1773 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
1775 ia32_transform_env_t tenv;
1776 const arch_register_t *out_reg, *base_reg, *index_reg;
1779 if (! is_ia32_Lea(irn))
1782 am_flav = get_ia32_am_flavour(irn);
1784 /* only some LEAs can be transformed to an Add */
1785 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
1788 noreg = ia32_new_NoReg_gp(cg);
1789 nomem = new_rd_NoMem(cg->irg);
1792 base = get_irn_n(irn, 0);
1793 index = get_irn_n(irn,1);
1795 offs = get_ia32_am_offs(irn);
1797 /* offset has a explicit sign -> we need to skip + */
1798 if (offs && offs[0] == '+')
1801 out_reg = arch_get_irn_register(cg->arch_env, irn);
1802 base_reg = arch_get_irn_register(cg->arch_env, base);
1803 index_reg = arch_get_irn_register(cg->arch_env, index);
1805 tenv.block = get_nodes_block(irn);
1806 tenv.dbg = get_irn_dbg_info(irn);
1810 tenv.mode = get_irn_mode(irn);
1813 switch(get_ia32_am_flavour(irn)) {
1815 /* out register must be same as base register */
1816 if (! REGS_ARE_EQUAL(out_reg, base_reg))
1822 /* out register must be same as base register */
1823 if (! REGS_ARE_EQUAL(out_reg, base_reg))
1830 /* out register must be same as index register */
1831 if (! REGS_ARE_EQUAL(out_reg, index_reg))
1838 /* out register must be same as one in register */
1839 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
1843 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
1848 /* in registers a different from out -> no Add possible */
1855 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem, mode_T);
1856 arch_set_irn_register(cg->arch_env, res, out_reg);
1857 set_ia32_op_type(res, ia32_Normal);
1860 set_ia32_cnst(res, offs);
1861 set_ia32_immop_type(res, ia32_ImmConst);
1864 SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv));
1866 /* add Add to schedule */
1867 sched_add_before(irn, res);
1869 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, 0);
1871 /* add result Proj to schedule */
1872 sched_add_before(irn, res);
1874 /* remove the old LEA */
1877 /* exchange the Add and the LEA */
1882 * Transforms the given firm node (and maybe some other related nodes)
1883 * into one or more assembler nodes.
1885 * @param node the firm node
1886 * @param env the debug module
1888 void ia32_transform_node(ir_node *node, void *env) {
1889 ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env;
1891 ir_node *asm_node = NULL;
1892 ia32_transform_env_t tenv;
1897 tenv.block = get_nodes_block(node);
1898 tenv.dbg = get_irn_dbg_info(node);
1899 tenv.irg = current_ir_graph;
1901 tenv.mod = cgenv->mod;
1902 tenv.mode = get_irn_mode(node);
1905 #define UNOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_op(node)); break
1906 #define BINOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_left(node), get_##a##_right(node)); break
1907 #define GEN(a) case iro_##a: asm_node = gen_##a(&tenv); break
1908 #define IGN(a) case iro_##a: break
1909 #define BAD(a) case iro_##a: goto bad
1910 #define OTHER_BIN(a) \
1911 if (get_irn_op(node) == get_op_##a()) { \
1912 asm_node = gen_##a(&tenv, get_irn_n(node, 0), get_irn_n(node, 1)); \
1916 if (be_is_##a(node)) { \
1917 asm_node = gen_##a(&tenv); \
1921 DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
1923 code = get_irn_opcode(node);
1969 /* constant transformation happens earlier */
1999 fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
2003 /* exchange nodes if a new one was generated */
2005 exchange(node, asm_node);
2006 DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2009 DB((tenv.mod, LEVEL_1, "ignored\n"));