2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_map_regs.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
67 #include "gen_ia32_regalloc_if.h"
69 #define SFP_SIGN "0x80000000"
70 #define DFP_SIGN "0x8000000000000000"
71 #define SFP_ABS "0x7FFFFFFF"
72 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
74 #define TP_SFP_SIGN "ia32_sfp_sign"
75 #define TP_DFP_SIGN "ia32_dfp_sign"
76 #define TP_SFP_ABS "ia32_sfp_abs"
77 #define TP_DFP_ABS "ia32_dfp_abs"
79 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
80 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
81 #define ENT_SFP_ABS "IA32_SFP_ABS"
82 #define ENT_DFP_ABS "IA32_DFP_ABS"
84 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
85 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
87 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 /** hold the current code generator during transformation */
90 static ia32_code_gen_t *env_cg = NULL;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
119 static ir_node *create_immediate_or_transform(ir_node *node,
120 char immediate_constraint_type);
123 * Return true if a mode can be stored in the GP register set
125 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
126 if(mode == mode_fpcw)
128 return mode_is_int(mode) || mode_is_character(mode)
129 || mode_is_reference(mode) || mode == mode_b;
133 * Returns 1 if irn is a Const representing 0, 0 otherwise
135 static INLINE int is_ia32_Const_0(ir_node *irn) {
136 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
137 && tarval_is_null(get_ia32_Immop_tarval(irn));
141 * Returns 1 if irn is a Const representing 1, 0 otherwise
143 static INLINE int is_ia32_Const_1(ir_node *irn) {
144 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
145 && tarval_is_one(get_ia32_Immop_tarval(irn));
149 * Collects all Projs of a node into the node array. Index is the projnum.
150 * BEWARE: The caller has to assure the appropriate array size!
152 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
153 const ir_edge_t *edge;
154 assert(get_irn_mode(irn) == mode_T && "need mode_T");
156 memset(projs, 0, size * sizeof(projs[0]));
158 foreach_out_edge(irn, edge) {
159 ir_node *proj = get_edge_src_irn(edge);
160 int proj_proj = get_Proj_proj(proj);
161 assert(proj_proj < size);
162 projs[proj_proj] = proj;
167 * Renumbers the proj having pn_old in the array tp pn_new
168 * and removes the proj from the array.
170 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
171 fprintf(stderr, "Warning: renumber_Proj used!\n");
173 set_Proj_proj(projs[pn_old], pn_new);
174 projs[pn_old] = NULL;
179 * creates a unique ident by adding a number to a tag
181 * @param tag the tag string, must contain a %d if a number
184 static ident *unique_id(const char *tag)
186 static unsigned id = 0;
189 snprintf(str, sizeof(str), tag, ++id);
190 return new_id_from_str(str);
194 * Get a primitive type for a mode.
196 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
198 pmap_entry *e = pmap_find(types, mode);
203 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
204 res = new_type_primitive(new_id_from_str(buf), mode);
205 set_type_alignment_bytes(res, 16);
206 pmap_insert(types, mode, res);
214 * Get an entity that is initialized with a tarval
216 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
218 tarval *tv = get_Const_tarval(cnst);
219 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
224 ir_mode *mode = get_irn_mode(cnst);
225 ir_type *tp = get_Const_type(cnst);
226 if (tp == firm_unknown_type)
227 tp = get_prim_type(cg->isa->types, mode);
229 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
231 set_entity_ld_ident(res, get_entity_ident(res));
232 set_entity_visibility(res, visibility_local);
233 set_entity_variability(res, variability_constant);
234 set_entity_allocation(res, allocation_static);
236 /* we create a new entity here: It's initialization must resist on the
238 rem = current_ir_graph;
239 current_ir_graph = get_const_code_irg();
240 set_atomic_ent_value(res, new_Const_type(tv, tp));
241 current_ir_graph = rem;
243 pmap_insert(cg->isa->tv_ent, tv, res);
251 static int is_Const_0(ir_node *node) {
255 return classify_Const(node) == CNST_NULL;
258 static int is_Const_1(ir_node *node) {
262 return classify_Const(node) == CNST_ONE;
266 * Transforms a Const.
268 static ir_node *gen_Const(ir_node *node) {
269 ir_graph *irg = current_ir_graph;
270 ir_node *block = be_transform_node(get_nodes_block(node));
271 dbg_info *dbgi = get_irn_dbg_info(node);
272 ir_mode *mode = get_irn_mode(node);
274 if (mode_is_float(mode)) {
276 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
277 ir_node *nomem = new_NoMem();
282 if (! USE_SSE2(env_cg)) {
283 cnst_classify_t clss = classify_Const(node);
285 if (clss == CNST_NULL) {
286 load = new_rd_ia32_vfldz(dbgi, irg, block);
288 } else if (clss == CNST_ONE) {
289 load = new_rd_ia32_vfld1(dbgi, irg, block);
292 floatent = get_entity_for_tv(env_cg, node);
294 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
295 set_ia32_op_type(load, ia32_AddrModeS);
296 set_ia32_am_flavour(load, ia32_am_N);
297 set_ia32_am_sc(load, floatent);
298 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
299 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
301 set_ia32_ls_mode(load, mode);
303 floatent = get_entity_for_tv(env_cg, node);
305 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
306 set_ia32_op_type(load, ia32_AddrModeS);
307 set_ia32_am_flavour(load, ia32_am_N);
308 set_ia32_am_sc(load, floatent);
309 set_ia32_ls_mode(load, mode);
310 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
312 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
315 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
317 /* Const Nodes before the initial IncSP are a bad idea, because
318 * they could be spilled and we have no SP ready at that point yet.
319 * So add a dependency to the initial frame pointer calculation to
320 * avoid that situation.
322 if (get_irg_start_block(irg) == block) {
323 add_irn_dep(load, get_irg_frame(irg));
326 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
329 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
332 if (get_irg_start_block(irg) == block) {
333 add_irn_dep(cnst, get_irg_frame(irg));
336 set_ia32_Const_attr(cnst, node);
337 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
342 return new_r_Bad(irg);
346 * Transforms a SymConst.
348 static ir_node *gen_SymConst(ir_node *node) {
349 ir_graph *irg = current_ir_graph;
350 ir_node *block = be_transform_node(get_nodes_block(node));
351 dbg_info *dbgi = get_irn_dbg_info(node);
352 ir_mode *mode = get_irn_mode(node);
355 if (mode_is_float(mode)) {
357 if (USE_SSE2(env_cg))
358 cnst = new_rd_ia32_xConst(dbgi, irg, block);
360 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
361 //set_ia32_ls_mode(cnst, mode);
362 set_ia32_ls_mode(cnst, mode_E);
364 cnst = new_rd_ia32_Const(dbgi, irg, block);
367 /* Const Nodes before the initial IncSP are a bad idea, because
368 * they could be spilled and we have no SP ready at that point yet
370 if (get_irg_start_block(irg) == block) {
371 add_irn_dep(cnst, get_irg_frame(irg));
374 set_ia32_Const_attr(cnst, node);
375 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
380 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
381 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
382 static const struct {
384 const char *ent_name;
385 const char *cnst_str;
386 } names [ia32_known_const_max] = {
387 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
388 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
389 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
390 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
392 static ir_entity *ent_cache[ia32_known_const_max];
394 const char *tp_name, *ent_name, *cnst_str;
402 ent_name = names[kct].ent_name;
403 if (! ent_cache[kct]) {
404 tp_name = names[kct].tp_name;
405 cnst_str = names[kct].cnst_str;
407 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
409 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
410 tp = new_type_primitive(new_id_from_str(tp_name), mode);
411 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
413 set_entity_ld_ident(ent, get_entity_ident(ent));
414 set_entity_visibility(ent, visibility_local);
415 set_entity_variability(ent, variability_constant);
416 set_entity_allocation(ent, allocation_static);
418 /* we create a new entity here: It's initialization must resist on the
420 rem = current_ir_graph;
421 current_ir_graph = get_const_code_irg();
422 cnst = new_Const(mode, tv);
423 current_ir_graph = rem;
425 set_atomic_ent_value(ent, cnst);
427 /* cache the entry */
428 ent_cache[kct] = ent;
431 return ent_cache[kct];
436 * Prints the old node name on cg obst and returns a pointer to it.
438 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
439 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
441 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
442 obstack_1grow(isa->name_obst, 0);
443 return obstack_finish(isa->name_obst);
447 /* determine if one operator is an Imm */
448 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
450 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
452 return is_ia32_Cnst(op2) ? op2 : NULL;
456 /* determine if one operator is not an Imm */
457 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
458 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
461 static void fold_immediate(ir_node *node, int in1, int in2) {
465 if (!(env_cg->opt & IA32_OPT_IMMOPS))
468 left = get_irn_n(node, in1);
469 right = get_irn_n(node, in2);
470 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
471 /* we can only set right operand to immediate */
472 if(!is_ia32_commutative(node))
474 /* exchange left/right */
475 set_irn_n(node, in1, right);
476 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
477 copy_ia32_Immop_attr(node, left);
478 } else if(is_ia32_Cnst(right)) {
479 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
480 copy_ia32_Immop_attr(node, right);
485 clear_ia32_commutative(node);
486 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
487 get_ia32_am_arity(node));
491 * Construct a standard binary operation, set AM and immediate if required.
493 * @param op1 The first operand
494 * @param op2 The second operand
495 * @param func The node constructor function
496 * @return The constructed ia32 node.
498 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
499 construct_binop_func *func, int commutative)
501 ir_node *block = be_transform_node(get_nodes_block(node));
502 ir_graph *irg = current_ir_graph;
503 dbg_info *dbgi = get_irn_dbg_info(node);
504 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
505 ir_node *nomem = new_NoMem();
508 ir_node *new_op1 = be_transform_node(op1);
509 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
510 if (is_ia32_Immediate(new_op2)) {
514 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
515 if (func == new_rd_ia32_IMul) {
516 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
518 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
521 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
523 set_ia32_commutative(new_node);
530 * Construct a standard binary operation, set AM and immediate if required.
532 * @param op1 The first operand
533 * @param op2 The second operand
534 * @param func The node constructor function
535 * @return The constructed ia32 node.
537 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
538 construct_binop_func *func)
540 ir_node *block = be_transform_node(get_nodes_block(node));
541 ir_node *new_op1 = be_transform_node(op1);
542 ir_node *new_op2 = be_transform_node(op2);
543 ir_node *new_node = NULL;
544 dbg_info *dbgi = get_irn_dbg_info(node);
545 ir_graph *irg = current_ir_graph;
546 ir_mode *mode = get_irn_mode(node);
547 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
548 ir_node *nomem = new_NoMem();
550 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
552 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
553 if (is_op_commutative(get_irn_op(node))) {
554 set_ia32_commutative(new_node);
556 set_ia32_ls_mode(new_node, mode);
558 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
564 * Construct a standard binary operation, set AM and immediate if required.
566 * @param op1 The first operand
567 * @param op2 The second operand
568 * @param func The node constructor function
569 * @return The constructed ia32 node.
571 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
572 construct_binop_float_func *func)
574 ir_node *block = be_transform_node(get_nodes_block(node));
575 ir_node *new_op1 = be_transform_node(op1);
576 ir_node *new_op2 = be_transform_node(op2);
577 ir_node *new_node = NULL;
578 dbg_info *dbgi = get_irn_dbg_info(node);
579 ir_graph *irg = current_ir_graph;
580 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
581 ir_node *nomem = new_NoMem();
582 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
583 &ia32_fp_cw_regs[REG_FPCW]);
585 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
587 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
588 if (is_op_commutative(get_irn_op(node))) {
589 set_ia32_commutative(new_node);
592 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
598 * Construct a shift/rotate binary operation, sets AM and immediate if required.
600 * @param op1 The first operand
601 * @param op2 The second operand
602 * @param func The node constructor function
603 * @return The constructed ia32 node.
605 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
606 construct_binop_func *func)
608 ir_node *block = be_transform_node(get_nodes_block(node));
609 ir_node *new_op1 = be_transform_node(op1);
611 ir_node *new_op = NULL;
612 dbg_info *dbgi = get_irn_dbg_info(node);
613 ir_graph *irg = current_ir_graph;
614 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
615 ir_node *nomem = new_NoMem();
617 assert(! mode_is_float(get_irn_mode(node))
618 && "Shift/Rotate with float not supported");
620 new_op2 = create_immediate_or_transform(op2, 'N');
622 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
625 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
627 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
629 set_ia32_emit_cl(new_op);
636 * Construct a standard unary operation, set AM and immediate if required.
638 * @param op The operand
639 * @param func The node constructor function
640 * @return The constructed ia32 node.
642 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
644 ir_node *block = be_transform_node(get_nodes_block(node));
645 ir_node *new_op = be_transform_node(op);
646 ir_node *new_node = NULL;
647 ir_graph *irg = current_ir_graph;
648 dbg_info *dbgi = get_irn_dbg_info(node);
649 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
650 ir_node *nomem = new_NoMem();
652 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
653 DB((dbg, LEVEL_1, "INT unop ..."));
654 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
656 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
662 * Creates an ia32 Add.
664 * @return the created ia32 Add node
666 static ir_node *gen_Add(ir_node *node) {
667 ir_node *block = be_transform_node(get_nodes_block(node));
668 ir_node *op1 = get_Add_left(node);
669 ir_node *new_op1 = be_transform_node(op1);
670 ir_node *op2 = get_Add_right(node);
671 ir_node *new_op2 = be_transform_node(op2);
672 ir_node *new_op = NULL;
673 ir_graph *irg = current_ir_graph;
674 dbg_info *dbgi = get_irn_dbg_info(node);
675 ir_mode *mode = get_irn_mode(node);
676 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
677 ir_node *nomem = new_NoMem();
678 ir_node *expr_op, *imm_op;
680 /* Check if immediate optimization is on and */
681 /* if it's an operation with immediate. */
682 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
683 expr_op = get_expr_op(new_op1, new_op2);
685 assert((expr_op || imm_op) && "invalid operands");
687 if (mode_is_float(mode)) {
689 if (USE_SSE2(env_cg))
690 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
692 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
697 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
698 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
700 /* No expr_op means, that we have two const - one symconst and */
701 /* one tarval or another symconst - because this case is not */
702 /* covered by constant folding */
703 /* We need to check for: */
704 /* 1) symconst + const -> becomes a LEA */
705 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
706 /* linker doesn't support two symconsts */
708 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
709 /* this is the 2nd case */
710 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
711 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
712 set_ia32_am_flavour(new_op, ia32_am_B);
713 set_ia32_op_type(new_op, ia32_AddrModeS);
715 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
716 } else if (tp1 == ia32_ImmSymConst) {
717 tarval *tv = get_ia32_Immop_tarval(new_op2);
718 long offs = get_tarval_long(tv);
720 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
721 add_irn_dep(new_op, get_irg_frame(irg));
722 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
724 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
725 add_ia32_am_offs_int(new_op, offs);
726 set_ia32_am_flavour(new_op, ia32_am_OB);
727 set_ia32_op_type(new_op, ia32_AddrModeS);
728 } else if (tp2 == ia32_ImmSymConst) {
729 tarval *tv = get_ia32_Immop_tarval(new_op1);
730 long offs = get_tarval_long(tv);
732 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
733 add_irn_dep(new_op, get_irg_frame(irg));
734 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
736 add_ia32_am_offs_int(new_op, offs);
737 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
738 set_ia32_am_flavour(new_op, ia32_am_OB);
739 set_ia32_op_type(new_op, ia32_AddrModeS);
741 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
742 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
743 tarval *restv = tarval_add(tv1, tv2);
745 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
747 new_op = new_rd_ia32_Const(dbgi, irg, block);
748 set_ia32_Const_tarval(new_op, restv);
749 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
752 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
755 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
756 tarval_classification_t class_tv, class_negtv;
757 tarval *tv = get_ia32_Immop_tarval(imm_op);
759 /* optimize tarvals */
760 class_tv = classify_tarval(tv);
761 class_negtv = classify_tarval(tarval_neg(tv));
763 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
764 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
765 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
766 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
768 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
769 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
770 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
771 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
777 /* This is a normal add */
778 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
781 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
782 set_ia32_commutative(new_op);
784 fold_immediate(new_op, 2, 3);
786 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
792 * Creates an ia32 Mul.
794 * @return the created ia32 Mul node
796 static ir_node *gen_Mul(ir_node *node) {
797 ir_node *op1 = get_Mul_left(node);
798 ir_node *op2 = get_Mul_right(node);
799 ir_mode *mode = get_irn_mode(node);
801 if (mode_is_float(mode)) {
803 if (USE_SSE2(env_cg))
804 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
806 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
810 for the lower 32bit of the result it doesn't matter whether we use
811 signed or unsigned multiplication so we use IMul as it has fewer
814 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
818 * Creates an ia32 Mulh.
819 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
820 * this result while Mul returns the lower 32 bit.
822 * @return the created ia32 Mulh node
824 static ir_node *gen_Mulh(ir_node *node) {
825 ir_node *block = be_transform_node(get_nodes_block(node));
826 ir_node *op1 = get_irn_n(node, 0);
827 ir_node *new_op1 = be_transform_node(op1);
828 ir_node *op2 = get_irn_n(node, 1);
829 ir_node *new_op2 = be_transform_node(op2);
830 ir_graph *irg = current_ir_graph;
831 dbg_info *dbgi = get_irn_dbg_info(node);
832 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
833 ir_mode *mode = get_irn_mode(node);
834 ir_node *proj_EAX, *proj_EDX, *res;
837 assert(!mode_is_float(mode) && "Mulh with float not supported");
838 if (mode_is_signed(mode)) {
839 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
841 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
844 set_ia32_commutative(res);
845 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
847 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
848 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
852 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
860 * Creates an ia32 And.
862 * @return The created ia32 And node
864 static ir_node *gen_And(ir_node *node) {
865 ir_node *op1 = get_And_left(node);
866 ir_node *op2 = get_And_right(node);
868 assert (! mode_is_float(get_irn_mode(node)));
869 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
875 * Creates an ia32 Or.
877 * @return The created ia32 Or node
879 static ir_node *gen_Or(ir_node *node) {
880 ir_node *op1 = get_Or_left(node);
881 ir_node *op2 = get_Or_right(node);
883 assert (! mode_is_float(get_irn_mode(node)));
884 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
890 * Creates an ia32 Eor.
892 * @return The created ia32 Eor node
894 static ir_node *gen_Eor(ir_node *node) {
895 ir_node *op1 = get_Eor_left(node);
896 ir_node *op2 = get_Eor_right(node);
898 assert(! mode_is_float(get_irn_mode(node)));
899 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
904 * Creates an ia32 Sub.
906 * @return The created ia32 Sub node
908 static ir_node *gen_Sub(ir_node *node) {
909 ir_node *block = be_transform_node(get_nodes_block(node));
910 ir_node *op1 = get_Sub_left(node);
911 ir_node *new_op1 = be_transform_node(op1);
912 ir_node *op2 = get_Sub_right(node);
913 ir_node *new_op2 = be_transform_node(op2);
914 ir_node *new_op = NULL;
915 ir_graph *irg = current_ir_graph;
916 dbg_info *dbgi = get_irn_dbg_info(node);
917 ir_mode *mode = get_irn_mode(node);
918 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
919 ir_node *nomem = new_NoMem();
920 ir_node *expr_op, *imm_op;
922 /* Check if immediate optimization is on and */
923 /* if it's an operation with immediate. */
924 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
925 expr_op = get_expr_op(new_op1, new_op2);
927 assert((expr_op || imm_op) && "invalid operands");
929 if (mode_is_float(mode)) {
931 if (USE_SSE2(env_cg))
932 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
934 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
939 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
940 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
942 /* No expr_op means, that we have two const - one symconst and */
943 /* one tarval or another symconst - because this case is not */
944 /* covered by constant folding */
945 /* We need to check for: */
946 /* 1) symconst - const -> becomes a LEA */
947 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
948 /* linker doesn't support two symconsts */
949 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
950 /* this is the 2nd case */
951 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
952 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
953 set_ia32_am_sc_sign(new_op);
954 set_ia32_am_flavour(new_op, ia32_am_B);
956 DBG_OPT_LEA3(op1, op2, node, new_op);
957 } else if (tp1 == ia32_ImmSymConst) {
958 tarval *tv = get_ia32_Immop_tarval(new_op2);
959 long offs = get_tarval_long(tv);
961 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
962 add_irn_dep(new_op, get_irg_frame(irg));
963 DBG_OPT_LEA3(op1, op2, node, new_op);
965 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
966 add_ia32_am_offs_int(new_op, -offs);
967 set_ia32_am_flavour(new_op, ia32_am_OB);
968 set_ia32_op_type(new_op, ia32_AddrModeS);
969 } else if (tp2 == ia32_ImmSymConst) {
970 tarval *tv = get_ia32_Immop_tarval(new_op1);
971 long offs = get_tarval_long(tv);
973 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
974 add_irn_dep(new_op, get_irg_frame(irg));
975 DBG_OPT_LEA3(op1, op2, node, new_op);
977 add_ia32_am_offs_int(new_op, offs);
978 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
979 set_ia32_am_sc_sign(new_op);
980 set_ia32_am_flavour(new_op, ia32_am_OB);
981 set_ia32_op_type(new_op, ia32_AddrModeS);
983 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
984 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
985 tarval *restv = tarval_sub(tv1, tv2);
987 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
989 new_op = new_rd_ia32_Const(dbgi, irg, block);
990 set_ia32_Const_tarval(new_op, restv);
991 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
994 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
997 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
998 tarval_classification_t class_tv, class_negtv;
999 tarval *tv = get_ia32_Immop_tarval(imm_op);
1001 /* optimize tarvals */
1002 class_tv = classify_tarval(tv);
1003 class_negtv = classify_tarval(tarval_neg(tv));
1005 if (class_tv == TV_CLASSIFY_ONE) {
1006 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1007 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1008 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1010 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1011 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1012 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1013 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1019 /* This is a normal sub */
1020 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1022 /* set AM support */
1023 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1025 fold_immediate(new_op, 2, 3);
1027 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1035 * Generates an ia32 DivMod with additional infrastructure for the
1036 * register allocator if needed.
1038 * @param dividend -no comment- :)
1039 * @param divisor -no comment- :)
1040 * @param dm_flav flavour_Div/Mod/DivMod
1041 * @return The created ia32 DivMod node
1043 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1044 ir_node *divisor, ia32_op_flavour_t dm_flav)
1046 ir_node *block = be_transform_node(get_nodes_block(node));
1047 ir_node *new_dividend = be_transform_node(dividend);
1048 ir_node *new_divisor = be_transform_node(divisor);
1049 ir_graph *irg = current_ir_graph;
1050 dbg_info *dbgi = get_irn_dbg_info(node);
1051 ir_mode *mode = get_irn_mode(node);
1052 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1053 ir_node *res, *proj_div, *proj_mod;
1054 ir_node *sign_extension;
1055 ir_node *in_keep[2];
1056 ir_node *mem, *new_mem;
1057 ir_node *projs[pn_DivMod_max];
1060 ia32_collect_Projs(node, projs, pn_DivMod_max);
1062 proj_div = proj_mod = NULL;
1066 mem = get_Div_mem(node);
1067 mode = get_Div_resmode(node);
1068 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1069 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1072 mem = get_Mod_mem(node);
1073 mode = get_Mod_resmode(node);
1074 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1075 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1077 case flavour_DivMod:
1078 mem = get_DivMod_mem(node);
1079 mode = get_DivMod_resmode(node);
1080 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1081 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1082 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1085 panic("invalid divmod flavour!");
1087 new_mem = be_transform_node(mem);
1089 if (mode_is_signed(mode)) {
1090 /* in signed mode, we need to sign extend the dividend */
1091 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1093 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1094 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1096 add_irn_dep(sign_extension, get_irg_frame(irg));
1099 if (mode_is_signed(mode)) {
1100 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1101 sign_extension, new_divisor, new_mem, dm_flav);
1103 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1104 sign_extension, new_divisor, new_mem, dm_flav);
1107 set_ia32_exc_label(res, has_exc);
1108 set_irn_pinned(res, get_irn_pinned(node));
1110 /* set AM support */
1111 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1113 /* check, which Proj-Keep, we need to add */
1115 if (proj_div == NULL) {
1116 /* We have only mod result: add div res Proj-Keep */
1117 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1120 if (proj_mod == NULL) {
1121 /* We have only div result: add mod res Proj-Keep */
1122 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1126 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1128 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1135 * Wrapper for generate_DivMod. Sets flavour_Mod.
1138 static ir_node *gen_Mod(ir_node *node) {
1139 return generate_DivMod(node, get_Mod_left(node),
1140 get_Mod_right(node), flavour_Mod);
1144 * Wrapper for generate_DivMod. Sets flavour_Div.
1147 static ir_node *gen_Div(ir_node *node) {
1148 return generate_DivMod(node, get_Div_left(node),
1149 get_Div_right(node), flavour_Div);
1153 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1155 static ir_node *gen_DivMod(ir_node *node) {
1156 return generate_DivMod(node, get_DivMod_left(node),
1157 get_DivMod_right(node), flavour_DivMod);
1163 * Creates an ia32 floating Div.
1165 * @return The created ia32 xDiv node
1167 static ir_node *gen_Quot(ir_node *node) {
1168 ir_node *block = be_transform_node(get_nodes_block(node));
1169 ir_node *op1 = get_Quot_left(node);
1170 ir_node *new_op1 = be_transform_node(op1);
1171 ir_node *op2 = get_Quot_right(node);
1172 ir_node *new_op2 = be_transform_node(op2);
1173 ir_graph *irg = current_ir_graph;
1174 dbg_info *dbgi = get_irn_dbg_info(node);
1175 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1176 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1180 if (USE_SSE2(env_cg)) {
1181 ir_mode *mode = get_irn_mode(op1);
1182 if (is_ia32_xConst(new_op2)) {
1183 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1184 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1185 copy_ia32_Immop_attr(new_op, new_op2);
1187 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1188 // Matze: disabled for now, spillslot coalescer fails
1189 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1191 set_ia32_ls_mode(new_op, mode);
1193 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1194 &ia32_fp_cw_regs[REG_FPCW]);
1195 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1196 new_op2, nomem, fpcw);
1197 // Matze: disabled for now (spillslot coalescer fails)
1198 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1200 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1206 * Creates an ia32 Shl.
1208 * @return The created ia32 Shl node
1210 static ir_node *gen_Shl(ir_node *node) {
1211 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1218 * Creates an ia32 Shr.
1220 * @return The created ia32 Shr node
1222 static ir_node *gen_Shr(ir_node *node) {
1223 return gen_shift_binop(node, get_Shr_left(node),
1224 get_Shr_right(node), new_rd_ia32_Shr);
1230 * Creates an ia32 Sar.
1232 * @return The created ia32 Shrs node
1234 static ir_node *gen_Shrs(ir_node *node) {
1235 ir_node *left = get_Shrs_left(node);
1236 ir_node *right = get_Shrs_right(node);
1237 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1238 tarval *tv = get_Const_tarval(right);
1239 long val = get_tarval_long(tv);
1241 /* this is a sign extension */
1242 ir_graph *irg = current_ir_graph;
1243 dbg_info *dbgi = get_irn_dbg_info(node);
1244 ir_node *block = be_transform_node(get_nodes_block(node));
1246 ir_node *new_op = be_transform_node(op);
1248 return new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1252 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1258 * Creates an ia32 RotL.
1260 * @param op1 The first operator
1261 * @param op2 The second operator
1262 * @return The created ia32 RotL node
1264 static ir_node *gen_RotL(ir_node *node,
1265 ir_node *op1, ir_node *op2) {
1266 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1272 * Creates an ia32 RotR.
1273 * NOTE: There is no RotR with immediate because this would always be a RotL
1274 * "imm-mode_size_bits" which can be pre-calculated.
1276 * @param op1 The first operator
1277 * @param op2 The second operator
1278 * @return The created ia32 RotR node
1280 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1282 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1288 * Creates an ia32 RotR or RotL (depending on the found pattern).
1290 * @return The created ia32 RotL or RotR node
1292 static ir_node *gen_Rot(ir_node *node) {
1293 ir_node *rotate = NULL;
1294 ir_node *op1 = get_Rot_left(node);
1295 ir_node *op2 = get_Rot_right(node);
1297 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1298 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1299 that means we can create a RotR instead of an Add and a RotL */
1301 if (get_irn_op(op2) == op_Add) {
1303 ir_node *left = get_Add_left(add);
1304 ir_node *right = get_Add_right(add);
1305 if (is_Const(right)) {
1306 tarval *tv = get_Const_tarval(right);
1307 ir_mode *mode = get_irn_mode(node);
1308 long bits = get_mode_size_bits(mode);
1310 if (get_irn_op(left) == op_Minus &&
1311 tarval_is_long(tv) &&
1312 get_tarval_long(tv) == bits)
1314 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1315 rotate = gen_RotR(node, op1, get_Minus_op(left));
1320 if (rotate == NULL) {
1321 rotate = gen_RotL(node, op1, op2);
1330 * Transforms a Minus node.
1332 * @param op The Minus operand
1333 * @return The created ia32 Minus node
1335 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1336 ir_node *block = be_transform_node(get_nodes_block(node));
1337 ir_graph *irg = current_ir_graph;
1338 dbg_info *dbgi = get_irn_dbg_info(node);
1339 ir_mode *mode = get_irn_mode(node);
1344 if (mode_is_float(mode)) {
1345 ir_node *new_op = be_transform_node(op);
1347 if (USE_SSE2(env_cg)) {
1348 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1349 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1350 ir_node *nomem = new_rd_NoMem(irg);
1352 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1354 size = get_mode_size_bits(mode);
1355 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1357 set_ia32_am_sc(res, ent);
1358 set_ia32_op_type(res, ia32_AddrModeS);
1359 set_ia32_ls_mode(res, mode);
1361 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1364 res = gen_unop(node, op, new_rd_ia32_Neg);
1367 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1373 * Transforms a Minus node.
1375 * @return The created ia32 Minus node
1377 static ir_node *gen_Minus(ir_node *node) {
1378 return gen_Minus_ex(node, get_Minus_op(node));
1381 static ir_node *gen_bin_Not(ir_node *node)
1383 ir_graph *irg = current_ir_graph;
1384 dbg_info *dbgi = get_irn_dbg_info(node);
1385 ir_node *block = be_transform_node(get_nodes_block(node));
1386 ir_node *op = get_Not_op(node);
1387 ir_node *new_op = be_transform_node(op);
1388 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1389 ir_node *nomem = new_NoMem();
1390 ir_node *one = new_rd_ia32_Immediate(dbgi, irg, block, NULL, 0, 1);
1391 arch_set_irn_register(env_cg->arch_env, one, &ia32_gp_regs[REG_GP_NOREG]);
1393 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1397 * Transforms a Not node.
1399 * @return The created ia32 Not node
1401 static ir_node *gen_Not(ir_node *node) {
1402 ir_node *op = get_Not_op(node);
1403 ir_mode *mode = get_irn_mode(node);
1405 if(mode == mode_b) {
1406 return gen_bin_Not(node);
1409 assert (! mode_is_float(get_irn_mode(node)));
1410 return gen_unop(node, op, new_rd_ia32_Not);
1416 * Transforms an Abs node.
1418 * @return The created ia32 Abs node
1420 static ir_node *gen_Abs(ir_node *node) {
1421 ir_node *block = be_transform_node(get_nodes_block(node));
1422 ir_node *op = get_Abs_op(node);
1423 ir_node *new_op = be_transform_node(op);
1424 ir_graph *irg = current_ir_graph;
1425 dbg_info *dbgi = get_irn_dbg_info(node);
1426 ir_mode *mode = get_irn_mode(node);
1427 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1428 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1429 ir_node *nomem = new_NoMem();
1434 if (mode_is_float(mode)) {
1436 if (USE_SSE2(env_cg)) {
1437 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1439 size = get_mode_size_bits(mode);
1440 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1442 set_ia32_am_sc(res, ent);
1444 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1446 set_ia32_op_type(res, ia32_AddrModeS);
1447 set_ia32_ls_mode(res, mode);
1450 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1451 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1455 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1456 SET_IA32_ORIG_NODE(sign_extension,
1457 ia32_get_old_node_name(env_cg, node));
1459 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1460 sign_extension, nomem);
1461 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1463 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1464 sign_extension, nomem);
1465 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1474 * Transforms a Load.
1476 * @return the created ia32 Load node
1478 static ir_node *gen_Load(ir_node *node) {
1479 ir_node *block = be_transform_node(get_nodes_block(node));
1480 ir_node *ptr = get_Load_ptr(node);
1481 ir_node *new_ptr = be_transform_node(ptr);
1482 ir_node *mem = get_Load_mem(node);
1483 ir_node *new_mem = be_transform_node(mem);
1484 ir_graph *irg = current_ir_graph;
1485 dbg_info *dbgi = get_irn_dbg_info(node);
1486 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1487 ir_mode *mode = get_Load_mode(node);
1489 ir_node *lptr = new_ptr;
1492 ir_node *projs[pn_Load_max];
1493 ia32_am_flavour_t am_flav = ia32_am_B;
1495 ia32_collect_Projs(node, projs, pn_Load_max);
1497 /* address might be a constant (symconst or absolute address) */
1498 if (is_ia32_Const(new_ptr)) {
1503 if (mode_is_float(mode)) {
1505 if (USE_SSE2(env_cg)) {
1506 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1507 res_mode = mode_xmm;
1509 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1510 res_mode = mode_vfp;
1513 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1518 check for special case: the loaded value might not be used
1520 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
1521 /* add a result proj and a Keep to produce a pseudo use */
1522 ir_node *proj = new_r_Proj(irg, block, new_op, mode_Iu,
1524 be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
1527 /* base is a constant address */
1529 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1530 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1531 am_flav = ia32_am_N;
1533 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1534 long offs = get_tarval_long(tv);
1536 add_ia32_am_offs_int(new_op, offs);
1537 am_flav = ia32_am_O;
1541 set_irn_pinned(new_op, get_irn_pinned(node));
1542 set_ia32_op_type(new_op, ia32_AddrModeS);
1543 set_ia32_am_flavour(new_op, am_flav);
1544 set_ia32_ls_mode(new_op, mode);
1546 /* make sure we are scheduled behind the initial IncSP/Barrier
1547 * to avoid spills being placed before it
1549 if (block == get_irg_start_block(irg)) {
1550 add_irn_dep(new_op, get_irg_frame(irg));
1553 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1554 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1562 * Transforms a Store.
1564 * @return the created ia32 Store node
1566 static ir_node *gen_Store(ir_node *node) {
1567 ir_node *block = be_transform_node(get_nodes_block(node));
1568 ir_node *ptr = get_Store_ptr(node);
1569 ir_node *new_ptr = be_transform_node(ptr);
1570 ir_node *val = get_Store_value(node);
1572 ir_node *mem = get_Store_mem(node);
1573 ir_node *new_mem = be_transform_node(mem);
1574 ir_graph *irg = current_ir_graph;
1575 dbg_info *dbgi = get_irn_dbg_info(node);
1576 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1577 ir_node *sptr = new_ptr;
1578 ir_mode *mode = get_irn_mode(val);
1581 ia32_am_flavour_t am_flav = ia32_am_B;
1583 /* address might be a constant (symconst or absolute address) */
1584 if (is_ia32_Const(new_ptr)) {
1589 if (mode_is_float(mode)) {
1592 new_val = be_transform_node(val);
1593 if (USE_SSE2(env_cg)) {
1594 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1597 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1601 new_val = create_immediate_or_transform(val, 0);
1603 if (get_mode_size_bits(mode) == 8) {
1604 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1607 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1612 /* base is an constant address */
1614 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1615 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1616 am_flav = ia32_am_N;
1618 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1619 long offs = get_tarval_long(tv);
1621 add_ia32_am_offs_int(new_op, offs);
1622 am_flav = ia32_am_O;
1626 set_irn_pinned(new_op, get_irn_pinned(node));
1627 set_ia32_op_type(new_op, ia32_AddrModeD);
1628 set_ia32_am_flavour(new_op, am_flav);
1629 set_ia32_ls_mode(new_op, mode);
1631 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1632 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1637 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1638 ir_node *cmp_left, ir_node *cmp_right)
1640 ir_node *new_cmp_left;
1641 ir_node *new_cmp_right;
1647 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1649 if(cmp_right != NULL && !is_Const_0(cmp_right))
1652 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1653 and_left = get_And_left(cmp_left);
1654 and_right = get_And_right(cmp_left);
1656 new_cmp_left = be_transform_node(and_left);
1657 new_cmp_right = create_immediate_or_transform(and_right, 0);
1659 new_cmp_left = be_transform_node(cmp_left);
1660 new_cmp_right = be_transform_node(cmp_left);
1663 noreg = ia32_new_NoReg_gp(env_cg);
1664 nomem = new_NoMem();
1666 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1667 new_cmp_left, new_cmp_right, nomem, pnc);
1668 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1673 static ir_node *create_Switch(ir_node *node)
1675 ir_graph *irg = current_ir_graph;
1676 dbg_info *dbgi = get_irn_dbg_info(node);
1677 ir_node *block = be_transform_node(get_nodes_block(node));
1678 ir_node *sel = get_Cond_selector(node);
1679 ir_node *new_sel = be_transform_node(sel);
1681 int switch_min = INT_MAX;
1682 const ir_edge_t *edge;
1684 /* determine the smallest switch case value */
1685 foreach_out_edge(node, edge) {
1686 ir_node *proj = get_edge_src_irn(edge);
1687 int pn = get_Proj_proj(proj);
1692 if (switch_min != 0) {
1693 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1695 /* if smallest switch case is not 0 we need an additional sub */
1696 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1697 add_ia32_am_offs_int(new_sel, -switch_min);
1698 set_ia32_am_flavour(new_sel, ia32_am_OB);
1699 set_ia32_op_type(new_sel, ia32_AddrModeS);
1701 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1704 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1705 set_ia32_pncode(res, get_Cond_defaultProj(node));
1707 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1713 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1715 * @return The transformed node.
1717 static ir_node *gen_Cond(ir_node *node) {
1718 ir_node *block = be_transform_node(get_nodes_block(node));
1719 ir_graph *irg = current_ir_graph;
1720 dbg_info *dbgi = get_irn_dbg_info(node);
1721 ir_node *sel = get_Cond_selector(node);
1722 ir_mode *sel_mode = get_irn_mode(sel);
1723 ir_node *res = NULL;
1724 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1731 ir_node *nomem = new_NoMem();
1734 if (sel_mode != mode_b) {
1735 return create_Switch(node);
1738 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
1739 /* it's some mode_b value not a direct comparison -> create a testjmp */
1740 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
1741 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1745 cmp = get_Proj_pred(sel);
1746 cmp_a = get_Cmp_left(cmp);
1747 cmp_b = get_Cmp_right(cmp);
1748 cmp_mode = get_irn_mode(cmp_a);
1749 pnc = get_Proj_proj(sel);
1750 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1751 pnc |= ia32_pn_Cmp_Unsigned;
1754 if(mode_needs_gp_reg(cmp_mode)) {
1755 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b);
1757 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1762 new_cmp_a = be_transform_node(cmp_a);
1763 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1765 if (mode_is_float(cmp_mode)) {
1767 if (USE_SSE2(env_cg)) {
1768 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1770 set_ia32_commutative(res);
1771 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1772 set_ia32_ls_mode(res, cmp_mode);
1775 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1776 set_ia32_commutative(res);
1777 proj_eax = new_r_Proj(irg, block, res, mode_Iu,
1778 pn_ia32_vfCondJmp_temp_reg_eax);
1779 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1,
1783 assert(get_mode_size_bits(cmp_mode) == 32);
1784 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1785 new_cmp_a, new_cmp_b, nomem, pnc);
1786 set_ia32_commutative(res);
1787 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1790 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1798 * Transforms a CopyB node.
1800 * @return The transformed node.
1802 static ir_node *gen_CopyB(ir_node *node) {
1803 ir_node *block = be_transform_node(get_nodes_block(node));
1804 ir_node *src = get_CopyB_src(node);
1805 ir_node *new_src = be_transform_node(src);
1806 ir_node *dst = get_CopyB_dst(node);
1807 ir_node *new_dst = be_transform_node(dst);
1808 ir_node *mem = get_CopyB_mem(node);
1809 ir_node *new_mem = be_transform_node(mem);
1810 ir_node *res = NULL;
1811 ir_graph *irg = current_ir_graph;
1812 dbg_info *dbgi = get_irn_dbg_info(node);
1813 int size = get_type_size_bytes(get_CopyB_type(node));
1814 ir_mode *dst_mode = get_irn_mode(dst);
1815 ir_mode *src_mode = get_irn_mode(src);
1819 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1820 /* then we need the size explicitly in ECX. */
1821 if (size >= 32 * 4) {
1822 rem = size & 0x3; /* size % 4 */
1825 res = new_rd_ia32_Const(dbgi, irg, block);
1826 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1827 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1829 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1830 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1832 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1833 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1834 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1835 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1836 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1839 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1840 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1842 /* ok: now attach Proj's because movsd will destroy esi and edi */
1843 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1844 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1845 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1848 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1854 ir_node *gen_be_Copy(ir_node *node)
1856 ir_node *result = be_duplicate_node(node);
1857 ir_mode *mode = get_irn_mode(result);
1859 if (mode_needs_gp_reg(mode)) {
1860 set_irn_mode(result, mode_Iu);
1867 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1868 dbg_info *dbgi, ir_node *block)
1870 ir_graph *irg = current_ir_graph;
1871 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1872 ir_node *nomem = new_rd_NoMem(irg);
1873 ir_node *new_cmp_left;
1874 ir_node *new_cmp_right;
1877 /* can we use a test instruction? */
1878 if(cmp_right == NULL || is_Const_0(cmp_right)) {
1879 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1880 if(is_And(cmp_left) &&
1881 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1882 ir_node *and_left = get_And_left(cmp_left);
1883 ir_node *and_right = get_And_right(cmp_left);
1885 new_cmp_left = be_transform_node(and_left);
1886 new_cmp_right = create_immediate_or_transform(and_right, 0);
1888 new_cmp_left = be_transform_node(cmp_left);
1889 new_cmp_right = be_transform_node(cmp_left);
1892 res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
1893 new_cmp_left, new_cmp_right, nomem, pnc);
1894 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1899 new_cmp_left = be_transform_node(cmp_left);
1900 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1901 res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
1902 new_cmp_left, new_cmp_right, nomem, pnc);
1907 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1908 ir_node *val_true, ir_node *val_false,
1909 dbg_info *dbgi, ir_node *block)
1911 ir_graph *irg = current_ir_graph;
1912 ir_node *new_val_true = be_transform_node(val_true);
1913 ir_node *new_val_false = be_transform_node(val_false);
1914 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1915 ir_node *nomem = new_NoMem();
1916 ir_node *new_cmp_left;
1917 ir_node *new_cmp_right;
1920 /* cmovs with unknowns are pointless... */
1921 if(is_Unknown(val_true)) {
1922 #ifdef DEBUG_libfirm
1923 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1925 return new_val_false;
1927 if(is_Unknown(val_false)) {
1928 #ifdef DEBUG_libfirm
1929 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1931 return new_val_true;
1934 /* can we use a test instruction? */
1935 if(is_Const_0(cmp_right)) {
1936 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1937 if(is_And(cmp_left) &&
1938 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1939 ir_node *and_left = get_And_left(cmp_left);
1940 ir_node *and_right = get_And_right(cmp_left);
1942 new_cmp_left = be_transform_node(and_left);
1943 new_cmp_right = create_immediate_or_transform(and_right, 0);
1945 new_cmp_left = be_transform_node(cmp_left);
1946 new_cmp_right = be_transform_node(cmp_left);
1949 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, block, noreg, noreg,
1950 new_cmp_left, new_cmp_right, nomem,
1951 new_val_true, new_val_false, pnc);
1952 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1957 new_cmp_left = be_transform_node(cmp_left);
1958 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1960 res = new_rd_ia32_CmpCMov(dbgi, irg, block, noreg, noreg, new_cmp_left,
1961 new_cmp_right, nomem, new_val_true, new_val_false,
1963 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1970 * Transforms a Psi node into CMov.
1972 * @return The transformed node.
1974 static ir_node *gen_Psi(ir_node *node) {
1975 ir_node *psi_true = get_Psi_val(node, 0);
1976 ir_node *psi_default = get_Psi_default(node);
1977 ia32_code_gen_t *cg = env_cg;
1978 ir_node *cond = get_Psi_cond(node, 0);
1979 ir_node *block = be_transform_node(get_nodes_block(node));
1980 dbg_info *dbgi = get_irn_dbg_info(node);
1987 assert(get_Psi_n_conds(node) == 1);
1988 assert(get_irn_mode(cond) == mode_b);
1990 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
1991 /* a mode_b value, we have to compare it against 0 */
1993 cmp_right = new_Const_long(mode_Iu, 0);
1997 ir_node *cmp = get_Proj_pred(cond);
1999 cmp_left = get_Cmp_left(cmp);
2000 cmp_right = get_Cmp_right(cmp);
2001 cmp_mode = get_irn_mode(cmp_left);
2002 pnc = get_Proj_proj(cond);
2004 assert(!mode_is_float(cmp_mode));
2006 if (!mode_is_signed(cmp_mode)) {
2007 pnc |= ia32_pn_Cmp_Unsigned;
2011 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2012 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2013 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2014 pnc = get_negated_pnc(pnc, cmp_mode);
2015 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2017 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
2020 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2026 * Following conversion rules apply:
2030 * 1) n bit -> m bit n > m (downscale)
2032 * 2) n bit -> m bit n == m (sign change)
2034 * 3) n bit -> m bit n < m (upscale)
2035 * a) source is signed: movsx
2036 * b) source is unsigned: and with lower bits sets
2040 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2044 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2048 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2049 * x87 is mode_E internally, conversions happen only at load and store
2050 * in non-strict semantic
2054 * Create a conversion from x87 state register to general purpose.
2056 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2057 ir_node *block = be_transform_node(get_nodes_block(node));
2058 ir_node *op = get_Conv_op(node);
2059 ir_node *new_op = be_transform_node(op);
2060 ia32_code_gen_t *cg = env_cg;
2061 ir_graph *irg = current_ir_graph;
2062 dbg_info *dbgi = get_irn_dbg_info(node);
2063 ir_node *noreg = ia32_new_NoReg_gp(cg);
2064 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2065 ir_node *fist, *load;
2068 fist = new_rd_ia32_vfist(dbgi, irg, block,
2069 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2071 set_irn_pinned(fist, op_pin_state_floats);
2072 set_ia32_use_frame(fist);
2073 set_ia32_op_type(fist, ia32_AddrModeD);
2074 set_ia32_am_flavour(fist, ia32_am_B);
2075 set_ia32_ls_mode(fist, mode_Iu);
2076 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2079 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2081 set_irn_pinned(load, op_pin_state_floats);
2082 set_ia32_use_frame(load);
2083 set_ia32_op_type(load, ia32_AddrModeS);
2084 set_ia32_am_flavour(load, ia32_am_B);
2085 set_ia32_ls_mode(load, mode_Iu);
2086 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2088 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2092 * Create a conversion from general purpose to x87 register
2094 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2095 ir_node *block = be_transform_node(get_nodes_block(node));
2096 ir_node *op = get_Conv_op(node);
2097 ir_node *new_op = be_transform_node(op);
2098 ir_graph *irg = current_ir_graph;
2099 dbg_info *dbgi = get_irn_dbg_info(node);
2100 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2101 ir_node *nomem = new_NoMem();
2102 ir_node *fild, *store;
2105 /* first convert to 32 bit if necessary */
2106 src_bits = get_mode_size_bits(src_mode);
2107 if (src_bits == 8) {
2108 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2109 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2110 set_ia32_ls_mode(new_op, src_mode);
2111 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2112 } else if (src_bits < 32) {
2113 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2114 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2115 set_ia32_ls_mode(new_op, src_mode);
2116 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2120 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2122 set_ia32_use_frame(store);
2123 set_ia32_op_type(store, ia32_AddrModeD);
2124 set_ia32_am_flavour(store, ia32_am_OB);
2125 set_ia32_ls_mode(store, mode_Iu);
2128 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2130 set_ia32_use_frame(fild);
2131 set_ia32_op_type(fild, ia32_AddrModeS);
2132 set_ia32_am_flavour(fild, ia32_am_OB);
2133 set_ia32_ls_mode(fild, mode_Iu);
2135 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2138 static ir_node *create_Strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
2141 ir_node *block = get_nodes_block(node);
2142 ir_graph *irg = current_ir_graph;
2143 dbg_info *dbgi = get_irn_dbg_info(node);
2144 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2145 ir_node *nomem = new_NoMem();
2146 int src_bits = get_mode_size_bits(src_mode);
2147 int tgt_bits = get_mode_size_bits(tgt_mode);
2148 ir_node *frame = get_irg_frame(irg);
2149 ir_mode *smaller_mode;
2150 ir_node *store, *load;
2153 if(src_bits <= tgt_bits)
2154 smaller_mode = src_mode;
2156 smaller_mode = tgt_mode;
2158 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2160 set_ia32_use_frame(store);
2161 set_ia32_op_type(store, ia32_AddrModeD);
2162 set_ia32_am_flavour(store, ia32_am_OB);
2164 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2166 set_ia32_use_frame(load);
2167 set_ia32_op_type(load, ia32_AddrModeS);
2168 set_ia32_am_flavour(load, ia32_am_OB);
2170 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2175 * Transforms a Conv node.
2177 * @return The created ia32 Conv node
2179 static ir_node *gen_Conv(ir_node *node) {
2180 ir_node *block = be_transform_node(get_nodes_block(node));
2181 ir_node *op = get_Conv_op(node);
2182 ir_node *new_op = be_transform_node(op);
2183 ir_graph *irg = current_ir_graph;
2184 dbg_info *dbgi = get_irn_dbg_info(node);
2185 ir_mode *src_mode = get_irn_mode(op);
2186 ir_mode *tgt_mode = get_irn_mode(node);
2187 int src_bits = get_mode_size_bits(src_mode);
2188 int tgt_bits = get_mode_size_bits(tgt_mode);
2189 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2190 ir_node *nomem = new_rd_NoMem(irg);
2193 if (src_mode == mode_b) {
2194 assert(mode_is_int(tgt_mode));
2195 /* nothing to do, we already model bools as 0/1 ints */
2199 if (src_mode == tgt_mode) {
2200 if (get_Conv_strict(node)) {
2201 if (USE_SSE2(env_cg)) {
2202 /* when we are in SSE mode, we can kill all strict no-op conversion */
2206 /* this should be optimized already, but who knows... */
2207 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2208 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2213 if (mode_is_float(src_mode)) {
2214 /* we convert from float ... */
2215 if (mode_is_float(tgt_mode)) {
2216 if(src_mode == mode_E && tgt_mode == mode_D
2217 && !get_Conv_strict(node)) {
2218 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2223 if (USE_SSE2(env_cg)) {
2224 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2225 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2226 set_ia32_ls_mode(res, tgt_mode);
2228 // Matze: TODO what about strict convs?
2229 if(get_Conv_strict(node)) {
2230 res = create_Strict_conv(src_mode, tgt_mode, new_op);
2231 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2234 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2239 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2240 if (USE_SSE2(env_cg)) {
2241 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2242 set_ia32_ls_mode(res, src_mode);
2244 return gen_x87_fp_to_gp(node);
2248 /* we convert from int ... */
2249 if (mode_is_float(tgt_mode)) {
2252 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2253 if (USE_SSE2(env_cg)) {
2254 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2255 set_ia32_ls_mode(res, tgt_mode);
2256 if(src_bits == 32) {
2257 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2260 return gen_x87_gp_to_fp(node, src_mode);
2262 } else if(tgt_mode == mode_b) {
2264 res = create_set(pn_Cmp_Lg, op, NULL, dbgi, block);
2267 ir_mode *smaller_mode;
2270 if (src_bits == tgt_bits) {
2271 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2275 if (src_bits < tgt_bits) {
2276 smaller_mode = src_mode;
2277 smaller_bits = src_bits;
2279 smaller_mode = tgt_mode;
2280 smaller_bits = tgt_bits;
2283 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2284 if (smaller_bits == 8) {
2285 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2286 set_ia32_ls_mode(res, smaller_mode);
2288 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2289 set_ia32_ls_mode(res, smaller_mode);
2291 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2295 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2301 int check_immediate_constraint(long val, char immediate_constraint_type)
2303 switch (immediate_constraint_type) {
2307 return val >= 0 && val <= 32;
2309 return val >= 0 && val <= 63;
2311 return val >= -128 && val <= 127;
2313 return val == 0xff || val == 0xffff;
2315 return val >= 0 && val <= 3;
2317 return val >= 0 && val <= 255;
2319 return val >= 0 && val <= 127;
2323 panic("Invalid immediate constraint found");
2328 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2331 tarval *offset = NULL;
2332 int offset_sign = 0;
2334 ir_entity *symconst_ent = NULL;
2335 int symconst_sign = 0;
2337 ir_node *cnst = NULL;
2338 ir_node *symconst = NULL;
2344 mode = get_irn_mode(node);
2345 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2346 !mode_is_reference(mode)) {
2350 if(is_Minus(node)) {
2352 node = get_Minus_op(node);
2355 if(is_Const(node)) {
2358 offset_sign = minus;
2359 } else if(is_SymConst(node)) {
2362 symconst_sign = minus;
2363 } else if(is_Add(node)) {
2364 ir_node *left = get_Add_left(node);
2365 ir_node *right = get_Add_right(node);
2366 if(is_Const(left) && is_SymConst(right)) {
2369 symconst_sign = minus;
2370 offset_sign = minus;
2371 } else if(is_SymConst(left) && is_Const(right)) {
2374 symconst_sign = minus;
2375 offset_sign = minus;
2377 } else if(is_Sub(node)) {
2378 ir_node *left = get_Sub_left(node);
2379 ir_node *right = get_Sub_right(node);
2380 if(is_Const(left) && is_SymConst(right)) {
2383 symconst_sign = !minus;
2384 offset_sign = minus;
2385 } else if(is_SymConst(left) && is_Const(right)) {
2388 symconst_sign = minus;
2389 offset_sign = !minus;
2396 offset = get_Const_tarval(cnst);
2397 if(tarval_is_long(offset)) {
2398 val = get_tarval_long(offset);
2399 } else if(tarval_is_null(offset)) {
2402 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2407 if(!check_immediate_constraint(val, immediate_constraint_type))
2410 if(symconst != NULL) {
2411 if(immediate_constraint_type != 0) {
2412 /* we need full 32bits for symconsts */
2416 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2418 symconst_ent = get_SymConst_entity(symconst);
2420 if(cnst == NULL && symconst == NULL)
2423 if(offset_sign && offset != NULL) {
2424 offset = tarval_neg(offset);
2427 irg = current_ir_graph;
2428 dbgi = get_irn_dbg_info(node);
2429 block = get_irg_start_block(irg);
2430 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2432 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2434 /* make sure we don't schedule stuff before the barrier */
2435 add_irn_dep(res, get_irg_frame(irg));
2441 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2443 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2444 if (new_node == NULL) {
2445 new_node = be_transform_node(node);
2450 typedef struct constraint_t constraint_t;
2451 struct constraint_t {
2454 const arch_register_req_t **out_reqs;
2456 const arch_register_req_t *req;
2457 unsigned immediate_possible;
2458 char immediate_type;
2461 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2463 int immediate_possible = 0;
2464 char immediate_type = 0;
2465 unsigned limited = 0;
2466 const arch_register_class_t *cls = NULL;
2468 struct obstack *obst;
2469 arch_register_req_t *req;
2470 unsigned *limited_ptr;
2474 /* TODO: replace all the asserts with nice error messages */
2476 printf("Constraint: %s\n", c);
2486 assert(cls == NULL ||
2487 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2488 cls = &ia32_reg_classes[CLASS_ia32_gp];
2489 limited |= 1 << REG_EAX;
2492 assert(cls == NULL ||
2493 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2494 cls = &ia32_reg_classes[CLASS_ia32_gp];
2495 limited |= 1 << REG_EBX;
2498 assert(cls == NULL ||
2499 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2500 cls = &ia32_reg_classes[CLASS_ia32_gp];
2501 limited |= 1 << REG_ECX;
2504 assert(cls == NULL ||
2505 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2506 cls = &ia32_reg_classes[CLASS_ia32_gp];
2507 limited |= 1 << REG_EDX;
2510 assert(cls == NULL ||
2511 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2512 cls = &ia32_reg_classes[CLASS_ia32_gp];
2513 limited |= 1 << REG_EDI;
2516 assert(cls == NULL ||
2517 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2518 cls = &ia32_reg_classes[CLASS_ia32_gp];
2519 limited |= 1 << REG_ESI;
2522 case 'q': /* q means lower part of the regs only, this makes no
2523 * difference to Q for us (we only assigne whole registers) */
2524 assert(cls == NULL ||
2525 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2526 cls = &ia32_reg_classes[CLASS_ia32_gp];
2527 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2531 assert(cls == NULL ||
2532 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2533 cls = &ia32_reg_classes[CLASS_ia32_gp];
2534 limited |= 1 << REG_EAX | 1 << REG_EDX;
2537 assert(cls == NULL ||
2538 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2539 cls = &ia32_reg_classes[CLASS_ia32_gp];
2540 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2541 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2548 assert(cls == NULL);
2549 cls = &ia32_reg_classes[CLASS_ia32_gp];
2555 /* TODO: mark values so the x87 simulator knows about t and u */
2556 assert(cls == NULL);
2557 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2562 assert(cls == NULL);
2563 /* TODO: check that sse2 is supported */
2564 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2574 assert(!immediate_possible);
2575 immediate_possible = 1;
2576 immediate_type = *c;
2580 assert(!immediate_possible);
2581 immediate_possible = 1;
2585 assert(!immediate_possible && cls == NULL);
2586 immediate_possible = 1;
2587 cls = &ia32_reg_classes[CLASS_ia32_gp];
2600 assert(constraint->is_in && "can only specify same constraint "
2603 sscanf(c, "%d%n", &same_as, &p);
2610 case 'E': /* no float consts yet */
2611 case 'F': /* no float consts yet */
2612 case 's': /* makes no sense on x86 */
2613 case 'X': /* we can't support that in firm */
2617 case '<': /* no autodecrement on x86 */
2618 case '>': /* no autoincrement on x86 */
2619 case 'C': /* sse constant not supported yet */
2620 case 'G': /* 80387 constant not supported yet */
2621 case 'y': /* we don't support mmx registers yet */
2622 case 'Z': /* not available in 32 bit mode */
2623 case 'e': /* not available in 32 bit mode */
2624 assert(0 && "asm constraint not supported");
2627 assert(0 && "unknown asm constraint found");
2634 const arch_register_req_t *other_constr;
2636 assert(cls == NULL && "same as and register constraint not supported");
2637 assert(!immediate_possible && "same as and immediate constraint not "
2639 assert(same_as < constraint->n_outs && "wrong constraint number in "
2640 "same_as constraint");
2642 other_constr = constraint->out_reqs[same_as];
2644 req = obstack_alloc(obst, sizeof(req[0]));
2645 req->cls = other_constr->cls;
2646 req->type = arch_register_req_type_should_be_same;
2647 req->limited = NULL;
2648 req->other_same = pos;
2649 req->other_different = -1;
2651 /* switch constraints. This is because in firm we have same_as
2652 * constraints on the output constraints while in the gcc asm syntax
2653 * they are specified on the input constraints */
2654 constraint->req = other_constr;
2655 constraint->out_reqs[same_as] = req;
2656 constraint->immediate_possible = 0;
2660 if(immediate_possible && cls == NULL) {
2661 cls = &ia32_reg_classes[CLASS_ia32_gp];
2663 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2664 assert(cls != NULL);
2666 if(immediate_possible) {
2667 assert(constraint->is_in
2668 && "imeediates make no sense for output constraints");
2670 /* todo: check types (no float input on 'r' constrainted in and such... */
2672 irg = current_ir_graph;
2673 obst = get_irg_obstack(irg);
2676 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2677 limited_ptr = (unsigned*) (req+1);
2679 req = obstack_alloc(obst, sizeof(req[0]));
2681 memset(req, 0, sizeof(req[0]));
2684 req->type = arch_register_req_type_limited;
2685 *limited_ptr = limited;
2686 req->limited = limited_ptr;
2688 req->type = arch_register_req_type_normal;
2692 constraint->req = req;
2693 constraint->immediate_possible = immediate_possible;
2694 constraint->immediate_type = immediate_type;
2698 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2705 panic("Clobbers not supported yet");
2708 ir_node *gen_ASM(ir_node *node)
2711 ir_graph *irg = current_ir_graph;
2712 ir_node *block = be_transform_node(get_nodes_block(node));
2713 dbg_info *dbgi = get_irn_dbg_info(node);
2720 ia32_asm_attr_t *attr;
2721 const arch_register_req_t **out_reqs;
2722 const arch_register_req_t **in_reqs;
2723 struct obstack *obst;
2724 constraint_t parsed_constraint;
2726 /* assembler could contain float statements */
2729 /* transform inputs */
2730 arity = get_irn_arity(node);
2731 in = alloca(arity * sizeof(in[0]));
2732 memset(in, 0, arity * sizeof(in[0]));
2734 n_outs = get_ASM_n_output_constraints(node);
2735 n_clobbers = get_ASM_n_clobbers(node);
2736 out_arity = n_outs + n_clobbers;
2738 /* construct register constraints */
2739 obst = get_irg_obstack(irg);
2740 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2741 parsed_constraint.out_reqs = out_reqs;
2742 parsed_constraint.n_outs = n_outs;
2743 parsed_constraint.is_in = 0;
2744 for(i = 0; i < out_arity; ++i) {
2748 const ir_asm_constraint *constraint;
2749 constraint = & get_ASM_output_constraints(node) [i];
2750 c = get_id_str(constraint->constraint);
2751 parse_asm_constraint(i, &parsed_constraint, c);
2753 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2754 c = get_id_str(glob_id);
2755 parse_clobber(node, i, &parsed_constraint, c);
2757 out_reqs[i] = parsed_constraint.req;
2760 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2761 parsed_constraint.is_in = 1;
2762 for(i = 0; i < arity; ++i) {
2763 const ir_asm_constraint *constraint;
2767 constraint = & get_ASM_input_constraints(node) [i];
2768 constr_id = constraint->constraint;
2769 c = get_id_str(constr_id);
2770 parse_asm_constraint(i, &parsed_constraint, c);
2771 in_reqs[i] = parsed_constraint.req;
2773 if(parsed_constraint.immediate_possible) {
2774 ir_node *pred = get_irn_n(node, i);
2775 char imm_type = parsed_constraint.immediate_type;
2776 ir_node *immediate = try_create_Immediate(pred, imm_type);
2778 if(immediate != NULL) {
2784 /* transform inputs */
2785 for(i = 0; i < arity; ++i) {
2787 ir_node *transformed;
2792 pred = get_irn_n(node, i);
2793 transformed = be_transform_node(pred);
2794 in[i] = transformed;
2797 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2799 generic_attr = get_irn_generic_attr(res);
2800 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2801 attr->asm_text = get_ASM_text(node);
2802 set_ia32_out_req_all(res, out_reqs);
2803 set_ia32_in_req_all(res, in_reqs);
2805 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2810 /********************************************
2813 * | |__ ___ _ __ ___ __| | ___ ___
2814 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2815 * | |_) | __/ | | | (_) | (_| | __/\__ \
2816 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2818 ********************************************/
2820 static ir_node *gen_be_StackParam(ir_node *node) {
2821 ir_node *block = be_transform_node(get_nodes_block(node));
2822 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2823 ir_node *new_ptr = be_transform_node(ptr);
2824 ir_node *new_op = NULL;
2825 ir_graph *irg = current_ir_graph;
2826 dbg_info *dbgi = get_irn_dbg_info(node);
2827 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2828 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2829 ir_mode *load_mode = get_irn_mode(node);
2830 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2834 if (mode_is_float(load_mode)) {
2836 if (USE_SSE2(env_cg)) {
2837 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2838 pn_res = pn_ia32_xLoad_res;
2839 proj_mode = mode_xmm;
2841 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2842 pn_res = pn_ia32_vfld_res;
2843 proj_mode = mode_vfp;
2846 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2847 proj_mode = mode_Iu;
2848 pn_res = pn_ia32_Load_res;
2851 set_irn_pinned(new_op, op_pin_state_floats);
2852 set_ia32_frame_ent(new_op, ent);
2853 set_ia32_use_frame(new_op);
2855 set_ia32_op_type(new_op, ia32_AddrModeS);
2856 set_ia32_am_flavour(new_op, ia32_am_B);
2857 set_ia32_ls_mode(new_op, load_mode);
2858 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2860 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2862 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2866 * Transforms a FrameAddr into an ia32 Add.
2868 static ir_node *gen_be_FrameAddr(ir_node *node) {
2869 ir_node *block = be_transform_node(get_nodes_block(node));
2870 ir_node *op = be_get_FrameAddr_frame(node);
2871 ir_node *new_op = be_transform_node(op);
2872 ir_graph *irg = current_ir_graph;
2873 dbg_info *dbgi = get_irn_dbg_info(node);
2874 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2877 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2878 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2879 set_ia32_use_frame(res);
2880 set_ia32_am_flavour(res, ia32_am_OB);
2882 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2888 * Transforms a FrameLoad into an ia32 Load.
2890 static ir_node *gen_be_FrameLoad(ir_node *node) {
2891 ir_node *block = be_transform_node(get_nodes_block(node));
2892 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2893 ir_node *new_mem = be_transform_node(mem);
2894 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2895 ir_node *new_ptr = be_transform_node(ptr);
2896 ir_node *new_op = NULL;
2897 ir_graph *irg = current_ir_graph;
2898 dbg_info *dbgi = get_irn_dbg_info(node);
2899 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2900 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2901 ir_mode *mode = get_type_mode(get_entity_type(ent));
2902 ir_node *projs[pn_Load_max];
2904 ia32_collect_Projs(node, projs, pn_Load_max);
2906 if (mode_is_float(mode)) {
2908 if (USE_SSE2(env_cg)) {
2909 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2912 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2916 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2919 set_irn_pinned(new_op, op_pin_state_floats);
2920 set_ia32_frame_ent(new_op, ent);
2921 set_ia32_use_frame(new_op);
2923 set_ia32_op_type(new_op, ia32_AddrModeS);
2924 set_ia32_am_flavour(new_op, ia32_am_B);
2925 set_ia32_ls_mode(new_op, mode);
2926 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2928 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2935 * Transforms a FrameStore into an ia32 Store.
2937 static ir_node *gen_be_FrameStore(ir_node *node) {
2938 ir_node *block = be_transform_node(get_nodes_block(node));
2939 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2940 ir_node *new_mem = be_transform_node(mem);
2941 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2942 ir_node *new_ptr = be_transform_node(ptr);
2943 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2944 ir_node *new_val = be_transform_node(val);
2945 ir_node *new_op = NULL;
2946 ir_graph *irg = current_ir_graph;
2947 dbg_info *dbgi = get_irn_dbg_info(node);
2948 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2949 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2950 ir_mode *mode = get_irn_mode(val);
2952 if (mode_is_float(mode)) {
2954 if (USE_SSE2(env_cg)) {
2955 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2957 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2959 } else if (get_mode_size_bits(mode) == 8) {
2960 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2962 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2965 set_ia32_frame_ent(new_op, ent);
2966 set_ia32_use_frame(new_op);
2968 set_ia32_op_type(new_op, ia32_AddrModeD);
2969 set_ia32_am_flavour(new_op, ia32_am_B);
2970 set_ia32_ls_mode(new_op, mode);
2972 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2978 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2980 static ir_node *gen_be_Return(ir_node *node) {
2981 ir_graph *irg = current_ir_graph;
2982 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2983 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2984 ir_entity *ent = get_irg_entity(irg);
2985 ir_type *tp = get_entity_type(ent);
2990 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2991 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2994 int pn_ret_val, pn_ret_mem, arity, i;
2996 assert(ret_val != NULL);
2997 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
2998 return be_duplicate_node(node);
3001 res_type = get_method_res_type(tp, 0);
3003 if (! is_Primitive_type(res_type)) {
3004 return be_duplicate_node(node);
3007 mode = get_type_mode(res_type);
3008 if (! mode_is_float(mode)) {
3009 return be_duplicate_node(node);
3012 assert(get_method_n_ress(tp) == 1);
3014 pn_ret_val = get_Proj_proj(ret_val);
3015 pn_ret_mem = get_Proj_proj(ret_mem);
3017 /* get the Barrier */
3018 barrier = get_Proj_pred(ret_val);
3020 /* get result input of the Barrier */
3021 ret_val = get_irn_n(barrier, pn_ret_val);
3022 new_ret_val = be_transform_node(ret_val);
3024 /* get memory input of the Barrier */
3025 ret_mem = get_irn_n(barrier, pn_ret_mem);
3026 new_ret_mem = be_transform_node(ret_mem);
3028 frame = get_irg_frame(irg);
3030 dbgi = get_irn_dbg_info(barrier);
3031 block = be_transform_node(get_nodes_block(barrier));
3033 noreg = ia32_new_NoReg_gp(env_cg);
3035 /* store xmm0 onto stack */
3036 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
3037 set_ia32_ls_mode(sse_store, mode);
3038 set_ia32_op_type(sse_store, ia32_AddrModeD);
3039 set_ia32_use_frame(sse_store);
3040 set_ia32_am_flavour(sse_store, ia32_am_B);
3043 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
3044 set_ia32_ls_mode(fld, mode);
3045 set_ia32_op_type(fld, ia32_AddrModeS);
3046 set_ia32_use_frame(fld);
3047 set_ia32_am_flavour(fld, ia32_am_B);
3049 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3050 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3051 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3053 /* create a new barrier */
3054 arity = get_irn_arity(barrier);
3055 in = alloca(arity * sizeof(in[0]));
3056 for (i = 0; i < arity; ++i) {
3059 if (i == pn_ret_val) {
3061 } else if (i == pn_ret_mem) {
3064 ir_node *in = get_irn_n(barrier, i);
3065 new_in = be_transform_node(in);
3070 new_barrier = new_ir_node(dbgi, irg, block,
3071 get_irn_op(barrier), get_irn_mode(barrier),
3073 copy_node_attr(barrier, new_barrier);
3074 be_duplicate_deps(barrier, new_barrier);
3075 be_set_transformed_node(barrier, new_barrier);
3076 mark_irn_visited(barrier);
3078 /* transform normally */
3079 return be_duplicate_node(node);
3083 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3085 static ir_node *gen_be_AddSP(ir_node *node) {
3086 ir_node *block = be_transform_node(get_nodes_block(node));
3087 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3089 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3090 ir_node *new_sp = be_transform_node(sp);
3091 ir_graph *irg = current_ir_graph;
3092 dbg_info *dbgi = get_irn_dbg_info(node);
3093 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3094 ir_node *nomem = new_NoMem();
3097 new_sz = create_immediate_or_transform(sz, 0);
3099 /* ia32 stack grows in reverse direction, make a SubSP */
3100 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3102 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3103 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3109 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3111 static ir_node *gen_be_SubSP(ir_node *node) {
3112 ir_node *block = be_transform_node(get_nodes_block(node));
3113 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3115 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3116 ir_node *new_sp = be_transform_node(sp);
3117 ir_graph *irg = current_ir_graph;
3118 dbg_info *dbgi = get_irn_dbg_info(node);
3119 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3120 ir_node *nomem = new_NoMem();
3123 new_sz = create_immediate_or_transform(sz, 0);
3125 /* ia32 stack grows in reverse direction, make an AddSP */
3126 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3127 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3128 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3134 * This function just sets the register for the Unknown node
3135 * as this is not done during register allocation because Unknown
3136 * is an "ignore" node.
3138 static ir_node *gen_Unknown(ir_node *node) {
3139 ir_mode *mode = get_irn_mode(node);
3141 if (mode_is_float(mode)) {
3143 if (USE_SSE2(env_cg))
3144 return ia32_new_Unknown_xmm(env_cg);
3146 return ia32_new_Unknown_vfp(env_cg);
3147 } else if (mode_needs_gp_reg(mode)) {
3148 return ia32_new_Unknown_gp(env_cg);
3150 assert(0 && "unsupported Unknown-Mode");
3157 * Change some phi modes
3159 static ir_node *gen_Phi(ir_node *node) {
3160 ir_node *block = be_transform_node(get_nodes_block(node));
3161 ir_graph *irg = current_ir_graph;
3162 dbg_info *dbgi = get_irn_dbg_info(node);
3163 ir_mode *mode = get_irn_mode(node);
3166 if(mode_needs_gp_reg(mode)) {
3167 /* we shouldn't have any 64bit stuff around anymore */
3168 assert(get_mode_size_bits(mode) <= 32);
3169 /* all integer operations are on 32bit registers now */
3171 } else if(mode_is_float(mode)) {
3172 if (USE_SSE2(env_cg)) {
3179 /* phi nodes allow loops, so we use the old arguments for now
3180 * and fix this later */
3181 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3182 copy_node_attr(node, phi);
3183 be_duplicate_deps(node, phi);
3185 be_set_transformed_node(node, phi);
3186 be_enqueue_preds(node);
3191 /**********************************************************************
3194 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3195 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3196 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3197 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3199 **********************************************************************/
3201 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3203 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3206 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3207 ir_node *val, ir_node *mem);
3210 * Transforms a lowered Load into a "real" one.
3212 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3213 ir_node *block = be_transform_node(get_nodes_block(node));
3214 ir_node *ptr = get_irn_n(node, 0);
3215 ir_node *new_ptr = be_transform_node(ptr);
3216 ir_node *mem = get_irn_n(node, 1);
3217 ir_node *new_mem = be_transform_node(mem);
3218 ir_graph *irg = current_ir_graph;
3219 dbg_info *dbgi = get_irn_dbg_info(node);
3220 ir_mode *mode = get_ia32_ls_mode(node);
3221 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3225 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3226 lowering we have x87 nodes, so we need to enforce simulation.
3228 if (mode_is_float(mode)) {
3230 if (fp_unit == fp_x87)
3234 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3236 set_ia32_op_type(new_op, ia32_AddrModeS);
3237 set_ia32_am_flavour(new_op, ia32_am_OB);
3238 set_ia32_am_offs_int(new_op, 0);
3239 set_ia32_am_scale(new_op, 1);
3240 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3241 if (is_ia32_am_sc_sign(node))
3242 set_ia32_am_sc_sign(new_op);
3243 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3244 if (is_ia32_use_frame(node)) {
3245 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3246 set_ia32_use_frame(new_op);
3249 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3255 * Transforms a lowered Store into a "real" one.
3257 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3258 ir_node *block = be_transform_node(get_nodes_block(node));
3259 ir_node *ptr = get_irn_n(node, 0);
3260 ir_node *new_ptr = be_transform_node(ptr);
3261 ir_node *val = get_irn_n(node, 1);
3262 ir_node *new_val = be_transform_node(val);
3263 ir_node *mem = get_irn_n(node, 2);
3264 ir_node *new_mem = be_transform_node(mem);
3265 ir_graph *irg = current_ir_graph;
3266 dbg_info *dbgi = get_irn_dbg_info(node);
3267 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3268 ir_mode *mode = get_ia32_ls_mode(node);
3271 ia32_am_flavour_t am_flav = ia32_B;
3274 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3275 lowering we have x87 nodes, so we need to enforce simulation.
3277 if (mode_is_float(mode)) {
3279 if (fp_unit == fp_x87)
3283 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3285 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3287 add_ia32_am_offs_int(new_op, am_offs);
3290 set_ia32_op_type(new_op, ia32_AddrModeD);
3291 set_ia32_am_flavour(new_op, am_flav);
3292 set_ia32_ls_mode(new_op, mode);
3293 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3294 set_ia32_use_frame(new_op);
3296 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3303 * Transforms an ia32_l_XXX into a "real" XXX node
3305 * @param env The transformation environment
3306 * @return the created ia32 XXX node
3308 #define GEN_LOWERED_OP(op) \
3309 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3310 ir_mode *mode = get_irn_mode(node); \
3311 if (mode_is_float(mode)) \
3313 return gen_binop(node, get_binop_left(node), \
3314 get_binop_right(node), new_rd_ia32_##op,0); \
3317 #define GEN_LOWERED_x87_OP(op) \
3318 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3320 FORCE_x87(env_cg); \
3321 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3322 get_binop_right(node), new_rd_ia32_##op); \
3326 #define GEN_LOWERED_UNOP(op) \
3327 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3328 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3331 #define GEN_LOWERED_SHIFT_OP(op) \
3332 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3333 return gen_shift_binop(node, get_binop_left(node), \
3334 get_binop_right(node), new_rd_ia32_##op); \
3337 #define GEN_LOWERED_LOAD(op, fp_unit) \
3338 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3339 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3342 #define GEN_LOWERED_STORE(op, fp_unit) \
3343 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3344 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3351 GEN_LOWERED_OP(IMul)
3353 GEN_LOWERED_x87_OP(vfprem)
3354 GEN_LOWERED_x87_OP(vfmul)
3355 GEN_LOWERED_x87_OP(vfsub)
3357 GEN_LOWERED_UNOP(Neg)
3359 GEN_LOWERED_LOAD(vfild, fp_x87)
3360 GEN_LOWERED_LOAD(Load, fp_none)
3361 /*GEN_LOWERED_STORE(vfist, fp_x87)
3364 GEN_LOWERED_STORE(Store, fp_none)
3366 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3367 ir_node *block = be_transform_node(get_nodes_block(node));
3368 ir_node *left = get_binop_left(node);
3369 ir_node *new_left = be_transform_node(left);
3370 ir_node *right = get_binop_right(node);
3371 ir_node *new_right = be_transform_node(right);
3372 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3373 ir_graph *irg = current_ir_graph;
3374 dbg_info *dbgi = get_irn_dbg_info(node);
3375 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
3376 &ia32_fp_cw_regs[REG_FPCW]);
3379 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3380 new_right, new_NoMem(), fpcw);
3381 clear_ia32_commutative(vfdiv);
3382 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3384 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3392 * Transforms a l_MulS into a "real" MulS node.
3394 * @param env The transformation environment
3395 * @return the created ia32 Mul node
3397 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3398 ir_node *block = be_transform_node(get_nodes_block(node));
3399 ir_node *left = get_binop_left(node);
3400 ir_node *new_left = be_transform_node(left);
3401 ir_node *right = get_binop_right(node);
3402 ir_node *new_right = be_transform_node(right);
3403 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3404 ir_graph *irg = current_ir_graph;
3405 dbg_info *dbgi = get_irn_dbg_info(node);
3408 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3409 /* and then skip the result Proj, because all needed Projs are already there. */
3410 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3411 new_right, new_NoMem());
3412 clear_ia32_commutative(muls);
3413 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3415 /* check if EAX and EDX proj exist, add missing one */
3416 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3417 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3418 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3420 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3425 GEN_LOWERED_SHIFT_OP(Shl)
3426 GEN_LOWERED_SHIFT_OP(Shr)
3427 GEN_LOWERED_SHIFT_OP(Sar)
3430 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3431 * op1 - target to be shifted
3432 * op2 - contains bits to be shifted into target
3434 * Only op3 can be an immediate.
3436 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3437 ir_node *op2, ir_node *count)
3439 ir_node *block = be_transform_node(get_nodes_block(node));
3440 ir_node *new_op1 = be_transform_node(op1);
3441 ir_node *new_op2 = be_transform_node(op2);
3442 ir_node *new_count = be_transform_node(count);
3443 ir_node *new_op = NULL;
3444 ir_graph *irg = current_ir_graph;
3445 dbg_info *dbgi = get_irn_dbg_info(node);
3446 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3447 ir_node *nomem = new_NoMem();
3451 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3453 /* Check if immediate optimization is on and */
3454 /* if it's an operation with immediate. */
3455 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3457 /* Limit imm_op within range imm8 */
3459 tv = get_ia32_Immop_tarval(imm_op);
3462 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3463 set_ia32_Immop_tarval(imm_op, tv);
3470 /* integer operations */
3472 /* This is ShiftD with const */
3473 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3475 if (is_ia32_l_ShlD(node))
3476 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3477 new_op1, new_op2, noreg, nomem);
3479 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3480 new_op1, new_op2, noreg, nomem);
3481 copy_ia32_Immop_attr(new_op, imm_op);
3484 /* This is a normal ShiftD */
3485 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3486 if (is_ia32_l_ShlD(node))
3487 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3488 new_op1, new_op2, new_count, nomem);
3490 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3491 new_op1, new_op2, new_count, nomem);
3494 /* set AM support */
3495 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3497 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3499 set_ia32_emit_cl(new_op);
3504 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3505 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3506 get_irn_n(node, 1), get_irn_n(node, 2));
3509 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3510 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3511 get_irn_n(node, 1), get_irn_n(node, 2));
3515 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3517 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3518 ir_node *block = be_transform_node(get_nodes_block(node));
3519 ir_node *val = get_irn_n(node, 1);
3520 ir_node *new_val = be_transform_node(val);
3521 ia32_code_gen_t *cg = env_cg;
3522 ir_node *res = NULL;
3523 ir_graph *irg = current_ir_graph;
3525 ir_node *noreg, *new_ptr, *new_mem;
3532 mem = get_irn_n(node, 2);
3533 new_mem = be_transform_node(mem);
3534 ptr = get_irn_n(node, 0);
3535 new_ptr = be_transform_node(ptr);
3536 noreg = ia32_new_NoReg_gp(cg);
3537 dbgi = get_irn_dbg_info(node);
3539 /* Store x87 -> MEM */
3540 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3541 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3542 set_ia32_use_frame(res);
3543 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3544 set_ia32_am_flavour(res, ia32_B);
3545 set_ia32_op_type(res, ia32_AddrModeD);
3547 /* Load MEM -> SSE */
3548 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3549 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3550 set_ia32_use_frame(res);
3551 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3552 set_ia32_am_flavour(res, ia32_B);
3553 set_ia32_op_type(res, ia32_AddrModeS);
3554 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3560 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3562 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3563 ir_node *block = be_transform_node(get_nodes_block(node));
3564 ir_node *val = get_irn_n(node, 1);
3565 ir_node *new_val = be_transform_node(val);
3566 ia32_code_gen_t *cg = env_cg;
3567 ir_graph *irg = current_ir_graph;
3568 ir_node *res = NULL;
3569 ir_entity *fent = get_ia32_frame_ent(node);
3570 ir_mode *lsmode = get_ia32_ls_mode(node);
3572 ir_node *noreg, *new_ptr, *new_mem;
3576 if (! USE_SSE2(cg)) {
3577 /* SSE unit is not used -> skip this node. */
3581 ptr = get_irn_n(node, 0);
3582 new_ptr = be_transform_node(ptr);
3583 mem = get_irn_n(node, 2);
3584 new_mem = be_transform_node(mem);
3585 noreg = ia32_new_NoReg_gp(cg);
3586 dbgi = get_irn_dbg_info(node);
3588 /* Store SSE -> MEM */
3589 if (is_ia32_xLoad(skip_Proj(new_val))) {
3590 ir_node *ld = skip_Proj(new_val);
3592 /* we can vfld the value directly into the fpu */
3593 fent = get_ia32_frame_ent(ld);
3594 ptr = get_irn_n(ld, 0);
3595 offs = get_ia32_am_offs_int(ld);
3597 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3598 set_ia32_frame_ent(res, fent);
3599 set_ia32_use_frame(res);
3600 set_ia32_ls_mode(res, lsmode);
3601 set_ia32_am_flavour(res, ia32_B);
3602 set_ia32_op_type(res, ia32_AddrModeD);
3606 /* Load MEM -> x87 */
3607 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3608 set_ia32_frame_ent(res, fent);
3609 set_ia32_use_frame(res);
3610 add_ia32_am_offs_int(res, offs);
3611 set_ia32_am_flavour(res, ia32_B);
3612 set_ia32_op_type(res, ia32_AddrModeS);
3613 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3618 /*********************************************************
3621 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3622 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3623 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3624 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3626 *********************************************************/
3629 * the BAD transformer.
3631 static ir_node *bad_transform(ir_node *node) {
3632 panic("No transform function for %+F available.\n", node);
3637 * Transform the Projs of an AddSP.
3639 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3640 ir_node *block = be_transform_node(get_nodes_block(node));
3641 ir_node *pred = get_Proj_pred(node);
3642 ir_node *new_pred = be_transform_node(pred);
3643 ir_graph *irg = current_ir_graph;
3644 dbg_info *dbgi = get_irn_dbg_info(node);
3645 long proj = get_Proj_proj(node);
3647 if (proj == pn_be_AddSP_res) {
3648 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3649 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3651 } else if (proj == pn_be_AddSP_M) {
3652 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3656 return new_rd_Unknown(irg, get_irn_mode(node));
3660 * Transform the Projs of a SubSP.
3662 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3663 ir_node *block = be_transform_node(get_nodes_block(node));
3664 ir_node *pred = get_Proj_pred(node);
3665 ir_node *new_pred = be_transform_node(pred);
3666 ir_graph *irg = current_ir_graph;
3667 dbg_info *dbgi = get_irn_dbg_info(node);
3668 long proj = get_Proj_proj(node);
3670 if (proj == pn_be_SubSP_res) {
3671 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3672 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3674 } else if (proj == pn_be_SubSP_M) {
3675 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3679 return new_rd_Unknown(irg, get_irn_mode(node));
3683 * Transform and renumber the Projs from a Load.
3685 static ir_node *gen_Proj_Load(ir_node *node) {
3686 ir_node *block = be_transform_node(get_nodes_block(node));
3687 ir_node *pred = get_Proj_pred(node);
3688 ir_node *new_pred = be_transform_node(pred);
3689 ir_graph *irg = current_ir_graph;
3690 dbg_info *dbgi = get_irn_dbg_info(node);
3691 long proj = get_Proj_proj(node);
3693 /* renumber the proj */
3694 if (is_ia32_Load(new_pred)) {
3695 if (proj == pn_Load_res) {
3696 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3697 } else if (proj == pn_Load_M) {
3698 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3700 } else if (is_ia32_xLoad(new_pred)) {
3701 if (proj == pn_Load_res) {
3702 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3703 } else if (proj == pn_Load_M) {
3704 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3706 } else if (is_ia32_vfld(new_pred)) {
3707 if (proj == pn_Load_res) {
3708 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3709 } else if (proj == pn_Load_M) {
3710 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3715 return new_rd_Unknown(irg, get_irn_mode(node));
3719 * Transform and renumber the Projs from a DivMod like instruction.
3721 static ir_node *gen_Proj_DivMod(ir_node *node) {
3722 ir_node *block = be_transform_node(get_nodes_block(node));
3723 ir_node *pred = get_Proj_pred(node);
3724 ir_node *new_pred = be_transform_node(pred);
3725 ir_graph *irg = current_ir_graph;
3726 dbg_info *dbgi = get_irn_dbg_info(node);
3727 ir_mode *mode = get_irn_mode(node);
3728 long proj = get_Proj_proj(node);
3730 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3732 switch (get_irn_opcode(pred)) {
3736 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3738 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3746 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3748 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3756 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3757 case pn_DivMod_res_div:
3758 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3759 case pn_DivMod_res_mod:
3760 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3770 return new_rd_Unknown(irg, mode);
3774 * Transform and renumber the Projs from a CopyB.
3776 static ir_node *gen_Proj_CopyB(ir_node *node) {
3777 ir_node *block = be_transform_node(get_nodes_block(node));
3778 ir_node *pred = get_Proj_pred(node);
3779 ir_node *new_pred = be_transform_node(pred);
3780 ir_graph *irg = current_ir_graph;
3781 dbg_info *dbgi = get_irn_dbg_info(node);
3782 ir_mode *mode = get_irn_mode(node);
3783 long proj = get_Proj_proj(node);
3786 case pn_CopyB_M_regular:
3787 if (is_ia32_CopyB_i(new_pred)) {
3788 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3789 } else if (is_ia32_CopyB(new_pred)) {
3790 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3798 return new_rd_Unknown(irg, mode);
3802 * Transform and renumber the Projs from a vfdiv.
3804 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3805 ir_node *block = be_transform_node(get_nodes_block(node));
3806 ir_node *pred = get_Proj_pred(node);
3807 ir_node *new_pred = be_transform_node(pred);
3808 ir_graph *irg = current_ir_graph;
3809 dbg_info *dbgi = get_irn_dbg_info(node);
3810 ir_mode *mode = get_irn_mode(node);
3811 long proj = get_Proj_proj(node);
3814 case pn_ia32_l_vfdiv_M:
3815 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3816 case pn_ia32_l_vfdiv_res:
3817 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3822 return new_rd_Unknown(irg, mode);
3826 * Transform and renumber the Projs from a Quot.
3828 static ir_node *gen_Proj_Quot(ir_node *node) {
3829 ir_node *block = be_transform_node(get_nodes_block(node));
3830 ir_node *pred = get_Proj_pred(node);
3831 ir_node *new_pred = be_transform_node(pred);
3832 ir_graph *irg = current_ir_graph;
3833 dbg_info *dbgi = get_irn_dbg_info(node);
3834 ir_mode *mode = get_irn_mode(node);
3835 long proj = get_Proj_proj(node);
3839 if (is_ia32_xDiv(new_pred)) {
3840 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3841 } else if (is_ia32_vfdiv(new_pred)) {
3842 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3846 if (is_ia32_xDiv(new_pred)) {
3847 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3848 } else if (is_ia32_vfdiv(new_pred)) {
3849 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3857 return new_rd_Unknown(irg, mode);
3861 * Transform the Thread Local Storage Proj.
3863 static ir_node *gen_Proj_tls(ir_node *node) {
3864 ir_node *block = be_transform_node(get_nodes_block(node));
3865 ir_graph *irg = current_ir_graph;
3866 dbg_info *dbgi = NULL;
3867 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3873 * Transform the Projs from a be_Call.
3875 static ir_node *gen_Proj_be_Call(ir_node *node) {
3876 ir_node *block = be_transform_node(get_nodes_block(node));
3877 ir_node *call = get_Proj_pred(node);
3878 ir_node *new_call = be_transform_node(call);
3879 ir_graph *irg = current_ir_graph;
3880 dbg_info *dbgi = get_irn_dbg_info(node);
3881 long proj = get_Proj_proj(node);
3882 ir_mode *mode = get_irn_mode(node);
3884 const arch_register_class_t *cls;
3886 /* The following is kinda tricky: If we're using SSE, then we have to
3887 * move the result value of the call in floating point registers to an
3888 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3889 * after the call, we have to make sure to correctly make the
3890 * MemProj and the result Proj use these 2 nodes
3892 if (proj == pn_be_Call_M_regular) {
3893 // get new node for result, are we doing the sse load/store hack?
3894 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3895 ir_node *call_res_new;
3896 ir_node *call_res_pred = NULL;
3898 if (call_res != NULL) {
3899 call_res_new = be_transform_node(call_res);
3900 call_res_pred = get_Proj_pred(call_res_new);
3903 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3904 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3906 assert(is_ia32_xLoad(call_res_pred));
3907 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3910 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3912 ir_node *frame = get_irg_frame(irg);
3913 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3915 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3917 const arch_register_class_t *cls;
3919 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3920 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3922 /* store st(0) onto stack */
3923 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3925 set_ia32_ls_mode(fstp, mode);
3926 set_ia32_op_type(fstp, ia32_AddrModeD);
3927 set_ia32_use_frame(fstp);
3928 set_ia32_am_flavour(fstp, ia32_am_B);
3930 /* load into SSE register */
3931 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3932 set_ia32_ls_mode(sse_load, mode);
3933 set_ia32_op_type(sse_load, ia32_AddrModeS);
3934 set_ia32_use_frame(sse_load);
3935 set_ia32_am_flavour(sse_load, ia32_am_B);
3937 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3939 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3941 /* get a Proj representing a caller save register */
3942 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3943 assert(is_Proj(p) && "Proj expected.");
3945 /* user of the the proj is the Keep */
3946 p = get_edge_src_irn(get_irn_out_edge_first(p));
3947 assert(be_is_Keep(p) && "Keep expected.");
3949 /* keep the result */
3950 cls = arch_get_irn_reg_class(env_cg->arch_env, sse_load, -1);
3951 keepin[0] = sse_load;
3952 be_new_Keep(cls, irg, block, 1, keepin);
3957 /* transform call modes */
3958 if (mode_is_data(mode)) {
3959 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
3963 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3967 * Transform the Projs from a Cmp.
3969 static ir_node *gen_Proj_Cmp(ir_node *node)
3971 /* normally Cmps are processed when looking at Cond nodes, but this case
3972 * can happen in complicated Psi conditions */
3974 ir_node *cmp = get_Proj_pred(node);
3975 long pnc = get_Proj_proj(node);
3976 ir_node *cmp_left = get_Cmp_left(cmp);
3977 ir_node *cmp_right = get_Cmp_right(cmp);
3978 ir_mode *cmp_mode = get_irn_mode(cmp_left);
3979 dbg_info *dbgi = get_irn_dbg_info(cmp);
3980 ir_node *block = be_transform_node(get_nodes_block(node));
3983 assert(!mode_is_float(cmp_mode));
3985 if(!mode_is_signed(cmp_mode)) {
3986 pnc |= ia32_pn_Cmp_Unsigned;
3989 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
3990 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
3996 * Transform and potentially renumber Proj nodes.
3998 static ir_node *gen_Proj(ir_node *node) {
3999 ir_graph *irg = current_ir_graph;
4000 dbg_info *dbgi = get_irn_dbg_info(node);
4001 ir_node *pred = get_Proj_pred(node);
4002 long proj = get_Proj_proj(node);
4004 if (is_Store(pred) || be_is_FrameStore(pred)) {
4005 if (proj == pn_Store_M) {
4006 return be_transform_node(pred);
4009 return new_r_Bad(irg);
4011 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4012 return gen_Proj_Load(node);
4013 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4014 return gen_Proj_DivMod(node);
4015 } else if (is_CopyB(pred)) {
4016 return gen_Proj_CopyB(node);
4017 } else if (is_Quot(pred)) {
4018 return gen_Proj_Quot(node);
4019 } else if (is_ia32_l_vfdiv(pred)) {
4020 return gen_Proj_l_vfdiv(node);
4021 } else if (be_is_SubSP(pred)) {
4022 return gen_Proj_be_SubSP(node);
4023 } else if (be_is_AddSP(pred)) {
4024 return gen_Proj_be_AddSP(node);
4025 } else if (be_is_Call(pred)) {
4026 return gen_Proj_be_Call(node);
4027 } else if (is_Cmp(pred)) {
4028 return gen_Proj_Cmp(node);
4029 } else if (get_irn_op(pred) == op_Start) {
4030 if (proj == pn_Start_X_initial_exec) {
4031 ir_node *block = get_nodes_block(pred);
4034 /* we exchange the ProjX with a jump */
4035 block = be_transform_node(block);
4036 jump = new_rd_Jmp(dbgi, irg, block);
4039 if (node == be_get_old_anchor(anchor_tls)) {
4040 return gen_Proj_tls(node);
4043 ir_node *new_pred = be_transform_node(pred);
4044 ir_node *block = be_transform_node(get_nodes_block(node));
4045 ir_mode *mode = get_irn_mode(node);
4046 if (mode_needs_gp_reg(mode)) {
4047 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4048 get_Proj_proj(node));
4049 #ifdef DEBUG_libfirm
4050 new_proj->node_nr = node->node_nr;
4056 return be_duplicate_node(node);
4060 * Enters all transform functions into the generic pointer
4062 static void register_transformers(void)
4066 /* first clear the generic function pointer for all ops */
4067 clear_irp_opcodes_generic_func();
4069 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4070 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4106 /* transform ops from intrinsic lowering */
4126 /* GEN(ia32_l_vfist); TODO */
4128 GEN(ia32_l_X87toSSE);
4129 GEN(ia32_l_SSEtoX87);
4134 /* we should never see these nodes */
4149 /* handle generic backend nodes */
4160 /* set the register for all Unknown nodes */
4163 op_Mulh = get_op_Mulh();
4172 * Pre-transform all unknown and noreg nodes.
4174 static void ia32_pretransform_node(void *arch_cg) {
4175 ia32_code_gen_t *cg = arch_cg;
4177 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4178 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4179 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4180 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4181 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4182 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4185 /* do the transformation */
4186 void ia32_transform_graph(ia32_code_gen_t *cg) {
4187 register_transformers();
4189 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4192 void ia32_init_transform(void)
4194 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");