2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
98 static transform_config_t transform_config;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
108 ir_node *op1, ir_node *op2, ir_node *flags);
110 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *op1, ir_node *op2);
113 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
118 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
120 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
122 ir_node *op1, ir_node *op2, ir_node *fpcw);
124 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
125 ir_node *block, ir_node *op);
127 /****************************************************************************************************
129 * | | | | / _| | | (_)
130 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
131 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
132 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
133 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
135 ****************************************************************************************************/
137 static ir_node *try_create_Immediate(ir_node *node,
138 char immediate_constraint_type);
140 static ir_node *create_immediate_or_transform(ir_node *node,
141 char immediate_constraint_type);
143 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
144 dbg_info *dbgi, ir_node *block,
145 ir_node *op, ir_node *orig_node);
148 * Return true if a mode can be stored in the GP register set
150 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
151 if(mode == mode_fpcw)
153 if(get_mode_size_bits(mode) > 32)
155 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
159 * creates a unique ident by adding a number to a tag
161 * @param tag the tag string, must contain a %d if a number
164 static ident *unique_id(const char *tag)
166 static unsigned id = 0;
169 snprintf(str, sizeof(str), tag, ++id);
170 return new_id_from_str(str);
174 * Get a primitive type for a mode.
176 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
178 pmap_entry *e = pmap_find(types, mode);
183 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
184 res = new_type_primitive(new_id_from_str(buf), mode);
185 set_type_alignment_bytes(res, 16);
186 pmap_insert(types, mode, res);
194 * Get an atomic entity that is initialized with a tarval
196 static ir_entity *create_float_const_entity(ir_node *cnst)
198 ia32_isa_t *isa = env_cg->isa;
199 tarval *tv = get_Const_tarval(cnst);
200 pmap_entry *e = pmap_find(isa->tv_ent, tv);
205 ir_mode *mode = get_irn_mode(cnst);
206 ir_type *tp = get_Const_type(cnst);
207 if (tp == firm_unknown_type)
208 tp = get_prim_type(isa->types, mode);
210 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
212 set_entity_ld_ident(res, get_entity_ident(res));
213 set_entity_visibility(res, visibility_local);
214 set_entity_variability(res, variability_constant);
215 set_entity_allocation(res, allocation_static);
217 /* we create a new entity here: It's initialization must resist on the
219 rem = current_ir_graph;
220 current_ir_graph = get_const_code_irg();
221 set_atomic_ent_value(res, new_Const_type(tv, tp));
222 current_ir_graph = rem;
224 pmap_insert(isa->tv_ent, tv, res);
232 static int is_Const_0(ir_node *node) {
233 return is_Const(node) && is_Const_null(node);
236 static int is_Const_1(ir_node *node) {
237 return is_Const(node) && is_Const_one(node);
240 static int is_Const_Minus_1(ir_node *node) {
241 return is_Const(node) && is_Const_all_one(node);
245 * returns true if constant can be created with a simple float command
247 static int is_simple_x87_Const(ir_node *node)
249 tarval *tv = get_Const_tarval(node);
251 if(tarval_is_null(tv) || tarval_is_one(tv))
254 /* TODO: match all the other float constants */
259 * Transforms a Const.
261 static ir_node *gen_Const(ir_node *node) {
262 ir_graph *irg = current_ir_graph;
263 ir_node *old_block = get_nodes_block(node);
264 ir_node *block = be_transform_node(old_block);
265 dbg_info *dbgi = get_irn_dbg_info(node);
266 ir_mode *mode = get_irn_mode(node);
268 if (mode_is_float(mode)) {
270 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
271 ir_node *nomem = new_NoMem();
275 if (USE_SSE2(env_cg)) {
276 if (is_Const_null(node)) {
277 load = new_rd_ia32_xZero(dbgi, irg, block);
278 set_ia32_ls_mode(load, mode);
281 floatent = create_float_const_entity(node);
283 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
285 set_ia32_op_type(load, ia32_AddrModeS);
286 set_ia32_am_sc(load, floatent);
287 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
288 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
291 if (is_Const_null(node)) {
292 load = new_rd_ia32_vfldz(dbgi, irg, block);
294 } else if (is_Const_one(node)) {
295 load = new_rd_ia32_vfld1(dbgi, irg, block);
298 floatent = create_float_const_entity(node);
300 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
301 set_ia32_op_type(load, ia32_AddrModeS);
302 set_ia32_am_sc(load, floatent);
303 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
304 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
306 set_ia32_ls_mode(load, mode);
309 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
311 /* Const Nodes before the initial IncSP are a bad idea, because
312 * they could be spilled and we have no SP ready at that point yet.
313 * So add a dependency to the initial frame pointer calculation to
314 * avoid that situation.
316 if (get_irg_start_block(irg) == block) {
317 add_irn_dep(load, get_irg_frame(irg));
320 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
324 tarval *tv = get_Const_tarval(node);
327 tv = tarval_convert_to(tv, mode_Iu);
329 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
331 panic("couldn't convert constant tarval (%+F)", node);
333 val = get_tarval_long(tv);
335 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
339 if (get_irg_start_block(irg) == block) {
340 add_irn_dep(cnst, get_irg_frame(irg));
348 * Transforms a SymConst.
350 static ir_node *gen_SymConst(ir_node *node) {
351 ir_graph *irg = current_ir_graph;
352 ir_node *old_block = get_nodes_block(node);
353 ir_node *block = be_transform_node(old_block);
354 dbg_info *dbgi = get_irn_dbg_info(node);
355 ir_mode *mode = get_irn_mode(node);
358 if (mode_is_float(mode)) {
359 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
360 ir_node *nomem = new_NoMem();
362 if (USE_SSE2(env_cg))
363 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
365 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
366 set_ia32_am_sc(cnst, get_SymConst_entity(node));
367 set_ia32_use_frame(cnst);
371 if(get_SymConst_kind(node) != symconst_addr_ent) {
372 panic("backend only support symconst_addr_ent (at %+F)", node);
374 entity = get_SymConst_entity(node);
375 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
378 /* Const Nodes before the initial IncSP are a bad idea, because
379 * they could be spilled and we have no SP ready at that point yet
381 if (get_irg_start_block(irg) == block) {
382 add_irn_dep(cnst, get_irg_frame(irg));
385 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
390 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
391 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
392 static const struct {
394 const char *ent_name;
395 const char *cnst_str;
398 } names [ia32_known_const_max] = {
399 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
400 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
401 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
402 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
403 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
405 static ir_entity *ent_cache[ia32_known_const_max];
407 const char *tp_name, *ent_name, *cnst_str;
415 ent_name = names[kct].ent_name;
416 if (! ent_cache[kct]) {
417 tp_name = names[kct].tp_name;
418 cnst_str = names[kct].cnst_str;
420 switch (names[kct].mode) {
421 case 0: mode = mode_Iu; break;
422 case 1: mode = mode_Lu; break;
423 default: mode = mode_F; break;
425 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
426 tp = new_type_primitive(new_id_from_str(tp_name), mode);
427 /* set the specified alignment */
428 set_type_alignment_bytes(tp, names[kct].align);
430 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
432 set_entity_ld_ident(ent, get_entity_ident(ent));
433 set_entity_visibility(ent, visibility_local);
434 set_entity_variability(ent, variability_constant);
435 set_entity_allocation(ent, allocation_static);
437 /* we create a new entity here: It's initialization must resist on the
439 rem = current_ir_graph;
440 current_ir_graph = get_const_code_irg();
441 cnst = new_Const(mode, tv);
442 current_ir_graph = rem;
444 set_atomic_ent_value(ent, cnst);
446 /* cache the entry */
447 ent_cache[kct] = ent;
450 return ent_cache[kct];
455 * Prints the old node name on cg obst and returns a pointer to it.
457 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
458 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
460 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
461 obstack_1grow(isa->name_obst, 0);
462 return obstack_finish(isa->name_obst);
466 int ia32_use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
468 ir_mode *mode = get_irn_mode(node);
472 /* float constants are always available */
473 if(is_Const(node) && mode_is_float(mode)
474 && !is_simple_x87_Const(node) && get_irn_n_edges(node) == 1) {
480 load = get_Proj_pred(node);
481 pn = get_Proj_proj(node);
482 if(!is_Load(load) || pn != pn_Load_res)
484 if(get_nodes_block(load) != block)
486 /* we only use address mode if we're the only user of the load */
487 if(get_irn_n_edges(node) > 1)
490 /* don't do AM if other node inputs depend on the load (via mem-proj) */
491 if(other != NULL && get_nodes_block(other) == block
492 && heights_reachable_in_block(heights, other, load))
498 typedef struct ia32_address_mode_t ia32_address_mode_t;
499 struct ia32_address_mode_t {
503 ia32_op_type_t op_type;
507 unsigned commutative:1;
508 unsigned ins_permuted:1;
511 static void build_address(ia32_address_mode_t *am, ir_node *node)
513 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
514 ia32_address_t *addr = &am->addr;
523 ir_entity *entity = create_float_const_entity(node);
524 addr->base = noreg_gp;
525 addr->index = noreg_gp;
526 addr->mem = new_NoMem();
527 addr->symconst_ent = entity;
529 am->ls_mode = get_irn_mode(node);
530 am->pinned = op_pin_state_floats;
534 load = get_Proj_pred(node);
535 ptr = get_Load_ptr(load);
536 mem = get_Load_mem(load);
537 new_mem = be_transform_node(mem);
538 am->pinned = get_irn_pinned(load);
539 am->ls_mode = get_Load_mode(load);
540 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
542 /* construct load address */
543 ia32_create_address_mode(addr, ptr, /*force=*/0);
550 base = be_transform_node(base);
556 index = be_transform_node(index);
564 static void set_address(ir_node *node, ia32_address_t *addr)
566 set_ia32_am_scale(node, addr->scale);
567 set_ia32_am_sc(node, addr->symconst_ent);
568 set_ia32_am_offs_int(node, addr->offset);
569 if(addr->symconst_sign)
570 set_ia32_am_sc_sign(node);
572 set_ia32_use_frame(node);
573 set_ia32_frame_ent(node, addr->frame_entity);
576 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
578 set_address(node, &am->addr);
580 set_ia32_op_type(node, am->op_type);
581 set_ia32_ls_mode(node, am->ls_mode);
582 if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) {
583 set_irn_pinned(node, am->pinned);
586 set_ia32_commutative(node);
590 * Check, if a given node is a Down-Conv, ie. a integer Conv
591 * from a mode with a mode with more bits to a mode with lesser bits.
592 * Moreover, we return only true if the node has not more than 1 user.
594 * @param node the node
595 * @return non-zero if node is a Down-Conv
597 static int is_downconv(const ir_node *node)
605 /* we only want to skip the conv when we're the only user
606 * (not optimal but for now...)
608 if(get_irn_n_edges(node) > 1)
611 src_mode = get_irn_mode(get_Conv_op(node));
612 dest_mode = get_irn_mode(node);
613 return mode_needs_gp_reg(src_mode)
614 && mode_needs_gp_reg(dest_mode)
615 && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode);
618 /* Skip all Down-Conv's on a given node and return the resulting node. */
619 ir_node *ia32_skip_downconv(ir_node *node) {
620 while (is_downconv(node))
621 node = get_Conv_op(node);
628 match_commutative = 1 << 0,
629 match_am_and_immediates = 1 << 1,
630 match_no_am = 1 << 2,
631 match_8_bit_am = 1 << 3,
632 match_16_bit_am = 1 << 4,
633 match_no_immediate = 1 << 5,
634 match_force_32bit_op = 1 << 6,
635 match_skip_input_conv = 1 << 7
638 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
639 ir_node *op1, ir_node *op2, match_flags_t flags)
641 ia32_address_t *addr = &am->addr;
642 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
645 ir_mode *mode = get_irn_mode(op2);
647 unsigned commutative;
648 int use_am_and_immediates;
651 int mode_bits = get_mode_size_bits(mode);
653 memset(am, 0, sizeof(am[0]));
655 commutative = (flags & match_commutative) != 0;
656 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
657 use_am = ! (flags & match_no_am);
658 use_immediate = !(flags & match_no_immediate);
659 skip_input_conv = (flags & match_skip_input_conv) != 0;
662 assert(!commutative || op1 != NULL);
664 if(mode_bits == 8 && !(flags & match_8_bit_am)) {
666 } else if(mode_bits == 16 && !(flags & match_16_bit_am)) {
670 op2 = ia32_skip_downconv(op2);
672 op1 = ia32_skip_downconv(op1);
674 new_op2 = (use_immediate ? try_create_Immediate(op2, 0) : NULL);
675 if(new_op2 == NULL && use_am && ia32_use_source_address_mode(block, op2, op1)) {
676 build_address(am, op2);
677 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
678 if(mode_is_float(mode)) {
679 new_op2 = ia32_new_NoReg_vfp(env_cg);
683 am->op_type = ia32_AddrModeS;
684 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
685 use_am && ia32_use_source_address_mode(block, op1, op2)) {
687 build_address(am, op1);
689 if(mode_is_float(mode)) {
690 noreg = ia32_new_NoReg_vfp(env_cg);
695 if(new_op2 != NULL) {
698 new_op1 = be_transform_node(op2);
700 am->ins_permuted = 1;
702 am->op_type = ia32_AddrModeS;
704 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
706 new_op2 = be_transform_node(op2);
707 am->op_type = ia32_Normal;
708 if(flags & match_force_32bit_op) {
709 am->ls_mode = mode_Iu;
711 am->ls_mode = get_irn_mode(op2);
714 if(addr->base == NULL)
715 addr->base = noreg_gp;
716 if(addr->index == NULL)
717 addr->index = noreg_gp;
718 if(addr->mem == NULL)
719 addr->mem = new_NoMem();
721 am->new_op1 = new_op1;
722 am->new_op2 = new_op2;
723 am->commutative = commutative;
726 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
728 ir_graph *irg = current_ir_graph;
732 if(am->mem_proj == NULL)
735 /* we have to create a mode_T so the old MemProj can attach to us */
736 mode = get_irn_mode(node);
737 load = get_Proj_pred(am->mem_proj);
739 mark_irn_visited(load);
740 be_set_transformed_node(load, node);
743 set_irn_mode(node, mode_T);
744 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
751 * Construct a standard binary operation, set AM and immediate if required.
753 * @param op1 The first operand
754 * @param op2 The second operand
755 * @param func The node constructor function
756 * @return The constructed ia32 node.
758 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
759 construct_binop_func *func, match_flags_t flags)
761 ir_node *block = get_nodes_block(node);
762 ir_node *new_block = be_transform_node(block);
763 ir_graph *irg = current_ir_graph;
764 dbg_info *dbgi = get_irn_dbg_info(node);
766 ia32_address_mode_t am;
767 ia32_address_t *addr = &am.addr;
769 flags |= match_force_32bit_op;
771 match_arguments(&am, block, op1, op2, flags);
773 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
774 am.new_op1, am.new_op2);
775 set_am_attributes(new_node, &am);
776 /* we can't use source address mode anymore when using immediates */
777 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
778 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
779 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
781 new_node = fix_mem_proj(new_node, &am);
788 n_ia32_l_binop_right,
789 n_ia32_l_binop_eflags
791 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
792 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
793 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
794 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left)
795 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right)
796 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
799 * Construct a binary operation which also consumes the eflags.
801 * @param node The node to transform
802 * @param func The node constructor function
803 * @param flags The match flags
804 * @return The constructor ia32 node
806 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
809 ir_node *src_block = get_nodes_block(node);
810 ir_node *block = be_transform_node(src_block);
811 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
812 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
813 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
814 ir_node *new_eflags = be_transform_node(eflags);
815 ir_graph *irg = current_ir_graph;
816 dbg_info *dbgi = get_irn_dbg_info(node);
818 ia32_address_mode_t am;
819 ia32_address_t *addr = &am.addr;
821 match_arguments(&am, src_block, op1, op2, flags);
823 new_node = func(dbgi, irg, block, addr->base, addr->index,
824 addr->mem, am.new_op1, am.new_op2, new_eflags);
825 set_am_attributes(new_node, &am);
826 /* we can't use source address mode anymore when using immediates */
827 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
828 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
829 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
831 new_node = fix_mem_proj(new_node, &am);
837 * Construct a standard binary operation, set AM and immediate if required.
839 * @param op1 The first operand
840 * @param op2 The second operand
841 * @param func The node constructor function
842 * @return The constructed ia32 node.
844 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
845 construct_binop_func *func,
848 ir_node *block = get_nodes_block(node);
849 ir_node *new_block = be_transform_node(block);
850 dbg_info *dbgi = get_irn_dbg_info(node);
851 ir_graph *irg = current_ir_graph;
853 ia32_address_mode_t am;
854 ia32_address_t *addr = &am.addr;
856 match_arguments(&am, block, op1, op2, flags);
858 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
859 am.new_op1, am.new_op2);
860 set_am_attributes(new_node, &am);
862 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
864 new_node = fix_mem_proj(new_node, &am);
869 static ir_node *get_fpcw(void)
872 if(initial_fpcw != NULL)
875 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
876 &ia32_fp_cw_regs[REG_FPCW]);
877 initial_fpcw = be_transform_node(fpcw);
883 * Construct a standard binary operation, set AM and immediate if required.
885 * @param op1 The first operand
886 * @param op2 The second operand
887 * @param func The node constructor function
888 * @return The constructed ia32 node.
890 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
891 construct_binop_float_func *func,
894 ir_graph *irg = current_ir_graph;
895 dbg_info *dbgi = get_irn_dbg_info(node);
896 ir_node *block = get_nodes_block(node);
897 ir_node *new_block = be_transform_node(block);
899 ia32_address_mode_t am;
900 ia32_address_t *addr = &am.addr;
902 match_arguments(&am, block, op1, op2, flags);
904 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
905 am.new_op1, am.new_op2, get_fpcw());
906 set_am_attributes(new_node, &am);
908 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
910 new_node = fix_mem_proj(new_node, &am);
916 * Construct a shift/rotate binary operation, sets AM and immediate if required.
918 * @param op1 The first operand
919 * @param op2 The second operand
920 * @param func The node constructor function
921 * @return The constructed ia32 node.
923 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
924 construct_shift_func *func)
926 dbg_info *dbgi = get_irn_dbg_info(node);
927 ir_graph *irg = current_ir_graph;
928 ir_node *block = get_nodes_block(node);
929 ir_node *new_block = be_transform_node(block);
930 ir_node *new_op1 = be_transform_node(op1);
934 assert(! mode_is_float(get_irn_mode(node))
935 && "Shift/Rotate with float not supported");
937 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
938 op2 = get_Conv_op(op2);
939 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
941 new_op2 = create_immediate_or_transform(op2, 0);
943 new_node = func(dbgi, irg, new_block, new_op1, new_op2);
944 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
946 /* lowered shift instruction may have a dependency operand, handle it here */
947 if (get_irn_arity(node) == 3) {
948 /* we have a dependency */
949 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
950 add_irn_dep(new_node, new_dep);
958 * Construct a standard unary operation, set AM and immediate if required.
960 * @param op The operand
961 * @param func The node constructor function
962 * @return The constructed ia32 node.
964 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
966 ir_node *block = be_transform_node(get_nodes_block(node));
967 ir_node *new_op = be_transform_node(op);
968 ir_node *new_node = NULL;
969 ir_graph *irg = current_ir_graph;
970 dbg_info *dbgi = get_irn_dbg_info(node);
972 new_node = func(dbgi, irg, block, new_op);
974 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
979 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
980 ia32_address_t *addr)
982 ir_graph *irg = current_ir_graph;
983 ir_node *base = addr->base;
984 ir_node *index = addr->index;
988 base = ia32_new_NoReg_gp(env_cg);
990 base = be_transform_node(base);
994 index = ia32_new_NoReg_gp(env_cg);
996 index = be_transform_node(index);
999 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1000 set_address(res, addr);
1005 static int am_has_immediates(const ia32_address_t *addr)
1007 return addr->offset != 0 || addr->symconst_ent != NULL
1008 || addr->frame_entity || addr->use_frame;
1012 * Creates an ia32 Add.
1014 * @return the created ia32 Add node
1016 static ir_node *gen_Add(ir_node *node) {
1017 ir_graph *irg = current_ir_graph;
1018 dbg_info *dbgi = get_irn_dbg_info(node);
1019 ir_node *block = get_nodes_block(node);
1020 ir_node *new_block = be_transform_node(block);
1021 ir_node *op1 = get_Add_left(node);
1022 ir_node *op2 = get_Add_right(node);
1023 ir_mode *mode = get_irn_mode(node);
1025 ir_node *add_immediate_op;
1026 ia32_address_t addr;
1027 ia32_address_mode_t am;
1029 if (mode_is_float(mode)) {
1030 if (USE_SSE2(env_cg))
1031 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd, match_commutative);
1033 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd, match_commutative);
1036 op2 = ia32_skip_downconv(op2);
1037 op1 = ia32_skip_downconv(op1);
1041 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1042 * 1. Add with immediate -> Lea
1043 * 2. Add with possible source address mode -> Add
1044 * 3. Otherwise -> Lea
1046 memset(&addr, 0, sizeof(addr));
1047 ia32_create_address_mode(&addr, node, /*force=*/1);
1048 add_immediate_op = NULL;
1050 if(addr.base == NULL && addr.index == NULL) {
1051 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
1052 addr.symconst_sign, addr.offset);
1053 add_irn_dep(new_node, get_irg_frame(irg));
1054 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1057 /* add with immediate? */
1058 if(addr.index == NULL) {
1059 add_immediate_op = addr.base;
1060 } else if(addr.base == NULL && addr.scale == 0) {
1061 add_immediate_op = addr.index;
1064 if(add_immediate_op != NULL) {
1065 if(!am_has_immediates(&addr)) {
1066 #ifdef DEBUG_libfirm
1067 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1070 return be_transform_node(add_immediate_op);
1073 new_node = create_lea_from_address(dbgi, new_block, &addr);
1074 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1078 /* test if we can use source address mode */
1079 match_arguments(&am, block, op1, op2,
1080 match_commutative | match_force_32bit_op | match_skip_input_conv);
1082 /* construct an Add with source address mode */
1083 if (am.op_type == ia32_AddrModeS) {
1084 ia32_address_t *am_addr = &am.addr;
1085 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
1086 am_addr->index, am_addr->mem, am.new_op1,
1088 set_am_attributes(new_node, &am);
1089 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1091 new_node = fix_mem_proj(new_node, &am);
1096 /* otherwise construct a lea */
1097 new_node = create_lea_from_address(dbgi, new_block, &addr);
1098 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1103 * Creates an ia32 Mul.
1105 * @return the created ia32 Mul node
1107 static ir_node *gen_Mul(ir_node *node) {
1108 ir_node *op1 = get_Mul_left(node);
1109 ir_node *op2 = get_Mul_right(node);
1110 ir_mode *mode = get_irn_mode(node);
1112 if (mode_is_float(mode)) {
1113 if (USE_SSE2(env_cg))
1114 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul, match_commutative);
1116 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul, match_commutative);
1120 for the lower 32bit of the result it doesn't matter whether we use
1121 signed or unsigned multiplication so we use IMul as it has fewer
1124 return gen_binop(node, op1, op2, new_rd_ia32_IMul,
1125 match_commutative | match_skip_input_conv | match_force_32bit_op);
1129 * Creates an ia32 Mulh.
1130 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1131 * this result while Mul returns the lower 32 bit.
1133 * @return the created ia32 Mulh node
1135 static ir_node *gen_Mulh(ir_node *node)
1137 ir_node *block = get_nodes_block(node);
1138 ir_node *new_block = be_transform_node(block);
1139 ir_graph *irg = current_ir_graph;
1140 dbg_info *dbgi = get_irn_dbg_info(node);
1141 ir_mode *mode = get_irn_mode(node);
1142 ir_node *op1 = get_Mulh_left(node);
1143 ir_node *op2 = get_Mulh_right(node);
1146 match_flags_t flags;
1147 ia32_address_mode_t am;
1148 ia32_address_t *addr = &am.addr;
1150 flags = match_force_32bit_op | match_commutative | match_no_immediate;
1152 assert(!mode_is_float(mode) && "Mulh with float not supported");
1154 match_arguments(&am, block, op1, op2, flags);
1156 if (mode_is_signed(mode)) {
1157 new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base,
1158 addr->index, addr->mem, am.new_op1,
1161 new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base,
1162 addr->index, addr->mem, am.new_op1,
1166 set_am_attributes(new_node, &am);
1167 /* we can't use source address mode anymore when using immediates */
1168 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
1169 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
1170 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1172 assert(get_irn_mode(new_node) == mode_T);
1174 fix_mem_proj(new_node, &am);
1176 assert(pn_ia32_IMul1OP_EDX == pn_ia32_Mul_EDX);
1177 proj_EDX = new_rd_Proj(dbgi, irg, block, new_node,
1178 mode_Iu, pn_ia32_IMul1OP_EDX);
1186 * Creates an ia32 And.
1188 * @return The created ia32 And node
1190 static ir_node *gen_And(ir_node *node) {
1191 ir_node *op1 = get_And_left(node);
1192 ir_node *op2 = get_And_right(node);
1193 assert(! mode_is_float(get_irn_mode(node)));
1195 /* is it a zero extension? */
1196 if (is_Const(op2)) {
1197 tarval *tv = get_Const_tarval(op2);
1198 long v = get_tarval_long(tv);
1200 if (v == 0xFF || v == 0xFFFF) {
1201 dbg_info *dbgi = get_irn_dbg_info(node);
1202 ir_node *block = get_nodes_block(node);
1209 assert(v == 0xFFFF);
1212 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1218 return gen_binop(node, op1, op2, new_rd_ia32_And,
1219 match_commutative | match_force_32bit_op | match_skip_input_conv);
1225 * Creates an ia32 Or.
1227 * @return The created ia32 Or node
1229 static ir_node *gen_Or(ir_node *node) {
1230 ir_node *op1 = get_Or_left(node);
1231 ir_node *op2 = get_Or_right(node);
1233 assert (! mode_is_float(get_irn_mode(node)));
1234 return gen_binop(node, op1, op2, new_rd_ia32_Or,
1235 match_commutative | match_skip_input_conv | match_force_32bit_op);
1241 * Creates an ia32 Eor.
1243 * @return The created ia32 Eor node
1245 static ir_node *gen_Eor(ir_node *node) {
1246 ir_node *op1 = get_Eor_left(node);
1247 ir_node *op2 = get_Eor_right(node);
1249 assert(! mode_is_float(get_irn_mode(node)));
1250 return gen_binop(node, op1, op2, new_rd_ia32_Xor,
1251 match_commutative | match_skip_input_conv | match_force_32bit_op);
1256 * Creates an ia32 Sub.
1258 * @return The created ia32 Sub node
1260 static ir_node *gen_Sub(ir_node *node) {
1261 ir_node *op1 = get_Sub_left(node);
1262 ir_node *op2 = get_Sub_right(node);
1263 ir_mode *mode = get_irn_mode(node);
1265 if (mode_is_float(mode)) {
1266 if (USE_SSE2(env_cg))
1267 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub, 0);
1269 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub, 0);
1273 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1277 return gen_binop(node, op1, op2, new_rd_ia32_Sub,
1278 match_force_32bit_op | match_skip_input_conv);
1281 typedef enum { flavour_Div = 1, flavour_Mod, flavour_DivMod } ia32_op_flavour_t;
1284 * Generates an ia32 DivMod with additional infrastructure for the
1285 * register allocator if needed.
1287 * @param dividend -no comment- :)
1288 * @param divisor -no comment- :)
1289 * @param dm_flav flavour_Div/Mod/DivMod
1290 * @return The created ia32 DivMod node
1292 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1293 ir_node *divisor, ia32_op_flavour_t dm_flav)
1295 ir_node *block = be_transform_node(get_nodes_block(node));
1296 ir_node *new_dividend = be_transform_node(dividend);
1297 ir_node *new_divisor = be_transform_node(divisor);
1298 ir_graph *irg = current_ir_graph;
1299 dbg_info *dbgi = get_irn_dbg_info(node);
1300 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1301 ir_node *res, *proj_div, *proj_mod;
1303 ir_node *sign_extension;
1304 ir_node *mem, *new_mem;
1307 /* the upper bits have random contents for smaller modes */
1309 proj_div = proj_mod = NULL;
1313 mem = get_Div_mem(node);
1314 mode = get_Div_resmode(node);
1315 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1316 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1319 mem = get_Mod_mem(node);
1320 mode = get_Mod_resmode(node);
1321 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1322 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1324 case flavour_DivMod:
1325 mem = get_DivMod_mem(node);
1326 mode = get_DivMod_resmode(node);
1327 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1328 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1329 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1332 panic("invalid divmod flavour!");
1334 new_mem = be_transform_node(mem);
1336 assert(get_mode_size_bits(mode) == 32);
1338 if (mode_is_signed(mode)) {
1339 /* in signed mode, we need to sign extend the dividend */
1340 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1341 add_irn_dep(produceval, get_irg_frame(irg));
1342 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1345 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1346 set_ia32_flags(sign_extension, get_ia32_flags(sign_extension) | arch_irn_flags_modify_flags);
1347 add_irn_dep(sign_extension, get_irg_frame(irg));
1350 if (mode_is_signed(mode)) {
1351 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
1352 new_dividend, sign_extension, new_divisor);
1354 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem,
1355 new_dividend, sign_extension, new_divisor);
1358 set_ia32_exc_label(res, has_exc);
1359 set_irn_pinned(res, get_irn_pinned(node));
1361 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1368 * Wrapper for generate_DivMod. Sets flavour_Mod.
1371 static ir_node *gen_Mod(ir_node *node) {
1372 return generate_DivMod(node, get_Mod_left(node),
1373 get_Mod_right(node), flavour_Mod);
1377 * Wrapper for generate_DivMod. Sets flavour_Div.
1380 static ir_node *gen_Div(ir_node *node) {
1381 return generate_DivMod(node, get_Div_left(node),
1382 get_Div_right(node), flavour_Div);
1386 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1388 static ir_node *gen_DivMod(ir_node *node) {
1389 return generate_DivMod(node, get_DivMod_left(node),
1390 get_DivMod_right(node), flavour_DivMod);
1396 * Creates an ia32 floating Div.
1398 * @return The created ia32 xDiv node
1400 static ir_node *gen_Quot(ir_node *node)
1402 ir_node *op1 = get_Quot_left(node);
1403 ir_node *op2 = get_Quot_right(node);
1405 if (USE_SSE2(env_cg)) {
1406 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xDiv, 0);
1408 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, 0);
1414 * Creates an ia32 Shl.
1416 * @return The created ia32 Shl node
1418 static ir_node *gen_Shl(ir_node *node) {
1419 ir_node *left = get_Shl_left(node);
1420 ir_node *right = get_Shl_right(node);
1422 left = ia32_skip_downconv(left);
1423 return gen_shift_binop(node, left, right, new_rd_ia32_Shl);
1429 * Creates an ia32 Shr.
1431 * @return The created ia32 Shr node
1433 static ir_node *gen_Shr(ir_node *node) {
1434 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
1435 return gen_shift_binop(node, get_Shr_left(node),
1436 get_Shr_right(node), new_rd_ia32_Shr);
1442 * Creates an ia32 Sar.
1444 * @return The created ia32 Shrs node
1446 static ir_node *gen_Shrs(ir_node *node) {
1447 ir_node *left = get_Shrs_left(node);
1448 ir_node *right = get_Shrs_right(node);
1449 ir_mode *mode = get_irn_mode(node);
1451 assert(get_mode_size_bits(mode) == 32);
1453 if(is_Const(right) && mode == mode_Is) {
1454 tarval *tv = get_Const_tarval(right);
1455 long val = get_tarval_long(tv);
1457 /* this is a sign extension */
1458 ir_graph *irg = current_ir_graph;
1459 dbg_info *dbgi = get_irn_dbg_info(node);
1460 ir_node *block = be_transform_node(get_nodes_block(node));
1462 ir_node *new_op = be_transform_node(op);
1463 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1464 add_irn_dep(pval, get_irg_frame(irg));
1466 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1470 /* 8 or 16 bit sign extension? */
1471 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1472 ir_node *shl_left = get_Shl_left(left);
1473 ir_node *shl_right = get_Shl_right(left);
1474 if(is_Const(shl_right)) {
1475 tarval *tv1 = get_Const_tarval(right);
1476 tarval *tv2 = get_Const_tarval(shl_right);
1477 if(tv1 == tv2 && tarval_is_long(tv1)) {
1478 long val = get_tarval_long(tv1);
1479 if(val == 16 || val == 24) {
1480 dbg_info *dbgi = get_irn_dbg_info(node);
1481 ir_node *block = get_nodes_block(node);
1491 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1500 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1506 * Creates an ia32 RotL.
1508 * @param op1 The first operator
1509 * @param op2 The second operator
1510 * @return The created ia32 RotL node
1512 static ir_node *gen_RotL(ir_node *node,
1513 ir_node *op1, ir_node *op2) {
1514 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
1515 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1521 * Creates an ia32 RotR.
1522 * NOTE: There is no RotR with immediate because this would always be a RotL
1523 * "imm-mode_size_bits" which can be pre-calculated.
1525 * @param op1 The first operator
1526 * @param op2 The second operator
1527 * @return The created ia32 RotR node
1529 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1531 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
1532 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1538 * Creates an ia32 RotR or RotL (depending on the found pattern).
1540 * @return The created ia32 RotL or RotR node
1542 static ir_node *gen_Rot(ir_node *node) {
1543 ir_node *rotate = NULL;
1544 ir_node *op1 = get_Rot_left(node);
1545 ir_node *op2 = get_Rot_right(node);
1547 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1548 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1549 that means we can create a RotR instead of an Add and a RotL */
1551 if (get_irn_op(op2) == op_Add) {
1553 ir_node *left = get_Add_left(add);
1554 ir_node *right = get_Add_right(add);
1555 if (is_Const(right)) {
1556 tarval *tv = get_Const_tarval(right);
1557 ir_mode *mode = get_irn_mode(node);
1558 long bits = get_mode_size_bits(mode);
1560 if (get_irn_op(left) == op_Minus &&
1561 tarval_is_long(tv) &&
1562 get_tarval_long(tv) == bits &&
1565 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1566 rotate = gen_RotR(node, op1, get_Minus_op(left));
1571 if (rotate == NULL) {
1572 rotate = gen_RotL(node, op1, op2);
1581 * Transforms a Minus node.
1583 * @return The created ia32 Minus node
1585 static ir_node *gen_Minus(ir_node *node)
1587 ir_node *op = get_Minus_op(node);
1588 ir_node *block = be_transform_node(get_nodes_block(node));
1589 ir_graph *irg = current_ir_graph;
1590 dbg_info *dbgi = get_irn_dbg_info(node);
1591 ir_mode *mode = get_irn_mode(node);
1596 if (mode_is_float(mode)) {
1597 ir_node *new_op = be_transform_node(op);
1598 if (USE_SSE2(env_cg)) {
1599 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1600 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1601 ir_node *nomem = new_rd_NoMem(irg);
1603 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1606 size = get_mode_size_bits(mode);
1607 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1609 set_ia32_am_sc(res, ent);
1610 set_ia32_op_type(res, ia32_AddrModeS);
1611 set_ia32_ls_mode(res, mode);
1613 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1616 op = ia32_skip_downconv(op);
1617 res = gen_unop(node, op, new_rd_ia32_Neg);
1620 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1626 * Transforms a Not node.
1628 * @return The created ia32 Not node
1630 static ir_node *gen_Not(ir_node *node) {
1631 ir_node *op = get_Not_op(node);
1633 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1634 assert (! mode_is_float(get_irn_mode(node)));
1636 node = ia32_skip_downconv(node);
1637 return gen_unop(node, op, new_rd_ia32_Not);
1643 * Transforms an Abs node.
1645 * @return The created ia32 Abs node
1647 static ir_node *gen_Abs(ir_node *node)
1649 ir_node *block = be_transform_node(get_nodes_block(node));
1650 ir_node *op = get_Abs_op(node);
1651 ir_node *new_op = be_transform_node(op);
1652 ir_graph *irg = current_ir_graph;
1653 dbg_info *dbgi = get_irn_dbg_info(node);
1654 ir_mode *mode = get_irn_mode(node);
1655 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1656 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1657 ir_node *nomem = new_NoMem();
1662 if (mode_is_float(mode)) {
1663 if (USE_SSE2(env_cg)) {
1664 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
1666 size = get_mode_size_bits(mode);
1667 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1669 set_ia32_am_sc(res, ent);
1671 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1673 set_ia32_op_type(res, ia32_AddrModeS);
1674 set_ia32_ls_mode(res, mode);
1676 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1677 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1681 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1682 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1685 add_irn_dep(pval, get_irg_frame(irg));
1686 SET_IA32_ORIG_NODE(sign_extension,
1687 ia32_get_old_node_name(env_cg, node));
1689 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
1691 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1693 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
1695 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1702 * Transforms a Load.
1704 * @return the created ia32 Load node
1706 static ir_node *gen_Load(ir_node *node) {
1707 ir_node *old_block = get_nodes_block(node);
1708 ir_node *block = be_transform_node(old_block);
1709 ir_node *ptr = get_Load_ptr(node);
1710 ir_node *mem = get_Load_mem(node);
1711 ir_node *new_mem = be_transform_node(mem);
1714 ir_graph *irg = current_ir_graph;
1715 dbg_info *dbgi = get_irn_dbg_info(node);
1716 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1717 ir_mode *mode = get_Load_mode(node);
1720 ia32_address_t addr;
1722 /* construct load address */
1723 memset(&addr, 0, sizeof(addr));
1724 ia32_create_address_mode(&addr, ptr, /*force=*/0);
1731 base = be_transform_node(base);
1737 index = be_transform_node(index);
1740 if (mode_is_float(mode)) {
1741 if (USE_SSE2(env_cg)) {
1742 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1744 res_mode = mode_xmm;
1746 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1748 res_mode = mode_vfp;
1754 /* create a conv node with address mode for smaller modes */
1755 if(get_mode_size_bits(mode) < 32) {
1756 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1757 new_mem, noreg, mode);
1759 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1764 set_irn_pinned(new_op, get_irn_pinned(node));
1765 set_ia32_op_type(new_op, ia32_AddrModeS);
1766 set_ia32_ls_mode(new_op, mode);
1767 set_address(new_op, &addr);
1769 /* make sure we are scheduled behind the initial IncSP/Barrier
1770 * to avoid spills being placed before it
1772 if (block == get_irg_start_block(irg)) {
1773 add_irn_dep(new_op, get_irg_frame(irg));
1776 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1777 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1782 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1783 ir_node *ptr, ir_node *other)
1790 /* we only use address mode if we're the only user of the load */
1791 if(get_irn_n_edges(node) > 1)
1794 load = get_Proj_pred(node);
1797 if(get_nodes_block(load) != block)
1800 /* Store should be attached to the load */
1801 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1803 /* store should have the same pointer as the load */
1804 if(get_Load_ptr(load) != ptr)
1807 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1808 if(other != NULL && get_nodes_block(other) == block
1809 && heights_reachable_in_block(heights, other, load))
1815 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1816 ir_node *mem, ir_node *ptr, ir_mode *mode,
1817 construct_binop_dest_func *func,
1818 construct_binop_dest_func *func8bit,
1821 ir_node *src_block = get_nodes_block(node);
1823 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1824 ir_graph *irg = current_ir_graph;
1828 ia32_address_mode_t am;
1829 ia32_address_t *addr = &am.addr;
1830 memset(&am, 0, sizeof(am));
1832 if(use_dest_am(src_block, op1, mem, ptr, op2)) {
1833 build_address(&am, op1);
1834 new_op = create_immediate_or_transform(op2, 0);
1835 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
1836 build_address(&am, op2);
1837 new_op = create_immediate_or_transform(op1, 0);
1842 if(addr->base == NULL)
1843 addr->base = noreg_gp;
1844 if(addr->index == NULL)
1845 addr->index = noreg_gp;
1846 if(addr->mem == NULL)
1847 addr->mem = new_NoMem();
1849 dbgi = get_irn_dbg_info(node);
1850 block = be_transform_node(src_block);
1851 if(get_mode_size_bits(mode) == 8) {
1852 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1855 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1858 set_address(new_node, addr);
1859 set_ia32_op_type(new_node, ia32_AddrModeD);
1860 set_ia32_ls_mode(new_node, mode);
1861 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1866 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1867 ir_node *ptr, ir_mode *mode,
1868 construct_unop_dest_func *func)
1870 ir_node *src_block = get_nodes_block(node);
1872 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1873 ir_graph *irg = current_ir_graph;
1876 ia32_address_mode_t am;
1877 ia32_address_t *addr = &am.addr;
1878 memset(&am, 0, sizeof(am));
1880 if(!use_dest_am(src_block, op, mem, ptr, NULL))
1883 build_address(&am, op);
1885 if(addr->base == NULL)
1886 addr->base = noreg_gp;
1887 if(addr->index == NULL)
1888 addr->index = noreg_gp;
1889 if(addr->mem == NULL)
1890 addr->mem = new_NoMem();
1892 dbgi = get_irn_dbg_info(node);
1893 block = be_transform_node(src_block);
1894 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1895 set_address(new_node, addr);
1896 set_ia32_op_type(new_node, ia32_AddrModeD);
1897 set_ia32_ls_mode(new_node, mode);
1898 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1903 static ir_node *try_create_dest_am(ir_node *node) {
1904 ir_node *val = get_Store_value(node);
1905 ir_node *mem = get_Store_mem(node);
1906 ir_node *ptr = get_Store_ptr(node);
1907 ir_mode *mode = get_irn_mode(val);
1912 /* handle only GP modes for now... */
1913 if(!mode_needs_gp_reg(mode))
1916 /* store must be the only user of the val node */
1917 if(get_irn_n_edges(val) > 1)
1920 switch(get_irn_opcode(val)) {
1922 op1 = get_Add_left(val);
1923 op2 = get_Add_right(val);
1924 if(is_Const_1(op2)) {
1925 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1926 new_rd_ia32_IncMem);
1928 } else if(is_Const_Minus_1(op2)) {
1929 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1930 new_rd_ia32_DecMem);
1933 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1934 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, 1);
1937 op1 = get_Sub_left(val);
1938 op2 = get_Sub_right(val);
1940 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
1943 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1944 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, 0);
1947 op1 = get_And_left(val);
1948 op2 = get_And_right(val);
1949 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1950 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, 1);
1953 op1 = get_Or_left(val);
1954 op2 = get_Or_right(val);
1955 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1956 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, 1);
1959 op1 = get_Eor_left(val);
1960 op2 = get_Eor_right(val);
1961 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1962 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, 1);
1965 op1 = get_Shl_left(val);
1966 op2 = get_Shl_right(val);
1967 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1968 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, 0);
1971 op1 = get_Shr_left(val);
1972 op2 = get_Shr_right(val);
1973 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1974 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, 0);
1977 op1 = get_Shrs_left(val);
1978 op2 = get_Shrs_right(val);
1979 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1980 new_rd_ia32_SarMem, new_rd_ia32_SarMem, 0);
1983 op1 = get_Rot_left(val);
1984 op2 = get_Rot_right(val);
1985 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1986 new_rd_ia32_RolMem, new_rd_ia32_RolMem, 0);
1988 /* TODO: match ROR patterns... */
1990 op1 = get_Minus_op(val);
1991 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1994 /* should be lowered already */
1995 assert(mode != mode_b);
1996 op1 = get_Not_op(val);
1997 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
2007 * Transforms a Store.
2009 * @return the created ia32 Store node
2011 static ir_node *gen_Store(ir_node *node) {
2012 ir_node *block = be_transform_node(get_nodes_block(node));
2013 ir_node *ptr = get_Store_ptr(node);
2016 ir_node *val = get_Store_value(node);
2018 ir_node *mem = get_Store_mem(node);
2019 ir_node *new_mem = be_transform_node(mem);
2020 ir_graph *irg = current_ir_graph;
2021 dbg_info *dbgi = get_irn_dbg_info(node);
2022 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2023 ir_mode *mode = get_irn_mode(val);
2025 ia32_address_t addr;
2027 /* check for destination address mode */
2028 new_op = try_create_dest_am(node);
2032 /* construct store address */
2033 memset(&addr, 0, sizeof(addr));
2034 ia32_create_address_mode(&addr, ptr, /*force=*/0);
2041 base = be_transform_node(base);
2047 index = be_transform_node(index);
2050 if (mode_is_float(mode)) {
2051 /* convs (and strict-convs) before stores are unnecessary if the mode
2053 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2054 val = get_Conv_op(val);
2056 new_val = be_transform_node(val);
2057 if (USE_SSE2(env_cg)) {
2058 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
2061 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
2065 new_val = create_immediate_or_transform(val, 0);
2069 if (get_mode_size_bits(mode) == 8) {
2070 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
2073 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
2078 set_irn_pinned(new_op, get_irn_pinned(node));
2079 set_ia32_op_type(new_op, ia32_AddrModeD);
2080 set_ia32_ls_mode(new_op, mode);
2082 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
2083 set_address(new_op, &addr);
2084 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2089 static ir_node *create_Switch(ir_node *node)
2091 ir_graph *irg = current_ir_graph;
2092 dbg_info *dbgi = get_irn_dbg_info(node);
2093 ir_node *block = be_transform_node(get_nodes_block(node));
2094 ir_node *sel = get_Cond_selector(node);
2095 ir_node *new_sel = be_transform_node(sel);
2097 int switch_min = INT_MAX;
2098 const ir_edge_t *edge;
2100 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2102 /* determine the smallest switch case value */
2103 foreach_out_edge(node, edge) {
2104 ir_node *proj = get_edge_src_irn(edge);
2105 int pn = get_Proj_proj(proj);
2110 if (switch_min != 0) {
2111 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2113 /* if smallest switch case is not 0 we need an additional sub */
2114 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2115 add_ia32_am_offs_int(new_sel, -switch_min);
2116 set_ia32_op_type(new_sel, ia32_AddrModeS);
2118 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2121 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel, get_Cond_defaultProj(node));
2123 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2128 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
2130 ir_graph *irg = current_ir_graph;
2138 /* we have a Cmp as input */
2140 ir_node *pred = get_Proj_pred(node);
2142 flags = be_transform_node(pred);
2143 *pnc_out = get_Proj_proj(node);
2148 /* a mode_b value, we have to compare it against 0 */
2149 dbgi = get_irn_dbg_info(node);
2150 new_block = be_transform_node(get_nodes_block(node));
2151 new_op = be_transform_node(node);
2152 noreg = ia32_new_NoReg_gp(env_cg);
2153 nomem = new_NoMem();
2154 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
2155 new_op, new_op, 0, 0);
2156 *pnc_out = pn_Cmp_Lg;
2160 static ir_node *gen_Cond(ir_node *node) {
2161 ir_node *block = get_nodes_block(node);
2162 ir_node *new_block = be_transform_node(block);
2163 ir_graph *irg = current_ir_graph;
2164 dbg_info *dbgi = get_irn_dbg_info(node);
2165 ir_node *sel = get_Cond_selector(node);
2166 ir_mode *sel_mode = get_irn_mode(sel);
2168 ir_node *flags = NULL;
2171 if (sel_mode != mode_b) {
2172 return create_Switch(node);
2175 /* we get flags from a cmp */
2176 flags = get_flags_node(sel, &pnc);
2178 res = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2179 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2187 * Transforms a CopyB node.
2189 * @return The transformed node.
2191 static ir_node *gen_CopyB(ir_node *node) {
2192 ir_node *block = be_transform_node(get_nodes_block(node));
2193 ir_node *src = get_CopyB_src(node);
2194 ir_node *new_src = be_transform_node(src);
2195 ir_node *dst = get_CopyB_dst(node);
2196 ir_node *new_dst = be_transform_node(dst);
2197 ir_node *mem = get_CopyB_mem(node);
2198 ir_node *new_mem = be_transform_node(mem);
2199 ir_node *res = NULL;
2200 ir_graph *irg = current_ir_graph;
2201 dbg_info *dbgi = get_irn_dbg_info(node);
2202 int size = get_type_size_bytes(get_CopyB_type(node));
2205 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2206 /* then we need the size explicitly in ECX. */
2207 if (size >= 32 * 4) {
2208 rem = size & 0x3; /* size % 4 */
2211 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2212 add_irn_dep(res, get_irg_frame(irg));
2214 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
2217 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2220 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
2223 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2228 static ir_node *gen_be_Copy(ir_node *node)
2230 ir_node *result = be_duplicate_node(node);
2231 ir_mode *mode = get_irn_mode(result);
2233 if (mode_needs_gp_reg(mode)) {
2234 set_irn_mode(result, mode_Iu);
2241 * helper function: checks whether all Cmp projs are Lg or Eq which is needed
2242 * to fold an And into a test node
2244 static int can_fold_test_and(ir_node *node)
2246 const ir_edge_t *edge;
2248 /* we can only have Eq and Lg Projs */
2249 foreach_out_edge(node, edge) {
2250 ir_node *proj = get_edge_src_irn(edge);
2251 pn_Cmp pnc = get_Proj_proj(proj);
2252 if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2259 static ir_node *try_create_Test(ir_node *node)
2261 ir_graph *irg = current_ir_graph;
2262 dbg_info *dbgi = get_irn_dbg_info(node);
2263 ir_node *block = get_nodes_block(node);
2264 ir_node *new_block = be_transform_node(block);
2265 ir_node *cmp_left = get_Cmp_left(node);
2266 ir_node *cmp_right = get_Cmp_right(node);
2271 ia32_address_mode_t am;
2272 ia32_address_t *addr = &am.addr;
2275 /* can we use a test instruction? */
2276 if(!is_Const_0(cmp_right))
2279 if(is_And(cmp_left) && get_irn_n_edges(cmp_left) == 1 &&
2280 can_fold_test_and(node)) {
2281 ir_node *and_left = get_And_left(cmp_left);
2282 ir_node *and_right = get_And_right(cmp_left);
2284 mode = get_irn_mode(and_left);
2288 mode = get_irn_mode(cmp_left);
2293 assert(get_mode_size_bits(mode) <= 32);
2295 match_arguments(&am, block, left, right, match_commutative |
2296 match_8_bit_am | match_16_bit_am | match_am_and_immediates);
2298 cmp_unsigned = !mode_is_signed(mode);
2299 if(get_mode_size_bits(mode) == 8) {
2300 res = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2301 addr->index, addr->mem, am.new_op1,
2302 am.new_op2, am.ins_permuted, cmp_unsigned);
2304 res = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, addr->index,
2305 addr->mem, am.new_op1, am.new_op2,
2306 am.ins_permuted, cmp_unsigned);
2308 set_am_attributes(res, &am);
2309 assert(mode != NULL);
2310 set_ia32_ls_mode(res, mode);
2312 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2314 res = fix_mem_proj(res, &am);
2318 static ir_node *create_Fucom(ir_node *node)
2320 ir_graph *irg = current_ir_graph;
2321 dbg_info *dbgi = get_irn_dbg_info(node);
2322 ir_node *block = get_nodes_block(node);
2323 ir_node *new_block = be_transform_node(block);
2324 ir_node *left = get_Cmp_left(node);
2325 ir_node *new_left = be_transform_node(left);
2326 ir_node *right = get_Cmp_right(node);
2330 if(transform_config.use_fucomi) {
2331 new_right = be_transform_node(right);
2332 res = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left, new_right, 0);
2333 set_ia32_commutative(res);
2334 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2336 if(transform_config.use_ftst && is_Const_null(right)) {
2337 res = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left, 0);
2339 new_right = be_transform_node(right);
2340 res = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2344 set_ia32_commutative(res);
2346 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2348 res = new_rd_ia32_Sahf(dbgi, irg, new_block, res);
2349 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2355 static ir_node *create_Ucomi(ir_node *node)
2357 ir_graph *irg = current_ir_graph;
2358 dbg_info *dbgi = get_irn_dbg_info(node);
2359 ir_node *src_block = get_nodes_block(node);
2360 ir_node *new_block = be_transform_node(src_block);
2361 ir_node *left = get_Cmp_left(node);
2362 ir_node *right = get_Cmp_right(node);
2364 ia32_address_mode_t am;
2365 ia32_address_t *addr = &am.addr;
2367 match_arguments(&am, src_block, left, right, match_commutative);
2369 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2370 addr->mem, am.new_op1, am.new_op2,
2372 set_am_attributes(new_node, &am);
2374 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2376 new_node = fix_mem_proj(new_node, &am);
2381 static ir_node *gen_Cmp(ir_node *node)
2383 ir_graph *irg = current_ir_graph;
2384 dbg_info *dbgi = get_irn_dbg_info(node);
2385 ir_node *block = get_nodes_block(node);
2386 ir_node *new_block = be_transform_node(block);
2387 ir_node *left = get_Cmp_left(node);
2388 ir_node *right = get_Cmp_right(node);
2389 ir_mode *cmp_mode = get_irn_mode(left);
2391 ia32_address_mode_t am;
2392 ia32_address_t *addr = &am.addr;
2395 if(mode_is_float(cmp_mode)) {
2396 if (USE_SSE2(env_cg)) {
2397 return create_Ucomi(node);
2399 return create_Fucom(node);
2403 assert(mode_needs_gp_reg(cmp_mode));
2405 /* we prefer the Test instruction where possible except cases where
2406 * we can use SourceAM */
2407 if(!ia32_use_source_address_mode(block, left, right) &&
2408 !ia32_use_source_address_mode(block, right, left)) {
2409 res = try_create_Test(node);
2414 match_arguments(&am, block, left, right,
2415 match_commutative | match_8_bit_am | match_16_bit_am |
2416 match_am_and_immediates);
2418 cmp_unsigned = !mode_is_signed(get_irn_mode(left));
2419 if(get_mode_size_bits(cmp_mode) == 8) {
2420 res = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, addr->index,
2421 addr->mem, am.new_op1, am.new_op2,
2422 am.ins_permuted, cmp_unsigned);
2424 res = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, addr->index,
2425 addr->mem, am.new_op1, am.new_op2,
2426 am.ins_permuted, cmp_unsigned);
2428 set_am_attributes(res, &am);
2429 assert(cmp_mode != NULL);
2430 set_ia32_ls_mode(res, cmp_mode);
2432 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2434 res = fix_mem_proj(res, &am);
2439 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2441 ir_graph *irg = current_ir_graph;
2442 dbg_info *dbgi = get_irn_dbg_info(node);
2443 ir_node *block = get_nodes_block(node);
2444 ir_node *new_block = be_transform_node(block);
2445 ir_node *val_true = get_Psi_val(node, 0);
2446 ir_node *val_false = get_Psi_default(node);
2448 match_flags_t match_flags;
2449 ia32_address_mode_t am;
2450 ia32_address_t *addr;
2452 assert(transform_config.use_cmov);
2453 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2457 match_flags = match_commutative | match_no_immediate | match_16_bit_am
2458 | match_force_32bit_op;
2460 match_arguments(&am, block, val_false, val_true, match_flags);
2462 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2463 addr->mem, am.new_op1, am.new_op2, new_flags,
2464 am.ins_permuted, pnc);
2465 set_am_attributes(new_node, &am);
2467 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2469 new_node = fix_mem_proj(new_node, &am);
2476 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2477 ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
2480 ir_graph *irg = current_ir_graph;
2481 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2482 ir_node *nomem = new_NoMem();
2485 res = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
2486 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2487 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2488 nomem, res, mode_Bu);
2489 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2496 * Transforms a Psi node into CMov.
2498 * @return The transformed node.
2500 static ir_node *gen_Psi(ir_node *node)
2502 dbg_info *dbgi = get_irn_dbg_info(node);
2503 ir_node *block = get_nodes_block(node);
2504 ir_node *new_block = be_transform_node(block);
2505 ir_node *psi_true = get_Psi_val(node, 0);
2506 ir_node *psi_default = get_Psi_default(node);
2507 ir_node *cond = get_Psi_cond(node, 0);
2508 ir_node *flags = NULL;
2512 assert(get_Psi_n_conds(node) == 1);
2513 assert(get_irn_mode(cond) == mode_b);
2514 assert(mode_needs_gp_reg(get_irn_mode(node)));
2516 flags = get_flags_node(cond, &pnc);
2518 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2519 res = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
2520 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2521 res = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
2523 res = create_CMov(node, flags, pnc);
2530 * Create a conversion from x87 state register to general purpose.
2532 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2533 ir_node *block = be_transform_node(get_nodes_block(node));
2534 ir_node *op = get_Conv_op(node);
2535 ir_node *new_op = be_transform_node(op);
2536 ia32_code_gen_t *cg = env_cg;
2537 ir_graph *irg = current_ir_graph;
2538 dbg_info *dbgi = get_irn_dbg_info(node);
2539 ir_node *noreg = ia32_new_NoReg_gp(cg);
2540 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2541 ir_mode *mode = get_irn_mode(node);
2542 ir_node *fist, *load;
2545 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2546 new_NoMem(), new_op, trunc_mode);
2548 set_irn_pinned(fist, op_pin_state_floats);
2549 set_ia32_use_frame(fist);
2550 set_ia32_op_type(fist, ia32_AddrModeD);
2552 assert(get_mode_size_bits(mode) <= 32);
2553 /* exception we can only store signed 32 bit integers, so for unsigned
2554 we store a 64bit (signed) integer and load the lower bits */
2555 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2556 set_ia32_ls_mode(fist, mode_Ls);
2558 set_ia32_ls_mode(fist, mode_Is);
2560 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2563 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2565 set_irn_pinned(load, op_pin_state_floats);
2566 set_ia32_use_frame(load);
2567 set_ia32_op_type(load, ia32_AddrModeS);
2568 set_ia32_ls_mode(load, mode_Is);
2569 if(get_ia32_ls_mode(fist) == mode_Ls) {
2570 ia32_attr_t *attr = get_ia32_attr(load);
2571 attr->data.need_64bit_stackent = 1;
2573 ia32_attr_t *attr = get_ia32_attr(load);
2574 attr->data.need_32bit_stackent = 1;
2576 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2578 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2582 * Creates a x87 strict Conv by placing a Sore and a Load
2584 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2586 ir_node *block = get_nodes_block(node);
2587 ir_graph *irg = current_ir_graph;
2588 dbg_info *dbgi = get_irn_dbg_info(node);
2589 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2590 ir_node *nomem = new_NoMem();
2591 ir_node *frame = get_irg_frame(irg);
2592 ir_node *store, *load;
2595 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2597 set_ia32_use_frame(store);
2598 set_ia32_op_type(store, ia32_AddrModeD);
2599 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2601 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2603 set_ia32_use_frame(load);
2604 set_ia32_op_type(load, ia32_AddrModeS);
2605 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2607 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2611 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2613 ir_graph *irg = current_ir_graph;
2614 ir_node *start_block = get_irg_start_block(irg);
2615 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2616 symconst, symconst_sign, val);
2617 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2623 * Create a conversion from general purpose to x87 register
2625 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2626 ir_node *src_block = get_nodes_block(node);
2627 ir_node *block = be_transform_node(src_block);
2628 ir_graph *irg = current_ir_graph;
2629 dbg_info *dbgi = get_irn_dbg_info(node);
2630 ir_node *op = get_Conv_op(node);
2635 ir_mode *store_mode;
2641 /* fild can use source AM if the operand is a signed 32bit integer */
2642 if (src_mode == mode_Is) {
2643 ia32_address_mode_t am;
2645 match_arguments(&am, src_block, NULL, op, match_no_immediate);
2646 if (am.op_type == ia32_AddrModeS) {
2647 ia32_address_t *addr = &am.addr;
2649 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base, addr->index, addr->mem);
2650 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2652 set_am_attributes(fild, &am);
2653 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2655 fix_mem_proj(fild, &am);
2659 new_op = am.new_op2;
2661 new_op = be_transform_node(op);
2664 noreg = ia32_new_NoReg_gp(env_cg);
2665 nomem = new_NoMem();
2666 mode = get_irn_mode(op);
2668 /* first convert to 32 bit signed if necessary */
2669 src_bits = get_mode_size_bits(src_mode);
2670 if (src_bits == 8) {
2671 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2673 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2675 } else if (src_bits < 32) {
2676 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2678 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2682 assert(get_mode_size_bits(mode) == 32);
2685 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2688 set_ia32_use_frame(store);
2689 set_ia32_op_type(store, ia32_AddrModeD);
2690 set_ia32_ls_mode(store, mode_Iu);
2692 /* exception for 32bit unsigned, do a 64bit spill+load */
2693 if(!mode_is_signed(mode)) {
2696 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2698 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2699 get_irg_frame(irg), noreg, nomem,
2702 set_ia32_use_frame(zero_store);
2703 set_ia32_op_type(zero_store, ia32_AddrModeD);
2704 add_ia32_am_offs_int(zero_store, 4);
2705 set_ia32_ls_mode(zero_store, mode_Iu);
2710 store = new_rd_Sync(dbgi, irg, block, 2, in);
2711 store_mode = mode_Ls;
2713 store_mode = mode_Is;
2717 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2719 set_ia32_use_frame(fild);
2720 set_ia32_op_type(fild, ia32_AddrModeS);
2721 set_ia32_ls_mode(fild, store_mode);
2723 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2729 * Create a conversion from one integer mode into another one
2731 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2732 dbg_info *dbgi, ir_node *block, ir_node *op,
2735 ir_graph *irg = current_ir_graph;
2736 int src_bits = get_mode_size_bits(src_mode);
2737 int tgt_bits = get_mode_size_bits(tgt_mode);
2738 ir_node *new_block = be_transform_node(block);
2740 ir_mode *smaller_mode;
2742 ia32_address_mode_t am;
2743 ia32_address_t *addr = &am.addr;
2745 if (src_bits < tgt_bits) {
2746 smaller_mode = src_mode;
2747 smaller_bits = src_bits;
2749 smaller_mode = tgt_mode;
2750 smaller_bits = tgt_bits;
2753 match_arguments(&am, block, NULL, op, match_8_bit_am | match_16_bit_am);
2754 if (smaller_bits == 8 && am.op_type == ia32_Normal) {
2755 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2756 addr->index, addr->mem, am.new_op2,
2759 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2760 addr->index, addr->mem, am.new_op2,
2763 set_am_attributes(res, &am);
2764 set_ia32_ls_mode(res, smaller_mode);
2765 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2766 res = fix_mem_proj(res, &am);
2771 * Transforms a Conv node.
2773 * @return The created ia32 Conv node
2775 static ir_node *gen_Conv(ir_node *node) {
2776 ir_node *block = get_nodes_block(node);
2777 ir_node *new_block = be_transform_node(block);
2778 ir_node *op = get_Conv_op(node);
2779 ir_node *new_op = NULL;
2780 ir_graph *irg = current_ir_graph;
2781 dbg_info *dbgi = get_irn_dbg_info(node);
2782 ir_mode *src_mode = get_irn_mode(op);
2783 ir_mode *tgt_mode = get_irn_mode(node);
2784 int src_bits = get_mode_size_bits(src_mode);
2785 int tgt_bits = get_mode_size_bits(tgt_mode);
2786 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2787 ir_node *nomem = new_rd_NoMem(irg);
2788 ir_node *res = NULL;
2790 if (src_mode == mode_b) {
2791 assert(mode_is_int(tgt_mode));
2792 /* nothing to do, we already model bools as 0/1 ints */
2793 return be_transform_node(op);
2796 if (src_mode == tgt_mode) {
2797 if (get_Conv_strict(node)) {
2798 if (USE_SSE2(env_cg)) {
2799 /* when we are in SSE mode, we can kill all strict no-op conversion */
2800 return be_transform_node(op);
2803 /* this should be optimized already, but who knows... */
2804 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2805 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2806 return be_transform_node(op);
2810 if (mode_is_float(src_mode)) {
2811 new_op = be_transform_node(op);
2812 /* we convert from float ... */
2813 if (mode_is_float(tgt_mode)) {
2814 if(src_mode == mode_E && tgt_mode == mode_D
2815 && !get_Conv_strict(node)) {
2816 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2821 if (USE_SSE2(env_cg)) {
2822 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2823 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2825 set_ia32_ls_mode(res, tgt_mode);
2827 if(get_Conv_strict(node)) {
2828 res = gen_x87_strict_conv(tgt_mode, new_op);
2829 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2832 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2837 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2838 if (USE_SSE2(env_cg)) {
2839 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2841 set_ia32_ls_mode(res, src_mode);
2843 return gen_x87_fp_to_gp(node);
2847 /* we convert from int ... */
2848 if (mode_is_float(tgt_mode)) {
2850 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2851 if (USE_SSE2(env_cg)) {
2852 new_op = be_transform_node(op);
2853 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2855 set_ia32_ls_mode(res, tgt_mode);
2857 res = gen_x87_gp_to_fp(node, src_mode);
2858 if(get_Conv_strict(node)) {
2859 res = gen_x87_strict_conv(tgt_mode, res);
2860 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2861 ia32_get_old_node_name(env_cg, node));
2865 } else if(tgt_mode == mode_b) {
2866 /* mode_b lowering already took care that we only have 0/1 values */
2867 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2868 src_mode, tgt_mode));
2869 return be_transform_node(op);
2872 if (src_bits == tgt_bits) {
2873 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2874 src_mode, tgt_mode));
2875 return be_transform_node(op);
2878 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2886 static int check_immediate_constraint(long val, char immediate_constraint_type)
2888 switch (immediate_constraint_type) {
2892 return val >= 0 && val <= 32;
2894 return val >= 0 && val <= 63;
2896 return val >= -128 && val <= 127;
2898 return val == 0xff || val == 0xffff;
2900 return val >= 0 && val <= 3;
2902 return val >= 0 && val <= 255;
2904 return val >= 0 && val <= 127;
2908 panic("Invalid immediate constraint found");
2912 static ir_node *try_create_Immediate(ir_node *node,
2913 char immediate_constraint_type)
2916 tarval *offset = NULL;
2917 int offset_sign = 0;
2919 ir_entity *symconst_ent = NULL;
2920 int symconst_sign = 0;
2922 ir_node *cnst = NULL;
2923 ir_node *symconst = NULL;
2926 mode = get_irn_mode(node);
2927 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2931 if(is_Minus(node)) {
2933 node = get_Minus_op(node);
2936 if(is_Const(node)) {
2939 offset_sign = minus;
2940 } else if(is_SymConst(node)) {
2943 symconst_sign = minus;
2944 } else if(is_Add(node)) {
2945 ir_node *left = get_Add_left(node);
2946 ir_node *right = get_Add_right(node);
2947 if(is_Const(left) && is_SymConst(right)) {
2950 symconst_sign = minus;
2951 offset_sign = minus;
2952 } else if(is_SymConst(left) && is_Const(right)) {
2955 symconst_sign = minus;
2956 offset_sign = minus;
2958 } else if(is_Sub(node)) {
2959 ir_node *left = get_Sub_left(node);
2960 ir_node *right = get_Sub_right(node);
2961 if(is_Const(left) && is_SymConst(right)) {
2964 symconst_sign = !minus;
2965 offset_sign = minus;
2966 } else if(is_SymConst(left) && is_Const(right)) {
2969 symconst_sign = minus;
2970 offset_sign = !minus;
2977 offset = get_Const_tarval(cnst);
2978 if(tarval_is_long(offset)) {
2979 val = get_tarval_long(offset);
2981 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2986 if(!check_immediate_constraint(val, immediate_constraint_type))
2989 if(symconst != NULL) {
2990 if(immediate_constraint_type != 0) {
2991 /* we need full 32bits for symconsts */
2995 /* unfortunately the assembler/linker doesn't support -symconst */
2999 if(get_SymConst_kind(symconst) != symconst_addr_ent)
3001 symconst_ent = get_SymConst_entity(symconst);
3003 if(cnst == NULL && symconst == NULL)
3006 if(offset_sign && offset != NULL) {
3007 offset = tarval_neg(offset);
3010 res = create_Immediate(symconst_ent, symconst_sign, val);
3015 static ir_node *create_immediate_or_transform(ir_node *node,
3016 char immediate_constraint_type)
3018 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
3019 if (new_node == NULL) {
3020 new_node = be_transform_node(node);
3025 static const arch_register_req_t no_register_req = {
3026 arch_register_req_type_none,
3027 NULL, /* regclass */
3028 NULL, /* limit bitset */
3029 { -1, -1 }, /* same pos */
3030 -1 /* different pos */
3034 * An assembler constraint.
3036 typedef struct constraint_t constraint_t;
3037 struct constraint_t {
3040 const arch_register_req_t **out_reqs;
3042 const arch_register_req_t *req;
3043 unsigned immediate_possible;
3044 char immediate_type;
3047 static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
3049 int immediate_possible = 0;
3050 char immediate_type = 0;
3051 unsigned limited = 0;
3052 const arch_register_class_t *cls = NULL;
3053 ir_graph *irg = current_ir_graph;
3054 struct obstack *obst = get_irg_obstack(irg);
3055 arch_register_req_t *req;
3056 unsigned *limited_ptr;
3060 /* TODO: replace all the asserts with nice error messages */
3063 /* a memory constraint: no need to do anything in backend about it
3064 * (the dependencies are already respected by the memory edge of
3066 constraint->req = &no_register_req;
3078 assert(cls == NULL ||
3079 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3080 cls = &ia32_reg_classes[CLASS_ia32_gp];
3081 limited |= 1 << REG_EAX;
3084 assert(cls == NULL ||
3085 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3086 cls = &ia32_reg_classes[CLASS_ia32_gp];
3087 limited |= 1 << REG_EBX;
3090 assert(cls == NULL ||
3091 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3092 cls = &ia32_reg_classes[CLASS_ia32_gp];
3093 limited |= 1 << REG_ECX;
3096 assert(cls == NULL ||
3097 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3098 cls = &ia32_reg_classes[CLASS_ia32_gp];
3099 limited |= 1 << REG_EDX;
3102 assert(cls == NULL ||
3103 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3104 cls = &ia32_reg_classes[CLASS_ia32_gp];
3105 limited |= 1 << REG_EDI;
3108 assert(cls == NULL ||
3109 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3110 cls = &ia32_reg_classes[CLASS_ia32_gp];
3111 limited |= 1 << REG_ESI;
3114 case 'q': /* q means lower part of the regs only, this makes no
3115 * difference to Q for us (we only assigne whole registers) */
3116 assert(cls == NULL ||
3117 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3118 cls = &ia32_reg_classes[CLASS_ia32_gp];
3119 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3123 assert(cls == NULL ||
3124 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3125 cls = &ia32_reg_classes[CLASS_ia32_gp];
3126 limited |= 1 << REG_EAX | 1 << REG_EDX;
3129 assert(cls == NULL ||
3130 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3131 cls = &ia32_reg_classes[CLASS_ia32_gp];
3132 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3133 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3140 assert(cls == NULL);
3141 cls = &ia32_reg_classes[CLASS_ia32_gp];
3147 /* TODO: mark values so the x87 simulator knows about t and u */
3148 assert(cls == NULL);
3149 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3154 assert(cls == NULL);
3155 /* TODO: check that sse2 is supported */
3156 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3166 assert(!immediate_possible);
3167 immediate_possible = 1;
3168 immediate_type = *c;
3172 assert(!immediate_possible);
3173 immediate_possible = 1;
3177 assert(!immediate_possible && cls == NULL);
3178 immediate_possible = 1;
3179 cls = &ia32_reg_classes[CLASS_ia32_gp];
3192 assert(constraint->is_in && "can only specify same constraint "
3195 sscanf(c, "%d%n", &same_as, &p);
3203 /* memory constraint no need to do anything in backend about it
3204 * (the dependencies are already respected by the memory edge of
3206 constraint->req = &no_register_req;
3209 case 'E': /* no float consts yet */
3210 case 'F': /* no float consts yet */
3211 case 's': /* makes no sense on x86 */
3212 case 'X': /* we can't support that in firm */
3215 case '<': /* no autodecrement on x86 */
3216 case '>': /* no autoincrement on x86 */
3217 case 'C': /* sse constant not supported yet */
3218 case 'G': /* 80387 constant not supported yet */
3219 case 'y': /* we don't support mmx registers yet */
3220 case 'Z': /* not available in 32 bit mode */
3221 case 'e': /* not available in 32 bit mode */
3222 panic("unsupported asm constraint '%c' found in (%+F)",
3223 *c, current_ir_graph);
3226 panic("unknown asm constraint '%c' found in (%+F)", *c,
3234 const arch_register_req_t *other_constr;
3236 assert(cls == NULL && "same as and register constraint not supported");
3237 assert(!immediate_possible && "same as and immediate constraint not "
3239 assert(same_as < constraint->n_outs && "wrong constraint number in "
3240 "same_as constraint");
3242 other_constr = constraint->out_reqs[same_as];
3244 req = obstack_alloc(obst, sizeof(req[0]));
3245 req->cls = other_constr->cls;
3246 req->type = arch_register_req_type_should_be_same;
3247 req->limited = NULL;
3248 req->other_same[0] = pos;
3249 req->other_same[1] = -1;
3250 req->other_different = -1;
3252 /* switch constraints. This is because in firm we have same_as
3253 * constraints on the output constraints while in the gcc asm syntax
3254 * they are specified on the input constraints */
3255 constraint->req = other_constr;
3256 constraint->out_reqs[same_as] = req;
3257 constraint->immediate_possible = 0;
3261 if(immediate_possible && cls == NULL) {
3262 cls = &ia32_reg_classes[CLASS_ia32_gp];
3264 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3265 assert(cls != NULL);
3267 if(immediate_possible) {
3268 assert(constraint->is_in
3269 && "immediate make no sense for output constraints");
3271 /* todo: check types (no float input on 'r' constrained in and such... */
3274 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3275 limited_ptr = (unsigned*) (req+1);
3277 req = obstack_alloc(obst, sizeof(req[0]));
3279 memset(req, 0, sizeof(req[0]));
3282 req->type = arch_register_req_type_limited;
3283 *limited_ptr = limited;
3284 req->limited = limited_ptr;
3286 req->type = arch_register_req_type_normal;
3290 constraint->req = req;
3291 constraint->immediate_possible = immediate_possible;
3292 constraint->immediate_type = immediate_type;
3295 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3302 panic("Clobbers not supported yet");
3305 static int is_memory_op(const ir_asm_constraint *constraint)
3307 ident *id = constraint->constraint;
3308 const char *str = get_id_str(id);
3311 for(c = str; *c != '\0'; ++c) {
3320 * generates code for a ASM node
3322 static ir_node *gen_ASM(ir_node *node)
3325 ir_graph *irg = current_ir_graph;
3326 ir_node *block = get_nodes_block(node);
3327 ir_node *new_block = be_transform_node(block);
3328 dbg_info *dbgi = get_irn_dbg_info(node);
3332 int n_out_constraints;
3334 const arch_register_req_t **out_reg_reqs;
3335 const arch_register_req_t **in_reg_reqs;
3336 ia32_asm_reg_t *register_map;
3337 unsigned reg_map_size = 0;
3338 struct obstack *obst;
3339 const ir_asm_constraint *in_constraints;
3340 const ir_asm_constraint *out_constraints;
3342 constraint_t parsed_constraint;
3344 arity = get_irn_arity(node);
3345 in = alloca(arity * sizeof(in[0]));
3346 memset(in, 0, arity * sizeof(in[0]));
3348 n_out_constraints = get_ASM_n_output_constraints(node);
3349 n_clobbers = get_ASM_n_clobbers(node);
3350 out_arity = n_out_constraints + n_clobbers;
3352 in_constraints = get_ASM_input_constraints(node);
3353 out_constraints = get_ASM_output_constraints(node);
3354 clobbers = get_ASM_clobbers(node);
3356 /* construct output constraints */
3357 obst = get_irg_obstack(irg);
3358 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
3359 parsed_constraint.out_reqs = out_reg_reqs;
3360 parsed_constraint.n_outs = n_out_constraints;
3361 parsed_constraint.is_in = 0;
3363 for(i = 0; i < out_arity; ++i) {
3366 if(i < n_out_constraints) {
3367 const ir_asm_constraint *constraint = &out_constraints[i];
3368 c = get_id_str(constraint->constraint);
3369 parse_asm_constraint(i, &parsed_constraint, c);
3371 if(constraint->pos > reg_map_size)
3372 reg_map_size = constraint->pos;
3374 ident *glob_id = clobbers [i - n_out_constraints];
3375 c = get_id_str(glob_id);
3376 parse_clobber(node, i, &parsed_constraint, c);
3379 out_reg_reqs[i] = parsed_constraint.req;
3382 /* construct input constraints */
3383 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
3384 parsed_constraint.is_in = 1;
3385 for(i = 0; i < arity; ++i) {
3386 const ir_asm_constraint *constraint = &in_constraints[i];
3387 ident *constr_id = constraint->constraint;
3388 const char *c = get_id_str(constr_id);
3390 parse_asm_constraint(i, &parsed_constraint, c);
3391 in_reg_reqs[i] = parsed_constraint.req;
3393 if(constraint->pos > reg_map_size)
3394 reg_map_size = constraint->pos;
3396 if(parsed_constraint.immediate_possible) {
3397 ir_node *pred = get_irn_n(node, i);
3398 char imm_type = parsed_constraint.immediate_type;
3399 ir_node *immediate = try_create_Immediate(pred, imm_type);
3401 if(immediate != NULL) {
3408 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
3409 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
3411 for(i = 0; i < n_out_constraints; ++i) {
3412 const ir_asm_constraint *constraint = &out_constraints[i];
3413 unsigned pos = constraint->pos;
3415 assert(pos < reg_map_size);
3416 register_map[pos].use_input = 0;
3417 register_map[pos].valid = 1;
3418 register_map[pos].memory = is_memory_op(constraint);
3419 register_map[pos].inout_pos = i;
3420 register_map[pos].mode = constraint->mode;
3423 /* transform inputs */
3424 for(i = 0; i < arity; ++i) {
3425 const ir_asm_constraint *constraint = &in_constraints[i];
3426 unsigned pos = constraint->pos;
3427 ir_node *pred = get_irn_n(node, i);
3428 ir_node *transformed;
3430 assert(pos < reg_map_size);
3431 register_map[pos].use_input = 1;
3432 register_map[pos].valid = 1;
3433 register_map[pos].memory = is_memory_op(constraint);
3434 register_map[pos].inout_pos = i;
3435 register_map[pos].mode = constraint->mode;
3440 transformed = be_transform_node(pred);
3441 in[i] = transformed;
3444 res = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
3445 get_ASM_text(node), register_map);
3447 set_ia32_out_req_all(res, out_reg_reqs);
3448 set_ia32_in_req_all(res, in_reg_reqs);
3450 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3455 /********************************************
3458 * | |__ ___ _ __ ___ __| | ___ ___
3459 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3460 * | |_) | __/ | | | (_) | (_| | __/\__ \
3461 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3463 ********************************************/
3466 * Transforms a FrameAddr into an ia32 Add.
3468 static ir_node *gen_be_FrameAddr(ir_node *node) {
3469 ir_node *block = be_transform_node(get_nodes_block(node));
3470 ir_node *op = be_get_FrameAddr_frame(node);
3471 ir_node *new_op = be_transform_node(op);
3472 ir_graph *irg = current_ir_graph;
3473 dbg_info *dbgi = get_irn_dbg_info(node);
3474 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3477 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3478 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3479 set_ia32_use_frame(res);
3481 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3487 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3489 static ir_node *gen_be_Return(ir_node *node) {
3490 ir_graph *irg = current_ir_graph;
3491 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3492 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3493 ir_entity *ent = get_irg_entity(irg);
3494 ir_type *tp = get_entity_type(ent);
3499 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3500 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3503 int pn_ret_val, pn_ret_mem, arity, i;
3505 assert(ret_val != NULL);
3506 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3507 return be_duplicate_node(node);
3510 res_type = get_method_res_type(tp, 0);
3512 if (! is_Primitive_type(res_type)) {
3513 return be_duplicate_node(node);
3516 mode = get_type_mode(res_type);
3517 if (! mode_is_float(mode)) {
3518 return be_duplicate_node(node);
3521 assert(get_method_n_ress(tp) == 1);
3523 pn_ret_val = get_Proj_proj(ret_val);
3524 pn_ret_mem = get_Proj_proj(ret_mem);
3526 /* get the Barrier */
3527 barrier = get_Proj_pred(ret_val);
3529 /* get result input of the Barrier */
3530 ret_val = get_irn_n(barrier, pn_ret_val);
3531 new_ret_val = be_transform_node(ret_val);
3533 /* get memory input of the Barrier */
3534 ret_mem = get_irn_n(barrier, pn_ret_mem);
3535 new_ret_mem = be_transform_node(ret_mem);
3537 frame = get_irg_frame(irg);
3539 dbgi = get_irn_dbg_info(barrier);
3540 block = be_transform_node(get_nodes_block(barrier));
3542 noreg = ia32_new_NoReg_gp(env_cg);
3544 /* store xmm0 onto stack */
3545 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3546 new_ret_mem, new_ret_val);
3547 set_ia32_ls_mode(sse_store, mode);
3548 set_ia32_op_type(sse_store, ia32_AddrModeD);
3549 set_ia32_use_frame(sse_store);
3551 /* load into x87 register */
3552 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3553 set_ia32_op_type(fld, ia32_AddrModeS);
3554 set_ia32_use_frame(fld);
3556 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3557 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3559 /* create a new barrier */
3560 arity = get_irn_arity(barrier);
3561 in = alloca(arity * sizeof(in[0]));
3562 for (i = 0; i < arity; ++i) {
3565 if (i == pn_ret_val) {
3567 } else if (i == pn_ret_mem) {
3570 ir_node *in = get_irn_n(barrier, i);
3571 new_in = be_transform_node(in);
3576 new_barrier = new_ir_node(dbgi, irg, block,
3577 get_irn_op(barrier), get_irn_mode(barrier),
3579 copy_node_attr(barrier, new_barrier);
3580 be_duplicate_deps(barrier, new_barrier);
3581 be_set_transformed_node(barrier, new_barrier);
3582 mark_irn_visited(barrier);
3584 /* transform normally */
3585 return be_duplicate_node(node);
3589 * Transform a be_AddSP into an ia32_SubSP.
3591 static ir_node *gen_be_AddSP(ir_node *node)
3593 ir_node *src_block = get_nodes_block(node);
3594 ir_node *new_block = be_transform_node(src_block);
3595 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3596 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3597 ir_graph *irg = current_ir_graph;
3598 dbg_info *dbgi = get_irn_dbg_info(node);
3600 ia32_address_mode_t am;
3601 ia32_address_t *addr = &am.addr;
3602 match_flags_t flags = 0;
3604 match_arguments(&am, src_block, sp, sz, flags);
3606 new_node = new_rd_ia32_SubSP(dbgi, irg, new_block, addr->base, addr->index,
3607 addr->mem, am.new_op1, am.new_op2);
3608 set_am_attributes(new_node, &am);
3609 /* we can't use source address mode anymore when using immediates */
3610 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3611 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3612 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3614 new_node = fix_mem_proj(new_node, &am);
3620 * Transform a be_SubSP into an ia32_AddSP
3622 static ir_node *gen_be_SubSP(ir_node *node)
3624 ir_node *src_block = get_nodes_block(node);
3625 ir_node *new_block = be_transform_node(src_block);
3626 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3627 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3628 ir_graph *irg = current_ir_graph;
3629 dbg_info *dbgi = get_irn_dbg_info(node);
3631 ia32_address_mode_t am;
3632 ia32_address_t *addr = &am.addr;
3633 match_flags_t flags = 0;
3635 match_arguments(&am, src_block, sp, sz, flags);
3637 new_node = new_rd_ia32_AddSP(dbgi, irg, new_block, addr->base, addr->index,
3638 addr->mem, am.new_op1, am.new_op2);
3639 set_am_attributes(new_node, &am);
3640 /* we can't use source address mode anymore when using immediates */
3641 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3642 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3643 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3645 new_node = fix_mem_proj(new_node, &am);
3651 * This function just sets the register for the Unknown node
3652 * as this is not done during register allocation because Unknown
3653 * is an "ignore" node.
3655 static ir_node *gen_Unknown(ir_node *node) {
3656 ir_mode *mode = get_irn_mode(node);
3658 if (mode_is_float(mode)) {
3659 if (USE_SSE2(env_cg)) {
3660 return ia32_new_Unknown_xmm(env_cg);
3662 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3663 ir_graph *irg = current_ir_graph;
3664 dbg_info *dbgi = get_irn_dbg_info(node);
3665 ir_node *block = get_irg_start_block(irg);
3666 return new_rd_ia32_vfldz(dbgi, irg, block);
3668 } else if (mode_needs_gp_reg(mode)) {
3669 return ia32_new_Unknown_gp(env_cg);
3671 assert(0 && "unsupported Unknown-Mode");
3678 * Change some phi modes
3680 static ir_node *gen_Phi(ir_node *node) {
3681 ir_node *block = be_transform_node(get_nodes_block(node));
3682 ir_graph *irg = current_ir_graph;
3683 dbg_info *dbgi = get_irn_dbg_info(node);
3684 ir_mode *mode = get_irn_mode(node);
3687 if(mode_needs_gp_reg(mode)) {
3688 /* we shouldn't have any 64bit stuff around anymore */
3689 assert(get_mode_size_bits(mode) <= 32);
3690 /* all integer operations are on 32bit registers now */
3692 } else if(mode_is_float(mode)) {
3693 if (USE_SSE2(env_cg)) {
3700 /* phi nodes allow loops, so we use the old arguments for now
3701 * and fix this later */
3702 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3703 get_irn_in(node) + 1);
3704 copy_node_attr(node, phi);
3705 be_duplicate_deps(node, phi);
3707 be_set_transformed_node(node, phi);
3708 be_enqueue_preds(node);
3716 static ir_node *gen_IJmp(ir_node *node)
3718 ir_node *block = get_nodes_block(node);
3719 ir_node *new_block = be_transform_node(block);
3720 ir_graph *irg = current_ir_graph;
3721 dbg_info *dbgi = get_irn_dbg_info(node);
3722 ir_node *op = get_IJmp_target(node);
3724 ia32_address_mode_t am;
3725 ia32_address_t *addr = &am.addr;
3726 match_flags_t flags;
3728 flags = match_force_32bit_op | match_no_immediate;
3730 match_arguments(&am, block, NULL, op, flags);
3732 new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index,
3733 addr->mem, am.new_op2);
3734 set_am_attributes(new_node, &am);
3735 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3737 new_node = fix_mem_proj(new_node, &am);
3743 /**********************************************************************
3746 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3747 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3748 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3749 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3751 **********************************************************************/
3753 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3755 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3758 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3759 ir_node *val, ir_node *mem);
3762 * Transforms a lowered Load into a "real" one.
3764 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3766 ir_node *block = be_transform_node(get_nodes_block(node));
3767 ir_node *ptr = get_irn_n(node, 0);
3768 ir_node *new_ptr = be_transform_node(ptr);
3769 ir_node *mem = get_irn_n(node, 1);
3770 ir_node *new_mem = be_transform_node(mem);
3771 ir_graph *irg = current_ir_graph;
3772 dbg_info *dbgi = get_irn_dbg_info(node);
3773 ir_mode *mode = get_ia32_ls_mode(node);
3774 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3777 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3779 set_ia32_op_type(new_op, ia32_AddrModeS);
3780 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3781 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3782 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3783 if (is_ia32_am_sc_sign(node))
3784 set_ia32_am_sc_sign(new_op);
3785 set_ia32_ls_mode(new_op, mode);
3786 if (is_ia32_use_frame(node)) {
3787 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3788 set_ia32_use_frame(new_op);
3791 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3797 * Transforms a lowered Store into a "real" one.
3799 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3801 ir_node *block = be_transform_node(get_nodes_block(node));
3802 ir_node *ptr = get_irn_n(node, 0);
3803 ir_node *new_ptr = be_transform_node(ptr);
3804 ir_node *val = get_irn_n(node, 1);
3805 ir_node *new_val = be_transform_node(val);
3806 ir_node *mem = get_irn_n(node, 2);
3807 ir_node *new_mem = be_transform_node(mem);
3808 ir_graph *irg = current_ir_graph;
3809 dbg_info *dbgi = get_irn_dbg_info(node);
3810 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3811 ir_mode *mode = get_ia32_ls_mode(node);
3815 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3817 am_offs = get_ia32_am_offs_int(node);
3818 add_ia32_am_offs_int(new_op, am_offs);
3820 set_ia32_op_type(new_op, ia32_AddrModeD);
3821 set_ia32_ls_mode(new_op, mode);
3822 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3823 set_ia32_use_frame(new_op);
3825 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3832 * Transforms an ia32_l_XXX into a "real" XXX node
3834 * @param node The node to transform
3835 * @return the created ia32 XXX node
3837 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3838 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3839 return gen_shift_binop(node, get_irn_n(node, 0), \
3840 get_irn_n(node, 1), new_rd_ia32_##op); \
3843 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3844 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3845 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3847 static ir_node *gen_ia32_l_Add(ir_node *node) {
3848 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3849 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3850 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, match_commutative);
3852 if(is_Proj(lowered)) {
3853 lowered = get_Proj_pred(lowered);
3855 assert(is_ia32_Add(lowered));
3856 set_irn_mode(lowered, mode_T);
3862 static ir_node *gen_ia32_l_Adc(ir_node *node)
3864 return gen_binop_flags(node, new_rd_ia32_Adc, match_commutative);
3868 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3870 * @param node The node to transform
3871 * @return the created ia32 Neg node
3873 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3874 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3878 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3880 * @param node The node to transform
3881 * @return the created ia32 vfild node
3883 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3884 return gen_lowered_Load(node, new_rd_ia32_vfild);
3888 * Transforms an ia32_l_Load into a "real" ia32_Load node
3890 * @param node The node to transform
3891 * @return the created ia32 Load node
3893 static ir_node *gen_ia32_l_Load(ir_node *node) {
3894 return gen_lowered_Load(node, new_rd_ia32_Load);
3898 * Transforms an ia32_l_Store into a "real" ia32_Store node
3900 * @param node The node to transform
3901 * @return the created ia32 Store node
3903 static ir_node *gen_ia32_l_Store(ir_node *node) {
3904 return gen_lowered_Store(node, new_rd_ia32_Store);
3908 * Transforms a l_vfist into a "real" vfist node.
3910 * @param node The node to transform
3911 * @return the created ia32 vfist node
3913 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3914 ir_node *block = be_transform_node(get_nodes_block(node));
3915 ir_node *ptr = get_irn_n(node, 0);
3916 ir_node *new_ptr = be_transform_node(ptr);
3917 ir_node *val = get_irn_n(node, 1);
3918 ir_node *new_val = be_transform_node(val);
3919 ir_node *mem = get_irn_n(node, 2);
3920 ir_node *new_mem = be_transform_node(mem);
3921 ir_graph *irg = current_ir_graph;
3922 dbg_info *dbgi = get_irn_dbg_info(node);
3923 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3924 ir_mode *mode = get_ia32_ls_mode(node);
3925 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3929 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3930 new_val, trunc_mode);
3932 am_offs = get_ia32_am_offs_int(node);
3933 add_ia32_am_offs_int(new_op, am_offs);
3935 set_ia32_op_type(new_op, ia32_AddrModeD);
3936 set_ia32_ls_mode(new_op, mode);
3937 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3938 set_ia32_use_frame(new_op);
3940 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3946 * Transforms a l_MulS into a "real" MulS node.
3948 * @return the created ia32 Mul node
3950 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3951 ir_node *left = get_binop_left(node);
3952 ir_node *right = get_binop_right(node);
3954 return gen_binop(node, left, right, new_rd_ia32_Mul,
3955 match_commutative | match_no_immediate);
3959 * Transforms a l_IMulS into a "real" IMul1OPS node.
3961 * @return the created ia32 IMul1OP node
3963 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3964 ir_node *left = get_binop_left(node);
3965 ir_node *right = get_binop_right(node);
3967 return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
3968 match_commutative | match_no_immediate);
3971 static ir_node *gen_ia32_l_Sub(ir_node *node) {
3972 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
3973 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
3974 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, 0);
3976 if(is_Proj(lowered)) {
3977 lowered = get_Proj_pred(lowered);
3979 assert(is_ia32_Sub(lowered));
3980 set_irn_mode(lowered, mode_T);
3986 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
3987 return gen_binop_flags(node, new_rd_ia32_Sbb, 0);
3991 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3992 * op1 - target to be shifted
3993 * op2 - contains bits to be shifted into target
3995 * Only op3 can be an immediate.
3997 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3998 ir_node *op2, ir_node *count)
4000 ir_node *block = be_transform_node(get_nodes_block(node));
4001 ir_node *new_op = NULL;
4002 ir_graph *irg = current_ir_graph;
4003 dbg_info *dbgi = get_irn_dbg_info(node);
4004 ir_node *new_op1 = be_transform_node(op1);
4005 ir_node *new_op2 = be_transform_node(op2);
4006 ir_node *new_count = create_immediate_or_transform(count, 'I');
4008 /* TODO proper AM support */
4010 if (is_ia32_l_ShlD(node))
4011 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
4013 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
4015 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
4020 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
4021 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
4022 get_irn_n(node, 1), get_irn_n(node, 2));
4025 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
4026 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
4027 get_irn_n(node, 1), get_irn_n(node, 2));
4031 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
4033 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
4034 ir_node *block = be_transform_node(get_nodes_block(node));
4035 ir_node *val = get_irn_n(node, 1);
4036 ir_node *new_val = be_transform_node(val);
4037 ia32_code_gen_t *cg = env_cg;
4038 ir_node *res = NULL;
4039 ir_graph *irg = current_ir_graph;
4041 ir_node *noreg, *new_ptr, *new_mem;
4048 mem = get_irn_n(node, 2);
4049 new_mem = be_transform_node(mem);
4050 ptr = get_irn_n(node, 0);
4051 new_ptr = be_transform_node(ptr);
4052 noreg = ia32_new_NoReg_gp(cg);
4053 dbgi = get_irn_dbg_info(node);
4055 /* Store x87 -> MEM */
4056 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
4057 get_ia32_ls_mode(node));
4058 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4059 set_ia32_use_frame(res);
4060 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
4061 set_ia32_op_type(res, ia32_AddrModeD);
4063 /* Load MEM -> SSE */
4064 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
4065 get_ia32_ls_mode(node));
4066 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4067 set_ia32_use_frame(res);
4068 set_ia32_op_type(res, ia32_AddrModeS);
4069 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
4075 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
4077 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
4078 ir_node *block = be_transform_node(get_nodes_block(node));
4079 ir_node *val = get_irn_n(node, 1);
4080 ir_node *new_val = be_transform_node(val);
4081 ia32_code_gen_t *cg = env_cg;
4082 ir_graph *irg = current_ir_graph;
4083 ir_node *res = NULL;
4084 ir_entity *fent = get_ia32_frame_ent(node);
4085 ir_mode *lsmode = get_ia32_ls_mode(node);
4087 ir_node *noreg, *new_ptr, *new_mem;
4091 if (! USE_SSE2(cg)) {
4092 /* SSE unit is not used -> skip this node. */
4096 ptr = get_irn_n(node, 0);
4097 new_ptr = be_transform_node(ptr);
4098 mem = get_irn_n(node, 2);
4099 new_mem = be_transform_node(mem);
4100 noreg = ia32_new_NoReg_gp(cg);
4101 dbgi = get_irn_dbg_info(node);
4103 /* Store SSE -> MEM */
4104 if (is_ia32_xLoad(skip_Proj(new_val))) {
4105 ir_node *ld = skip_Proj(new_val);
4107 /* we can vfld the value directly into the fpu */
4108 fent = get_ia32_frame_ent(ld);
4109 ptr = get_irn_n(ld, 0);
4110 offs = get_ia32_am_offs_int(ld);
4112 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
4114 set_ia32_frame_ent(res, fent);
4115 set_ia32_use_frame(res);
4116 set_ia32_ls_mode(res, lsmode);
4117 set_ia32_op_type(res, ia32_AddrModeD);
4121 /* Load MEM -> x87 */
4122 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4123 set_ia32_frame_ent(res, fent);
4124 set_ia32_use_frame(res);
4125 add_ia32_am_offs_int(res, offs);
4126 set_ia32_op_type(res, ia32_AddrModeS);
4127 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4132 /*********************************************************
4135 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
4136 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
4137 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4138 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4140 *********************************************************/
4143 * the BAD transformer.
4145 static ir_node *bad_transform(ir_node *node) {
4146 panic("No transform function for %+F available.\n", node);
4151 * Transform the Projs of an AddSP.
4153 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4154 ir_node *block = be_transform_node(get_nodes_block(node));
4155 ir_node *pred = get_Proj_pred(node);
4156 ir_node *new_pred = be_transform_node(pred);
4157 ir_graph *irg = current_ir_graph;
4158 dbg_info *dbgi = get_irn_dbg_info(node);
4159 long proj = get_Proj_proj(node);
4161 if (proj == pn_be_AddSP_sp) {
4162 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4163 pn_ia32_SubSP_stack);
4164 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4166 } else if(proj == pn_be_AddSP_res) {
4167 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4168 pn_ia32_SubSP_addr);
4169 } else if (proj == pn_be_AddSP_M) {
4170 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4174 return new_rd_Unknown(irg, get_irn_mode(node));
4178 * Transform the Projs of a SubSP.
4180 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4181 ir_node *block = be_transform_node(get_nodes_block(node));
4182 ir_node *pred = get_Proj_pred(node);
4183 ir_node *new_pred = be_transform_node(pred);
4184 ir_graph *irg = current_ir_graph;
4185 dbg_info *dbgi = get_irn_dbg_info(node);
4186 long proj = get_Proj_proj(node);
4188 if (proj == pn_be_SubSP_sp) {
4189 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4190 pn_ia32_AddSP_stack);
4191 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4193 } else if (proj == pn_be_SubSP_M) {
4194 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4198 return new_rd_Unknown(irg, get_irn_mode(node));
4202 * Transform and renumber the Projs from a Load.
4204 static ir_node *gen_Proj_Load(ir_node *node) {
4206 ir_node *block = be_transform_node(get_nodes_block(node));
4207 ir_node *pred = get_Proj_pred(node);
4208 ir_graph *irg = current_ir_graph;
4209 dbg_info *dbgi = get_irn_dbg_info(node);
4210 long proj = get_Proj_proj(node);
4213 /* loads might be part of source address mode matches, so we don't
4214 transform the ProjMs yet (with the exception of loads whose result is
4217 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4220 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4222 /* this is needed, because sometimes we have loops that are only
4223 reachable through the ProjM */
4224 be_enqueue_preds(node);
4225 /* do it in 2 steps, to silence firm verifier */
4226 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4227 set_Proj_proj(res, pn_ia32_Load_M);
4231 /* renumber the proj */
4232 new_pred = be_transform_node(pred);
4233 if (is_ia32_Load(new_pred)) {
4234 if (proj == pn_Load_res) {
4235 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4237 } else if (proj == pn_Load_M) {
4238 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4241 } else if(is_ia32_Conv_I2I(new_pred)
4242 || is_ia32_Conv_I2I8Bit(new_pred)) {
4243 set_irn_mode(new_pred, mode_T);
4244 if (proj == pn_Load_res) {
4245 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4246 } else if (proj == pn_Load_M) {
4247 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4249 } else if (is_ia32_xLoad(new_pred)) {
4250 if (proj == pn_Load_res) {
4251 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4253 } else if (proj == pn_Load_M) {
4254 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4257 } else if (is_ia32_vfld(new_pred)) {
4258 if (proj == pn_Load_res) {
4259 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4261 } else if (proj == pn_Load_M) {
4262 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4266 /* can happen for ProJMs when source address mode happened for the
4269 /* however it should not be the result proj, as that would mean the
4270 load had multiple users and should not have been used for
4272 if(proj != pn_Load_M) {
4273 panic("internal error: transformed node not a Load");
4275 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4279 return new_rd_Unknown(irg, get_irn_mode(node));
4283 * Transform and renumber the Projs from a DivMod like instruction.
4285 static ir_node *gen_Proj_DivMod(ir_node *node) {
4286 ir_node *block = be_transform_node(get_nodes_block(node));
4287 ir_node *pred = get_Proj_pred(node);
4288 ir_node *new_pred = be_transform_node(pred);
4289 ir_graph *irg = current_ir_graph;
4290 dbg_info *dbgi = get_irn_dbg_info(node);
4291 ir_mode *mode = get_irn_mode(node);
4292 long proj = get_Proj_proj(node);
4294 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4296 switch (get_irn_opcode(pred)) {
4300 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4302 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4310 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4312 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4320 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4321 case pn_DivMod_res_div:
4322 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4323 case pn_DivMod_res_mod:
4324 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4334 return new_rd_Unknown(irg, mode);
4338 * Transform and renumber the Projs from a CopyB.
4340 static ir_node *gen_Proj_CopyB(ir_node *node) {
4341 ir_node *block = be_transform_node(get_nodes_block(node));
4342 ir_node *pred = get_Proj_pred(node);
4343 ir_node *new_pred = be_transform_node(pred);
4344 ir_graph *irg = current_ir_graph;
4345 dbg_info *dbgi = get_irn_dbg_info(node);
4346 ir_mode *mode = get_irn_mode(node);
4347 long proj = get_Proj_proj(node);
4350 case pn_CopyB_M_regular:
4351 if (is_ia32_CopyB_i(new_pred)) {
4352 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4353 } else if (is_ia32_CopyB(new_pred)) {
4354 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4362 return new_rd_Unknown(irg, mode);
4366 * Transform and renumber the Projs from a Quot.
4368 static ir_node *gen_Proj_Quot(ir_node *node) {
4369 ir_node *block = be_transform_node(get_nodes_block(node));
4370 ir_node *pred = get_Proj_pred(node);
4371 ir_node *new_pred = be_transform_node(pred);
4372 ir_graph *irg = current_ir_graph;
4373 dbg_info *dbgi = get_irn_dbg_info(node);
4374 ir_mode *mode = get_irn_mode(node);
4375 long proj = get_Proj_proj(node);
4379 if (is_ia32_xDiv(new_pred)) {
4380 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4381 } else if (is_ia32_vfdiv(new_pred)) {
4382 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4386 if (is_ia32_xDiv(new_pred)) {
4387 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4388 } else if (is_ia32_vfdiv(new_pred)) {
4389 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4397 return new_rd_Unknown(irg, mode);
4401 * Transform the Thread Local Storage Proj.
4403 static ir_node *gen_Proj_tls(ir_node *node) {
4404 ir_node *block = be_transform_node(get_nodes_block(node));
4405 ir_graph *irg = current_ir_graph;
4406 dbg_info *dbgi = NULL;
4407 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4412 static ir_node *gen_be_Call(ir_node *node) {
4413 ir_node *res = be_duplicate_node(node);
4414 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4419 static ir_node *gen_be_IncSP(ir_node *node) {
4420 ir_node *res = be_duplicate_node(node);
4421 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4427 * Transform the Projs from a be_Call.
4429 static ir_node *gen_Proj_be_Call(ir_node *node) {
4430 ir_node *block = be_transform_node(get_nodes_block(node));
4431 ir_node *call = get_Proj_pred(node);
4432 ir_node *new_call = be_transform_node(call);
4433 ir_graph *irg = current_ir_graph;
4434 dbg_info *dbgi = get_irn_dbg_info(node);
4435 ir_type *method_type = be_Call_get_type(call);
4436 int n_res = get_method_n_ress(method_type);
4437 long proj = get_Proj_proj(node);
4438 ir_mode *mode = get_irn_mode(node);
4440 const arch_register_class_t *cls;
4442 /* The following is kinda tricky: If we're using SSE, then we have to
4443 * move the result value of the call in floating point registers to an
4444 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4445 * after the call, we have to make sure to correctly make the
4446 * MemProj and the result Proj use these 2 nodes
4448 if (proj == pn_be_Call_M_regular) {
4449 // get new node for result, are we doing the sse load/store hack?
4450 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4451 ir_node *call_res_new;
4452 ir_node *call_res_pred = NULL;
4454 if (call_res != NULL) {
4455 call_res_new = be_transform_node(call_res);
4456 call_res_pred = get_Proj_pred(call_res_new);
4459 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4460 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4461 pn_be_Call_M_regular);
4463 assert(is_ia32_xLoad(call_res_pred));
4464 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4468 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4469 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4470 && USE_SSE2(env_cg)) {
4472 ir_node *frame = get_irg_frame(irg);
4473 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4475 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4478 /* in case there is no memory output: create one to serialize the copy
4480 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4481 pn_be_Call_M_regular);
4482 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4483 pn_be_Call_first_res);
4485 /* store st(0) onto stack */
4486 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4488 set_ia32_op_type(fstp, ia32_AddrModeD);
4489 set_ia32_use_frame(fstp);
4491 /* load into SSE register */
4492 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4494 set_ia32_op_type(sse_load, ia32_AddrModeS);
4495 set_ia32_use_frame(sse_load);
4497 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4503 /* transform call modes */
4504 if (mode_is_data(mode)) {
4505 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4509 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4513 * Transform the Projs from a Cmp.
4515 static ir_node *gen_Proj_Cmp(ir_node *node)
4517 /* normally Cmps are processed when looking at Cond nodes, but this case
4518 * can happen in complicated Psi conditions */
4519 dbg_info *dbgi = get_irn_dbg_info(node);
4520 ir_node *block = get_nodes_block(node);
4521 ir_node *new_block = be_transform_node(block);
4522 ir_node *cmp = get_Proj_pred(node);
4523 ir_node *new_cmp = be_transform_node(cmp);
4524 long pnc = get_Proj_proj(node);
4527 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node, 0);
4533 * Transform and potentially renumber Proj nodes.
4535 static ir_node *gen_Proj(ir_node *node) {
4536 ir_graph *irg = current_ir_graph;
4537 dbg_info *dbgi = get_irn_dbg_info(node);
4538 ir_node *pred = get_Proj_pred(node);
4539 long proj = get_Proj_proj(node);
4541 if (is_Store(pred)) {
4542 if (proj == pn_Store_M) {
4543 return be_transform_node(pred);
4546 return new_r_Bad(irg);
4548 } else if (is_Load(pred)) {
4549 return gen_Proj_Load(node);
4550 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4551 return gen_Proj_DivMod(node);
4552 } else if (is_CopyB(pred)) {
4553 return gen_Proj_CopyB(node);
4554 } else if (is_Quot(pred)) {
4555 return gen_Proj_Quot(node);
4556 } else if (be_is_SubSP(pred)) {
4557 return gen_Proj_be_SubSP(node);
4558 } else if (be_is_AddSP(pred)) {
4559 return gen_Proj_be_AddSP(node);
4560 } else if (be_is_Call(pred)) {
4561 return gen_Proj_be_Call(node);
4562 } else if (is_Cmp(pred)) {
4563 return gen_Proj_Cmp(node);
4564 } else if (get_irn_op(pred) == op_Start) {
4565 if (proj == pn_Start_X_initial_exec) {
4566 ir_node *block = get_nodes_block(pred);
4569 /* we exchange the ProjX with a jump */
4570 block = be_transform_node(block);
4571 jump = new_rd_Jmp(dbgi, irg, block);
4574 if (node == be_get_old_anchor(anchor_tls)) {
4575 return gen_Proj_tls(node);
4578 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4582 ir_node *new_pred = be_transform_node(pred);
4583 ir_node *block = be_transform_node(get_nodes_block(node));
4584 ir_mode *mode = get_irn_mode(node);
4585 if (mode_needs_gp_reg(mode)) {
4586 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4587 get_Proj_proj(node));
4588 #ifdef DEBUG_libfirm
4589 new_proj->node_nr = node->node_nr;
4595 return be_duplicate_node(node);
4599 * Enters all transform functions into the generic pointer
4601 static void register_transformers(void)
4605 /* first clear the generic function pointer for all ops */
4606 clear_irp_opcodes_generic_func();
4608 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4609 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4647 /* transform ops from intrinsic lowering */
4664 GEN(ia32_l_X87toSSE);
4665 GEN(ia32_l_SSEtoX87);
4671 /* we should never see these nodes */
4686 /* handle generic backend nodes */
4695 op_Mulh = get_op_Mulh();
4704 * Pre-transform all unknown and noreg nodes.
4706 static void ia32_pretransform_node(void *arch_cg) {
4707 ia32_code_gen_t *cg = arch_cg;
4709 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4710 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4711 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4712 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4713 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4714 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4719 * Walker, checks if all ia32 nodes producing more than one result have
4720 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4722 static void add_missing_keep_walker(ir_node *node, void *data)
4725 unsigned found_projs = 0;
4726 const ir_edge_t *edge;
4727 ir_mode *mode = get_irn_mode(node);
4732 if(!is_ia32_irn(node))
4735 n_outs = get_ia32_n_res(node);
4738 if(is_ia32_SwitchJmp(node))
4741 assert(n_outs < (int) sizeof(unsigned) * 8);
4742 foreach_out_edge(node, edge) {
4743 ir_node *proj = get_edge_src_irn(edge);
4744 int pn = get_Proj_proj(proj);
4746 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4747 found_projs |= 1 << pn;
4751 /* are keeps missing? */
4753 for(i = 0; i < n_outs; ++i) {
4756 const arch_register_req_t *req;
4757 const arch_register_class_t *class;
4759 if(found_projs & (1 << i)) {
4763 req = get_ia32_out_req(node, i);
4768 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4772 block = get_nodes_block(node);
4773 in[0] = new_r_Proj(current_ir_graph, block, node,
4774 arch_register_class_mode(class), i);
4775 if(last_keep != NULL) {
4776 be_Keep_add_node(last_keep, class, in[0]);
4778 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4779 if(sched_is_scheduled(node)) {
4780 sched_add_after(node, last_keep);
4787 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4790 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4792 ir_graph *irg = be_get_birg_irg(cg->birg);
4793 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4796 /* do the transformation */
4797 void ia32_transform_graph(ia32_code_gen_t *cg) {
4799 ir_graph *irg = cg->irg;
4800 int opt_arch = cg->isa->opt_arch;
4801 int arch = cg->isa->arch;
4803 /* TODO: look at cpu and fill transform config in with that... */
4804 transform_config.use_incdec = 1;
4805 transform_config.use_sse2 = 0;
4806 transform_config.use_ffreep = ARCH_ATHLON(opt_arch);
4807 transform_config.use_ftst = 0;
4808 transform_config.use_femms = ARCH_ATHLON(opt_arch) && ARCH_MMX(arch) && ARCH_AMD(arch);
4809 transform_config.use_fucomi = 1;
4810 transform_config.use_cmov = IS_P6_ARCH(arch);
4812 register_transformers();
4814 initial_fpcw = NULL;
4816 heights = heights_new(irg);
4817 calculate_non_address_mode_nodes(irg);
4819 /* the transform phase is not safe for CSE (yet) because several nodes get
4820 * attributes set after their creation */
4821 cse_last = get_opt_cse();
4824 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4826 set_opt_cse(cse_last);
4828 free_non_address_mode_nodes();
4829 heights_free(heights);
4833 void ia32_init_transform(void)
4835 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");