2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
50 #include "../benode_t.h"
51 #include "../besched.h"
53 #include "../beutil.h"
54 #include "../beirg_t.h"
55 #include "../betranshlp.h"
57 #include "bearch_ia32_t.h"
58 #include "ia32_nodes_attr.h"
59 #include "ia32_transform.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_dbg_stat.h"
63 #include "ia32_optimize.h"
64 #include "ia32_util.h"
66 #include "gen_ia32_regalloc_if.h"
68 #define SFP_SIGN "0x80000000"
69 #define DFP_SIGN "0x8000000000000000"
70 #define SFP_ABS "0x7FFFFFFF"
71 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
73 #define TP_SFP_SIGN "ia32_sfp_sign"
74 #define TP_DFP_SIGN "ia32_dfp_sign"
75 #define TP_SFP_ABS "ia32_sfp_abs"
76 #define TP_DFP_ABS "ia32_dfp_abs"
78 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
79 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
80 #define ENT_SFP_ABS "IA32_SFP_ABS"
81 #define ENT_DFP_ABS "IA32_DFP_ABS"
83 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
84 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
86 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
88 /** hold the current code generator during transformation */
89 static ia32_code_gen_t *env_cg = NULL;
90 static ir_node *initial_fpcw = NULL;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
119 static ir_node *create_immediate_or_transform(ir_node *node,
120 char immediate_constraint_type);
122 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
123 dbg_info *dbgi, ir_node *new_block,
127 * Return true if a mode can be stored in the GP register set
129 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
130 if(mode == mode_fpcw)
132 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
136 * Returns 1 if irn is a Const representing 0, 0 otherwise
138 static INLINE int is_ia32_Const_0(ir_node *irn) {
139 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
140 && tarval_is_null(get_ia32_Immop_tarval(irn));
144 * Returns 1 if irn is a Const representing 1, 0 otherwise
146 static INLINE int is_ia32_Const_1(ir_node *irn) {
147 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
148 && tarval_is_one(get_ia32_Immop_tarval(irn));
152 * Collects all Projs of a node into the node array. Index is the projnum.
153 * BEWARE: The caller has to assure the appropriate array size!
155 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
156 const ir_edge_t *edge;
157 assert(get_irn_mode(irn) == mode_T && "need mode_T");
159 memset(projs, 0, size * sizeof(projs[0]));
161 foreach_out_edge(irn, edge) {
162 ir_node *proj = get_edge_src_irn(edge);
163 int proj_proj = get_Proj_proj(proj);
164 assert(proj_proj < size);
165 projs[proj_proj] = proj;
170 * Renumbers the proj having pn_old in the array tp pn_new
171 * and removes the proj from the array.
173 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
174 fprintf(stderr, "Warning: renumber_Proj used!\n");
176 set_Proj_proj(projs[pn_old], pn_new);
177 projs[pn_old] = NULL;
182 * creates a unique ident by adding a number to a tag
184 * @param tag the tag string, must contain a %d if a number
187 static ident *unique_id(const char *tag)
189 static unsigned id = 0;
192 snprintf(str, sizeof(str), tag, ++id);
193 return new_id_from_str(str);
197 * Get a primitive type for a mode.
199 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
201 pmap_entry *e = pmap_find(types, mode);
206 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
207 res = new_type_primitive(new_id_from_str(buf), mode);
208 set_type_alignment_bytes(res, 16);
209 pmap_insert(types, mode, res);
217 * Get an entity that is initialized with a tarval
219 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
221 tarval *tv = get_Const_tarval(cnst);
222 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
227 ir_mode *mode = get_irn_mode(cnst);
228 ir_type *tp = get_Const_type(cnst);
229 if (tp == firm_unknown_type)
230 tp = get_prim_type(cg->isa->types, mode);
232 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
234 set_entity_ld_ident(res, get_entity_ident(res));
235 set_entity_visibility(res, visibility_local);
236 set_entity_variability(res, variability_constant);
237 set_entity_allocation(res, allocation_static);
239 /* we create a new entity here: It's initialization must resist on the
241 rem = current_ir_graph;
242 current_ir_graph = get_const_code_irg();
243 set_atomic_ent_value(res, new_Const_type(tv, tp));
244 current_ir_graph = rem;
246 pmap_insert(cg->isa->tv_ent, tv, res);
254 static int is_Const_0(ir_node *node) {
258 return classify_Const(node) == CNST_NULL;
261 static int is_Const_1(ir_node *node) {
265 return classify_Const(node) == CNST_ONE;
269 * Transforms a Const.
271 static ir_node *gen_Const(ir_node *node) {
272 ir_graph *irg = current_ir_graph;
273 ir_node *old_block = get_nodes_block(node);
274 ir_node *block = be_transform_node(old_block);
275 dbg_info *dbgi = get_irn_dbg_info(node);
276 ir_mode *mode = get_irn_mode(node);
278 if (mode_is_float(mode)) {
280 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
281 ir_node *nomem = new_NoMem();
285 if (! USE_SSE2(env_cg)) {
286 cnst_classify_t clss = classify_Const(node);
288 if (clss == CNST_NULL) {
289 load = new_rd_ia32_vfldz(dbgi, irg, block);
291 } else if (clss == CNST_ONE) {
292 load = new_rd_ia32_vfld1(dbgi, irg, block);
295 floatent = get_entity_for_tv(env_cg, node);
297 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
298 set_ia32_op_type(load, ia32_AddrModeS);
299 set_ia32_am_flavour(load, ia32_am_N);
300 set_ia32_am_sc(load, floatent);
301 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
302 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
304 set_ia32_ls_mode(load, mode);
306 floatent = get_entity_for_tv(env_cg, node);
308 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
309 set_ia32_op_type(load, ia32_AddrModeS);
310 set_ia32_am_flavour(load, ia32_am_N);
311 set_ia32_am_sc(load, floatent);
312 set_ia32_ls_mode(load, mode);
313 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
315 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
318 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
320 /* Const Nodes before the initial IncSP are a bad idea, because
321 * they could be spilled and we have no SP ready at that point yet.
322 * So add a dependency to the initial frame pointer calculation to
323 * avoid that situation.
325 if (get_irg_start_block(irg) == block) {
326 add_irn_dep(load, get_irg_frame(irg));
329 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
332 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
335 if (get_irg_start_block(irg) == block) {
336 add_irn_dep(cnst, get_irg_frame(irg));
339 set_ia32_Const_attr(cnst, node);
340 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
345 return new_r_Bad(irg);
349 * Transforms a SymConst.
351 static ir_node *gen_SymConst(ir_node *node) {
352 ir_graph *irg = current_ir_graph;
353 ir_node *old_block = get_nodes_block(node);
354 ir_node *block = be_transform_node(old_block);
355 dbg_info *dbgi = get_irn_dbg_info(node);
356 ir_mode *mode = get_irn_mode(node);
359 if (mode_is_float(mode)) {
360 if (USE_SSE2(env_cg))
361 cnst = new_rd_ia32_xConst(dbgi, irg, block);
363 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
364 //set_ia32_ls_mode(cnst, mode);
365 set_ia32_ls_mode(cnst, mode_E);
367 cnst = new_rd_ia32_Const(dbgi, irg, block);
370 /* Const Nodes before the initial IncSP are a bad idea, because
371 * they could be spilled and we have no SP ready at that point yet
373 if (get_irg_start_block(irg) == block) {
374 add_irn_dep(cnst, get_irg_frame(irg));
377 set_ia32_Const_attr(cnst, node);
378 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
383 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
384 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
385 static const struct {
387 const char *ent_name;
388 const char *cnst_str;
389 } names [ia32_known_const_max] = {
390 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
391 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
392 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
393 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
395 static ir_entity *ent_cache[ia32_known_const_max];
397 const char *tp_name, *ent_name, *cnst_str;
405 ent_name = names[kct].ent_name;
406 if (! ent_cache[kct]) {
407 tp_name = names[kct].tp_name;
408 cnst_str = names[kct].cnst_str;
410 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
412 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
413 tp = new_type_primitive(new_id_from_str(tp_name), mode);
414 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
416 set_entity_ld_ident(ent, get_entity_ident(ent));
417 set_entity_visibility(ent, visibility_local);
418 set_entity_variability(ent, variability_constant);
419 set_entity_allocation(ent, allocation_static);
421 /* we create a new entity here: It's initialization must resist on the
423 rem = current_ir_graph;
424 current_ir_graph = get_const_code_irg();
425 cnst = new_Const(mode, tv);
426 current_ir_graph = rem;
428 set_atomic_ent_value(ent, cnst);
430 /* cache the entry */
431 ent_cache[kct] = ent;
434 return ent_cache[kct];
439 * Prints the old node name on cg obst and returns a pointer to it.
441 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
442 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
444 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
445 obstack_1grow(isa->name_obst, 0);
446 return obstack_finish(isa->name_obst);
450 /* determine if one operator is an Imm */
451 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
453 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
455 return is_ia32_Cnst(op2) ? op2 : NULL;
459 /* determine if one operator is not an Imm */
460 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
461 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
464 static void fold_immediate(ir_node *node, int in1, int in2) {
468 if (!(env_cg->opt & IA32_OPT_IMMOPS))
471 left = get_irn_n(node, in1);
472 right = get_irn_n(node, in2);
473 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
474 /* we can only set right operand to immediate */
475 if(!is_ia32_commutative(node))
477 /* exchange left/right */
478 set_irn_n(node, in1, right);
479 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
480 copy_ia32_Immop_attr(node, left);
481 } else if(is_ia32_Cnst(right)) {
482 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
483 copy_ia32_Immop_attr(node, right);
488 clear_ia32_commutative(node);
489 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
490 get_ia32_am_arity(node));
494 * Construct a standard binary operation, set AM and immediate if required.
496 * @param op1 The first operand
497 * @param op2 The second operand
498 * @param func The node constructor function
499 * @return The constructed ia32 node.
501 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
502 construct_binop_func *func, int commutative)
504 ir_node *block = be_transform_node(get_nodes_block(node));
505 ir_graph *irg = current_ir_graph;
506 dbg_info *dbgi = get_irn_dbg_info(node);
507 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
508 ir_node *nomem = new_NoMem();
511 ir_node *new_op1 = be_transform_node(op1);
512 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
513 if (is_ia32_Immediate(new_op2)) {
517 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
518 if (func == new_rd_ia32_IMul) {
519 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
521 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
524 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
526 set_ia32_commutative(new_node);
533 * Construct a standard binary operation, set AM and immediate if required.
535 * @param op1 The first operand
536 * @param op2 The second operand
537 * @param func The node constructor function
538 * @return The constructed ia32 node.
540 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
541 construct_binop_func *func)
543 ir_node *block = be_transform_node(get_nodes_block(node));
544 ir_node *new_op1 = be_transform_node(op1);
545 ir_node *new_op2 = be_transform_node(op2);
546 ir_node *new_node = NULL;
547 dbg_info *dbgi = get_irn_dbg_info(node);
548 ir_graph *irg = current_ir_graph;
549 ir_mode *mode = get_irn_mode(node);
550 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
551 ir_node *nomem = new_NoMem();
553 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
555 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
556 if (is_op_commutative(get_irn_op(node))) {
557 set_ia32_commutative(new_node);
559 set_ia32_ls_mode(new_node, mode);
561 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
566 static ir_node *get_fpcw(void)
569 if(initial_fpcw != NULL)
572 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
573 &ia32_fp_cw_regs[REG_FPCW]);
574 initial_fpcw = be_transform_node(fpcw);
580 * Construct a standard binary operation, set AM and immediate if required.
582 * @param op1 The first operand
583 * @param op2 The second operand
584 * @param func The node constructor function
585 * @return The constructed ia32 node.
587 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
588 construct_binop_float_func *func)
590 ir_node *block = be_transform_node(get_nodes_block(node));
591 ir_node *new_op1 = be_transform_node(op1);
592 ir_node *new_op2 = be_transform_node(op2);
593 ir_node *new_node = NULL;
594 dbg_info *dbgi = get_irn_dbg_info(node);
595 ir_graph *irg = current_ir_graph;
596 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
597 ir_node *nomem = new_NoMem();
599 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
601 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
602 if (is_op_commutative(get_irn_op(node))) {
603 set_ia32_commutative(new_node);
606 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
612 * Construct a shift/rotate binary operation, sets AM and immediate if required.
614 * @param op1 The first operand
615 * @param op2 The second operand
616 * @param func The node constructor function
617 * @return The constructed ia32 node.
619 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
620 construct_binop_func *func)
622 ir_node *block = be_transform_node(get_nodes_block(node));
623 ir_node *new_op1 = be_transform_node(op1);
625 ir_node *new_op = NULL;
626 dbg_info *dbgi = get_irn_dbg_info(node);
627 ir_graph *irg = current_ir_graph;
628 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
629 ir_node *nomem = new_NoMem();
631 assert(! mode_is_float(get_irn_mode(node))
632 && "Shift/Rotate with float not supported");
634 new_op2 = create_immediate_or_transform(op2, 'N');
636 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
639 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
641 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
643 set_ia32_emit_cl(new_op);
650 * Construct a standard unary operation, set AM and immediate if required.
652 * @param op The operand
653 * @param func The node constructor function
654 * @return The constructed ia32 node.
656 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
658 ir_node *block = be_transform_node(get_nodes_block(node));
659 ir_node *new_op = be_transform_node(op);
660 ir_node *new_node = NULL;
661 ir_graph *irg = current_ir_graph;
662 dbg_info *dbgi = get_irn_dbg_info(node);
663 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
664 ir_node *nomem = new_NoMem();
666 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
667 DB((dbg, LEVEL_1, "INT unop ..."));
668 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
670 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
676 * Creates an ia32 Add.
678 * @return the created ia32 Add node
680 static ir_node *gen_Add(ir_node *node) {
681 ir_node *block = be_transform_node(get_nodes_block(node));
682 ir_node *op1 = get_Add_left(node);
683 ir_node *new_op1 = be_transform_node(op1);
684 ir_node *op2 = get_Add_right(node);
685 ir_node *new_op2 = be_transform_node(op2);
686 ir_node *new_op = NULL;
687 ir_graph *irg = current_ir_graph;
688 dbg_info *dbgi = get_irn_dbg_info(node);
689 ir_mode *mode = get_irn_mode(node);
690 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
691 ir_node *nomem = new_NoMem();
692 ir_node *expr_op, *imm_op;
694 /* Check if immediate optimization is on and */
695 /* if it's an operation with immediate. */
696 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
697 expr_op = get_expr_op(new_op1, new_op2);
699 assert((expr_op || imm_op) && "invalid operands");
701 if (mode_is_float(mode)) {
702 if (USE_SSE2(env_cg))
703 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
705 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
710 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
711 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
713 /* No expr_op means, that we have two const - one symconst and */
714 /* one tarval or another symconst - because this case is not */
715 /* covered by constant folding */
716 /* We need to check for: */
717 /* 1) symconst + const -> becomes a LEA */
718 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
719 /* linker doesn't support two symconsts */
721 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
722 /* this is the 2nd case */
723 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
724 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
725 set_ia32_am_flavour(new_op, ia32_am_B);
726 set_ia32_op_type(new_op, ia32_AddrModeS);
728 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
729 } else if (tp1 == ia32_ImmSymConst) {
730 tarval *tv = get_ia32_Immop_tarval(new_op2);
731 long offs = get_tarval_long(tv);
733 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
734 add_irn_dep(new_op, get_irg_frame(irg));
735 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
737 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
738 add_ia32_am_offs_int(new_op, offs);
739 set_ia32_am_flavour(new_op, ia32_am_OB);
740 set_ia32_op_type(new_op, ia32_AddrModeS);
741 } else if (tp2 == ia32_ImmSymConst) {
742 tarval *tv = get_ia32_Immop_tarval(new_op1);
743 long offs = get_tarval_long(tv);
745 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
746 add_irn_dep(new_op, get_irg_frame(irg));
747 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
749 add_ia32_am_offs_int(new_op, offs);
750 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
751 set_ia32_am_flavour(new_op, ia32_am_OB);
752 set_ia32_op_type(new_op, ia32_AddrModeS);
754 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
755 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
756 tarval *restv = tarval_add(tv1, tv2);
758 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
760 new_op = new_rd_ia32_Const(dbgi, irg, block);
761 set_ia32_Const_tarval(new_op, restv);
762 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
765 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
768 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
769 tarval_classification_t class_tv, class_negtv;
770 tarval *tv = get_ia32_Immop_tarval(imm_op);
772 /* optimize tarvals */
773 class_tv = classify_tarval(tv);
774 class_negtv = classify_tarval(tarval_neg(tv));
776 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
777 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
778 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
779 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
781 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
782 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
783 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
784 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
790 /* This is a normal add */
791 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
794 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
795 set_ia32_commutative(new_op);
797 fold_immediate(new_op, 2, 3);
799 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
805 * Creates an ia32 Mul.
807 * @return the created ia32 Mul node
809 static ir_node *gen_Mul(ir_node *node) {
810 ir_node *op1 = get_Mul_left(node);
811 ir_node *op2 = get_Mul_right(node);
812 ir_mode *mode = get_irn_mode(node);
814 if (mode_is_float(mode)) {
815 if (USE_SSE2(env_cg))
816 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
818 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
822 for the lower 32bit of the result it doesn't matter whether we use
823 signed or unsigned multiplication so we use IMul as it has fewer
826 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
830 * Creates an ia32 Mulh.
831 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
832 * this result while Mul returns the lower 32 bit.
834 * @return the created ia32 Mulh node
836 static ir_node *gen_Mulh(ir_node *node) {
837 ir_node *block = be_transform_node(get_nodes_block(node));
838 ir_node *op1 = get_irn_n(node, 0);
839 ir_node *new_op1 = be_transform_node(op1);
840 ir_node *op2 = get_irn_n(node, 1);
841 ir_node *new_op2 = be_transform_node(op2);
842 ir_graph *irg = current_ir_graph;
843 dbg_info *dbgi = get_irn_dbg_info(node);
844 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
845 ir_mode *mode = get_irn_mode(node);
846 ir_node *proj_EDX, *res;
848 assert(!mode_is_float(mode) && "Mulh with float not supported");
849 if (mode_is_signed(mode)) {
850 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
851 new_op2, new_NoMem());
853 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
857 set_ia32_commutative(res);
858 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
860 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
868 * Creates an ia32 And.
870 * @return The created ia32 And node
872 static ir_node *gen_And(ir_node *node) {
873 ir_node *op1 = get_And_left(node);
874 ir_node *op2 = get_And_right(node);
876 assert(! mode_is_float(get_irn_mode(node)));
878 if (is_Const(op2) && is_Load(skip_Proj(op1)) && get_irn_n_edges(op1) == 1) {
879 /* a Load() & Const */
880 tarval *tv = get_Const_tarval(op2);
881 long v = get_tarval_long(tv);
884 ir_node *new_op = be_transform_node(op1);
885 ir_node *load = skip_Proj(new_op);
886 set_ia32_ls_mode(load, mode_Bu);
888 } else if (v == 0xFFFF) {
889 ir_node *new_op = be_transform_node(op1);
890 ir_node *load = skip_Proj(new_op);
891 set_ia32_ls_mode(load, mode_Hu);
895 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
901 * Creates an ia32 Or.
903 * @return The created ia32 Or node
905 static ir_node *gen_Or(ir_node *node) {
906 ir_node *op1 = get_Or_left(node);
907 ir_node *op2 = get_Or_right(node);
909 assert (! mode_is_float(get_irn_mode(node)));
910 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
916 * Creates an ia32 Eor.
918 * @return The created ia32 Eor node
920 static ir_node *gen_Eor(ir_node *node) {
921 ir_node *op1 = get_Eor_left(node);
922 ir_node *op2 = get_Eor_right(node);
924 assert(! mode_is_float(get_irn_mode(node)));
925 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
930 * Creates an ia32 Sub.
932 * @return The created ia32 Sub node
934 static ir_node *gen_Sub(ir_node *node) {
935 ir_node *block = be_transform_node(get_nodes_block(node));
936 ir_node *op1 = get_Sub_left(node);
937 ir_node *new_op1 = be_transform_node(op1);
938 ir_node *op2 = get_Sub_right(node);
939 ir_node *new_op2 = be_transform_node(op2);
940 ir_node *new_op = NULL;
941 ir_graph *irg = current_ir_graph;
942 dbg_info *dbgi = get_irn_dbg_info(node);
943 ir_mode *mode = get_irn_mode(node);
944 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
945 ir_node *nomem = new_NoMem();
946 ir_node *expr_op, *imm_op;
948 /* Check if immediate optimization is on and */
949 /* if it's an operation with immediate. */
950 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
951 expr_op = get_expr_op(new_op1, new_op2);
953 assert((expr_op || imm_op) && "invalid operands");
955 if (mode_is_float(mode)) {
956 if (USE_SSE2(env_cg))
957 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
959 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
964 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
965 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
967 /* No expr_op means, that we have two const - one symconst and */
968 /* one tarval or another symconst - because this case is not */
969 /* covered by constant folding */
970 /* We need to check for: */
971 /* 1) symconst - const -> becomes a LEA */
972 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
973 /* linker doesn't support two symconsts */
974 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
975 /* this is the 2nd case */
976 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
977 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
978 set_ia32_am_sc_sign(new_op);
979 set_ia32_am_flavour(new_op, ia32_am_B);
981 DBG_OPT_LEA3(op1, op2, node, new_op);
982 } else if (tp1 == ia32_ImmSymConst) {
983 tarval *tv = get_ia32_Immop_tarval(new_op2);
984 long offs = get_tarval_long(tv);
986 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
987 add_irn_dep(new_op, get_irg_frame(irg));
988 DBG_OPT_LEA3(op1, op2, node, new_op);
990 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
991 add_ia32_am_offs_int(new_op, -offs);
992 set_ia32_am_flavour(new_op, ia32_am_OB);
993 set_ia32_op_type(new_op, ia32_AddrModeS);
994 } else if (tp2 == ia32_ImmSymConst) {
995 tarval *tv = get_ia32_Immop_tarval(new_op1);
996 long offs = get_tarval_long(tv);
998 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
999 add_irn_dep(new_op, get_irg_frame(irg));
1000 DBG_OPT_LEA3(op1, op2, node, new_op);
1002 add_ia32_am_offs_int(new_op, offs);
1003 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1004 set_ia32_am_sc_sign(new_op);
1005 set_ia32_am_flavour(new_op, ia32_am_OB);
1006 set_ia32_op_type(new_op, ia32_AddrModeS);
1008 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1009 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1010 tarval *restv = tarval_sub(tv1, tv2);
1012 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1014 new_op = new_rd_ia32_Const(dbgi, irg, block);
1015 set_ia32_Const_tarval(new_op, restv);
1016 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1019 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1021 } else if (imm_op) {
1022 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1023 tarval_classification_t class_tv, class_negtv;
1024 tarval *tv = get_ia32_Immop_tarval(imm_op);
1026 /* optimize tarvals */
1027 class_tv = classify_tarval(tv);
1028 class_negtv = classify_tarval(tarval_neg(tv));
1030 if (class_tv == TV_CLASSIFY_ONE) {
1031 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1032 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1033 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1035 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1036 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1037 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1038 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1044 /* This is a normal sub */
1045 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1047 /* set AM support */
1048 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1050 fold_immediate(new_op, 2, 3);
1052 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1060 * Generates an ia32 DivMod with additional infrastructure for the
1061 * register allocator if needed.
1063 * @param dividend -no comment- :)
1064 * @param divisor -no comment- :)
1065 * @param dm_flav flavour_Div/Mod/DivMod
1066 * @return The created ia32 DivMod node
1068 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1069 ir_node *divisor, ia32_op_flavour_t dm_flav)
1071 ir_node *block = be_transform_node(get_nodes_block(node));
1072 ir_node *new_dividend = be_transform_node(dividend);
1073 ir_node *new_divisor = be_transform_node(divisor);
1074 ir_graph *irg = current_ir_graph;
1075 dbg_info *dbgi = get_irn_dbg_info(node);
1076 ir_mode *mode = get_irn_mode(node);
1077 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1078 ir_node *res, *proj_div, *proj_mod;
1079 ir_node *sign_extension;
1080 ir_node *mem, *new_mem;
1081 ir_node *projs[pn_DivMod_max];
1084 ia32_collect_Projs(node, projs, pn_DivMod_max);
1086 proj_div = proj_mod = NULL;
1090 mem = get_Div_mem(node);
1091 mode = get_Div_resmode(node);
1092 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1093 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1096 mem = get_Mod_mem(node);
1097 mode = get_Mod_resmode(node);
1098 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1099 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1101 case flavour_DivMod:
1102 mem = get_DivMod_mem(node);
1103 mode = get_DivMod_resmode(node);
1104 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1105 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1106 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1109 panic("invalid divmod flavour!");
1111 new_mem = be_transform_node(mem);
1113 if (mode_is_signed(mode)) {
1114 /* in signed mode, we need to sign extend the dividend */
1115 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1116 add_irn_dep(produceval, get_irg_frame(irg));
1117 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1120 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1121 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1123 add_irn_dep(sign_extension, get_irg_frame(irg));
1126 if (mode_is_signed(mode)) {
1127 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1128 sign_extension, new_divisor, new_mem, dm_flav);
1130 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1131 sign_extension, new_divisor, new_mem, dm_flav);
1134 set_ia32_exc_label(res, has_exc);
1135 set_irn_pinned(res, get_irn_pinned(node));
1136 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1138 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1145 * Wrapper for generate_DivMod. Sets flavour_Mod.
1148 static ir_node *gen_Mod(ir_node *node) {
1149 return generate_DivMod(node, get_Mod_left(node),
1150 get_Mod_right(node), flavour_Mod);
1154 * Wrapper for generate_DivMod. Sets flavour_Div.
1157 static ir_node *gen_Div(ir_node *node) {
1158 return generate_DivMod(node, get_Div_left(node),
1159 get_Div_right(node), flavour_Div);
1163 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1165 static ir_node *gen_DivMod(ir_node *node) {
1166 return generate_DivMod(node, get_DivMod_left(node),
1167 get_DivMod_right(node), flavour_DivMod);
1173 * Creates an ia32 floating Div.
1175 * @return The created ia32 xDiv node
1177 static ir_node *gen_Quot(ir_node *node) {
1178 ir_node *block = be_transform_node(get_nodes_block(node));
1179 ir_node *op1 = get_Quot_left(node);
1180 ir_node *new_op1 = be_transform_node(op1);
1181 ir_node *op2 = get_Quot_right(node);
1182 ir_node *new_op2 = be_transform_node(op2);
1183 ir_graph *irg = current_ir_graph;
1184 dbg_info *dbgi = get_irn_dbg_info(node);
1185 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1186 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1189 if (USE_SSE2(env_cg)) {
1190 ir_mode *mode = get_irn_mode(op1);
1191 if (is_ia32_xConst(new_op2)) {
1192 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1193 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1194 copy_ia32_Immop_attr(new_op, new_op2);
1196 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1197 // Matze: disabled for now, spillslot coalescer fails
1198 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1200 set_ia32_ls_mode(new_op, mode);
1202 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1203 new_op2, nomem, get_fpcw());
1204 // Matze: disabled for now (spillslot coalescer fails)
1205 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1207 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1213 * Creates an ia32 Shl.
1215 * @return The created ia32 Shl node
1217 static ir_node *gen_Shl(ir_node *node) {
1218 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1225 * Creates an ia32 Shr.
1227 * @return The created ia32 Shr node
1229 static ir_node *gen_Shr(ir_node *node) {
1230 return gen_shift_binop(node, get_Shr_left(node),
1231 get_Shr_right(node), new_rd_ia32_Shr);
1237 * Creates an ia32 Sar.
1239 * @return The created ia32 Shrs node
1241 static ir_node *gen_Shrs(ir_node *node) {
1242 ir_node *left = get_Shrs_left(node);
1243 ir_node *right = get_Shrs_right(node);
1244 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1245 tarval *tv = get_Const_tarval(right);
1246 long val = get_tarval_long(tv);
1248 /* this is a sign extension */
1249 ir_graph *irg = current_ir_graph;
1250 dbg_info *dbgi = get_irn_dbg_info(node);
1251 ir_node *block = be_transform_node(get_nodes_block(node));
1253 ir_node *new_op = be_transform_node(op);
1254 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1255 add_irn_dep(pval, get_irg_frame(irg));
1257 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1261 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1267 * Creates an ia32 RotL.
1269 * @param op1 The first operator
1270 * @param op2 The second operator
1271 * @return The created ia32 RotL node
1273 static ir_node *gen_RotL(ir_node *node,
1274 ir_node *op1, ir_node *op2) {
1275 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1281 * Creates an ia32 RotR.
1282 * NOTE: There is no RotR with immediate because this would always be a RotL
1283 * "imm-mode_size_bits" which can be pre-calculated.
1285 * @param op1 The first operator
1286 * @param op2 The second operator
1287 * @return The created ia32 RotR node
1289 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1291 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1297 * Creates an ia32 RotR or RotL (depending on the found pattern).
1299 * @return The created ia32 RotL or RotR node
1301 static ir_node *gen_Rot(ir_node *node) {
1302 ir_node *rotate = NULL;
1303 ir_node *op1 = get_Rot_left(node);
1304 ir_node *op2 = get_Rot_right(node);
1306 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1307 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1308 that means we can create a RotR instead of an Add and a RotL */
1310 if (get_irn_op(op2) == op_Add) {
1312 ir_node *left = get_Add_left(add);
1313 ir_node *right = get_Add_right(add);
1314 if (is_Const(right)) {
1315 tarval *tv = get_Const_tarval(right);
1316 ir_mode *mode = get_irn_mode(node);
1317 long bits = get_mode_size_bits(mode);
1319 if (get_irn_op(left) == op_Minus &&
1320 tarval_is_long(tv) &&
1321 get_tarval_long(tv) == bits)
1323 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1324 rotate = gen_RotR(node, op1, get_Minus_op(left));
1329 if (rotate == NULL) {
1330 rotate = gen_RotL(node, op1, op2);
1339 * Transforms a Minus node.
1341 * @param op The Minus operand
1342 * @return The created ia32 Minus node
1344 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1345 ir_node *block = be_transform_node(get_nodes_block(node));
1346 ir_graph *irg = current_ir_graph;
1347 dbg_info *dbgi = get_irn_dbg_info(node);
1348 ir_mode *mode = get_irn_mode(node);
1353 if (mode_is_float(mode)) {
1354 ir_node *new_op = be_transform_node(op);
1355 if (USE_SSE2(env_cg)) {
1356 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1357 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1358 ir_node *nomem = new_rd_NoMem(irg);
1360 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1362 size = get_mode_size_bits(mode);
1363 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1365 set_ia32_am_sc(res, ent);
1366 set_ia32_op_type(res, ia32_AddrModeS);
1367 set_ia32_ls_mode(res, mode);
1369 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1372 res = gen_unop(node, op, new_rd_ia32_Neg);
1375 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1381 * Transforms a Minus node.
1383 * @return The created ia32 Minus node
1385 static ir_node *gen_Minus(ir_node *node) {
1386 return gen_Minus_ex(node, get_Minus_op(node));
1389 static ir_node *gen_bin_Not(ir_node *node)
1391 ir_graph *irg = current_ir_graph;
1392 dbg_info *dbgi = get_irn_dbg_info(node);
1393 ir_node *block = be_transform_node(get_nodes_block(node));
1394 ir_node *op = get_Not_op(node);
1395 ir_node *new_op = be_transform_node(op);
1396 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1397 ir_node *nomem = new_NoMem();
1398 ir_node *one = new_rd_ia32_Immediate(dbgi, irg, block, NULL, 0, 1);
1399 arch_set_irn_register(env_cg->arch_env, one, &ia32_gp_regs[REG_GP_NOREG]);
1401 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1405 * Transforms a Not node.
1407 * @return The created ia32 Not node
1409 static ir_node *gen_Not(ir_node *node) {
1410 ir_node *op = get_Not_op(node);
1411 ir_mode *mode = get_irn_mode(node);
1413 if(mode == mode_b) {
1414 return gen_bin_Not(node);
1417 assert (! mode_is_float(get_irn_mode(node)));
1418 return gen_unop(node, op, new_rd_ia32_Not);
1424 * Transforms an Abs node.
1426 * @return The created ia32 Abs node
1428 static ir_node *gen_Abs(ir_node *node) {
1429 ir_node *block = be_transform_node(get_nodes_block(node));
1430 ir_node *op = get_Abs_op(node);
1431 ir_node *new_op = be_transform_node(op);
1432 ir_graph *irg = current_ir_graph;
1433 dbg_info *dbgi = get_irn_dbg_info(node);
1434 ir_mode *mode = get_irn_mode(node);
1435 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1436 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1437 ir_node *nomem = new_NoMem();
1442 if (mode_is_float(mode)) {
1443 if (USE_SSE2(env_cg)) {
1444 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1446 size = get_mode_size_bits(mode);
1447 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1449 set_ia32_am_sc(res, ent);
1451 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1453 set_ia32_op_type(res, ia32_AddrModeS);
1454 set_ia32_ls_mode(res, mode);
1457 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1458 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1462 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1463 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1466 add_irn_dep(pval, get_irg_frame(irg));
1467 SET_IA32_ORIG_NODE(sign_extension,
1468 ia32_get_old_node_name(env_cg, node));
1470 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1471 sign_extension, nomem);
1472 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1474 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1475 sign_extension, nomem);
1476 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1485 * Transforms a Load.
1487 * @return the created ia32 Load node
1489 static ir_node *gen_Load(ir_node *node) {
1490 ir_node *old_block = get_nodes_block(node);
1491 ir_node *block = be_transform_node(old_block);
1492 ir_node *ptr = get_Load_ptr(node);
1493 ir_node *new_ptr = be_transform_node(ptr);
1494 ir_node *mem = get_Load_mem(node);
1495 ir_node *new_mem = be_transform_node(mem);
1496 ir_graph *irg = current_ir_graph;
1497 dbg_info *dbgi = get_irn_dbg_info(node);
1498 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1499 ir_mode *mode = get_Load_mode(node);
1501 ir_node *lptr = new_ptr;
1504 ia32_am_flavour_t am_flav = ia32_am_B;
1506 /* address might be a constant (symconst or absolute address) */
1507 if (is_ia32_Const(new_ptr)) {
1512 if (mode_is_float(mode)) {
1513 if (USE_SSE2(env_cg)) {
1514 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1515 res_mode = mode_xmm;
1517 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1518 res_mode = mode_vfp;
1524 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1528 /* base is a constant address */
1530 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1531 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1532 am_flav = ia32_am_N;
1534 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1535 long offs = get_tarval_long(tv);
1537 add_ia32_am_offs_int(new_op, offs);
1538 am_flav = ia32_am_O;
1542 set_irn_pinned(new_op, get_irn_pinned(node));
1543 set_ia32_op_type(new_op, ia32_AddrModeS);
1544 set_ia32_am_flavour(new_op, am_flav);
1545 set_ia32_ls_mode(new_op, mode);
1547 /* make sure we are scheduled behind the initial IncSP/Barrier
1548 * to avoid spills being placed before it
1550 if (block == get_irg_start_block(irg)) {
1551 add_irn_dep(new_op, get_irg_frame(irg));
1554 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1555 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1563 * Transforms a Store.
1565 * @return the created ia32 Store node
1567 static ir_node *gen_Store(ir_node *node) {
1568 ir_node *block = be_transform_node(get_nodes_block(node));
1569 ir_node *ptr = get_Store_ptr(node);
1570 ir_node *new_ptr = be_transform_node(ptr);
1571 ir_node *val = get_Store_value(node);
1573 ir_node *mem = get_Store_mem(node);
1574 ir_node *new_mem = be_transform_node(mem);
1575 ir_graph *irg = current_ir_graph;
1576 dbg_info *dbgi = get_irn_dbg_info(node);
1577 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1578 ir_node *sptr = new_ptr;
1579 ir_mode *mode = get_irn_mode(val);
1582 ia32_am_flavour_t am_flav = ia32_am_B;
1584 /* address might be a constant (symconst or absolute address) */
1585 if (is_ia32_Const(new_ptr)) {
1590 if (mode_is_float(mode)) {
1591 new_val = be_transform_node(val);
1592 if (USE_SSE2(env_cg)) {
1593 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1596 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1600 new_val = create_immediate_or_transform(val, 0);
1604 if (get_mode_size_bits(mode) == 8) {
1605 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1608 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1613 /* base is an constant address */
1615 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1616 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1617 am_flav = ia32_am_N;
1619 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1620 long offs = get_tarval_long(tv);
1622 add_ia32_am_offs_int(new_op, offs);
1623 am_flav = ia32_am_O;
1627 set_irn_pinned(new_op, get_irn_pinned(node));
1628 set_ia32_op_type(new_op, ia32_AddrModeD);
1629 set_ia32_am_flavour(new_op, am_flav);
1630 set_ia32_ls_mode(new_op, mode);
1632 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1633 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1638 static ir_node *maybe_scale_up(ir_node *new_op, ir_mode *mode, dbg_info *dbgi)
1643 if(get_mode_size_bits(mode) == 32)
1647 if(is_ia32_Immediate(new_op))
1650 if(mode_is_signed(mode))
1655 block = get_nodes_block(new_op);
1656 return create_I2I_Conv(mode, tgt_mode, dbgi, block, new_op);
1659 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1660 ir_node *cmp_left, ir_node *cmp_right)
1662 ir_node *new_cmp_left;
1663 ir_node *new_cmp_right;
1670 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1672 if(cmp_right != NULL && !is_Const_0(cmp_right))
1675 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1676 and_left = get_And_left(cmp_left);
1677 and_right = get_And_right(cmp_left);
1679 mode = get_irn_mode(and_left);
1680 new_cmp_left = be_transform_node(and_left);
1681 new_cmp_right = create_immediate_or_transform(and_right, 0);
1683 mode = get_irn_mode(cmp_left);
1684 new_cmp_left = be_transform_node(cmp_left);
1685 new_cmp_right = be_transform_node(cmp_left);
1688 assert(get_mode_size_bits(mode) <= 32);
1689 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1690 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1691 noreg = ia32_new_NoReg_gp(env_cg);
1692 nomem = new_NoMem();
1694 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1695 new_cmp_left, new_cmp_right, nomem, pnc);
1696 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1701 static ir_node *create_Switch(ir_node *node)
1703 ir_graph *irg = current_ir_graph;
1704 dbg_info *dbgi = get_irn_dbg_info(node);
1705 ir_node *block = be_transform_node(get_nodes_block(node));
1706 ir_node *sel = get_Cond_selector(node);
1707 ir_node *new_sel = be_transform_node(sel);
1709 int switch_min = INT_MAX;
1710 const ir_edge_t *edge;
1712 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1714 /* determine the smallest switch case value */
1715 foreach_out_edge(node, edge) {
1716 ir_node *proj = get_edge_src_irn(edge);
1717 int pn = get_Proj_proj(proj);
1722 if (switch_min != 0) {
1723 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1725 /* if smallest switch case is not 0 we need an additional sub */
1726 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1727 add_ia32_am_offs_int(new_sel, -switch_min);
1728 set_ia32_am_flavour(new_sel, ia32_am_OB);
1729 set_ia32_op_type(new_sel, ia32_AddrModeS);
1731 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1734 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1735 set_ia32_pncode(res, get_Cond_defaultProj(node));
1737 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1743 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1745 * @return The transformed node.
1747 static ir_node *gen_Cond(ir_node *node) {
1748 ir_node *block = be_transform_node(get_nodes_block(node));
1749 ir_graph *irg = current_ir_graph;
1750 dbg_info *dbgi = get_irn_dbg_info(node);
1751 ir_node *sel = get_Cond_selector(node);
1752 ir_mode *sel_mode = get_irn_mode(sel);
1753 ir_node *res = NULL;
1754 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1761 ir_node *nomem = new_NoMem();
1764 if (sel_mode != mode_b) {
1765 return create_Switch(node);
1768 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
1769 /* it's some mode_b value but not a direct comparison -> create a
1771 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
1772 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1776 cmp = get_Proj_pred(sel);
1777 cmp_a = get_Cmp_left(cmp);
1778 cmp_b = get_Cmp_right(cmp);
1779 cmp_mode = get_irn_mode(cmp_a);
1780 pnc = get_Proj_proj(sel);
1781 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1782 pnc |= ia32_pn_Cmp_Unsigned;
1785 if(mode_needs_gp_reg(cmp_mode)) {
1786 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b);
1788 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1793 new_cmp_a = be_transform_node(cmp_a);
1794 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1796 if (mode_is_float(cmp_mode)) {
1797 if (USE_SSE2(env_cg)) {
1798 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1800 set_ia32_commutative(res);
1801 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1802 set_ia32_ls_mode(res, cmp_mode);
1804 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1805 set_ia32_commutative(res);
1808 /** workaround smaller compare modes with converts...
1809 * We could easily support 16bit compares, for 8 bit we have to set
1810 * additional register constraints, which we don't do yet
1812 new_cmp_a = maybe_scale_up(new_cmp_a, cmp_mode, dbgi);
1813 new_cmp_b = maybe_scale_up(new_cmp_b, cmp_mode, dbgi);
1815 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1816 new_cmp_a, new_cmp_b, nomem, pnc);
1817 set_ia32_commutative(res);
1818 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1821 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1829 * Transforms a CopyB node.
1831 * @return The transformed node.
1833 static ir_node *gen_CopyB(ir_node *node) {
1834 ir_node *block = be_transform_node(get_nodes_block(node));
1835 ir_node *src = get_CopyB_src(node);
1836 ir_node *new_src = be_transform_node(src);
1837 ir_node *dst = get_CopyB_dst(node);
1838 ir_node *new_dst = be_transform_node(dst);
1839 ir_node *mem = get_CopyB_mem(node);
1840 ir_node *new_mem = be_transform_node(mem);
1841 ir_node *res = NULL;
1842 ir_graph *irg = current_ir_graph;
1843 dbg_info *dbgi = get_irn_dbg_info(node);
1844 int size = get_type_size_bytes(get_CopyB_type(node));
1847 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1848 /* then we need the size explicitly in ECX. */
1849 if (size >= 32 * 4) {
1850 rem = size & 0x3; /* size % 4 */
1853 res = new_rd_ia32_Const(dbgi, irg, block);
1854 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1855 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1857 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1858 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1860 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1861 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1864 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1870 ir_node *gen_be_Copy(ir_node *node)
1872 ir_node *result = be_duplicate_node(node);
1873 ir_mode *mode = get_irn_mode(result);
1875 if (mode_needs_gp_reg(mode)) {
1876 set_irn_mode(result, mode_Iu);
1883 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1884 dbg_info *dbgi, ir_node *block)
1886 ir_graph *irg = current_ir_graph;
1887 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1888 ir_node *nomem = new_rd_NoMem(irg);
1890 ir_node *new_cmp_left;
1891 ir_node *new_cmp_right;
1894 /* can we use a test instruction? */
1895 if(cmp_right == NULL || is_Const_0(cmp_right)) {
1896 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1897 if(is_And(cmp_left) &&
1898 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1899 ir_node *and_left = get_And_left(cmp_left);
1900 ir_node *and_right = get_And_right(cmp_left);
1902 mode = get_irn_mode(and_left);
1903 new_cmp_left = be_transform_node(and_left);
1904 new_cmp_right = create_immediate_or_transform(and_right, 0);
1906 mode = get_irn_mode(cmp_left);
1907 new_cmp_left = be_transform_node(cmp_left);
1908 new_cmp_right = be_transform_node(cmp_left);
1911 assert(get_mode_size_bits(mode) <= 32);
1912 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1913 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1915 res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
1916 new_cmp_left, new_cmp_right, nomem, pnc);
1917 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1922 mode = get_irn_mode(cmp_left);
1924 new_cmp_left = be_transform_node(cmp_left);
1925 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1927 assert(get_mode_size_bits(mode) <= 32);
1928 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1929 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1931 res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
1932 new_cmp_left, new_cmp_right, nomem, pnc);
1937 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1938 ir_node *val_true, ir_node *val_false,
1939 dbg_info *dbgi, ir_node *block)
1941 ir_graph *irg = current_ir_graph;
1942 ir_node *new_val_true = be_transform_node(val_true);
1943 ir_node *new_val_false = be_transform_node(val_false);
1944 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1945 ir_node *nomem = new_NoMem();
1946 ir_node *new_cmp_left;
1947 ir_node *new_cmp_right;
1950 /* cmovs with unknowns are pointless... */
1951 if(is_Unknown(val_true)) {
1952 #ifdef DEBUG_libfirm
1953 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1955 return new_val_false;
1957 if(is_Unknown(val_false)) {
1958 #ifdef DEBUG_libfirm
1959 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1961 return new_val_true;
1964 /* can we use a test instruction? */
1965 if(is_Const_0(cmp_right)) {
1966 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1967 if(is_And(cmp_left) &&
1968 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1969 ir_node *and_left = get_And_left(cmp_left);
1970 ir_node *and_right = get_And_right(cmp_left);
1972 new_cmp_left = be_transform_node(and_left);
1973 new_cmp_right = create_immediate_or_transform(and_right, 0);
1975 new_cmp_left = be_transform_node(cmp_left);
1976 new_cmp_right = be_transform_node(cmp_left);
1979 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, block, noreg, noreg,
1980 new_cmp_left, new_cmp_right, nomem,
1981 new_val_true, new_val_false, pnc);
1982 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1987 new_cmp_left = be_transform_node(cmp_left);
1988 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1990 res = new_rd_ia32_CmpCMov(dbgi, irg, block, noreg, noreg, new_cmp_left,
1991 new_cmp_right, nomem, new_val_true, new_val_false,
1993 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
2000 * Transforms a Psi node into CMov.
2002 * @return The transformed node.
2004 static ir_node *gen_Psi(ir_node *node) {
2005 ir_node *psi_true = get_Psi_val(node, 0);
2006 ir_node *psi_default = get_Psi_default(node);
2007 ia32_code_gen_t *cg = env_cg;
2008 ir_node *cond = get_Psi_cond(node, 0);
2009 ir_node *block = be_transform_node(get_nodes_block(node));
2010 dbg_info *dbgi = get_irn_dbg_info(node);
2017 assert(get_Psi_n_conds(node) == 1);
2018 assert(get_irn_mode(cond) == mode_b);
2020 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
2021 /* a mode_b value, we have to compare it against 0 */
2023 cmp_right = new_Const_long(mode_Iu, 0);
2027 ir_node *cmp = get_Proj_pred(cond);
2029 cmp_left = get_Cmp_left(cmp);
2030 cmp_right = get_Cmp_right(cmp);
2031 cmp_mode = get_irn_mode(cmp_left);
2032 pnc = get_Proj_proj(cond);
2034 assert(!mode_is_float(cmp_mode));
2036 if (!mode_is_signed(cmp_mode)) {
2037 pnc |= ia32_pn_Cmp_Unsigned;
2041 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2042 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2043 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2044 pnc = get_negated_pnc(pnc, cmp_mode);
2045 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2047 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
2050 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2056 * Following conversion rules apply:
2060 * 1) n bit -> m bit n > m (downscale)
2062 * 2) n bit -> m bit n == m (sign change)
2064 * 3) n bit -> m bit n < m (upscale)
2065 * a) source is signed: movsx
2066 * b) source is unsigned: and with lower bits sets
2070 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2074 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2078 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2079 * x87 is mode_E internally, conversions happen only at load and store
2080 * in non-strict semantic
2084 * Create a conversion from x87 state register to general purpose.
2086 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2087 ir_node *block = be_transform_node(get_nodes_block(node));
2088 ir_node *op = get_Conv_op(node);
2089 ir_node *new_op = be_transform_node(op);
2090 ia32_code_gen_t *cg = env_cg;
2091 ir_graph *irg = current_ir_graph;
2092 dbg_info *dbgi = get_irn_dbg_info(node);
2093 ir_node *noreg = ia32_new_NoReg_gp(cg);
2094 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2095 ir_node *fist, *load;
2098 fist = new_rd_ia32_vfist(dbgi, irg, block,
2099 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2101 set_irn_pinned(fist, op_pin_state_floats);
2102 set_ia32_use_frame(fist);
2103 set_ia32_op_type(fist, ia32_AddrModeD);
2104 set_ia32_am_flavour(fist, ia32_am_B);
2105 set_ia32_ls_mode(fist, mode_Iu);
2106 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2109 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2111 set_irn_pinned(load, op_pin_state_floats);
2112 set_ia32_use_frame(load);
2113 set_ia32_op_type(load, ia32_AddrModeS);
2114 set_ia32_am_flavour(load, ia32_am_B);
2115 set_ia32_ls_mode(load, mode_Iu);
2116 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2118 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2121 static ir_node *create_strict_conv(ir_mode *tgt_mode, ir_node *node)
2123 ir_node *block = get_nodes_block(node);
2124 ir_graph *irg = current_ir_graph;
2125 dbg_info *dbgi = get_irn_dbg_info(node);
2126 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2127 ir_node *nomem = new_NoMem();
2128 ir_node *frame = get_irg_frame(irg);
2129 ir_node *store, *load;
2132 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2134 set_ia32_use_frame(store);
2135 set_ia32_op_type(store, ia32_AddrModeD);
2136 set_ia32_am_flavour(store, ia32_am_OB);
2137 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2139 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2141 set_ia32_use_frame(load);
2142 set_ia32_op_type(load, ia32_AddrModeS);
2143 set_ia32_am_flavour(load, ia32_am_OB);
2144 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2146 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2151 * Create a conversion from general purpose to x87 register
2153 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2154 ir_node *block = be_transform_node(get_nodes_block(node));
2155 ir_node *op = get_Conv_op(node);
2156 ir_node *new_op = be_transform_node(op);
2157 ir_graph *irg = current_ir_graph;
2158 dbg_info *dbgi = get_irn_dbg_info(node);
2159 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2160 ir_node *nomem = new_NoMem();
2161 ir_node *fild, *store;
2165 /* first convert to 32 bit if necessary */
2166 src_bits = get_mode_size_bits(src_mode);
2167 if (src_bits == 8) {
2168 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2169 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2170 set_ia32_ls_mode(new_op, src_mode);
2171 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2172 } else if (src_bits < 32) {
2173 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2174 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2175 set_ia32_ls_mode(new_op, src_mode);
2176 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2180 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2182 set_ia32_use_frame(store);
2183 set_ia32_op_type(store, ia32_AddrModeD);
2184 set_ia32_am_flavour(store, ia32_am_OB);
2185 set_ia32_ls_mode(store, mode_Iu);
2188 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2190 set_ia32_use_frame(fild);
2191 set_ia32_op_type(fild, ia32_AddrModeS);
2192 set_ia32_am_flavour(fild, ia32_am_OB);
2193 set_ia32_ls_mode(fild, mode_Iu);
2195 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2200 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2201 dbg_info *dbgi, ir_node *new_block,
2204 ir_graph *irg = current_ir_graph;
2205 int src_bits = get_mode_size_bits(src_mode);
2206 int tgt_bits = get_mode_size_bits(tgt_mode);
2207 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2208 ir_node *nomem = new_rd_NoMem(irg);
2210 ir_mode *smaller_mode;
2213 if (src_bits < tgt_bits) {
2214 smaller_mode = src_mode;
2215 smaller_bits = src_bits;
2217 smaller_mode = tgt_mode;
2218 smaller_bits = tgt_bits;
2221 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2222 if (smaller_bits == 8) {
2223 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2225 set_ia32_ls_mode(res, smaller_mode);
2227 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, noreg, noreg, new_op,
2229 set_ia32_ls_mode(res, smaller_mode);
2231 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2237 * Transforms a Conv node.
2239 * @return The created ia32 Conv node
2241 static ir_node *gen_Conv(ir_node *node) {
2242 ir_node *block = be_transform_node(get_nodes_block(node));
2243 ir_node *op = get_Conv_op(node);
2244 ir_node *new_op = be_transform_node(op);
2245 ir_graph *irg = current_ir_graph;
2246 dbg_info *dbgi = get_irn_dbg_info(node);
2247 ir_mode *src_mode = get_irn_mode(op);
2248 ir_mode *tgt_mode = get_irn_mode(node);
2249 int src_bits = get_mode_size_bits(src_mode);
2250 int tgt_bits = get_mode_size_bits(tgt_mode);
2251 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2252 ir_node *nomem = new_rd_NoMem(irg);
2255 if (src_mode == mode_b) {
2256 assert(mode_is_int(tgt_mode));
2257 /* nothing to do, we already model bools as 0/1 ints */
2261 if (src_mode == tgt_mode) {
2262 if (get_Conv_strict(node)) {
2263 if (USE_SSE2(env_cg)) {
2264 /* when we are in SSE mode, we can kill all strict no-op conversion */
2268 /* this should be optimized already, but who knows... */
2269 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2270 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2275 if (mode_is_float(src_mode)) {
2276 /* we convert from float ... */
2277 if (mode_is_float(tgt_mode)) {
2278 if(src_mode == mode_E && tgt_mode == mode_D
2279 && !get_Conv_strict(node)) {
2280 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2285 if (USE_SSE2(env_cg)) {
2286 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2287 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2288 set_ia32_ls_mode(res, tgt_mode);
2290 if(get_Conv_strict(node)) {
2291 res = create_strict_conv(tgt_mode, new_op);
2292 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2295 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2300 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2301 if (USE_SSE2(env_cg)) {
2302 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2303 set_ia32_ls_mode(res, src_mode);
2305 return gen_x87_fp_to_gp(node);
2309 /* we convert from int ... */
2310 if (mode_is_float(tgt_mode)) {
2312 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2313 if (USE_SSE2(env_cg)) {
2314 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2315 set_ia32_ls_mode(res, tgt_mode);
2316 if(src_bits == 32) {
2317 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2320 res = gen_x87_gp_to_fp(node, src_mode);
2321 if(get_Conv_strict(node)) {
2322 res = create_strict_conv(tgt_mode, res);
2323 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2324 ia32_get_old_node_name(env_cg, node));
2328 } else if(tgt_mode == mode_b) {
2329 /* mode_b lowering already took care that we only have 0/1 values */
2330 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2331 src_mode, tgt_mode));
2335 if (src_bits == tgt_bits) {
2336 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2337 src_mode, tgt_mode));
2341 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, new_op);
2345 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2351 int check_immediate_constraint(long val, char immediate_constraint_type)
2353 switch (immediate_constraint_type) {
2357 return val >= 0 && val <= 32;
2359 return val >= 0 && val <= 63;
2361 return val >= -128 && val <= 127;
2363 return val == 0xff || val == 0xffff;
2365 return val >= 0 && val <= 3;
2367 return val >= 0 && val <= 255;
2369 return val >= 0 && val <= 127;
2373 panic("Invalid immediate constraint found");
2378 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2381 tarval *offset = NULL;
2382 int offset_sign = 0;
2384 ir_entity *symconst_ent = NULL;
2385 int symconst_sign = 0;
2387 ir_node *cnst = NULL;
2388 ir_node *symconst = NULL;
2394 mode = get_irn_mode(node);
2395 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2399 if(is_Minus(node)) {
2401 node = get_Minus_op(node);
2404 if(is_Const(node)) {
2407 offset_sign = minus;
2408 } else if(is_SymConst(node)) {
2411 symconst_sign = minus;
2412 } else if(is_Add(node)) {
2413 ir_node *left = get_Add_left(node);
2414 ir_node *right = get_Add_right(node);
2415 if(is_Const(left) && is_SymConst(right)) {
2418 symconst_sign = minus;
2419 offset_sign = minus;
2420 } else if(is_SymConst(left) && is_Const(right)) {
2423 symconst_sign = minus;
2424 offset_sign = minus;
2426 } else if(is_Sub(node)) {
2427 ir_node *left = get_Sub_left(node);
2428 ir_node *right = get_Sub_right(node);
2429 if(is_Const(left) && is_SymConst(right)) {
2432 symconst_sign = !minus;
2433 offset_sign = minus;
2434 } else if(is_SymConst(left) && is_Const(right)) {
2437 symconst_sign = minus;
2438 offset_sign = !minus;
2445 offset = get_Const_tarval(cnst);
2446 if(tarval_is_long(offset)) {
2447 val = get_tarval_long(offset);
2448 } else if(tarval_is_null(offset)) {
2451 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2456 if(!check_immediate_constraint(val, immediate_constraint_type))
2459 if(symconst != NULL) {
2460 if(immediate_constraint_type != 0) {
2461 /* we need full 32bits for symconsts */
2465 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2467 symconst_ent = get_SymConst_entity(symconst);
2469 if(cnst == NULL && symconst == NULL)
2472 if(offset_sign && offset != NULL) {
2473 offset = tarval_neg(offset);
2476 irg = current_ir_graph;
2477 dbgi = get_irn_dbg_info(node);
2478 block = get_irg_start_block(irg);
2479 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2480 symconst_sign, val);
2481 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2487 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2489 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2490 if (new_node == NULL) {
2491 new_node = be_transform_node(node);
2496 typedef struct constraint_t constraint_t;
2497 struct constraint_t {
2500 const arch_register_req_t **out_reqs;
2502 const arch_register_req_t *req;
2503 unsigned immediate_possible;
2504 char immediate_type;
2507 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2509 int immediate_possible = 0;
2510 char immediate_type = 0;
2511 unsigned limited = 0;
2512 const arch_register_class_t *cls = NULL;
2514 struct obstack *obst;
2515 arch_register_req_t *req;
2516 unsigned *limited_ptr;
2520 /* TODO: replace all the asserts with nice error messages */
2522 printf("Constraint: %s\n", c);
2532 assert(cls == NULL ||
2533 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2534 cls = &ia32_reg_classes[CLASS_ia32_gp];
2535 limited |= 1 << REG_EAX;
2538 assert(cls == NULL ||
2539 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2540 cls = &ia32_reg_classes[CLASS_ia32_gp];
2541 limited |= 1 << REG_EBX;
2544 assert(cls == NULL ||
2545 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2546 cls = &ia32_reg_classes[CLASS_ia32_gp];
2547 limited |= 1 << REG_ECX;
2550 assert(cls == NULL ||
2551 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2552 cls = &ia32_reg_classes[CLASS_ia32_gp];
2553 limited |= 1 << REG_EDX;
2556 assert(cls == NULL ||
2557 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2558 cls = &ia32_reg_classes[CLASS_ia32_gp];
2559 limited |= 1 << REG_EDI;
2562 assert(cls == NULL ||
2563 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2564 cls = &ia32_reg_classes[CLASS_ia32_gp];
2565 limited |= 1 << REG_ESI;
2568 case 'q': /* q means lower part of the regs only, this makes no
2569 * difference to Q for us (we only assigne whole registers) */
2570 assert(cls == NULL ||
2571 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2572 cls = &ia32_reg_classes[CLASS_ia32_gp];
2573 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2577 assert(cls == NULL ||
2578 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2579 cls = &ia32_reg_classes[CLASS_ia32_gp];
2580 limited |= 1 << REG_EAX | 1 << REG_EDX;
2583 assert(cls == NULL ||
2584 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2585 cls = &ia32_reg_classes[CLASS_ia32_gp];
2586 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2587 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2594 assert(cls == NULL);
2595 cls = &ia32_reg_classes[CLASS_ia32_gp];
2601 /* TODO: mark values so the x87 simulator knows about t and u */
2602 assert(cls == NULL);
2603 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2608 assert(cls == NULL);
2609 /* TODO: check that sse2 is supported */
2610 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2620 assert(!immediate_possible);
2621 immediate_possible = 1;
2622 immediate_type = *c;
2626 assert(!immediate_possible);
2627 immediate_possible = 1;
2631 assert(!immediate_possible && cls == NULL);
2632 immediate_possible = 1;
2633 cls = &ia32_reg_classes[CLASS_ia32_gp];
2646 assert(constraint->is_in && "can only specify same constraint "
2649 sscanf(c, "%d%n", &same_as, &p);
2656 case 'E': /* no float consts yet */
2657 case 'F': /* no float consts yet */
2658 case 's': /* makes no sense on x86 */
2659 case 'X': /* we can't support that in firm */
2663 case '<': /* no autodecrement on x86 */
2664 case '>': /* no autoincrement on x86 */
2665 case 'C': /* sse constant not supported yet */
2666 case 'G': /* 80387 constant not supported yet */
2667 case 'y': /* we don't support mmx registers yet */
2668 case 'Z': /* not available in 32 bit mode */
2669 case 'e': /* not available in 32 bit mode */
2670 assert(0 && "asm constraint not supported");
2673 assert(0 && "unknown asm constraint found");
2680 const arch_register_req_t *other_constr;
2682 assert(cls == NULL && "same as and register constraint not supported");
2683 assert(!immediate_possible && "same as and immediate constraint not "
2685 assert(same_as < constraint->n_outs && "wrong constraint number in "
2686 "same_as constraint");
2688 other_constr = constraint->out_reqs[same_as];
2690 req = obstack_alloc(obst, sizeof(req[0]));
2691 req->cls = other_constr->cls;
2692 req->type = arch_register_req_type_should_be_same;
2693 req->limited = NULL;
2694 req->other_same = pos;
2695 req->other_different = -1;
2697 /* switch constraints. This is because in firm we have same_as
2698 * constraints on the output constraints while in the gcc asm syntax
2699 * they are specified on the input constraints */
2700 constraint->req = other_constr;
2701 constraint->out_reqs[same_as] = req;
2702 constraint->immediate_possible = 0;
2706 if(immediate_possible && cls == NULL) {
2707 cls = &ia32_reg_classes[CLASS_ia32_gp];
2709 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2710 assert(cls != NULL);
2712 if(immediate_possible) {
2713 assert(constraint->is_in
2714 && "imeediates make no sense for output constraints");
2716 /* todo: check types (no float input on 'r' constrainted in and such... */
2718 irg = current_ir_graph;
2719 obst = get_irg_obstack(irg);
2722 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2723 limited_ptr = (unsigned*) (req+1);
2725 req = obstack_alloc(obst, sizeof(req[0]));
2727 memset(req, 0, sizeof(req[0]));
2730 req->type = arch_register_req_type_limited;
2731 *limited_ptr = limited;
2732 req->limited = limited_ptr;
2734 req->type = arch_register_req_type_normal;
2738 constraint->req = req;
2739 constraint->immediate_possible = immediate_possible;
2740 constraint->immediate_type = immediate_type;
2744 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2751 panic("Clobbers not supported yet");
2754 ir_node *gen_ASM(ir_node *node)
2757 ir_graph *irg = current_ir_graph;
2758 ir_node *block = be_transform_node(get_nodes_block(node));
2759 dbg_info *dbgi = get_irn_dbg_info(node);
2766 ia32_asm_attr_t *attr;
2767 const arch_register_req_t **out_reqs;
2768 const arch_register_req_t **in_reqs;
2769 struct obstack *obst;
2770 constraint_t parsed_constraint;
2772 /* transform inputs */
2773 arity = get_irn_arity(node);
2774 in = alloca(arity * sizeof(in[0]));
2775 memset(in, 0, arity * sizeof(in[0]));
2777 n_outs = get_ASM_n_output_constraints(node);
2778 n_clobbers = get_ASM_n_clobbers(node);
2779 out_arity = n_outs + n_clobbers;
2781 /* construct register constraints */
2782 obst = get_irg_obstack(irg);
2783 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2784 parsed_constraint.out_reqs = out_reqs;
2785 parsed_constraint.n_outs = n_outs;
2786 parsed_constraint.is_in = 0;
2787 for(i = 0; i < out_arity; ++i) {
2791 const ir_asm_constraint *constraint;
2792 constraint = & get_ASM_output_constraints(node) [i];
2793 c = get_id_str(constraint->constraint);
2794 parse_asm_constraint(i, &parsed_constraint, c);
2796 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2797 c = get_id_str(glob_id);
2798 parse_clobber(node, i, &parsed_constraint, c);
2800 out_reqs[i] = parsed_constraint.req;
2803 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2804 parsed_constraint.is_in = 1;
2805 for(i = 0; i < arity; ++i) {
2806 const ir_asm_constraint *constraint;
2810 constraint = & get_ASM_input_constraints(node) [i];
2811 constr_id = constraint->constraint;
2812 c = get_id_str(constr_id);
2813 parse_asm_constraint(i, &parsed_constraint, c);
2814 in_reqs[i] = parsed_constraint.req;
2816 if(parsed_constraint.immediate_possible) {
2817 ir_node *pred = get_irn_n(node, i);
2818 char imm_type = parsed_constraint.immediate_type;
2819 ir_node *immediate = try_create_Immediate(pred, imm_type);
2821 if(immediate != NULL) {
2827 /* transform inputs */
2828 for(i = 0; i < arity; ++i) {
2830 ir_node *transformed;
2835 pred = get_irn_n(node, i);
2836 transformed = be_transform_node(pred);
2837 in[i] = transformed;
2840 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2842 generic_attr = get_irn_generic_attr(res);
2843 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2844 attr->asm_text = get_ASM_text(node);
2845 set_ia32_out_req_all(res, out_reqs);
2846 set_ia32_in_req_all(res, in_reqs);
2848 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2853 /********************************************
2856 * | |__ ___ _ __ ___ __| | ___ ___
2857 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2858 * | |_) | __/ | | | (_) | (_| | __/\__ \
2859 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2861 ********************************************/
2863 static ir_node *gen_be_StackParam(ir_node *node) {
2864 ir_node *block = be_transform_node(get_nodes_block(node));
2865 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2866 ir_node *new_ptr = be_transform_node(ptr);
2867 ir_node *new_op = NULL;
2868 ir_graph *irg = current_ir_graph;
2869 dbg_info *dbgi = get_irn_dbg_info(node);
2870 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2871 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2872 ir_mode *load_mode = get_irn_mode(node);
2873 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2877 if (mode_is_float(load_mode)) {
2878 if (USE_SSE2(env_cg)) {
2879 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2880 pn_res = pn_ia32_xLoad_res;
2881 proj_mode = mode_xmm;
2883 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2884 pn_res = pn_ia32_vfld_res;
2885 proj_mode = mode_vfp;
2888 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2889 proj_mode = mode_Iu;
2890 pn_res = pn_ia32_Load_res;
2893 set_irn_pinned(new_op, op_pin_state_floats);
2894 set_ia32_frame_ent(new_op, ent);
2895 set_ia32_use_frame(new_op);
2897 set_ia32_op_type(new_op, ia32_AddrModeS);
2898 set_ia32_am_flavour(new_op, ia32_am_B);
2899 set_ia32_ls_mode(new_op, load_mode);
2900 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2902 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2904 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2908 * Transforms a FrameAddr into an ia32 Add.
2910 static ir_node *gen_be_FrameAddr(ir_node *node) {
2911 ir_node *block = be_transform_node(get_nodes_block(node));
2912 ir_node *op = be_get_FrameAddr_frame(node);
2913 ir_node *new_op = be_transform_node(op);
2914 ir_graph *irg = current_ir_graph;
2915 dbg_info *dbgi = get_irn_dbg_info(node);
2916 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2919 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2920 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2921 set_ia32_use_frame(res);
2922 set_ia32_am_flavour(res, ia32_am_OB);
2924 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2930 * Transforms a FrameLoad into an ia32 Load.
2932 static ir_node *gen_be_FrameLoad(ir_node *node) {
2933 ir_node *block = be_transform_node(get_nodes_block(node));
2934 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2935 ir_node *new_mem = be_transform_node(mem);
2936 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2937 ir_node *new_ptr = be_transform_node(ptr);
2938 ir_node *new_op = NULL;
2939 ir_graph *irg = current_ir_graph;
2940 dbg_info *dbgi = get_irn_dbg_info(node);
2941 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2942 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2943 ir_mode *mode = get_type_mode(get_entity_type(ent));
2944 ir_node *projs[pn_Load_max];
2946 ia32_collect_Projs(node, projs, pn_Load_max);
2948 if (mode_is_float(mode)) {
2949 if (USE_SSE2(env_cg)) {
2950 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2953 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2957 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2960 set_irn_pinned(new_op, op_pin_state_floats);
2961 set_ia32_frame_ent(new_op, ent);
2962 set_ia32_use_frame(new_op);
2964 set_ia32_op_type(new_op, ia32_AddrModeS);
2965 set_ia32_am_flavour(new_op, ia32_am_B);
2966 set_ia32_ls_mode(new_op, mode);
2967 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2969 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2976 * Transforms a FrameStore into an ia32 Store.
2978 static ir_node *gen_be_FrameStore(ir_node *node) {
2979 ir_node *block = be_transform_node(get_nodes_block(node));
2980 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2981 ir_node *new_mem = be_transform_node(mem);
2982 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2983 ir_node *new_ptr = be_transform_node(ptr);
2984 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2985 ir_node *new_val = be_transform_node(val);
2986 ir_node *new_op = NULL;
2987 ir_graph *irg = current_ir_graph;
2988 dbg_info *dbgi = get_irn_dbg_info(node);
2989 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2990 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2991 ir_mode *mode = get_irn_mode(val);
2993 if (mode_is_float(mode)) {
2994 if (USE_SSE2(env_cg)) {
2995 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2997 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2999 } else if (get_mode_size_bits(mode) == 8) {
3000 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3002 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3005 set_ia32_frame_ent(new_op, ent);
3006 set_ia32_use_frame(new_op);
3008 set_ia32_op_type(new_op, ia32_AddrModeD);
3009 set_ia32_am_flavour(new_op, ia32_am_B);
3010 set_ia32_ls_mode(new_op, mode);
3012 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3018 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3020 static ir_node *gen_be_Return(ir_node *node) {
3021 ir_graph *irg = current_ir_graph;
3022 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3023 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3024 ir_entity *ent = get_irg_entity(irg);
3025 ir_type *tp = get_entity_type(ent);
3030 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3031 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3034 int pn_ret_val, pn_ret_mem, arity, i;
3036 assert(ret_val != NULL);
3037 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3038 return be_duplicate_node(node);
3041 res_type = get_method_res_type(tp, 0);
3043 if (! is_Primitive_type(res_type)) {
3044 return be_duplicate_node(node);
3047 mode = get_type_mode(res_type);
3048 if (! mode_is_float(mode)) {
3049 return be_duplicate_node(node);
3052 assert(get_method_n_ress(tp) == 1);
3054 pn_ret_val = get_Proj_proj(ret_val);
3055 pn_ret_mem = get_Proj_proj(ret_mem);
3057 /* get the Barrier */
3058 barrier = get_Proj_pred(ret_val);
3060 /* get result input of the Barrier */
3061 ret_val = get_irn_n(barrier, pn_ret_val);
3062 new_ret_val = be_transform_node(ret_val);
3064 /* get memory input of the Barrier */
3065 ret_mem = get_irn_n(barrier, pn_ret_mem);
3066 new_ret_mem = be_transform_node(ret_mem);
3068 frame = get_irg_frame(irg);
3070 dbgi = get_irn_dbg_info(barrier);
3071 block = be_transform_node(get_nodes_block(barrier));
3073 noreg = ia32_new_NoReg_gp(env_cg);
3075 /* store xmm0 onto stack */
3076 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3077 new_ret_val, new_ret_mem);
3078 set_ia32_ls_mode(sse_store, mode);
3079 set_ia32_op_type(sse_store, ia32_AddrModeD);
3080 set_ia32_use_frame(sse_store);
3081 set_ia32_am_flavour(sse_store, ia32_am_B);
3083 /* load into x87 register */
3084 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3085 set_ia32_op_type(fld, ia32_AddrModeS);
3086 set_ia32_use_frame(fld);
3087 set_ia32_am_flavour(fld, ia32_am_B);
3089 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3090 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3092 /* create a new barrier */
3093 arity = get_irn_arity(barrier);
3094 in = alloca(arity * sizeof(in[0]));
3095 for (i = 0; i < arity; ++i) {
3098 if (i == pn_ret_val) {
3100 } else if (i == pn_ret_mem) {
3103 ir_node *in = get_irn_n(barrier, i);
3104 new_in = be_transform_node(in);
3109 new_barrier = new_ir_node(dbgi, irg, block,
3110 get_irn_op(barrier), get_irn_mode(barrier),
3112 copy_node_attr(barrier, new_barrier);
3113 be_duplicate_deps(barrier, new_barrier);
3114 be_set_transformed_node(barrier, new_barrier);
3115 mark_irn_visited(barrier);
3117 /* transform normally */
3118 return be_duplicate_node(node);
3122 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3124 static ir_node *gen_be_AddSP(ir_node *node) {
3125 ir_node *block = be_transform_node(get_nodes_block(node));
3126 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3128 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3129 ir_node *new_sp = be_transform_node(sp);
3130 ir_graph *irg = current_ir_graph;
3131 dbg_info *dbgi = get_irn_dbg_info(node);
3132 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3133 ir_node *nomem = new_NoMem();
3136 new_sz = create_immediate_or_transform(sz, 0);
3138 /* ia32 stack grows in reverse direction, make a SubSP */
3139 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3141 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3142 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3148 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3150 static ir_node *gen_be_SubSP(ir_node *node) {
3151 ir_node *block = be_transform_node(get_nodes_block(node));
3152 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3154 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3155 ir_node *new_sp = be_transform_node(sp);
3156 ir_graph *irg = current_ir_graph;
3157 dbg_info *dbgi = get_irn_dbg_info(node);
3158 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3159 ir_node *nomem = new_NoMem();
3162 new_sz = create_immediate_or_transform(sz, 0);
3164 /* ia32 stack grows in reverse direction, make an AddSP */
3165 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3166 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3167 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3173 * This function just sets the register for the Unknown node
3174 * as this is not done during register allocation because Unknown
3175 * is an "ignore" node.
3177 static ir_node *gen_Unknown(ir_node *node) {
3178 ir_mode *mode = get_irn_mode(node);
3180 if (mode_is_float(mode)) {
3182 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3183 if (USE_SSE2(env_cg))
3184 return ia32_new_Unknown_xmm(env_cg);
3186 return ia32_new_Unknown_vfp(env_cg);
3188 ir_graph *irg = current_ir_graph;
3189 dbg_info *dbgi = get_irn_dbg_info(node);
3190 ir_node *block = get_irg_start_block(irg);
3191 return new_rd_ia32_vfldz(dbgi, irg, block);
3193 } else if (mode_needs_gp_reg(mode)) {
3194 return ia32_new_Unknown_gp(env_cg);
3196 assert(0 && "unsupported Unknown-Mode");
3203 * Change some phi modes
3205 static ir_node *gen_Phi(ir_node *node) {
3206 ir_node *block = be_transform_node(get_nodes_block(node));
3207 ir_graph *irg = current_ir_graph;
3208 dbg_info *dbgi = get_irn_dbg_info(node);
3209 ir_mode *mode = get_irn_mode(node);
3212 if(mode_needs_gp_reg(mode)) {
3213 /* we shouldn't have any 64bit stuff around anymore */
3214 assert(get_mode_size_bits(mode) <= 32);
3215 /* all integer operations are on 32bit registers now */
3217 } else if(mode_is_float(mode)) {
3218 if (USE_SSE2(env_cg)) {
3225 /* phi nodes allow loops, so we use the old arguments for now
3226 * and fix this later */
3227 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3228 copy_node_attr(node, phi);
3229 be_duplicate_deps(node, phi);
3231 be_set_transformed_node(node, phi);
3232 be_enqueue_preds(node);
3240 static ir_node *gen_IJmp(ir_node *node) {
3241 ir_node *block = be_transform_node(get_nodes_block(node));
3242 ir_graph *irg = current_ir_graph;
3243 dbg_info *dbgi = get_irn_dbg_info(node);
3244 ir_node *new_op = be_transform_node(get_IJmp_target(node));
3245 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3246 ir_node *nomem = new_NoMem();
3249 new_node = new_rd_ia32_IJmp(dbgi, irg, block, noreg, noreg, new_op, nomem);
3250 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_unary);
3252 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3258 /**********************************************************************
3261 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3262 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3263 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3264 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3266 **********************************************************************/
3268 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3270 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3273 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3274 ir_node *val, ir_node *mem);
3277 * Transforms a lowered Load into a "real" one.
3279 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3281 ir_node *block = be_transform_node(get_nodes_block(node));
3282 ir_node *ptr = get_irn_n(node, 0);
3283 ir_node *new_ptr = be_transform_node(ptr);
3284 ir_node *mem = get_irn_n(node, 1);
3285 ir_node *new_mem = be_transform_node(mem);
3286 ir_graph *irg = current_ir_graph;
3287 dbg_info *dbgi = get_irn_dbg_info(node);
3288 ir_mode *mode = get_ia32_ls_mode(node);
3289 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3292 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3294 set_ia32_op_type(new_op, ia32_AddrModeS);
3295 set_ia32_am_flavour(new_op, ia32_am_OB);
3296 set_ia32_am_offs_int(new_op, 0);
3297 set_ia32_am_scale(new_op, 1);
3298 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3299 if (is_ia32_am_sc_sign(node))
3300 set_ia32_am_sc_sign(new_op);
3301 set_ia32_ls_mode(new_op, mode);
3302 if (is_ia32_use_frame(node)) {
3303 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3304 set_ia32_use_frame(new_op);
3307 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3313 * Transforms a lowered Store into a "real" one.
3315 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3317 ir_node *block = be_transform_node(get_nodes_block(node));
3318 ir_node *ptr = get_irn_n(node, 0);
3319 ir_node *new_ptr = be_transform_node(ptr);
3320 ir_node *val = get_irn_n(node, 1);
3321 ir_node *new_val = be_transform_node(val);
3322 ir_node *mem = get_irn_n(node, 2);
3323 ir_node *new_mem = be_transform_node(mem);
3324 ir_graph *irg = current_ir_graph;
3325 dbg_info *dbgi = get_irn_dbg_info(node);
3326 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3327 ir_mode *mode = get_ia32_ls_mode(node);
3330 ia32_am_flavour_t am_flav = ia32_B;
3332 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3334 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3336 add_ia32_am_offs_int(new_op, am_offs);
3339 set_ia32_op_type(new_op, ia32_AddrModeD);
3340 set_ia32_am_flavour(new_op, am_flav);
3341 set_ia32_ls_mode(new_op, mode);
3342 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3343 set_ia32_use_frame(new_op);
3345 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3352 * Transforms an ia32_l_XXX into a "real" XXX node
3354 * @param env The transformation environment
3355 * @return the created ia32 XXX node
3357 #define GEN_LOWERED_OP(op) \
3358 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3359 return gen_binop(node, get_binop_left(node), \
3360 get_binop_right(node), new_rd_ia32_##op,0); \
3363 #define GEN_LOWERED_x87_OP(op) \
3364 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3366 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3367 get_binop_right(node), new_rd_ia32_##op); \
3371 #define GEN_LOWERED_UNOP(op) \
3372 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3373 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3376 #define GEN_LOWERED_SHIFT_OP(op) \
3377 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3378 return gen_shift_binop(node, get_binop_left(node), \
3379 get_binop_right(node), new_rd_ia32_##op); \
3382 #define GEN_LOWERED_LOAD(op) \
3383 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3384 return gen_lowered_Load(node, new_rd_ia32_##op); \
3387 #define GEN_LOWERED_STORE(op) \
3388 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3389 return gen_lowered_Store(node, new_rd_ia32_##op); \
3396 GEN_LOWERED_OP(IMul)
3398 GEN_LOWERED_x87_OP(vfprem)
3399 GEN_LOWERED_x87_OP(vfmul)
3400 GEN_LOWERED_x87_OP(vfsub)
3402 GEN_LOWERED_UNOP(Neg)
3404 GEN_LOWERED_LOAD(vfild)
3405 GEN_LOWERED_LOAD(Load)
3406 // GEN_LOWERED_STORE(vfist) TODO
3407 GEN_LOWERED_STORE(Store)
3409 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3410 ir_node *block = be_transform_node(get_nodes_block(node));
3411 ir_node *left = get_binop_left(node);
3412 ir_node *new_left = be_transform_node(left);
3413 ir_node *right = get_binop_right(node);
3414 ir_node *new_right = be_transform_node(right);
3415 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3416 ir_graph *irg = current_ir_graph;
3417 dbg_info *dbgi = get_irn_dbg_info(node);
3418 ir_node *fpcw = get_fpcw();
3421 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3422 new_right, new_NoMem(), fpcw);
3423 clear_ia32_commutative(vfdiv);
3424 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3426 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3432 * Transforms a l_MulS into a "real" MulS node.
3434 * @param env The transformation environment
3435 * @return the created ia32 Mul node
3437 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3438 ir_node *block = be_transform_node(get_nodes_block(node));
3439 ir_node *left = get_binop_left(node);
3440 ir_node *new_left = be_transform_node(left);
3441 ir_node *right = get_binop_right(node);
3442 ir_node *new_right = be_transform_node(right);
3443 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3444 ir_graph *irg = current_ir_graph;
3445 dbg_info *dbgi = get_irn_dbg_info(node);
3447 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3448 /* and then skip the result Proj, because all needed Projs are already there. */
3449 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3450 new_right, new_NoMem());
3451 clear_ia32_commutative(muls);
3452 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3454 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3459 GEN_LOWERED_SHIFT_OP(Shl)
3460 GEN_LOWERED_SHIFT_OP(Shr)
3461 GEN_LOWERED_SHIFT_OP(Sar)
3464 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3465 * op1 - target to be shifted
3466 * op2 - contains bits to be shifted into target
3468 * Only op3 can be an immediate.
3470 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3471 ir_node *op2, ir_node *count)
3473 ir_node *block = be_transform_node(get_nodes_block(node));
3474 ir_node *new_op1 = be_transform_node(op1);
3475 ir_node *new_op2 = be_transform_node(op2);
3476 ir_node *new_count = be_transform_node(count);
3477 ir_node *new_op = NULL;
3478 ir_graph *irg = current_ir_graph;
3479 dbg_info *dbgi = get_irn_dbg_info(node);
3480 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3481 ir_node *nomem = new_NoMem();
3485 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3487 /* Check if immediate optimization is on and */
3488 /* if it's an operation with immediate. */
3489 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3491 /* Limit imm_op within range imm8 */
3493 tv = get_ia32_Immop_tarval(imm_op);
3496 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3497 set_ia32_Immop_tarval(imm_op, tv);
3504 /* integer operations */
3506 /* This is ShiftD with const */
3507 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3509 if (is_ia32_l_ShlD(node))
3510 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3511 new_op1, new_op2, noreg, nomem);
3513 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3514 new_op1, new_op2, noreg, nomem);
3515 copy_ia32_Immop_attr(new_op, imm_op);
3518 /* This is a normal ShiftD */
3519 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3520 if (is_ia32_l_ShlD(node))
3521 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3522 new_op1, new_op2, new_count, nomem);
3524 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3525 new_op1, new_op2, new_count, nomem);
3528 /* set AM support */
3529 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3531 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3533 set_ia32_emit_cl(new_op);
3538 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3539 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3540 get_irn_n(node, 1), get_irn_n(node, 2));
3543 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3544 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3545 get_irn_n(node, 1), get_irn_n(node, 2));
3549 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3551 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3552 ir_node *block = be_transform_node(get_nodes_block(node));
3553 ir_node *val = get_irn_n(node, 1);
3554 ir_node *new_val = be_transform_node(val);
3555 ia32_code_gen_t *cg = env_cg;
3556 ir_node *res = NULL;
3557 ir_graph *irg = current_ir_graph;
3559 ir_node *noreg, *new_ptr, *new_mem;
3566 mem = get_irn_n(node, 2);
3567 new_mem = be_transform_node(mem);
3568 ptr = get_irn_n(node, 0);
3569 new_ptr = be_transform_node(ptr);
3570 noreg = ia32_new_NoReg_gp(cg);
3571 dbgi = get_irn_dbg_info(node);
3573 /* Store x87 -> MEM */
3574 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3575 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3576 set_ia32_use_frame(res);
3577 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3578 set_ia32_am_flavour(res, ia32_B);
3579 set_ia32_op_type(res, ia32_AddrModeD);
3581 /* Load MEM -> SSE */
3582 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3583 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3584 set_ia32_use_frame(res);
3585 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3586 set_ia32_am_flavour(res, ia32_B);
3587 set_ia32_op_type(res, ia32_AddrModeS);
3588 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3594 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3596 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3597 ir_node *block = be_transform_node(get_nodes_block(node));
3598 ir_node *val = get_irn_n(node, 1);
3599 ir_node *new_val = be_transform_node(val);
3600 ia32_code_gen_t *cg = env_cg;
3601 ir_graph *irg = current_ir_graph;
3602 ir_node *res = NULL;
3603 ir_entity *fent = get_ia32_frame_ent(node);
3604 ir_mode *lsmode = get_ia32_ls_mode(node);
3606 ir_node *noreg, *new_ptr, *new_mem;
3610 if (! USE_SSE2(cg)) {
3611 /* SSE unit is not used -> skip this node. */
3615 ptr = get_irn_n(node, 0);
3616 new_ptr = be_transform_node(ptr);
3617 mem = get_irn_n(node, 2);
3618 new_mem = be_transform_node(mem);
3619 noreg = ia32_new_NoReg_gp(cg);
3620 dbgi = get_irn_dbg_info(node);
3622 /* Store SSE -> MEM */
3623 if (is_ia32_xLoad(skip_Proj(new_val))) {
3624 ir_node *ld = skip_Proj(new_val);
3626 /* we can vfld the value directly into the fpu */
3627 fent = get_ia32_frame_ent(ld);
3628 ptr = get_irn_n(ld, 0);
3629 offs = get_ia32_am_offs_int(ld);
3631 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3632 set_ia32_frame_ent(res, fent);
3633 set_ia32_use_frame(res);
3634 set_ia32_ls_mode(res, lsmode);
3635 set_ia32_am_flavour(res, ia32_B);
3636 set_ia32_op_type(res, ia32_AddrModeD);
3640 /* Load MEM -> x87 */
3641 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3642 set_ia32_frame_ent(res, fent);
3643 set_ia32_use_frame(res);
3644 add_ia32_am_offs_int(res, offs);
3645 set_ia32_am_flavour(res, ia32_B);
3646 set_ia32_op_type(res, ia32_AddrModeS);
3647 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3652 /*********************************************************
3655 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3656 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3657 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3658 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3660 *********************************************************/
3663 * the BAD transformer.
3665 static ir_node *bad_transform(ir_node *node) {
3666 panic("No transform function for %+F available.\n", node);
3671 * Transform the Projs of an AddSP.
3673 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3674 ir_node *block = be_transform_node(get_nodes_block(node));
3675 ir_node *pred = get_Proj_pred(node);
3676 ir_node *new_pred = be_transform_node(pred);
3677 ir_graph *irg = current_ir_graph;
3678 dbg_info *dbgi = get_irn_dbg_info(node);
3679 long proj = get_Proj_proj(node);
3681 if (proj == pn_be_AddSP_sp) {
3682 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3683 pn_ia32_SubSP_stack);
3684 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3686 } else if(proj == pn_be_AddSP_res) {
3687 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3688 pn_ia32_SubSP_addr);
3689 } else if (proj == pn_be_AddSP_M) {
3690 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3694 return new_rd_Unknown(irg, get_irn_mode(node));
3698 * Transform the Projs of a SubSP.
3700 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3701 ir_node *block = be_transform_node(get_nodes_block(node));
3702 ir_node *pred = get_Proj_pred(node);
3703 ir_node *new_pred = be_transform_node(pred);
3704 ir_graph *irg = current_ir_graph;
3705 dbg_info *dbgi = get_irn_dbg_info(node);
3706 long proj = get_Proj_proj(node);
3708 if (proj == pn_be_SubSP_sp) {
3709 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3710 pn_ia32_AddSP_stack);
3711 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3713 } else if (proj == pn_be_SubSP_M) {
3714 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3718 return new_rd_Unknown(irg, get_irn_mode(node));
3722 * Transform and renumber the Projs from a Load.
3724 static ir_node *gen_Proj_Load(ir_node *node) {
3725 ir_node *block = be_transform_node(get_nodes_block(node));
3726 ir_node *pred = get_Proj_pred(node);
3727 ir_node *new_pred = be_transform_node(pred);
3728 ir_graph *irg = current_ir_graph;
3729 dbg_info *dbgi = get_irn_dbg_info(node);
3730 long proj = get_Proj_proj(node);
3732 /* renumber the proj */
3733 if (is_ia32_Load(new_pred)) {
3734 if (proj == pn_Load_res) {
3735 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3736 } else if (proj == pn_Load_M) {
3737 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3739 } else if (is_ia32_xLoad(new_pred)) {
3740 if (proj == pn_Load_res) {
3741 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3742 } else if (proj == pn_Load_M) {
3743 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3745 } else if (is_ia32_vfld(new_pred)) {
3746 if (proj == pn_Load_res) {
3747 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3748 } else if (proj == pn_Load_M) {
3749 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3754 return new_rd_Unknown(irg, get_irn_mode(node));
3758 * Transform and renumber the Projs from a DivMod like instruction.
3760 static ir_node *gen_Proj_DivMod(ir_node *node) {
3761 ir_node *block = be_transform_node(get_nodes_block(node));
3762 ir_node *pred = get_Proj_pred(node);
3763 ir_node *new_pred = be_transform_node(pred);
3764 ir_graph *irg = current_ir_graph;
3765 dbg_info *dbgi = get_irn_dbg_info(node);
3766 ir_mode *mode = get_irn_mode(node);
3767 long proj = get_Proj_proj(node);
3769 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3771 switch (get_irn_opcode(pred)) {
3775 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3777 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3785 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3787 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3795 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3796 case pn_DivMod_res_div:
3797 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3798 case pn_DivMod_res_mod:
3799 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3809 return new_rd_Unknown(irg, mode);
3813 * Transform and renumber the Projs from a CopyB.
3815 static ir_node *gen_Proj_CopyB(ir_node *node) {
3816 ir_node *block = be_transform_node(get_nodes_block(node));
3817 ir_node *pred = get_Proj_pred(node);
3818 ir_node *new_pred = be_transform_node(pred);
3819 ir_graph *irg = current_ir_graph;
3820 dbg_info *dbgi = get_irn_dbg_info(node);
3821 ir_mode *mode = get_irn_mode(node);
3822 long proj = get_Proj_proj(node);
3825 case pn_CopyB_M_regular:
3826 if (is_ia32_CopyB_i(new_pred)) {
3827 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3828 } else if (is_ia32_CopyB(new_pred)) {
3829 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3837 return new_rd_Unknown(irg, mode);
3841 * Transform and renumber the Projs from a vfdiv.
3843 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3844 ir_node *block = be_transform_node(get_nodes_block(node));
3845 ir_node *pred = get_Proj_pred(node);
3846 ir_node *new_pred = be_transform_node(pred);
3847 ir_graph *irg = current_ir_graph;
3848 dbg_info *dbgi = get_irn_dbg_info(node);
3849 ir_mode *mode = get_irn_mode(node);
3850 long proj = get_Proj_proj(node);
3853 case pn_ia32_l_vfdiv_M:
3854 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3855 case pn_ia32_l_vfdiv_res:
3856 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3861 return new_rd_Unknown(irg, mode);
3865 * Transform and renumber the Projs from a Quot.
3867 static ir_node *gen_Proj_Quot(ir_node *node) {
3868 ir_node *block = be_transform_node(get_nodes_block(node));
3869 ir_node *pred = get_Proj_pred(node);
3870 ir_node *new_pred = be_transform_node(pred);
3871 ir_graph *irg = current_ir_graph;
3872 dbg_info *dbgi = get_irn_dbg_info(node);
3873 ir_mode *mode = get_irn_mode(node);
3874 long proj = get_Proj_proj(node);
3878 if (is_ia32_xDiv(new_pred)) {
3879 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3880 } else if (is_ia32_vfdiv(new_pred)) {
3881 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3885 if (is_ia32_xDiv(new_pred)) {
3886 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3887 } else if (is_ia32_vfdiv(new_pred)) {
3888 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3896 return new_rd_Unknown(irg, mode);
3900 * Transform the Thread Local Storage Proj.
3902 static ir_node *gen_Proj_tls(ir_node *node) {
3903 ir_node *block = be_transform_node(get_nodes_block(node));
3904 ir_graph *irg = current_ir_graph;
3905 dbg_info *dbgi = NULL;
3906 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3912 * Transform the Projs from a be_Call.
3914 static ir_node *gen_Proj_be_Call(ir_node *node) {
3915 ir_node *block = be_transform_node(get_nodes_block(node));
3916 ir_node *call = get_Proj_pred(node);
3917 ir_node *new_call = be_transform_node(call);
3918 ir_graph *irg = current_ir_graph;
3919 dbg_info *dbgi = get_irn_dbg_info(node);
3920 long proj = get_Proj_proj(node);
3921 ir_mode *mode = get_irn_mode(node);
3923 const arch_register_class_t *cls;
3925 /* The following is kinda tricky: If we're using SSE, then we have to
3926 * move the result value of the call in floating point registers to an
3927 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3928 * after the call, we have to make sure to correctly make the
3929 * MemProj and the result Proj use these 2 nodes
3931 if (proj == pn_be_Call_M_regular) {
3932 // get new node for result, are we doing the sse load/store hack?
3933 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3934 ir_node *call_res_new;
3935 ir_node *call_res_pred = NULL;
3937 if (call_res != NULL) {
3938 call_res_new = be_transform_node(call_res);
3939 call_res_pred = get_Proj_pred(call_res_new);
3942 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3943 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
3944 pn_be_Call_M_regular);
3946 assert(is_ia32_xLoad(call_res_pred));
3947 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
3951 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3953 ir_node *frame = get_irg_frame(irg);
3954 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3956 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3959 /* in case there is no memory output: create one to serialize the copy
3961 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
3962 pn_be_Call_M_regular);
3963 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
3964 pn_be_Call_first_res);
3966 /* store st(0) onto stack */
3967 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
3969 set_ia32_op_type(fstp, ia32_AddrModeD);
3970 set_ia32_use_frame(fstp);
3971 set_ia32_am_flavour(fstp, ia32_am_B);
3973 /* load into SSE register */
3974 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3975 set_ia32_ls_mode(sse_load, mode);
3976 set_ia32_op_type(sse_load, ia32_AddrModeS);
3977 set_ia32_use_frame(sse_load);
3978 set_ia32_am_flavour(sse_load, ia32_am_B);
3980 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
3984 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3986 /* get a Proj representing a caller save register */
3987 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3988 assert(is_Proj(p) && "Proj expected.");
3990 /* user of the the proj is the Keep */
3991 p = get_edge_src_irn(get_irn_out_edge_first(p));
3992 assert(be_is_Keep(p) && "Keep expected.");
3998 /* transform call modes */
3999 if (mode_is_data(mode)) {
4000 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4004 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4008 * Transform the Projs from a Cmp.
4010 static ir_node *gen_Proj_Cmp(ir_node *node)
4012 /* normally Cmps are processed when looking at Cond nodes, but this case
4013 * can happen in complicated Psi conditions */
4015 ir_node *cmp = get_Proj_pred(node);
4016 long pnc = get_Proj_proj(node);
4017 ir_node *cmp_left = get_Cmp_left(cmp);
4018 ir_node *cmp_right = get_Cmp_right(cmp);
4019 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4020 dbg_info *dbgi = get_irn_dbg_info(cmp);
4021 ir_node *block = be_transform_node(get_nodes_block(node));
4024 assert(!mode_is_float(cmp_mode));
4026 if(!mode_is_signed(cmp_mode)) {
4027 pnc |= ia32_pn_Cmp_Unsigned;
4030 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
4031 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
4037 * Transform and potentially renumber Proj nodes.
4039 static ir_node *gen_Proj(ir_node *node) {
4040 ir_graph *irg = current_ir_graph;
4041 dbg_info *dbgi = get_irn_dbg_info(node);
4042 ir_node *pred = get_Proj_pred(node);
4043 long proj = get_Proj_proj(node);
4045 if (is_Store(pred) || be_is_FrameStore(pred)) {
4046 if (proj == pn_Store_M) {
4047 return be_transform_node(pred);
4050 return new_r_Bad(irg);
4052 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4053 return gen_Proj_Load(node);
4054 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4055 return gen_Proj_DivMod(node);
4056 } else if (is_CopyB(pred)) {
4057 return gen_Proj_CopyB(node);
4058 } else if (is_Quot(pred)) {
4059 return gen_Proj_Quot(node);
4060 } else if (is_ia32_l_vfdiv(pred)) {
4061 return gen_Proj_l_vfdiv(node);
4062 } else if (be_is_SubSP(pred)) {
4063 return gen_Proj_be_SubSP(node);
4064 } else if (be_is_AddSP(pred)) {
4065 return gen_Proj_be_AddSP(node);
4066 } else if (be_is_Call(pred)) {
4067 return gen_Proj_be_Call(node);
4068 } else if (is_Cmp(pred)) {
4069 return gen_Proj_Cmp(node);
4070 } else if (get_irn_op(pred) == op_Start) {
4071 if (proj == pn_Start_X_initial_exec) {
4072 ir_node *block = get_nodes_block(pred);
4075 /* we exchange the ProjX with a jump */
4076 block = be_transform_node(block);
4077 jump = new_rd_Jmp(dbgi, irg, block);
4080 if (node == be_get_old_anchor(anchor_tls)) {
4081 return gen_Proj_tls(node);
4084 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4088 ir_node *new_pred = be_transform_node(pred);
4089 ir_node *block = be_transform_node(get_nodes_block(node));
4090 ir_mode *mode = get_irn_mode(node);
4091 if (mode_needs_gp_reg(mode)) {
4092 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4093 get_Proj_proj(node));
4094 #ifdef DEBUG_libfirm
4095 new_proj->node_nr = node->node_nr;
4101 return be_duplicate_node(node);
4105 * Enters all transform functions into the generic pointer
4107 static void register_transformers(void)
4111 /* first clear the generic function pointer for all ops */
4112 clear_irp_opcodes_generic_func();
4114 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4115 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4152 /* transform ops from intrinsic lowering */
4172 /* GEN(ia32_l_vfist); TODO */
4174 GEN(ia32_l_X87toSSE);
4175 GEN(ia32_l_SSEtoX87);
4180 /* we should never see these nodes */
4195 /* handle generic backend nodes */
4206 /* set the register for all Unknown nodes */
4209 op_Mulh = get_op_Mulh();
4218 * Pre-transform all unknown and noreg nodes.
4220 static void ia32_pretransform_node(void *arch_cg) {
4221 ia32_code_gen_t *cg = arch_cg;
4223 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4224 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4225 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4226 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4227 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4228 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4233 void add_missing_keep_walker(ir_node *node, void *data)
4236 unsigned found_projs = 0;
4237 const ir_edge_t *edge;
4238 ir_mode *mode = get_irn_mode(node);
4243 if(!is_ia32_irn(node))
4246 n_outs = get_ia32_n_res(node);
4249 if(is_ia32_SwitchJmp(node))
4252 assert(n_outs < (int) sizeof(unsigned) * 8);
4253 foreach_out_edge(node, edge) {
4254 ir_node *proj = get_edge_src_irn(edge);
4255 int pn = get_Proj_proj(proj);
4257 assert(pn < n_outs);
4258 found_projs |= 1 << pn;
4262 /* are keeps missing? */
4264 for(i = 0; i < n_outs; ++i) {
4267 const arch_register_req_t *req;
4268 const arch_register_class_t *class;
4270 if(found_projs & (1 << i)) {
4274 req = get_ia32_out_req(node, i);
4280 block = get_nodes_block(node);
4281 in[0] = new_r_Proj(current_ir_graph, block, node,
4282 arch_register_class_mode(class), i);
4283 if(last_keep != NULL) {
4284 be_Keep_add_node(last_keep, class, in[0]);
4286 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4292 * Adds missing keeps to nodes
4295 void add_missing_keeps(ia32_code_gen_t *cg)
4297 ir_graph *irg = be_get_birg_irg(cg->birg);
4298 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4301 /* do the transformation */
4302 void ia32_transform_graph(ia32_code_gen_t *cg) {
4303 register_transformers();
4305 initial_fpcw = NULL;
4306 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4307 edges_verify(cg->irg);
4308 add_missing_keeps(cg);
4309 edges_verify(cg->irg);
4312 void ia32_init_transform(void)
4314 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");