2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
30 #include "archop.h" /* we need this for Min and Max nodes */
37 #include "../benode_t.h"
38 #include "../besched.h"
40 #include "../beutil.h"
42 #include "bearch_ia32_t.h"
43 #include "ia32_nodes_attr.h"
44 #include "ia32_transform.h"
45 #include "ia32_new_nodes.h"
46 #include "ia32_map_regs.h"
47 #include "ia32_dbg_stat.h"
48 #include "ia32_optimize.h"
49 #include "ia32_util.h"
51 #include "gen_ia32_regalloc_if.h"
53 #define SFP_SIGN "0x80000000"
54 #define DFP_SIGN "0x8000000000000000"
55 #define SFP_ABS "0x7FFFFFFF"
56 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
58 #define TP_SFP_SIGN "ia32_sfp_sign"
59 #define TP_DFP_SIGN "ia32_dfp_sign"
60 #define TP_SFP_ABS "ia32_sfp_abs"
61 #define TP_DFP_ABS "ia32_dfp_abs"
63 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
64 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
65 #define ENT_SFP_ABS "IA32_SFP_ABS"
66 #define ENT_DFP_ABS "IA32_DFP_ABS"
68 typedef struct ia32_transform_env_t {
69 ir_graph *irg; /**< The irg, the node should be created in */
70 ia32_code_gen_t *cg; /**< The code generator */
71 int visited; /**< visited count that indicates whether a
72 node is already transformed */
73 pdeq *worklist; /**< worklist of nodes that still need to be
75 ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/
76 DEBUG_ONLY(firm_dbg_module_t *mod;) /**< The firm debugger */
77 } ia32_transform_env_t;
79 extern ir_op *get_op_Mulh(void);
81 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
82 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
83 ir_node *op2, ir_node *mem);
85 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
86 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
89 typedef ir_node *(transform_func)(ia32_transform_env_t *env, ir_node *node);
91 /****************************************************************************************************
93 * | | | | / _| | | (_)
94 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
95 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
96 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
97 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
99 ****************************************************************************************************/
101 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node);
102 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node);
103 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
106 static INLINE void set_new_node(ir_node *old_node, ir_node *new_node)
108 set_irn_link(old_node, new_node);
111 static INLINE ir_node *get_new_node(ir_node *old_node)
113 assert(irn_visited(old_node));
114 return (ir_node*) get_irn_link(old_node);
118 * Returns 1 if irn is a Const representing 0, 0 otherwise
120 static INLINE int is_ia32_Const_0(ir_node *irn) {
121 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
122 && tarval_is_null(get_ia32_Immop_tarval(irn));
126 * Returns 1 if irn is a Const representing 1, 0 otherwise
128 static INLINE int is_ia32_Const_1(ir_node *irn) {
129 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
130 && tarval_is_one(get_ia32_Immop_tarval(irn));
134 * Collects all Projs of a node into the node array. Index is the projnum.
135 * BEWARE: The caller has to assure the appropriate array size!
137 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
138 const ir_edge_t *edge;
139 assert(get_irn_mode(irn) == mode_T && "need mode_T");
141 memset(projs, 0, size * sizeof(projs[0]));
143 foreach_out_edge(irn, edge) {
144 ir_node *proj = get_edge_src_irn(edge);
145 int proj_proj = get_Proj_proj(proj);
146 assert(proj_proj < size);
147 projs[proj_proj] = proj;
152 * Renumbers the proj having pn_old in the array tp pn_new
153 * and removes the proj from the array.
155 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
156 fprintf(stderr, "Warning: renumber_Proj used!\n");
158 set_Proj_proj(projs[pn_old], pn_new);
159 projs[pn_old] = NULL;
164 * creates a unique ident by adding a number to a tag
166 * @param tag the tag string, must contain a %d if a number
169 static ident *unique_id(const char *tag)
171 static unsigned id = 0;
174 snprintf(str, sizeof(str), tag, ++id);
175 return new_id_from_str(str);
179 * Get a primitive type for a mode.
181 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
183 pmap_entry *e = pmap_find(types, mode);
188 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
189 res = new_type_primitive(new_id_from_str(buf), mode);
190 pmap_insert(types, mode, res);
198 * Get an entity that is initialized with a tarval
200 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
202 tarval *tv = get_Const_tarval(cnst);
203 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
208 ir_mode *mode = get_irn_mode(cnst);
209 ir_type *tp = get_Const_type(cnst);
210 if (tp == firm_unknown_type)
211 tp = get_prim_type(cg->isa->types, mode);
213 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
215 set_entity_ld_ident(res, get_entity_ident(res));
216 set_entity_visibility(res, visibility_local);
217 set_entity_variability(res, variability_constant);
218 set_entity_allocation(res, allocation_static);
220 /* we create a new entity here: It's initialization must resist on the
222 rem = current_ir_graph;
223 current_ir_graph = get_const_code_irg();
224 set_atomic_ent_value(res, new_Const_type(tv, tp));
225 current_ir_graph = rem;
227 pmap_insert(cg->isa->tv_ent, tv, res);
235 * Transforms a Const.
237 * @param mod the debug module
238 * @param block the block the new node should belong to
239 * @param node the ir Const node
240 * @param mode mode of the Const
241 * @return the created ia32 Const node
243 static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) {
244 ir_graph *irg = env->irg;
245 dbg_info *dbg = get_irn_dbg_info(node);
246 ir_mode *mode = get_irn_mode(node);
247 ir_node *block = transform_node(env, get_nodes_block(node));
249 if (mode_is_float(mode)) {
252 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
253 ir_node *nomem = new_NoMem();
257 if (! USE_SSE2(env->cg)) {
258 cnst_classify_t clss = classify_Const(node);
260 if (clss == CNST_NULL) {
261 load = new_rd_ia32_vfldz(dbg, irg, block);
263 } else if (clss == CNST_ONE) {
264 load = new_rd_ia32_vfld1(dbg, irg, block);
267 floatent = get_entity_for_tv(env->cg, node);
269 load = new_rd_ia32_vfld(dbg, irg, block, noreg, noreg, nomem);
270 set_ia32_am_support(load, ia32_am_Source);
271 set_ia32_op_type(load, ia32_AddrModeS);
272 set_ia32_am_flavour(load, ia32_am_N);
273 set_ia32_am_sc(load, ia32_get_ent_ident(floatent));
274 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
277 floatent = get_entity_for_tv(env->cg, node);
279 load = new_rd_ia32_xLoad(dbg, irg, block, noreg, noreg, nomem);
280 set_ia32_am_support(load, ia32_am_Source);
281 set_ia32_op_type(load, ia32_AddrModeS);
282 set_ia32_am_flavour(load, ia32_am_N);
283 set_ia32_am_sc(load, ia32_get_ent_ident(floatent));
284 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_xLoad_res);
287 set_ia32_ls_mode(load, mode);
288 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
290 /* Const Nodes before the initial IncSP are a bad idea, because
291 * they could be spilled and we have no SP ready at that point yet
293 if (get_irg_start_block(irg) == block) {
294 add_irn_dep(load, get_irg_frame(irg));
297 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
300 ir_node *cnst = new_rd_ia32_Const(dbg, irg, block);
303 if (get_irg_start_block(irg) == block) {
304 add_irn_dep(cnst, get_irg_frame(irg));
307 set_ia32_Const_attr(cnst, node);
308 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
313 return new_r_Bad(irg);
317 * Transforms a SymConst.
319 * @param mod the debug module
320 * @param block the block the new node should belong to
321 * @param node the ir SymConst node
322 * @param mode mode of the SymConst
323 * @return the created ia32 Const node
325 static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) {
326 ir_graph *irg = env->irg;
327 dbg_info *dbg = get_irn_dbg_info(node);
328 ir_mode *mode = get_irn_mode(node);
329 ir_node *block = transform_node(env, get_nodes_block(node));
332 if (mode_is_float(mode)) {
334 if (USE_SSE2(env->cg))
335 cnst = new_rd_ia32_xConst(dbg, irg, block);
337 cnst = new_rd_ia32_vfConst(dbg, irg, block);
338 set_ia32_ls_mode(cnst, mode);
340 cnst = new_rd_ia32_Const(dbg, irg, block);
343 /* Const Nodes before the initial IncSP are a bad idea, because
344 * they could be spilled and we have no SP ready at that point yet
346 if (get_irg_start_block(irg) == block) {
347 add_irn_dep(cnst, get_irg_frame(irg));
350 set_ia32_Const_attr(cnst, node);
351 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
357 * SSE convert of an integer node into a floating point node.
359 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg,
360 ir_graph *irg, ir_node *block,
361 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
363 ir_node *noreg = ia32_new_NoReg_gp(cg);
364 ir_node *nomem = new_rd_NoMem(irg);
365 ir_node *old_pred = get_Cmp_left(old_node);
366 ir_mode *in_mode = get_irn_mode(old_pred);
367 int in_bits = get_mode_size_bits(in_mode);
369 ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
370 set_ia32_ls_mode(conv, tgt_mode);
372 set_ia32_am_support(conv, ia32_am_Source);
374 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
380 * SSE convert of an float node into a double node.
382 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbg,
383 ir_graph *irg, ir_node *block,
384 ir_node *in, ir_node *old_node)
386 ir_node *noreg = ia32_new_NoReg_gp(cg);
387 ir_node *nomem = new_rd_NoMem(irg);
389 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, in, nomem);
390 set_ia32_am_support(conv, ia32_am_Source);
391 set_ia32_ls_mode(conv, mode_E);
392 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
397 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
398 ident *ia32_gen_fp_known_const(ia32_known_const_t kct) {
399 static const struct {
401 const char *ent_name;
402 const char *cnst_str;
403 } names [ia32_known_const_max] = {
404 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
405 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
406 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
407 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
409 static ir_entity *ent_cache[ia32_known_const_max];
411 const char *tp_name, *ent_name, *cnst_str;
419 ent_name = names[kct].ent_name;
420 if (! ent_cache[kct]) {
421 tp_name = names[kct].tp_name;
422 cnst_str = names[kct].cnst_str;
424 //mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
426 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
427 tp = new_type_primitive(new_id_from_str(tp_name), mode);
428 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
430 set_entity_ld_ident(ent, get_entity_ident(ent));
431 set_entity_visibility(ent, visibility_local);
432 set_entity_variability(ent, variability_constant);
433 set_entity_allocation(ent, allocation_static);
435 /* we create a new entity here: It's initialization must resist on the
437 rem = current_ir_graph;
438 current_ir_graph = get_const_code_irg();
439 cnst = new_Const(mode, tv);
440 current_ir_graph = rem;
442 set_atomic_ent_value(ent, cnst);
444 /* cache the entry */
445 ent_cache[kct] = ent;
448 return get_entity_ident(ent_cache[kct]);
453 * Prints the old node name on cg obst and returns a pointer to it.
455 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
456 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
458 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
459 obstack_1grow(isa->name_obst, 0);
460 return obstack_finish(isa->name_obst);
464 /* determine if one operator is an Imm */
465 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
467 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
468 else return is_ia32_Cnst(op2) ? op2 : NULL;
471 /* determine if one operator is not an Imm */
472 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
473 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
476 static void fold_immediate(ia32_transform_env_t *env, ir_node *node, int in1, int in2) {
480 if(! (env->cg->opt & IA32_OPT_IMMOPS))
483 left = get_irn_n(node, in1);
484 right = get_irn_n(node, in2);
485 if(!is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
486 /* we can only set right operand to immediate */
487 if(!is_ia32_commutative(node))
489 /* exchange left/right */
490 set_irn_n(node, in1, right);
491 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
492 copy_ia32_Immop_attr(node, left);
493 } else if(is_ia32_Cnst(right)) {
494 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
495 copy_ia32_Immop_attr(node, right);
500 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
504 * Construct a standard binary operation, set AM and immediate if required.
506 * @param env The transformation environment
507 * @param op1 The first operand
508 * @param op2 The second operand
509 * @param func The node constructor function
510 * @return The constructed ia32 node.
512 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *node,
513 ir_node *op1, ir_node *op2,
514 construct_binop_func *func) {
515 ir_node *new_node = NULL;
516 ir_graph *irg = env->irg;
517 dbg_info *dbg = get_irn_dbg_info(node);
518 ir_node *block = transform_node(env, get_nodes_block(node));
519 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
520 ir_node *nomem = new_NoMem();
521 ir_node *new_op1 = transform_node(env, op1);
522 ir_node *new_op2 = transform_node(env, op2);
524 new_node = func(dbg, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
525 if(func == new_rd_ia32_IMul) {
526 set_ia32_am_support(new_node, ia32_am_Source);
528 set_ia32_am_support(new_node, ia32_am_Full);
531 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
532 if (is_op_commutative(get_irn_op(node))) {
533 set_ia32_commutative(new_node);
535 fold_immediate(env, new_node, 2, 3);
541 * Construct a standard binary operation, set AM and immediate if required.
543 * @param env The transformation environment
544 * @param op1 The first operand
545 * @param op2 The second operand
546 * @param func The node constructor function
547 * @return The constructed ia32 node.
549 static ir_node *gen_binop_float(ia32_transform_env_t *env, ir_node *node,
550 ir_node *op1, ir_node *op2,
551 construct_binop_func *func)
553 ir_node *new_node = NULL;
554 dbg_info *dbg = get_irn_dbg_info(node);
555 ir_graph *irg = env->irg;
556 ir_mode *mode = get_irn_mode(node);
557 ir_node *block = transform_node(env, get_nodes_block(node));
558 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
559 ir_node *nomem = new_NoMem();
560 ir_node *new_op1 = transform_node(env, op1);
561 ir_node *new_op2 = transform_node(env, op2);
563 new_node = func(dbg, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
564 set_ia32_am_support(new_node, ia32_am_Source);
565 if (is_op_commutative(get_irn_op(node))) {
566 set_ia32_commutative(new_node);
568 if (USE_SSE2(env->cg)) {
569 set_ia32_ls_mode(new_node, mode);
572 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
579 * Construct a shift/rotate binary operation, sets AM and immediate if required.
581 * @param env The transformation environment
582 * @param op1 The first operand
583 * @param op2 The second operand
584 * @param func The node constructor function
585 * @return The constructed ia32 node.
587 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node,
588 ir_node *op1, ir_node *op2,
589 construct_binop_func *func) {
590 ir_node *new_op = NULL;
591 dbg_info *dbg = get_irn_dbg_info(node);
592 ir_graph *irg = env->irg;
593 ir_node *block = transform_node(env, get_nodes_block(node));
594 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
595 ir_node *nomem = new_NoMem();
598 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
599 ir_node *new_op1 = transform_node(env, op1);
600 ir_node *new_op2 = transform_node(env, op2);
603 assert(! mode_is_float(get_irn_mode(node))
604 && "Shift/Rotate with float not supported");
606 /* Check if immediate optimization is on and */
607 /* if it's an operation with immediate. */
608 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
609 expr_op = get_expr_op(new_op1, new_op2);
611 assert((expr_op || imm_op) && "invalid operands");
614 /* We have two consts here: not yet supported */
618 /* Limit imm_op within range imm8 */
620 tv = get_ia32_Immop_tarval(imm_op);
623 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
624 set_ia32_Immop_tarval(imm_op, tv);
631 /* integer operations */
633 /* This is shift/rot with const */
634 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
636 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
637 copy_ia32_Immop_attr(new_op, imm_op);
639 /* This is a normal shift/rot */
640 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
641 new_op = func(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
645 set_ia32_am_support(new_op, ia32_am_Dest);
647 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
649 set_ia32_emit_cl(new_op);
656 * Construct a standard unary operation, set AM and immediate if required.
658 * @param env The transformation environment
659 * @param op The operand
660 * @param func The node constructor function
661 * @return The constructed ia32 node.
663 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *node, ir_node *op,
664 construct_unop_func *func) {
665 ir_node *new_node = NULL;
666 ir_graph *irg = env->irg;
667 dbg_info *dbg = get_irn_dbg_info(node);
668 ir_node *block = transform_node(env, get_nodes_block(node));
669 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
670 ir_node *nomem = new_NoMem();
671 ir_node *new_op = transform_node(env, op);
672 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
674 new_node = func(dbg, irg, block, noreg, noreg, new_op, nomem);
675 DB((mod, LEVEL_1, "INT unop ..."));
676 set_ia32_am_support(new_node, ia32_am_Dest);
678 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
685 * Creates an ia32 Add.
687 * @param env The transformation environment
688 * @return the created ia32 Add node
690 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) {
691 ir_node *new_op = NULL;
692 ir_graph *irg = env->irg;
693 dbg_info *dbg = get_irn_dbg_info(node);
694 ir_mode *mode = get_irn_mode(node);
695 ir_node *block = transform_node(env, get_nodes_block(node));
696 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
697 ir_node *nomem = new_NoMem();
698 ir_node *expr_op, *imm_op;
699 ir_node *op1 = get_Add_left(node);
700 ir_node *op2 = get_Add_right(node);
701 ir_node *new_op1 = transform_node(env, op1);
702 ir_node *new_op2 = transform_node(env, op2);
704 /* Check if immediate optimization is on and */
705 /* if it's an operation with immediate. */
706 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
707 expr_op = get_expr_op(new_op1, new_op2);
709 assert((expr_op || imm_op) && "invalid operands");
711 if (mode_is_float(mode)) {
713 if (USE_SSE2(env->cg))
714 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xAdd);
716 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfadd);
721 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
722 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
724 /* No expr_op means, that we have two const - one symconst and */
725 /* one tarval or another symconst - because this case is not */
726 /* covered by constant folding */
727 /* We need to check for: */
728 /* 1) symconst + const -> becomes a LEA */
729 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
730 /* linker doesn't support two symconsts */
732 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
733 /* this is the 2nd case */
734 new_op = new_rd_ia32_Lea(dbg, irg, block, new_op1, noreg);
735 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
736 set_ia32_am_flavour(new_op, ia32_am_OB);
737 set_ia32_am_support(new_op, ia32_am_Source);
738 set_ia32_op_type(new_op, ia32_AddrModeS);
740 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
741 } else if (tp1 == ia32_ImmSymConst) {
742 tarval *tv = get_ia32_Immop_tarval(new_op2);
743 long offs = get_tarval_long(tv);
745 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
746 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
748 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
749 add_ia32_am_offs_int(new_op, offs);
750 set_ia32_am_flavour(new_op, ia32_am_O);
751 set_ia32_am_support(new_op, ia32_am_Source);
752 set_ia32_op_type(new_op, ia32_AddrModeS);
753 } else if (tp2 == ia32_ImmSymConst) {
754 tarval *tv = get_ia32_Immop_tarval(new_op1);
755 long offs = get_tarval_long(tv);
757 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
758 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
760 add_ia32_am_offs_int(new_op, offs);
761 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
762 set_ia32_am_flavour(new_op, ia32_am_O);
763 set_ia32_am_support(new_op, ia32_am_Source);
764 set_ia32_op_type(new_op, ia32_AddrModeS);
766 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
767 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
768 tarval *restv = tarval_add(tv1, tv2);
770 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
772 new_op = new_rd_ia32_Const(dbg, irg, block);
773 set_ia32_Const_tarval(new_op, restv);
774 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
777 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
780 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
781 tarval_classification_t class_tv, class_negtv;
782 tarval *tv = get_ia32_Immop_tarval(imm_op);
784 /* optimize tarvals */
785 class_tv = classify_tarval(tv);
786 class_negtv = classify_tarval(tarval_neg(tv));
788 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
789 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
790 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
791 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
793 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
794 DB((env->mod, LEVEL_2, "Add(-1) to Dec ... "));
795 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
796 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
802 /* This is a normal add */
803 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
806 set_ia32_am_support(new_op, ia32_am_Full);
807 set_ia32_commutative(new_op);
809 fold_immediate(env, new_op, 2, 3);
811 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
817 static ir_node *create_ia32_Mul(ia32_transform_env_t *env, ir_node *node) {
818 ir_graph *irg = env->irg;
819 dbg_info *dbg = get_irn_dbg_info(node);
820 ir_node *block = transform_node(env, get_nodes_block(node));
821 ir_node *op1 = get_Mul_left(node);
822 ir_node *op2 = get_Mul_right(node);
823 ir_node *new_op1 = transform_node(env, op1);
824 ir_node *new_op2 = transform_node(env, op2);
825 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
826 ir_node *proj_EAX, *proj_EDX, *res;
829 res = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
830 set_ia32_commutative(res);
831 set_ia32_am_support(res, ia32_am_Source);
833 /* imediates are not supported, so no fold_immediate */
834 proj_EAX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX);
835 proj_EDX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX);
839 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
847 * Creates an ia32 Mul.
849 * @param env The transformation environment
850 * @return the created ia32 Mul node
852 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) {
853 ir_node *op1 = get_Mul_left(node);
854 ir_node *op2 = get_Mul_right(node);
855 ir_mode *mode = get_irn_mode(node);
857 if (mode_is_float(mode)) {
859 if (USE_SSE2(env->cg))
860 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul);
862 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul);
865 // for the lower 32bit of the result it doesn't matter whether we use
866 // signed or unsigned multiplication so we use IMul as it has fewer
868 return gen_binop(env, node, op1, op2, new_rd_ia32_IMul);
872 * Creates an ia32 Mulh.
873 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
874 * this result while Mul returns the lower 32 bit.
876 * @param env The transformation environment
877 * @return the created ia32 Mulh node
879 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) {
880 ir_graph *irg = env->irg;
881 dbg_info *dbg = get_irn_dbg_info(node);
882 ir_node *block = transform_node(env, get_nodes_block(node));
883 ir_node *op1 = get_irn_n(node, 0);
884 ir_node *op2 = get_irn_n(node, 1);
885 ir_node *new_op1 = transform_node(env, op1);
886 ir_node *new_op2 = transform_node(env, op2);
887 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
888 ir_node *proj_EAX, *proj_EDX, *res;
889 ir_mode *mode = get_irn_mode(node);
892 assert(!mode_is_float(mode) && "Mulh with float not supported");
893 if(mode_is_signed(mode)) {
894 res = new_rd_ia32_IMul1OP(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
896 res = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
899 set_ia32_commutative(res);
900 set_ia32_am_support(res, ia32_am_Source);
902 set_ia32_am_support(res, ia32_am_Source);
904 proj_EAX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX);
905 proj_EDX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX);
909 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
917 * Creates an ia32 And.
919 * @param env The transformation environment
920 * @return The created ia32 And node
922 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *node) {
923 ir_node *op1 = get_And_left(node);
924 ir_node *op2 = get_And_right(node);
926 assert (! mode_is_float(get_irn_mode(node)));
927 return gen_binop(env, node, op1, op2, new_rd_ia32_And);
933 * Creates an ia32 Or.
935 * @param env The transformation environment
936 * @return The created ia32 Or node
938 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *node) {
939 ir_node *op1 = get_Or_left(node);
940 ir_node *op2 = get_Or_right(node);
942 assert (! mode_is_float(get_irn_mode(node)));
943 return gen_binop(env, node, op1, op2, new_rd_ia32_Or);
949 * Creates an ia32 Eor.
951 * @param env The transformation environment
952 * @return The created ia32 Eor node
954 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *node) {
955 ir_node *op1 = get_Eor_left(node);
956 ir_node *op2 = get_Eor_right(node);
957 ir_mode *mode = get_irn_mode(node);
959 assert(! mode_is_float(mode));
960 return gen_binop(env, node, op1, op2, new_rd_ia32_Xor);
966 * Creates an ia32 Max.
968 * @param env The transformation environment
969 * @return the created ia32 Max node
971 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *node) {
972 ir_graph *irg = env->irg;
974 ir_mode *mode = get_irn_mode(node);
975 dbg_info *dbg = get_irn_dbg_info(node);
976 ir_node *block = transform_node(env, get_nodes_block(node));
977 ir_node *op1 = get_irn_n(node, 0);
978 ir_node *op2 = get_irn_n(node, 1);
979 ir_node *new_op1 = transform_node(env, op1);
980 ir_node *new_op2 = transform_node(env, op2);
981 ir_mode *op_mode = get_irn_mode(op1);
983 assert(get_mode_size_bits(mode) == 32);
985 if (mode_is_float(mode)) {
987 if (USE_SSE2(env->cg))
988 new_op = gen_binop_float(env, node, new_op1, new_op2, new_rd_ia32_xMax);
994 long pnc = pn_Cmp_Gt;
995 if(!mode_is_signed(op_mode)) {
996 pnc |= ia32_pn_Cmp_Unsigned;
998 new_op = new_rd_ia32_CmpCMov(dbg, irg, block, new_op1, new_op2, new_op1, new_op2);
999 set_ia32_pncode(new_op, pnc);
1000 set_ia32_am_support(new_op, ia32_am_None);
1002 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1008 * Creates an ia32 Min.
1010 * @param env The transformation environment
1011 * @return the created ia32 Min node
1013 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *node) {
1014 ir_graph *irg = env->irg;
1016 ir_mode *mode = get_irn_mode(node);
1017 dbg_info *dbg = get_irn_dbg_info(node);
1018 ir_node *block = transform_node(env, get_nodes_block(node));
1019 ir_node *op1 = get_irn_n(node, 0);
1020 ir_node *op2 = get_irn_n(node, 1);
1021 ir_node *new_op1 = transform_node(env, op1);
1022 ir_node *new_op2 = transform_node(env, op2);
1023 ir_mode *op_mode = get_irn_mode(op1);
1025 assert(get_mode_size_bits(mode) == 32);
1027 if (mode_is_float(mode)) {
1029 if (USE_SSE2(env->cg))
1030 new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMin);
1036 long pnc = pn_Cmp_Lt;
1037 if(!mode_is_signed(op_mode)) {
1038 pnc |= ia32_pn_Cmp_Unsigned;
1040 new_op = new_rd_ia32_CmpCMov(dbg, irg, block, new_op1, new_op2, new_op1, new_op2);
1041 set_ia32_pncode(new_op, pnc);
1042 set_ia32_am_support(new_op, ia32_am_None);
1044 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1051 * Creates an ia32 Sub.
1053 * @param env The transformation environment
1054 * @return The created ia32 Sub node
1056 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) {
1057 ir_node *new_op = NULL;
1058 ir_graph *irg = env->irg;
1059 dbg_info *dbg = get_irn_dbg_info(node);
1060 ir_mode *mode = get_irn_mode(node);
1061 ir_node *block = transform_node(env, get_nodes_block(node));
1062 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1063 ir_node *nomem = new_NoMem();
1064 ir_node *op1 = get_Sub_left(node);
1065 ir_node *op2 = get_Sub_right(node);
1066 ir_node *new_op1 = transform_node(env, op1);
1067 ir_node *new_op2 = transform_node(env, op2);
1068 ir_node *expr_op, *imm_op;
1070 /* Check if immediate optimization is on and */
1071 /* if it's an operation with immediate. */
1072 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1073 expr_op = get_expr_op(new_op1, new_op2);
1075 assert((expr_op || imm_op) && "invalid operands");
1077 if (mode_is_float(mode)) {
1079 if (USE_SSE2(env->cg))
1080 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xSub);
1082 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfsub);
1087 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1088 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1090 /* No expr_op means, that we have two const - one symconst and */
1091 /* one tarval or another symconst - because this case is not */
1092 /* covered by constant folding */
1093 /* We need to check for: */
1094 /* 1) symconst - const -> becomes a LEA */
1095 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1096 /* linker doesn't support two symconsts */
1097 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1098 /* this is the 2nd case */
1099 new_op = new_rd_ia32_Lea(dbg, irg, block, new_op1, noreg);
1100 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1101 set_ia32_am_sc_sign(new_op);
1102 set_ia32_am_flavour(new_op, ia32_am_OB);
1104 DBG_OPT_LEA3(op1, op2, node, new_op);
1105 } else if (tp1 == ia32_ImmSymConst) {
1106 tarval *tv = get_ia32_Immop_tarval(new_op2);
1107 long offs = get_tarval_long(tv);
1109 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
1110 DBG_OPT_LEA3(op1, op2, node, new_op);
1112 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1113 add_ia32_am_offs_int(new_op, -offs);
1114 set_ia32_am_flavour(new_op, ia32_am_O);
1115 set_ia32_am_support(new_op, ia32_am_Source);
1116 set_ia32_op_type(new_op, ia32_AddrModeS);
1117 } else if (tp2 == ia32_ImmSymConst) {
1118 tarval *tv = get_ia32_Immop_tarval(new_op1);
1119 long offs = get_tarval_long(tv);
1121 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
1122 DBG_OPT_LEA3(op1, op2, node, new_op);
1124 add_ia32_am_offs_int(new_op, offs);
1125 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1126 set_ia32_am_sc_sign(new_op);
1127 set_ia32_am_flavour(new_op, ia32_am_O);
1128 set_ia32_am_support(new_op, ia32_am_Source);
1129 set_ia32_op_type(new_op, ia32_AddrModeS);
1131 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1132 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1133 tarval *restv = tarval_sub(tv1, tv2);
1135 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1137 new_op = new_rd_ia32_Const(dbg, irg, block);
1138 set_ia32_Const_tarval(new_op, restv);
1139 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1142 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1144 } else if (imm_op) {
1145 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1146 tarval_classification_t class_tv, class_negtv;
1147 tarval *tv = get_ia32_Immop_tarval(imm_op);
1149 /* optimize tarvals */
1150 class_tv = classify_tarval(tv);
1151 class_negtv = classify_tarval(tarval_neg(tv));
1153 if (class_tv == TV_CLASSIFY_ONE) {
1154 DB((env->mod, LEVEL_2, "Sub(1) to Dec ... "));
1155 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
1156 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1158 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1159 DB((env->mod, LEVEL_2, "Sub(-1) to Inc ... "));
1160 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
1161 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1167 /* This is a normal sub */
1168 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1170 /* set AM support */
1171 set_ia32_am_support(new_op, ia32_am_Full);
1173 fold_immediate(env, new_op, 2, 3);
1175 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1183 * Generates an ia32 DivMod with additional infrastructure for the
1184 * register allocator if needed.
1186 * @param env The transformation environment
1187 * @param dividend -no comment- :)
1188 * @param divisor -no comment- :)
1189 * @param dm_flav flavour_Div/Mod/DivMod
1190 * @return The created ia32 DivMod node
1192 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *node,
1193 ir_node *dividend, ir_node *divisor,
1194 ia32_op_flavour_t dm_flav) {
1195 ir_graph *irg = env->irg;
1196 dbg_info *dbg = get_irn_dbg_info(node);
1197 ir_mode *mode = get_irn_mode(node);
1198 ir_node *block = transform_node(env, get_nodes_block(node));
1199 ir_node *res, *proj_div, *proj_mod;
1200 ir_node *edx_node, *cltd;
1201 ir_node *in_keep[1];
1202 ir_node *mem, *new_mem;
1203 ir_node *projs[pn_DivMod_max];
1204 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1205 ir_node *new_dividend = transform_node(env, dividend);
1206 ir_node *new_divisor = transform_node(env, divisor);
1208 ia32_collect_Projs(node, projs, pn_DivMod_max);
1212 mem = get_Div_mem(node);
1213 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Div_res));
1216 mem = get_Mod_mem(node);
1217 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Mod_res));
1219 case flavour_DivMod:
1220 mem = get_DivMod_mem(node);
1221 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1222 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1223 mode = proj_div ? get_irn_mode(proj_div) : get_irn_mode(proj_mod);
1228 new_mem = transform_node(env, mem);
1230 if (mode_is_signed(mode)) {
1231 /* in signed mode, we need to sign extend the dividend */
1232 cltd = new_rd_ia32_Cltd(dbg, irg, block, new_dividend);
1233 new_dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1234 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1236 edx_node = new_rd_ia32_Const(dbg, irg, block);
1237 add_irn_dep(edx_node, be_abi_get_start_barrier(env->cg->birg->abi));
1238 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1241 if(mode_is_signed(mode)) {
1242 res = new_rd_ia32_IDiv(dbg, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1244 res = new_rd_ia32_Div(dbg, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1247 /* Matze: code can't handle this at the moment... */
1249 /* set AM support */
1250 set_ia32_am_support(res, ia32_am_Source);
1253 set_ia32_n_res(res, 2);
1255 /* Only one proj is used -> We must add a second proj and */
1256 /* connect this one to a Keep node to eat up the second */
1257 /* destroyed register. */
1258 /* We also renumber the Firm projs into ia32 projs. */
1260 switch (get_irn_opcode(node)) {
1262 /* add Proj-Keep for mod res */
1263 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1264 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1267 /* add Proj-Keep for div res */
1268 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1269 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1272 /* check, which Proj-Keep, we need to add */
1273 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1274 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1276 if (proj_div && proj_mod) {
1277 /* nothing to be done */
1279 else if (! proj_div && ! proj_mod) {
1280 assert(0 && "Missing DivMod result proj");
1282 else if (! proj_div) {
1283 /* We have only mod result: add div res Proj-Keep */
1284 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1285 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1288 /* We have only div result: add mod res Proj-Keep */
1289 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1290 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1294 assert(0 && "Div, Mod, or DivMod expected.");
1298 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1305 * Wrapper for generate_DivMod. Sets flavour_Mod.
1307 * @param env The transformation environment
1309 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *node) {
1310 return generate_DivMod(env, node, get_Mod_left(node),
1311 get_Mod_right(node), flavour_Mod);
1315 * Wrapper for generate_DivMod. Sets flavour_Div.
1317 * @param env The transformation environment
1319 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *node) {
1320 return generate_DivMod(env, node, get_Div_left(node),
1321 get_Div_right(node), flavour_Div);
1325 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1327 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *node) {
1328 return generate_DivMod(env, node, get_DivMod_left(node),
1329 get_DivMod_right(node), flavour_DivMod);
1335 * Creates an ia32 floating Div.
1337 * @param env The transformation environment
1338 * @return The created ia32 xDiv node
1340 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *node) {
1341 ir_graph *irg = env->irg;
1342 dbg_info *dbg = get_irn_dbg_info(node);
1343 ir_node *block = transform_node(env, get_nodes_block(node));
1344 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1346 ir_node *nomem = new_rd_NoMem(env->irg);
1347 ir_node *op1 = get_Quot_left(node);
1348 ir_node *op2 = get_Quot_right(node);
1349 ir_node *new_op1 = transform_node(env, op1);
1350 ir_node *new_op2 = transform_node(env, op2);
1353 if (USE_SSE2(env->cg)) {
1354 ir_mode *mode = get_irn_mode(op1);
1355 if (is_ia32_xConst(new_op2)) {
1356 new_op = new_rd_ia32_xDiv(dbg, irg, block, noreg, noreg, new_op1, noreg, nomem);
1357 set_ia32_am_support(new_op, ia32_am_None);
1358 copy_ia32_Immop_attr(new_op, new_op2);
1360 new_op = new_rd_ia32_xDiv(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1361 // Matze: disabled for now, spillslot coalescer fails
1362 //set_ia32_am_support(new_op, ia32_am_Source);
1364 set_ia32_ls_mode(new_op, mode);
1366 new_op = new_rd_ia32_vfdiv(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1367 // Matze: disabled for now (spillslot coalescer fails)
1368 //set_ia32_am_support(new_op, ia32_am_Source);
1370 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1376 * Creates an ia32 Shl.
1378 * @param env The transformation environment
1379 * @return The created ia32 Shl node
1381 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *node) {
1382 return gen_shift_binop(env, node, get_Shl_left(node), get_Shl_right(node),
1389 * Creates an ia32 Shr.
1391 * @param env The transformation environment
1392 * @return The created ia32 Shr node
1394 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *node) {
1395 return gen_shift_binop(env, node, get_Shr_left(node),
1396 get_Shr_right(node), new_rd_ia32_Shr);
1402 * Creates an ia32 Sar.
1404 * @param env The transformation environment
1405 * @return The created ia32 Shrs node
1407 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) {
1408 return gen_shift_binop(env, node, get_Shrs_left(node),
1409 get_Shrs_right(node), new_rd_ia32_Sar);
1415 * Creates an ia32 RotL.
1417 * @param env The transformation environment
1418 * @param op1 The first operator
1419 * @param op2 The second operator
1420 * @return The created ia32 RotL node
1422 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node,
1423 ir_node *op1, ir_node *op2) {
1424 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Rol);
1430 * Creates an ia32 RotR.
1431 * NOTE: There is no RotR with immediate because this would always be a RotL
1432 * "imm-mode_size_bits" which can be pre-calculated.
1434 * @param env The transformation environment
1435 * @param op1 The first operator
1436 * @param op2 The second operator
1437 * @return The created ia32 RotR node
1439 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1,
1441 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Ror);
1447 * Creates an ia32 RotR or RotL (depending on the found pattern).
1449 * @param env The transformation environment
1450 * @return The created ia32 RotL or RotR node
1452 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) {
1453 ir_node *rotate = NULL;
1454 ir_node *op1 = get_Rot_left(node);
1455 ir_node *op2 = get_Rot_right(node);
1457 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1458 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1459 that means we can create a RotR instead of an Add and a RotL */
1461 if (get_irn_op(op2) == op_Add) {
1463 ir_node *left = get_Add_left(add);
1464 ir_node *right = get_Add_right(add);
1465 if (is_Const(right)) {
1466 tarval *tv = get_Const_tarval(right);
1467 ir_mode *mode = get_irn_mode(node);
1468 long bits = get_mode_size_bits(mode);
1470 if (get_irn_op(left) == op_Minus &&
1471 tarval_is_long(tv) &&
1472 get_tarval_long(tv) == bits)
1474 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1475 rotate = gen_RotR(env, node, op1, get_Minus_op(left));
1480 if (rotate == NULL) {
1481 rotate = gen_RotL(env, node, op1, op2);
1490 * Transforms a Minus node.
1492 * @param env The transformation environment
1493 * @param op The Minus operand
1494 * @return The created ia32 Minus node
1496 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *node, ir_node *op) {
1499 ir_graph *irg = env->irg;
1500 dbg_info *dbg = get_irn_dbg_info(node);
1501 ir_node *block = transform_node(env, get_nodes_block(node));
1502 ir_mode *mode = get_irn_mode(node);
1505 if (mode_is_float(mode)) {
1506 ir_node *new_op = transform_node(env, op);
1508 if (USE_SSE2(env->cg)) {
1509 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1510 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1511 ir_node *nomem = new_rd_NoMem(irg);
1513 res = new_rd_ia32_xXor(dbg, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1515 size = get_mode_size_bits(mode);
1516 name = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1518 set_ia32_am_sc(res, name);
1519 set_ia32_op_type(res, ia32_AddrModeS);
1520 set_ia32_ls_mode(res, mode);
1522 res = new_rd_ia32_vfchs(dbg, irg, block, new_op);
1525 res = gen_unop(env, node, op, new_rd_ia32_Neg);
1528 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1534 * Transforms a Minus node.
1536 * @param env The transformation environment
1537 * @return The created ia32 Minus node
1539 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *node) {
1540 return gen_Minus_ex(env, node, get_Minus_op(node));
1545 * Transforms a Not node.
1547 * @param env The transformation environment
1548 * @return The created ia32 Not node
1550 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *node) {
1551 ir_mode *mode = get_irn_mode(node);
1552 ir_node *op = get_Not_op(node);
1554 assert (! mode_is_float(mode));
1555 return gen_unop(env, node, op, new_rd_ia32_Not);
1561 * Transforms an Abs node.
1563 * @param env The transformation environment
1564 * @return The created ia32 Abs node
1566 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *node) {
1567 ir_node *res, *p_eax, *p_edx;
1568 ir_graph *irg = env->irg;
1569 dbg_info *dbg = get_irn_dbg_info(node);
1570 ir_node *block = transform_node(env, get_nodes_block(node));
1571 ir_mode *mode = get_irn_mode(node);
1572 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1573 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1574 ir_node *nomem = new_NoMem();
1575 ir_node *op = get_Abs_op(node);
1576 ir_node *new_op = transform_node(env, op);
1580 if (mode_is_float(mode)) {
1582 if (USE_SSE2(env->cg)) {
1583 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1585 size = get_mode_size_bits(mode);
1586 name = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1588 set_ia32_am_sc(res, name);
1590 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1592 set_ia32_op_type(res, ia32_AddrModeS);
1593 set_ia32_ls_mode(res, mode);
1596 res = new_rd_ia32_vfabs(dbg, irg, block, new_op);
1597 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1601 res = new_rd_ia32_Cltd(dbg, irg, block, new_op);
1602 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1604 p_eax = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX);
1605 p_edx = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX);
1607 res = new_rd_ia32_Xor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1608 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1610 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1611 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1620 * Transforms a Load.
1622 * @param env The transformation environment
1623 * @return the created ia32 Load node
1625 static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) {
1626 ir_graph *irg = env->irg;
1627 dbg_info *dbg = get_irn_dbg_info(node);
1628 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1629 ir_mode *mode = get_Load_mode(node);
1630 ir_node *block = transform_node(env, get_nodes_block(node));
1631 ir_node *ptr = get_Load_ptr(node);
1632 ir_node *new_ptr = transform_node(env, ptr);
1633 ir_node *lptr = new_ptr;
1634 ir_node *mem = get_Load_mem(node);
1635 ir_node *new_mem = transform_node(env, mem);
1638 ia32_am_flavour_t am_flav = ia32_am_B;
1639 ir_node *projs[pn_Load_max];
1641 ia32_collect_Projs(node, projs, pn_Load_max);
1644 check for special case: the loaded value might not be used (optimized, volatile, ...)
1645 we add a Proj + Keep for volatile loads and ignore all other cases
1647 if (! be_get_Proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1648 /* add a result proj and a Keep to produce a pseudo use */
1649 ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res);
1650 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), irg, block, 1, &proj);
1653 /* address might be a constant (symconst or absolute address) */
1654 if (is_ia32_Const(new_ptr)) {
1659 if (mode_is_float(mode)) {
1661 if (USE_SSE2(env->cg)) {
1662 new_op = new_rd_ia32_xLoad(dbg, irg, block, lptr, noreg, new_mem);
1664 new_op = new_rd_ia32_vfld(dbg, irg, block, lptr, noreg, new_mem);
1667 new_op = new_rd_ia32_Load(dbg, irg, block, lptr, noreg, new_mem);
1670 /* base is a constant address */
1672 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1673 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1674 am_flav = ia32_am_N;
1676 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1677 long offs = get_tarval_long(tv);
1679 add_ia32_am_offs_int(new_op, offs);
1680 am_flav = ia32_am_O;
1684 set_ia32_am_support(new_op, ia32_am_Source);
1685 set_ia32_op_type(new_op, ia32_AddrModeS);
1686 set_ia32_am_flavour(new_op, am_flav);
1687 set_ia32_ls_mode(new_op, mode);
1689 /* make sure we are scheduled behind the intial IncSP/Barrier
1690 * to avoid spills being placed before it
1692 if(block == get_irg_start_block(irg)) {
1693 add_irn_dep(new_op, get_irg_frame(irg));
1696 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1704 * Transforms a Store.
1706 * @param env The transformation environment
1707 * @return the created ia32 Store node
1709 static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) {
1710 ir_graph *irg = env->irg;
1711 dbg_info *dbg = get_irn_dbg_info(node);
1712 ir_node *block = transform_node(env, get_nodes_block(node));
1713 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1714 ir_node *ptr = get_Store_ptr(node);
1715 ir_node *new_ptr = transform_node(env, ptr);
1716 ir_node *sptr = new_ptr;
1717 ir_node *val = get_Store_value(node);
1718 ir_node *new_val = transform_node(env, val);
1719 ir_node *mem = get_Store_mem(node);
1720 ir_node *new_mem = transform_node(env, mem);
1721 ir_mode *mode = get_irn_mode(val);
1722 ir_node *sval = new_val;
1725 ia32_am_flavour_t am_flav = ia32_am_B;
1727 if (is_ia32_Const(new_val)) {
1728 assert(!mode_is_float(mode));
1732 /* address might be a constant (symconst or absolute address) */
1733 if (is_ia32_Const(new_ptr)) {
1738 if (mode_is_float(mode)) {
1740 if (USE_SSE2(env->cg)) {
1741 new_op = new_rd_ia32_xStore(dbg, irg, block, sptr, noreg, sval, new_mem);
1743 new_op = new_rd_ia32_vfst(dbg, irg, block, sptr, noreg, sval, new_mem);
1745 } else if (get_mode_size_bits(mode) == 8) {
1746 new_op = new_rd_ia32_Store8Bit(dbg, irg, block, sptr, noreg, sval, new_mem);
1748 new_op = new_rd_ia32_Store(dbg, irg, block, sptr, noreg, sval, new_mem);
1751 /* stored const is an immediate value */
1752 if (is_ia32_Const(new_val)) {
1753 assert(!mode_is_float(mode));
1754 copy_ia32_Immop_attr(new_op, new_val);
1757 /* base is an constant address */
1759 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1760 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1761 am_flav = ia32_am_N;
1763 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1764 long offs = get_tarval_long(tv);
1766 add_ia32_am_offs_int(new_op, offs);
1767 am_flav = ia32_am_O;
1771 set_ia32_am_support(new_op, ia32_am_Dest);
1772 set_ia32_op_type(new_op, ia32_AddrModeD);
1773 set_ia32_am_flavour(new_op, am_flav);
1774 set_ia32_ls_mode(new_op, mode);
1776 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1784 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1786 * @param env The transformation environment
1787 * @return The transformed node.
1789 static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) {
1790 ir_graph *irg = env->irg;
1791 dbg_info *dbg = get_irn_dbg_info(node);
1792 ir_node *block = transform_node(env, get_nodes_block(node));
1793 ir_node *sel = get_Cond_selector(node);
1794 ir_mode *sel_mode = get_irn_mode(sel);
1795 ir_node *res = NULL;
1796 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1797 ir_node *cnst, *expr;
1799 if (is_Proj(sel) && sel_mode == mode_b) {
1800 ir_node *nomem = new_NoMem();
1801 ir_node *pred = get_Proj_pred(sel);
1802 ir_node *cmp_a = get_Cmp_left(pred);
1803 ir_node *new_cmp_a = transform_node(env, cmp_a);
1804 ir_node *cmp_b = get_Cmp_right(pred);
1805 ir_node *new_cmp_b = transform_node(env, cmp_b);
1806 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1808 int pnc = get_Proj_proj(sel);
1809 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1810 pnc |= ia32_pn_Cmp_Unsigned;
1813 /* check if we can use a CondJmp with immediate */
1814 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1815 expr = get_expr_op(new_cmp_a, new_cmp_b);
1817 if (cnst != NULL && expr != NULL) {
1818 /* immop has to be the right operand, we might need to flip pnc */
1819 if(cnst != new_cmp_b) {
1820 pnc = get_inversed_pnc(pnc);
1823 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1824 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1825 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1827 /* a Cmp A =/!= 0 */
1828 ir_node *op1 = expr;
1829 ir_node *op2 = expr;
1832 /* check, if expr is an only once used And operation */
1833 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1834 op1 = get_irn_n(expr, 2);
1835 op2 = get_irn_n(expr, 3);
1837 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1839 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1840 set_ia32_pncode(res, pnc);
1843 copy_ia32_Immop_attr(res, expr);
1846 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1851 if (mode_is_float(cmp_mode)) {
1853 if (USE_SSE2(env->cg)) {
1854 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1855 set_ia32_ls_mode(res, cmp_mode);
1861 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1863 copy_ia32_Immop_attr(res, cnst);
1866 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1868 if (mode_is_float(cmp_mode)) {
1870 if (USE_SSE2(env->cg)) {
1871 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1872 set_ia32_ls_mode(res, cmp_mode);
1875 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1876 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1877 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1881 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1882 set_ia32_commutative(res);
1886 set_ia32_pncode(res, pnc);
1887 // Matze: disabled for now, because the default collect_spills_walker
1888 // is not able to detect the mode of the spilled value
1889 // moreover, the lea optimize phase freely exchanges left/right
1890 // without updating the pnc
1891 //set_ia32_am_support(res, ia32_am_Source);
1894 /* determine the smallest switch case value */
1895 int switch_min = INT_MAX;
1896 const ir_edge_t *edge;
1897 ir_node *new_sel = transform_node(env, sel);
1899 foreach_out_edge(node, edge) {
1900 int pn = get_Proj_proj(get_edge_src_irn(edge));
1901 switch_min = pn < switch_min ? pn : switch_min;
1905 /* if smallest switch case is not 0 we need an additional sub */
1906 res = new_rd_ia32_Lea(dbg, irg, block, new_sel, noreg);
1907 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1908 add_ia32_am_offs_int(res, -switch_min);
1909 set_ia32_am_flavour(res, ia32_am_OB);
1910 set_ia32_am_support(res, ia32_am_Source);
1911 set_ia32_op_type(res, ia32_AddrModeS);
1914 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : new_sel, mode_T);
1915 set_ia32_pncode(res, get_Cond_defaultProj(node));
1918 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1925 * Transforms a CopyB node.
1927 * @param env The transformation environment
1928 * @return The transformed node.
1930 static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) {
1931 ir_node *res = NULL;
1932 ir_graph *irg = env->irg;
1933 dbg_info *dbg = get_irn_dbg_info(node);
1934 ir_node *block = transform_node(env, get_nodes_block(node));
1935 ir_node *src = get_CopyB_src(node);
1936 ir_node *new_src = transform_node(env, src);
1937 ir_node *dst = get_CopyB_dst(node);
1938 ir_node *new_dst = transform_node(env, dst);
1939 ir_node *mem = get_CopyB_mem(node);
1940 ir_node *new_mem = transform_node(env, mem);
1941 int size = get_type_size_bytes(get_CopyB_type(node));
1942 ir_mode *dst_mode = get_irn_mode(dst);
1943 ir_mode *src_mode = get_irn_mode(src);
1947 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1948 /* then we need the size explicitly in ECX. */
1949 if (size >= 32 * 4) {
1950 rem = size & 0x3; /* size % 4 */
1953 res = new_rd_ia32_Const(dbg, irg, block);
1954 add_irn_dep(res, be_abi_get_start_barrier(env->cg->birg->abi));
1955 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1957 res = new_rd_ia32_CopyB(dbg, irg, block, new_dst, new_src, res, new_mem);
1958 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1960 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1961 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1962 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1963 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1964 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1967 res = new_rd_ia32_CopyB_i(dbg, irg, block, new_dst, new_src, new_mem);
1968 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1970 /* ok: now attach Proj's because movsd will destroy esi and edi */
1971 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1972 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1973 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1976 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1984 * Transforms a Mux node into CMov.
1986 * @param env The transformation environment
1987 * @return The transformed node.
1989 static ir_node *gen_Mux(ia32_transform_env_t *env, ir_node *node) {
1990 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1991 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1993 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1999 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
2000 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
2001 ir_node *psi_default);
2004 * Transforms a Psi node into CMov.
2006 * @param env The transformation environment
2007 * @return The transformed node.
2009 static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) {
2010 ia32_code_gen_t *cg = env->cg;
2011 ir_graph *irg = env->irg;
2012 dbg_info *dbg = get_irn_dbg_info(node);
2013 ir_mode *mode = get_irn_mode(node);
2014 ir_node *block = transform_node(env, get_nodes_block(node));
2015 ir_node *cmp_proj = get_Mux_sel(node);
2016 ir_node *psi_true = get_Psi_val(node, 0);
2017 ir_node *psi_default = get_Psi_default(node);
2018 ir_node *new_psi_true = transform_node(env, psi_true);
2019 ir_node *new_psi_default = transform_node(env, psi_default);
2020 ir_node *noreg = ia32_new_NoReg_gp(cg);
2021 ir_node *nomem = new_rd_NoMem(irg);
2022 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
2023 ir_node *new_cmp_a, *new_cmp_b;
2027 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
2029 cmp = get_Proj_pred(cmp_proj);
2030 cmp_a = get_Cmp_left(cmp);
2031 cmp_b = get_Cmp_right(cmp);
2032 cmp_mode = get_irn_mode(cmp_a);
2033 new_cmp_a = transform_node(env, cmp_a);
2034 new_cmp_b = transform_node(env, cmp_b);
2036 pnc = get_Proj_proj(cmp_proj);
2037 if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2038 pnc |= ia32_pn_Cmp_Unsigned;
2041 if (mode_is_float(mode)) {
2042 /* floating point psi */
2045 /* 1st case: compare operands are float too */
2047 /* psi(cmp(a, b), t, f) can be done as: */
2048 /* tmp = cmp a, b */
2049 /* tmp2 = t and tmp */
2050 /* tmp3 = f and not tmp */
2051 /* res = tmp2 or tmp3 */
2053 /* in case the compare operands are int, we move them into xmm register */
2054 if (! mode_is_float(get_irn_mode(cmp_a))) {
2055 new_cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_a, node, mode_E);
2056 new_cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_b, node, mode_E);
2058 pnc |= 8; /* transform integer compare to fp compare */
2061 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2062 set_ia32_pncode(new_op, pnc);
2063 set_ia32_am_support(new_op, ia32_am_Source);
2064 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2066 and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2067 set_ia32_am_support(and1, ia32_am_None);
2068 set_ia32_commutative(and1);
2069 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2071 and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2072 set_ia32_am_support(and2, ia32_am_None);
2073 set_ia32_commutative(and2);
2074 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2076 new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
2077 set_ia32_am_support(new_op, ia32_am_None);
2078 set_ia32_commutative(new_op);
2079 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2083 new_op = new_rd_ia32_vfCMov(dbg, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2084 set_ia32_pncode(new_op, pnc);
2085 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2090 construct_binop_func *set_func = NULL;
2091 cmov_func_t *cmov_func = NULL;
2093 if (mode_is_float(get_irn_mode(cmp_a))) {
2094 /* 1st case: compare operands are floats */
2099 set_func = new_rd_ia32_xCmpSet;
2100 cmov_func = new_rd_ia32_xCmpCMov;
2104 set_func = new_rd_ia32_vfCmpSet;
2105 cmov_func = new_rd_ia32_vfCmpCMov;
2108 pnc &= ~0x8; /* fp compare -> int compare */
2111 /* 2nd case: compare operand are integer too */
2112 set_func = new_rd_ia32_CmpSet;
2113 cmov_func = new_rd_ia32_CmpCMov;
2116 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2117 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2118 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2119 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2120 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, new_cmp_a);
2121 set_ia32_pncode(new_op, pnc);
2123 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2124 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2125 /* we invert condition and set default to 0 */
2126 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, new_cmp_a);
2127 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2130 /* otherwise: use CMOVcc */
2131 new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2132 set_ia32_pncode(new_op, pnc);
2135 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2138 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2139 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2140 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2141 set_ia32_pncode(new_op, pnc);
2142 set_ia32_am_support(new_op, ia32_am_Source);
2144 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2145 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2146 /* we invert condition and set default to 0 */
2147 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2148 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2149 set_ia32_am_support(new_op, ia32_am_Source);
2152 /* otherwise: use CMOVcc */
2153 new_op = cmov_func(dbg, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2154 set_ia32_pncode(new_op, pnc);
2155 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2165 * Following conversion rules apply:
2169 * 1) n bit -> m bit n > m (downscale)
2171 * 2) n bit -> m bit n == m (sign change)
2173 * 3) n bit -> m bit n < m (upscale)
2174 * a) source is signed: movsx
2175 * b) source is unsigned: and with lower bits sets
2179 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2183 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2187 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2188 * x87 is mode_E internally, conversions happen only at load and store
2189 * in non-strict semantic
2193 * Create a conversion from x87 state register to general purpose.
2195 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) {
2196 ia32_code_gen_t *cg = env->cg;
2197 ir_graph *irg = env->irg;
2198 dbg_info *dbg = get_irn_dbg_info(node);
2199 ir_node *block = transform_node(env, get_nodes_block(node));
2200 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2201 ir_node *op = get_Conv_op(node);
2202 ir_node *new_op = transform_node(env, op);
2203 ir_node *fist, *load;
2206 fist = new_rd_ia32_vfist(dbg, irg, block, get_irg_frame(irg), noreg, new_op, new_NoMem());
2208 set_ia32_use_frame(fist);
2209 set_ia32_am_support(fist, ia32_am_Dest);
2210 set_ia32_op_type(fist, ia32_AddrModeD);
2211 set_ia32_am_flavour(fist, ia32_am_B);
2212 set_ia32_ls_mode(fist, mode_Iu);
2213 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2216 load = new_rd_ia32_Load(dbg, irg, block, get_irg_frame(irg), noreg, fist);
2218 set_ia32_use_frame(load);
2219 set_ia32_am_support(load, ia32_am_Source);
2220 set_ia32_op_type(load, ia32_AddrModeS);
2221 set_ia32_am_flavour(load, ia32_am_B);
2222 set_ia32_ls_mode(load, mode_Iu);
2223 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2225 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2229 * Create a conversion from general purpose to x87 register
2231 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mode *src_mode) {
2232 ia32_code_gen_t *cg = env->cg;
2233 ir_graph *irg = env->irg;
2234 dbg_info *dbg = get_irn_dbg_info(node);
2235 ir_mode *mode = get_irn_mode(node);
2236 ir_node *block = transform_node(env, get_nodes_block(node));
2237 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2238 ir_node *nomem = new_NoMem();
2239 ir_node *op = get_Conv_op(node);
2240 ir_node *new_op = transform_node(env, op);
2241 ir_node *fild, *store;
2244 /* first convert to 32 bit if necessary */
2245 src_bits = get_mode_size_bits(src_mode);
2246 if (src_bits == 8) {
2247 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, new_op, nomem);
2248 set_ia32_am_support(new_op, ia32_am_Source);
2249 set_ia32_ls_mode(new_op, src_mode);
2250 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2251 } else if (src_bits < 32) {
2252 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, new_op, nomem);
2253 set_ia32_am_support(new_op, ia32_am_Source);
2254 set_ia32_ls_mode(new_op, src_mode);
2255 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2259 store = new_rd_ia32_Store(dbg, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2261 set_ia32_use_frame(store);
2262 set_ia32_am_support(store, ia32_am_Dest);
2263 set_ia32_op_type(store, ia32_AddrModeD);
2264 set_ia32_am_flavour(store, ia32_am_OB);
2265 set_ia32_ls_mode(store, mode_Iu);
2268 fild = new_rd_ia32_vfild(dbg, irg, block, get_irg_frame(irg), noreg, store);
2270 set_ia32_use_frame(fild);
2271 set_ia32_am_support(fild, ia32_am_Source);
2272 set_ia32_op_type(fild, ia32_AddrModeS);
2273 set_ia32_am_flavour(fild, ia32_am_OB);
2274 set_ia32_ls_mode(fild, mode);
2276 return new_r_Proj(irg, block, fild, mode_F, pn_ia32_vfild_res);
2280 * Transforms a Conv node.
2282 * @param env The transformation environment
2283 * @return The created ia32 Conv node
2285 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) {
2286 ir_graph *irg = env->irg;
2287 dbg_info *dbg = get_irn_dbg_info(node);
2288 ir_node *op = get_Conv_op(node);
2289 ir_mode *src_mode = get_irn_mode(op);
2290 ir_mode *tgt_mode = get_irn_mode(node);
2291 int src_bits = get_mode_size_bits(src_mode);
2292 int tgt_bits = get_mode_size_bits(tgt_mode);
2293 ir_node *block = transform_node(env, get_nodes_block(node));
2295 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2296 ir_node *nomem = new_rd_NoMem(irg);
2297 ir_node *new_op = transform_node(env, op);
2298 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
2300 if (src_mode == tgt_mode) {
2301 /* this should be optimized already, but who knows... */
2302 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2303 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
2307 if (mode_is_float(src_mode)) {
2308 /* we convert from float ... */
2309 if (mode_is_float(tgt_mode)) {
2311 if (USE_SSE2(env->cg)) {
2312 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
2313 res = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, new_op, nomem);
2314 set_ia32_ls_mode(res, tgt_mode);
2316 // Matze: TODO what about strict convs?
2317 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
2322 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
2323 if (USE_SSE2(env->cg)) {
2324 res = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, new_op, nomem);
2325 set_ia32_ls_mode(res, src_mode);
2327 return gen_x87_fp_to_gp(env, node);
2331 /* we convert from int ... */
2332 if (mode_is_float(tgt_mode)) {
2335 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
2336 if (USE_SSE2(env->cg)) {
2337 res = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, new_op, nomem);
2338 set_ia32_ls_mode(res, tgt_mode);
2339 if(src_bits == 32) {
2340 set_ia32_am_support(res, ia32_am_Source);
2343 return gen_x87_gp_to_fp(env, node, src_mode);
2347 ir_mode *smaller_mode;
2350 if (src_bits == tgt_bits) {
2351 DB((mod, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2355 if(src_bits < tgt_bits) {
2356 smaller_mode = src_mode;
2357 smaller_bits = src_bits;
2359 smaller_mode = tgt_mode;
2360 smaller_bits = tgt_bits;
2363 // The following is not correct, we can't change the mode,
2364 // maybe others are using the load too
2365 // better move this to a separate phase!
2368 if(is_Proj(new_op)) {
2369 /* load operations do already sign/zero extend, so we have
2370 * nothing left to do */
2371 ir_node *pred = get_Proj_pred(new_op);
2372 if(is_ia32_Load(pred)) {
2373 set_ia32_ls_mode(pred, smaller_mode);
2379 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2380 if (smaller_bits == 8) {
2381 res = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, new_op, nomem);
2382 set_ia32_ls_mode(res, smaller_mode);
2384 res = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, new_op, nomem);
2385 set_ia32_ls_mode(res, smaller_mode);
2387 set_ia32_am_support(res, ia32_am_Source);
2391 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2398 /********************************************
2401 * | |__ ___ _ __ ___ __| | ___ ___
2402 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2403 * | |_) | __/ | | | (_) | (_| | __/\__ \
2404 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2406 ********************************************/
2408 static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) {
2409 ir_node *new_op = NULL;
2410 ir_graph *irg = env->irg;
2411 dbg_info *dbg = get_irn_dbg_info(node);
2412 ir_node *block = transform_node(env, get_nodes_block(node));
2413 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2414 ir_node *nomem = new_rd_NoMem(env->irg);
2415 ir_node *ptr = get_irn_n(node, 0);
2416 ir_node *new_ptr = transform_node(env, ptr);
2417 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2418 ir_mode *load_mode = get_irn_mode(node);
2422 if (mode_is_float(load_mode)) {
2424 if (USE_SSE2(env->cg)) {
2425 new_op = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, nomem);
2426 pn_res = pn_ia32_xLoad_res;
2428 new_op = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, nomem);
2429 pn_res = pn_ia32_vfld_res;
2434 new_op = new_rd_ia32_Load(dbg, irg, block, new_ptr, noreg, nomem);
2435 proj_mode = mode_Iu;
2436 pn_res = pn_ia32_Load_res;
2439 set_ia32_frame_ent(new_op, ent);
2440 set_ia32_use_frame(new_op);
2442 set_ia32_am_support(new_op, ia32_am_Source);
2443 set_ia32_op_type(new_op, ia32_AddrModeS);
2444 set_ia32_am_flavour(new_op, ia32_am_B);
2445 set_ia32_ls_mode(new_op, load_mode);
2446 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2448 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2450 return new_rd_Proj(dbg, irg, block, new_op, proj_mode, pn_res);
2454 * Transforms a FrameAddr into an ia32 Add.
2456 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) {
2457 ir_graph *irg = env->irg;
2458 dbg_info *dbg = get_irn_dbg_info(node);
2459 ir_node *block = transform_node(env, get_nodes_block(node));
2460 ir_node *op = get_irn_n(node, 0);
2461 ir_node *new_op = transform_node(env, op);
2463 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2465 res = new_rd_ia32_Lea(dbg, irg, block, new_op, noreg);
2466 set_ia32_frame_ent(res, arch_get_frame_entity(env->cg->arch_env, node));
2467 set_ia32_am_support(res, ia32_am_Full);
2468 set_ia32_use_frame(res);
2469 set_ia32_am_flavour(res, ia32_am_OB);
2471 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2477 * Transforms a FrameLoad into an ia32 Load.
2479 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) {
2480 ir_node *new_op = NULL;
2481 ir_graph *irg = env->irg;
2482 dbg_info *dbg = get_irn_dbg_info(node);
2483 ir_node *block = transform_node(env, get_nodes_block(node));
2484 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2485 ir_node *mem = get_irn_n(node, 0);
2486 ir_node *ptr = get_irn_n(node, 1);
2487 ir_node *new_mem = transform_node(env, mem);
2488 ir_node *new_ptr = transform_node(env, ptr);
2489 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2490 ir_mode *mode = get_type_mode(get_entity_type(ent));
2491 ir_node *projs[pn_Load_max];
2493 ia32_collect_Projs(node, projs, pn_Load_max);
2495 if (mode_is_float(mode)) {
2497 if (USE_SSE2(env->cg)) {
2498 new_op = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, new_mem);
2501 new_op = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, new_mem);
2505 new_op = new_rd_ia32_Load(dbg, irg, block, new_ptr, noreg, new_mem);
2508 set_ia32_frame_ent(new_op, ent);
2509 set_ia32_use_frame(new_op);
2511 set_ia32_am_support(new_op, ia32_am_Source);
2512 set_ia32_op_type(new_op, ia32_AddrModeS);
2513 set_ia32_am_flavour(new_op, ia32_am_B);
2514 set_ia32_ls_mode(new_op, mode);
2516 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2523 * Transforms a FrameStore into an ia32 Store.
2525 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) {
2526 ir_node *new_op = NULL;
2527 ir_graph *irg = env->irg;
2528 dbg_info *dbg = get_irn_dbg_info(node);
2529 ir_node *block = transform_node(env, get_nodes_block(node));
2530 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2531 ir_node *mem = get_irn_n(node, 0);
2532 ir_node *ptr = get_irn_n(node, 1);
2533 ir_node *val = get_irn_n(node, 2);
2534 ir_node *new_mem = transform_node(env, mem);
2535 ir_node *new_ptr = transform_node(env, ptr);
2536 ir_node *new_val = transform_node(env, val);
2537 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2538 ir_mode *mode = get_irn_mode(val);
2540 if (mode_is_float(mode)) {
2542 if (USE_SSE2(env->cg)) {
2543 new_op = new_rd_ia32_xStore(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2546 new_op = new_rd_ia32_vfst(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2549 else if (get_mode_size_bits(mode) == 8) {
2550 new_op = new_rd_ia32_Store8Bit(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2553 new_op = new_rd_ia32_Store(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2556 set_ia32_frame_ent(new_op, ent);
2557 set_ia32_use_frame(new_op);
2559 set_ia32_am_support(new_op, ia32_am_Dest);
2560 set_ia32_op_type(new_op, ia32_AddrModeD);
2561 set_ia32_am_flavour(new_op, ia32_am_B);
2562 set_ia32_ls_mode(new_op, mode);
2564 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2570 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2572 static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
2573 ir_graph *irg = env->irg;
2576 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2577 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2578 ir_entity *ent = get_irg_entity(irg);
2579 ir_type *tp = get_entity_type(ent);
2582 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2583 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2585 int pn_ret_val, pn_ret_mem, arity, i;
2587 assert(ret_val != NULL);
2588 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env->cg)) {
2589 return duplicate_node(env, node);
2592 res_type = get_method_res_type(tp, 0);
2594 if (!is_Primitive_type(res_type)) {
2595 return duplicate_node(env, node);
2598 mode = get_type_mode(res_type);
2599 if (!mode_is_float(mode)) {
2600 return duplicate_node(env, node);
2603 assert(get_method_n_ress(tp) == 1);
2605 pn_ret_val = get_Proj_proj(ret_val);
2606 pn_ret_mem = get_Proj_proj(ret_mem);
2608 /* get the Barrier */
2609 barrier = get_Proj_pred(ret_val);
2611 /* get result input of the Barrier */
2612 ret_val = get_irn_n(barrier, pn_ret_val);
2613 new_ret_val = transform_node(env, ret_val);
2615 /* get memory input of the Barrier */
2616 ret_mem = get_irn_n(barrier, pn_ret_mem);
2617 new_ret_mem = transform_node(env, ret_mem);
2619 frame = get_irg_frame(irg);
2621 dbg = get_irn_dbg_info(barrier);
2622 block = transform_node(env, get_nodes_block(barrier));
2624 /* store xmm0 onto stack */
2625 sse_store = new_rd_ia32_xStoreSimple(dbg, irg, block, frame, new_ret_val, new_ret_mem);
2626 set_ia32_ls_mode(sse_store, mode);
2627 set_ia32_op_type(sse_store, ia32_AddrModeD);
2628 set_ia32_use_frame(sse_store);
2629 set_ia32_am_flavour(sse_store, ia32_am_B);
2630 set_ia32_am_support(sse_store, ia32_am_Dest);
2633 fld = new_rd_ia32_SetST0(dbg, irg, block, frame, sse_store);
2634 set_ia32_ls_mode(fld, mode);
2635 set_ia32_op_type(fld, ia32_AddrModeS);
2636 set_ia32_use_frame(fld);
2637 set_ia32_am_flavour(fld, ia32_am_B);
2638 set_ia32_am_support(fld, ia32_am_Source);
2640 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
2641 fld = new_r_Proj(irg, block, fld, mode_E, pn_ia32_SetST0_res);
2642 arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2644 /* create a new barrier */
2645 arity = get_irn_arity(barrier);
2646 in = alloca(arity * sizeof(in[0]));
2647 for(i = 0; i < arity; ++i) {
2649 if(i == pn_ret_val) {
2651 } else if(i == pn_ret_mem) {
2654 ir_node *in = get_irn_n(barrier, i);
2655 new_in = transform_node(env, in);
2660 new_barrier = new_ir_node(dbg, irg, block,
2661 get_irn_op(barrier), get_irn_mode(barrier),
2663 copy_node_attr(barrier, new_barrier);
2664 duplicate_deps(env, barrier, new_barrier);
2665 set_new_node(barrier, new_barrier);
2666 mark_irn_visited(barrier);
2668 /* transform normally */
2669 return duplicate_node(env, node);
2673 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2675 static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
2677 ir_graph *irg = env->irg;
2678 dbg_info *dbg = get_irn_dbg_info(node);
2679 ir_node *block = transform_node(env, get_nodes_block(node));
2680 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
2681 ir_node *new_sz = transform_node(env, sz);
2682 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
2683 ir_node *new_sp = transform_node(env, sp);
2684 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2685 ir_node *nomem = new_NoMem();
2687 /* ia32 stack grows in reverse direction, make a SubSP */
2688 new_op = new_rd_ia32_SubSP(dbg, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2689 set_ia32_am_support(new_op, ia32_am_Source);
2690 fold_immediate(env, new_op, 2, 3);
2692 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2698 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
2700 static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
2702 ir_graph *irg = env->irg;
2703 dbg_info *dbg = get_irn_dbg_info(node);
2704 ir_node *block = transform_node(env, get_nodes_block(node));
2705 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
2706 ir_node *new_sz = transform_node(env, sz);
2707 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
2708 ir_node *new_sp = transform_node(env, sp);
2709 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2710 ir_node *nomem = new_NoMem();
2712 /* ia32 stack grows in reverse direction, make an AddSP */
2713 new_op = new_rd_ia32_AddSP(dbg, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2714 set_ia32_am_support(new_op, ia32_am_Source);
2715 fold_immediate(env, new_op, 2, 3);
2717 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2723 * This function just sets the register for the Unknown node
2724 * as this is not done during register allocation because Unknown
2725 * is an "ignore" node.
2727 static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) {
2728 ir_mode *mode = get_irn_mode(node);
2730 if (mode_is_float(mode)) {
2731 if (USE_SSE2(env->cg))
2732 return ia32_new_Unknown_xmm(env->cg);
2734 return ia32_new_Unknown_vfp(env->cg);
2735 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
2736 return ia32_new_Unknown_gp(env->cg);
2738 assert(0 && "unsupported Unknown-Mode");
2745 * Change some phi modes
2747 static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
2748 ir_graph *irg = env->irg;
2749 dbg_info *dbg = get_irn_dbg_info(node);
2750 ir_mode *mode = get_irn_mode(node);
2751 ir_node *block = transform_node(env, get_nodes_block(node));
2755 if(mode_is_int(mode) || mode_is_reference(mode)) {
2756 // we shouldn't have any 64bit stuff around anymore
2757 assert(get_mode_size_bits(mode) <= 32);
2758 // all integer operations are on 32bit registers now
2760 } else if(mode_is_float(mode)) {
2761 assert(mode == mode_D || mode == mode_F);
2762 // all float operations are on mode_E registers
2766 /* phi nodes allow loops, so we use the old arguments for now
2767 * and fix this later */
2768 phi = new_ir_node(dbg, irg, block, op_Phi, mode, get_irn_arity(node),
2769 get_irn_in(node) + 1);
2770 copy_node_attr(node, phi);
2771 duplicate_deps(env, node, phi);
2773 set_new_node(node, phi);
2775 /* put the preds in the worklist */
2776 arity = get_irn_arity(node);
2777 for(i = 0; i < arity; ++i) {
2778 ir_node *pred = get_irn_n(node, i);
2779 pdeq_putr(env->worklist, pred);
2785 /**********************************************************************
2788 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2789 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2790 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2791 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2793 **********************************************************************/
2795 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2797 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2800 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2801 ir_node *val, ir_node *mem);
2804 * Transforms a lowered Load into a "real" one.
2806 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) {
2807 ir_graph *irg = env->irg;
2808 dbg_info *dbg = get_irn_dbg_info(node);
2809 ir_node *block = transform_node(env, get_nodes_block(node));
2810 ir_mode *mode = get_ia32_ls_mode(node);
2812 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2813 ir_node *ptr = get_irn_n(node, 0);
2814 ir_node *mem = get_irn_n(node, 1);
2815 ir_node *new_ptr = transform_node(env, ptr);
2816 ir_node *new_mem = transform_node(env, mem);
2819 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2820 lowering we have x87 nodes, so we need to enforce simulation.
2822 if (mode_is_float(mode)) {
2824 if (fp_unit == fp_x87)
2828 new_op = func(dbg, irg, block, new_ptr, noreg, new_mem);
2830 set_ia32_am_support(new_op, ia32_am_Source);
2831 set_ia32_op_type(new_op, ia32_AddrModeS);
2832 set_ia32_am_flavour(new_op, ia32_am_OB);
2833 set_ia32_am_offs_int(new_op, 0);
2834 set_ia32_am_scale(new_op, 1);
2835 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
2836 if(is_ia32_am_sc_sign(node))
2837 set_ia32_am_sc_sign(new_op);
2838 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
2839 if(is_ia32_use_frame(node)) {
2840 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2841 set_ia32_use_frame(new_op);
2844 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2850 * Transforms a lowered Store into a "real" one.
2852 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) {
2853 ir_graph *irg = env->irg;
2854 dbg_info *dbg = get_irn_dbg_info(node);
2855 ir_node *block = transform_node(env, get_nodes_block(node));
2856 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2857 ir_mode *mode = get_ia32_ls_mode(node);
2860 ia32_am_flavour_t am_flav = ia32_B;
2861 ir_node *ptr = get_irn_n(node, 0);
2862 ir_node *val = get_irn_n(node, 1);
2863 ir_node *mem = get_irn_n(node, 2);
2864 ir_node *new_ptr = transform_node(env, ptr);
2865 ir_node *new_val = transform_node(env, val);
2866 ir_node *new_mem = transform_node(env, mem);
2869 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2870 lowering we have x87 nodes, so we need to enforce simulation.
2872 if (mode_is_float(mode)) {
2874 if (fp_unit == fp_x87)
2878 new_op = func(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2880 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
2882 add_ia32_am_offs_int(new_op, am_offs);
2885 set_ia32_am_support(new_op, ia32_am_Dest);
2886 set_ia32_op_type(new_op, ia32_AddrModeD);
2887 set_ia32_am_flavour(new_op, am_flav);
2888 set_ia32_ls_mode(new_op, mode);
2889 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2890 set_ia32_use_frame(new_op);
2892 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2899 * Transforms an ia32_l_XXX into a "real" XXX node
2901 * @param env The transformation environment
2902 * @return the created ia32 XXX node
2904 #define GEN_LOWERED_OP(op) \
2905 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2906 ir_mode *mode = get_irn_mode(node); \
2907 if (mode_is_float(mode)) \
2909 return gen_binop(env, node, get_binop_left(node), \
2910 get_binop_right(node), new_rd_ia32_##op); \
2913 #define GEN_LOWERED_x87_OP(op) \
2914 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2916 FORCE_x87(env->cg); \
2917 new_op = gen_binop_float(env, node, get_binop_left(node), \
2918 get_binop_right(node), new_rd_ia32_##op); \
2922 #define GEN_LOWERED_UNOP(op) \
2923 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2924 return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \
2927 #define GEN_LOWERED_SHIFT_OP(op) \
2928 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2929 return gen_shift_binop(env, node, get_binop_left(node), \
2930 get_binop_right(node), new_rd_ia32_##op); \
2933 #define GEN_LOWERED_LOAD(op, fp_unit) \
2934 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2935 return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \
2938 #define GEN_LOWERED_STORE(op, fp_unit) \
2939 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2940 return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \
2947 GEN_LOWERED_OP(IMul)
2949 GEN_LOWERED_x87_OP(vfprem)
2950 GEN_LOWERED_x87_OP(vfmul)
2951 GEN_LOWERED_x87_OP(vfsub)
2953 GEN_LOWERED_UNOP(Neg)
2955 GEN_LOWERED_LOAD(vfild, fp_x87)
2956 GEN_LOWERED_LOAD(Load, fp_none)
2957 GEN_LOWERED_STORE(vfist, fp_x87)
2958 GEN_LOWERED_STORE(Store, fp_none)
2960 static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
2961 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2962 ir_graph *irg = env->irg;
2963 dbg_info *dbg = get_irn_dbg_info(node);
2964 ir_node *block = transform_node(env, get_nodes_block(node));
2965 ir_node *left = get_binop_left(node);
2966 ir_node *right = get_binop_right(node);
2967 ir_node *new_left = transform_node(env, left);
2968 ir_node *new_right = transform_node(env, right);
2971 vfdiv = new_rd_ia32_vfdiv(dbg, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
2972 clear_ia32_commutative(vfdiv);
2973 set_ia32_am_support(vfdiv, ia32_am_Source);
2974 fold_immediate(env, vfdiv, 2, 3);
2976 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env->cg, node));
2984 * Transforms a l_MulS into a "real" MulS node.
2986 * @param env The transformation environment
2987 * @return the created ia32 Mul node
2989 static ir_node *gen_ia32_l_Mul(ia32_transform_env_t *env, ir_node *node) {
2990 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2991 ir_graph *irg = env->irg;
2992 dbg_info *dbg = get_irn_dbg_info(node);
2993 ir_node *block = transform_node(env, get_nodes_block(node));
2994 ir_node *left = get_binop_left(node);
2995 ir_node *right = get_binop_right(node);
2996 ir_node *new_left = transform_node(env, left);
2997 ir_node *new_right = transform_node(env, right);
3000 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3001 /* and then skip the result Proj, because all needed Projs are already there. */
3002 ir_node *muls = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3003 clear_ia32_commutative(muls);
3004 set_ia32_am_support(muls, ia32_am_Source);
3005 fold_immediate(env, muls, 2, 3);
3007 /* check if EAX and EDX proj exist, add missing one */
3008 in[0] = new_rd_Proj(dbg, irg, block, muls, mode_Iu, pn_EAX);
3009 in[1] = new_rd_Proj(dbg, irg, block, muls, mode_Iu, pn_EDX);
3010 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3012 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env->cg, node));
3017 GEN_LOWERED_SHIFT_OP(Shl)
3018 GEN_LOWERED_SHIFT_OP(Shr)
3019 GEN_LOWERED_SHIFT_OP(Sar)
3022 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3023 * op1 - target to be shifted
3024 * op2 - contains bits to be shifted into target
3026 * Only op3 can be an immediate.
3028 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *node,
3029 ir_node *op1, ir_node *op2,
3031 ir_node *new_op = NULL;
3032 ir_graph *irg = env->irg;
3033 ir_mode *mode = get_irn_mode(node);
3034 dbg_info *dbg = get_irn_dbg_info(node);
3035 ir_node *block = transform_node(env, get_nodes_block(node));
3036 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3037 ir_node *nomem = new_NoMem();
3039 ir_node *new_op1 = transform_node(env, op1);
3040 ir_node *new_op2 = transform_node(env, op2);
3041 ir_node *new_count = transform_node(env, count);
3043 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
3045 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
3047 /* Check if immediate optimization is on and */
3048 /* if it's an operation with immediate. */
3049 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3051 /* Limit imm_op within range imm8 */
3053 tv = get_ia32_Immop_tarval(imm_op);
3056 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3057 set_ia32_Immop_tarval(imm_op, tv);
3064 /* integer operations */
3066 /* This is ShiftD with const */
3067 DB((mod, LEVEL_1, "ShiftD with immediate ..."));
3069 if (is_ia32_l_ShlD(node))
3070 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg,
3071 new_op1, new_op2, noreg, nomem);
3073 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg,
3074 new_op1, new_op2, noreg, nomem);
3075 copy_ia32_Immop_attr(new_op, imm_op);
3078 /* This is a normal ShiftD */
3079 DB((mod, LEVEL_1, "ShiftD binop ..."));
3080 if (is_ia32_l_ShlD(node))
3081 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg,
3082 new_op1, new_op2, new_count, nomem);
3084 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg,
3085 new_op1, new_op2, new_count, nomem);
3088 /* set AM support */
3089 // Matze: node has unsupported format (6inputs)
3090 //set_ia32_am_support(new_op, ia32_am_Dest);
3092 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3094 set_ia32_emit_cl(new_op);
3099 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env, ir_node *node) {
3100 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3101 get_irn_n(node, 1), get_irn_n(node, 2));
3104 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env, ir_node *node) {
3105 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3106 get_irn_n(node, 1), get_irn_n(node, 2));
3110 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3112 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) {
3113 ia32_code_gen_t *cg = env->cg;
3114 ir_node *res = NULL;
3115 ir_graph *irg = env->irg;
3116 dbg_info *dbg = get_irn_dbg_info(node);
3117 ir_node *block = transform_node(env, get_nodes_block(node));
3118 ir_node *ptr = get_irn_n(node, 0);
3119 ir_node *val = get_irn_n(node, 1);
3120 ir_node *new_val = transform_node(env, val);
3121 ir_node *mem = get_irn_n(node, 2);
3122 ir_node *noreg, *new_ptr, *new_mem;
3128 noreg = ia32_new_NoReg_gp(cg);
3129 new_mem = transform_node(env, mem);
3130 new_ptr = transform_node(env, ptr);
3132 /* Store x87 -> MEM */
3133 res = new_rd_ia32_vfst(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
3134 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3135 set_ia32_use_frame(res);
3136 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3137 set_ia32_am_support(res, ia32_am_Dest);
3138 set_ia32_am_flavour(res, ia32_B);
3139 set_ia32_op_type(res, ia32_AddrModeD);
3141 /* Load MEM -> SSE */
3142 res = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, res);
3143 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3144 set_ia32_use_frame(res);
3145 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3146 set_ia32_am_support(res, ia32_am_Source);
3147 set_ia32_am_flavour(res, ia32_B);
3148 set_ia32_op_type(res, ia32_AddrModeS);
3149 res = new_rd_Proj(dbg, irg, block, res, mode_E, pn_ia32_xLoad_res);
3155 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3157 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) {
3158 ia32_code_gen_t *cg = env->cg;
3159 ir_graph *irg = env->irg;
3160 dbg_info *dbg = get_irn_dbg_info(node);
3161 ir_node *block = transform_node(env, get_nodes_block(node));
3162 ir_node *res = NULL;
3163 ir_node *ptr = get_irn_n(node, 0);
3164 ir_node *val = get_irn_n(node, 1);
3165 ir_node *mem = get_irn_n(node, 2);
3166 ir_entity *fent = get_ia32_frame_ent(node);
3167 ir_mode *lsmode = get_ia32_ls_mode(node);
3168 ir_node *new_val = transform_node(env, val);
3169 ir_node *noreg, *new_ptr, *new_mem;
3172 if (!USE_SSE2(cg)) {
3173 /* SSE unit is not used -> skip this node. */
3177 noreg = ia32_new_NoReg_gp(cg);
3178 new_val = transform_node(env, val);
3179 new_ptr = transform_node(env, ptr);
3180 new_mem = transform_node(env, mem);
3182 /* Store SSE -> MEM */
3183 if (is_ia32_xLoad(skip_Proj(new_val))) {
3184 ir_node *ld = skip_Proj(new_val);
3186 /* we can vfld the value directly into the fpu */
3187 fent = get_ia32_frame_ent(ld);
3188 ptr = get_irn_n(ld, 0);
3189 offs = get_ia32_am_offs_int(ld);
3191 res = new_rd_ia32_xStore(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
3192 set_ia32_frame_ent(res, fent);
3193 set_ia32_use_frame(res);
3194 set_ia32_ls_mode(res, lsmode);
3195 set_ia32_am_support(res, ia32_am_Dest);
3196 set_ia32_am_flavour(res, ia32_B);
3197 set_ia32_op_type(res, ia32_AddrModeD);
3201 /* Load MEM -> x87 */
3202 res = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, new_mem);
3203 set_ia32_frame_ent(res, fent);
3204 set_ia32_use_frame(res);
3205 set_ia32_ls_mode(res, lsmode);
3206 add_ia32_am_offs_int(res, offs);
3207 set_ia32_am_support(res, ia32_am_Source);
3208 set_ia32_am_flavour(res, ia32_B);
3209 set_ia32_op_type(res, ia32_AddrModeS);
3210 res = new_rd_Proj(dbg, irg, block, res, lsmode, pn_ia32_vfld_res);
3215 /*********************************************************
3218 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3219 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3220 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3221 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3223 *********************************************************/
3226 * the BAD transformer.
3228 static ir_node *bad_transform(ia32_transform_env_t *env, ir_node *node) {
3229 panic("No transform function for %+F available.\n", node);
3233 static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) {
3234 /* end has to be duplicated manually because we need a dynamic in array */
3235 ir_graph *irg = env->irg;
3236 dbg_info *dbg = get_irn_dbg_info(node);
3237 ir_node *block = transform_node(env, get_nodes_block(node));
3241 new_end = new_ir_node(dbg, irg, block, op_End, mode_X, -1, NULL);
3242 copy_node_attr(node, new_end);
3243 duplicate_deps(env, node, new_end);
3245 set_irg_end(irg, new_end);
3246 set_new_node(new_end, new_end);
3248 /* transform preds */
3249 arity = get_irn_arity(node);
3250 for(i = 0; i < arity; ++i) {
3251 ir_node *in = get_irn_n(node, i);
3252 ir_node *new_in = transform_node(env, in);
3254 add_End_keepalive(new_end, new_in);
3260 static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) {
3261 ir_graph *irg = env->irg;
3262 dbg_info *dbg = get_irn_dbg_info(node);
3263 ir_node *start_block = env->old_anchors[anchor_start_block];
3268 * We replace the ProjX from the start node with a jump,
3269 * so the startblock has no preds anymore now
3271 if(node == start_block) {
3272 return new_rd_Block(dbg, irg, 0, NULL);
3275 /* we use the old blocks for now, because jumps allow cycles in the graph
3276 * we have to fix this later */
3277 block = new_ir_node(dbg, irg, NULL, get_irn_op(node), get_irn_mode(node),
3278 get_irn_arity(node), get_irn_in(node) + 1);
3279 copy_node_attr(node, block);
3281 #ifdef DEBUG_libfirm
3282 block->node_nr = node->node_nr;
3284 set_new_node(node, block);
3286 /* put the preds in the worklist */
3287 arity = get_irn_arity(node);
3288 for(i = 0; i < arity; ++i) {
3289 ir_node *in = get_irn_n(node, i);
3290 pdeq_putr(env->worklist, in);
3296 static ir_node *gen_Proj_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
3297 ir_graph *irg = env->irg;
3298 ir_node *block = transform_node(env, get_nodes_block(node));
3299 dbg_info *dbg = get_irn_dbg_info(node);
3300 ir_node *pred = get_Proj_pred(node);
3301 ir_node *new_pred = transform_node(env, pred);
3302 long proj = get_Proj_proj(node);
3304 if(proj == pn_be_AddSP_res) {
3305 ir_node *res = new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3306 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3308 } else if(proj == pn_be_AddSP_M) {
3309 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3313 return new_rd_Unknown(irg, get_irn_mode(node));
3316 static ir_node *gen_Proj_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
3317 ir_graph *irg = env->irg;
3318 ir_node *block = transform_node(env, get_nodes_block(node));
3319 dbg_info *dbg = get_irn_dbg_info(node);
3320 ir_node *pred = get_Proj_pred(node);
3321 ir_node *new_pred = transform_node(env, pred);
3322 long proj = get_Proj_proj(node);
3324 if(proj == pn_be_SubSP_res) {
3325 ir_node *res = new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3326 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3328 } else if(proj == pn_be_SubSP_M) {
3329 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3333 return new_rd_Unknown(irg, get_irn_mode(node));
3336 static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) {
3337 ir_graph *irg = env->irg;
3338 ir_node *block = transform_node(env, get_nodes_block(node));
3339 dbg_info *dbg = get_irn_dbg_info(node);
3340 ir_node *pred = get_Proj_pred(node);
3341 ir_node *new_pred = transform_node(env, pred);
3342 long proj = get_Proj_proj(node);
3344 /* renumber the proj */
3345 if(is_ia32_Load(new_pred)) {
3346 if(proj == pn_Load_res) {
3347 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3348 } else if(proj == pn_Load_M) {
3349 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3351 } else if(is_ia32_xLoad(new_pred)) {
3352 if(proj == pn_Load_res) {
3353 return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_xLoad_res);
3354 } else if(proj == pn_Load_M) {
3355 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3357 } else if(is_ia32_vfld(new_pred)) {
3358 if(proj == pn_Load_res) {
3359 return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_vfld_res);
3360 } else if(proj == pn_Load_M) {
3361 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3366 return new_rd_Unknown(irg, get_irn_mode(node));
3369 static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) {
3370 ir_graph *irg = env->irg;
3371 dbg_info *dbg = get_irn_dbg_info(node);
3372 ir_node *block = transform_node(env, get_nodes_block(node));
3373 ir_mode *mode = get_irn_mode(node);
3375 ir_node *pred = get_Proj_pred(node);
3376 ir_node *new_pred = transform_node(env, pred);
3377 long proj = get_Proj_proj(node);
3379 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3381 switch(get_irn_opcode(pred)) {
3385 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3387 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3395 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3397 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3405 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3406 case pn_DivMod_res_div:
3407 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3408 case pn_DivMod_res_mod:
3409 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3419 return new_rd_Unknown(irg, mode);
3422 static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node)
3424 ir_graph *irg = env->irg;
3425 dbg_info *dbg = get_irn_dbg_info(node);
3426 ir_node *block = transform_node(env, get_nodes_block(node));
3427 ir_mode *mode = get_irn_mode(node);
3429 ir_node *pred = get_Proj_pred(node);
3430 ir_node *new_pred = transform_node(env, pred);
3431 long proj = get_Proj_proj(node);
3434 case pn_CopyB_M_regular:
3435 if(is_ia32_CopyB_i(new_pred)) {
3436 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3438 } else if(is_ia32_CopyB(new_pred)) {
3439 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3448 return new_rd_Unknown(irg, mode);
3451 static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node)
3453 ir_graph *irg = env->irg;
3454 dbg_info *dbg = get_irn_dbg_info(node);
3455 ir_node *block = transform_node(env, get_nodes_block(node));
3456 ir_mode *mode = get_irn_mode(node);
3458 ir_node *pred = get_Proj_pred(node);
3459 ir_node *new_pred = transform_node(env, pred);
3460 long proj = get_Proj_proj(node);
3463 case pn_ia32_l_vfdiv_M:
3464 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3465 case pn_ia32_l_vfdiv_res:
3466 return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_vfdiv_res);
3471 return new_rd_Unknown(irg, mode);
3474 static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node)
3476 ir_graph *irg = env->irg;
3477 dbg_info *dbg = get_irn_dbg_info(node);
3478 ir_node *block = transform_node(env, get_nodes_block(node));
3479 ir_mode *mode = get_irn_mode(node);
3481 ir_node *pred = get_Proj_pred(node);
3482 ir_node *new_pred = transform_node(env, pred);
3483 long proj = get_Proj_proj(node);
3487 if(is_ia32_xDiv(new_pred)) {
3488 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3490 } else if(is_ia32_vfdiv(new_pred)) {
3491 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3496 if(is_ia32_xDiv(new_pred)) {
3497 return new_rd_Proj(dbg, irg, block, new_pred, mode_E,
3499 } else if(is_ia32_vfdiv(new_pred)) {
3500 return new_rd_Proj(dbg, irg, block, new_pred, mode_E,
3509 return new_rd_Unknown(irg, mode);
3512 static ir_node *gen_Proj_tls(ia32_transform_env_t *env, ir_node *node) {
3513 ir_graph *irg = env->irg;
3514 //dbg_info *dbg = get_irn_dbg_info(node);
3515 dbg_info *dbg = NULL;
3516 ir_node *block = transform_node(env, get_nodes_block(node));
3518 ir_node *res = new_rd_ia32_LdTls(dbg, irg, block, mode_Iu);
3523 static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) {
3524 ir_graph *irg = env->irg;
3525 dbg_info *dbg = get_irn_dbg_info(node);
3526 long proj = get_Proj_proj(node);
3527 ir_mode *mode = get_irn_mode(node);
3528 ir_node *block = transform_node(env, get_nodes_block(node));
3530 ir_node *call = get_Proj_pred(node);
3531 ir_node *new_call = transform_node(env, call);
3533 /* The following is kinda tricky: If we're using SSE, then we have to
3534 * move the result value of the call in floating point registers to an
3535 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3536 * after the call, we have to make sure to correctly make the
3537 * MemProj and the result Proj use these 2 nodes
3539 if(proj == pn_be_Call_M_regular) {
3540 // get new node for result, are we doing the sse load/store hack?
3541 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3542 ir_node *call_res_new;
3543 ir_node *call_res_pred = NULL;
3545 if(call_res != NULL) {
3546 call_res_new = transform_node(env, call_res);
3547 call_res_pred = get_Proj_pred(call_res_new);
3550 if(call_res_pred == NULL || be_is_Call(call_res_pred)) {
3551 return new_rd_Proj(dbg, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3553 assert(is_ia32_xLoad(call_res_pred));
3554 return new_rd_Proj(dbg, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3557 if(proj == pn_be_Call_first_res && mode_is_float(mode)
3558 && USE_SSE2(env->cg)) {
3560 ir_node *frame = get_irg_frame(irg);
3561 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3563 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3565 const arch_register_class_t *cls;
3567 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3568 call_mem = new_rd_Proj(dbg, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3570 /* store st(0) onto stack */
3571 fstp = new_rd_ia32_GetST0(dbg, irg, block, frame, noreg, call_mem);
3573 set_ia32_ls_mode(fstp, mode);
3574 set_ia32_op_type(fstp, ia32_AddrModeD);
3575 set_ia32_use_frame(fstp);
3576 set_ia32_am_flavour(fstp, ia32_am_B);
3577 set_ia32_am_support(fstp, ia32_am_Dest);
3579 /* load into SSE register */
3580 sse_load = new_rd_ia32_xLoad(dbg, irg, block, frame, noreg, fstp);
3581 set_ia32_ls_mode(sse_load, mode);
3582 set_ia32_op_type(sse_load, ia32_AddrModeS);
3583 set_ia32_use_frame(sse_load);
3584 set_ia32_am_flavour(sse_load, ia32_am_B);
3585 set_ia32_am_support(sse_load, ia32_am_Source);
3587 //mproj = new_rd_Proj(dbg, irg, block, sse_load, mode_M, pn_ia32_xLoad_M);
3588 sse_load = new_rd_Proj(dbg, irg, block, sse_load, mode_E, pn_ia32_xLoad_res);
3590 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3592 /* get a Proj representing a caller save register */
3593 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3594 assert(is_Proj(p) && "Proj expected.");
3596 /* user of the the proj is the Keep */
3597 p = get_edge_src_irn(get_irn_out_edge_first(p));
3598 assert(be_is_Keep(p) && "Keep expected.");
3600 /* keep the result */
3601 cls = arch_get_irn_reg_class(env->cg->arch_env, sse_load, -1);
3602 keepin[0] = sse_load;
3603 be_new_Keep(cls, irg, block, 1, keepin);
3608 /* transform call modes to the mode_Iu or mode_E */
3609 if(mode_is_float(mode)) {
3611 } else if(mode != mode_M) {
3615 return new_rd_Proj(dbg, irg, block, new_call, mode, proj);
3618 static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) {
3619 ir_graph *irg = env->irg;
3620 dbg_info *dbg = get_irn_dbg_info(node);
3621 ir_node *pred = get_Proj_pred(node);
3622 long proj = get_Proj_proj(node);
3624 if(is_Store(pred) || be_is_FrameStore(pred)) {
3625 if(proj == pn_Store_M) {
3626 return transform_node(env, pred);
3629 return new_r_Bad(irg);
3631 } else if(is_Load(pred) || be_is_FrameLoad(pred)) {
3632 return gen_Proj_Load(env, node);
3633 } else if(is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3634 return gen_Proj_DivMod(env, node);
3635 } else if(is_CopyB(pred)) {
3636 return gen_Proj_CopyB(env, node);
3637 } else if(is_Quot(pred)) {
3638 return gen_Proj_Quot(env, node);
3639 } else if(is_ia32_l_vfdiv(pred)) {
3640 return gen_Proj_l_vfdiv(env, node);
3641 } else if(be_is_SubSP(pred)) {
3642 return gen_Proj_be_SubSP(env, node);
3643 } else if(be_is_AddSP(pred)) {
3644 return gen_Proj_be_AddSP(env, node);
3645 } else if(be_is_Call(pred)) {
3646 return gen_Proj_be_Call(env, node);
3647 } else if(get_irn_op(pred) == op_Start) {
3648 if(proj == pn_Start_X_initial_exec) {
3649 ir_node *block = get_nodes_block(pred);
3652 block = transform_node(env, block);
3653 // we exchange the ProjX with a jump
3654 jump = new_rd_Jmp(dbg, irg, block);
3655 ir_fprintf(stderr, "created jump: %+F\n", jump);
3658 if(node == env->old_anchors[anchor_tls]) {
3659 return gen_Proj_tls(env, node);
3663 return duplicate_node(env, node);
3667 * Enters all transform functions into the generic pointer
3669 static void register_transformers(void) {
3670 ir_op *op_Max, *op_Min, *op_Mulh;
3672 /* first clear the generic function pointer for all ops */
3673 clear_irp_opcodes_generic_func();
3675 #define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3676 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
3715 /* transform ops from intrinsic lowering */
3737 GEN(ia32_l_X87toSSE);
3738 GEN(ia32_l_SSEtoX87);
3743 /* we should never see these nodes */
3758 /* handle generic backend nodes */
3768 /* set the register for all Unknown nodes */
3771 op_Max = get_op_Max();
3774 op_Min = get_op_Min();
3777 op_Mulh = get_op_Mulh();
3785 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
3789 int deps = get_irn_deps(old_node);
3791 for(i = 0; i < deps; ++i) {
3792 ir_node *dep = get_irn_dep(old_node, i);
3793 ir_node *new_dep = transform_node(env, dep);
3795 add_irn_dep(new_node, new_dep);
3799 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node)
3801 ir_graph *irg = env->irg;
3802 dbg_info *dbg = get_irn_dbg_info(node);
3803 ir_mode *mode = get_irn_mode(node);
3804 ir_op *op = get_irn_op(node);
3809 block = transform_node(env, get_nodes_block(node));
3811 arity = get_irn_arity(node);
3812 if(op->opar == oparity_dynamic) {
3813 new_node = new_ir_node(dbg, irg, block, op, mode, -1, NULL);
3814 for(i = 0; i < arity; ++i) {
3815 ir_node *in = get_irn_n(node, i);
3816 in = transform_node(env, in);
3817 add_irn_n(new_node, in);
3820 ir_node **ins = alloca(arity * sizeof(ins[0]));
3821 for(i = 0; i < arity; ++i) {
3822 ir_node *in = get_irn_n(node, i);
3823 ins[i] = transform_node(env, in);
3826 new_node = new_ir_node(dbg, irg, block, op, mode, arity, ins);
3829 copy_node_attr(node, new_node);
3830 duplicate_deps(env, node, new_node);
3835 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node)
3838 ir_op *op = get_irn_op(node);
3840 if(irn_visited(node)) {
3841 assert(get_new_node(node) != NULL);
3842 return get_new_node(node);
3845 mark_irn_visited(node);
3846 DEBUG_ONLY(set_new_node(node, NULL));
3848 if (op->ops.generic) {
3849 transform_func *transform = (transform_func *)op->ops.generic;
3851 new_node = (*transform)(env, node);
3852 assert(new_node != NULL);
3854 new_node = duplicate_node(env, node);
3856 //ir_fprintf(stderr, "%+F -> %+F\n", node, new_node);
3858 set_new_node(node, new_node);
3859 mark_irn_visited(new_node);
3860 hook_dead_node_elim_subst(current_ir_graph, node, new_node);
3864 static void fix_loops(ia32_transform_env_t *env, ir_node *node)
3868 if(irn_visited(node))
3870 mark_irn_visited(node);
3872 assert(node_is_in_irgs_storage(env->irg, node));
3874 if(!is_Block(node)) {
3875 ir_node *block = get_nodes_block(node);
3876 ir_node *new_block = (ir_node*) get_irn_link(block);
3878 if(new_block != NULL) {
3879 set_nodes_block(node, new_block);
3883 fix_loops(env, block);
3886 arity = get_irn_arity(node);
3887 for(i = 0; i < arity; ++i) {
3888 ir_node *in = get_irn_n(node, i);
3889 ir_node *new = (ir_node*) get_irn_link(in);
3891 if(new != NULL && new != in) {
3892 set_irn_n(node, i, new);
3899 arity = get_irn_deps(node);
3900 for(i = 0; i < arity; ++i) {
3901 ir_node *in = get_irn_dep(node, i);
3902 ir_node *new = (ir_node*) get_irn_link(in);
3904 if(new != NULL && new != in) {
3905 set_irn_dep(node, i, new);
3913 static void pre_transform_node(ir_node **place, ia32_transform_env_t *env)
3918 *place = transform_node(env, *place);
3921 static void transform_nodes(ia32_code_gen_t *cg)
3924 ir_graph *irg = cg->irg;
3926 ia32_transform_env_t env;
3928 hook_dead_node_elim(irg, 1);
3930 inc_irg_visited(irg);
3934 env.visited = get_irg_visited(irg);
3935 env.worklist = new_pdeq();
3936 env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
3937 DEBUG_ONLY(env.mod = cg->mod);
3939 old_end = get_irg_end(irg);
3941 /* put all anchor nodes in the worklist */
3942 for(i = 0; i < anchor_max; ++i) {
3943 ir_node *anchor = irg->anchors[i];
3946 pdeq_putr(env.worklist, anchor);
3949 env.old_anchors[i] = anchor;
3950 // and set it to NULL to make sure we don't accidently use it
3951 irg->anchors[i] = NULL;
3954 // pre transform some anchors (so they are available in the other transform
3956 set_irg_bad(irg, transform_node(&env, env.old_anchors[anchor_bad]));
3957 set_irg_no_mem(irg, transform_node(&env, env.old_anchors[anchor_no_mem]));
3958 set_irg_start_block(irg, transform_node(&env, env.old_anchors[anchor_start_block]));
3959 set_irg_start(irg, transform_node(&env, env.old_anchors[anchor_start]));
3960 set_irg_frame(irg, transform_node(&env, env.old_anchors[anchor_frame]));
3962 pre_transform_node(&cg->unknown_gp, &env);
3963 pre_transform_node(&cg->unknown_vfp, &env);
3964 pre_transform_node(&cg->unknown_xmm, &env);
3965 pre_transform_node(&cg->noreg_gp, &env);
3966 pre_transform_node(&cg->noreg_vfp, &env);
3967 pre_transform_node(&cg->noreg_xmm, &env);
3969 /* process worklist (this should transform all nodes in the graph) */
3970 while(!pdeq_empty(env.worklist)) {
3971 ir_node *node = pdeq_getl(env.worklist);
3972 transform_node(&env, node);
3975 /* fix loops and set new anchors*/
3976 inc_irg_visited(irg);
3977 for(i = 0; i < anchor_max; ++i) {
3978 ir_node *anchor = env.old_anchors[i];
3982 anchor = get_irn_link(anchor);
3983 fix_loops(&env, anchor);
3984 assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
3985 irg->anchors[i] = anchor;
3988 del_pdeq(env.worklist);
3990 hook_dead_node_elim(irg, 0);
3993 void ia32_transform_graph(ia32_code_gen_t *cg)
3995 ir_graph *irg = cg->irg;
3996 be_irg_t *birg = cg->birg;
3997 ir_graph *old_current_ir_graph = current_ir_graph;
3998 int old_interprocedural_view = get_interprocedural_view();
3999 struct obstack *old_obst = NULL;
4000 struct obstack *new_obst = NULL;
4002 current_ir_graph = irg;
4003 set_interprocedural_view(0);
4004 register_transformers();
4006 /* most analysis info is wrong after transformation */
4007 free_callee_info(irg);
4009 irg->outs_state = outs_none;
4011 free_loop_information(irg);
4012 set_irg_doms_inconsistent(irg);
4013 be_invalidate_liveness(birg);
4014 be_invalidate_dom_front(birg);
4016 /* create a new obstack */
4017 old_obst = irg->obst;
4018 new_obst = xmalloc(sizeof(*new_obst));
4019 obstack_init(new_obst);
4020 irg->obst = new_obst;
4021 irg->last_node_idx = 0;
4023 /* create new value table for CSE */
4024 del_identities(irg->value_table);
4025 irg->value_table = new_identities();
4027 /* do the main transformation */
4028 transform_nodes(cg);
4030 /* we don't want the globals anchor anymore */
4031 set_irg_globals(irg, new_r_Bad(irg));
4033 /* free the old obstack */
4034 obstack_free(old_obst, 0);
4038 current_ir_graph = old_current_ir_graph;
4039 set_interprocedural_view(old_interprocedural_view);
4041 /* recalculate edges */
4042 edges_deactivate(irg);
4043 edges_activate(irg);
4047 * Transforms a psi condition.
4049 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
4052 /* if the mode is target mode, we have already seen this part of the tree */
4053 if (get_irn_mode(cond) == mode)
4056 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
4058 set_irn_mode(cond, mode);
4060 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
4061 ir_node *in = get_irn_n(cond, i);
4063 /* if in is a compare: transform into Set/xCmp */
4065 ir_node *new_op = NULL;
4066 ir_node *cmp = get_Proj_pred(in);
4067 ir_node *cmp_a = get_Cmp_left(cmp);
4068 ir_node *cmp_b = get_Cmp_right(cmp);
4069 dbg_info *dbg = get_irn_dbg_info(cmp);
4070 ir_graph *irg = get_irn_irg(cmp);
4071 ir_node *block = get_nodes_block(cmp);
4072 ir_node *noreg = ia32_new_NoReg_gp(cg);
4073 ir_node *nomem = new_rd_NoMem(irg);
4074 int pnc = get_Proj_proj(in);
4076 /* this is a compare */
4077 if (mode_is_float(mode)) {
4078 /* Psi is float, we need a floating point compare */
4081 ir_mode *m = get_irn_mode(cmp_a);
4083 if (! mode_is_float(m)) {
4084 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
4085 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
4087 else if (m == mode_F) {
4088 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
4089 cmp_a = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_a, cmp_a);
4090 cmp_b = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_b, cmp_b);
4093 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4094 set_ia32_pncode(new_op, pnc);
4095 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
4104 construct_binop_func *set_func = NULL;
4106 if (mode_is_float(get_irn_mode(cmp_a))) {
4107 /* 1st case: compare operands are floats */
4112 set_func = new_rd_ia32_xCmpSet;
4116 set_func = new_rd_ia32_vfCmpSet;
4119 pnc &= 7; /* fp compare -> int compare */
4122 /* 2nd case: compare operand are integer too */
4123 set_func = new_rd_ia32_CmpSet;
4126 new_op = set_func(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4127 if(!mode_is_signed(mode))
4128 pnc |= ia32_pn_Cmp_Unsigned;
4130 set_ia32_pncode(new_op, pnc);
4131 set_ia32_am_support(new_op, ia32_am_Source);
4134 /* the the new compare as in */
4135 set_irn_n(cond, i, new_op);
4138 /* another complex condition */
4139 transform_psi_cond(in, mode, cg);
4145 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
4146 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
4147 * compare, which causes the compare result to be stores in a register. The
4148 * "And"s and "Or"s are transformed later, we just have to set their mode right.
4150 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
4151 ia32_code_gen_t *cg = env;
4152 ir_node *psi_sel, *new_cmp, *block;
4157 if (get_irn_opcode(node) != iro_Psi)
4160 psi_sel = get_Psi_cond(node, 0);
4162 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
4163 if (is_Proj(psi_sel))
4166 //mode = get_irn_mode(node);
4167 // TODO this is probably wrong...
4170 transform_psi_cond(psi_sel, mode, cg);
4172 irg = get_irn_irg(node);
4173 block = get_nodes_block(node);
4175 /* we need to compare the evaluated condition tree with 0 */
4176 mode = get_irn_mode(node);
4177 if (mode_is_float(mode)) {
4178 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
4179 /* BEWARE: new_r_Const_long works for floating point as well */
4180 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
4181 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
4184 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode_Iu, 0));
4185 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
4188 set_Psi_cond(node, 0, new_cmp);