2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
30 #include "archop.h" /* we need this for Min and Max nodes */
37 #include "../benode_t.h"
38 #include "../besched.h"
41 #include "bearch_ia32_t.h"
42 #include "ia32_nodes_attr.h"
43 #include "ia32_transform.h"
44 #include "ia32_new_nodes.h"
45 #include "ia32_map_regs.h"
46 #include "ia32_dbg_stat.h"
47 #include "ia32_optimize.h"
48 #include "ia32_util.h"
50 #include "gen_ia32_regalloc_if.h"
52 #define SFP_SIGN "0x80000000"
53 #define DFP_SIGN "0x8000000000000000"
54 #define SFP_ABS "0x7FFFFFFF"
55 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
57 #define TP_SFP_SIGN "ia32_sfp_sign"
58 #define TP_DFP_SIGN "ia32_dfp_sign"
59 #define TP_SFP_ABS "ia32_sfp_abs"
60 #define TP_DFP_ABS "ia32_dfp_abs"
62 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
63 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
64 #define ENT_SFP_ABS "IA32_SFP_ABS"
65 #define ENT_DFP_ABS "IA32_DFP_ABS"
67 typedef struct ia32_transform_env_t {
68 ir_graph *irg; /**< The irg, the node should be created in */
69 ia32_code_gen_t *cg; /**< The code generator */
70 int visited; /**< visited count that indicates whether a
71 node is already transformed */
72 pdeq *worklist; /**< worklist of nodes that still need to be
74 ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/
75 DEBUG_ONLY(firm_dbg_module_t *mod;) /**< The firm debugger */
76 } ia32_transform_env_t;
78 extern ir_op *get_op_Mulh(void);
80 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
81 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
82 ir_node *op2, ir_node *mem);
84 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
85 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
88 typedef ir_node *(transform_func)(ia32_transform_env_t *env, ir_node *node);
90 /****************************************************************************************************
92 * | | | | / _| | | (_)
93 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
94 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
95 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
96 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
98 ****************************************************************************************************/
100 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node);
101 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node);
102 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
105 static INLINE void set_new_node(ir_node *old_node, ir_node *new_node)
107 set_irn_link(old_node, new_node);
110 static INLINE ir_node *get_new_node(ir_node *old_node)
112 assert(irn_visited(old_node));
113 return (ir_node*) get_irn_link(old_node);
117 * Returns 1 if irn is a Const representing 0, 0 otherwise
119 static INLINE int is_ia32_Const_0(ir_node *irn) {
120 return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
121 classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
125 * Returns 1 if irn is a Const representing 1, 0 otherwise
127 static INLINE int is_ia32_Const_1(ir_node *irn) {
128 return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
129 classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
133 * Gets the Proj with number pn from irn.
135 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
136 const ir_edge_t *edge;
138 assert(get_irn_mode(irn) == mode_T && "need mode_T");
140 foreach_out_edge(irn, edge) {
141 proj = get_edge_src_irn(edge);
143 if (get_Proj_proj(proj) == pn)
151 * Collects all Projs of a node into the node array. Index is the projnum.
152 * BEWARE: The caller has to assure the appropriate array size!
154 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
155 const ir_edge_t *edge;
156 assert(get_irn_mode(irn) == mode_T && "need mode_T");
158 memset(projs, 0, size * sizeof(projs[0]));
160 foreach_out_edge(irn, edge) {
161 ir_node *proj = get_edge_src_irn(edge);
162 int proj_proj = get_Proj_proj(proj);
163 assert(proj_proj < size);
164 projs[proj_proj] = proj;
169 * Renumbers the proj having pn_old in the array tp pn_new
170 * and removes the proj from the array.
172 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
173 fprintf(stderr, "Warning: renumber_Proj used!\n");
175 set_Proj_proj(projs[pn_old], pn_new);
176 projs[pn_old] = NULL;
181 * creates a unique ident by adding a number to a tag
183 * @param tag the tag string, must contain a %d if a number
186 static ident *unique_id(const char *tag)
188 static unsigned id = 0;
191 snprintf(str, sizeof(str), tag, ++id);
192 return new_id_from_str(str);
196 * Get a primitive type for a mode.
198 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
200 pmap_entry *e = pmap_find(types, mode);
205 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
206 res = new_type_primitive(new_id_from_str(buf), mode);
207 pmap_insert(types, mode, res);
215 * Get an entity that is initialized with a tarval
217 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
219 tarval *tv = get_Const_tarval(cnst);
220 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
225 ir_mode *mode = get_irn_mode(cnst);
226 ir_type *tp = get_Const_type(cnst);
227 if (tp == firm_unknown_type)
228 tp = get_prim_type(cg->isa->types, mode);
230 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
232 set_entity_ld_ident(res, get_entity_ident(res));
233 set_entity_visibility(res, visibility_local);
234 set_entity_variability(res, variability_constant);
235 set_entity_allocation(res, allocation_static);
237 /* we create a new entity here: It's initialization must resist on the
239 rem = current_ir_graph;
240 current_ir_graph = get_const_code_irg();
241 set_atomic_ent_value(res, new_Const_type(tv, tp));
242 current_ir_graph = rem;
244 pmap_insert(cg->isa->tv_ent, tv, res);
252 * Transforms a Const.
254 * @param mod the debug module
255 * @param block the block the new node should belong to
256 * @param node the ir Const node
257 * @param mode mode of the Const
258 * @return the created ia32 Const node
260 static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) {
261 ir_graph *irg = env->irg;
262 dbg_info *dbg = get_irn_dbg_info(node);
263 ir_mode *mode = get_irn_mode(node);
264 ir_node *block = transform_node(env, get_nodes_block(node));
266 if (mode_is_float(mode)) {
269 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
270 ir_node *nomem = new_NoMem();
274 if (! USE_SSE2(env->cg)) {
275 cnst_classify_t clss = classify_Const(node);
277 if (clss == CNST_NULL) {
278 load = new_rd_ia32_vfldz(dbg, irg, block);
280 } else if (clss == CNST_ONE) {
281 load = new_rd_ia32_vfld1(dbg, irg, block);
284 floatent = get_entity_for_tv(env->cg, node);
286 load = new_rd_ia32_vfld(dbg, irg, block, noreg, noreg, nomem);
287 set_ia32_am_support(load, ia32_am_Source);
288 set_ia32_op_type(load, ia32_AddrModeS);
289 set_ia32_am_flavour(load, ia32_am_N);
290 set_ia32_am_sc(load, ia32_get_ent_ident(floatent));
291 res = new_r_Proj(irg, block, load, mode_D, pn_ia32_vfld_res);
294 floatent = get_entity_for_tv(env->cg, node);
296 load = new_rd_ia32_xLoad(dbg, irg, block, noreg, noreg, nomem);
297 set_ia32_am_support(load, ia32_am_Source);
298 set_ia32_op_type(load, ia32_AddrModeS);
299 set_ia32_am_flavour(load, ia32_am_N);
300 set_ia32_am_sc(load, ia32_get_ent_ident(floatent));
301 res = new_r_Proj(irg, block, load, mode_D, pn_ia32_xLoad_res);
304 set_ia32_ls_mode(load, mode);
305 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
307 /* Const Nodes before the initial IncSP are a bad idea, because
308 * they could be spilled and we have no SP ready at that point yet
310 if (get_irg_start_block(irg) == block) {
311 add_irn_dep(load, get_irg_frame(irg));
314 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
317 ir_node *cnst = new_rd_ia32_Const(dbg, irg, block);
320 if (get_irg_start_block(irg) == block) {
321 add_irn_dep(cnst, get_irg_frame(irg));
324 set_ia32_Const_attr(cnst, node);
325 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
330 return new_r_Bad(irg);
334 * Transforms a SymConst.
336 * @param mod the debug module
337 * @param block the block the new node should belong to
338 * @param node the ir SymConst node
339 * @param mode mode of the SymConst
340 * @return the created ia32 Const node
342 static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) {
343 ir_graph *irg = env->irg;
344 dbg_info *dbg = get_irn_dbg_info(node);
345 ir_mode *mode = get_irn_mode(node);
346 ir_node *block = transform_node(env, get_nodes_block(node));
349 if (mode_is_float(mode)) {
351 if (USE_SSE2(env->cg))
352 cnst = new_rd_ia32_xConst(dbg, irg, block);
354 cnst = new_rd_ia32_vfConst(dbg, irg, block);
355 set_ia32_ls_mode(cnst, mode);
357 cnst = new_rd_ia32_Const(dbg, irg, block);
360 /* Const Nodes before the initial IncSP are a bad idea, because
361 * they could be spilled and we have no SP ready at that point yet
363 if (get_irg_start_block(irg) == block) {
364 add_irn_dep(cnst, get_irg_frame(irg));
367 set_ia32_Const_attr(cnst, node);
368 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
374 * SSE convert of an integer node into a floating point node.
376 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg,
377 ir_graph *irg, ir_node *block,
378 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
380 ir_node *noreg = ia32_new_NoReg_gp(cg);
381 ir_node *nomem = new_rd_NoMem(irg);
382 ir_node *old_pred = get_Cmp_left(old_node);
383 ir_mode *in_mode = get_irn_mode(old_pred);
384 int in_bits = get_mode_size_bits(in_mode);
386 ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
387 set_ia32_ls_mode(conv, tgt_mode);
389 set_ia32_am_support(conv, ia32_am_Source);
391 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
397 * SSE convert of an float node into a double node.
399 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbg,
400 ir_graph *irg, ir_node *block,
401 ir_node *in, ir_node *old_node)
403 ir_node *noreg = ia32_new_NoReg_gp(cg);
404 ir_node *nomem = new_rd_NoMem(irg);
406 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, in, nomem);
407 set_ia32_am_support(conv, ia32_am_Source);
408 set_ia32_ls_mode(conv, mode_D);
409 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
414 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
415 ident *ia32_gen_fp_known_const(ia32_known_const_t kct) {
416 static const struct {
418 const char *ent_name;
419 const char *cnst_str;
420 } names [ia32_known_const_max] = {
421 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
422 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
423 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
424 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
426 static ir_entity *ent_cache[ia32_known_const_max];
428 const char *tp_name, *ent_name, *cnst_str;
436 ent_name = names[kct].ent_name;
437 if (! ent_cache[kct]) {
438 tp_name = names[kct].tp_name;
439 cnst_str = names[kct].cnst_str;
441 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
442 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
443 tp = new_type_primitive(new_id_from_str(tp_name), mode);
444 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
446 set_entity_ld_ident(ent, get_entity_ident(ent));
447 set_entity_visibility(ent, visibility_local);
448 set_entity_variability(ent, variability_constant);
449 set_entity_allocation(ent, allocation_static);
451 /* we create a new entity here: It's initialization must resist on the
453 rem = current_ir_graph;
454 current_ir_graph = get_const_code_irg();
455 cnst = new_Const(mode, tv);
456 current_ir_graph = rem;
458 set_atomic_ent_value(ent, cnst);
460 /* cache the entry */
461 ent_cache[kct] = ent;
464 return get_entity_ident(ent_cache[kct]);
469 * Prints the old node name on cg obst and returns a pointer to it.
471 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
472 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
474 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
475 obstack_1grow(isa->name_obst, 0);
476 return obstack_finish(isa->name_obst);
480 /* determine if one operator is an Imm */
481 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
483 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
484 else return is_ia32_Cnst(op2) ? op2 : NULL;
487 /* determine if one operator is not an Imm */
488 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
489 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
492 static void fold_immediate(ia32_transform_env_t *env, ir_node *node, int in1, int in2) {
496 if(! (env->cg->opt & IA32_OPT_IMMOPS))
499 left = get_irn_n(node, in1);
500 right = get_irn_n(node, in2);
501 if(!is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
502 /* we can only set right operand to immediate */
503 if(!is_ia32_commutative(node))
505 /* exchange left/right */
506 set_irn_n(node, in1, right);
507 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
508 set_ia32_Immop_attr(node, left);
509 } else if(is_ia32_Cnst(right)) {
510 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
511 set_ia32_Immop_attr(node, right);
516 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
520 * Construct a standard binary operation, set AM and immediate if required.
522 * @param env The transformation environment
523 * @param op1 The first operand
524 * @param op2 The second operand
525 * @param func The node constructor function
526 * @return The constructed ia32 node.
528 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *node,
529 ir_node *op1, ir_node *op2,
530 construct_binop_func *func) {
531 ir_node *new_node = NULL;
532 ir_graph *irg = env->irg;
533 dbg_info *dbg = get_irn_dbg_info(node);
534 ir_node *block = transform_node(env, get_nodes_block(node));
535 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
536 ir_node *nomem = new_NoMem();
537 ir_node *new_op1 = transform_node(env, op1);
538 ir_node *new_op2 = transform_node(env, op2);
540 new_node = func(dbg, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
541 if(func == new_rd_ia32_Mul) {
542 set_ia32_am_support(new_node, ia32_am_Source);
544 set_ia32_am_support(new_node, ia32_am_Full);
547 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
548 if (is_op_commutative(get_irn_op(node))) {
549 set_ia32_commutative(new_node);
551 fold_immediate(env, new_node, 2, 3);
557 * Construct a standard binary operation, set AM and immediate if required.
559 * @param env The transformation environment
560 * @param op1 The first operand
561 * @param op2 The second operand
562 * @param func The node constructor function
563 * @return The constructed ia32 node.
565 static ir_node *gen_binop_float(ia32_transform_env_t *env, ir_node *node,
566 ir_node *op1, ir_node *op2,
567 construct_binop_func *func)
569 ir_node *new_node = NULL;
570 dbg_info *dbg = get_irn_dbg_info(node);
571 ir_graph *irg = env->irg;
572 ir_mode *mode = get_irn_mode(node);
573 ir_node *block = transform_node(env, get_nodes_block(node));
574 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
575 ir_node *nomem = new_NoMem();
576 ir_node *new_op1 = transform_node(env, op1);
577 ir_node *new_op2 = transform_node(env, op2);
579 new_node = func(dbg, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
580 set_ia32_am_support(new_node, ia32_am_Source);
581 if (is_op_commutative(get_irn_op(node))) {
582 set_ia32_commutative(new_node);
584 if (USE_SSE2(env->cg)) {
585 set_ia32_ls_mode(new_node, mode);
588 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
595 * Construct a shift/rotate binary operation, sets AM and immediate if required.
597 * @param env The transformation environment
598 * @param op1 The first operand
599 * @param op2 The second operand
600 * @param func The node constructor function
601 * @return The constructed ia32 node.
603 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node,
604 ir_node *op1, ir_node *op2,
605 construct_binop_func *func) {
606 ir_node *new_op = NULL;
607 ir_mode *mode = get_irn_mode(node);
608 dbg_info *dbg = get_irn_dbg_info(node);
609 ir_graph *irg = env->irg;
610 ir_node *block = transform_node(env, get_nodes_block(node));
611 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
612 ir_node *nomem = new_NoMem();
615 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
616 ir_node *new_op1 = transform_node(env, op1);
617 ir_node *new_op2 = transform_node(env, op2);
620 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
622 /* Check if immediate optimization is on and */
623 /* if it's an operation with immediate. */
624 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
625 expr_op = get_expr_op(new_op1, new_op2);
627 assert((expr_op || imm_op) && "invalid operands");
630 /* We have two consts here: not yet supported */
634 /* Limit imm_op within range imm8 */
636 tv = get_ia32_Immop_tarval(imm_op);
639 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
640 set_ia32_Immop_tarval(imm_op, tv);
647 /* integer operations */
649 /* This is shift/rot with const */
650 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
652 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
653 set_ia32_Immop_attr(new_op, imm_op);
655 /* This is a normal shift/rot */
656 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
657 new_op = func(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
661 set_ia32_am_support(new_op, ia32_am_Dest);
663 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
665 set_ia32_emit_cl(new_op);
672 * Construct a standard unary operation, set AM and immediate if required.
674 * @param env The transformation environment
675 * @param op The operand
676 * @param func The node constructor function
677 * @return The constructed ia32 node.
679 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *node, ir_node *op,
680 construct_unop_func *func) {
681 ir_node *new_node = NULL;
682 ir_graph *irg = env->irg;
683 dbg_info *dbg = get_irn_dbg_info(node);
684 ir_node *block = transform_node(env, get_nodes_block(node));
685 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
686 ir_node *nomem = new_NoMem();
687 ir_node *new_op = transform_node(env, op);
688 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
690 new_node = func(dbg, irg, block, noreg, noreg, new_op, nomem);
691 DB((mod, LEVEL_1, "INT unop ..."));
692 set_ia32_am_support(new_node, ia32_am_Dest);
694 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
701 * Creates an ia32 Add with immediate.
703 * @param env The transformation environment
704 * @param expr_op The expression operator
705 * @param const_op The constant
706 * @return the created ia32 Add node
708 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *node,
709 ir_node *expr_op, ir_node *const_op) {
710 ir_node *new_op = NULL;
711 tarval *tv = get_ia32_Immop_tarval(const_op);
712 ir_graph *irg = env->irg;
713 dbg_info *dbg = get_irn_dbg_info(node);
714 ir_node *block = transform_node(env, get_nodes_block(node));
715 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
716 ir_node *nomem = new_NoMem();
718 tarval_classification_t class_tv, class_negtv;
719 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
721 /* try to optimize to inc/dec */
722 if ((env->cg->opt & IA32_OPT_INCDEC) && tv && (get_ia32_op_type(const_op) == ia32_Const)) {
723 /* optimize tarvals */
724 class_tv = classify_tarval(tv);
725 class_negtv = classify_tarval(tarval_neg(tv));
727 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
728 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
729 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
732 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
733 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
734 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
740 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
741 set_ia32_Immop_attr(new_op, const_op);
742 set_ia32_commutative(new_op);
749 * Creates an ia32 Add.
751 * @param env The transformation environment
752 * @return the created ia32 Add node
754 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) {
755 ir_node *new_op = NULL;
756 ir_graph *irg = env->irg;
757 dbg_info *dbg = get_irn_dbg_info(node);
758 ir_mode *mode = get_irn_mode(node);
759 ir_node *block = transform_node(env, get_nodes_block(node));
760 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
761 ir_node *nomem = new_NoMem();
762 ir_node *expr_op, *imm_op;
763 ir_node *op1 = get_Add_left(node);
764 ir_node *op2 = get_Add_right(node);
765 ir_node *new_op1 = transform_node(env, op1);
766 ir_node *new_op2 = transform_node(env, op2);
768 /* Check if immediate optimization is on and */
769 /* if it's an operation with immediate. */
770 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
771 expr_op = get_expr_op(new_op1, new_op2);
773 assert((expr_op || imm_op) && "invalid operands");
775 if (mode_is_float(mode)) {
777 if (USE_SSE2(env->cg))
778 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xAdd);
780 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfadd);
785 /* No expr_op means, that we have two const - one symconst and */
786 /* one tarval or another symconst - because this case is not */
787 /* covered by constant folding */
788 /* We need to check for: */
789 /* 1) symconst + const -> becomes a LEA */
790 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
791 /* linker doesn't support two symconsts */
793 if (get_ia32_op_type(new_op1) == ia32_SymConst
794 && get_ia32_op_type(new_op2) == ia32_SymConst) {
795 /* this is the 2nd case */
796 new_op = new_rd_ia32_Lea(dbg, irg, block, new_op1, noreg);
797 set_ia32_am_sc(new_op, get_ia32_id_cnst(new_op2));
798 set_ia32_am_flavour(new_op, ia32_am_OB);
799 set_ia32_am_support(new_op, ia32_am_Source);
800 set_ia32_op_type(new_op, ia32_AddrModeS);
802 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
804 /* this is the 1st case */
805 if (get_ia32_op_type(new_op1) == ia32_SymConst) {
806 tarval *tv = get_ia32_cnst_tv(new_op2);
807 long offs = get_tarval_long(tv);
809 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
810 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
812 set_ia32_am_sc(new_op, get_ia32_id_cnst(new_op1));
813 add_ia32_am_offs_int(new_op, offs);
814 set_ia32_am_flavour(new_op, ia32_am_O);
815 set_ia32_am_support(new_op, ia32_am_Source);
816 set_ia32_op_type(new_op, ia32_AddrModeS);
817 } else if (get_ia32_op_type(new_op2) == ia32_SymConst) {
818 tarval *tv = get_ia32_cnst_tv(new_op1);
819 long offs = get_tarval_long(tv);
821 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
822 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
824 add_ia32_am_offs_int(new_op, offs);
825 set_ia32_am_sc(new_op, get_ia32_id_cnst(new_op2));
826 set_ia32_am_flavour(new_op, ia32_am_O);
827 set_ia32_am_support(new_op, ia32_am_Source);
828 set_ia32_op_type(new_op, ia32_AddrModeS);
830 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
832 tarval *tv1 = get_ia32_cnst_tv(new_op1);
833 tarval *tv2 = get_ia32_cnst_tv(new_op2);
834 tarval *restv = tarval_add(tv1, tv2);
836 new_op = new_rd_ia32_Const(dbg, irg, block);
837 set_ia32_Const_tarval(new_op, restv);
838 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
845 /* This is expr + const */
846 new_op = gen_imm_Add(env, node, expr_op, imm_op);
849 set_ia32_am_support(new_op, ia32_am_Dest);
852 /* This is a normal add */
853 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
856 set_ia32_am_support(new_op, ia32_am_Full);
857 set_ia32_commutative(new_op);
861 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
869 * Creates an ia32 Mul.
871 * @param env The transformation environment
872 * @return the created ia32 Mul node
874 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) {
875 ir_node *op1 = get_Mul_left(node);
876 ir_node *op2 = get_Mul_right(node);
878 ir_mode *mode = get_irn_mode(node);
880 if (mode_is_float(mode)) {
882 if (USE_SSE2(env->cg))
883 new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul);
885 new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul);
888 new_op = gen_binop(env, node, op1, op2, new_rd_ia32_Mul);
897 * Creates an ia32 Mulh.
898 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
899 * this result while Mul returns the lower 32 bit.
901 * @param env The transformation environment
902 * @return the created ia32 Mulh node
904 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) {
905 ir_graph *irg = env->irg;
906 dbg_info *dbg = get_irn_dbg_info(node);
907 ir_node *block = transform_node(env, get_nodes_block(node));
908 ir_node *op1 = get_irn_n(node, 0);
909 ir_node *op2 = get_irn_n(node, 1);
910 ir_node *new_op1 = transform_node(env, op1);
911 ir_node *new_op2 = transform_node(env, op2);
912 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
913 ir_node *proj_EAX, *proj_EDX, *mulh;
914 ir_mode *mode = get_irn_mode(node);
917 assert(!mode_is_float(mode) && "Mulh with float not supported");
918 mulh = new_rd_ia32_Mulh(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
919 set_ia32_commutative(mulh);
920 set_ia32_am_support(mulh, ia32_am_Source);
922 /* imediates are not supported, so no fold_immediate */
923 proj_EAX = new_rd_Proj(dbg, irg, block, mulh, mode_Iu, pn_EAX);
924 proj_EDX = new_rd_Proj(dbg, irg, block, mulh, mode_Iu, pn_EDX);
928 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
936 * Creates an ia32 And.
938 * @param env The transformation environment
939 * @return The created ia32 And node
941 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *node) {
942 ir_node *op1 = get_And_left(node);
943 ir_node *op2 = get_And_right(node);
944 ir_mode *mode = get_irn_mode(node);
946 assert (! mode_is_float(mode));
947 return gen_binop(env, node, op1, op2, new_rd_ia32_And);
953 * Creates an ia32 Or.
955 * @param env The transformation environment
956 * @return The created ia32 Or node
958 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *node) {
959 ir_node *op1 = get_Or_left(node);
960 ir_node *op2 = get_Or_right(node);
961 ir_mode *mode = get_irn_mode(node);
963 assert (! mode_is_float(mode));
964 return gen_binop(env, node, op1, op2, new_rd_ia32_Or);
970 * Creates an ia32 Eor.
972 * @param env The transformation environment
973 * @return The created ia32 Eor node
975 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *node) {
976 ir_node *op1 = get_Eor_left(node);
977 ir_node *op2 = get_Eor_right(node);
978 ir_mode *mode = get_irn_mode(node);
980 assert(! mode_is_float(mode));
981 return gen_binop(env, node, op1, op2, new_rd_ia32_Eor);
987 * Creates an ia32 Max.
989 * @param env The transformation environment
990 * @return the created ia32 Max node
992 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *node) {
993 ir_graph *irg = env->irg;
995 ir_mode *mode = get_irn_mode(node);
996 dbg_info *dbg = get_irn_dbg_info(node);
997 ir_node *block = transform_node(env, get_nodes_block(node));
998 ir_node *op1 = get_irn_n(node, 0);
999 ir_node *op2 = get_irn_n(node, 1);
1000 ir_node *new_op1 = transform_node(env, op1);
1001 ir_node *new_op2 = transform_node(env, op2);
1002 ir_mode *op_mode = get_irn_mode(op1);
1004 assert(get_mode_size_bits(mode) == 32);
1006 if (mode_is_float(mode)) {
1008 if (USE_SSE2(env->cg))
1009 new_op = gen_binop_float(env, node, new_op1, new_op2, new_rd_ia32_xMax);
1015 long pnc = pn_Cmp_Gt;
1016 if(!mode_is_signed(op_mode)) {
1017 pnc |= ia32_pn_Cmp_Unsigned;
1019 new_op = new_rd_ia32_CmpCMov(dbg, irg, block, new_op1, new_op2, new_op1, new_op2);
1020 set_ia32_pncode(new_op, pnc);
1021 set_ia32_am_support(new_op, ia32_am_None);
1023 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1029 * Creates an ia32 Min.
1031 * @param env The transformation environment
1032 * @return the created ia32 Min node
1034 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *node) {
1035 ir_graph *irg = env->irg;
1037 ir_mode *mode = get_irn_mode(node);
1038 dbg_info *dbg = get_irn_dbg_info(node);
1039 ir_node *block = transform_node(env, get_nodes_block(node));
1040 ir_node *op1 = get_irn_n(node, 0);
1041 ir_node *op2 = get_irn_n(node, 1);
1042 ir_node *new_op1 = transform_node(env, op1);
1043 ir_node *new_op2 = transform_node(env, op2);
1044 ir_mode *op_mode = get_irn_mode(op1);
1046 assert(get_mode_size_bits(mode) == 32);
1048 if (mode_is_float(mode)) {
1050 if (USE_SSE2(env->cg))
1051 new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMin);
1057 long pnc = pn_Cmp_Lt;
1058 if(!mode_is_signed(op_mode)) {
1059 pnc |= ia32_pn_Cmp_Unsigned;
1061 new_op = new_rd_ia32_CmpCMov(dbg, irg, block, new_op1, new_op2, new_op1, new_op2);
1062 set_ia32_pncode(new_op, pnc);
1063 set_ia32_am_support(new_op, ia32_am_None);
1065 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1073 * Creates an ia32 Sub with immediate.
1075 * @param env The transformation environment
1076 * @param expr_op The first operator
1077 * @param const_op The constant operator
1078 * @return The created ia32 Sub node
1080 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *node,
1081 ir_node *expr_op, ir_node *const_op) {
1082 ir_node *new_op = NULL;
1083 tarval *tv = get_ia32_Immop_tarval(const_op);
1084 ir_graph *irg = env->irg;
1085 dbg_info *dbg = get_irn_dbg_info(node);
1086 ir_node *block = transform_node(env, get_nodes_block(node));
1087 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1088 ir_node *nomem = new_NoMem();
1090 tarval_classification_t class_tv, class_negtv;
1091 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1093 /* try to optimize to inc/dec */
1094 if ((env->cg->opt & IA32_OPT_INCDEC) && tv && (get_ia32_op_type(const_op) == ia32_Const)) {
1095 /* optimize tarvals */
1096 class_tv = classify_tarval(tv);
1097 class_negtv = classify_tarval(tarval_neg(tv));
1099 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
1100 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
1101 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
1104 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
1105 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
1106 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
1112 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
1113 set_ia32_Immop_attr(new_op, const_op);
1120 * Creates an ia32 Sub.
1122 * @param env The transformation environment
1123 * @return The created ia32 Sub node
1125 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) {
1126 ir_node *new_op = NULL;
1127 ir_graph *irg = env->irg;
1128 dbg_info *dbg = get_irn_dbg_info(node);
1129 ir_mode *mode = get_irn_mode(node);
1130 ir_node *block = transform_node(env, get_nodes_block(node));
1131 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1132 ir_node *nomem = new_NoMem();
1133 ir_node *op1 = get_Sub_left(node);
1134 ir_node *op2 = get_Sub_right(node);
1135 ir_node *new_op1 = transform_node(env, op1);
1136 ir_node *new_op2 = transform_node(env, op2);
1137 ir_node *expr_op, *imm_op;
1139 /* Check if immediate optimization is on and */
1140 /* if it's an operation with immediate. */
1141 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1142 expr_op = get_expr_op(new_op1, new_op2);
1144 assert((expr_op || imm_op) && "invalid operands");
1146 if (mode_is_float(mode)) {
1148 if (USE_SSE2(env->cg))
1149 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xSub);
1151 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfsub);
1155 /* No expr_op means, that we have two const - one symconst and */
1156 /* one tarval or another symconst - because this case is not */
1157 /* covered by constant folding */
1158 /* We need to check for: */
1159 /* 1) symconst - const -> becomes a LEA */
1160 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1161 /* linker doesn't support two symconsts */
1163 if (get_ia32_op_type(new_op1) == ia32_SymConst
1164 && get_ia32_op_type(new_op2) == ia32_SymConst) {
1165 /* this is the 2nd case */
1166 new_op = new_rd_ia32_Lea(dbg, irg, block, new_op1, noreg);
1167 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
1168 set_ia32_am_sc_sign(new_op);
1169 set_ia32_am_flavour(new_op, ia32_am_OB);
1171 DBG_OPT_LEA3(op1, op2, node, new_op);
1173 /* this is the 1st case */
1174 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
1176 DBG_OPT_LEA3(op1, op2, node, new_op);
1178 if (get_ia32_op_type(new_op1) == ia32_SymConst) {
1179 tarval *tv = get_ia32_cnst_tv(new_op2);
1180 long offs = get_tarval_long(tv);
1182 set_ia32_am_sc(new_op, get_ia32_id_cnst(new_op1));
1183 add_ia32_am_offs_int(new_op, -offs);
1184 set_ia32_am_flavour(new_op, ia32_am_O);
1185 set_ia32_am_support(new_op, ia32_am_Source);
1186 set_ia32_op_type(new_op, ia32_AddrModeS);
1187 } else if (get_ia32_op_type(new_op2) == ia32_SymConst) {
1188 tarval *tv = get_ia32_cnst_tv(new_op1);
1189 long offs = get_tarval_long(tv);
1191 add_ia32_am_offs_int(new_op, offs);
1192 set_ia32_am_sc(new_op, get_ia32_id_cnst(new_op2));
1193 set_ia32_am_sc_sign(new_op);
1194 set_ia32_am_flavour(new_op, ia32_am_O);
1195 set_ia32_am_support(new_op, ia32_am_Source);
1196 set_ia32_op_type(new_op, ia32_AddrModeS);
1198 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1200 tarval *tv1 = get_ia32_cnst_tv(new_op1);
1201 tarval *tv2 = get_ia32_cnst_tv(new_op2);
1202 tarval *restv = tarval_sub(tv1, tv2);
1204 new_op = new_rd_ia32_Const(dbg, irg, block);
1205 set_ia32_Const_tarval(new_op, restv);
1206 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1211 } else if (imm_op) {
1212 /* This is expr - const */
1213 new_op = gen_imm_Sub(env, node, expr_op, imm_op);
1215 /* set AM support */
1216 set_ia32_am_support(new_op, ia32_am_Dest);
1218 /* This is a normal sub */
1219 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1221 /* set AM support */
1222 set_ia32_am_support(new_op, ia32_am_Full);
1226 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1234 * Generates an ia32 DivMod with additional infrastructure for the
1235 * register allocator if needed.
1237 * @param env The transformation environment
1238 * @param dividend -no comment- :)
1239 * @param divisor -no comment- :)
1240 * @param dm_flav flavour_Div/Mod/DivMod
1241 * @return The created ia32 DivMod node
1243 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *node,
1244 ir_node *dividend, ir_node *divisor,
1245 ia32_op_flavour_t dm_flav) {
1246 ir_graph *irg = env->irg;
1247 dbg_info *dbg = get_irn_dbg_info(node);
1248 ir_mode *mode = get_irn_mode(node);
1249 ir_node *block = transform_node(env, get_nodes_block(node));
1250 ir_node *res, *proj_div, *proj_mod;
1251 ir_node *edx_node, *cltd;
1252 ir_node *in_keep[1];
1253 ir_node *mem, *new_mem;
1254 ir_node *projs[pn_DivMod_max];
1255 ir_node *new_dividend = transform_node(env, dividend);
1256 ir_node *new_divisor = transform_node(env, divisor);
1258 ia32_collect_Projs(node, projs, pn_DivMod_max);
1262 mem = get_Div_mem(node);
1263 mode = get_irn_mode(get_proj_for_pn(node, pn_Div_res));
1266 mem = get_Mod_mem(node);
1267 mode = get_irn_mode(get_proj_for_pn(node, pn_Mod_res));
1269 case flavour_DivMod:
1270 mem = get_DivMod_mem(node);
1271 proj_div = get_proj_for_pn(node, pn_DivMod_res_div);
1272 proj_mod = get_proj_for_pn(node, pn_DivMod_res_mod);
1273 mode = proj_div ? get_irn_mode(proj_div) : get_irn_mode(proj_mod);
1278 new_mem = transform_node(env, mem);
1280 if (mode_is_signed(mode)) {
1281 /* in signed mode, we need to sign extend the dividend */
1282 cltd = new_rd_ia32_Cdq(dbg, irg, block, new_dividend);
1283 new_dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Iu, pn_ia32_Cdq_EAX);
1284 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Iu, pn_ia32_Cdq_EDX);
1287 edx_node = new_rd_ia32_Const(dbg, irg, block);
1288 add_irn_dep(edx_node, be_abi_get_start_barrier(env->cg->birg->abi));
1289 set_ia32_Const_type(edx_node, ia32_Const);
1290 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1293 if(mode_is_signed(mode)) {
1294 res = new_rd_ia32_IDiv(dbg, irg, block, new_dividend, new_divisor, edx_node, new_mem, dm_flav);
1296 res = new_rd_ia32_Div(dbg, irg, block, new_dividend, new_divisor, edx_node, new_mem, dm_flav);
1298 set_ia32_n_res(res, 2);
1300 /* Only one proj is used -> We must add a second proj and */
1301 /* connect this one to a Keep node to eat up the second */
1302 /* destroyed register. */
1303 /* We also renumber the Firm projs into ia32 projs. */
1305 switch (get_irn_opcode(node)) {
1307 /* add Proj-Keep for mod res */
1308 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1309 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1312 /* add Proj-Keep for div res */
1313 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1314 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1317 /* check, which Proj-Keep, we need to add */
1318 proj_div = get_proj_for_pn(node, pn_DivMod_res_div);
1319 proj_mod = get_proj_for_pn(node, pn_DivMod_res_mod);
1321 if (proj_div && proj_mod) {
1322 /* nothing to be done */
1324 else if (! proj_div && ! proj_mod) {
1325 assert(0 && "Missing DivMod result proj");
1327 else if (! proj_div) {
1328 /* We have only mod result: add div res Proj-Keep */
1329 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1330 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1333 /* We have only div result: add mod res Proj-Keep */
1334 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1335 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1339 assert(0 && "Div, Mod, or DivMod expected.");
1343 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1350 * Wrapper for generate_DivMod. Sets flavour_Mod.
1352 * @param env The transformation environment
1354 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *node) {
1355 return generate_DivMod(env, node, get_Mod_left(node),
1356 get_Mod_right(node), flavour_Mod);
1360 * Wrapper for generate_DivMod. Sets flavour_Div.
1362 * @param env The transformation environment
1364 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *node) {
1365 return generate_DivMod(env, node, get_Div_left(node),
1366 get_Div_right(node), flavour_Div);
1370 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1372 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *node) {
1373 return generate_DivMod(env, node, get_DivMod_left(node),
1374 get_DivMod_right(node), flavour_DivMod);
1380 * Creates an ia32 floating Div.
1382 * @param env The transformation environment
1383 * @return The created ia32 xDiv node
1385 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *node) {
1386 ir_graph *irg = env->irg;
1387 dbg_info *dbg = get_irn_dbg_info(node);
1388 ir_node *block = transform_node(env, get_nodes_block(node));
1389 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1391 ir_node *nomem = new_rd_NoMem(env->irg);
1392 ir_node *op1 = get_Quot_left(node);
1393 ir_node *op2 = get_Quot_right(node);
1394 ir_node *new_op1 = transform_node(env, op1);
1395 ir_node *new_op2 = transform_node(env, op2);
1398 if (USE_SSE2(env->cg)) {
1399 ir_mode *mode = get_irn_mode(op1);
1400 if (is_ia32_xConst(new_op2)) {
1401 new_op = new_rd_ia32_xDiv(dbg, irg, block, noreg, noreg, new_op1, noreg, nomem);
1402 set_ia32_am_support(new_op, ia32_am_None);
1403 set_ia32_Immop_attr(new_op, new_op2);
1405 new_op = new_rd_ia32_xDiv(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1406 // Matze: disabled for now, spillslot coalescer fails
1407 //set_ia32_am_support(new_op, ia32_am_Source);
1409 set_ia32_ls_mode(new_op, mode);
1411 new_op = new_rd_ia32_vfdiv(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1412 // Matze: disabled for now (spillslot coalescer fails)
1413 //set_ia32_am_support(new_op, ia32_am_Source);
1415 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1421 * Creates an ia32 Shl.
1423 * @param env The transformation environment
1424 * @return The created ia32 Shl node
1426 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *node) {
1427 return gen_shift_binop(env, node, get_Shl_left(node), get_Shl_right(node),
1434 * Creates an ia32 Shr.
1436 * @param env The transformation environment
1437 * @return The created ia32 Shr node
1439 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *node) {
1440 return gen_shift_binop(env, node, get_Shr_left(node),
1441 get_Shr_right(node), new_rd_ia32_Shr);
1447 * Creates an ia32 Shrs.
1449 * @param env The transformation environment
1450 * @return The created ia32 Shrs node
1452 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) {
1453 return gen_shift_binop(env, node, get_Shrs_left(node),
1454 get_Shrs_right(node), new_rd_ia32_Shrs);
1460 * Creates an ia32 RotL.
1462 * @param env The transformation environment
1463 * @param op1 The first operator
1464 * @param op2 The second operator
1465 * @return The created ia32 RotL node
1467 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node,
1468 ir_node *op1, ir_node *op2) {
1469 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_RotL);
1475 * Creates an ia32 RotR.
1476 * NOTE: There is no RotR with immediate because this would always be a RotL
1477 * "imm-mode_size_bits" which can be pre-calculated.
1479 * @param env The transformation environment
1480 * @param op1 The first operator
1481 * @param op2 The second operator
1482 * @return The created ia32 RotR node
1484 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1,
1486 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_RotR);
1492 * Creates an ia32 RotR or RotL (depending on the found pattern).
1494 * @param env The transformation environment
1495 * @return The created ia32 RotL or RotR node
1497 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) {
1498 ir_node *rotate = NULL;
1499 ir_node *op1 = get_Rot_left(node);
1500 ir_node *op2 = get_Rot_right(node);
1502 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1503 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1504 that means we can create a RotR instead of an Add and a RotL */
1507 ir_node *pred = get_Proj_pred(op2);
1509 if (is_ia32_Add(pred)) {
1510 ir_node *pred_pred = get_irn_n(pred, 2);
1511 tarval *tv = get_ia32_Immop_tarval(pred);
1512 ir_mode *mode = get_irn_mode(node);
1513 long bits = get_mode_size_bits(mode);
1515 if (is_Proj(pred_pred)) {
1516 pred_pred = get_Proj_pred(pred_pred);
1519 if (is_ia32_Minus(pred_pred) &&
1520 tarval_is_long(tv) &&
1521 get_tarval_long(tv) == bits)
1523 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1524 rotate = gen_RotR(env, node, op1, get_irn_n(pred_pred, 2));
1531 rotate = gen_RotL(env, node, op1, op2);
1540 * Transforms a Minus node.
1542 * @param env The transformation environment
1543 * @param op The Minus operand
1544 * @return The created ia32 Minus node
1546 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *node, ir_node *op) {
1549 ir_graph *irg = env->irg;
1550 dbg_info *dbg = get_irn_dbg_info(node);
1551 ir_node *block = transform_node(env, get_nodes_block(node));
1552 ir_mode *mode = get_irn_mode(node);
1555 if (mode_is_float(mode)) {
1556 ir_node *new_op = transform_node(env, op);
1558 if (USE_SSE2(env->cg)) {
1559 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1560 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1561 ir_node *nomem = new_rd_NoMem(irg);
1563 res = new_rd_ia32_xEor(dbg, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1565 size = get_mode_size_bits(mode);
1566 name = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1568 set_ia32_am_sc(res, name);
1569 set_ia32_op_type(res, ia32_AddrModeS);
1570 set_ia32_ls_mode(res, mode);
1572 res = new_rd_ia32_vfchs(dbg, irg, block, new_op);
1575 res = gen_unop(env, node, op, new_rd_ia32_Minus);
1578 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1584 * Transforms a Minus node.
1586 * @param env The transformation environment
1587 * @return The created ia32 Minus node
1589 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *node) {
1590 return gen_Minus_ex(env, node, get_Minus_op(node));
1595 * Transforms a Not node.
1597 * @param env The transformation environment
1598 * @return The created ia32 Not node
1600 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *node) {
1601 ir_mode *mode = get_irn_mode(node);
1602 ir_node *op = get_Not_op(node);
1604 assert (! mode_is_float(mode));
1605 return gen_unop(env, node, op, new_rd_ia32_Not);
1611 * Transforms an Abs node.
1613 * @param env The transformation environment
1614 * @return The created ia32 Abs node
1616 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *node) {
1617 ir_node *res, *p_eax, *p_edx;
1618 ir_graph *irg = env->irg;
1619 dbg_info *dbg = get_irn_dbg_info(node);
1620 ir_node *block = transform_node(env, get_nodes_block(node));
1621 ir_mode *mode = get_irn_mode(node);
1622 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1623 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1624 ir_node *nomem = new_NoMem();
1625 ir_node *op = get_Abs_op(node);
1626 ir_node *new_op = transform_node(env, op);
1630 if (mode_is_float(mode)) {
1632 if (USE_SSE2(env->cg)) {
1633 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1635 size = get_mode_size_bits(mode);
1636 name = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1638 set_ia32_am_sc(res, name);
1640 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1642 set_ia32_op_type(res, ia32_AddrModeS);
1643 set_ia32_ls_mode(res, mode);
1646 res = new_rd_ia32_vfabs(dbg, irg, block, new_op);
1647 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1651 res = new_rd_ia32_Cdq(dbg, irg, block, new_op);
1652 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1654 p_eax = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX);
1655 p_edx = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX);
1657 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1658 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1660 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1661 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1670 * Transforms a Load.
1672 * @param env The transformation environment
1673 * @return the created ia32 Load node
1675 static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) {
1676 ir_graph *irg = env->irg;
1677 dbg_info *dbg = get_irn_dbg_info(node);
1678 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1679 ir_mode *mode = get_Load_mode(node);
1680 ir_node *block = transform_node(env, get_nodes_block(node));
1681 ir_node *ptr = get_Load_ptr(node);
1682 ir_node *new_ptr = transform_node(env, ptr);
1683 ir_node *lptr = new_ptr;
1684 ir_node *mem = get_Load_mem(node);
1685 ir_node *new_mem = transform_node(env, mem);
1688 ia32_am_flavour_t am_flav = ia32_am_B;
1689 ir_node *projs[pn_Load_max];
1691 ia32_collect_Projs(node, projs, pn_Load_max);
1694 check for special case: the loaded value might not be used (optimized, volatile, ...)
1695 we add a Proj + Keep for volatile loads and ignore all other cases
1697 if (! get_proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1698 /* add a result proj and a Keep to produce a pseudo use */
1699 ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res);
1700 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), irg, block, 1, &proj);
1703 /* address might be a constant (symconst or absolute address) */
1704 if (is_ia32_Const(new_ptr)) {
1709 if (mode_is_float(mode)) {
1711 if (USE_SSE2(env->cg)) {
1712 new_op = new_rd_ia32_xLoad(dbg, irg, block, lptr, noreg, new_mem);
1714 new_op = new_rd_ia32_vfld(dbg, irg, block, lptr, noreg, new_mem);
1717 new_op = new_rd_ia32_Load(dbg, irg, block, lptr, noreg, new_mem);
1720 /* base is a constant address */
1722 if (get_ia32_op_type(new_ptr) == ia32_SymConst) {
1723 set_ia32_am_sc(new_op, get_ia32_id_cnst(new_ptr));
1724 am_flav = ia32_am_N;
1726 tarval *tv = get_ia32_cnst_tv(new_ptr);
1727 long offs = get_tarval_long(tv);
1729 add_ia32_am_offs_int(new_op, offs);
1730 am_flav = ia32_am_O;
1734 set_ia32_am_support(new_op, ia32_am_Source);
1735 set_ia32_op_type(new_op, ia32_AddrModeS);
1736 set_ia32_am_flavour(new_op, am_flav);
1737 set_ia32_ls_mode(new_op, mode);
1739 /* make sure we are scheduled behind the intial IncSP/Barrier
1740 * to avoid spills being placed before it
1742 if(block == get_irg_start_block(irg)) {
1743 add_irn_dep(new_op, get_irg_frame(irg));
1746 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1754 * Transforms a Store.
1756 * @param env The transformation environment
1757 * @return the created ia32 Store node
1759 static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) {
1760 ir_graph *irg = env->irg;
1761 dbg_info *dbg = get_irn_dbg_info(node);
1762 ir_node *block = transform_node(env, get_nodes_block(node));
1763 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1764 ir_node *ptr = get_Store_ptr(node);
1765 ir_node *new_ptr = transform_node(env, ptr);
1766 ir_node *sptr = new_ptr;
1767 ir_node *val = get_Store_value(node);
1768 ir_node *new_val = transform_node(env, val);
1769 ir_node *mem = get_Store_mem(node);
1770 ir_node *new_mem = transform_node(env, mem);
1771 ir_mode *mode = get_irn_mode(val);
1772 ir_node *sval = new_val;
1775 ia32_am_flavour_t am_flav = ia32_am_B;
1776 ia32_immop_type_t immop = ia32_ImmNone;
1778 if (! mode_is_float(mode)) {
1779 /* in case of storing a const (but not a symconst) -> make it an attribute */
1780 if (is_ia32_Cnst(new_val)) {
1781 switch (get_ia32_op_type(new_val)) {
1783 immop = ia32_ImmConst;
1786 immop = ia32_ImmSymConst;
1789 assert(0 && "unsupported Const type");
1795 /* address might be a constant (symconst or absolute address) */
1796 if (is_ia32_Const(new_ptr)) {
1801 if (mode_is_float(mode)) {
1803 if (USE_SSE2(env->cg)) {
1804 new_op = new_rd_ia32_xStore(dbg, irg, block, sptr, noreg, sval, new_mem);
1807 new_op = new_rd_ia32_vfst(dbg, irg, block, sptr, noreg, sval, new_mem);
1810 else if (get_mode_size_bits(mode) == 8) {
1811 new_op = new_rd_ia32_Store8Bit(dbg, irg, block, sptr, noreg, sval, new_mem);
1814 new_op = new_rd_ia32_Store(dbg, irg, block, sptr, noreg, sval, new_mem);
1817 /* stored const is an immediate value */
1818 if (! mode_is_float(mode) && is_ia32_Cnst(new_val)) {
1819 set_ia32_Immop_attr(new_op, new_val);
1822 /* base is an constant address */
1824 if (get_ia32_op_type(new_ptr) == ia32_SymConst) {
1825 set_ia32_am_sc(new_op, get_ia32_id_cnst(new_ptr));
1826 am_flav = ia32_am_N;
1829 tarval *tv = get_ia32_cnst_tv(new_ptr);
1830 long offs = get_tarval_long(tv);
1832 add_ia32_am_offs_int(new_op, offs);
1833 am_flav = ia32_am_O;
1837 set_ia32_am_support(new_op, ia32_am_Dest);
1838 set_ia32_op_type(new_op, ia32_AddrModeD);
1839 set_ia32_am_flavour(new_op, am_flav);
1840 set_ia32_ls_mode(new_op, mode);
1841 set_ia32_immop_type(new_op, immop);
1843 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1851 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1853 * @param env The transformation environment
1854 * @return The transformed node.
1856 static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) {
1857 ir_graph *irg = env->irg;
1858 dbg_info *dbg = get_irn_dbg_info(node);
1859 ir_node *block = transform_node(env, get_nodes_block(node));
1860 ir_node *sel = get_Cond_selector(node);
1861 ir_mode *sel_mode = get_irn_mode(sel);
1862 ir_node *res = NULL;
1863 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1864 ir_node *cnst, *expr;
1866 if (is_Proj(sel) && sel_mode == mode_b) {
1867 ir_node *nomem = new_NoMem();
1868 ir_node *pred = get_Proj_pred(sel);
1869 ir_node *cmp_a = get_Cmp_left(pred);
1870 ir_node *new_cmp_a = transform_node(env, cmp_a);
1871 ir_node *cmp_b = get_Cmp_right(pred);
1872 ir_node *new_cmp_b = transform_node(env, cmp_b);
1873 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1875 int pnc = get_Proj_proj(sel);
1876 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1877 pnc |= ia32_pn_Cmp_Unsigned;
1880 /* check if we can use a CondJmp with immediate */
1881 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1882 expr = get_expr_op(new_cmp_a, new_cmp_b);
1884 if (cnst != NULL && expr != NULL) {
1885 /* immop has to be the right operand, we might need to flip pnc */
1886 if(cnst != new_cmp_b) {
1887 pnc = get_inversed_pnc(pnc);
1890 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1891 if (get_ia32_op_type(cnst) == ia32_Const &&
1892 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1894 /* a Cmp A =/!= 0 */
1895 ir_node *op1 = expr;
1896 ir_node *op2 = expr;
1897 const char *cnst = NULL;
1899 /* check, if expr is an only once used And operation */
1900 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1901 op1 = get_irn_n(expr, 2);
1902 op2 = get_irn_n(expr, 3);
1904 cnst = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr)) ? get_ia32_cnst(expr) : NULL;
1906 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1907 set_ia32_pncode(res, pnc);
1910 copy_ia32_Immop_attr(res, expr);
1913 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1918 if (mode_is_float(cmp_mode)) {
1920 if (USE_SSE2(env->cg)) {
1921 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1922 set_ia32_ls_mode(res, cmp_mode);
1928 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1930 set_ia32_Immop_attr(res, cnst);
1933 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1935 if (mode_is_float(cmp_mode)) {
1937 if (USE_SSE2(env->cg)) {
1938 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1939 set_ia32_ls_mode(res, cmp_mode);
1942 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1943 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1944 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1948 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1949 set_ia32_commutative(res);
1953 set_ia32_pncode(res, pnc);
1954 // Matze: disabled for now, because the default collect_spills_walker
1955 // is not able to detect the mode of the spilled value
1956 // moreover, the lea optimize phase freely exchanges left/right
1957 // without updating the pnc
1958 //set_ia32_am_support(res, ia32_am_Source);
1961 /* determine the smallest switch case value */
1962 int switch_min = INT_MAX;
1963 const ir_edge_t *edge;
1964 ir_node *new_sel = transform_node(env, sel);
1966 foreach_out_edge(node, edge) {
1967 int pn = get_Proj_proj(get_edge_src_irn(edge));
1968 switch_min = pn < switch_min ? pn : switch_min;
1972 /* if smallest switch case is not 0 we need an additional sub */
1973 res = new_rd_ia32_Lea(dbg, irg, block, new_sel, noreg);
1974 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1975 add_ia32_am_offs_int(res, -switch_min);
1976 set_ia32_am_flavour(res, ia32_am_OB);
1977 set_ia32_am_support(res, ia32_am_Source);
1978 set_ia32_op_type(res, ia32_AddrModeS);
1981 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : new_sel, mode_T);
1982 set_ia32_pncode(res, get_Cond_defaultProj(node));
1985 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1992 * Transforms a CopyB node.
1994 * @param env The transformation environment
1995 * @return The transformed node.
1997 static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) {
1998 ir_node *res = NULL;
1999 ir_graph *irg = env->irg;
2000 dbg_info *dbg = get_irn_dbg_info(node);
2001 ir_node *block = transform_node(env, get_nodes_block(node));
2002 ir_node *src = get_CopyB_src(node);
2003 ir_node *new_src = transform_node(env, src);
2004 ir_node *dst = get_CopyB_dst(node);
2005 ir_node *new_dst = transform_node(env, dst);
2006 ir_node *mem = get_CopyB_mem(node);
2007 ir_node *new_mem = transform_node(env, mem);
2008 int size = get_type_size_bytes(get_CopyB_type(node));
2009 ir_mode *dst_mode = get_irn_mode(dst);
2010 ir_mode *src_mode = get_irn_mode(src);
2014 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2015 /* then we need the size explicitly in ECX. */
2016 if (size >= 32 * 4) {
2017 rem = size & 0x3; /* size % 4 */
2020 res = new_rd_ia32_Const(dbg, irg, block);
2021 add_irn_dep(res, be_abi_get_start_barrier(env->cg->birg->abi));
2022 set_ia32_op_type(res, ia32_Const);
2023 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
2025 res = new_rd_ia32_CopyB(dbg, irg, block, new_dst, new_src, res, new_mem);
2026 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
2028 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
2029 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
2030 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
2031 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
2032 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
2035 res = new_rd_ia32_CopyB_i(dbg, irg, block, new_dst, new_src, new_mem);
2036 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
2037 set_ia32_immop_type(res, ia32_ImmConst);
2039 /* ok: now attach Proj's because movsd will destroy esi and edi */
2040 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
2041 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
2042 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
2045 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2053 * Transforms a Mux node into CMov.
2055 * @param env The transformation environment
2056 * @return The transformed node.
2058 static ir_node *gen_Mux(ia32_transform_env_t *env, ir_node *node) {
2059 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
2060 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
2062 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2068 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
2069 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
2070 ir_node *psi_default);
2073 * Transforms a Psi node into CMov.
2075 * @param env The transformation environment
2076 * @return The transformed node.
2078 static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) {
2079 ia32_code_gen_t *cg = env->cg;
2080 ir_graph *irg = env->irg;
2081 dbg_info *dbg = get_irn_dbg_info(node);
2082 ir_mode *mode = get_irn_mode(node);
2083 ir_node *block = transform_node(env, get_nodes_block(node));
2084 ir_node *cmp_proj = get_Mux_sel(node);
2085 ir_node *psi_true = get_Psi_val(node, 0);
2086 ir_node *psi_default = get_Psi_default(node);
2087 ir_node *new_psi_true = transform_node(env, psi_true);
2088 ir_node *new_psi_default = transform_node(env, psi_default);
2089 ir_node *noreg = ia32_new_NoReg_gp(cg);
2090 ir_node *nomem = new_rd_NoMem(irg);
2091 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
2092 ir_node *new_cmp_a, *new_cmp_b;
2096 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
2098 cmp = get_Proj_pred(cmp_proj);
2099 cmp_a = get_Cmp_left(cmp);
2100 cmp_b = get_Cmp_right(cmp);
2101 cmp_mode = get_irn_mode(cmp_a);
2102 new_cmp_a = transform_node(env, cmp_a);
2103 new_cmp_b = transform_node(env, cmp_b);
2105 pnc = get_Proj_proj(cmp_proj);
2106 if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2107 pnc |= ia32_pn_Cmp_Unsigned;
2110 if (mode_is_float(mode)) {
2111 /* floating point psi */
2114 /* 1st case: compare operands are float too */
2116 /* psi(cmp(a, b), t, f) can be done as: */
2117 /* tmp = cmp a, b */
2118 /* tmp2 = t and tmp */
2119 /* tmp3 = f and not tmp */
2120 /* res = tmp2 or tmp3 */
2122 /* in case the compare operands are int, we move them into xmm register */
2123 if (! mode_is_float(get_irn_mode(cmp_a))) {
2124 new_cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_a, node, mode_D);
2125 new_cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_b, node, mode_D);
2127 pnc |= 8; /* transform integer compare to fp compare */
2130 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2131 set_ia32_pncode(new_op, pnc);
2132 set_ia32_am_support(new_op, ia32_am_Source);
2133 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2135 and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2136 set_ia32_am_support(and1, ia32_am_None);
2137 set_ia32_commutative(and1);
2138 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2140 and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2141 set_ia32_am_support(and2, ia32_am_None);
2142 set_ia32_commutative(and2);
2143 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2145 new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
2146 set_ia32_am_support(new_op, ia32_am_None);
2147 set_ia32_commutative(new_op);
2148 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2152 new_op = new_rd_ia32_vfCMov(dbg, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2153 set_ia32_pncode(new_op, pnc);
2154 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2159 construct_binop_func *set_func = NULL;
2160 cmov_func_t *cmov_func = NULL;
2162 if (mode_is_float(get_irn_mode(cmp_a))) {
2163 /* 1st case: compare operands are floats */
2168 set_func = new_rd_ia32_xCmpSet;
2169 cmov_func = new_rd_ia32_xCmpCMov;
2173 set_func = new_rd_ia32_vfCmpSet;
2174 cmov_func = new_rd_ia32_vfCmpCMov;
2177 pnc &= ~0x8; /* fp compare -> int compare */
2180 /* 2nd case: compare operand are integer too */
2181 set_func = new_rd_ia32_CmpSet;
2182 cmov_func = new_rd_ia32_CmpCMov;
2185 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2186 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2187 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2188 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2189 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, new_cmp_a);
2190 set_ia32_pncode(new_op, pnc);
2192 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2193 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2194 /* we invert condition and set default to 0 */
2195 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, new_cmp_a);
2196 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2199 /* otherwise: use CMOVcc */
2200 new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2201 set_ia32_pncode(new_op, pnc);
2204 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2207 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2208 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2209 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2210 set_ia32_pncode(new_op, pnc);
2211 set_ia32_am_support(new_op, ia32_am_Source);
2213 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2214 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2215 /* we invert condition and set default to 0 */
2216 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2217 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2218 set_ia32_am_support(new_op, ia32_am_Source);
2221 /* otherwise: use CMOVcc */
2222 new_op = cmov_func(dbg, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2223 set_ia32_pncode(new_op, pnc);
2224 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2234 * Following conversion rules apply:
2238 * 1) n bit -> m bit n > m (downscale)
2240 * 2) n bit -> m bit n == m (sign change)
2242 * 3) n bit -> m bit n < m (upscale)
2243 * a) source is signed: movsx
2244 * b) source is unsigned: and with lower bits sets
2248 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2252 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2256 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2257 * x87 is mode_E internally, conversions happen only at load and store
2258 * in non-strict semantic
2262 * Create a conversion from x87 state register to general purpose.
2264 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) {
2265 ia32_code_gen_t *cg = env->cg;
2266 ir_graph *irg = env->irg;
2267 dbg_info *dbg = get_irn_dbg_info(node);
2268 ir_node *block = transform_node(env, get_nodes_block(node));
2269 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2270 ir_node *op = get_Conv_op(node);
2271 ir_node *new_op = transform_node(env, op);
2272 ir_node *fist, *load;
2275 fist = new_rd_ia32_vfist(dbg, irg, block, get_irg_frame(irg), noreg, new_op, new_NoMem());
2277 set_ia32_use_frame(fist);
2278 set_ia32_am_support(fist, ia32_am_Dest);
2279 set_ia32_op_type(fist, ia32_AddrModeD);
2280 set_ia32_am_flavour(fist, ia32_am_B);
2281 set_ia32_ls_mode(fist, mode_Iu);
2282 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2285 load = new_rd_ia32_Load(dbg, irg, block, get_irg_frame(irg), noreg, fist);
2287 set_ia32_use_frame(load);
2288 set_ia32_am_support(load, ia32_am_Source);
2289 set_ia32_op_type(load, ia32_AddrModeS);
2290 set_ia32_am_flavour(load, ia32_am_B);
2291 set_ia32_ls_mode(load, mode_Iu);
2292 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2294 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2298 * Create a conversion from general purpose to x87 register
2300 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mode *src_mode) {
2301 ia32_code_gen_t *cg = env->cg;
2302 ir_graph *irg = env->irg;
2303 dbg_info *dbg = get_irn_dbg_info(node);
2304 ir_mode *mode = get_irn_mode(node);
2305 ir_node *block = transform_node(env, get_nodes_block(node));
2306 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2307 ir_node *nomem = new_NoMem();
2308 ir_node *op = get_Conv_op(node);
2309 ir_node *new_op = transform_node(env, op);
2310 ir_node *fild, *store;
2313 /* first convert to 32 bit if necessary */
2314 src_bits = get_mode_size_bits(src_mode);
2315 if (src_bits == 8) {
2316 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, new_op, nomem);
2317 set_ia32_am_support(new_op, ia32_am_Source);
2318 set_ia32_ls_mode(new_op, src_mode);
2319 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2320 } else if (src_bits < 32) {
2321 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, new_op, nomem);
2322 set_ia32_am_support(new_op, ia32_am_Source);
2323 set_ia32_ls_mode(new_op, src_mode);
2324 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2328 store = new_rd_ia32_Store(dbg, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2330 set_ia32_use_frame(store);
2331 set_ia32_am_support(store, ia32_am_Dest);
2332 set_ia32_op_type(store, ia32_AddrModeD);
2333 set_ia32_am_flavour(store, ia32_am_OB);
2334 set_ia32_ls_mode(store, mode_Iu);
2337 fild = new_rd_ia32_vfild(dbg, irg, block, get_irg_frame(irg), noreg, store);
2339 set_ia32_use_frame(fild);
2340 set_ia32_am_support(fild, ia32_am_Source);
2341 set_ia32_op_type(fild, ia32_AddrModeS);
2342 set_ia32_am_flavour(fild, ia32_am_OB);
2343 set_ia32_ls_mode(fild, mode);
2345 return new_r_Proj(irg, block, fild, mode_F, pn_ia32_vfild_res);
2349 * Transforms a Conv node.
2351 * @param env The transformation environment
2352 * @return The created ia32 Conv node
2354 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) {
2355 ir_graph *irg = env->irg;
2356 dbg_info *dbg = get_irn_dbg_info(node);
2357 ir_node *op = get_Conv_op(node);
2358 ir_mode *src_mode = get_irn_mode(op);
2359 ir_mode *tgt_mode = get_irn_mode(node);
2360 int src_bits = get_mode_size_bits(src_mode);
2361 int tgt_bits = get_mode_size_bits(tgt_mode);
2362 ir_node *block = transform_node(env, get_nodes_block(node));
2364 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2365 ir_node *nomem = new_rd_NoMem(irg);
2366 ir_node *new_op = transform_node(env, op);
2367 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
2369 if (src_mode == tgt_mode) {
2370 /* this should be optimized already, but who knows... */
2371 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2372 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
2376 if (mode_is_float(src_mode)) {
2377 /* we convert from float ... */
2378 if (mode_is_float(tgt_mode)) {
2380 if (USE_SSE2(env->cg)) {
2381 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
2382 res = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, new_op, nomem);
2383 set_ia32_ls_mode(res, tgt_mode);
2385 // Matze: TODO what about strict convs?
2386 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
2391 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
2392 if (USE_SSE2(env->cg)) {
2393 res = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, new_op, nomem);
2394 set_ia32_ls_mode(res, src_mode);
2396 return gen_x87_fp_to_gp(env, node);
2400 /* we convert from int ... */
2401 if (mode_is_float(tgt_mode)) {
2404 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
2405 if (USE_SSE2(env->cg)) {
2406 res = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, new_op, nomem);
2407 set_ia32_ls_mode(res, tgt_mode);
2408 if(src_bits == 32) {
2409 set_ia32_am_support(res, ia32_am_Source);
2412 return gen_x87_gp_to_fp(env, node, src_mode);
2416 ir_mode *smaller_mode;
2419 if (src_bits == tgt_bits) {
2420 DB((mod, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2424 if(src_bits < tgt_bits) {
2425 smaller_mode = src_mode;
2426 smaller_bits = src_bits;
2428 smaller_mode = tgt_mode;
2429 smaller_bits = tgt_bits;
2432 // The following is not correct, we can't change the mode,
2433 // maybe others are using the load too
2434 // better move this to a separate phase!
2437 if(is_Proj(new_op)) {
2438 /* load operations do already sign/zero extend, so we have
2439 * nothing left to do */
2440 ir_node *pred = get_Proj_pred(new_op);
2441 if(is_ia32_Load(pred)) {
2442 set_ia32_ls_mode(pred, smaller_mode);
2448 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2449 if (smaller_bits == 8) {
2450 res = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, new_op, nomem);
2451 set_ia32_ls_mode(res, smaller_mode);
2453 res = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, new_op, nomem);
2454 set_ia32_ls_mode(res, smaller_mode);
2456 set_ia32_am_support(res, ia32_am_Source);
2460 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2467 /********************************************
2470 * | |__ ___ _ __ ___ __| | ___ ___
2471 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2472 * | |_) | __/ | | | (_) | (_| | __/\__ \
2473 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2475 ********************************************/
2477 static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) {
2478 ir_node *new_op = NULL;
2479 ir_graph *irg = env->irg;
2480 dbg_info *dbg = get_irn_dbg_info(node);
2481 ir_node *block = transform_node(env, get_nodes_block(node));
2482 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2483 ir_node *nomem = new_rd_NoMem(env->irg);
2484 ir_node *ptr = get_irn_n(node, 0);
2485 ir_node *new_ptr = transform_node(env, ptr);
2486 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2487 ir_mode *load_mode = get_irn_mode(node);
2491 if (mode_is_float(load_mode)) {
2493 if (USE_SSE2(env->cg)) {
2494 new_op = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, nomem);
2495 pn_res = pn_ia32_xLoad_res;
2497 new_op = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, nomem);
2498 pn_res = pn_ia32_vfld_res;
2503 new_op = new_rd_ia32_Load(dbg, irg, block, new_ptr, noreg, nomem);
2504 proj_mode = mode_Iu;
2505 pn_res = pn_ia32_Load_res;
2508 set_ia32_frame_ent(new_op, ent);
2509 set_ia32_use_frame(new_op);
2511 set_ia32_am_support(new_op, ia32_am_Source);
2512 set_ia32_op_type(new_op, ia32_AddrModeS);
2513 set_ia32_am_flavour(new_op, ia32_am_B);
2514 set_ia32_ls_mode(new_op, load_mode);
2515 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2517 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2519 return new_rd_Proj(dbg, irg, block, new_op, proj_mode, pn_res);
2523 * Transforms a FrameAddr into an ia32 Add.
2525 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) {
2526 ir_graph *irg = env->irg;
2527 dbg_info *dbg = get_irn_dbg_info(node);
2528 ir_node *block = transform_node(env, get_nodes_block(node));
2529 ir_node *op = get_irn_n(node, 0);
2530 ir_node *new_op = transform_node(env, op);
2532 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2534 res = new_rd_ia32_Lea(dbg, irg, block, new_op, noreg);
2535 set_ia32_frame_ent(res, arch_get_frame_entity(env->cg->arch_env, node));
2536 set_ia32_am_support(res, ia32_am_Full);
2537 set_ia32_use_frame(res);
2538 set_ia32_am_flavour(res, ia32_am_OB);
2540 //set_ia32_immop_type(res, ia32_ImmConst);
2541 //set_ia32_commutative(res);
2543 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2549 * Transforms a FrameLoad into an ia32 Load.
2551 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) {
2552 ir_node *new_op = NULL;
2553 ir_graph *irg = env->irg;
2554 dbg_info *dbg = get_irn_dbg_info(node);
2555 ir_node *block = transform_node(env, get_nodes_block(node));
2556 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2557 ir_node *mem = get_irn_n(node, 0);
2558 ir_node *ptr = get_irn_n(node, 1);
2559 ir_node *new_mem = transform_node(env, mem);
2560 ir_node *new_ptr = transform_node(env, ptr);
2561 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2562 ir_mode *mode = get_type_mode(get_entity_type(ent));
2563 ir_node *projs[pn_Load_max];
2565 ia32_collect_Projs(node, projs, pn_Load_max);
2567 if (mode_is_float(mode)) {
2569 if (USE_SSE2(env->cg)) {
2570 new_op = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, new_mem);
2573 new_op = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, new_mem);
2577 new_op = new_rd_ia32_Load(dbg, irg, block, new_ptr, noreg, new_mem);
2580 set_ia32_frame_ent(new_op, ent);
2581 set_ia32_use_frame(new_op);
2583 set_ia32_am_support(new_op, ia32_am_Source);
2584 set_ia32_op_type(new_op, ia32_AddrModeS);
2585 set_ia32_am_flavour(new_op, ia32_am_B);
2586 set_ia32_ls_mode(new_op, mode);
2588 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2595 * Transforms a FrameStore into an ia32 Store.
2597 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) {
2598 ir_node *new_op = NULL;
2599 ir_graph *irg = env->irg;
2600 dbg_info *dbg = get_irn_dbg_info(node);
2601 ir_node *block = transform_node(env, get_nodes_block(node));
2602 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2603 ir_node *mem = get_irn_n(node, 0);
2604 ir_node *ptr = get_irn_n(node, 1);
2605 ir_node *val = get_irn_n(node, 2);
2606 ir_node *new_mem = transform_node(env, mem);
2607 ir_node *new_ptr = transform_node(env, ptr);
2608 ir_node *new_val = transform_node(env, val);
2609 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2610 ir_mode *mode = get_irn_mode(val);
2612 if (mode_is_float(mode)) {
2614 if (USE_SSE2(env->cg)) {
2615 new_op = new_rd_ia32_xStore(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2618 new_op = new_rd_ia32_vfst(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2621 else if (get_mode_size_bits(mode) == 8) {
2622 new_op = new_rd_ia32_Store8Bit(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2625 new_op = new_rd_ia32_Store(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2628 set_ia32_frame_ent(new_op, ent);
2629 set_ia32_use_frame(new_op);
2631 set_ia32_am_support(new_op, ia32_am_Dest);
2632 set_ia32_op_type(new_op, ia32_AddrModeD);
2633 set_ia32_am_flavour(new_op, ia32_am_B);
2634 set_ia32_ls_mode(new_op, mode);
2636 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2642 * In case SSE is used we need to copy the result from FPU TOS.
2644 static ir_node *gen_be_Call(ia32_transform_env_t *env, ir_node *node) {
2645 ir_graph *irg = env->irg;
2646 dbg_info *dbg = get_irn_dbg_info(node);
2647 ir_node *block = transform_node(env, get_nodes_block(node));
2648 ir_node *call_res = get_proj_for_pn(node, pn_be_Call_first_res);
2649 ir_node *call_mem = get_proj_for_pn(node, pn_be_Call_M_regular);
2651 ir_node *nomem = new_NoMem();
2652 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2654 if (! call_res || ! USE_SSE2(env->cg)) {
2655 return duplicate_node(env, node);
2658 mode = get_irn_mode(call_res);
2660 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
2661 if (call_mem == NULL)
2662 call_mem = new_rd_Proj(dbg, irg, block, node, mode_M, pn_be_Call_M_regular);
2664 if (mode_is_float(mode)) {
2665 // Matze: TODO, fix this for new transform code...
2668 /* store st(0) onto stack */
2669 ir_node *frame = get_irg_frame(irg);
2670 ir_node *fstp = new_rd_ia32_GetST0(dbg, irg, block, frame, noreg, nomem);
2671 ir_entity *ent = frame_alloc_area(get_irg_frame_type(irg), get_mode_size_bytes(mode), 16, 0);
2672 ir_node *sse_load, *p, *bad, *keep;
2677 set_ia32_ls_mode(fstp, mode);
2678 set_ia32_op_type(fstp, ia32_AddrModeD);
2679 set_ia32_use_frame(fstp);
2680 set_ia32_frame_ent(fstp, ent);
2681 set_ia32_am_flavour(fstp, ia32_am_B);
2682 set_ia32_am_support(fstp, ia32_am_Dest);
2684 /* load into SSE register */
2685 sse_load = new_rd_ia32_xLoad(dbg, irg, block, frame, ia32_new_NoReg_gp(env->cg), fstp);
2686 set_ia32_ls_mode(sse_load, mode);
2687 set_ia32_op_type(sse_load, ia32_AddrModeS);
2688 set_ia32_use_frame(sse_load);
2689 set_ia32_frame_ent(sse_load, ent);
2690 set_ia32_am_flavour(sse_load, ia32_am_B);
2691 set_ia32_am_support(sse_load, ia32_am_Source);
2692 mproj = new_rd_Proj(dbg, irg, block, sse_load, mode_M, pn_ia32_xLoad_M);
2693 sse_load = new_rd_Proj(dbg, irg, block, sse_load, mode, pn_ia32_xLoad_res);
2695 /* reroute all users of the result proj to the sse load */
2696 edges_reroute(call_res, sse_load, irg);
2697 edges_reroute_kind(call_res, sse_load, EDGE_KIND_DEP, irg);
2699 /* reroute all users of the old call memory to the sse load memory */
2700 edges_reroute(call_mem, mproj, irg);
2701 edges_reroute_kind(call_mem, mproj, EDGE_KIND_DEP, irg);
2703 /* now, we can set the old call mem as input of GetST0 */
2704 set_irn_n(fstp, 1, call_mem);
2706 /* now: create new Keep whith all former ins and one additional in - the result Proj */
2708 /* get a Proj representing a caller save register */
2709 p = get_proj_for_pn(node, pn_be_Call_first_res + 1);
2710 assert(is_Proj(p) && "Proj expected.");
2712 /* user of the the proj is the Keep */
2713 p = get_edge_src_irn(get_irn_out_edge_first(p));
2714 assert(be_is_Keep(p) && "Keep expected.");
2716 /* copy in array of the old keep and set the result proj as additional in */
2717 keep_arity = get_irn_arity(p) + 1;
2718 NEW_ARR_A(ir_node *, in_keep, keep_arity);
2719 in_keep[keep_arity - 1] = call_res;
2720 for (i = 0; i < keep_arity - 1; ++i)
2721 in_keep[i] = get_irn_n(p, i);
2723 /* create new keep and set the in class requirements properly */
2724 keep = be_new_Keep(NULL, irg, block, keep_arity, in_keep);
2725 for(i = 0; i < keep_arity; ++i) {
2726 const arch_register_class_t *cls = arch_get_irn_reg_class(env->cg->arch_env, in_keep[i], -1);
2727 be_node_set_reg_class(keep, i, cls);
2730 /* kill the old keep */
2731 bad = get_irg_bad(irg);
2732 for (i = 0; i < keep_arity - 1; i++)
2733 set_irn_n(p, i, bad);
2734 remove_End_keepalive(get_irg_end(irg), p);
2737 return duplicate_node(env, node);
2741 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2743 static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
2744 ir_graph *irg = env->irg;
2747 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2748 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2749 ir_entity *ent = get_irg_entity(irg);
2750 ir_type *tp = get_entity_type(ent);
2753 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2754 ir_node *new_barrier, *new_frame, *new_ret_val, *new_ret_mem;
2756 int pn_ret_val, pn_ret_mem, arity, i;
2758 assert(ret_val != NULL);
2759 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env->cg)) {
2760 return duplicate_node(env, node);
2763 res_type = get_method_res_type(tp, 0);
2765 if (!is_Primitive_type(res_type)) {
2766 return duplicate_node(env, node);
2769 mode = get_type_mode(res_type);
2770 if (!mode_is_float(mode)) {
2771 return duplicate_node(env, node);
2774 assert(get_method_n_ress(tp) == 1);
2777 pn_ret_val = get_Proj_proj(ret_val);
2778 pn_ret_mem = get_Proj_proj(ret_mem);
2780 /* get the Barrier */
2781 barrier = get_Proj_pred(ret_val);
2783 /* get result input of the Barrier */
2784 ret_val = get_irn_n(barrier, pn_ret_val);
2785 new_ret_val = transform_node(env, ret_val);
2787 /* get memory input of the Barrier */
2788 ret_mem = get_irn_n(barrier, pn_ret_mem);
2789 new_ret_mem = transform_node(env, ret_mem);
2791 frame = get_irg_frame(irg);
2792 new_frame = transform_node(env, frame);
2794 dbg = get_irn_dbg_info(barrier);
2795 block = transform_node(env, get_nodes_block(barrier));
2797 /* store xmm0 onto stack */
2798 sse_store = new_rd_ia32_xStoreSimple(dbg, irg, block, new_frame, new_ret_val, new_ret_mem);
2799 set_ia32_ls_mode(sse_store, mode);
2800 set_ia32_op_type(sse_store, ia32_AddrModeD);
2801 set_ia32_use_frame(sse_store);
2802 set_ia32_am_flavour(sse_store, ia32_am_B);
2803 set_ia32_am_support(sse_store, ia32_am_Dest);
2806 fld = new_rd_ia32_SetST0(dbg, irg, block, new_frame, sse_store);
2807 set_ia32_ls_mode(fld, mode);
2808 set_ia32_op_type(fld, ia32_AddrModeS);
2809 set_ia32_use_frame(fld);
2810 set_ia32_am_flavour(fld, ia32_am_B);
2811 set_ia32_am_support(fld, ia32_am_Source);
2813 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
2814 fld = new_r_Proj(irg, block, fld, mode_D, pn_ia32_SetST0_res);
2815 arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2817 /* create a new barrier */
2818 arity = get_irn_arity(barrier);
2819 in = alloca(arity * sizeof(in[0]));
2820 for(i = 0; i < arity; ++i) {
2822 if(i == pn_ret_val) {
2824 } else if(i == pn_ret_mem) {
2827 ir_node *in = get_irn_n(barrier, i);
2828 new_in = transform_node(env, in);
2833 new_barrier = new_ir_node(dbg, irg, block,
2834 get_irn_op(barrier), get_irn_mode(barrier),
2836 copy_node_attr(barrier, new_barrier);
2837 duplicate_deps(env, barrier, new_barrier);
2838 set_new_node(barrier, new_barrier);
2839 mark_irn_visited(barrier);
2841 /* transform normally */
2842 return duplicate_node(env, node);
2846 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2848 static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
2850 ir_graph *irg = env->irg;
2851 dbg_info *dbg = get_irn_dbg_info(node);
2852 ir_node *block = transform_node(env, get_nodes_block(node));
2853 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
2854 ir_node *new_sz = transform_node(env, sz);
2855 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
2856 ir_node *new_sp = transform_node(env, sp);
2858 new_op = new_rd_ia32_AddSP(dbg, irg, block, new_sp, new_sz);
2859 fold_immediate(env, new_op, 0, 1);
2861 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2867 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
2869 static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
2871 ir_graph *irg = env->irg;
2872 dbg_info *dbg = get_irn_dbg_info(node);
2873 ir_node *block = transform_node(env, get_nodes_block(node));
2874 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
2875 ir_node *new_sz = transform_node(env, sz);
2876 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
2877 ir_node *new_sp = transform_node(env, sp);
2879 new_op = new_rd_ia32_SubSP(dbg, irg, block, new_sp, new_sz);
2880 fold_immediate(env, new_op, 0, 1);
2882 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2888 * This function just sets the register for the Unknown node
2889 * as this is not done during register allocation because Unknown
2890 * is an "ignore" node.
2892 static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) {
2893 ir_mode *mode = get_irn_mode(node);
2895 if (mode_is_float(mode)) {
2896 if (USE_SSE2(env->cg))
2897 return ia32_new_Unknown_xmm(env->cg);
2899 return ia32_new_Unknown_vfp(env->cg);
2900 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
2901 return ia32_new_Unknown_gp(env->cg);
2903 assert(0 && "unsupported Unknown-Mode");
2910 * Change some phi modes
2912 static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
2913 ir_graph *irg = env->irg;
2914 dbg_info *dbg = get_irn_dbg_info(node);
2915 ir_mode *mode = get_irn_mode(node);
2916 ir_node *block = transform_node(env, get_nodes_block(node));
2920 if(mode_is_int(mode) || mode_is_reference(mode)) {
2921 // we shouldn't have any 64bit stuff around anymore
2922 assert(get_mode_size_bits(mode) <= 32);
2923 // all integer operations are on 32bit registers now
2925 } else if(mode_is_float(mode)) {
2926 assert(mode == mode_D || mode == mode_F);
2927 // all float operations are on mode_D registers
2931 /* phi nodes allow loops, so we use the old arguments for now
2932 * and fix this later */
2933 phi = new_ir_node(dbg, irg, block, op_Phi, mode, get_irn_arity(node),
2934 get_irn_in(node) + 1);
2935 copy_node_attr(node, phi);
2936 duplicate_deps(env, node, phi);
2938 set_new_node(node, phi);
2940 /* put the preds in the worklist */
2941 arity = get_irn_arity(node);
2942 for(i = 0; i < arity; ++i) {
2943 ir_node *pred = get_irn_n(node, i);
2944 pdeq_putr(env->worklist, pred);
2950 /**********************************************************************
2953 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2954 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2955 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2956 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2958 **********************************************************************/
2960 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2962 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2965 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2966 ir_node *val, ir_node *mem);
2969 * Transforms a lowered Load into a "real" one.
2971 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) {
2972 ir_graph *irg = env->irg;
2973 dbg_info *dbg = get_irn_dbg_info(node);
2974 ir_node *block = transform_node(env, get_nodes_block(node));
2975 ir_mode *mode = get_ia32_ls_mode(node);
2977 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2978 ir_node *ptr = get_irn_n(node, 0);
2979 ir_node *mem = get_irn_n(node, 1);
2980 ir_node *new_ptr = transform_node(env, ptr);
2981 ir_node *new_mem = transform_node(env, mem);
2984 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2985 lowering we have x87 nodes, so we need to enforce simulation.
2987 if (mode_is_float(mode)) {
2989 if (fp_unit == fp_x87)
2993 new_op = func(dbg, irg, block, new_ptr, noreg, new_mem);
2995 set_ia32_am_support(new_op, ia32_am_Source);
2996 set_ia32_op_type(new_op, ia32_AddrModeS);
2997 set_ia32_am_flavour(new_op, ia32_am_OB);
2998 set_ia32_am_offs_int(new_op, 0);
2999 set_ia32_am_scale(new_op, 1);
3000 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3001 if(is_ia32_am_sc_sign(node))
3002 set_ia32_am_sc_sign(new_op);
3003 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3004 if(is_ia32_use_frame(node)) {
3005 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3006 set_ia32_use_frame(new_op);
3009 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3015 * Transforms a lowered Store into a "real" one.
3017 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) {
3018 ir_graph *irg = env->irg;
3019 dbg_info *dbg = get_irn_dbg_info(node);
3020 ir_node *block = transform_node(env, get_nodes_block(node));
3021 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3022 ir_mode *mode = get_ia32_ls_mode(node);
3025 ia32_am_flavour_t am_flav = ia32_B;
3026 ir_node *ptr = get_irn_n(node, 0);
3027 ir_node *val = get_irn_n(node, 1);
3028 ir_node *mem = get_irn_n(node, 2);
3029 ir_node *new_ptr = transform_node(env, ptr);
3030 ir_node *new_val = transform_node(env, val);
3031 ir_node *new_mem = transform_node(env, mem);
3034 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3035 lowering we have x87 nodes, so we need to enforce simulation.
3037 if (mode_is_float(mode)) {
3039 if (fp_unit == fp_x87)
3043 new_op = func(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
3045 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3047 add_ia32_am_offs_int(new_op, am_offs);
3050 set_ia32_am_support(new_op, ia32_am_Dest);
3051 set_ia32_op_type(new_op, ia32_AddrModeD);
3052 set_ia32_am_flavour(new_op, am_flav);
3053 set_ia32_ls_mode(new_op, mode);
3054 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3055 set_ia32_use_frame(new_op);
3057 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3064 * Transforms an ia32_l_XXX into a "real" XXX node
3066 * @param env The transformation environment
3067 * @return the created ia32 XXX node
3069 #define GEN_LOWERED_OP(op) \
3070 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
3071 ir_mode *mode = get_irn_mode(node); \
3072 if (mode_is_float(mode)) \
3074 return gen_binop(env, node, get_binop_left(node), \
3075 get_binop_right(node), new_rd_ia32_##op); \
3078 #define GEN_LOWERED_x87_OP(op) \
3079 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
3081 FORCE_x87(env->cg); \
3082 new_op = gen_binop_float(env, node, get_binop_left(node), \
3083 get_binop_right(node), new_rd_ia32_##op); \
3087 #define GEN_LOWERED_UNOP(op) \
3088 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
3089 return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \
3092 #define GEN_LOWERED_SHIFT_OP(op) \
3093 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
3094 return gen_shift_binop(env, node, get_binop_left(node), \
3095 get_binop_right(node), new_rd_ia32_##op); \
3098 #define GEN_LOWERED_LOAD(op, fp_unit) \
3099 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
3100 return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \
3103 #define GEN_LOWERED_STORE(op, fp_unit) \
3104 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
3105 return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \
3108 GEN_LOWERED_OP(AddC)
3110 GEN_LOWERED_OP(SubC)
3114 GEN_LOWERED_x87_OP(vfprem)
3115 GEN_LOWERED_x87_OP(vfmul)
3116 GEN_LOWERED_x87_OP(vfsub)
3118 GEN_LOWERED_UNOP(Minus)
3120 GEN_LOWERED_LOAD(vfild, fp_x87)
3121 GEN_LOWERED_LOAD(Load, fp_none)
3122 GEN_LOWERED_STORE(vfist, fp_x87)
3123 GEN_LOWERED_STORE(Store, fp_none)
3125 static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
3126 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3127 ir_graph *irg = env->irg;
3128 dbg_info *dbg = get_irn_dbg_info(node);
3129 ir_node *block = transform_node(env, get_nodes_block(node));
3130 ir_node *left = get_binop_left(node);
3131 ir_node *right = get_binop_right(node);
3132 ir_node *new_left = transform_node(env, left);
3133 ir_node *new_right = transform_node(env, right);
3136 vfdiv = new_rd_ia32_vfdiv(dbg, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3137 clear_ia32_commutative(vfdiv);
3138 set_ia32_am_support(vfdiv, ia32_am_Source);
3139 fold_immediate(env, vfdiv, 2, 3);
3141 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env->cg, node));
3149 * Transforms a l_MulS into a "real" MulS node.
3151 * @param env The transformation environment
3152 * @return the created ia32 MulS node
3154 static ir_node *gen_ia32_l_MulS(ia32_transform_env_t *env, ir_node *node) {
3155 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3156 ir_graph *irg = env->irg;
3157 dbg_info *dbg = get_irn_dbg_info(node);
3158 ir_node *block = transform_node(env, get_nodes_block(node));
3159 ir_node *left = get_binop_left(node);
3160 ir_node *right = get_binop_right(node);
3163 /* l_MulS is already a mode_T node, so we create the MulS in the normal way */
3164 /* and then skip the result Proj, because all needed Projs are already there. */
3166 ir_node *muls = new_rd_ia32_MulS(dbg, irg, block, noreg, noreg, left, right, new_NoMem());
3167 clear_ia32_commutative(muls);
3168 set_ia32_am_support(muls, ia32_am_Source);
3169 fold_immediate(env, muls, 2, 3);
3171 /* check if EAX and EDX proj exist, add missing one */
3172 in[0] = new_rd_Proj(dbg, irg, block, muls, mode_Iu, pn_EAX);
3173 in[1] = new_rd_Proj(dbg, irg, block, muls, mode_Iu, pn_EDX);
3174 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3176 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env->cg, node));
3181 GEN_LOWERED_SHIFT_OP(Shl)
3182 GEN_LOWERED_SHIFT_OP(Shr)
3183 GEN_LOWERED_SHIFT_OP(Shrs)
3186 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3187 * op1 - target to be shifted
3188 * op2 - contains bits to be shifted into target
3190 * Only op3 can be an immediate.
3192 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *node,
3193 ir_node *op1, ir_node *op2,
3195 ir_node *new_op = NULL;
3196 ir_graph *irg = env->irg;
3197 ir_mode *mode = get_irn_mode(node);
3198 dbg_info *dbg = get_irn_dbg_info(node);
3199 ir_node *block = transform_node(env, get_nodes_block(node));
3200 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3201 ir_node *nomem = new_NoMem();
3203 ir_node *new_op1 = transform_node(env, op1);
3204 ir_node *new_op2 = transform_node(env, op2);
3205 ir_node *new_count = transform_node(env, count);
3207 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
3209 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
3211 /* Check if immediate optimization is on and */
3212 /* if it's an operation with immediate. */
3213 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3215 /* Limit imm_op within range imm8 */
3217 tv = get_ia32_Immop_tarval(imm_op);
3220 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3221 set_ia32_Immop_tarval(imm_op, tv);
3228 /* integer operations */
3230 /* This is ShiftD with const */
3231 DB((mod, LEVEL_1, "ShiftD with immediate ..."));
3233 if (is_ia32_l_ShlD(node))
3234 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg,
3235 new_op1, new_op2, noreg, nomem);
3237 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg,
3238 new_op1, new_op2, noreg, nomem);
3239 set_ia32_Immop_attr(new_op, imm_op);
3242 /* This is a normal ShiftD */
3243 DB((mod, LEVEL_1, "ShiftD binop ..."));
3244 if (is_ia32_l_ShlD(node))
3245 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg,
3246 new_op1, new_op2, new_count, nomem);
3248 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg,
3249 new_op1, new_op2, new_count, nomem);
3252 /* set AM support */
3253 // Matze: node has unsupported format (6inputs)
3254 //set_ia32_am_support(new_op, ia32_am_Dest);
3256 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3258 set_ia32_emit_cl(new_op);
3263 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env, ir_node *node) {
3264 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3265 get_irn_n(node, 1), get_irn_n(node, 2));
3268 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env, ir_node *node) {
3269 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3270 get_irn_n(node, 1), get_irn_n(node, 2));
3274 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3276 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) {
3277 ia32_code_gen_t *cg = env->cg;
3278 ir_node *res = NULL;
3279 ir_graph *irg = env->irg;
3280 dbg_info *dbg = get_irn_dbg_info(node);
3281 ir_node *block = transform_node(env, get_nodes_block(node));
3282 ir_node *ptr = get_irn_n(node, 0);
3283 ir_node *val = get_irn_n(node, 1);
3284 ir_node *new_val = transform_node(env, val);
3285 ir_node *mem = get_irn_n(node, 2);
3286 ir_node *noreg, *new_ptr, *new_mem;
3292 noreg = ia32_new_NoReg_gp(cg);
3293 new_mem = transform_node(env, mem);
3294 new_ptr = transform_node(env, ptr);
3296 /* Store x87 -> MEM */
3297 res = new_rd_ia32_vfst(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
3298 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3299 set_ia32_use_frame(res);
3300 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3301 set_ia32_am_support(res, ia32_am_Dest);
3302 set_ia32_am_flavour(res, ia32_B);
3303 set_ia32_op_type(res, ia32_AddrModeD);
3305 /* Load MEM -> SSE */
3306 res = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, res);
3307 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3308 set_ia32_use_frame(res);
3309 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3310 set_ia32_am_support(res, ia32_am_Source);
3311 set_ia32_am_flavour(res, ia32_B);
3312 set_ia32_op_type(res, ia32_AddrModeS);
3313 res = new_rd_Proj(dbg, irg, block, res, mode_D, pn_ia32_xLoad_res);
3319 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3321 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) {
3322 ia32_code_gen_t *cg = env->cg;
3323 ir_graph *irg = env->irg;
3324 dbg_info *dbg = get_irn_dbg_info(node);
3325 ir_node *block = transform_node(env, get_nodes_block(node));
3326 ir_node *res = NULL;
3327 ir_node *ptr = get_irn_n(node, 0);
3328 ir_node *val = get_irn_n(node, 1);
3329 ir_node *mem = get_irn_n(node, 2);
3330 ir_entity *fent = get_ia32_frame_ent(node);
3331 ir_mode *lsmode = get_ia32_ls_mode(node);
3332 ir_node *new_val = transform_node(env, val);
3333 ir_node *noreg, *new_ptr, *new_mem;
3336 if (!USE_SSE2(cg)) {
3337 /* SSE unit is not used -> skip this node. */
3341 noreg = ia32_new_NoReg_gp(cg);
3342 new_val = transform_node(env, val);
3343 new_ptr = transform_node(env, ptr);
3344 new_mem = transform_node(env, mem);
3346 /* Store SSE -> MEM */
3347 if (is_ia32_xLoad(skip_Proj(new_val))) {
3348 ir_node *ld = skip_Proj(new_val);
3350 /* we can vfld the value directly into the fpu */
3351 fent = get_ia32_frame_ent(ld);
3352 ptr = get_irn_n(ld, 0);
3353 offs = get_ia32_am_offs_int(ld);
3355 res = new_rd_ia32_xStore(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
3356 set_ia32_frame_ent(res, fent);
3357 set_ia32_use_frame(res);
3358 set_ia32_ls_mode(res, lsmode);
3359 set_ia32_am_support(res, ia32_am_Dest);
3360 set_ia32_am_flavour(res, ia32_B);
3361 set_ia32_op_type(res, ia32_AddrModeD);
3365 /* Load MEM -> x87 */
3366 res = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, new_mem);
3367 set_ia32_frame_ent(res, fent);
3368 set_ia32_use_frame(res);
3369 set_ia32_ls_mode(res, lsmode);
3370 add_ia32_am_offs_int(res, offs);
3371 set_ia32_am_support(res, ia32_am_Source);
3372 set_ia32_am_flavour(res, ia32_B);
3373 set_ia32_op_type(res, ia32_AddrModeS);
3374 res = new_rd_Proj(dbg, irg, block, res, lsmode, pn_ia32_vfld_res);
3379 /*********************************************************
3382 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3383 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3384 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3385 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3387 *********************************************************/
3390 * the BAD transformer.
3392 static ir_node *bad_transform(ia32_transform_env_t *env, ir_node *node) {
3393 panic("No transform function for %+F available.\n", node);
3397 static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) {
3398 /* end has to be duplicated manually because we need a dynamic in array */
3399 ir_graph *irg = env->irg;
3400 dbg_info *dbg = get_irn_dbg_info(node);
3401 ir_node *block = transform_node(env, get_nodes_block(node));
3405 new_end = new_ir_node(dbg, irg, block, op_End, mode_X, -1, NULL);
3406 copy_node_attr(node, new_end);
3407 duplicate_deps(env, node, new_end);
3409 set_irg_end(irg, new_end);
3410 set_new_node(new_end, new_end);
3412 /* transform preds */
3413 arity = get_irn_arity(node);
3414 for(i = 0; i < arity; ++i) {
3415 ir_node *in = get_irn_n(node, i);
3416 ir_node *new_in = transform_node(env, in);
3418 add_End_keepalive(new_end, new_in);
3424 static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) {
3425 ir_graph *irg = env->irg;
3426 dbg_info *dbg = get_irn_dbg_info(node);
3427 ir_node *start_block = env->old_anchors[anchor_start_block];
3432 * We replace the ProjX from the start node with a jump,
3433 * so the startblock has no preds anymore now
3435 if(node == start_block) {
3436 return new_rd_Block(dbg, irg, 0, NULL);
3439 /* we use the old blocks for now, because jumps allow cycles in the graph
3440 * we have to fix this later */
3441 block = new_ir_node(dbg, irg, NULL, get_irn_op(node), get_irn_mode(node),
3442 get_irn_arity(node), get_irn_in(node) + 1);
3443 copy_node_attr(node, block);
3445 #ifdef DEBUG_libfirm
3446 block->node_nr = node->node_nr;
3448 set_new_node(node, block);
3450 /* put the preds in the worklist */
3451 arity = get_irn_arity(node);
3452 for(i = 0; i < arity; ++i) {
3453 ir_node *in = get_irn_n(node, i);
3454 pdeq_putr(env->worklist, in);
3460 static ir_node *gen_Proj_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
3461 ir_graph *irg = env->irg;
3462 ir_node *block = transform_node(env, get_nodes_block(node));
3463 dbg_info *dbg = get_irn_dbg_info(node);
3464 ir_node *pred = get_Proj_pred(node);
3465 ir_node *new_pred = transform_node(env, pred);
3466 int proj = get_Proj_proj(node);
3468 if(proj == pn_be_AddSP_res) {
3469 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3470 } else if(proj == pn_be_AddSP_M) {
3471 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3475 return new_rd_Unknown(irg, get_irn_mode(node));
3478 static ir_node *gen_Proj_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
3479 ir_graph *irg = env->irg;
3480 ir_node *block = transform_node(env, get_nodes_block(node));
3481 dbg_info *dbg = get_irn_dbg_info(node);
3482 ir_node *pred = get_Proj_pred(node);
3483 ir_node *new_pred = transform_node(env, pred);
3484 int proj = get_Proj_proj(node);
3486 if(proj == pn_be_SubSP_res) {
3487 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3488 } else if(proj == pn_be_SubSP_M) {
3489 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3493 return new_rd_Unknown(irg, get_irn_mode(node));
3496 static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) {
3497 ir_graph *irg = env->irg;
3498 ir_node *block = transform_node(env, get_nodes_block(node));
3499 dbg_info *dbg = get_irn_dbg_info(node);
3500 ir_node *pred = get_Proj_pred(node);
3501 ir_node *new_pred = transform_node(env, pred);
3502 int proj = get_Proj_proj(node);
3504 /* renumber the proj */
3505 if(is_ia32_Load(new_pred)) {
3506 if(proj == pn_Load_res) {
3507 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3508 } else if(proj == pn_Load_M) {
3509 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3511 } else if(is_ia32_xLoad(new_pred)) {
3512 if(proj == pn_Load_res) {
3513 return new_rd_Proj(dbg, irg, block, new_pred, mode_D, pn_ia32_xLoad_res);
3514 } else if(proj == pn_Load_M) {
3515 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3517 } else if(is_ia32_vfld(new_pred)) {
3518 if(proj == pn_Load_res) {
3519 return new_rd_Proj(dbg, irg, block, new_pred, mode_D, pn_ia32_vfld_res);
3520 } else if(proj == pn_Load_M) {
3521 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3526 return new_rd_Unknown(irg, get_irn_mode(node));
3529 static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) {
3530 ir_graph *irg = env->irg;
3531 dbg_info *dbg = get_irn_dbg_info(node);
3532 ir_node *block = transform_node(env, get_nodes_block(node));
3533 ir_mode *mode = get_irn_mode(node);
3535 ir_node *pred = get_Proj_pred(node);
3536 ir_node *new_pred = transform_node(env, pred);
3537 int proj = get_Proj_proj(node);
3539 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3541 switch(get_irn_opcode(pred)) {
3545 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3547 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3555 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3557 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3565 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3566 case pn_DivMod_res_div:
3567 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3568 case pn_DivMod_res_mod:
3569 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3579 return new_rd_Unknown(irg, mode);
3582 static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node)
3584 ir_graph *irg = env->irg;
3585 dbg_info *dbg = get_irn_dbg_info(node);
3586 ir_node *block = transform_node(env, get_nodes_block(node));
3587 ir_mode *mode = get_irn_mode(node);
3589 ir_node *pred = get_Proj_pred(node);
3590 ir_node *new_pred = transform_node(env, pred);
3591 int proj = get_Proj_proj(node);
3594 case pn_CopyB_M_regular:
3595 if(is_ia32_CopyB_i(new_pred)) {
3596 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3598 } else if(is_ia32_CopyB(new_pred)) {
3599 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3608 return new_rd_Unknown(irg, mode);
3611 static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node)
3613 ir_graph *irg = env->irg;
3614 dbg_info *dbg = get_irn_dbg_info(node);
3615 ir_node *block = transform_node(env, get_nodes_block(node));
3616 ir_mode *mode = get_irn_mode(node);
3618 ir_node *pred = get_Proj_pred(node);
3619 ir_node *new_pred = transform_node(env, pred);
3620 int proj = get_Proj_proj(node);
3623 case pn_ia32_l_vfdiv_M:
3624 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3625 case pn_ia32_l_vfdiv_res:
3626 return new_rd_Proj(dbg, irg, block, new_pred, mode_D, pn_ia32_vfdiv_res);
3631 return new_rd_Unknown(irg, mode);
3634 static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node)
3636 ir_graph *irg = env->irg;
3637 dbg_info *dbg = get_irn_dbg_info(node);
3638 ir_node *block = transform_node(env, get_nodes_block(node));
3639 ir_mode *mode = get_irn_mode(node);
3641 ir_node *pred = get_Proj_pred(node);
3642 ir_node *new_pred = transform_node(env, pred);
3643 int proj = get_Proj_proj(node);
3647 if(is_ia32_xDiv(new_pred)) {
3648 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3650 } else if(is_ia32_vfdiv(new_pred)) {
3651 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3656 if(is_ia32_xDiv(new_pred)) {
3657 return new_rd_Proj(dbg, irg, block, new_pred, mode,
3659 } else if(is_ia32_vfdiv(new_pred)) {
3660 return new_rd_Proj(dbg, irg, block, new_pred, mode,
3669 return new_rd_Unknown(irg, mode);
3672 static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) {
3673 ir_graph *irg = env->irg;
3674 dbg_info *dbg = get_irn_dbg_info(node);
3675 ir_node *pred = get_Proj_pred(node);
3676 int proj = get_Proj_proj(node);
3678 if(is_Store(pred) || be_is_FrameStore(pred)) {
3679 if(proj == pn_Store_M) {
3680 return transform_node(env, pred);
3683 return new_r_Bad(irg);
3685 } else if(is_Load(pred) || be_is_FrameLoad(pred)) {
3686 return gen_Proj_Load(env, node);
3687 } else if(is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3688 return gen_Proj_DivMod(env, node);
3689 } else if(is_CopyB(pred)) {
3690 return gen_Proj_CopyB(env, node);
3691 } else if(is_Quot(pred)) {
3692 return gen_Proj_Quot(env, node);
3693 } else if(is_ia32_l_vfdiv(pred)) {
3694 return gen_Proj_l_vfdiv(env, node);
3695 } else if(be_is_SubSP(pred)) {
3696 return gen_Proj_be_SubSP(env, node);
3697 } else if(be_is_AddSP(pred)) {
3698 return gen_Proj_be_AddSP(env, node);
3699 } else if(get_irn_op(pred) == op_Start && proj == pn_Start_X_initial_exec) {
3700 ir_node *block = get_nodes_block(pred);
3703 block = transform_node(env, block);
3704 // we exchange the ProjX with a jump
3705 jump = new_rd_Jmp(dbg, irg, block);
3706 ir_fprintf(stderr, "created jump: %+F\n", jump);
3710 return duplicate_node(env, node);
3714 * Enters all transform functions into the generic pointer
3716 static void register_transformers(void) {
3717 ir_op *op_Max, *op_Min, *op_Mulh;
3719 /* first clear the generic function pointer for all ops */
3720 clear_irp_opcodes_generic_func();
3722 #define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3723 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
3762 /* transform ops from intrinsic lowering */
3784 GEN(ia32_l_X87toSSE);
3785 GEN(ia32_l_SSEtoX87);
3790 /* we should never see these nodes */
3805 /* handle generic backend nodes */
3815 /* set the register for all Unknown nodes */
3818 op_Max = get_op_Max();
3821 op_Min = get_op_Min();
3824 op_Mulh = get_op_Mulh();
3832 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
3836 int deps = get_irn_deps(old_node);
3838 for(i = 0; i < deps; ++i) {
3839 ir_node *dep = get_irn_dep(old_node, i);
3840 ir_node *new_dep = transform_node(env, dep);
3842 add_irn_dep(new_node, new_dep);
3846 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node)
3848 ir_graph *irg = env->irg;
3849 dbg_info *dbg = get_irn_dbg_info(node);
3850 ir_mode *mode = get_irn_mode(node);
3851 ir_op *op = get_irn_op(node);
3857 block = transform_node(env, get_nodes_block(node));
3859 arity = get_irn_arity(node);
3860 ins = alloca(arity * sizeof(ins[0]));
3861 for(i = 0; i < arity; ++i) {
3862 ir_node *in = get_irn_n(node, i);
3863 ins[i] = transform_node(env, in);
3866 new_node = new_ir_node(dbg, irg, block,
3867 op, mode, arity, ins);
3868 copy_node_attr(node, new_node);
3869 duplicate_deps(env, node, new_node);
3874 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node)
3877 ir_op *op = get_irn_op(node);
3879 if(irn_visited(node)) {
3880 assert(get_new_node(node) != NULL);
3881 return get_new_node(node);
3884 mark_irn_visited(node);
3885 DEBUG_ONLY(set_new_node(node, NULL));
3887 if (op->ops.generic) {
3888 transform_func *transform = (transform_func *)op->ops.generic;
3890 new_node = (*transform)(env, node);
3891 assert(new_node != NULL);
3893 new_node = duplicate_node(env, node);
3895 //ir_fprintf(stderr, "%+F -> %+F\n", node, new_node);
3897 set_new_node(node, new_node);
3898 mark_irn_visited(new_node);
3899 hook_dead_node_elim_subst(current_ir_graph, node, new_node);
3903 static void fix_loops(ia32_transform_env_t *env, ir_node *node)
3907 if(irn_visited(node))
3909 mark_irn_visited(node);
3911 assert(node_is_in_irgs_storage(env->irg, node));
3913 if(!is_Block(node)) {
3914 ir_node *block = get_nodes_block(node);
3915 ir_node *new_block = (ir_node*) get_irn_link(block);
3917 if(new_block != NULL) {
3918 set_nodes_block(node, new_block);
3922 fix_loops(env, block);
3925 arity = get_irn_arity(node);
3926 for(i = 0; i < arity; ++i) {
3927 ir_node *in = get_irn_n(node, i);
3928 ir_node *new = (ir_node*) get_irn_link(in);
3930 if(new != NULL && new != in) {
3931 set_irn_n(node, i, new);
3938 arity = get_irn_deps(node);
3939 for(i = 0; i < arity; ++i) {
3940 ir_node *in = get_irn_dep(node, i);
3941 ir_node *new = (ir_node*) get_irn_link(in);
3943 if(new != NULL && new != in) {
3944 set_irn_dep(node, i, new);
3952 static void pre_transform_node(ir_node **place, ia32_transform_env_t *env)
3957 *place = transform_node(env, *place);
3960 static void transform_nodes(ia32_code_gen_t *cg)
3963 ir_graph *irg = cg->irg;
3965 ia32_transform_env_t env;
3967 hook_dead_node_elim(irg, 1);
3969 inc_irg_visited(irg);
3973 env.visited = get_irg_visited(irg);
3974 env.worklist = new_pdeq();
3975 env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
3976 DEBUG_ONLY(env.mod = cg->mod);
3978 old_end = get_irg_end(irg);
3980 /* put all anchor nodes in the worklist */
3981 for(i = 0; i < anchor_max; ++i) {
3982 ir_node *anchor = irg->anchors[i];
3985 pdeq_putr(env.worklist, anchor);
3988 env.old_anchors[i] = anchor;
3989 // and set it to NULL to make sure we don't accidently use it
3990 irg->anchors[i] = NULL;
3993 // pre transform some anchors (so they are available in the other transform
3995 set_irg_bad(irg, transform_node(&env, env.old_anchors[anchor_bad]));
3996 set_irg_no_mem(irg, transform_node(&env, env.old_anchors[anchor_no_mem]));
3997 set_irg_start_block(irg, transform_node(&env, env.old_anchors[anchor_start_block]));
3998 set_irg_start(irg, transform_node(&env, env.old_anchors[anchor_start]));
3999 set_irg_frame(irg, transform_node(&env, env.old_anchors[anchor_frame]));
4001 pre_transform_node(&cg->unknown_gp, &env);
4002 pre_transform_node(&cg->unknown_vfp, &env);
4003 pre_transform_node(&cg->unknown_xmm, &env);
4004 pre_transform_node(&cg->noreg_gp, &env);
4005 pre_transform_node(&cg->noreg_vfp, &env);
4006 pre_transform_node(&cg->noreg_xmm, &env);
4008 /* process worklist (this should transform all nodes in the graph) */
4009 while(!pdeq_empty(env.worklist)) {
4010 ir_node *node = pdeq_getl(env.worklist);
4011 transform_node(&env, node);
4014 /* fix loops and set new anchors*/
4015 inc_irg_visited(irg);
4016 for(i = 0; i < anchor_max; ++i) {
4017 ir_node *anchor = env.old_anchors[i];
4021 anchor = get_irn_link(anchor);
4022 fix_loops(&env, anchor);
4023 assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
4024 irg->anchors[i] = anchor;
4027 del_pdeq(env.worklist);
4029 hook_dead_node_elim(irg, 0);
4032 void ia32_transform_graph(ia32_code_gen_t *cg)
4034 ir_graph *irg = cg->irg;
4035 be_irg_t *birg = cg->birg;
4036 ir_graph *old_current_ir_graph = current_ir_graph;
4037 int old_interprocedural_view = get_interprocedural_view();
4038 struct obstack *old_obst = NULL;
4039 struct obstack *new_obst = NULL;
4041 current_ir_graph = irg;
4042 set_interprocedural_view(0);
4043 register_transformers();
4045 /* most analysis info is wrong after transformation */
4046 free_callee_info(irg);
4048 irg->outs_state = outs_none;
4050 free_loop_information(irg);
4051 set_irg_doms_inconsistent(irg);
4052 be_invalidate_liveness(birg);
4053 be_invalidate_dom_front(birg);
4055 /* create a new obstack */
4056 old_obst = irg->obst;
4057 new_obst = xmalloc(sizeof(*new_obst));
4058 obstack_init(new_obst);
4059 irg->obst = new_obst;
4060 irg->last_node_idx = 0;
4062 /* create new value table for CSE */
4063 del_identities(irg->value_table);
4064 irg->value_table = new_identities();
4066 /* do the main transformation */
4067 transform_nodes(cg);
4069 /* we don't want the globals anchor anymore */
4070 set_irg_globals(irg, new_r_Bad(irg));
4072 /* free the old obstack */
4073 obstack_free(old_obst, 0);
4077 current_ir_graph = old_current_ir_graph;
4078 set_interprocedural_view(old_interprocedural_view);
4080 /* recalculate edges */
4081 edges_deactivate(irg);
4082 edges_activate(irg);
4086 * Transforms a psi condition.
4088 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
4091 /* if the mode is target mode, we have already seen this part of the tree */
4092 if (get_irn_mode(cond) == mode)
4095 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
4097 set_irn_mode(cond, mode);
4099 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
4100 ir_node *in = get_irn_n(cond, i);
4102 /* if in is a compare: transform into Set/xCmp */
4104 ir_node *new_op = NULL;
4105 ir_node *cmp = get_Proj_pred(in);
4106 ir_node *cmp_a = get_Cmp_left(cmp);
4107 ir_node *cmp_b = get_Cmp_right(cmp);
4108 dbg_info *dbg = get_irn_dbg_info(cmp);
4109 ir_graph *irg = get_irn_irg(cmp);
4110 ir_node *block = get_nodes_block(cmp);
4111 ir_node *noreg = ia32_new_NoReg_gp(cg);
4112 ir_node *nomem = new_rd_NoMem(irg);
4113 int pnc = get_Proj_proj(in);
4115 /* this is a compare */
4116 if (mode_is_float(mode)) {
4117 /* Psi is float, we need a floating point compare */
4120 ir_mode *m = get_irn_mode(cmp_a);
4122 if (! mode_is_float(m)) {
4123 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
4124 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
4126 else if (m == mode_F) {
4127 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
4128 cmp_a = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_a, cmp_a);
4129 cmp_b = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_b, cmp_b);
4132 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4133 set_ia32_pncode(new_op, pnc);
4134 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
4143 construct_binop_func *set_func = NULL;
4145 if (mode_is_float(get_irn_mode(cmp_a))) {
4146 /* 1st case: compare operands are floats */
4151 set_func = new_rd_ia32_xCmpSet;
4155 set_func = new_rd_ia32_vfCmpSet;
4158 pnc &= 7; /* fp compare -> int compare */
4161 /* 2nd case: compare operand are integer too */
4162 set_func = new_rd_ia32_CmpSet;
4165 new_op = set_func(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4166 if(!mode_is_signed(mode))
4167 pnc |= ia32_pn_Cmp_Unsigned;
4169 set_ia32_pncode(new_op, pnc);
4170 set_ia32_am_support(new_op, ia32_am_Source);
4173 /* the the new compare as in */
4174 set_irn_n(cond, i, new_op);
4177 /* another complex condition */
4178 transform_psi_cond(in, mode, cg);
4184 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
4185 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
4186 * compare, which causes the compare result to be stores in a register. The
4187 * "And"s and "Or"s are transformed later, we just have to set their mode right.
4189 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
4190 ia32_code_gen_t *cg = env;
4191 ir_node *psi_sel, *new_cmp, *block;
4196 if (get_irn_opcode(node) != iro_Psi)
4199 psi_sel = get_Psi_cond(node, 0);
4201 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
4202 if (is_Proj(psi_sel))
4205 //mode = get_irn_mode(node);
4206 // TODO this is probably wrong...
4209 transform_psi_cond(psi_sel, mode, cg);
4211 irg = get_irn_irg(node);
4212 block = get_nodes_block(node);
4214 /* we need to compare the evaluated condition tree with 0 */
4215 mode = get_irn_mode(node);
4216 if (mode_is_float(mode)) {
4217 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
4218 /* BEWARE: new_r_Const_long works for floating point as well */
4219 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
4220 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
4223 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode_Iu, 0));
4224 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
4227 set_Psi_cond(node, 0, new_cmp);