3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I|S"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
36 # "latency" => "latency of this operation (can be float)"
39 # ... # (all nodes you need to describe)
41 # ); # close the %nodes initializer
43 # op_flags: flags for the operation, OPTIONAL (default is "N")
44 # the op_flags correspond to the firm irop_flags:
47 # C irop_flag_commutative
48 # X irop_flag_cfopcode
49 # I irop_flag_ip_cfopcode
52 # H irop_flag_highlevel
53 # c irop_flag_constlike
56 # irn_flags: special node flags, OPTIONAL (default is 0)
57 # following irn_flags are supported:
60 # I ignore for register allocation
61 # S modifies stack pointer
63 # state: state of the operation, OPTIONAL (default is "floats")
65 # arity: arity of the operation, MUST NOT BE OMITTED
67 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
68 # are always the first 3 arguments and are always autmatically
70 # If this key is missing the following arguments will be created:
71 # for i = 1 .. arity: ir_node *op_i
74 # outs: if a node defines more than one output, the names of the projections
75 # nodes having outs having automatically the mode mode_T
76 # One can also annotate some flags for each out, additional to irn_flags.
77 # They are separated from name with a colon ':', and concatenated by pipe '|'
78 # Only I and S are available at the moment (same meaning as in irn_flags).
79 # example: [ "frame:I", "stack:I|S", "M" ]
81 # comment: OPTIONAL comment for the node constructor
83 # rd_constructor: for every operation there will be a
84 # new_rd_<arch>_<op-name> function with the arguments from above
85 # which creates the ir_node corresponding to the defined operation
86 # you can either put the complete source code of this function here
88 # This key is OPTIONAL. If omitted, the following constructor will
90 # if (!op_<arch>_<op-name>) assert(0);
94 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
97 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
99 # latency: the latency of the operation, default is 1
103 # 0 - no special type
104 # 1 - caller save (register must be saved by the caller of a function)
105 # 2 - callee save (register must be saved by the called function)
106 # 4 - ignore (do not assign this register)
107 # 8 - emitter can choose an arbitrary register of this class
108 # 16 - the register is a virtual one
109 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
112 { "name" => "eax", "type" => 1 },
113 { "name" => "edx", "type" => 1 },
114 { "name" => "ebx", "type" => 2 },
115 { "name" => "ecx", "type" => 1 },
116 { "name" => "esi", "type" => 2 },
117 { "name" => "edi", "type" => 2 },
118 # { "name" => "r11", "type" => 1 },
119 # { "name" => "r12", "type" => 1 },
120 # { "name" => "r13", "type" => 1 },
121 # { "name" => "r14", "type" => 1 },
122 # { "name" => "r15", "type" => 1 },
123 # { "name" => "r16", "type" => 1 },
124 # { "name" => "r17", "type" => 1 },
125 # { "name" => "r18", "type" => 1 },
126 # { "name" => "r19", "type" => 1 },
127 # { "name" => "r20", "type" => 1 },
128 # { "name" => "r21", "type" => 1 },
129 # { "name" => "r22", "type" => 1 },
130 # { "name" => "r23", "type" => 1 },
131 # { "name" => "r24", "type" => 1 },
132 # { "name" => "r25", "type" => 1 },
133 # { "name" => "r26", "type" => 1 },
134 # { "name" => "r27", "type" => 1 },
135 # { "name" => "r28", "type" => 1 },
136 # { "name" => "r29", "type" => 1 },
137 # { "name" => "r30", "type" => 1 },
138 # { "name" => "r31", "type" => 1 },
139 # { "name" => "r32", "type" => 1 },
140 { "name" => "ebp", "type" => 2 },
141 { "name" => "esp", "type" => 4 },
142 { "name" => "gp_NOREG", "type" => 2 | 4 | 16 }, # we need a dummy register for NoReg nodes
143 { "name" => "gp_UKNWN", "type" => 2 | 4 | 8 | 16}, # we need a dummy register for Unknown nodes
144 { "mode" => "mode_P" }
147 { "name" => "xmm0", "type" => 1 },
148 { "name" => "xmm1", "type" => 1 },
149 { "name" => "xmm2", "type" => 1 },
150 { "name" => "xmm3", "type" => 1 },
151 { "name" => "xmm4", "type" => 1 },
152 { "name" => "xmm5", "type" => 1 },
153 { "name" => "xmm6", "type" => 1 },
154 { "name" => "xmm7", "type" => 1 },
155 { "name" => "xmm_NOREG", "type" => 2 | 4 | 16 }, # we need a dummy register for NoReg nodes
156 { "name" => "xmm_UKNWN", "type" => 2 | 4 | 8 | 16}, # we need a dummy register for Unknown nodes
157 { "mode" => "mode_D" }
160 { "name" => "vf0", "type" => 1 | 16 },
161 { "name" => "vf1", "type" => 1 | 16 },
162 { "name" => "vf2", "type" => 1 | 16 },
163 { "name" => "vf3", "type" => 1 | 16 },
164 { "name" => "vf4", "type" => 1 | 16 },
165 { "name" => "vf5", "type" => 1 | 16 },
166 { "name" => "vf6", "type" => 1 | 16 },
167 { "name" => "vf7", "type" => 1 | 16 },
168 { "name" => "vfp_NOREG", "type" => 2 | 4 | 16 }, # we need a dummy register for NoReg nodes
169 { "name" => "vfp_UKNWN", "type" => 2 | 4 | 8 | 16}, # we need a dummy register for Unknown nodes
170 { "mode" => "mode_E" }
173 { "name" => "st0", "type" => 1 },
174 { "name" => "st1", "type" => 1 },
175 { "name" => "st2", "type" => 1 },
176 { "name" => "st3", "type" => 1 },
177 { "name" => "st4", "type" => 1 },
178 { "name" => "st5", "type" => 1 },
179 { "name" => "st6", "type" => 1 },
180 { "name" => "st7", "type" => 1 },
181 { "mode" => "mode_E" }
186 "ALU" => [ "ALU1", "ALU2", "ALU3", "ALU4" ],
187 "MUL" => [ "MUL1", "MUL2" ],
188 "SSE" => [ "SSE1", "SSE2" ],
190 "MEM" => [ "MEM1", "MEM2" ],
191 "BRANCH" => [ "BRANCH1", "BRANCH2" ]
194 #--------------------------------------------------#
197 # _ __ _____ __ _ _ __ ___ _ __ ___ #
198 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
199 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
200 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
203 #--------------------------------------------------#
210 #-----------------------------------------------------------------#
213 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
214 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
215 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
216 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
219 #-----------------------------------------------------------------#
221 # commutative operations
224 # All nodes supporting Addressmode have 5 INs:
225 # 1 - base r1 == NoReg in case of no AM or no base
226 # 2 - index r2 == NoReg in case of no AM or no index
227 # 3 - op1 r3 == always present
228 # 4 - op2 r4 == NoReg in case of immediate operation
229 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
233 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
234 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
235 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
236 "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
237 "outs" => [ "res", "M" ],
238 "units" => [ "ALU", "MEM" ],
242 "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
243 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
244 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
245 "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
246 "outs" => [ "res", "M" ],
247 "units" => [ "ALU", "MEM" ],
252 "comment" => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
254 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
256 . mov %D1, %S1 /* mov a_l into assigned l_res register */
257 . mov %D2, %S2 /* mov a_h into assigned h_res register */
258 . add %D1, %S3 /* a_l + b_l */
259 . adc %D2, %S4 /* a_h + b_h + carry */
261 "outs" => [ "low_res", "high_res" ],
262 "units" => [ "ALU", "MEM" ],
268 "cmp_attr" => " return 1;\n",
269 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
275 "cmp_attr" => " return 1;\n",
276 "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
281 # we should not rematrialize this node. It produces 2 results and has
282 # very strict constrains
283 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
284 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
285 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
286 "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */',
287 "outs" => [ "EAX", "EDX", "M" ],
292 # we should not rematrialize this node. It produces 2 results and has
293 # very strict constrains
295 "cmp_attr" => " return 1;\n",
296 "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
297 "outs" => [ "EAX", "EDX", "M" ],
303 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
304 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
305 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
306 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
307 "outs" => [ "res", "M" ],
313 "cmp_attr" => " return 1;\n",
314 "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
318 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
320 # we should not rematrialize this node. It produces 2 results and has
321 # very strict constrains
322 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
323 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
324 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
325 "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */',
326 "outs" => [ "EAX", "EDX", "M" ],
332 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
333 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
334 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
335 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
336 "outs" => [ "res", "M" ],
341 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
342 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
343 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
344 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
345 "outs" => [ "res", "M" ],
350 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
351 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
352 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
353 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
354 "outs" => [ "res", "M" ],
359 "cmp_attr" => " return 1;\n",
360 "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b",
366 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
367 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
369 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
370 if (mode_is_signed(get_irn_mode(n))) {
371 4. cmovl %D1, %S2 /* %S1 is less %S2 */
374 4. cmovb %D1, %S2 /* %S1 is below %S2 */
382 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
383 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
385 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
386 if (mode_is_signed(get_irn_mode(n))) {
387 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
390 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
396 # not commutative operations
400 "comment" => "construct Sub: Sub(a, b) = a - b",
401 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
402 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
403 "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
404 "outs" => [ "res", "M" ],
408 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
409 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
410 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] },
411 "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
412 "outs" => [ "res", "M" ],
417 "comment" => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
419 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
421 . mov %D1, %S1 /* mov a_l into assigned l_res register */
422 . mov %D2, %S2 /* mov a_h into assigned h_res register */
423 . sub %D1, %S3 /* a_l - b_l */
424 . sbb %D2, %S4 /* a_h - b_h - borrow */
426 "outs" => [ "low_res", "high_res" ],
431 "cmp_attr" => " return 1;\n",
432 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
437 "cmp_attr" => " return 1;\n",
438 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
444 "state" => "exc_pinned",
445 "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx" ] },
446 "attr" => "ia32_op_flavour_t dm_flav",
447 "init_attr" => " attr->data.op_flav = dm_flav;",
448 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
450 ' if (mode_is_signed(get_ia32_res_mode(n))) {
451 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
454 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
457 "outs" => [ "div_res", "mod_res", "M" ],
463 "comment" => "construct Shl: Shl(a, b) = a << b",
464 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
465 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] },
466 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
467 "outs" => [ "res", "M" ],
468 "units" => [ "ALU1", "SSE1" ],
472 "cmp_attr" => " return 1;\n",
473 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
479 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
480 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
481 # Out requirements is: different from all in
482 # This is because, out must be different from LowPart and ShiftCount.
483 # We could say "!ecx !in_r4" but it can occur, that all values live through
484 # this Shift and the only value dying is the ShiftCount. Then there would be a
485 # register missing, as result must not be ecx and all other registers are
486 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
487 # (and probably never will). So we create artificial interferences of the result
488 # with all inputs, so the spiller can always assure a free register.
489 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
492 if (get_ia32_immop_type(n) == ia32_ImmNone) {
493 if (get_ia32_op_type(n) == ia32_AddrModeD) {
494 4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
497 4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
501 if (get_ia32_op_type(n) == ia32_AddrModeD) {
502 4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
505 4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
509 "outs" => [ "res", "M" ],
514 "cmp_attr" => " return 1;\n",
515 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
521 "comment" => "construct Shr: Shr(a, b) = a >> b",
522 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
523 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] },
524 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
525 "outs" => [ "res", "M" ],
529 "cmp_attr" => " return 1;\n",
530 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
536 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
537 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
538 # Out requirements is: different from all in
539 # This is because, out must be different from LowPart and ShiftCount.
540 # We could say "!ecx !in_r4" but it can occur, that all values live through
541 # this Shift and the only value dying is the ShiftCount. Then there would be a
542 # register missing, as result must not be ecx and all other registers are
543 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
544 # (and probably never will). So we create artificial interferences of the result
545 # with all inputs, so the spiller can always assure a free register.
546 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
549 if (get_ia32_immop_type(n) == ia32_ImmNone) {
550 if (get_ia32_op_type(n) == ia32_AddrModeD) {
551 4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
554 4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
558 if (get_ia32_op_type(n) == ia32_AddrModeD) {
559 4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
562 4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
566 "outs" => [ "res", "M" ],
571 "cmp_attr" => " return 1;\n",
572 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
578 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
579 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
580 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] },
581 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
582 "outs" => [ "res", "M" ],
586 "cmp_attr" => " return 1;\n",
587 "comment" => "construct lowered Shrs: Shrs(a, b) = a << b",
593 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
594 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
595 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
596 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
597 "outs" => [ "res", "M" ],
602 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
603 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
604 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
605 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
606 "outs" => [ "res", "M" ],
613 "comment" => "construct Minus: Minus(a) = -a",
614 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
615 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
616 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
617 "outs" => [ "res", "M" ],
622 "comment" => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
624 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "!in", "!in" ] },
626 . mov %D1, %S1 /* l_res */
627 . mov %D2, %S1 /* h_res */
628 . sub %D1, %S2 /* 0 - a_l -> low_res */
629 . sbb %D2, %S3 /* 0 - a_h - borrow -> high_res */
631 "outs" => [ "low_res", "high_res" ],
636 "cmp_attr" => " return 1;\n",
637 "comment" => "construct lowered Minus: Minus(a) = -a",
643 "comment" => "construct Increment: Inc(a) = a++",
644 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
645 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
646 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
647 "outs" => [ "res", "M" ],
652 "comment" => "construct Decrement: Dec(a) = a--",
653 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
654 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
655 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
656 "outs" => [ "res", "M" ],
661 "comment" => "construct Not: Not(a) = !a",
662 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
663 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
664 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
665 "outs" => [ "res", "M" ],
671 "op_flags" => "L|X|Y",
672 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
673 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
674 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
675 "outs" => [ "false", "true" ],
680 "op_flags" => "L|X|Y",
681 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
682 "reg_req" => { "in" => [ "gp", "gp" ] },
683 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
684 "outs" => [ "false", "true" ],
689 "op_flags" => "L|X|Y",
690 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
691 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
692 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
693 "outs" => [ "false", "true" ],
697 "op_flags" => "L|X|Y",
698 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
699 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
700 "reg_req" => { "in" => [ "gp", "gp" ] },
704 "op_flags" => "L|X|Y",
705 "comment" => "construct switch",
706 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
707 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
714 "comment" => "represents an integer constant",
715 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
716 "reg_req" => { "out" => [ "gp" ] },
720 # we should not rematrialize this node. It produces 2 results and has
721 # very strict constrains
722 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
723 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
724 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
725 "outs" => [ "EAX", "EDX" ],
732 "state" => "exc_pinned",
733 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
734 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
735 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
738 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
739 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
742 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
745 "outs" => [ "res", "M" ],
750 "cmp_attr" => " return 1;\n",
751 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
752 "outs" => [ "res", "M" ],
758 "cmp_attr" => " return 1;\n",
759 "state" => "exc_pinned",
760 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
767 "state" => "exc_pinned",
768 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
769 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
770 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
771 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
778 "state" => "exc_pinned",
779 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
780 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
781 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx gp_NOREG", "none" ] },
782 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
789 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
790 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
791 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
792 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */',
797 "comment" => "push on the stack",
798 "reg_req" => { "in" => [ "gp", "gp", "gp", "esp", "none" ], "out" => [ "esp" ] },
799 "emit" => '. push %ia32_emit_unop /* PUSH(%A1) */',
800 "outs" => [ "stack:I|S", "M" ],
805 # We don't set class modify stack here (but we will do this on proj 1)
806 "comment" => "pop a gp register from the stack",
807 "reg_req" => { "in" => [ "gp", "gp", "esp", "none" ], "out" => [ "gp", "esp" ] },
808 "emit" => '. pop %ia32_emit_unop /* POP(%A1) */',
809 "outs" => [ "res", "stack:I|S", "M" ],
814 "comment" => "create stack frame",
815 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
816 "emit" => '. enter /* Enter */',
817 "outs" => [ "frame:I", "stack:I|S", "M" ],
822 "comment" => "destroy stack frame",
823 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
824 "emit" => '. leave /* Leave */',
825 "outs" => [ "frame:I", "stack:I|S", "M" ],
831 "comment" => "allocate space on stack",
832 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
833 "outs" => [ "stack:S", "M" ],
838 "comment" => "free space on stack",
839 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
840 "outs" => [ "stack:S", "M" ],
845 "comment" => "get the TLS base address",
846 "reg_req" => { "out" => [ "gp" ] },
851 #-----------------------------------------------------------------------------#
852 # _____ _____ ______ __ _ _ _ #
853 # / ____/ ____| ____| / _| | | | | | #
854 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
855 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
856 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
857 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
858 #-----------------------------------------------------------------------------#
860 # commutative operations
864 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
865 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
866 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
867 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
868 "outs" => [ "res", "M" ],
874 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
875 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
876 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
877 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
878 "outs" => [ "res", "M" ],
884 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
885 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
886 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
887 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
888 "outs" => [ "res", "M" ],
894 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
895 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
896 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
897 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
898 "outs" => [ "res", "M" ],
904 "comment" => "construct SSE And: And(a, b) = a AND b",
905 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
906 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
907 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
908 "outs" => [ "res", "M" ],
914 "comment" => "construct SSE Or: Or(a, b) = a OR b",
915 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
916 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
917 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
918 "outs" => [ "res", "M" ],
923 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
924 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
925 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
926 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
927 "outs" => [ "res", "M" ],
931 # not commutative operations
935 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
936 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
937 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
938 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
939 "outs" => [ "res", "M" ],
945 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
946 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
947 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
948 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
949 "outs" => [ "res", "M" ],
955 "comment" => "construct SSE Div: Div(a, b) = a / b",
956 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
957 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
958 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
959 "outs" => [ "res", "M" ],
967 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
968 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
969 "outs" => [ "res", "M" ],
974 "op_flags" => "L|X|Y",
975 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
976 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
977 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
978 "outs" => [ "false", "true" ],
985 "comment" => "represents a SSE constant",
986 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
987 "reg_req" => { "out" => [ "xmm" ] },
988 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
996 "state" => "exc_pinned",
997 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
998 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
999 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
1000 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
1001 "outs" => [ "res", "M" ],
1006 "op_flags" => "L|F",
1007 "state" => "exc_pinned",
1008 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1009 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1010 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
1011 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
1017 "op_flags" => "L|F",
1018 "state" => "exc_pinned",
1019 "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
1020 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1021 "reg_req" => { "in" => [ "gp", "xmm", "none" ] },
1022 "emit" => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */',
1028 "op_flags" => "L|F",
1029 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
1030 "cmp_attr" => " return 1;\n",
1035 "op_flags" => "L|F",
1036 "comment" => "construct: transfer a value from SSE register to x87 FPU",
1037 "cmp_attr" => " return 1;\n",
1042 "op_flags" => "L|F",
1044 "state" => "exc_pinned",
1045 "comment" => "store ST0 onto stack",
1046 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1047 "reg_req" => { "in" => [ "gp", "none" ] },
1048 "emit" => '. fstp %ia32_emit_am /* store ST0 onto stack */',
1054 "op_flags" => "L|F",
1056 "state" => "exc_pinned",
1057 "comment" => "load ST0 from stack",
1058 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1059 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "vf0", "none" ] },
1060 "emit" => '. fld %ia32_emit_am /* load ST0 from stack */',
1061 "outs" => [ "res", "M" ],
1068 "op_flags" => "F|H",
1069 "state" => "pinned",
1070 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1071 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
1072 "outs" => [ "DST", "SRC", "CNT", "M" ],
1076 "op_flags" => "F|H",
1077 "state" => "pinned",
1078 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1079 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1080 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
1081 "outs" => [ "DST", "SRC", "M" ],
1087 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
1088 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1089 "comment" => "construct Conv Int -> Int",
1090 "outs" => [ "res", "M" ],
1094 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
1095 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1096 "comment" => "construct Conv Int -> Int",
1097 "outs" => [ "res", "M" ],
1101 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1102 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1103 "comment" => "construct Conv Int -> Floating Point",
1104 "outs" => [ "res", "M" ],
1109 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
1110 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1111 "comment" => "construct Conv Floating Point -> Int",
1112 "outs" => [ "res", "M" ],
1117 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
1118 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1119 "comment" => "construct Conv Floating Point -> Floating Point",
1120 "outs" => [ "res", "M" ],
1126 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1127 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
1133 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
1134 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
1140 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
1141 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
1147 "comment" => "construct Conditional Move: x87 Compare + int CMov",
1148 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
1154 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
1155 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1156 "outs" => [ "res", "M" ],
1162 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
1163 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
1169 "comment" => "construct Set: SSE Compare + int Set",
1170 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1171 "outs" => [ "res", "M" ],
1177 "comment" => "construct Set: x87 Compare + int Set",
1178 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1179 "outs" => [ "res", "M" ],
1185 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1186 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
1190 #----------------------------------------------------------#
1192 # (_) | | | | / _| | | | #
1193 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1194 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1195 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1196 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1198 # _ __ ___ __| | ___ ___ #
1199 # | '_ \ / _ \ / _` |/ _ \/ __| #
1200 # | | | | (_) | (_| | __/\__ \ #
1201 # |_| |_|\___/ \__,_|\___||___/ #
1202 #----------------------------------------------------------#
1206 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1207 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1208 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1209 "outs" => [ "res", "M" ],
1215 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1216 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1217 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1218 "outs" => [ "res", "M" ],
1224 "cmp_attr" => " return 1;\n",
1225 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1231 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1232 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1233 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1234 "outs" => [ "res", "M" ],
1239 "cmp_attr" => " return 1;\n",
1240 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1245 "comment" => "virtual fp Div: Div(a, b) = a / b",
1246 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1247 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1248 "outs" => [ "res", "M" ],
1253 "cmp_attr" => " return 1;\n",
1254 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1259 "comment" => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1260 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1261 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1262 "outs" => [ "res", "M" ],
1267 "cmp_attr" => " return 1;\n",
1268 "comment" => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1274 "comment" => "virtual fp Abs: Abs(a) = |a|",
1275 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1281 "comment" => "virtual fp Chs: Chs(a) = -a",
1282 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1288 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1289 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1295 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1296 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1302 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1303 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1307 # virtual Load and Store
1310 "op_flags" => "L|F",
1311 "state" => "exc_pinned",
1312 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1313 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1314 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1315 "outs" => [ "res", "M" ],
1320 "op_flags" => "L|F",
1321 "state" => "exc_pinned",
1322 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1323 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1324 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1332 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1333 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1334 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1335 "outs" => [ "res", "M" ],
1340 "cmp_attr" => " return 1;\n",
1341 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1342 "outs" => [ "res", "M" ],
1347 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1348 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1349 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1355 "cmp_attr" => " return 1;\n",
1356 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1366 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1367 "reg_req" => { "out" => [ "vfp" ] },
1373 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1374 "reg_req" => { "out" => [ "vfp" ] },
1380 "comment" => "virtual fp Load pi: Ld pi -> reg",
1381 "reg_req" => { "out" => [ "vfp" ] },
1387 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1388 "reg_req" => { "out" => [ "vfp" ] },
1394 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1395 "reg_req" => { "out" => [ "vfp" ] },
1401 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1402 "reg_req" => { "out" => [ "vfp" ] },
1408 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1409 "reg_req" => { "out" => [ "vfp" ] },
1416 "init_attr" => " set_ia32_ls_mode(res, mode);",
1417 "comment" => "represents a virtual floating point constant",
1418 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1419 "reg_req" => { "out" => [ "vfp" ] },
1426 "op_flags" => "L|X|Y",
1427 "comment" => "represents a virtual floating point compare",
1428 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1429 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1430 "outs" => [ "false", "true", "temp_reg_eax" ],
1434 #------------------------------------------------------------------------#
1435 # ___ _____ __ _ _ _ #
1436 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1437 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1438 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1439 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1440 #------------------------------------------------------------------------#
1444 "rd_constructor" => "NONE",
1445 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1447 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1452 "rd_constructor" => "NONE",
1453 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1455 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1460 "rd_constructor" => "NONE",
1461 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1463 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',
1468 "rd_constructor" => "NONE",
1469 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1471 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',,
1476 "rd_constructor" => "NONE",
1477 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1479 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1484 "rd_constructor" => "NONE",
1485 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1487 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1492 "rd_constructor" => "NONE",
1494 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1496 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1501 "rd_constructor" => "NONE",
1503 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1505 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1510 "rd_constructor" => "NONE",
1511 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1513 "emit" => '. fprem1 /* x87 fprem(%A3, %A4) -> %D1 */',
1516 # this node is just here, to keep the simulator running
1517 # we can omit this when a fprem simulation function exists
1520 "rd_constructor" => "NONE",
1521 "comment" => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1523 "emit" => '. fprem1 /* x87 fprem(%A3, %A4) -> %D1 WITH POP */',
1528 "rd_constructor" => "NONE",
1529 "comment" => "x87 fp Div: Div(a, b) = a / b",
1531 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1536 "rd_constructor" => "NONE",
1537 "comment" => "x87 fp Div: Div(a, b) = a / b",
1539 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1544 "rd_constructor" => "NONE",
1545 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1547 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1552 "rd_constructor" => "NONE",
1553 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1555 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1560 "rd_constructor" => "NONE",
1561 "comment" => "x87 fp Abs: Abs(a) = |a|",
1563 "emit" => '. fabs /* x87 fabs(%A1) -> %D1 */',
1568 "rd_constructor" => "NONE",
1569 "comment" => "x87 fp Chs: Chs(a) = -a",
1571 "emit" => '. fchs /* x87 fchs(%A1) -> %D1 */',
1576 "rd_constructor" => "NONE",
1577 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1579 "emit" => '. fsin /* x87 sin(%A1) -> %D1 */',
1584 "rd_constructor" => "NONE",
1585 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1587 "emit" => '. fcos /* x87 cos(%A1) -> %D1 */',
1592 "rd_constructor" => "NONE",
1593 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1595 "emit" => '. fsqrt $ /* x87 sqrt(%A1) -> %D1 */',
1598 # x87 Load and Store
1601 "rd_constructor" => "NONE",
1602 "op_flags" => "R|L|F",
1603 "state" => "exc_pinned",
1604 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1606 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1610 "rd_constructor" => "NONE",
1611 "op_flags" => "R|L|F",
1612 "state" => "exc_pinned",
1613 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1615 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1619 "rd_constructor" => "NONE",
1620 "op_flags" => "R|L|F",
1621 "state" => "exc_pinned",
1622 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1624 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1631 "rd_constructor" => "NONE",
1632 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1634 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1639 "rd_constructor" => "NONE",
1640 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1642 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1647 "rd_constructor" => "NONE",
1648 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1650 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1656 "op_flags" => "R|c",
1658 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1659 "reg_req" => { "out" => [ "vfp" ] },
1660 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1664 "op_flags" => "R|c",
1666 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1667 "reg_req" => { "out" => [ "vfp" ] },
1668 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1672 "op_flags" => "R|c",
1674 "comment" => "x87 fp Load pi: Ld pi -> reg",
1675 "reg_req" => { "out" => [ "vfp" ] },
1676 "emit" => '. fldpi /* x87 pi -> %D1 */',
1680 "op_flags" => "R|c",
1682 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1683 "reg_req" => { "out" => [ "vfp" ] },
1684 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1688 "op_flags" => "R|c",
1690 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1691 "reg_req" => { "out" => [ "vfp" ] },
1692 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1696 "op_flags" => "R|c",
1698 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1699 "reg_req" => { "out" => [ "vfp" ] },
1700 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1704 "op_flags" => "R|c",
1706 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1707 "reg_req" => { "out" => [ "vfp" ] },
1708 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1712 "op_flags" => "R|c",
1714 "rd_constructor" => "NONE",
1715 "comment" => "represents a x87 constant",
1716 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1717 "reg_req" => { "out" => [ "vfp" ] },
1718 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1722 # Note that it is NEVER allowed to do CSE on these nodes
1723 # Moreover, note the virtual register requierements!
1726 "op_flags" => "R|K",
1727 "comment" => "x87 stack exchange",
1729 "cmp_attr" => " return 1;\n",
1730 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1734 "op_flags" => "R|K",
1735 "comment" => "x87 stack push",
1737 "cmp_attr" => " return 1;\n",
1738 "emit" => '. fld %X1 /* x87 push %X1 */',
1743 "comment" => "x87 stack push",
1744 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1745 "cmp_attr" => " return 1;\n",
1746 "emit" => '. fld %X1 /* x87 push %X1 */',
1750 "op_flags" => "R|K",
1751 "comment" => "x87 stack pop",
1753 "cmp_attr" => " return 1;\n",
1754 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1760 "op_flags" => "L|X|Y",
1761 "comment" => "floating point compare",
1762 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1767 "op_flags" => "L|X|Y",
1768 "comment" => "floating point compare and pop",
1769 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1774 "op_flags" => "L|X|Y",
1775 "comment" => "floating point compare and pop twice",
1776 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1781 "op_flags" => "L|X|Y",
1782 "comment" => "floating point compare reverse",
1783 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1788 "op_flags" => "L|X|Y",
1789 "comment" => "floating point compare reverse and pop",
1790 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1795 "op_flags" => "L|X|Y",
1796 "comment" => "floating point compare reverse and pop twice",
1797 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",