3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
61 # state: state of the operation, OPTIONAL (default is "floats")
63 # arity: arity of the operation, MUST NOT BE OMITTED
65 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
66 # are always the first 3 arguments and are always autmatically
68 # If this key is missing the following arguments will be created:
69 # for i = 1 .. arity: ir_node *op_i
72 # comment: OPTIONAL comment for the node constructor
74 # rd_constructor: for every operation there will be a
75 # new_rd_<arch>_<op-name> function with the arguments from above
76 # which creates the ir_node corresponding to the defined operation
77 # you can either put the complete source code of this function here
79 # This key is OPTIONAL. If omitted, the following constructor will
81 # if (!op_<arch>_<op-name>) assert(0);
85 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
88 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
92 # 1 - caller save (register must be saved by the caller of a function)
93 # 2 - callee save (register must be saved by the called function)
94 # 4 - ignore (do not assign this register)
95 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
98 { "name" => "eax", "type" => 1 },
99 { "name" => "edx", "type" => 1 },
100 { "name" => "ebx", "type" => 2 },
101 { "name" => "ecx", "type" => 1 },
102 { "name" => "esi", "type" => 2 },
103 { "name" => "edi", "type" => 2 },
104 { "name" => "ebp", "type" => 2 },
105 { "name" => "esp", "type" => 4 },
106 { "name" => "gp_NOREG", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
107 { "mode" => "mode_P" }
110 { "name" => "xmm0", "type" => 1 },
111 { "name" => "xmm1", "type" => 1 },
112 { "name" => "xmm2", "type" => 1 },
113 { "name" => "xmm3", "type" => 1 },
114 { "name" => "xmm4", "type" => 1 },
115 { "name" => "xmm5", "type" => 1 },
116 { "name" => "xmm6", "type" => 1 },
117 { "name" => "xmm7", "type" => 1 },
118 { "name" => "xmm_NOREG", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
119 { "mode" => "mode_D" }
122 { "name" => "vf0", "type" => 1 },
123 { "name" => "vf1", "type" => 1 },
124 { "name" => "vf2", "type" => 1 },
125 { "name" => "vf3", "type" => 1 },
126 { "name" => "vf4", "type" => 1 },
127 { "name" => "vf5", "type" => 1 },
128 { "name" => "vf6", "type" => 1 },
129 { "name" => "vf7", "type" => 1 },
130 { "name" => "vfp_NOREG", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
131 { "mode" => "mode_E" }
134 { "name" => "st0", "type" => 1 },
135 { "name" => "st1", "type" => 1 },
136 { "name" => "st2", "type" => 1 },
137 { "name" => "st3", "type" => 1 },
138 { "name" => "st4", "type" => 1 },
139 { "name" => "st5", "type" => 1 },
140 { "name" => "st6", "type" => 1 },
141 { "name" => "st7", "type" => 1 },
142 { "name" => "st_NOREG", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
143 { "mode" => "mode_E" }
147 #--------------------------------------------------#
150 # _ __ _____ __ _ _ __ ___ _ __ ___ #
151 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
152 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
153 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
156 #--------------------------------------------------#
160 #-----------------------------------------------------------------#
163 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
164 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
165 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
166 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
169 #-----------------------------------------------------------------#
171 # commutative operations
174 # All nodes supporting Addressmode have 5 INs:
175 # 1 - base r1 == NoReg in case of no AM or no base
176 # 2 - index r2 == NoReg in case of no AM or no index
177 # 3 - op1 r3 == always present
178 # 4 - op2 r4 == NoReg in case of immediate operation
179 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
183 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
184 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
185 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
186 "emit" => '. add %ia32_emit_binop /* Add(%A1, %A2) -> %D1 */',
191 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
192 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
193 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
194 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */'
197 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
199 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
200 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
201 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
202 "emit" => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */'
207 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
208 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
209 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
210 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */'
215 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
216 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
217 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
218 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */'
223 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
224 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
225 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
226 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */'
231 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
232 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
234 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
235 if (mode_is_signed(get_irn_mode(n))) {
236 4. cmovl %D1, %S2 /* %S1 is less %S2 */
239 4. cmovb %D1, %S2 /* %S1 is below %S2 */
246 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
247 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
249 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
250 if (mode_is_signed(get_irn_mode(n))) {
251 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
254 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
261 "comment" => "construct Mux: Mux(sel, a, b) == sel ? a : b",
262 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r2" ] },
264 '. cmp %S1, 0 /* compare Sel for CMov (%A2, %A3) */
265 . cmovne %D1, %S3 /* sel == true -> return %S3 */
269 # not commutative operations
273 "comment" => "construct Sub: Sub(a, b) = a - b",
274 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
275 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
276 "emit" => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */'
281 "state" => "exc_pinned",
282 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
283 "attr" => "ia32_op_flavour_t dm_flav",
284 "init_attr" => " attr->data.op_flav = dm_flav;",
285 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
287 ' if (mode_is_signed(get_irn_mode(n))) {
288 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
291 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
298 "comment" => "construct Shl: Shl(a, b) = a << b",
299 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
300 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
301 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */'
306 "comment" => "construct Shr: Shr(a, b) = a >> b",
307 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
308 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
309 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */'
314 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
315 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
316 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
317 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */'
322 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
323 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
324 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
325 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */'
330 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
331 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
332 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
333 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */'
340 "comment" => "construct Minus: Minus(a) = -a",
341 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
342 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
343 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */'
348 "comment" => "construct Increment: Inc(a) = a++",
349 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
350 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
351 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */'
356 "comment" => "construct Decrement: Dec(a) = a--",
357 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
358 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
359 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */'
364 "comment" => "construct Not: Not(a) = !a",
365 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
366 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
367 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */'
373 "op_flags" => "L|X|Y",
374 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
375 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
376 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
380 "op_flags" => "L|X|Y",
381 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
382 "reg_req" => { "in" => [ "gp", "gp" ] },
383 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
387 "op_flags" => "L|X|Y",
388 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
389 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
390 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
394 "op_flags" => "L|X|Y",
395 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
396 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
397 "reg_req" => { "in" => [ "gp", "gp" ] },
401 "op_flags" => "L|X|Y",
402 "comment" => "construct switch",
403 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
404 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
410 "comment" => "represents an integer constant",
411 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
412 "reg_req" => { "out" => [ "gp" ] },
414 ' if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
415 4. sub %D1, %D1 /* optimized mov 0 to register */
418 if (get_ia32_op_type(n) == ia32_SymConst) {
419 6. mov %D1, OFFSET FLAT:%C /* Move address of SymConst into register */
422 6. mov %D1, %C /* Mov Const into register */
430 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
431 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
432 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */'
440 "state" => "exc_pinned",
441 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
442 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
443 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
445 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
446 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
449 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
456 "state" => "exc_pinned",
457 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
458 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
459 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
460 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
465 "state" => "exc_pinned",
466 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
467 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
468 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
469 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
474 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
475 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
476 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
477 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
481 "comment" => "push a gp register on the stack",
482 "reg_req" => { "in" => [ "esp", "gp", "none" ], "out" => [ "gp" ] },
483 "emit" => '. push %S2 /* Push(%A2) */'
487 "comment" => "pop a gp register from the stack",
488 "reg_req" => { "in" => [ "esp", "none" ], "out" => [ "gp", "esp" ] },
489 "emit" => '. pop %D1 /* Pop -> %D1 */'
493 "comment" => "create stack frame",
494 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
495 "emit" => '. enter /* Enter */'
499 "comment" => "destroy stack frame",
500 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "esp" ] },
501 "emit" => '. leave /* Enter */'
504 #-----------------------------------------------------------------------------#
505 # _____ _____ ______ __ _ _ _ #
506 # / ____/ ____| ____| / _| | | | | | #
507 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
508 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
509 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
510 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
511 #-----------------------------------------------------------------------------#
513 # commutative operations
517 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
518 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
519 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
520 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */'
525 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
526 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
527 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
528 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */'
533 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
534 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
535 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
536 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */'
541 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
542 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
543 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
544 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */'
549 "comment" => "construct SSE And: And(a, b) = a AND b",
550 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
551 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
552 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */'
557 "comment" => "construct SSE Or: Or(a, b) = a OR b",
558 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
559 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
560 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */'
565 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
566 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
567 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
568 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */'
571 # not commutative operations
575 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
576 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
577 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
578 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */'
583 "comment" => "construct SSE Div: Div(a, b) = a / b",
584 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
585 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
586 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */'
592 "op_flags" => "L|X|Y",
593 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
594 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
595 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
601 "comment" => "represents a SSE constant",
602 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
603 "reg_req" => { "out" => [ "xmm" ] },
604 "emit" => '. mov%M %D1, %C /* Load fConst into register */',
612 "state" => "exc_pinned",
613 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
614 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
615 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
616 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */'
621 "state" => "exc_pinned",
622 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
623 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
624 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
625 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */'
633 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
634 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
640 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
641 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
642 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
648 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
649 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
650 "comment" => "construct Conv Int -> Int"
654 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
655 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
656 "comment" => "construct Conv Int -> Int"
660 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
661 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
662 "comment" => "construct Conv Int -> Floating Point"
666 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
667 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
668 "comment" => "construct Conv Floating Point -> Int"
672 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
673 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
674 "comment" => "construct Conv Floating Point -> Floating Point",
677 #----------------------------------------------------------#
679 # (_) | | | | / _| | | | #
680 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
681 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
682 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
683 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
685 # _ __ ___ __| | ___ ___ #
686 # | '_ \ / _ \ / _` |/ _ \/ __| #
687 # | | | | (_) | (_| | __/\__ \ #
688 # |_| |_|\___/ \__,_|\___||___/ #
689 #----------------------------------------------------------#
693 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
694 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
695 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
700 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a + b",
701 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
702 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
707 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
708 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
709 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
713 "comment" => "virtual fp Div: Div(a, b) = a / b",
714 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
715 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
720 "comment" => "virtual fp Abs: Abs(a) = |a|",
721 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
726 "comment" => "virtual fp Chs: Chs(a) = -a",
727 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
732 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
733 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
738 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
739 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
744 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
745 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
748 # virtual Load and Store
753 "state" => "exc_pinned",
754 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
755 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
756 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp" ] },
761 "state" => "exc_pinned",
762 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
763 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
764 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
771 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
772 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
773 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp" ] },
777 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
778 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
779 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
786 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
787 "reg_req" => { "out" => [ "vfp" ] },
792 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
793 "reg_req" => { "out" => [ "vfp" ] },
798 "comment" => "virtual fp Load pi: Ld pi -> reg",
799 "reg_req" => { "out" => [ "vfp" ] },
804 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
805 "reg_req" => { "out" => [ "vfp" ] },
810 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
811 "reg_req" => { "out" => [ "vfp" ] },
816 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
817 "reg_req" => { "out" => [ "vfp" ] },
822 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
823 "reg_req" => { "out" => [ "vfp" ] },
829 "comment" => "represents a virtual floating point constant",
830 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
831 "reg_req" => { "out" => [ "vfp" ] },
834 #------------------------------------------------------------------------#
835 # ___ _____ __ _ _ _ #
836 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
837 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
838 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
839 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
840 #------------------------------------------------------------------------#
844 "rd_constructor" => "NONE",
845 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
847 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */'
852 "rd_constructor" => "NONE",
853 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
855 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A1, %A2) -> %D1 */'
860 "rd_constructor" => "NONE",
861 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
863 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */'
868 "rd_constructor" => "NONE",
869 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
871 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A1, %A2) -> %D1 */'
876 "rd_constructor" => "NONE",
877 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
879 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */'
884 "rd_constructor" => "NONE",
885 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
887 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A1, %A2) -> %D1 */'
892 "rd_constructor" => "NONE",
894 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
896 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */'
901 "rd_constructor" => "NONE",
903 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
905 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A1, %A2) -> %D1 */'
910 "rd_constructor" => "NONE",
911 "comment" => "x87 fp Div: Div(a, b) = a / b",
913 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
918 "rd_constructor" => "NONE",
919 "comment" => "x87 fp Div: Div(a, b) = a / b",
921 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A1, %A2) -> %D1 */'
926 "rd_constructor" => "NONE",
927 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
929 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
934 "rd_constructor" => "NONE",
935 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
937 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A1, %A2) -> %D1 */'
942 "rd_constructor" => "NONE",
943 "comment" => "x87 fp Abs: Abs(a) = |a|",
945 "emit" => '. fabs /* x87 fabs(%S1) -> %D1 */'
950 "rd_constructor" => "NONE",
951 "comment" => "x87 fp Chs: Chs(a) = -a",
953 "emit" => '. fchs /* x87 fchs(%S1) -> %D1 */'
958 "rd_constructor" => "NONE",
959 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
961 "emit" => '. fsin /* x87 sin(%S1) -> %D1 */'
966 "rd_constructor" => "NONE",
967 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
969 "emit" => '. fcos /* x87 cos(%S1) -> %D1 */'
974 "rd_constructor" => "NONE",
975 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
977 "emit" => '. fsqrt $ /* x87 sqrt(%S1) -> %D1 */'
983 "rd_constructor" => "NONE",
984 "op_flags" => "R|L|F",
985 "state" => "exc_pinned",
986 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
988 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */'
992 "rd_constructor" => "NONE",
993 "op_flags" => "R|L|F",
994 "state" => "exc_pinned",
995 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
997 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */'
1001 "rd_constructor" => "NONE",
1002 "op_flags" => "R|L|F",
1003 "state" => "exc_pinned",
1004 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1006 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */'
1014 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1016 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */'
1021 "rd_constructor" => "NONE",
1022 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1024 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */'
1029 "rd_constructor" => "NONE",
1030 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1032 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */'
1039 "rd_constructor" => "NONE",
1040 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1042 "emit" => '. fldz /* x87 0.0 -> %D1 */'
1047 "rd_constructor" => "NONE",
1048 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1050 "emit" => '. fld1 /* x87 1.0 -> %D1 */'
1055 "rd_constructor" => "NONE",
1056 "comment" => "x87 fp Load pi: Ld pi -> reg",
1058 "emit" => '. fldpi /* x87 pi -> %D1 */'
1063 "rd_constructor" => "NONE",
1064 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1066 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */'
1071 "rd_constructor" => "NONE",
1072 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1074 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */'
1079 "rd_constructor" => "NONE",
1080 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1082 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */'
1087 "rd_constructor" => "NONE",
1088 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1090 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */'
1097 "comment" => "represents a x87 constant",
1098 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1099 "reg_req" => { "out" => [ "st" ] },
1100 "emit" => '. fld%M %C /* Load fConst into register -> %D1 */',
1104 # Note that it is NEVER allowed to do CSE on these nodes
1107 "op_flags" => "R|K",
1108 "comment" => "x87 stack exchange",
1109 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1110 "cmp_attr" => " return 1;\n",
1111 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1116 "comment" => "x87 stack push",
1117 "reg_req" => { "in" => [ "st"], "out" => [ "st" ] },
1118 "cmp_attr" => " return 1;\n",
1119 "emit" => '. fld %X1 /* x87 push %X1 */',