3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
8 # this string marks the beginning of a comment in emit
9 $comment_string = "/*";
11 # the number of additional opcodes you want to register
12 #$additional_opcodes = 0;
14 # The node description is done as a perl hash initializer with the
15 # following structure:
20 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
21 # "irn_flags" => "R|N|I|S"
22 # "arity" => "0|1|2|3 ... |variable|dynamic|any",
23 # "state" => "floats|pinned|mem_pinned|exc_pinned",
25 # { "type" => "type 1", "name" => "name 1" },
26 # { "type" => "type 2", "name" => "name 2" },
29 # "comment" => "any comment for constructor",
30 # "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
31 # "cmp_attr" => "c source code for comparing node attributes",
32 # "emit" => "emit code with templates",
33 # "attr" => "attitional attribute arguments for constructor"
34 # "init_attr" => "emit attribute initialization template"
35 # "rd_constructor" => "c source code which constructs an ir_node"
36 # "latency" => "latency of this operation (can be float)"
39 # ... # (all nodes you need to describe)
41 # ); # close the %nodes initializer
43 # op_flags: flags for the operation, OPTIONAL (default is "N")
44 # the op_flags correspond to the firm irop_flags:
47 # C irop_flag_commutative
48 # X irop_flag_cfopcode
49 # I irop_flag_ip_cfopcode
52 # H irop_flag_highlevel
53 # c irop_flag_constlike
56 # irn_flags: special node flags, OPTIONAL (default is 0)
57 # following irn_flags are supported:
60 # I ignore for register allocation
61 # S modifies stack pointer
63 # state: state of the operation, OPTIONAL (default is "floats")
65 # arity: arity of the operation, MUST NOT BE OMITTED
67 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
68 # are always the first 3 arguments and are always autmatically
70 # If this key is missing the following arguments will be created:
71 # for i = 1 .. arity: ir_node *op_i
74 # outs: if a node defines more than one output, the names of the projections
75 # nodes having outs having automatically the mode mode_T
76 # One can also annotate some flags for each out, additional to irn_flags.
77 # They are separated from name with a colon ':', and concatenated by pipe '|'
78 # Only I and S are available at the moment (same meaning as in irn_flags).
79 # example: [ "frame:I", "stack:I|S", "M" ]
81 # comment: OPTIONAL comment for the node constructor
83 # rd_constructor: for every operation there will be a
84 # new_rd_<arch>_<op-name> function with the arguments from above
85 # which creates the ir_node corresponding to the defined operation
86 # you can either put the complete source code of this function here
88 # This key is OPTIONAL. If omitted, the following constructor will
90 # if (!op_<arch>_<op-name>) assert(0);
94 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
97 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
99 # latency: the latency of the operation, default is 1
103 # 0 - no special type
104 # 1 - caller save (register must be saved by the caller of a function)
105 # 2 - callee save (register must be saved by the called function)
106 # 4 - ignore (do not assign this register)
107 # 8 - emitter can choose an arbitrary register of this class
108 # 16 - the register is a virtual one
109 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
112 { "name" => "eax", "type" => 1 },
113 { "name" => "edx", "type" => 1 },
114 { "name" => "ebx", "type" => 2 },
115 { "name" => "ecx", "type" => 1 },
116 { "name" => "esi", "type" => 2 },
117 { "name" => "edi", "type" => 2 },
118 # { "name" => "r11", "type" => 1 },
119 # { "name" => "r12", "type" => 1 },
120 # { "name" => "r13", "type" => 1 },
121 # { "name" => "r14", "type" => 1 },
122 # { "name" => "r15", "type" => 1 },
123 # { "name" => "r16", "type" => 1 },
124 # { "name" => "r17", "type" => 1 },
125 # { "name" => "r18", "type" => 1 },
126 # { "name" => "r19", "type" => 1 },
127 # { "name" => "r20", "type" => 1 },
128 # { "name" => "r21", "type" => 1 },
129 # { "name" => "r22", "type" => 1 },
130 # { "name" => "r23", "type" => 1 },
131 # { "name" => "r24", "type" => 1 },
132 # { "name" => "r25", "type" => 1 },
133 # { "name" => "r26", "type" => 1 },
134 # { "name" => "r27", "type" => 1 },
135 # { "name" => "r28", "type" => 1 },
136 # { "name" => "r29", "type" => 1 },
137 # { "name" => "r30", "type" => 1 },
138 # { "name" => "r31", "type" => 1 },
139 # { "name" => "r32", "type" => 1 },
140 { "name" => "ebp", "type" => 2 },
141 { "name" => "esp", "type" => 4 },
142 { "name" => "gp_NOREG", "type" => 2 | 4 | 16 }, # we need a dummy register for NoReg nodes
143 { "name" => "gp_UKNWN", "type" => 2 | 4 | 8 | 16}, # we need a dummy register for Unknown nodes
144 { "mode" => "mode_P" }
147 { "name" => "xmm0", "type" => 1 },
148 { "name" => "xmm1", "type" => 1 },
149 { "name" => "xmm2", "type" => 1 },
150 { "name" => "xmm3", "type" => 1 },
151 { "name" => "xmm4", "type" => 1 },
152 { "name" => "xmm5", "type" => 1 },
153 { "name" => "xmm6", "type" => 1 },
154 { "name" => "xmm7", "type" => 1 },
155 { "name" => "xmm_NOREG", "type" => 2 | 4 | 16 }, # we need a dummy register for NoReg nodes
156 { "name" => "xmm_UKNWN", "type" => 2 | 4 | 8 | 16}, # we need a dummy register for Unknown nodes
157 { "mode" => "mode_D" }
160 { "name" => "vf0", "type" => 1 | 16 },
161 { "name" => "vf1", "type" => 1 | 16 },
162 { "name" => "vf2", "type" => 1 | 16 },
163 { "name" => "vf3", "type" => 1 | 16 },
164 { "name" => "vf4", "type" => 1 | 16 },
165 { "name" => "vf5", "type" => 1 | 16 },
166 { "name" => "vf6", "type" => 1 | 16 },
167 { "name" => "vf7", "type" => 1 | 16 },
168 { "name" => "vfp_NOREG", "type" => 2 | 4 | 16 }, # we need a dummy register for NoReg nodes
169 { "name" => "vfp_UKNWN", "type" => 2 | 4 | 8 | 16}, # we need a dummy register for Unknown nodes
170 { "mode" => "mode_E" }
173 { "name" => "st0", "type" => 1 },
174 { "name" => "st1", "type" => 1 },
175 { "name" => "st2", "type" => 1 },
176 { "name" => "st3", "type" => 1 },
177 { "name" => "st4", "type" => 1 },
178 { "name" => "st5", "type" => 1 },
179 { "name" => "st6", "type" => 1 },
180 { "name" => "st7", "type" => 1 },
181 { "mode" => "mode_E" }
185 #--------------------------------------------------#
188 # _ __ _____ __ _ _ __ ___ _ __ ___ #
189 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
190 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
191 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
194 #--------------------------------------------------#
201 #-----------------------------------------------------------------#
204 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
205 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
206 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
207 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
210 #-----------------------------------------------------------------#
212 # commutative operations
215 # All nodes supporting Addressmode have 5 INs:
216 # 1 - base r1 == NoReg in case of no AM or no base
217 # 2 - index r2 == NoReg in case of no AM or no index
218 # 3 - op1 r3 == always present
219 # 4 - op2 r4 == NoReg in case of immediate operation
220 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
224 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
225 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
226 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
227 "emit" => '. add %ia32_emit_binop /* Add(%A3, %A4) -> %D1 */',
228 "outs" => [ "res", "M" ],
232 "comment" => "construct Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
233 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
234 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
235 "emit" => '. adc %ia32_emit_binop /* AddC(%A3, %A4) -> %D1 */',
236 "outs" => [ "res", "M" ],
242 "cmp_attr" => " return 1;\n",
243 "comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
249 "cmp_attr" => " return 1;\n",
250 "comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
255 # we should not rematrialize this node. It produces 2 results and has
256 # very strict constrains
257 "comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
258 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
259 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
260 "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */',
261 "outs" => [ "EAX", "EDX", "M" ],
266 # we should not rematrialize this node. It produces 2 results and has
267 # very strict constrains
269 "cmp_attr" => " return 1;\n",
270 "comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
271 "outs" => [ "EAX", "EDX", "M" ],
277 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
278 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
279 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
280 "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
281 "outs" => [ "res", "M" ],
287 "cmp_attr" => " return 1;\n",
288 "comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
292 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
294 # we should not rematrialize this node. It produces 2 results and has
295 # very strict constrains
296 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
297 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
298 "reg_req" => { "in" => [ "gp", "gp", "eax", "gp", "none" ], "out" => [ "eax", "edx" ] },
299 "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */',
300 "outs" => [ "EAX", "EDX", "M" ],
306 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
307 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
308 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
309 "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */',
310 "outs" => [ "res", "M" ],
315 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
316 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
317 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
318 "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */',
319 "outs" => [ "res", "M" ],
324 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
325 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
326 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
327 "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */',
328 "outs" => [ "res", "M" ],
333 "cmp_attr" => " return 1;\n",
334 "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b",
340 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
341 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
343 '2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
344 if (mode_is_signed(get_irn_mode(n))) {
345 4. cmovl %D1, %S2 /* %S1 is less %S2 */
348 4. cmovb %D1, %S2 /* %S1 is below %S2 */
356 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
357 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
359 '2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
360 if (mode_is_signed(get_irn_mode(n))) {
361 2. cmovg %D1, %S2 /* %S1 is greater %S2 */
364 2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
370 # not commutative operations
374 "comment" => "construct Sub: Sub(a, b) = a - b",
375 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
376 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
377 "emit" => '. sub %ia32_emit_binop /* Sub(%A3, %A4) -> %D1 */',
378 "outs" => [ "res", "M" ],
382 "comment" => "construct Sub with Carry: SubC(a, b) = a - b - carry",
383 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
384 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3 !in_r4" ] },
385 "emit" => '. sbb %ia32_emit_binop /* SubC(%A3, %A4) -> %D1 */',
386 "outs" => [ "res", "M" ],
391 "cmp_attr" => " return 1;\n",
392 "comment" => "construct lowered Sub: Sub(a, b) = a - b",
397 "cmp_attr" => " return 1;\n",
398 "comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
404 "state" => "exc_pinned",
405 "reg_req" => { "in" => [ "eax", "gp", "edx", "none" ], "out" => [ "eax", "edx" ] },
406 "attr" => "ia32_op_flavour_t dm_flav",
407 "init_attr" => " attr->data.op_flav = dm_flav;",
408 "cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
410 ' if (mode_is_signed(get_ia32_res_mode(n))) {
411 4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
414 4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
417 "outs" => [ "div_res", "mod_res", "M" ],
423 "comment" => "construct Shl: Shl(a, b) = a << b",
424 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
425 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] },
426 "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */',
427 "outs" => [ "res", "M" ],
431 "cmp_attr" => " return 1;\n",
432 "comment" => "construct lowered Shl: Shl(a, b) = a << b",
438 "comment" => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
439 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
440 # Out requirements is: different from all in
441 # This is because, out must be different from LowPart and ShiftCount.
442 # We could say "!ecx !in_r4" but it can occur, that all values live through
443 # this Shift and the only value dying is the ShiftCount. Then there would be a
444 # register missing, as result must not be ecx and all other registers are
445 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
446 # (and probably never will). So we create artificial interferences of the result
447 # with all inputs, so the spiller can always assure a free register.
448 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
451 if (get_ia32_immop_type(n) == ia32_ImmNone) {
452 if (get_ia32_op_type(n) == ia32_AddrModeD) {
453 4. shld %ia32_emit_am, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
456 4. shld %S3, %S4, %%cl /* ShlD(%A3, %A4, %A5) -> %D1 */
460 if (get_ia32_op_type(n) == ia32_AddrModeD) {
461 4. shld %ia32_emit_am, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
464 4. shld %S3, %S4, %C /* ShlD(%A3, %A4, %A5) -> %D1 */
468 "outs" => [ "res", "M" ],
473 "cmp_attr" => " return 1;\n",
474 "comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
480 "comment" => "construct Shr: Shr(a, b) = a >> b",
481 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
482 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] },
483 "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */',
484 "outs" => [ "res", "M" ],
488 "cmp_attr" => " return 1;\n",
489 "comment" => "construct lowered Shr: Shr(a, b) = a << b",
495 "comment" => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
496 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
497 # Out requirements is: different from all in
498 # This is because, out must be different from LowPart and ShiftCount.
499 # We could say "!ecx !in_r4" but it can occur, that all values live through
500 # this Shift and the only value dying is the ShiftCount. Then there would be a
501 # register missing, as result must not be ecx and all other registers are
502 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
503 # (and probably never will). So we create artificial interferences of the result
504 # with all inputs, so the spiller can always assure a free register.
505 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "ecx", "none" ], "out" => [ "!in" ] },
508 if (get_ia32_immop_type(n) == ia32_ImmNone) {
509 if (get_ia32_op_type(n) == ia32_AddrModeD) {
510 4. shrd %ia32_emit_am, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
513 4. shrd %S3, %S4, %%cl /* ShrD(%A3, %A4, %A5) -> %D1 */
517 if (get_ia32_op_type(n) == ia32_AddrModeD) {
518 4. shrd %ia32_emit_am, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
521 4. shrd %S3, %S4, %C /* ShrD(%A3, %A4, %A5) -> %D1 */
525 "outs" => [ "res", "M" ],
530 "cmp_attr" => " return 1;\n",
531 "comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
537 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
538 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
539 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx gp_NOREG", "none" ], "out" => [ "in_r3 !in_r4" ] },
540 "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */',
541 "outs" => [ "res", "M" ],
545 "cmp_attr" => " return 1;\n",
546 "comment" => "construct lowered Shrs: Shrs(a, b) = a << b",
552 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
553 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
554 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
555 "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */',
556 "outs" => [ "res", "M" ],
561 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
562 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
563 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
564 "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */',
565 "outs" => [ "res", "M" ],
572 "comment" => "construct Minus: Minus(a) = -a",
573 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
574 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
575 "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */',
576 "outs" => [ "res", "M" ],
580 "cmp_attr" => " return 1;\n",
581 "comment" => "construct lowered Minus: Minus(a) = -a",
587 "comment" => "construct Increment: Inc(a) = a++",
588 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
589 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
590 "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */',
591 "outs" => [ "res", "M" ],
596 "comment" => "construct Decrement: Dec(a) = a--",
597 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
598 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
599 "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */',
600 "outs" => [ "res", "M" ],
605 "comment" => "construct Not: Not(a) = !a",
606 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
607 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
608 "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */',
609 "outs" => [ "res", "M" ],
615 "op_flags" => "L|X|Y",
616 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
617 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
618 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ] },
619 "outs" => [ "false", "true" ],
624 "op_flags" => "L|X|Y",
625 "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
626 "reg_req" => { "in" => [ "gp", "gp" ] },
627 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
628 "outs" => [ "false", "true" ],
633 "op_flags" => "L|X|Y",
634 "comment" => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
635 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
636 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
637 "outs" => [ "false", "true" ],
641 "op_flags" => "L|X|Y",
642 "comment" => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
643 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
644 "reg_req" => { "in" => [ "gp", "gp" ] },
648 "op_flags" => "L|X|Y",
649 "comment" => "construct switch",
650 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
651 "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
658 "comment" => "represents an integer constant",
659 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
660 "reg_req" => { "out" => [ "gp" ] },
664 # we should not rematrialize this node. It produces 2 results and has
665 # very strict constrains
666 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
667 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
668 "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */',
669 "outs" => [ "EAX", "EDX" ],
676 "state" => "exc_pinned",
677 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
678 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
679 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
682 ' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
683 4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
686 4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
689 "outs" => [ "res", "M" ],
694 "cmp_attr" => " return 1;\n",
695 "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
696 "outs" => [ "res", "M" ],
702 "cmp_attr" => " return 1;\n",
703 "state" => "exc_pinned",
704 "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
711 "state" => "exc_pinned",
712 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
713 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
714 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
715 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
722 "state" => "exc_pinned",
723 "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
724 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
725 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx gp_NOREG", "none" ] },
726 "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */',
733 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
734 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
735 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
736 "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */',
741 "comment" => "push on the stack",
742 "reg_req" => { "in" => [ "gp", "gp", "gp", "esp", "none" ], "out" => [ "esp" ] },
743 "emit" => '. push %ia32_emit_unop /* PUSH(%A1) */',
744 "outs" => [ "stack:I|S", "M" ],
749 # We don't set class modify stack here (but we will do this on proj 1)
750 "comment" => "pop a gp register from the stack",
751 "reg_req" => { "in" => [ "gp", "gp", "esp", "none" ], "out" => [ "gp", "esp" ] },
752 "emit" => '. pop %ia32_emit_unop /* POP(%A1) */',
753 "outs" => [ "res", "stack:I|S", "M" ],
758 "comment" => "create stack frame",
759 "reg_req" => { "in" => [ "esp" ], "out" => [ "ebp", "esp" ] },
760 "emit" => '. enter /* Enter */',
761 "outs" => [ "frame:I", "stack:I|S", "M" ],
766 "comment" => "destroy stack frame",
767 "reg_req" => { "in" => [ "esp", "ebp" ], "out" => [ "ebp", "esp" ] },
768 "emit" => '. leave /* Leave */',
769 "outs" => [ "frame:I", "stack:I|S", "M" ],
775 "comment" => "allocate space on stack",
776 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
777 "outs" => [ "stack:S", "M" ],
782 "comment" => "free space on stack",
783 "reg_req" => { "in" => [ "esp", "gp" ], "out" => [ "esp", "none" ] },
784 "outs" => [ "stack:S", "M" ],
789 "comment" => "get the TLS base address",
790 "reg_req" => { "out" => [ "gp" ] },
795 #-----------------------------------------------------------------------------#
796 # _____ _____ ______ __ _ _ _ #
797 # / ____/ ____| ____| / _| | | | | | #
798 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
799 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
800 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
801 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
802 #-----------------------------------------------------------------------------#
804 # commutative operations
808 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
809 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
810 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
811 "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */',
812 "outs" => [ "res", "M" ],
818 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
819 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
820 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
821 "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */',
822 "outs" => [ "res", "M" ],
828 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
829 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
830 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
831 "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */',
832 "outs" => [ "res", "M" ],
838 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
839 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
840 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
841 "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */',
842 "outs" => [ "res", "M" ],
848 "comment" => "construct SSE And: And(a, b) = a AND b",
849 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
850 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
851 "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */',
852 "outs" => [ "res", "M" ],
858 "comment" => "construct SSE Or: Or(a, b) = a OR b",
859 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
860 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
861 "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */',
862 "outs" => [ "res", "M" ],
867 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
868 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
869 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
870 "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */',
871 "outs" => [ "res", "M" ],
875 # not commutative operations
879 "comment" => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
880 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
881 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
882 "emit" => '. andnp%M %ia32_emit_binop /* SSE AndNot(%A3, %A4) -> %D1 */',
883 "outs" => [ "res", "M" ],
889 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
890 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
891 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
892 "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */',
893 "outs" => [ "res", "M" ],
899 "comment" => "construct SSE Div: Div(a, b) = a / b",
900 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
901 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
902 "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */',
903 "outs" => [ "res", "M" ],
911 "comment" => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
912 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
913 "outs" => [ "res", "M" ],
918 "op_flags" => "L|X|Y",
919 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
920 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
921 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "none", "none" ] },
922 "outs" => [ "false", "true" ],
929 "comment" => "represents a SSE constant",
930 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
931 "reg_req" => { "out" => [ "xmm" ] },
932 "emit" => '. movs%M %D1, %C /* Load fConst into register */',
940 "state" => "exc_pinned",
941 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
942 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
943 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "xmm" ] },
944 "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */',
945 "outs" => [ "res", "M" ],
951 "state" => "exc_pinned",
952 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
953 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
954 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ] },
955 "emit" => '. movs%M %ia32_emit_binop /* Store(%S3) -> (%A1) */',
962 "state" => "exc_pinned",
963 "comment" => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
964 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
965 "reg_req" => { "in" => [ "gp", "xmm", "none" ] },
966 "emit" => '. movs%M %ia32_emit_am, %S2 /* store XMM0 onto stack */',
973 "comment" => "construct: transfer a value from x87 FPU into a SSE register",
974 "cmp_attr" => " return 1;\n",
980 "comment" => "construct: transfer a value from SSE register to x87 FPU",
981 "cmp_attr" => " return 1;\n",
988 "state" => "exc_pinned",
989 "comment" => "store ST0 onto stack",
990 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
991 "reg_req" => { "in" => [ "gp", "none" ] },
992 "emit" => '. fstp %ia32_emit_am /* store ST0 onto stack */',
1000 "state" => "exc_pinned",
1001 "comment" => "load ST0 from stack",
1002 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1003 "reg_req" => { "in" => [ "gp", "none" ], "out" => [ "vf0", "none" ] },
1004 "emit" => '. fld %ia32_emit_am /* load ST0 from stack */',
1005 "outs" => [ "res", "M" ],
1012 "op_flags" => "F|H",
1013 "state" => "pinned",
1014 "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1015 "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "edi", "esi", "ecx", "none" ] },
1016 "outs" => [ "DST", "SRC", "CNT", "M" ],
1020 "op_flags" => "F|H",
1021 "state" => "pinned",
1022 "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1023 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1024 "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "edi", "esi", "none" ] },
1025 "outs" => [ "DST", "SRC", "M" ],
1031 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3", "none" ] },
1032 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1033 "comment" => "construct Conv Int -> Int",
1034 "outs" => [ "res", "M" ],
1038 "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ], "out" => [ "in_r3", "none" ] },
1039 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1040 "comment" => "construct Conv Int -> Int",
1041 "outs" => [ "res", "M" ],
1045 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "xmm", "none" ] },
1046 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1047 "comment" => "construct Conv Int -> Floating Point",
1048 "outs" => [ "res", "M" ],
1053 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "gp", "none" ] },
1054 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1055 "comment" => "construct Conv Floating Point -> Int",
1056 "outs" => [ "res", "M" ],
1061 "reg_req" => { "in" => [ "gp", "gp", "xmm", "none" ], "out" => [ "xmm", "none" ] },
1062 "cmp_attr" => " return ia32_compare_conv_attr(attr_a, attr_b);\n",
1063 "comment" => "construct Conv Floating Point -> Floating Point",
1064 "outs" => [ "res", "M" ],
1070 "comment" => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1071 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp" ], "out" => [ "in_r4" ] },
1077 "comment" => "check if Psi condition tree evaluates to true and move result accordingly",
1078 "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r3" ] },
1084 "comment" => "construct Conditional Move: SSE Compare + int CMov ",
1085 "reg_req" => { "in" => [ "xmm", "xmm", "gp", "gp" ], "out" => [ "in_r4" ] },
1091 "comment" => "construct Conditional Move: x87 Compare + int CMov",
1092 "reg_req" => { "in" => [ "vfp", "vfp", "gp", "gp" ], "out" => [ "in_r4" ] },
1098 "comment" => "construct Set: Set(sel) == sel ? 1 : 0",
1099 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1100 "outs" => [ "res", "M" ],
1106 "comment" => "check if Psi condition tree evaluates to true and set result accordingly",
1107 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax ebx ecx edx" ] },
1113 "comment" => "construct Set: SSE Compare + int Set",
1114 "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1115 "outs" => [ "res", "M" ],
1121 "comment" => "construct Set: x87 Compare + int Set",
1122 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "eax ebx ecx edx", "none" ] },
1123 "outs" => [ "res", "M" ],
1129 "comment" => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1130 "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
1134 #----------------------------------------------------------#
1136 # (_) | | | | / _| | | | #
1137 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1138 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1139 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1140 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1142 # _ __ ___ __| | ___ ___ #
1143 # | '_ \ / _ \ / _` |/ _ \/ __| #
1144 # | | | | (_) | (_| | __/\__ \ #
1145 # |_| |_|\___/ \__,_|\___||___/ #
1146 #----------------------------------------------------------#
1150 "comment" => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1151 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1152 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1153 "outs" => [ "res", "M" ],
1159 "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1160 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1161 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1162 "outs" => [ "res", "M" ],
1168 "cmp_attr" => " return 1;\n",
1169 "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1175 "comment" => "virtual fp Sub: Sub(a, b) = a - b",
1176 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1177 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1178 "outs" => [ "res", "M" ],
1183 "cmp_attr" => " return 1;\n",
1184 "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
1189 "comment" => "virtual fp Div: Div(a, b) = a / b",
1190 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1191 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
1192 "outs" => [ "res", "M" ],
1197 "cmp_attr" => " return 1;\n",
1198 "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
1204 "comment" => "virtual fp Abs: Abs(a) = |a|",
1205 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1211 "comment" => "virtual fp Chs: Chs(a) = -a",
1212 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1218 "comment" => "virtual fp Sin: Sin(a) = sin(a)",
1219 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1225 "comment" => "virtual fp Cos: Cos(a) = cos(a)",
1226 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1232 "comment" => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1233 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1237 # virtual Load and Store
1240 "op_flags" => "L|F",
1241 "state" => "exc_pinned",
1242 "comment" => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1243 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1244 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1245 "outs" => [ "res", "M" ],
1250 "op_flags" => "L|F",
1251 "state" => "exc_pinned",
1252 "comment" => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1253 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1254 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1262 "comment" => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1263 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1264 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "vfp", "none" ] },
1265 "outs" => [ "res", "M" ],
1270 "cmp_attr" => " return 1;\n",
1271 "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1272 "outs" => [ "res", "M" ],
1277 "comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1278 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1279 "reg_req" => { "in" => [ "gp", "gp", "vfp", "none" ] },
1285 "cmp_attr" => " return 1;\n",
1286 "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1296 "comment" => "virtual fp Load 0.0: Ld 0.0 -> reg",
1297 "reg_req" => { "out" => [ "vfp" ] },
1303 "comment" => "virtual fp Load 1.0: Ld 1.0 -> reg",
1304 "reg_req" => { "out" => [ "vfp" ] },
1310 "comment" => "virtual fp Load pi: Ld pi -> reg",
1311 "reg_req" => { "out" => [ "vfp" ] },
1317 "comment" => "virtual fp Load ln 2: Ld ln 2 -> reg",
1318 "reg_req" => { "out" => [ "vfp" ] },
1324 "comment" => "virtual fp Load lg 2: Ld lg 2 -> reg",
1325 "reg_req" => { "out" => [ "vfp" ] },
1331 "comment" => "virtual fp Load ld 10: Ld ld 10 -> reg",
1332 "reg_req" => { "out" => [ "vfp" ] },
1338 "comment" => "virtual fp Load ld e: Ld ld e -> reg",
1339 "reg_req" => { "out" => [ "vfp" ] },
1346 "init_attr" => " set_ia32_ls_mode(res, mode);",
1347 "comment" => "represents a virtual floating point constant",
1348 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1349 "reg_req" => { "out" => [ "vfp" ] },
1356 "op_flags" => "L|X|Y",
1357 "comment" => "represents a virtual floating point compare",
1358 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1359 "reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "none", "none", "eax" ] },
1360 "outs" => [ "false", "true", "temp_reg_eax" ],
1364 #------------------------------------------------------------------------#
1365 # ___ _____ __ _ _ _ #
1366 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1367 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1368 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1369 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1370 #------------------------------------------------------------------------#
1374 "rd_constructor" => "NONE",
1375 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1377 "emit" => '. fadd %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1382 "rd_constructor" => "NONE",
1383 "comment" => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1385 "emit" => '. faddp %ia32_emit_x87_binop /* x87 fadd(%A3, %A4) -> %D1 */',
1390 "rd_constructor" => "NONE",
1391 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1393 "emit" => '. fmul %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',
1398 "rd_constructor" => "NONE",
1399 "comment" => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1401 "emit" => '. fmulp %ia32_emit_x87_binop /* x87 fmul(%A3, %A4) -> %D1 */',,
1406 "rd_constructor" => "NONE",
1407 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1409 "emit" => '. fsub %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1414 "rd_constructor" => "NONE",
1415 "comment" => "x87 fp Sub: Sub(a, b) = a - b",
1417 "emit" => '. fsubp %ia32_emit_x87_binop /* x87 fsub(%A3, %A4) -> %D1 */',
1422 "rd_constructor" => "NONE",
1424 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1426 "emit" => '. fsubr %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1431 "rd_constructor" => "NONE",
1433 "comment" => "x87 fp SubR: SubR(a, b) = b - a",
1435 "emit" => '. fsubrp %ia32_emit_x87_binop /* x87 fsubr(%A3, %A4) -> %D1 */',
1440 "rd_constructor" => "NONE",
1441 "comment" => "x87 fp Div: Div(a, b) = a / b",
1443 "emit" => '. fdiv %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1448 "rd_constructor" => "NONE",
1449 "comment" => "x87 fp Div: Div(a, b) = a / b",
1451 "emit" => '. fdivp %ia32_emit_x87_binop /* x87 fdiv(%A3, %A4) -> %D1 */',
1456 "rd_constructor" => "NONE",
1457 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1459 "emit" => '. fdivr %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1464 "rd_constructor" => "NONE",
1465 "comment" => "x87 fp DivR: DivR(a, b) = b / a",
1467 "emit" => '. fdivrp %ia32_emit_x87_binop /* x87 fdivr(%A3, %A4) -> %D1 */',
1472 "rd_constructor" => "NONE",
1473 "comment" => "x87 fp Abs: Abs(a) = |a|",
1475 "emit" => '. fabs /* x87 fabs(%A1) -> %D1 */',
1480 "rd_constructor" => "NONE",
1481 "comment" => "x87 fp Chs: Chs(a) = -a",
1483 "emit" => '. fchs /* x87 fchs(%A1) -> %D1 */',
1488 "rd_constructor" => "NONE",
1489 "comment" => "x87 fp Sin: Sin(a) = sin(a)",
1491 "emit" => '. fsin /* x87 sin(%A1) -> %D1 */',
1496 "rd_constructor" => "NONE",
1497 "comment" => "x87 fp Cos: Cos(a) = cos(a)",
1499 "emit" => '. fcos /* x87 cos(%A1) -> %D1 */',
1504 "rd_constructor" => "NONE",
1505 "comment" => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1507 "emit" => '. fsqrt $ /* x87 sqrt(%A1) -> %D1 */',
1510 # x87 Load and Store
1513 "rd_constructor" => "NONE",
1514 "op_flags" => "R|L|F",
1515 "state" => "exc_pinned",
1516 "comment" => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1518 "emit" => '. fld %ia32_emit_am /* Load((%A1)) -> %D1 */',
1522 "rd_constructor" => "NONE",
1523 "op_flags" => "R|L|F",
1524 "state" => "exc_pinned",
1525 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1527 "emit" => '. fst %ia32_emit_am /* Store(%A3) -> (%A1) */',
1531 "rd_constructor" => "NONE",
1532 "op_flags" => "R|L|F",
1533 "state" => "exc_pinned",
1534 "comment" => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1536 "emit" => '. fstp %ia32_emit_am /* Store(%A3) -> (%A1) and pop */',
1543 "rd_constructor" => "NONE",
1544 "comment" => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1546 "emit" => '. fild %ia32_emit_am /* integer Load((%A1)) -> %D1 */',
1551 "rd_constructor" => "NONE",
1552 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1554 "emit" => '. fist %ia32_emit_am /* integer Store(%A3) -> (%A1) */',
1559 "rd_constructor" => "NONE",
1560 "comment" => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1562 "emit" => '. fistp %ia32_emit_am /* integer Store(%A3) -> (%A1) and pop */',
1568 "op_flags" => "R|c",
1570 "comment" => "x87 fp Load 0.0: Ld 0.0 -> reg",
1571 "reg_req" => { "out" => [ "vfp" ] },
1572 "emit" => '. fldz /* x87 0.0 -> %D1 */',
1576 "op_flags" => "R|c",
1578 "comment" => "x87 fp Load 1.0: Ld 1.0 -> reg",
1579 "reg_req" => { "out" => [ "vfp" ] },
1580 "emit" => '. fld1 /* x87 1.0 -> %D1 */',
1584 "op_flags" => "R|c",
1586 "comment" => "x87 fp Load pi: Ld pi -> reg",
1587 "reg_req" => { "out" => [ "vfp" ] },
1588 "emit" => '. fldpi /* x87 pi -> %D1 */',
1592 "op_flags" => "R|c",
1594 "comment" => "x87 fp Load ln 2: Ld ln 2 -> reg",
1595 "reg_req" => { "out" => [ "vfp" ] },
1596 "emit" => '. fldln2 /* x87 ln(2) -> %D1 */',
1600 "op_flags" => "R|c",
1602 "comment" => "x87 fp Load lg 2: Ld lg 2 -> reg",
1603 "reg_req" => { "out" => [ "vfp" ] },
1604 "emit" => '. fldlg2 /* x87 log(2) -> %D1 */',
1608 "op_flags" => "R|c",
1610 "comment" => "x87 fp Load ld 10: Ld ld 10 -> reg",
1611 "reg_req" => { "out" => [ "vfp" ] },
1612 "emit" => '. fldll2t /* x87 ld(10) -> %D1 */',
1616 "op_flags" => "R|c",
1618 "comment" => "x87 fp Load ld e: Ld ld e -> reg",
1619 "reg_req" => { "out" => [ "vfp" ] },
1620 "emit" => '. fldl2e /* x87 ld(e) -> %D1 */',
1624 "op_flags" => "R|c",
1626 "rd_constructor" => "NONE",
1627 "comment" => "represents a x87 constant",
1628 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1629 "reg_req" => { "out" => [ "vfp" ] },
1630 "emit" => '. fld %ia32_emit_adr /* Load fConst into register -> %D1 */',
1634 # Note that it is NEVER allowed to do CSE on these nodes
1635 # Moreover, note the virtual register requierements!
1638 "op_flags" => "R|K",
1639 "comment" => "x87 stack exchange",
1641 "cmp_attr" => " return 1;\n",
1642 "emit" => '. fxch %X1 /* x87 swap %X1, %X3 */',
1646 "op_flags" => "R|K",
1647 "comment" => "x87 stack push",
1649 "cmp_attr" => " return 1;\n",
1650 "emit" => '. fld %X1 /* x87 push %X1 */',
1655 "comment" => "x87 stack push",
1656 "reg_req" => { "in" => [ "vfp"], "out" => [ "vfp" ] },
1657 "cmp_attr" => " return 1;\n",
1658 "emit" => '. fld %X1 /* x87 push %X1 */',
1662 "op_flags" => "R|K",
1663 "comment" => "x87 stack pop",
1665 "cmp_attr" => " return 1;\n",
1666 "emit" => '. fstp %X1 /* x87 pop %X1 */',
1672 "op_flags" => "L|X|Y",
1673 "comment" => "floating point compare",
1674 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1679 "op_flags" => "L|X|Y",
1680 "comment" => "floating point compare and pop",
1681 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1686 "op_flags" => "L|X|Y",
1687 "comment" => "floating point compare and pop twice",
1688 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1693 "op_flags" => "L|X|Y",
1694 "comment" => "floating point compare reverse",
1695 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1700 "op_flags" => "L|X|Y",
1701 "comment" => "floating point compare reverse and pop",
1702 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
1707 "op_flags" => "L|X|Y",
1708 "comment" => "floating point compare reverse and pop twice",
1709 "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",