3 # This is the specification for the ia32 assembler Firm-operations
10 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
13 # The node description is done as a perl hash initializer with the
14 # following structure:
19 # op_flags => "N|L|C|X|I|F|Y|H|c|K",
20 # irn_flags => "R|N|I|S"
21 # arity => "0|1|2|3 ... |variable|dynamic|any",
22 # state => "floats|pinned|mem_pinned|exc_pinned",
24 # { type => "type 1", name => "name 1" },
25 # { type => "type 2", name => "name 2" },
28 # comment => "any comment for constructor",
29 # reg_req => { in => [ "reg_class|register" ], out => [ "reg_class|register|in_rX" ] },
30 # cmp_attr => "c source code for comparing node attributes",
31 # emit => "emit code with templates",
32 # attr => "attitional attribute arguments for constructor"
33 # init_attr => "emit attribute initialization template"
34 # rd_constructor => "c source code which constructs an ir_node"
35 # latency => "latency of this operation (can be float)"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
60 # S modifies stack pointer
62 # state: state of the operation, OPTIONAL (default is "floats")
64 # arity: arity of the operation, MUST NOT BE OMITTED
66 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
67 # are always the first 3 arguments and are always autmatically
69 # If this key is missing the following arguments will be created:
70 # for i = 1 .. arity: ir_node *op_i
73 # outs: if a node defines more than one output, the names of the projections
74 # nodes having outs having automatically the mode mode_T
75 # One can also annotate some flags for each out, additional to irn_flags.
76 # They are separated from name with a colon ':', and concatenated by pipe '|'
77 # Only I and S are available at the moment (same meaning as in irn_flags).
78 # example: [ "frame:I", "stack:I|S", "M" ]
80 # comment: OPTIONAL comment for the node constructor
82 # rd_constructor: for every operation there will be a
83 # new_rd_<arch>_<op-name> function with the arguments from above
84 # which creates the ir_node corresponding to the defined operation
85 # you can either put the complete source code of this function here
87 # This key is OPTIONAL. If omitted, the following constructor will
89 # if (!op_<arch>_<op-name>) assert(0);
93 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
96 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
98 # latency: the latency of the operation, default is 1
102 # 0 - no special type
103 # 1 - caller save (register must be saved by the caller of a function)
104 # 2 - callee save (register must be saved by the called function)
105 # 4 - ignore (do not assign this register)
106 # 8 - emitter can choose an arbitrary register of this class
107 # 16 - the register is a virtual one
108 # 32 - register represents a state
109 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
112 { name => "eax", type => 1 },
113 { name => "edx", type => 1 },
114 { name => "ebx", type => 2 },
115 { name => "ecx", type => 1 },
116 { name => "esi", type => 2 },
117 { name => "edi", type => 2 },
118 { name => "ebp", type => 2 },
119 { name => "esp", type => 4 },
120 { name => "gp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
121 { name => "gp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
122 { mode => "mode_Iu" }
125 { name => "xmm0", type => 1 },
126 { name => "xmm1", type => 1 },
127 { name => "xmm2", type => 1 },
128 { name => "xmm3", type => 1 },
129 { name => "xmm4", type => 1 },
130 { name => "xmm5", type => 1 },
131 { name => "xmm6", type => 1 },
132 { name => "xmm7", type => 1 },
133 { name => "xmm_NOREG", type => 4 | 16 }, # we need a dummy register for NoReg nodes
134 { name => "xmm_UKNWN", type => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
138 { name => "vf0", type => 1 | 16 },
139 { name => "vf1", type => 1 | 16 },
140 { name => "vf2", type => 1 | 16 },
141 { name => "vf3", type => 1 | 16 },
142 { name => "vf4", type => 1 | 16 },
143 { name => "vf5", type => 1 | 16 },
144 { name => "vf6", type => 1 | 16 },
145 { name => "vf7", type => 1 | 16 },
146 { name => "vfp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
147 { name => "vfp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
151 { name => "st0", realname => "st", type => 4 },
152 { name => "st1", realname => "st(1)", type => 4 },
153 { name => "st2", realname => "st(2)", type => 4 },
154 { name => "st3", realname => "st(3)", type => 4 },
155 { name => "st4", realname => "st(4)", type => 4 },
156 { name => "st5", realname => "st(5)", type => 4 },
157 { name => "st6", realname => "st(6)", type => 4 },
158 { name => "st7", realname => "st(7)", type => 4 },
161 fp_cw => [ # the floating point control word
162 { name => "fpcw", type => 4 | 32},
163 { mode => "mode_fpcw" }
166 { name => "eflags", type => 4 },
167 { mode => "mode_Iu" }
170 { name => "fpsw", type => 4 },
171 { mode => "mode_Hu" }
176 CF => { reg => "eflags", bit => 0 },
177 PF => { reg => "eflags", bit => 2 },
178 AF => { reg => "eflags", bit => 4 },
179 ZF => { reg => "eflags", bit => 6 },
180 SF => { reg => "eflags", bit => 7 },
181 TF => { reg => "eflags", bit => 8 },
182 IF => { reg => "eflags", bit => 9 },
183 DF => { reg => "eflags", bit => 10 },
184 OF => { reg => "eflags", bit => 11 },
185 IOPL0 => { reg => "eflags", bit => 12 },
186 IOPL1 => { reg => "eflags", bit => 13 },
187 NT => { reg => "eflags", bit => 14 },
188 RF => { reg => "eflags", bit => 16 },
189 VM => { reg => "eflags", bit => 17 },
190 AC => { reg => "eflags", bit => 18 },
191 VIF => { reg => "eflags", bit => 19 },
192 VIP => { reg => "eflags", bit => 20 },
193 ID => { reg => "eflags", bit => 21 },
195 FP_IE => { reg => "fpsw", bit => 0 },
196 FP_DE => { reg => "fpsw", bit => 1 },
197 FP_ZE => { reg => "fpsw", bit => 2 },
198 FP_OE => { reg => "fpsw", bit => 3 },
199 FP_UE => { reg => "fpsw", bit => 4 },
200 FP_PE => { reg => "fpsw", bit => 5 },
201 FP_SF => { reg => "fpsw", bit => 6 },
202 FP_ES => { reg => "fpsw", bit => 7 },
203 FP_C0 => { reg => "fpsw", bit => 8 },
204 FP_C1 => { reg => "fpsw", bit => 9 },
205 FP_C2 => { reg => "fpsw", bit => 10 },
206 FP_TOP0 => { reg => "fpsw", bit => 11 },
207 FP_TOP1 => { reg => "fpsw", bit => 12 },
208 FP_TOP2 => { reg => "fpsw", bit => 13 },
209 FP_C3 => { reg => "fpsw", bit => 14 },
210 FP_B => { reg => "fpsw", bit => 15 },
212 FP_IM => { reg => "fpcw", bit => 0 },
213 FP_DM => { reg => "fpcw", bit => 1 },
214 FP_ZM => { reg => "fpcw", bit => 2 },
215 FP_OM => { reg => "fpcw", bit => 3 },
216 FP_UM => { reg => "fpcw", bit => 4 },
217 FP_PM => { reg => "fpcw", bit => 5 },
218 FP_PC0 => { reg => "fpcw", bit => 8 },
219 FP_PC1 => { reg => "fpcw", bit => 9 },
220 FP_RC0 => { reg => "fpcw", bit => 10 },
221 FP_RC1 => { reg => "fpcw", bit => 11 },
222 FP_X => { reg => "fpcw", bit => 12 }
226 GP => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ],
227 SSE => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ],
228 VFP => [ 1, "VFP_VF0", "VFP_VF1", "VFP_VF2", "VFP_VF3", "VFP_VF4", "VFP_VF5", "VFP_VF6", "VFP_VF7" ],
229 BRANCH => [ 1, "BRANCH1", "BRANCH2" ],
234 bundels_per_cycle => 1
238 S0 => "${arch}_emit_source_register(env, node, 0);",
239 S1 => "${arch}_emit_source_register(env, node, 1);",
240 S2 => "${arch}_emit_source_register(env, node, 2);",
241 S3 => "${arch}_emit_source_register(env, node, 3);",
242 S4 => "${arch}_emit_source_register(env, node, 4);",
243 S5 => "${arch}_emit_source_register(env, node, 5);",
244 D0 => "${arch}_emit_dest_register(env, node, 0);",
245 D1 => "${arch}_emit_dest_register(env, node, 1);",
246 D2 => "${arch}_emit_dest_register(env, node, 2);",
247 D3 => "${arch}_emit_dest_register(env, node, 3);",
248 D4 => "${arch}_emit_dest_register(env, node, 4);",
249 D5 => "${arch}_emit_dest_register(env, node, 5);",
250 X0 => "${arch}_emit_x87_name(env, node, 0);",
251 X1 => "${arch}_emit_x87_name(env, node, 1);",
252 X2 => "${arch}_emit_x87_name(env, node, 2);",
253 C => "${arch}_emit_immediate(env, node);",
254 SE => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));",
255 ME => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
256 ia32_emit_mode_suffix(env, node);",
257 M => "${arch}_emit_mode_suffix(env, node);",
258 XM => "${arch}_emit_x87_mode_suffix(env, node);",
259 XXM => "${arch}_emit_xmm_mode_suffix(env, node);",
260 XSD => "${arch}_emit_xmm_mode_suffix_s(env, node);",
261 AM => "${arch}_emit_am(env, node);",
262 unop => "${arch}_emit_unop(env, node);",
263 binop => "${arch}_emit_binop(env, node);",
264 x87_binop => "${arch}_emit_x87_binop(env, node);",
267 #--------------------------------------------------#
270 # _ __ _____ __ _ _ __ ___ _ __ ___ #
271 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
272 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
273 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
276 #--------------------------------------------------#
278 $default_cmp_attr = "return ia32_compare_attr(attr_a, attr_b);";
283 $mode_xmm = "mode_E";
284 $mode_gp = "mode_Iu";
285 $mode_fpcw = "mode_fpcw";
286 $status_flags = [ "CF", "PF", "AF", "ZF", "SF", "OF" ];
287 $fpcw_flags = [ "FP_IM", "FP_DM", "FP_ZM", "FP_OM", "FP_UM", "FP_PM",
288 "FP_PC0", "FP_PC1", "FP_RC0", "FP_RC1", "FP_X" ];
292 #-----------------------------------------------------------------#
295 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
296 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
297 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
298 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
301 #-----------------------------------------------------------------#
303 # commutative operations
306 # All nodes supporting Addressmode have 5 INs:
307 # 1 - base r1 == NoReg in case of no AM or no base
308 # 2 - index r2 == NoReg in case of no AM or no index
309 # 3 - op1 r3 == always present
310 # 4 - op2 r4 == NoReg in case of immediate operation
311 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
315 comment => "construct Add: Add(a, b) = Add(b, a) = a + b",
316 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
317 ins => [ "base", "index", "left", "right", "mem" ],
318 emit => '. add%M %binop',
321 modified_flags => $status_flags
325 comment => "construct Add with Carry: Adc(a, b) = Add(b, a) = a + b + carry",
326 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
327 emit => '. adc%M %binop',
330 modified_flags => $status_flags
335 comment => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
337 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
344 outs => [ "low_res", "high_res" ],
346 modified_flags => $status_flags
352 cmp_attr => "return 1;",
353 comment => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
359 cmp_attr => "return 1;",
360 comment => "construct lowered Add with Carry: Adc(a, b) = Adc(b, a) = a + b + carry",
365 # we should not rematrialize this node. It produces 2 results and has
366 # very strict constrains
367 comment => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
368 reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
369 emit => '. mul%M %unop',
370 outs => [ "EAX", "EDX", "M" ],
373 modified_flags => $status_flags
377 # we should not rematrialize this node. It produces 2 results and has
378 # very strict constrains
380 cmp_attr => "return 1;",
381 comment => "construct lowered MulS: Mul(a, b) = Mul(b, a) = a * b",
382 outs => [ "EAX", "EDX", "M" ],
388 comment => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
389 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
390 emit => '. imul%M %binop',
394 modified_flags => $status_flags
399 comment => "construct Mul (1 operand format): Mul(a, b) = Mul(b, a) = a * b",
400 reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
401 emit => '. imul%M %unop',
402 outs => [ "EAX", "EDX", "M" ],
405 modified_flags => $status_flags
410 cmp_attr => "return 1;",
411 comment => "construct lowered IMul: IMul(a, b) = IMul(b, a) = a * b",
417 comment => "construct And: And(a, b) = And(b, a) = a AND b",
418 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
419 emit => '. and%M %binop',
422 modified_flags => $status_flags
427 comment => "construct Or: Or(a, b) = Or(b, a) = a OR b",
428 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
429 emit => '. or%M %binop',
432 modified_flags => $status_flags
437 comment => "construct Xor: Xor(a, b) = Xor(b, a) = a EOR b",
438 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
439 emit => '. xor%M %binop',
442 modified_flags => $status_flags
447 cmp_attr => "return 1;",
448 comment => "construct lowered Xor: Xor(a, b) = Xor(b, a) = a XOR b",
450 modified_flags => $status_flags
453 # not commutative operations
457 comment => "construct Sub: Sub(a, b) = a - b",
458 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
459 emit => '. sub%M %binop',
462 modified_flags => $status_flags
466 comment => "construct Sub with Carry: SubC(a, b) = a - b - carry",
467 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3 !in_r4" ] },
468 emit => '. sbb%M %binop',
471 modified_flags => $status_flags
476 comment => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
478 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
485 outs => [ "low_res", "high_res" ],
487 modified_flags => $status_flags
492 cmp_attr => "return 1;",
493 comment => "construct lowered Sub: Sub(a, b) = a - b",
498 cmp_attr => "return 1;",
499 comment => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
505 state => "exc_pinned",
506 reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
507 attr => "ia32_op_flavour_t dm_flav",
508 init_attr => "attr->data.op_flav = dm_flav;",
509 emit => ". idiv%M %unop",
510 outs => [ "div_res", "mod_res", "M" ],
513 modified_flags => $status_flags
518 state => "exc_pinned",
519 reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
520 attr => "ia32_op_flavour_t dm_flav",
521 init_attr => "attr->data.op_flav = dm_flav;",
522 emit => ". div%M %unop",
523 outs => [ "div_res", "mod_res", "M" ],
526 modified_flags => $status_flags
531 comment => "construct Shl: Shl(a, b) = a << b",
532 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
533 ins => [ "base", "index", "left", "right", "mem" ],
534 emit => '. shl%M %binop',
537 modified_flags => $status_flags
541 cmp_attr => "return 1;",
542 comment => "construct lowered Shl: Shl(a, b) = a << b",
548 comment => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
549 # Out requirements is: different from all in
550 # This is because, out must be different from LowPart and ShiftCount.
551 # We could say "!ecx !in_r4" but it can occur, that all values live through
552 # this Shift and the only value dying is the ShiftCount. Then there would be a
553 # register missing, as result must not be ecx and all other registers are
554 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
555 # (and probably never will). So we create artificial interferences of the result
556 # with all inputs, so the spiller can always assure a free register.
557 reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
560 if (get_ia32_immop_type(node) == ia32_ImmNone) {
561 if (get_ia32_op_type(node) == ia32_AddrModeD) {
562 . shld%M %%cl, %S3, %AM
564 . shld%M %%cl, %S3, %S2
567 if (get_ia32_op_type(node) == ia32_AddrModeD) {
568 . shld%M %C, %S3, %AM
570 . shld%M %C, %S3, %S2
577 modified_flags => $status_flags
581 cmp_attr => "return 1;",
582 comment => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
588 comment => "construct Shr: Shr(a, b) = a >> b",
589 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
590 emit => '. shr%M %binop',
593 modified_flags => $status_flags
597 cmp_attr => "return 1;",
598 comment => "construct lowered Shr: Shr(a, b) = a << b",
604 comment => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
605 # Out requirements is: different from all in
606 # This is because, out must be different from LowPart and ShiftCount.
607 # We could say "!ecx !in_r4" but it can occur, that all values live through
608 # this Shift and the only value dying is the ShiftCount. Then there would be a
609 # register missing, as result must not be ecx and all other registers are
610 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
611 # (and probably never will). So we create artificial interferences of the result
612 # with all inputs, so the spiller can always assure a free register.
613 reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
615 if (get_ia32_immop_type(node) == ia32_ImmNone) {
616 if (get_ia32_op_type(node) == ia32_AddrModeD) {
617 . shrd%M %%cl, %S3, %AM
619 . shrd%M %%cl, %S3, %S2
622 if (get_ia32_op_type(node) == ia32_AddrModeD) {
623 . shrd%M %C, %S3, %AM
625 . shrd%M %C, %S3, %S2
632 modified_flags => $status_flags
636 cmp_attr => "return 1;",
637 comment => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
643 comment => "construct Shrs: Shrs(a, b) = a >> b",
644 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
645 emit => '. sar%M %binop',
648 modified_flags => $status_flags
652 cmp_attr => "return 1;",
653 comment => "construct lowered Sar: Sar(a, b) = a << b",
659 comment => "construct Ror: Ror(a, b) = a ROR b",
660 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
661 emit => '. ror%M %binop',
664 modified_flags => $status_flags
669 comment => "construct Rol: Rol(a, b) = a ROL b",
670 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
671 emit => '. rol%M %binop',
674 modified_flags => $status_flags
681 comment => "construct Minus: Minus(a) = -a",
682 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
683 emit => '. neg%M %unop',
686 modified_flags => $status_flags
691 comment => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
693 reg_req => { in => [ "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
700 outs => [ "low_res", "high_res" ],
702 modified_flags => $status_flags
707 cmp_attr => "return 1;",
708 comment => "construct lowered Minus: Minus(a) = -a",
714 comment => "construct Increment: Inc(a) = a++",
715 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
716 emit => '. inc%M %unop',
719 modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
724 comment => "construct Decrement: Dec(a) = a--",
725 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
726 emit => '. dec%M %unop',
729 modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
734 comment => "construct Not: Not(a) = !a",
735 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
736 emit => '. not%M %unop',
747 comment => "construct conditional jump: CMP A, B && JMPxx LABEL",
748 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ] },
749 outs => [ "false", "true" ],
751 units => [ "BRANCH" ],
757 comment => "construct conditional jump: TEST A, B && JMPxx LABEL",
758 reg_req => { in => [ "gp", "gp" ] },
759 outs => [ "false", "true" ],
761 units => [ "BRANCH" ],
767 comment => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
768 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "none", "none" ] },
769 outs => [ "false", "true" ],
770 units => [ "BRANCH" ],
776 comment => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
777 reg_req => { in => [ "gp", "gp" ] },
778 units => [ "BRANCH" ],
784 comment => "construct switch",
785 reg_req => { in => [ "gp" ], out => [ "none" ] },
787 units => [ "BRANCH" ],
793 comment => "represents an integer constant",
794 reg_req => { out => [ "gp" ] },
803 comment => "unknown value",
804 reg_req => { out => [ "gp_UKNWN" ] },
814 comment => "unknown value",
815 reg_req => { out => [ "vfp_UKNWN" ] },
825 comment => "unknown value",
826 reg_req => { out => [ "xmm_UKNWN" ] },
836 comment => "noreg GP value",
837 reg_req => { out => [ "gp_NOREG" ] },
847 comment => "noreg VFP value",
848 reg_req => { out => [ "vfp_NOREG" ] },
858 comment => "noreg XMM value",
859 reg_req => { out => [ "xmm_NOREG" ] },
869 comment => "change floating point control word",
870 reg_req => { out => [ "fp_cw" ] },
874 modified_flags => $fpcw_flags
879 state => "exc_pinned",
880 comment => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg",
881 reg_req => { in => [ "gp", "gp", "none" ], out => [ "fp_cw" ] },
883 emit => ". fldcw %AM",
886 modified_flags => $fpcw_flags
891 state => "exc_pinned",
892 comment => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg",
893 reg_req => { in => [ "gp", "gp", "fp_cw", "none" ], out => [ "none" ] },
895 emit => ". fnstcw %AM",
901 # we should not rematrialize this node. It produces 2 results and has
902 # very strict constrains
903 comment => "construct CDQ: sign extend EAX -> EDX:EAX",
904 reg_req => { in => [ "gp" ], out => [ "eax in_r1", "edx" ] },
906 outs => [ "EAX", "EDX" ],
914 state => "exc_pinned",
915 comment => "construct Load: Load(ptr, mem) = LD ptr -> reg",
916 reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] },
918 emit => ". mov%SE%ME%.l %AM, %D0",
919 outs => [ "res", "M" ],
925 cmp_attr => "return 1;",
926 comment => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
927 outs => [ "res", "M" ],
933 cmp_attr => "return 1;",
934 state => "exc_pinned",
935 comment => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
942 state => "exc_pinned",
943 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
944 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
945 emit => '. mov%M %binop',
953 state => "exc_pinned",
954 comment => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
955 reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => ["none" ] },
956 emit => '. mov%M %binop',
964 comment => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
965 reg_req => { in => [ "gp", "gp" ], out => [ "in_r1" ] },
966 emit => '. leal %AM, %D0',
970 modified_flags => [],
974 comment => "push on the stack",
975 reg_req => { in => [ "gp", "gp", "gp", "esp", "none" ], out => [ "esp", "none" ] },
976 emit => '. push%M %unop',
977 outs => [ "stack:I|S", "M" ],
980 modified_flags => [],
984 comment => "pop a gp register from the stack",
985 reg_req => { in => [ "gp", "gp", "esp", "none" ], out => [ "esp", "gp", "none" ] },
986 emit => '. pop%M %unop',
987 outs => [ "stack:I|S", "res", "M" ],
990 modified_flags => [],
994 comment => "create stack frame",
995 reg_req => { in => [ "esp" ], out => [ "ebp", "esp" ] },
997 outs => [ "frame:I", "stack:I|S", "M" ],
1003 comment => "destroy stack frame",
1004 reg_req => { in => [ "esp", "ebp" ], out => [ "ebp", "esp" ] },
1006 outs => [ "frame:I", "stack:I|S" ],
1013 comment => "allocate space on stack",
1014 reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
1015 emit => '. addl %binop',
1016 outs => [ "stack:S", "M" ],
1018 modified_flags => $status_flags
1023 comment => "free space on stack",
1024 reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
1025 emit => '. subl %binop',
1026 outs => [ "stack:S", "M" ],
1028 modified_flags => $status_flags
1033 comment => "get the TLS base address",
1034 reg_req => { out => [ "gp" ] },
1040 #-----------------------------------------------------------------------------#
1041 # _____ _____ ______ __ _ _ _ #
1042 # / ____/ ____| ____| / _| | | | | | #
1043 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1044 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1045 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1046 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1047 #-----------------------------------------------------------------------------#
1049 # commutative operations
1053 comment => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
1054 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1055 emit => '. add%XXM %binop',
1063 comment => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
1064 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1065 emit => '. mul%XXM %binop',
1073 comment => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
1074 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1075 emit => '. max%XXM %binop',
1083 comment => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
1084 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1085 emit => '. min%XXM %binop',
1093 comment => "construct SSE And: And(a, b) = a AND b",
1094 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1095 emit => '. andp%XSD %binop',
1103 comment => "construct SSE Or: Or(a, b) = a OR b",
1104 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1105 emit => '. orp%XSD %binop',
1112 comment => "construct SSE Xor: Xor(a, b) = a XOR b",
1113 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1114 emit => '. xorp%XSD %binop',
1120 # not commutative operations
1124 comment => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
1125 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1126 emit => '. andnp%XSD %binop',
1134 comment => "construct SSE Sub: Sub(a, b) = a - b",
1135 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1136 emit => '. sub%XXM %binop',
1144 comment => "construct SSE Div: Div(a, b) = a / b",
1145 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1146 outs => [ "res", "M" ],
1147 emit => '. div%XXM %binop',
1156 comment => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
1157 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1165 op_flags => "L|X|Y",
1166 comment => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
1167 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "none", "none" ] },
1168 outs => [ "false", "true" ],
1176 comment => "represents a SSE constant",
1177 reg_req => { out => [ "xmm" ] },
1178 emit => '. mov%XXM %C, %D0',
1188 state => "exc_pinned",
1189 comment => "construct SSE Load: Load(ptr, mem) = LD ptr",
1190 reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
1191 emit => '. mov%XXM %AM, %D0',
1192 outs => [ "res", "M" ],
1199 state => "exc_pinned",
1200 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1201 reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
1202 emit => '. mov%XXM %binop',
1210 state => "exc_pinned",
1211 comment => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
1212 reg_req => { in => [ "gp", "xmm", "none" ] },
1213 emit => '. mov%XXM %S1, %AM',
1221 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
1222 emit => '. cvtsi2ss %D0, %AM',
1230 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
1231 emit => '. cvtsi2sd %unop',
1240 comment => "construct: transfer a value from x87 FPU into a SSE register",
1241 cmp_attr => "return 1;",
1247 comment => "construct: transfer a value from SSE register to x87 FPU",
1248 cmp_attr => "return 1;",
1255 state => "exc_pinned",
1256 comment => "store ST0 onto stack",
1257 reg_req => { in => [ "gp", "gp", "none" ] },
1258 emit => '. fstp%XM %AM',
1267 state => "exc_pinned",
1268 comment => "load ST0 from stack",
1269 reg_req => { in => [ "gp", "none" ], out => [ "vf0", "none" ] },
1270 emit => '. fld%XM %AM',
1271 outs => [ "res", "M" ],
1281 comment => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1282 reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] },
1283 outs => [ "DST", "SRC", "CNT", "M" ],
1285 modified_flags => [ "DF" ]
1291 comment => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1292 reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] },
1293 outs => [ "DST", "SRC", "M" ],
1295 modified_flags => [ "DF" ]
1301 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3", "none" ] },
1302 comment => "construct Conv Int -> Int",
1305 modified_flags => $status_flags
1309 reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => [ "in_r3", "none" ] },
1310 comment => "construct Conv Int -> Int",
1313 modified_flags => $status_flags
1317 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm", "none" ] },
1318 comment => "construct Conv Int -> Floating Point",
1325 reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "gp", "none" ] },
1326 comment => "construct Conv Floating Point -> Int",
1333 reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "xmm", "none" ] },
1334 comment => "construct Conv Floating Point -> Floating Point",
1342 comment => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1343 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "in_r4" ] },
1351 comment => "check if Psi condition tree evaluates to true and move result accordingly",
1352 reg_req => { in => [ "gp", "gp", "gp" ], out => [ "in_r3" ] },
1360 comment => "construct Conditional Move: SSE Compare + int CMov ",
1361 reg_req => { in => [ "xmm", "xmm", "gp", "gp" ], out => [ "in_r4" ] },
1369 comment => "construct Conditional Move: x87 Compare + int CMov",
1370 reg_req => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] },
1378 comment => "construct Set: Set(sel) == sel ? 1 : 0",
1379 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
1387 comment => "check if Psi condition tree evaluates to true and set result accordingly",
1388 reg_req => { in => [ "gp" ], out => [ "eax ebx ecx edx" ] },
1396 comment => "construct Set: SSE Compare + int Set",
1397 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "eax ebx ecx edx" ] },
1405 comment => "construct Set: x87 Compare + int Set",
1406 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "eax ebx ecx edx" ] },
1414 comment => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1415 reg_req => { in => [ "vfp", "vfp", "vfp", "vfp" ], out => [ "vfp" ] },
1421 #----------------------------------------------------------#
1423 # (_) | | | | / _| | | | #
1424 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1425 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1426 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1427 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1429 # _ __ ___ __| | ___ ___ #
1430 # | '_ \ / _ \ / _` |/ _ \/ __| #
1431 # | | | | (_) | (_| | __/\__ \ #
1432 # |_| |_|\___/ \__,_|\___||___/ #
1433 #----------------------------------------------------------#
1437 comment => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1438 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1446 comment => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1447 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1455 cmp_attr => "return 1;",
1456 comment => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1462 comment => "virtual fp Sub: Sub(a, b) = a - b",
1463 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1470 cmp_attr => "return 1;",
1471 comment => "lowered virtual fp Sub: Sub(a, b) = a - b",
1476 comment => "virtual fp Div: Div(a, b) = a / b",
1477 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1478 outs => [ "res", "M" ],
1484 cmp_attr => "return 1;",
1485 comment => "lowered virtual fp Div: Div(a, b) = a / b",
1486 outs => [ "res", "M" ],
1491 comment => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1492 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1499 cmp_attr => "return 1;",
1500 comment => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1506 comment => "virtual fp Abs: Abs(a) = |a|",
1507 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1515 comment => "virtual fp Chs: Chs(a) = -a",
1516 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1524 comment => "virtual fp Sin: Sin(a) = sin(a)",
1525 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1533 comment => "virtual fp Cos: Cos(a) = cos(a)",
1534 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1542 comment => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1543 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1549 # virtual Load and Store
1553 state => "exc_pinned",
1554 comment => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1555 reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
1556 outs => [ "res", "M" ],
1563 state => "exc_pinned",
1564 comment => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1565 reg_req => { in => [ "gp", "gp", "vfp", "none" ] },
1574 comment => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1575 reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
1576 outs => [ "res", "M" ],
1582 cmp_attr => "return 1;",
1583 comment => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1584 outs => [ "res", "M" ],
1589 comment => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1590 reg_req => { in => [ "gp", "gp", "vfp", "fpcw", "none" ] },
1597 cmp_attr => "return 1;",
1598 comment => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1608 comment => "virtual fp Load 0.0: Ld 0.0 -> reg",
1609 reg_req => { out => [ "vfp" ] },
1617 comment => "virtual fp Load 1.0: Ld 1.0 -> reg",
1618 reg_req => { out => [ "vfp" ] },
1626 comment => "virtual fp Load pi: Ld pi -> reg",
1627 reg_req => { out => [ "vfp" ] },
1635 comment => "virtual fp Load ln 2: Ld ln 2 -> reg",
1636 reg_req => { out => [ "vfp" ] },
1644 comment => "virtual fp Load lg 2: Ld lg 2 -> reg",
1645 reg_req => { out => [ "vfp" ] },
1653 comment => "virtual fp Load ld 10: Ld ld 10 -> reg",
1654 reg_req => { out => [ "vfp" ] },
1662 comment => "virtual fp Load ld e: Ld ld e -> reg",
1663 reg_req => { out => [ "vfp" ] },
1672 # init_attr => " set_ia32_ls_mode(res, mode);",
1673 comment => "represents a virtual floating point constant",
1674 reg_req => { out => [ "vfp" ] },
1684 op_flags => "L|X|Y",
1685 comment => "represents a virtual floating point compare",
1686 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "none", "none", "eax" ] },
1687 outs => [ "false", "true", "temp_reg_eax" ],
1692 #------------------------------------------------------------------------#
1693 # ___ _____ __ _ _ _ #
1694 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1695 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1696 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1697 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1698 #------------------------------------------------------------------------#
1700 # Note: gas is strangely buggy: fdivrp and fdivp as well as fsubrp and fsubp
1701 # are swapped, we work this around in the emitter...
1705 rd_constructor => "NONE",
1706 comment => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1708 emit => '. fadd%XM %x87_binop',
1713 rd_constructor => "NONE",
1714 comment => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1716 emit => '. faddp %x87_binop',
1721 rd_constructor => "NONE",
1722 comment => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1724 emit => '. fmul%XM %x87_binop',
1729 rd_constructor => "NONE",
1730 comment => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1732 emit => '. fmulp %x87_binop',,
1737 rd_constructor => "NONE",
1738 comment => "x87 fp Sub: Sub(a, b) = a - b",
1740 emit => '. fsub%XM %x87_binop',
1745 rd_constructor => "NONE",
1746 comment => "x87 fp Sub: Sub(a, b) = a - b",
1748 # see note about gas bugs
1749 emit => '. fsubrp %x87_binop',
1754 rd_constructor => "NONE",
1756 comment => "x87 fp SubR: SubR(a, b) = b - a",
1758 emit => '. fsubr%XM %x87_binop',
1763 rd_constructor => "NONE",
1765 comment => "x87 fp SubR: SubR(a, b) = b - a",
1767 # see note about gas bugs
1768 emit => '. fsubp %x87_binop',
1773 rd_constructor => "NONE",
1774 comment => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1779 # this node is just here, to keep the simulator running
1780 # we can omit this when a fprem simulation function exists
1783 rd_constructor => "NONE",
1784 comment => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1791 rd_constructor => "NONE",
1792 comment => "x87 fp Div: Div(a, b) = a / b",
1794 emit => '. fdiv%XM %x87_binop',
1799 rd_constructor => "NONE",
1800 comment => "x87 fp Div: Div(a, b) = a / b",
1802 # see note about gas bugs
1803 emit => '. fdivrp %x87_binop',
1808 rd_constructor => "NONE",
1809 comment => "x87 fp DivR: DivR(a, b) = b / a",
1811 emit => '. fdivr%XM %x87_binop',
1816 rd_constructor => "NONE",
1817 comment => "x87 fp DivR: DivR(a, b) = b / a",
1819 # see note about gas bugs
1820 emit => '. fdivp %x87_binop',
1825 rd_constructor => "NONE",
1826 comment => "x87 fp Abs: Abs(a) = |a|",
1833 rd_constructor => "NONE",
1834 comment => "x87 fp Chs: Chs(a) = -a",
1841 rd_constructor => "NONE",
1842 comment => "x87 fp Sin: Sin(a) = sin(a)",
1849 rd_constructor => "NONE",
1850 comment => "x87 fp Cos: Cos(a) = cos(a)",
1857 rd_constructor => "NONE",
1858 comment => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1860 emit => '. fsqrt $',
1863 # x87 Load and Store
1866 rd_constructor => "NONE",
1867 op_flags => "R|L|F",
1868 state => "exc_pinned",
1869 comment => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1871 emit => '. fld%XM %AM',
1875 rd_constructor => "NONE",
1876 op_flags => "R|L|F",
1877 state => "exc_pinned",
1878 comment => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1880 emit => '. fst%XM %AM',
1885 rd_constructor => "NONE",
1886 op_flags => "R|L|F",
1887 state => "exc_pinned",
1888 comment => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1890 emit => '. fstp%XM %AM',
1898 rd_constructor => "NONE",
1899 comment => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1901 emit => '. fild%XM %AM',
1906 rd_constructor => "NONE",
1907 comment => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1909 emit => '. fist%XM %AM',
1915 rd_constructor => "NONE",
1916 comment => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1918 emit => '. fistp%XM %AM',
1927 comment => "x87 fp Load 0.0: Ld 0.0 -> reg",
1935 comment => "x87 fp Load 1.0: Ld 1.0 -> reg",
1943 comment => "x87 fp Load pi: Ld pi -> reg",
1951 comment => "x87 fp Load ln 2: Ld ln 2 -> reg",
1959 comment => "x87 fp Load lg 2: Ld lg 2 -> reg",
1967 comment => "x87 fp Load ld 10: Ld ld 10 -> reg",
1969 emit => '. fldll2t',
1975 comment => "x87 fp Load ld e: Ld ld e -> reg",
1981 # Note that it is NEVER allowed to do CSE on these nodes
1982 # Moreover, note the virtual register requierements!
1986 comment => "x87 stack exchange",
1988 cmp_attr => "return 1;",
1989 emit => '. fxch %X0',
1994 comment => "x87 stack push",
1996 cmp_attr => "return 1;",
1997 emit => '. fld %X0',
2002 comment => "x87 stack push",
2003 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
2004 cmp_attr => "return 1;",
2005 emit => '. fld %X0',
2010 comment => "x87 stack pop",
2012 cmp_attr => "return 1;",
2013 emit => '. fstp %X0',
2019 op_flags => "L|X|Y",
2020 comment => "floating point compare",
2025 op_flags => "L|X|Y",
2026 comment => "floating point compare and pop",
2031 op_flags => "L|X|Y",
2032 comment => "floating point compare and pop twice",
2037 op_flags => "L|X|Y",
2038 comment => "floating point compare reverse",
2043 op_flags => "L|X|Y",
2044 comment => "floating point compare reverse and pop",
2049 op_flags => "L|X|Y",
2050 comment => "floating point compare reverse and pop twice",
2055 # -------------------------------------------------------------------------------- #
2056 # ____ ____ _____ _ _ #
2057 # / ___/ ___|| ____| __ _____ ___| |_ ___ _ __ _ __ ___ __| | ___ ___ #
2058 # \___ \___ \| _| \ \ / / _ \/ __| __/ _ \| '__| | '_ \ / _ \ / _` |/ _ \/ __| #
2059 # ___) |__) | |___ \ V / __/ (__| || (_) | | | | | | (_) | (_| | __/\__ \ #
2060 # |____/____/|_____| \_/ \___|\___|\__\___/|_| |_| |_|\___/ \__,_|\___||___/ #
2062 # -------------------------------------------------------------------------------- #
2065 # Spilling and reloading of SSE registers, hardcoded, not generated #
2069 state => "exc_pinned",
2070 comment => "construct SSE Load: Load(ptr, mem) = LD ptr",
2071 reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
2072 emit => '. movdqu %D0, %AM',
2073 outs => [ "res", "M" ],
2079 state => "exc_pinned",
2080 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
2081 reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
2082 emit => '. movdqu %binop',
2089 # Include the generated SIMD node specification written by the SIMD optimization
2090 $my_script_name = dirname($myname) . "/../ia32/ia32_simd_spec.pl";
2091 unless ($return = do $my_script_name) {
2092 warn "couldn't parse $my_script_name: $@" if $@;
2093 warn "couldn't do $my_script_name: $!" unless defined $return;
2094 warn "couldn't run $my_script_name" unless $return;