3 # This is the specification for the ia32 assembler Firm-operations
5 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
9 # The node description is done as a perl hash initializer with the
10 # following structure:
15 # "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
16 # "irn_flags" => "R|N|I"
17 # "arity" => "0|1|2|3 ... |variable|dynamic|all",
18 # "state" => "floats|pinned",
20 # { "type" => "type 1", "name" => "name 1" },
21 # { "type" => "type 2", "name" => "name 2" },
24 # "comment" => "any comment for constructor",
25 # "emit" => "emit code with templates",
26 # "rd_constructor" => "c source code which constructs an ir_node"
29 # ... # (all nodes you need to describe)
31 # ); # close the %nodes initializer
33 # op_flags: flags for the operation, OPTIONAL (default is "N")
34 # the op_flags correspond to the firm irop_flags:
37 # C irop_flag_commutative
38 # X irop_flag_cfopcode
39 # I irop_flag_ip_cfopcode
42 # H irop_flag_highlevel
43 # c irop_flag_constlike
46 # irn_flags: special node flags, OPTIONAL (default is 0)
47 # following irn_flags are supported:
50 # I ignore for register allocation
52 # state: state of the operation, OPTIONAL (default is "pinned")
54 # arity: arity of the operation, MUST NOT BE OMITTED
56 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
57 # are always the first 3 arguments and are always autmatically
59 # If this key is missing the following arguments will be created:
60 # for i = 1 .. arity: ir_node *op_i
63 # comment: OPTIONAL comment for the node constructor
65 # rd_constructor: for every operation there will be a
66 # new_rd_<arch>_<op-name> function with the arguments from above
67 # which creates the ir_node corresponding to the defined operation
68 # you can either put the complete source code of this function here
70 # This key is OPTIONAL. If omitted, the following constructor will
72 # if (!op_<arch>_<op-name>) assert(0);
76 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
79 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
83 # 1 - write invariant (writes to this register doesn't change it's content)
84 # 2 - caller save (register must be saved by the caller of a function)
85 # 3 - callee save (register must be saved by the called function)
86 # 4 - ignore (do not assign this register)
87 # NOTE: Make sure to list the registers returning the call-result before all other
88 # caller save registers and in the correct order, otherwise it will break
92 { "name" => "eax", "type" => 2 },
93 { "name" => "edx", "type" => 2 },
94 { "name" => "ebx", "type" => 3 },
95 { "name" => "ecx", "type" => 2 },
96 { "name" => "esi", "type" => 3 },
97 { "name" => "edi", "type" => 3 },
98 { "name" => "ebp", "type" => 3 },
99 { "name" => "esp", "type" => 4 }, # we don't want esp to be assigned
100 { "name" => "xxx", "type" => 4 } # we need a dummy register for NoReg and Unknown nodes
103 { "name" => "xmm0", "type" => 2 },
104 { "name" => "xmm1", "type" => 2 },
105 { "name" => "xmm2", "type" => 2 },
106 { "name" => "xmm3", "type" => 2 },
107 { "name" => "xmm4", "type" => 2 },
108 { "name" => "xmm5", "type" => 2 },
109 { "name" => "xmm6", "type" => 2 },
110 { "name" => "xmm7", "type" => 2 }
114 #--------------------------------------------------#
117 # _ __ _____ __ _ _ __ ___ _ __ ___ #
118 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
119 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
120 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
123 #--------------------------------------------------#
127 #-----------------------------------------------------------------#
130 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
131 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
132 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
133 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
136 #-----------------------------------------------------------------#
138 # commutative operations
141 # All nodes supporting Addressmode have 5 INs:
142 # 1 - base r1 == NoReg in case of no AM or no base
143 # 2 - index r2 == NoReg in case of no AM or no index
144 # 3 - op1 r3 == always present
145 # 4 - op2 r4 == NoReg in case of immediate operation
146 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
151 "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
152 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
153 "emit" => '. add %ia32_emit_binop\t\t\t/* Add(%A1, %A2) -> %D1 */'
159 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
160 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
161 "emit" => '. imul %ia32_emit_binop\t\t\t/* Mul(%A1, %A2) -> %D1 */'
164 # Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
167 "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
168 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r2" ] },
169 "emit" => '. imul %ia32_emit_unop\t\t\t/* Mulh(%A1, %A2) -> %D1 */ '
175 "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
176 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
177 "emit" => '. and %ia32_emit_binop\t\t\t/* And(%A1, %A2) -> %D1 */'
183 "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
184 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
185 "emit" => '. or %ia32_emit_binop\t\t\t/* Or(%A1, %A2) -> %D1 */'
191 "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
192 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
193 "emit" => '. xor %ia32_emit_binop\t\t\t/* Xor(%A1, %A2) -> %D1 */'
199 "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
200 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
202 '2. cmp %S1, %S2\t\t\t/* prepare Max (%S1 - %S2), (%A1, %A2) */
203 if (mode_is_signed(get_irn_mode(n))) {
204 4. cmovl %D1, %S2\t\t\t/* %S1 is less %S2 */
207 4. cmovb %D1, %S2\t\t\t/* %S1 is below %S2 */
215 "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
216 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
218 '2. cmp %S1, %S2\t\t\t/* prepare Min (%S1 - %S2), (%A1, %A2) */
219 if (mode_is_signed(get_irn_mode(n))) {
220 2. cmovg %D1, %S2\t\t\t/* %S1 is greater %S2 */
223 2. cmova %D1, %S2, %D1\t\t\t/* %S1 is above %S2 */
228 # not commutative operations
232 "comment" => "construct Sub: Sub(a, b) = a - b",
233 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
234 "emit" => '. sub %ia32_emit_binop\t\t\t/* Sub(%A1, %A2) -> %D1 */'
239 "state" => "exc_pinned",
240 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
242 ' if (mode_is_signed(get_irn_mode(n))) {
243 4. idiv %S2\t\t\t/* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
246 4. div %S2\t\t\t/* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
253 "comment" => "construct Shl: Shl(a, b) = a << b",
254 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
255 "emit" => '. shl %ia32_emit_binop\t\t\t/* Shl(%A1, %A2) -> %D1 */'
260 "comment" => "construct Shr: Shr(a, b) = a >> b",
261 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
262 "emit" => '. shr %ia32_emit_binop\t\t\t/* Shr(%A1, %A2) -> %D1 */'
267 "comment" => "construct Shrs: Shrs(a, b) = a >> b",
268 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
269 "emit" => '. sar %ia32_emit_binop\t\t\t/* Shrs(%A1, %A2) -> %D1 */'
274 "comment" => "construct RotR: RotR(a, b) = a ROTR b",
275 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
276 "emit" => '. ror %ia32_emit_binop\t\t\t/* RotR(%A1, %A2) -> %D1 */'
281 "comment" => "construct RotL: RotL(a, b) = a ROTL b",
282 "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
283 "emit" => '. rol %ia32_emit_binop\t\t\t/* RotL(%A1, %A2) -> %D1 */'
290 "comment" => "construct Minus: Minus(a) = -a",
291 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
292 "emit" => '. neg %ia32_emit_unop\t\t\t/* Neg(%A1) -> %D1, (%A1) */'
297 "comment" => "construct Increment: Inc(a) = a++",
298 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
299 "emit" => '. inc %ia32_emit_unop\t\t\t/* Inc(%S1) -> %D1, (%A1) */'
304 "comment" => "construct Decrement: Dec(a) = a--",
305 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
306 "emit" => '. dec %ia32_emit_unop\t\t\t/* Dec(%S1) -> %D1, (%A1) */'
311 "comment" => "construct Not: Not(a) = !a",
312 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
313 "emit" => '. not %ia32_emit_unop\t\t\t/* Not(%S1) -> %D1, (%A1) */'
320 "reg_req" => { "in" => [ "gp" ], "out" => [ "in_r1" ] },
321 "comment" => "construct Conv: Conv(a) = (conv)a"
325 "op_flags" => "C|L|X|Y",
326 "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
327 "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
331 "op_flags" => "L|X|Y",
332 "comment" => "construct switch",
333 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "none" ] },
339 "comment" => "represents an integer constant",
340 "reg_req" => { "out" => [ "gp" ] },
341 "emit" => '. mov %D1, %C\t\t\t/* Mov Const into register */',
344 if (attr_a->tp == attr_b->tp) {
345 if (attr_a->tp == ia32_SymConst) {
346 if (attr_a->sc == NULL || attr_b->sc == NULL)
349 return strcmp(attr_a->sc, attr_b->sc);
352 if (attr_a->tv == NULL || attr_b->tv == NULL)
355 if (tarval_cmp(attr_a->tv, attr_b->tv) == pn_Cmp_Eq)
368 "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
369 "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
370 "emit" => '. cdq\t\t\t/* sign extend EAX -> EDX:EAX, (%A1) */'
378 "state" => "exc_pinned",
379 "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
380 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
381 "emit" => '. mov %D1, %ia32_emit_am\t\t\t/* Load((%A1)) -> %D1 */'
386 "state" => "exc_pinned",
387 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
388 "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
389 "emit" => '. mov %ia32_emit_am, %S3\t\t\t/* Store(%A2) -> (%A1) */'
394 "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
395 "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
396 "emit" => '. lea %D1, %ia32_emit_am\t\t/* %D1 = %S1 + %S2 << %C + %O, (%A1, %A2) */'
402 "comment" => "constructs a Stack Parameter to retrieve a parameter from Stack",
403 "reg_req" => { "in" => [ "none" ], "out" => [ "gp" ] },
406 return (attr_a->pn_code != attr_b->pn_code);
412 "comment" => "constructs a Stack Argument to pass an argument on Stack",
413 "reg_req" => { "in" => [ "none", "gp" ], "out" => [ "none" ] },
416 return (attr_a->pn_code != attr_b->pn_code);
420 #--------------------------------------------------------#
423 # | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
424 # | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
425 # | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
426 # |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
427 #--------------------------------------------------------#
429 # commutative operations
434 "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
435 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r1" ] },
436 "emit" => '. adds%M %ia32_emit_binop\t\t\t/* SSE Add(%A1, %A2) -> %D1 */'
442 "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
443 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
444 "emit" => '. muls%M %ia32_emit_binop\t\t\t/* SSE Mul(%A1, %A2) -> %D1 */'
450 "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
451 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
452 "emit" => '. maxs%M %ia32_emit_binop\t\t\t/* SSE Max(%A1, %A2) -> %D1 */'
458 "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
459 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
460 "emit" => '. mins%M %ia32_emit_binop\t\t\t/* SSE Min(%A1, %A2) -> %D1 */'
466 "comment" => "construct SSE And: And(a, b) = a AND b",
467 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
468 "emit" => '. andp%M %ia32_emit_binop\t\t\t/* SSE And(%A3, %A4) -> %D1 */'
474 "comment" => "construct SSE Or: Or(a, b) = a OR b",
475 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
476 "emit" => '. orp%M %ia32_emit_binop\t\t\t/* SSE Or(%A3, %A4) -> %D1 */'
482 "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
483 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
484 "emit" => '. xorp%M %ia32_emit_binop\t\t\t/* SSE Xor(%A3, %A4) -> %D1 */'
487 # not commutative operations
491 "comment" => "construct SSE Sub: Sub(a, b) = a - b",
492 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r1" ] },
493 "emit" => '. subs%M %ia32_emit_binop\t\t\t/* SSE Sub(%A1, %A2) -> %D1 */'
498 "comment" => "construct SSE Div: Div(a, b) = a / b",
499 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r1" ] },
500 "emit" => '. divs%M %ia32_emit_binop\t\t\t/* SSE Div(%A1, %A2) -> %D1 */'
507 "reg_req" => { "in" => [ "fp" ], "out" => [ "gp" ] },
508 "comment" => "construct Conv: Conv(a) = (conv)a"
512 "op_flags" => "C|L|X|Y",
513 "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
514 "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "none", "none" ] },
520 "comment" => "represents a SSE constant",
521 "reg_req" => { "out" => [ "fp" ] },
522 "emit" => '. mov%M %D1, %C\t\t\t/* Load fConst into register */',
525 if (attr_a->tp == attr_b->tp) {
526 if (attr_a->tp == ia32_SymConst) {
527 if (attr_a->sc == NULL || attr_b->sc == NULL)
530 return strcmp(attr_a->sc, attr_b->sc);
533 if (attr_a->tv == NULL || attr_b->tv == NULL)
536 if (tarval_cmp(attr_a->tv, attr_b->tv) == pn_Cmp_Eq)
552 "state" => "exc_pinned",
553 "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
554 "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp" ] },
555 "emit" => '. movs%M %D1, %ia32_emit_am\t\t\t/* Load((%A1)) -> %D1 */'
560 "state" => "exc_pinned",
561 "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
562 "reg_req" => { "in" => [ "gp", "gp", "fp", "none" ] },
563 "emit" => '. movs%M %ia32_emit_am, %S3\t\t\t/* Store(%S3) -> (%A1) */'
569 "comment" => "constructs a Stack Parameter to retrieve a SSE parameter from Stack",
570 "reg_req" => { "in" => [ "none" ], "out" => [ "fp" ] },
573 return (attr_a->pn_code != attr_b->pn_code);
579 "comment" => "constructs a Stack Argument to pass an argument on Stack",
580 "reg_req" => { "in" => [ "none", "fp" ], "out" => [ "none" ] },
583 return (attr_a->pn_code != attr_b->pn_code);
591 "state" => "mem_pinned",
592 "arity" => "variable",
593 "comment" => "construct Call: Call(...)",
595 { "type" => "int", "name" => "n" },
596 { "type" => "ir_node **", "name" => "in" }
599 " if (!op_ia32_Call) assert(0);
600 return new_ir_node(db, irg, block, op_ia32_Call, mode_T, n, in);
609 "arity" => "variable",
610 "comment" => "construct Return: Return(...)",
612 { "type" => "int", "name" => "n" },
613 { "type" => "ir_node **", "name" => "in" }
616 " if (!op_ia32_Return) assert(0);
617 return new_ir_node(db, irg, block, op_ia32_Return, mode_X, n, in);
627 "comment" => "construct Alloca: allocate memory on Stack",
628 "reg_req" => { "in" => [ "gp" ], "out" => [ "gp" ] }