3 # This is the specification for the ia32 assembler Firm-operations
10 # the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
13 # The node description is done as a perl hash initializer with the
14 # following structure:
19 # op_flags => "N|L|C|X|I|F|Y|H|c|K",
20 # irn_flags => "R|N|I|S"
21 # arity => "0|1|2|3 ... |variable|dynamic|any",
22 # state => "floats|pinned|mem_pinned|exc_pinned",
24 # { type => "type 1", name => "name 1" },
25 # { type => "type 2", name => "name 2" },
28 # comment => "any comment for constructor",
29 # reg_req => { in => [ "reg_class|register" ], out => [ "reg_class|register|in_rX" ] },
30 # cmp_attr => "c source code for comparing node attributes",
31 # emit => "emit code with templates",
32 # attr => "attitional attribute arguments for constructor"
33 # init_attr => "emit attribute initialization template"
34 # rd_constructor => "c source code which constructs an ir_node"
35 # latency => "latency of this operation (can be float)"
38 # ... # (all nodes you need to describe)
40 # ); # close the %nodes initializer
42 # op_flags: flags for the operation, OPTIONAL (default is "N")
43 # the op_flags correspond to the firm irop_flags:
46 # C irop_flag_commutative
47 # X irop_flag_cfopcode
48 # I irop_flag_ip_cfopcode
51 # H irop_flag_highlevel
52 # c irop_flag_constlike
55 # irn_flags: special node flags, OPTIONAL (default is 0)
56 # following irn_flags are supported:
59 # I ignore for register allocation
60 # S modifies stack pointer
62 # state: state of the operation, OPTIONAL (default is "floats")
64 # arity: arity of the operation, MUST NOT BE OMITTED
66 # args: the OPTIONAL arguments of the node constructor (debug, irg and block
67 # are always the first 3 arguments and are always autmatically
69 # If this key is missing the following arguments will be created:
70 # for i = 1 .. arity: ir_node *op_i
73 # outs: if a node defines more than one output, the names of the projections
74 # nodes having outs having automatically the mode mode_T
75 # One can also annotate some flags for each out, additional to irn_flags.
76 # They are separated from name with a colon ':', and concatenated by pipe '|'
77 # Only I and S are available at the moment (same meaning as in irn_flags).
78 # example: [ "frame:I", "stack:I|S", "M" ]
80 # comment: OPTIONAL comment for the node constructor
82 # rd_constructor: for every operation there will be a
83 # new_rd_<arch>_<op-name> function with the arguments from above
84 # which creates the ir_node corresponding to the defined operation
85 # you can either put the complete source code of this function here
87 # This key is OPTIONAL. If omitted, the following constructor will
89 # if (!op_<arch>_<op-name>) assert(0);
93 # res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
96 # NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
98 # latency: the latency of the operation, default is 1
102 # 0 - no special type
103 # 1 - caller save (register must be saved by the caller of a function)
104 # 2 - callee save (register must be saved by the called function)
105 # 4 - ignore (do not assign this register)
106 # 8 - emitter can choose an arbitrary register of this class
107 # 16 - the register is a virtual one
108 # 32 - register represents a state
109 # NOTE: Last entry of each class is the largest Firm-Mode a register can hold
112 { name => "eax", type => 1 },
113 { name => "edx", type => 1 },
114 { name => "ebx", type => 2 },
115 { name => "ecx", type => 1 },
116 { name => "esi", type => 2 },
117 { name => "edi", type => 2 },
118 { name => "ebp", type => 2 },
119 { name => "esp", type => 4 },
120 { name => "gp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
121 { name => "gp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
122 { mode => "mode_Iu" }
125 { name => "xmm0", type => 1 },
126 { name => "xmm1", type => 1 },
127 { name => "xmm2", type => 1 },
128 { name => "xmm3", type => 1 },
129 { name => "xmm4", type => 1 },
130 { name => "xmm5", type => 1 },
131 { name => "xmm6", type => 1 },
132 { name => "xmm7", type => 1 },
133 { name => "xmm_NOREG", type => 4 | 16 }, # we need a dummy register for NoReg nodes
134 { name => "xmm_UKNWN", type => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
138 { name => "vf0", type => 1 | 16 },
139 { name => "vf1", type => 1 | 16 },
140 { name => "vf2", type => 1 | 16 },
141 { name => "vf3", type => 1 | 16 },
142 { name => "vf4", type => 1 | 16 },
143 { name => "vf5", type => 1 | 16 },
144 { name => "vf6", type => 1 | 16 },
145 { name => "vf7", type => 1 | 16 },
146 { name => "vfp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
147 { name => "vfp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
151 { name => "st0", realname => "st", type => 4 },
152 { name => "st1", realname => "st(1)", type => 4 },
153 { name => "st2", realname => "st(2)", type => 4 },
154 { name => "st3", realname => "st(3)", type => 4 },
155 { name => "st4", realname => "st(4)", type => 4 },
156 { name => "st5", realname => "st(5)", type => 4 },
157 { name => "st6", realname => "st(6)", type => 4 },
158 { name => "st7", realname => "st(7)", type => 4 },
161 fp_cw => [ # the floating point control word
162 { name => "fpcw", type => 4 | 32},
163 { mode => "mode_fpcw" }
166 { name => "eflags", type => 4 },
167 { mode => "mode_Iu" }
170 { name => "fpsw", type => 4 },
171 { mode => "mode_Hu" }
176 CF => { reg => "eflags", bit => 0 },
177 PF => { reg => "eflags", bit => 2 },
178 AF => { reg => "eflags", bit => 4 },
179 ZF => { reg => "eflags", bit => 6 },
180 SF => { reg => "eflags", bit => 7 },
181 TF => { reg => "eflags", bit => 8 },
182 IF => { reg => "eflags", bit => 9 },
183 DF => { reg => "eflags", bit => 10 },
184 OF => { reg => "eflags", bit => 11 },
185 IOPL0 => { reg => "eflags", bit => 12 },
186 IOPL1 => { reg => "eflags", bit => 13 },
187 NT => { reg => "eflags", bit => 14 },
188 RF => { reg => "eflags", bit => 16 },
189 VM => { reg => "eflags", bit => 17 },
190 AC => { reg => "eflags", bit => 18 },
191 VIF => { reg => "eflags", bit => 19 },
192 VIP => { reg => "eflags", bit => 20 },
193 ID => { reg => "eflags", bit => 21 },
195 FP_IE => { reg => "fpsw", bit => 0 },
196 FP_DE => { reg => "fpsw", bit => 1 },
197 FP_ZE => { reg => "fpsw", bit => 2 },
198 FP_OE => { reg => "fpsw", bit => 3 },
199 FP_UE => { reg => "fpsw", bit => 4 },
200 FP_PE => { reg => "fpsw", bit => 5 },
201 FP_SF => { reg => "fpsw", bit => 6 },
202 FP_ES => { reg => "fpsw", bit => 7 },
203 FP_C0 => { reg => "fpsw", bit => 8 },
204 FP_C1 => { reg => "fpsw", bit => 9 },
205 FP_C2 => { reg => "fpsw", bit => 10 },
206 FP_TOP0 => { reg => "fpsw", bit => 11 },
207 FP_TOP1 => { reg => "fpsw", bit => 12 },
208 FP_TOP2 => { reg => "fpsw", bit => 13 },
209 FP_C3 => { reg => "fpsw", bit => 14 },
210 FP_B => { reg => "fpsw", bit => 15 },
212 FP_IM => { reg => "fpcw", bit => 0 },
213 FP_DM => { reg => "fpcw", bit => 1 },
214 FP_ZM => { reg => "fpcw", bit => 2 },
215 FP_OM => { reg => "fpcw", bit => 3 },
216 FP_UM => { reg => "fpcw", bit => 4 },
217 FP_PM => { reg => "fpcw", bit => 5 },
218 FP_PC0 => { reg => "fpcw", bit => 8 },
219 FP_PC1 => { reg => "fpcw", bit => 9 },
220 FP_RC0 => { reg => "fpcw", bit => 10 },
221 FP_RC1 => { reg => "fpcw", bit => 11 },
222 FP_X => { reg => "fpcw", bit => 12 }
226 GP => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ],
227 SSE => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ],
228 VFP => [ 1, "VFP_VF0", "VFP_VF1", "VFP_VF2", "VFP_VF3", "VFP_VF4", "VFP_VF5", "VFP_VF6", "VFP_VF7" ],
229 BRANCH => [ 1, "BRANCH1", "BRANCH2" ],
234 bundels_per_cycle => 1
238 S1 => "${arch}_emit_source_register(env, node, 0);",
239 S2 => "${arch}_emit_source_register(env, node, 1);",
240 S3 => "${arch}_emit_source_register(env, node, 2);",
241 S4 => "${arch}_emit_source_register(env, node, 3);",
242 S5 => "${arch}_emit_source_register(env, node, 4);",
243 S6 => "${arch}_emit_source_register(env, node, 5);",
244 D1 => "${arch}_emit_dest_register(env, node, 0);",
245 D2 => "${arch}_emit_dest_register(env, node, 1);",
246 D3 => "${arch}_emit_dest_register(env, node, 2);",
247 D4 => "${arch}_emit_dest_register(env, node, 3);",
248 D5 => "${arch}_emit_dest_register(env, node, 4);",
249 D6 => "${arch}_emit_dest_register(env, node, 5);",
250 A1 => "${arch}_emit_in_node_name(env, node, 0);",
251 A2 => "${arch}_emit_in_node_name(env, node, 1);",
252 A3 => "${arch}_emit_in_node_name(env, node, 2);",
253 A4 => "${arch}_emit_in_node_name(env, node, 3);",
254 A5 => "${arch}_emit_in_node_name(env, node, 4);",
255 A6 => "${arch}_emit_in_node_name(env, node, 5);",
256 X1 => "${arch}_emit_x87_name(env, node, 0);",
257 X2 => "${arch}_emit_x87_name(env, node, 1);",
258 X3 => "${arch}_emit_x87_name(env, node, 2);",
259 C => "${arch}_emit_immediate(env, node);",
260 SE => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));",
261 ME => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
262 ia32_emit_mode_suffix(env, get_ia32_ls_mode(node));",
263 M => "${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
264 XM => "${arch}_emit_x87_mode_suffix(env, node);",
265 XXM => "${arch}_emit_xmm_mode_suffix(env, node);",
266 XSD => "${arch}_emit_xmm_mode_suffix_s(env, node);",
267 AM => "${arch}_emit_am(env, node);",
268 unop => "${arch}_emit_unop(env, node);",
269 binop => "${arch}_emit_binop(env, node);",
270 x87_binop => "${arch}_emit_x87_binop(env, node);",
273 #--------------------------------------------------#
276 # _ __ _____ __ _ _ __ ___ _ __ ___ #
277 # | '_ \ / _ \ \ /\ / / | | '__| / _ \| '_ \/ __| #
278 # | | | | __/\ V V / | | | | (_) | |_) \__ \ #
279 # |_| |_|\___| \_/\_/ |_|_| \___/| .__/|___/ #
282 #--------------------------------------------------#
284 $default_cmp_attr = "return ia32_compare_attr(attr_a, attr_b);";
289 $mode_xmm = "mode_E";
290 $mode_gp = "mode_Iu";
291 $mode_fpcw = "mode_fpcw";
292 $status_flags = [ "CF", "PF", "AF", "ZF", "SF", "OF" ];
293 $fpcw_flags = [ "FP_IM", "FP_DM", "FP_ZM", "FP_OM", "FP_UM", "FP_PM",
294 "FP_PC0", "FP_PC1", "FP_RC0", "FP_RC1", "FP_X" ];
298 #-----------------------------------------------------------------#
301 # _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
302 # | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
303 # | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
304 # |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
307 #-----------------------------------------------------------------#
309 # commutative operations
312 # All nodes supporting Addressmode have 5 INs:
313 # 1 - base r1 == NoReg in case of no AM or no base
314 # 2 - index r2 == NoReg in case of no AM or no index
315 # 3 - op1 r3 == always present
316 # 4 - op2 r4 == NoReg in case of immediate operation
317 # 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
321 comment => "construct Add: Add(a, b) = Add(b, a) = a + b",
322 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
323 emit => '. addl %binop',
326 modified_flags => $status_flags
330 comment => "construct Add with Carry: Adc(a, b) = Add(b, a) = a + b + carry",
331 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
332 emit => '. adcl %binop',
335 modified_flags => $status_flags
340 comment => "construct 64Bit Add: Add(a_l, a_h, b_l, b_h) = a_l + b_l; a_h + b_h + carry",
342 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
349 outs => [ "low_res", "high_res" ],
351 modified_flags => $status_flags
357 cmp_attr => "return 1;",
358 comment => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
364 cmp_attr => "return 1;",
365 comment => "construct lowered Add with Carry: Adc(a, b) = Adc(b, a) = a + b + carry",
370 # we should not rematrialize this node. It produces 2 results and has
371 # very strict constrains
372 comment => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
373 reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
374 emit => '. mull %unop',
375 outs => [ "EAX", "EDX", "M" ],
378 modified_flags => $status_flags
382 # we should not rematrialize this node. It produces 2 results and has
383 # very strict constrains
385 cmp_attr => "return 1;",
386 comment => "construct lowered MulS: Mul(a, b) = Mul(b, a) = a * b",
387 outs => [ "EAX", "EDX", "M" ],
393 comment => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
394 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
395 emit => '. imull %binop',
399 modified_flags => $status_flags
404 comment => "construct Mul (1 operand format): Mul(a, b) = Mul(b, a) = a * b",
405 reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
406 emit => '. imull %unop',
407 outs => [ "EAX", "EDX", "M" ],
410 modified_flags => $status_flags
415 cmp_attr => "return 1;",
416 comment => "construct lowered IMul: IMul(a, b) = IMul(b, a) = a * b",
422 comment => "construct And: And(a, b) = And(b, a) = a AND b",
423 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
424 emit => '. andl %binop',
427 modified_flags => $status_flags
432 comment => "construct Or: Or(a, b) = Or(b, a) = a OR b",
433 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
434 emit => '. orl %binop',
437 modified_flags => $status_flags
442 comment => "construct Xor: Xor(a, b) = Xor(b, a) = a EOR b",
443 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
444 emit => '. xorl %binop',
447 modified_flags => $status_flags
452 cmp_attr => "return 1;",
453 comment => "construct lowered Xor: Xor(a, b) = Xor(b, a) = a XOR b",
455 modified_flags => $status_flags
458 # not commutative operations
462 comment => "construct Sub: Sub(a, b) = a - b",
463 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
464 emit => '. subl %binop',
467 modified_flags => $status_flags
471 comment => "construct Sub with Carry: SubC(a, b) = a - b - carry",
472 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3 !in_r4" ] },
473 emit => '. sbbl %binop',
476 modified_flags => $status_flags
481 comment => "construct 64Bit Sub: Sub(a_l, a_h, b_l, b_h) = a_l - b_l; a_h - b_h - borrow",
483 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
490 outs => [ "low_res", "high_res" ],
492 modified_flags => $status_flags
497 cmp_attr => "return 1;",
498 comment => "construct lowered Sub: Sub(a, b) = a - b",
503 cmp_attr => "return 1;",
504 comment => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
510 state => "exc_pinned",
511 reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
512 attr => "ia32_op_flavour_t dm_flav",
513 init_attr => "attr->data.op_flav = dm_flav;",
514 emit => ". idivl %unop",
515 outs => [ "div_res", "mod_res", "M" ],
518 modified_flags => $status_flags
523 state => "exc_pinned",
524 reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
525 attr => "ia32_op_flavour_t dm_flav",
526 init_attr => "attr->data.op_flav = dm_flav;",
527 emit => ". divl %unop",
528 outs => [ "div_res", "mod_res", "M" ],
531 modified_flags => $status_flags
536 comment => "construct Shl: Shl(a, b) = a << b",
537 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
538 emit => '. shll %binop',
541 modified_flags => $status_flags
545 cmp_attr => "return 1;",
546 comment => "construct lowered Shl: Shl(a, b) = a << b",
552 comment => "construct ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
553 # Out requirements is: different from all in
554 # This is because, out must be different from LowPart and ShiftCount.
555 # We could say "!ecx !in_r4" but it can occur, that all values live through
556 # this Shift and the only value dying is the ShiftCount. Then there would be a
557 # register missing, as result must not be ecx and all other registers are
558 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
559 # (and probably never will). So we create artificial interferences of the result
560 # with all inputs, so the spiller can always assure a free register.
561 reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
564 if (get_ia32_immop_type(node) == ia32_ImmNone) {
565 if (get_ia32_op_type(node) == ia32_AddrModeD) {
566 . shldl %%cl, %S4, %AM
568 . shldl %%cl, %S4, %S3
571 if (get_ia32_op_type(node) == ia32_AddrModeD) {
581 modified_flags => $status_flags
585 cmp_attr => "return 1;",
586 comment => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
592 comment => "construct Shr: Shr(a, b) = a >> b",
593 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
594 emit => '. shrl %binop',
597 modified_flags => $status_flags
601 cmp_attr => "return 1;",
602 comment => "construct lowered Shr: Shr(a, b) = a << b",
608 comment => "construct ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
609 # Out requirements is: different from all in
610 # This is because, out must be different from LowPart and ShiftCount.
611 # We could say "!ecx !in_r4" but it can occur, that all values live through
612 # this Shift and the only value dying is the ShiftCount. Then there would be a
613 # register missing, as result must not be ecx and all other registers are
614 # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
615 # (and probably never will). So we create artificial interferences of the result
616 # with all inputs, so the spiller can always assure a free register.
617 reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
619 if (get_ia32_immop_type(node) == ia32_ImmNone) {
620 if (get_ia32_op_type(node) == ia32_AddrModeD) {
621 . shrdl %%cl, %S4, %AM
623 . shrdl %%cl, %S4, %S3
626 if (get_ia32_op_type(node) == ia32_AddrModeD) {
636 modified_flags => $status_flags
640 cmp_attr => "return 1;",
641 comment => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
647 comment => "construct Shrs: Shrs(a, b) = a >> b",
648 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
649 emit => '. sarl %binop',
652 modified_flags => $status_flags
656 cmp_attr => "return 1;",
657 comment => "construct lowered Sar: Sar(a, b) = a << b",
663 comment => "construct Ror: Ror(a, b) = a ROR b",
664 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
665 emit => '. rorl %binop',
668 modified_flags => $status_flags
673 comment => "construct Rol: Rol(a, b) = a ROL b",
674 reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
675 emit => '. roll %binop',
678 modified_flags => $status_flags
685 comment => "construct Minus: Minus(a) = -a",
686 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
687 emit => '. negl %unop',
690 modified_flags => $status_flags
695 comment => "construct 64Bit Minus: Minus(a_l, a_h, 0) = 0 - a_l; 0 - a_h - borrow",
697 reg_req => { in => [ "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
704 outs => [ "low_res", "high_res" ],
706 modified_flags => $status_flags
711 cmp_attr => "return 1;",
712 comment => "construct lowered Minus: Minus(a) = -a",
718 comment => "construct Increment: Inc(a) = a++",
719 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
720 emit => '. incl %unop',
723 modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
728 comment => "construct Decrement: Dec(a) = a--",
729 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
730 emit => '. decl %unop',
733 modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
738 comment => "construct Not: Not(a) = !a",
739 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
740 emit => '. notl %unop',
751 comment => "construct conditional jump: CMP A, B && JMPxx LABEL",
752 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ] },
753 outs => [ "false", "true" ],
755 units => [ "BRANCH" ],
761 comment => "construct conditional jump: TEST A, B && JMPxx LABEL",
762 reg_req => { in => [ "gp", "gp" ] },
763 outs => [ "false", "true" ],
765 units => [ "BRANCH" ],
771 comment => "construct conditional jump without CMP (replaces CondJmp): JMPxx LABEL",
772 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "none", "none" ] },
773 outs => [ "false", "true" ],
774 units => [ "BRANCH" ],
780 comment => "construct conditional jump without CMP (replaces TestJmp): JMPxx LABEL",
781 reg_req => { in => [ "gp", "gp" ] },
782 units => [ "BRANCH" ],
788 comment => "construct switch",
789 reg_req => { in => [ "gp" ], out => [ "none" ] },
791 units => [ "BRANCH" ],
797 comment => "represents an integer constant",
798 reg_req => { out => [ "gp" ] },
807 comment => "unknown value",
808 reg_req => { out => [ "gp_UKNWN" ] },
818 comment => "unknown value",
819 reg_req => { out => [ "vfp_UKNWN" ] },
829 comment => "unknown value",
830 reg_req => { out => [ "xmm_UKNWN" ] },
840 comment => "noreg GP value",
841 reg_req => { out => [ "gp_NOREG" ] },
851 comment => "noreg VFP value",
852 reg_req => { out => [ "vfp_NOREG" ] },
862 comment => "noreg XMM value",
863 reg_req => { out => [ "xmm_NOREG" ] },
873 comment => "change floating point control word",
874 reg_req => { out => [ "fp_cw" ] },
878 modified_flags => $fpcw_flags
883 state => "exc_pinned",
884 comment => "load floating point control word FldCW(ptr, mem) = LD ptr -> reg",
885 reg_req => { in => [ "gp", "gp", "none" ], out => [ "fp_cw" ] },
887 emit => ". fldcw %AM",
890 modified_flags => $fpcw_flags
895 state => "exc_pinned",
896 comment => "store floating point control word: FstCW(ptr, mem) = ST ptr -> reg",
897 reg_req => { in => [ "gp", "gp", "fp_cw", "none" ], out => [ "none" ] },
899 emit => ". fnstcw %AM",
905 # we should not rematrialize this node. It produces 2 results and has
906 # very strict constrains
907 comment => "construct CDQ: sign extend EAX -> EDX:EAX",
908 reg_req => { in => [ "gp" ], out => [ "eax in_r1", "edx" ] },
910 outs => [ "EAX", "EDX" ],
918 state => "exc_pinned",
919 comment => "construct Load: Load(ptr, mem) = LD ptr -> reg",
920 reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] },
922 emit => ". mov%SE%ME%.l %AM, %D1",
923 outs => [ "res", "M" ],
929 cmp_attr => "return 1;",
930 comment => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
931 outs => [ "res", "M" ],
937 cmp_attr => "return 1;",
938 state => "exc_pinned",
939 comment => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
946 state => "exc_pinned",
947 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
948 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
949 emit => '. mov%M %binop',
957 state => "exc_pinned",
958 comment => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
959 reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => ["none" ] },
960 emit => '. mov%M %binop',
968 comment => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
969 reg_req => { in => [ "gp", "gp" ], out => [ "in_r1" ] },
970 emit => '. leal %AM, %D1',
974 modified_flags => [],
978 comment => "push on the stack",
979 reg_req => { in => [ "gp", "gp", "gp", "esp", "none" ], out => [ "esp", "none" ] },
980 emit => '. pushl %unop',
981 outs => [ "stack:I|S", "M" ],
984 modified_flags => [],
988 comment => "pop a gp register from the stack",
989 reg_req => { in => [ "gp", "gp", "esp", "none" ], out => [ "esp", "gp", "none" ] },
990 emit => '. popl %unop',
991 outs => [ "stack:I|S", "res", "M" ],
994 modified_flags => [],
998 comment => "create stack frame",
999 reg_req => { in => [ "esp" ], out => [ "ebp", "esp" ] },
1001 outs => [ "frame:I", "stack:I|S", "M" ],
1007 comment => "destroy stack frame",
1008 reg_req => { in => [ "esp", "ebp" ], out => [ "ebp", "esp" ] },
1010 outs => [ "frame:I", "stack:I|S" ],
1017 comment => "allocate space on stack",
1018 reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
1019 emit => '. addl %binop',
1020 outs => [ "stack:S", "M" ],
1022 modified_flags => $status_flags
1027 comment => "free space on stack",
1028 reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
1029 emit => '. subl %binop',
1030 outs => [ "stack:S", "M" ],
1032 modified_flags => $status_flags
1037 comment => "get the TLS base address",
1038 reg_req => { out => [ "gp" ] },
1044 #-----------------------------------------------------------------------------#
1045 # _____ _____ ______ __ _ _ _ #
1046 # / ____/ ____| ____| / _| | | | | | #
1047 # | (___| (___ | |__ | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1048 # \___ \\___ \| __| | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1049 # ____) |___) | |____ | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1050 # |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1051 #-----------------------------------------------------------------------------#
1053 # commutative operations
1057 comment => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
1058 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1059 emit => '. add%XXM %binop',
1067 comment => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
1068 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1069 emit => '. mul%XXM %binop',
1077 comment => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
1078 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1079 emit => '. max%XXM %binop',
1087 comment => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
1088 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1089 emit => '. min%XXM %binop',
1097 comment => "construct SSE And: And(a, b) = a AND b",
1098 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1099 emit => '. andp%XSD %binop',
1107 comment => "construct SSE Or: Or(a, b) = a OR b",
1108 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1109 emit => '. orp%XSD %binop',
1116 comment => "construct SSE Xor: Xor(a, b) = a XOR b",
1117 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1118 emit => '. xorp%XSD %binop',
1124 # not commutative operations
1128 comment => "construct SSE AndNot: AndNot(a, b) = a AND NOT b",
1129 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1130 emit => '. andnp%XSD %binop',
1138 comment => "construct SSE Sub: Sub(a, b) = a - b",
1139 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
1140 emit => '. sub%XXM %binop',
1148 comment => "construct SSE Div: Div(a, b) = a / b",
1149 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1150 outs => [ "res", "M" ],
1151 emit => '. div%XXM %binop',
1160 comment => "construct SSE Compare: Cmp(a, b) == a = a cmp b",
1161 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
1169 op_flags => "L|X|Y",
1170 comment => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
1171 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "none", "none" ] },
1172 outs => [ "false", "true" ],
1180 comment => "represents a SSE constant",
1181 reg_req => { out => [ "xmm" ] },
1182 emit => '. mov%XXM %C, %D1',
1192 state => "exc_pinned",
1193 comment => "construct SSE Load: Load(ptr, mem) = LD ptr",
1194 reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
1195 emit => '. mov%XXM %AM, %D1',
1196 outs => [ "res", "M" ],
1203 state => "exc_pinned",
1204 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
1205 reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
1206 emit => '. mov%XXM %binop',
1214 state => "exc_pinned",
1215 comment => "construct Store without index: Store(ptr, val, mem) = ST ptr,val",
1216 reg_req => { in => [ "gp", "xmm", "none" ] },
1217 emit => '. mov%XXM %S2, %AM',
1225 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
1226 emit => '. cvtsi2ss %D1, %AM',
1234 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
1235 emit => '. cvtsi2sd %unop',
1244 comment => "construct: transfer a value from x87 FPU into a SSE register",
1245 cmp_attr => "return 1;",
1251 comment => "construct: transfer a value from SSE register to x87 FPU",
1252 cmp_attr => "return 1;",
1259 state => "exc_pinned",
1260 comment => "store ST0 onto stack",
1261 reg_req => { in => [ "gp", "gp", "none" ] },
1262 emit => '. fstp%XM %AM',
1271 state => "exc_pinned",
1272 comment => "load ST0 from stack",
1273 reg_req => { in => [ "gp", "none" ], out => [ "vf0", "none" ] },
1274 emit => '. fld%M %AM',
1275 outs => [ "res", "M" ],
1285 comment => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
1286 reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] },
1287 outs => [ "DST", "SRC", "CNT", "M" ],
1289 modified_flags => [ "DF" ]
1295 comment => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
1296 reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] },
1297 outs => [ "DST", "SRC", "M" ],
1299 modified_flags => [ "DF" ]
1305 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3", "none" ] },
1306 comment => "construct Conv Int -> Int",
1309 modified_flags => $status_flags
1313 reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => [ "in_r3", "none" ] },
1314 comment => "construct Conv Int -> Int",
1317 modified_flags => $status_flags
1321 reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm", "none" ] },
1322 comment => "construct Conv Int -> Floating Point",
1329 reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "gp", "none" ] },
1330 comment => "construct Conv Floating Point -> Int",
1337 reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "xmm", "none" ] },
1338 comment => "construct Conv Floating Point -> Floating Point",
1346 comment => "construct Conditional Move: CMov(sel, a, b) == sel ? a : b",
1347 reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "in_r4" ] },
1355 comment => "check if Psi condition tree evaluates to true and move result accordingly",
1356 reg_req => { in => [ "gp", "gp", "gp" ], out => [ "in_r3" ] },
1364 comment => "construct Conditional Move: SSE Compare + int CMov ",
1365 reg_req => { in => [ "xmm", "xmm", "gp", "gp" ], out => [ "in_r4" ] },
1373 comment => "construct Conditional Move: x87 Compare + int CMov",
1374 reg_req => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] },
1382 comment => "construct Set: Set(sel) == sel ? 1 : 0",
1383 reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
1391 comment => "check if Psi condition tree evaluates to true and set result accordingly",
1392 reg_req => { in => [ "gp" ], out => [ "eax ebx ecx edx" ] },
1400 comment => "construct Set: SSE Compare + int Set",
1401 reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "eax ebx ecx edx" ] },
1409 comment => "construct Set: x87 Compare + int Set",
1410 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "eax ebx ecx edx" ] },
1418 comment => "construct x87 Conditional Move: vfCMov(sel, a, b) = sel ? a : b",
1419 reg_req => { in => [ "vfp", "vfp", "vfp", "vfp" ], out => [ "vfp" ] },
1425 #----------------------------------------------------------#
1427 # (_) | | | | / _| | | | #
1428 # __ ___ _ __| |_ _ _ __ _| | | |_| | ___ __ _| |_ #
1429 # \ \ / / | '__| __| | | |/ _` | | | _| |/ _ \ / _` | __| #
1430 # \ V /| | | | |_| |_| | (_| | | | | | | (_) | (_| | |_ #
1431 # \_/ |_|_| \__|\__,_|\__,_|_| |_| |_|\___/ \__,_|\__| #
1433 # _ __ ___ __| | ___ ___ #
1434 # | '_ \ / _ \ / _` |/ _ \/ __| #
1435 # | | | | (_) | (_| | __/\__ \ #
1436 # |_| |_|\___/ \__,_|\___||___/ #
1437 #----------------------------------------------------------#
1441 comment => "virtual fp Add: Add(a, b) = Add(b, a) = a + b",
1442 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1450 comment => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1451 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1459 cmp_attr => "return 1;",
1460 comment => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
1466 comment => "virtual fp Sub: Sub(a, b) = a - b",
1467 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1474 cmp_attr => "return 1;",
1475 comment => "lowered virtual fp Sub: Sub(a, b) = a - b",
1480 comment => "virtual fp Div: Div(a, b) = a / b",
1481 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1482 outs => [ "res", "M" ],
1488 cmp_attr => "return 1;",
1489 comment => "lowered virtual fp Div: Div(a, b) = a / b",
1490 outs => [ "res", "M" ],
1495 comment => "virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1496 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
1503 cmp_attr => "return 1;",
1504 comment => "lowered virtual fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1510 comment => "virtual fp Abs: Abs(a) = |a|",
1511 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1519 comment => "virtual fp Chs: Chs(a) = -a",
1520 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1528 comment => "virtual fp Sin: Sin(a) = sin(a)",
1529 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1537 comment => "virtual fp Cos: Cos(a) = cos(a)",
1538 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1546 comment => "virtual fp Sqrt: Sqrt(a) = a ^ 0.5",
1547 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
1553 # virtual Load and Store
1557 state => "exc_pinned",
1558 comment => "virtual fp Load: Load(ptr, mem) = LD ptr -> reg",
1559 reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
1560 outs => [ "res", "M" ],
1567 state => "exc_pinned",
1568 comment => "virtual fp Store: Store(ptr, val, mem) = ST ptr,val",
1569 reg_req => { in => [ "gp", "gp", "vfp", "none" ] },
1578 comment => "virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1579 reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
1580 outs => [ "res", "M" ],
1586 cmp_attr => "return 1;",
1587 comment => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1588 outs => [ "res", "M" ],
1593 comment => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1594 reg_req => { in => [ "gp", "gp", "vfp", "fpcw", "none" ] },
1601 cmp_attr => "return 1;",
1602 comment => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1612 comment => "virtual fp Load 0.0: Ld 0.0 -> reg",
1613 reg_req => { out => [ "vfp" ] },
1621 comment => "virtual fp Load 1.0: Ld 1.0 -> reg",
1622 reg_req => { out => [ "vfp" ] },
1630 comment => "virtual fp Load pi: Ld pi -> reg",
1631 reg_req => { out => [ "vfp" ] },
1639 comment => "virtual fp Load ln 2: Ld ln 2 -> reg",
1640 reg_req => { out => [ "vfp" ] },
1648 comment => "virtual fp Load lg 2: Ld lg 2 -> reg",
1649 reg_req => { out => [ "vfp" ] },
1657 comment => "virtual fp Load ld 10: Ld ld 10 -> reg",
1658 reg_req => { out => [ "vfp" ] },
1666 comment => "virtual fp Load ld e: Ld ld e -> reg",
1667 reg_req => { out => [ "vfp" ] },
1676 # init_attr => " set_ia32_ls_mode(res, mode);",
1677 comment => "represents a virtual floating point constant",
1678 reg_req => { out => [ "vfp" ] },
1688 op_flags => "L|X|Y",
1689 comment => "represents a virtual floating point compare",
1690 reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "none", "none", "eax" ] },
1691 outs => [ "false", "true", "temp_reg_eax" ],
1696 #------------------------------------------------------------------------#
1697 # ___ _____ __ _ _ _ #
1698 # __ _( _ )___ | / _| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
1699 # \ \/ / _ \ / / | |_| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
1700 # > < (_) |/ / | _| | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
1701 # /_/\_\___//_/ |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
1702 #------------------------------------------------------------------------#
1704 # Note: gas is strangely buggy: fdivrp and fdivp as well as fsubrp and fsubp
1705 # are swapped, we work this around in the emitter...
1709 rd_constructor => "NONE",
1710 comment => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1712 emit => '. fadd%XM %x87_binop',
1717 rd_constructor => "NONE",
1718 comment => "x87 Add: Add(a, b) = Add(b, a) = a + b",
1720 emit => '. faddp %x87_binop',
1725 rd_constructor => "NONE",
1726 comment => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1728 emit => '. fmul%XM %x87_binop',
1733 rd_constructor => "NONE",
1734 comment => "x87 fp Mul: Mul(a, b) = Mul(b, a) = a + b",
1736 emit => '. fmulp %x87_binop',,
1741 rd_constructor => "NONE",
1742 comment => "x87 fp Sub: Sub(a, b) = a - b",
1744 emit => '. fsub%XM %x87_binop',
1749 rd_constructor => "NONE",
1750 comment => "x87 fp Sub: Sub(a, b) = a - b",
1752 # see note about gas bugs
1753 emit => '. fsubrp %x87_binop',
1758 rd_constructor => "NONE",
1760 comment => "x87 fp SubR: SubR(a, b) = b - a",
1762 emit => '. fsubr%XM %x87_binop',
1767 rd_constructor => "NONE",
1769 comment => "x87 fp SubR: SubR(a, b) = b - a",
1771 # see note about gas bugs
1772 emit => '. fsubp %x87_binop',
1777 rd_constructor => "NONE",
1778 comment => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1783 # this node is just here, to keep the simulator running
1784 # we can omit this when a fprem simulation function exists
1787 rd_constructor => "NONE",
1788 comment => "x87 fp Rem: Rem(a, b) = a - Q * b (Q is integer)",
1795 rd_constructor => "NONE",
1796 comment => "x87 fp Div: Div(a, b) = a / b",
1798 emit => '. fdiv%XM %x87_binop',
1803 rd_constructor => "NONE",
1804 comment => "x87 fp Div: Div(a, b) = a / b",
1806 # see note about gas bugs
1807 emit => '. fdivrp %x87_binop',
1812 rd_constructor => "NONE",
1813 comment => "x87 fp DivR: DivR(a, b) = b / a",
1815 emit => '. fdivr%XM %x87_binop',
1820 rd_constructor => "NONE",
1821 comment => "x87 fp DivR: DivR(a, b) = b / a",
1823 # see note about gas bugs
1824 emit => '. fdivp %x87_binop',
1829 rd_constructor => "NONE",
1830 comment => "x87 fp Abs: Abs(a) = |a|",
1837 rd_constructor => "NONE",
1838 comment => "x87 fp Chs: Chs(a) = -a",
1845 rd_constructor => "NONE",
1846 comment => "x87 fp Sin: Sin(a) = sin(a)",
1853 rd_constructor => "NONE",
1854 comment => "x87 fp Cos: Cos(a) = cos(a)",
1861 rd_constructor => "NONE",
1862 comment => "x87 fp Sqrt: Sqrt(a) = a ^ 0.5",
1864 emit => '. fsqrt $',
1867 # x87 Load and Store
1870 rd_constructor => "NONE",
1871 op_flags => "R|L|F",
1872 state => "exc_pinned",
1873 comment => "x87 fp Load: Load(ptr, mem) = LD ptr -> reg",
1875 emit => '. fld%XM %AM',
1879 rd_constructor => "NONE",
1880 op_flags => "R|L|F",
1881 state => "exc_pinned",
1882 comment => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1884 emit => '. fst%XM %AM',
1889 rd_constructor => "NONE",
1890 op_flags => "R|L|F",
1891 state => "exc_pinned",
1892 comment => "x87 fp Store: Store(ptr, val, mem) = ST ptr,val",
1894 emit => '. fstp%XM %AM',
1902 rd_constructor => "NONE",
1903 comment => "x87 fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
1905 emit => '. fild%XM %AM',
1910 rd_constructor => "NONE",
1911 comment => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1913 emit => '. fist%M %AM',
1919 rd_constructor => "NONE",
1920 comment => "x87 fp integer Store: Store(ptr, val, mem) = iST ptr,val",
1922 emit => '. fistp%M %AM',
1931 comment => "x87 fp Load 0.0: Ld 0.0 -> reg",
1939 comment => "x87 fp Load 1.0: Ld 1.0 -> reg",
1947 comment => "x87 fp Load pi: Ld pi -> reg",
1955 comment => "x87 fp Load ln 2: Ld ln 2 -> reg",
1963 comment => "x87 fp Load lg 2: Ld lg 2 -> reg",
1971 comment => "x87 fp Load ld 10: Ld ld 10 -> reg",
1973 emit => '. fldll2t',
1979 comment => "x87 fp Load ld e: Ld ld e -> reg",
1985 # Note that it is NEVER allowed to do CSE on these nodes
1986 # Moreover, note the virtual register requierements!
1990 comment => "x87 stack exchange",
1992 cmp_attr => "return 1;",
1993 emit => '. fxch %X1',
1998 comment => "x87 stack push",
2000 cmp_attr => "return 1;",
2001 emit => '. fld %X1',
2006 comment => "x87 stack push",
2007 reg_req => { in => [ "vfp"], out => [ "vfp" ] },
2008 cmp_attr => "return 1;",
2009 emit => '. fld %X1',
2014 comment => "x87 stack pop",
2016 cmp_attr => "return 1;",
2017 emit => '. fstp %X1',
2023 op_flags => "L|X|Y",
2024 comment => "floating point compare",
2029 op_flags => "L|X|Y",
2030 comment => "floating point compare and pop",
2035 op_flags => "L|X|Y",
2036 comment => "floating point compare and pop twice",
2041 op_flags => "L|X|Y",
2042 comment => "floating point compare reverse",
2047 op_flags => "L|X|Y",
2048 comment => "floating point compare reverse and pop",
2053 op_flags => "L|X|Y",
2054 comment => "floating point compare reverse and pop twice",
2059 # -------------------------------------------------------------------------------- #
2060 # ____ ____ _____ _ _ #
2061 # / ___/ ___|| ____| __ _____ ___| |_ ___ _ __ _ __ ___ __| | ___ ___ #
2062 # \___ \___ \| _| \ \ / / _ \/ __| __/ _ \| '__| | '_ \ / _ \ / _` |/ _ \/ __| #
2063 # ___) |__) | |___ \ V / __/ (__| || (_) | | | | | | (_) | (_| | __/\__ \ #
2064 # |____/____/|_____| \_/ \___|\___|\__\___/|_| |_| |_|\___/ \__,_|\___||___/ #
2066 # -------------------------------------------------------------------------------- #
2069 # Spilling and reloading of SSE registers, hardcoded, not generated #
2073 state => "exc_pinned",
2074 comment => "construct SSE Load: Load(ptr, mem) = LD ptr",
2075 reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
2076 emit => '. movdqu %D1, %AM',
2077 outs => [ "res", "M" ],
2083 state => "exc_pinned",
2084 comment => "construct Store: Store(ptr, val, mem) = ST ptr,val",
2085 reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
2086 emit => '. movdqu %binop',
2093 # Include the generated SIMD node specification written by the SIMD optimization
2094 $my_script_name = dirname($myname) . "/../ia32/ia32_simd_spec.pl";
2095 unless ($return = do $my_script_name) {
2096 warn "couldn't parse $my_script_name: $@" if $@;
2097 warn "couldn't do $my_script_name: $!" unless defined $return;
2098 warn "couldn't run $my_script_name" unless $return;